1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 #include "target-descriptions.h"
60 #include "dwarf2-frame.h"
61 #include "user-regs.h"
63 static const struct objfile_data
*mips_pdr_data
;
65 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
67 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
68 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
69 #define ST0_FR (1 << 26)
71 /* The sizes of floating point registers. */
75 MIPS_FPU_SINGLE_REGSIZE
= 4,
76 MIPS_FPU_DOUBLE_REGSIZE
= 8
85 static const char *mips_abi_string
;
87 static const char *mips_abi_strings
[] = {
98 /* The standard register names, and all the valid aliases for them. */
105 /* Aliases for o32 and most other ABIs. */
106 const struct register_alias mips_o32_aliases
[] = {
113 /* Aliases for n32 and n64. */
114 const struct register_alias mips_n32_n64_aliases
[] = {
121 /* Aliases for ABI-independent registers. */
122 const struct register_alias mips_register_aliases
[] = {
123 /* The architecture manuals specify these ABI-independent names for
125 #define R(n) { "r" #n, n }
126 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
127 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
128 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
129 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
132 /* k0 and k1 are sometimes called these instead (for "kernel
137 /* This is the traditional GDB name for the CP0 status register. */
138 { "sr", MIPS_PS_REGNUM
},
140 /* This is the traditional GDB name for the CP0 BadVAddr register. */
141 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
143 /* This is the traditional GDB name for the FCSR. */
144 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
147 /* Some MIPS boards don't support floating point while others only
148 support single-precision floating-point operations. */
152 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
153 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
154 MIPS_FPU_NONE
/* No floating point. */
157 #ifndef MIPS_DEFAULT_FPU_TYPE
158 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
160 static int mips_fpu_type_auto
= 1;
161 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
163 static int mips_debug
= 0;
165 /* Properties (for struct target_desc) describing the g/G packet
167 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
168 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
170 /* MIPS specific per-architecture information */
173 /* from the elf header */
177 enum mips_abi mips_abi
;
178 enum mips_abi found_abi
;
179 enum mips_fpu_type mips_fpu_type
;
180 int mips_last_arg_regnum
;
181 int mips_last_fp_arg_regnum
;
182 int default_mask_address_p
;
183 /* Is the target using 64-bit raw integer registers but only
184 storing a left-aligned 32-bit value in each? */
185 int mips64_transfers_32bit_regs_p
;
186 /* Indexes for various registers. IRIX and embedded have
187 different values. This contains the "public" fields. Don't
188 add any that do not need to be public. */
189 const struct mips_regnum
*regnum
;
190 /* Register names table for the current register set. */
191 const char **mips_processor_reg_names
;
193 /* The size of register data available from the target, if known.
194 This doesn't quite obsolete the manual
195 mips64_transfers_32bit_regs_p, since that is documented to force
196 left alignment even for big endian (very strange). */
197 int register_size_valid_p
;
202 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
208 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
209 They are implemented as a pair of 64bit doubles where the high
210 part holds the result of the operation rounded to double, and
211 the low double holds the difference between the exact result and
212 the rounded result. So "high" + "low" contains the result with
213 added precision. Unfortunately, the floatformat structure used
214 by GDB is not powerful enough to describe this format. As a temporary
215 measure, we define a 128bit floatformat that only uses the high part.
216 We lose a bit of precision but that's probably the best we can do
217 for now with the current infrastructure. */
219 static const struct floatformat floatformat_n32n64_long_double_big
=
221 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
222 floatformat_intbit_no
,
223 "floatformat_n32n64_long_double_big",
224 n32n64_floatformat_always_valid
227 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
229 &floatformat_n32n64_long_double_big
,
230 &floatformat_n32n64_long_double_big
233 const struct mips_regnum
*
234 mips_regnum (struct gdbarch
*gdbarch
)
236 return gdbarch_tdep (gdbarch
)->regnum
;
240 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
242 return mips_regnum (gdbarch
)->fp0
+ 12;
245 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
246 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
248 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
250 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
252 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
254 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
255 functions to test, set, or clear bit 0 of addresses. */
258 is_mips16_addr (CORE_ADDR addr
)
264 unmake_mips16_addr (CORE_ADDR addr
)
266 return ((addr
) & ~(CORE_ADDR
) 1);
269 /* Return the MIPS ABI associated with GDBARCH. */
271 mips_abi (struct gdbarch
*gdbarch
)
273 return gdbarch_tdep (gdbarch
)->mips_abi
;
277 mips_isa_regsize (struct gdbarch
*gdbarch
)
279 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
281 /* If we know how big the registers are, use that size. */
282 if (tdep
->register_size_valid_p
)
283 return tdep
->register_size
;
285 /* Fall back to the previous behavior. */
286 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
287 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
290 /* Return the currently configured (or set) saved register size. */
293 mips_abi_regsize (struct gdbarch
*gdbarch
)
295 switch (mips_abi (gdbarch
))
297 case MIPS_ABI_EABI32
:
303 case MIPS_ABI_EABI64
:
305 case MIPS_ABI_UNKNOWN
:
308 internal_error (__FILE__
, __LINE__
, _("bad switch"));
312 /* Functions for setting and testing a bit in a minimal symbol that
313 marks it as 16-bit function. The MSB of the minimal symbol's
314 "info" field is used for this purpose.
316 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
317 i.e. refers to a 16-bit function, and sets a "special" bit in a
318 minimal symbol to mark it as a 16-bit function
320 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
323 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
325 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
327 MSYMBOL_INFO (msym
) = (char *)
328 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
329 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
334 msymbol_is_special (struct minimal_symbol
*msym
)
336 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
339 /* XFER a value from the big/little/left end of the register.
340 Depending on the size of the value it might occupy the entire
341 register or just part of it. Make an allowance for this, aligning
342 things accordingly. */
345 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
346 enum bfd_endian endian
, gdb_byte
*in
,
347 const gdb_byte
*out
, int buf_offset
)
350 gdb_assert (reg_num
>= gdbarch_num_regs (current_gdbarch
));
351 /* Need to transfer the left or right part of the register, based on
352 the targets byte order. */
356 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
358 case BFD_ENDIAN_LITTLE
:
361 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
365 internal_error (__FILE__
, __LINE__
, _("bad switch"));
368 fprintf_unfiltered (gdb_stderr
,
369 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
370 reg_num
, reg_offset
, buf_offset
, length
);
371 if (mips_debug
&& out
!= NULL
)
374 fprintf_unfiltered (gdb_stdlog
, "out ");
375 for (i
= 0; i
< length
; i
++)
376 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
379 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
382 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
384 if (mips_debug
&& in
!= NULL
)
387 fprintf_unfiltered (gdb_stdlog
, "in ");
388 for (i
= 0; i
< length
; i
++)
389 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
392 fprintf_unfiltered (gdb_stdlog
, "\n");
395 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
396 compatiblity mode. A return value of 1 means that we have
397 physical 64-bit registers, but should treat them as 32-bit registers. */
400 mips2_fp_compat (struct frame_info
*frame
)
402 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
404 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
409 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
410 in all the places we deal with FP registers. PR gdb/413. */
411 /* Otherwise check the FR bit in the status register - it controls
412 the FP compatiblity mode. If it is clear we are in compatibility
414 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
421 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
423 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
425 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
427 static struct type
*mips_float_register_type (void);
428 static struct type
*mips_double_register_type (void);
430 /* The list of available "set mips " and "show mips " commands */
432 static struct cmd_list_element
*setmipscmdlist
= NULL
;
433 static struct cmd_list_element
*showmipscmdlist
= NULL
;
435 /* Integer registers 0 thru 31 are handled explicitly by
436 mips_register_name(). Processor specific registers 32 and above
437 are listed in the following tables. */
440 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
444 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
445 "sr", "lo", "hi", "bad", "cause", "pc",
446 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
447 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
448 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
449 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
450 "fsr", "fir", "" /*"fp" */ , "",
451 "", "", "", "", "", "", "", "",
452 "", "", "", "", "", "", "", "",
455 /* Names of IDT R3041 registers. */
457 static const char *mips_r3041_reg_names
[] = {
458 "sr", "lo", "hi", "bad", "cause", "pc",
459 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
460 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
461 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
462 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
463 "fsr", "fir", "", /*"fp" */ "",
464 "", "", "bus", "ccfg", "", "", "", "",
465 "", "", "port", "cmp", "", "", "epc", "prid",
468 /* Names of tx39 registers. */
470 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
471 "sr", "lo", "hi", "bad", "cause", "pc",
472 "", "", "", "", "", "", "", "",
473 "", "", "", "", "", "", "", "",
474 "", "", "", "", "", "", "", "",
475 "", "", "", "", "", "", "", "",
477 "", "", "", "", "", "", "", "",
478 "", "", "config", "cache", "debug", "depc", "epc", ""
481 /* Names of IRIX registers. */
482 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
483 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
484 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
485 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
486 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
487 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
491 /* Return the name of the register corresponding to REGNO. */
493 mips_register_name (int regno
)
495 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
496 /* GPR names for all ABIs other than n32/n64. */
497 static char *mips_gpr_names
[] = {
498 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
499 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
500 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
501 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
504 /* GPR names for n32 and n64 ABIs. */
505 static char *mips_n32_n64_gpr_names
[] = {
506 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
507 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
508 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
509 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
512 enum mips_abi abi
= mips_abi (current_gdbarch
);
514 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
515 but then don't make the raw register names visible. */
516 int rawnum
= regno
% gdbarch_num_regs (current_gdbarch
);
517 if (regno
< gdbarch_num_regs (current_gdbarch
))
520 /* The MIPS integer registers are always mapped from 0 to 31. The
521 names of the registers (which reflects the conventions regarding
522 register use) vary depending on the ABI. */
523 if (0 <= rawnum
&& rawnum
< 32)
525 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
526 return mips_n32_n64_gpr_names
[rawnum
];
528 return mips_gpr_names
[rawnum
];
530 else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch
)))
531 return tdesc_register_name (rawnum
);
532 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (current_gdbarch
))
534 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
535 return tdep
->mips_processor_reg_names
[rawnum
- 32];
538 internal_error (__FILE__
, __LINE__
,
539 _("mips_register_name: bad register number %d"), rawnum
);
542 /* Return the groups that a MIPS register can be categorised into. */
545 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
546 struct reggroup
*reggroup
)
551 int rawnum
= regnum
% gdbarch_num_regs (current_gdbarch
);
552 int pseudo
= regnum
/ gdbarch_num_regs (current_gdbarch
);
553 if (reggroup
== all_reggroup
)
555 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
556 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
557 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
558 (gdbarch), as not all architectures are multi-arch. */
559 raw_p
= rawnum
< gdbarch_num_regs (current_gdbarch
);
560 if (gdbarch_register_name (current_gdbarch
, regnum
) == NULL
561 || gdbarch_register_name (current_gdbarch
, regnum
)[0] == '\0')
563 if (reggroup
== float_reggroup
)
564 return float_p
&& pseudo
;
565 if (reggroup
== vector_reggroup
)
566 return vector_p
&& pseudo
;
567 if (reggroup
== general_reggroup
)
568 return (!vector_p
&& !float_p
) && pseudo
;
569 /* Save the pseudo registers. Need to make certain that any code
570 extracting register values from a saved register cache also uses
572 if (reggroup
== save_reggroup
)
573 return raw_p
&& pseudo
;
574 /* Restore the same pseudo register. */
575 if (reggroup
== restore_reggroup
)
576 return raw_p
&& pseudo
;
580 /* Return the groups that a MIPS register can be categorised into.
581 This version is only used if we have a target description which
582 describes real registers (and their groups). */
585 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
586 struct reggroup
*reggroup
)
588 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
589 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
592 /* Only save, restore, and display the pseudo registers. Need to
593 make certain that any code extracting register values from a
594 saved register cache also uses pseudo registers.
596 Note: saving and restoring the pseudo registers is slightly
597 strange; if we have 64 bits, we should save and restore all
598 64 bits. But this is hard and has little benefit. */
602 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
606 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
609 /* Map the symbol table registers which live in the range [1 *
610 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
611 registers. Take care of alignment and size problems. */
614 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
615 int cookednum
, gdb_byte
*buf
)
617 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
618 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
619 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
620 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
621 regcache_raw_read (regcache
, rawnum
, buf
);
622 else if (register_size (gdbarch
, rawnum
) >
623 register_size (gdbarch
, cookednum
))
625 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
626 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
627 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
629 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
632 internal_error (__FILE__
, __LINE__
, _("bad register size"));
636 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
637 struct regcache
*regcache
, int cookednum
,
640 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
641 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
642 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
643 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
644 regcache_raw_write (regcache
, rawnum
, buf
);
645 else if (register_size (gdbarch
, rawnum
) >
646 register_size (gdbarch
, cookednum
))
648 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
649 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
650 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
652 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
655 internal_error (__FILE__
, __LINE__
, _("bad register size"));
658 /* Table to translate MIPS16 register field to actual register number. */
659 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
661 /* Heuristic_proc_start may hunt through the text section for a long
662 time across a 2400 baud serial line. Allows the user to limit this
665 static unsigned int heuristic_fence_post
= 0;
667 /* Number of bytes of storage in the actual machine representation for
668 register N. NOTE: This defines the pseudo register type so need to
669 rebuild the architecture vector. */
671 static int mips64_transfers_32bit_regs_p
= 0;
674 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
675 struct cmd_list_element
*c
)
677 struct gdbarch_info info
;
678 gdbarch_info_init (&info
);
679 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
680 instead of relying on globals. Doing that would let generic code
681 handle the search for this specific architecture. */
682 if (!gdbarch_update_p (info
))
684 mips64_transfers_32bit_regs_p
= 0;
685 error (_("32-bit compatibility mode not supported"));
689 /* Convert to/from a register and the corresponding memory value. */
692 mips_convert_register_p (int regnum
, struct type
*type
)
694 return (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
695 && register_size (current_gdbarch
, regnum
) == 4
696 && (regnum
% gdbarch_num_regs (current_gdbarch
))
697 >= mips_regnum (current_gdbarch
)->fp0
698 && (regnum
% gdbarch_num_regs (current_gdbarch
))
699 < mips_regnum (current_gdbarch
)->fp0
+ 32
700 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
704 mips_register_to_value (struct frame_info
*frame
, int regnum
,
705 struct type
*type
, gdb_byte
*to
)
707 get_frame_register (frame
, regnum
+ 0, to
+ 4);
708 get_frame_register (frame
, regnum
+ 1, to
+ 0);
712 mips_value_to_register (struct frame_info
*frame
, int regnum
,
713 struct type
*type
, const gdb_byte
*from
)
715 put_frame_register (frame
, regnum
+ 0, from
+ 4);
716 put_frame_register (frame
, regnum
+ 1, from
+ 0);
719 /* Return the GDB type object for the "standard" data type of data in
723 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
725 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (current_gdbarch
));
726 if ((regnum
% gdbarch_num_regs (current_gdbarch
))
727 >= mips_regnum (current_gdbarch
)->fp0
728 && (regnum
% gdbarch_num_regs (current_gdbarch
))
729 < mips_regnum (current_gdbarch
)->fp0
+ 32)
731 /* The floating-point registers raw, or cooked, always match
732 mips_isa_regsize(), and also map 1:1, byte for byte. */
733 if (mips_isa_regsize (gdbarch
) == 4)
734 return builtin_type_ieee_single
;
736 return builtin_type_ieee_double
;
738 else if (regnum
< gdbarch_num_regs (current_gdbarch
))
740 /* The raw or ISA registers. These are all sized according to
742 if (mips_isa_regsize (gdbarch
) == 4)
743 return builtin_type_int32
;
745 return builtin_type_int64
;
749 /* The cooked or ABI registers. These are sized according to
750 the ABI (with a few complications). */
751 if (regnum
>= (gdbarch_num_regs (current_gdbarch
)
752 + mips_regnum (current_gdbarch
)->fp_control_status
)
753 && regnum
<= gdbarch_num_regs (current_gdbarch
)
754 + MIPS_LAST_EMBED_REGNUM
)
755 /* The pseudo/cooked view of the embedded registers is always
756 32-bit. The raw view is handled below. */
757 return builtin_type_int32
;
758 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
759 /* The target, while possibly using a 64-bit register buffer,
760 is only transfering 32-bits of each integer register.
761 Reflect this in the cooked/pseudo (ABI) register value. */
762 return builtin_type_int32
;
763 else if (mips_abi_regsize (gdbarch
) == 4)
764 /* The ABI is restricted to 32-bit registers (the ISA could be
766 return builtin_type_int32
;
769 return builtin_type_int64
;
773 /* Return the GDB type for the pseudo register REGNUM, which is the
774 ABI-level view. This function is only called if there is a target
775 description which includes registers, so we know precisely the
776 types of hardware registers. */
779 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
781 const int num_regs
= gdbarch_num_regs (gdbarch
);
782 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
783 int rawnum
= regnum
% num_regs
;
784 struct type
*rawtype
;
786 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
788 /* Absent registers are still absent. */
789 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
790 if (TYPE_LENGTH (rawtype
) == 0)
793 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
794 /* Present the floating point registers however the hardware did;
795 do not try to convert between FPU layouts. */
798 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
800 /* The pseudo/cooked view of embedded registers is always
801 32-bit, even if the target transfers 64-bit values for them.
802 New targets relying on XML descriptions should only transfer
803 the necessary 32 bits, but older versions of GDB expected 64,
804 so allow the target to provide 64 bits without interfering
805 with the displayed type. */
806 return builtin_type_int32
;
809 /* Use pointer types for registers if we can. For n32 we can not,
810 since we do not have a 64-bit pointer type. */
811 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
813 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
814 return builtin_type_void_data_ptr
;
815 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
816 return builtin_type_void_func_ptr
;
819 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
820 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
821 return builtin_type_int32
;
823 /* For all other registers, pass through the hardware type. */
827 /* Should the upper word of 64-bit addresses be zeroed? */
828 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
831 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
833 switch (mask_address_var
)
835 case AUTO_BOOLEAN_TRUE
:
837 case AUTO_BOOLEAN_FALSE
:
840 case AUTO_BOOLEAN_AUTO
:
841 return tdep
->default_mask_address_p
;
843 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
849 show_mask_address (struct ui_file
*file
, int from_tty
,
850 struct cmd_list_element
*c
, const char *value
)
852 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
854 deprecated_show_value_hack (file
, from_tty
, c
, value
);
855 switch (mask_address_var
)
857 case AUTO_BOOLEAN_TRUE
:
858 printf_filtered ("The 32 bit mips address mask is enabled\n");
860 case AUTO_BOOLEAN_FALSE
:
861 printf_filtered ("The 32 bit mips address mask is disabled\n");
863 case AUTO_BOOLEAN_AUTO
:
865 ("The 32 bit address mask is set automatically. Currently %s\n",
866 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
869 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
874 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
877 mips_pc_is_mips16 (CORE_ADDR memaddr
)
879 struct minimal_symbol
*sym
;
881 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
882 if (is_mips16_addr (memaddr
))
885 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
886 the high bit of the info field. Use this to decide if the function is
887 MIPS16 or normal MIPS. */
888 sym
= lookup_minimal_symbol_by_pc (memaddr
);
890 return msymbol_is_special (sym
);
895 /* MIPS believes that the PC has a sign extended value. Perhaps the
896 all registers should be sign extended for simplicity? */
899 mips_read_pc (struct regcache
*regcache
)
902 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
903 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
908 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
910 return frame_unwind_register_signed (next_frame
,
911 gdbarch_num_regs (current_gdbarch
)
912 + mips_regnum (gdbarch
)->pc
);
916 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
918 return frame_unwind_register_signed (next_frame
,
919 gdbarch_num_regs (current_gdbarch
)
923 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
924 dummy frame. The frame ID's base needs to match the TOS value
925 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
928 static struct frame_id
929 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
931 return frame_id_build
932 (frame_unwind_register_signed (next_frame
,
933 gdbarch_num_regs (current_gdbarch
)
935 frame_pc_unwind (next_frame
));
939 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
941 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
942 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
945 /* Fetch and return instruction from the specified location. If the PC
946 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
949 mips_fetch_instruction (CORE_ADDR addr
)
951 gdb_byte buf
[MIPS_INSN32_SIZE
];
955 if (mips_pc_is_mips16 (addr
))
957 instlen
= MIPS_INSN16_SIZE
;
958 addr
= unmake_mips16_addr (addr
);
961 instlen
= MIPS_INSN32_SIZE
;
962 status
= read_memory_nobpt (addr
, buf
, instlen
);
964 memory_error (status
, addr
);
965 return extract_unsigned_integer (buf
, instlen
);
968 /* These the fields of 32 bit mips instructions */
969 #define mips32_op(x) (x >> 26)
970 #define itype_op(x) (x >> 26)
971 #define itype_rs(x) ((x >> 21) & 0x1f)
972 #define itype_rt(x) ((x >> 16) & 0x1f)
973 #define itype_immediate(x) (x & 0xffff)
975 #define jtype_op(x) (x >> 26)
976 #define jtype_target(x) (x & 0x03ffffff)
978 #define rtype_op(x) (x >> 26)
979 #define rtype_rs(x) ((x >> 21) & 0x1f)
980 #define rtype_rt(x) ((x >> 16) & 0x1f)
981 #define rtype_rd(x) ((x >> 11) & 0x1f)
982 #define rtype_shamt(x) ((x >> 6) & 0x1f)
983 #define rtype_funct(x) (x & 0x3f)
986 mips32_relative_offset (ULONGEST inst
)
988 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
991 /* Determine where to set a single step breakpoint while considering
992 branch prediction. */
994 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
998 inst
= mips_fetch_instruction (pc
);
999 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1001 if (itype_op (inst
) >> 2 == 5)
1002 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1004 op
= (itype_op (inst
) & 0x03);
1014 goto greater_branch
;
1019 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1020 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1022 int tf
= itype_rt (inst
) & 0x01;
1023 int cnum
= itype_rt (inst
) >> 2;
1025 get_frame_register_signed (frame
, mips_regnum (current_gdbarch
)->
1027 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1029 if (((cond
>> cnum
) & 0x01) == tf
)
1030 pc
+= mips32_relative_offset (inst
) + 4;
1035 pc
+= 4; /* Not a branch, next instruction is easy */
1038 { /* This gets way messy */
1040 /* Further subdivide into SPECIAL, REGIMM and other */
1041 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1043 case 0: /* SPECIAL */
1044 op
= rtype_funct (inst
);
1049 /* Set PC to that address */
1050 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1056 break; /* end SPECIAL */
1057 case 1: /* REGIMM */
1059 op
= itype_rt (inst
); /* branch condition */
1064 case 16: /* BLTZAL */
1065 case 18: /* BLTZALL */
1067 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1068 pc
+= mips32_relative_offset (inst
) + 4;
1070 pc
+= 8; /* after the delay slot */
1074 case 17: /* BGEZAL */
1075 case 19: /* BGEZALL */
1076 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1077 pc
+= mips32_relative_offset (inst
) + 4;
1079 pc
+= 8; /* after the delay slot */
1081 /* All of the other instructions in the REGIMM category */
1086 break; /* end REGIMM */
1091 reg
= jtype_target (inst
) << 2;
1092 /* Upper four bits get never changed... */
1093 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1096 /* FIXME case JALX : */
1099 reg
= jtype_target (inst
) << 2;
1100 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1101 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1103 break; /* The new PC will be alternate mode */
1104 case 4: /* BEQ, BEQL */
1106 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1107 get_frame_register_signed (frame
, itype_rt (inst
)))
1108 pc
+= mips32_relative_offset (inst
) + 4;
1112 case 5: /* BNE, BNEL */
1114 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1115 get_frame_register_signed (frame
, itype_rt (inst
)))
1116 pc
+= mips32_relative_offset (inst
) + 4;
1120 case 6: /* BLEZ, BLEZL */
1121 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1122 pc
+= mips32_relative_offset (inst
) + 4;
1128 greater_branch
: /* BGTZ, BGTZL */
1129 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1130 pc
+= mips32_relative_offset (inst
) + 4;
1137 } /* mips32_next_pc */
1139 /* Decoding the next place to set a breakpoint is irregular for the
1140 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1141 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1142 We dont want to set a single step instruction on the extend instruction
1146 /* Lots of mips16 instruction formats */
1147 /* Predicting jumps requires itype,ritype,i8type
1148 and their extensions extItype,extritype,extI8type
1150 enum mips16_inst_fmts
1152 itype
, /* 0 immediate 5,10 */
1153 ritype
, /* 1 5,3,8 */
1154 rrtype
, /* 2 5,3,3,5 */
1155 rritype
, /* 3 5,3,3,5 */
1156 rrrtype
, /* 4 5,3,3,3,2 */
1157 rriatype
, /* 5 5,3,3,1,4 */
1158 shifttype
, /* 6 5,3,3,3,2 */
1159 i8type
, /* 7 5,3,8 */
1160 i8movtype
, /* 8 5,3,3,5 */
1161 i8mov32rtype
, /* 9 5,3,5,3 */
1162 i64type
, /* 10 5,3,8 */
1163 ri64type
, /* 11 5,3,3,5 */
1164 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1165 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1166 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1167 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1168 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1169 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1170 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1171 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1172 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1173 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1175 /* I am heaping all the fields of the formats into one structure and
1176 then, only the fields which are involved in instruction extension */
1180 unsigned int regx
; /* Function in i8 type */
1185 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1186 for the bits which make up the immediatate extension. */
1189 extended_offset (unsigned int extension
)
1192 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1194 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1196 value
|= extension
& 0x01f; /* extract 4:0 */
1200 /* Only call this function if you know that this is an extendable
1201 instruction. It won't malfunction, but why make excess remote memory
1202 references? If the immediate operands get sign extended or something,
1203 do it after the extension is performed. */
1204 /* FIXME: Every one of these cases needs to worry about sign extension
1205 when the offset is to be used in relative addressing. */
1208 fetch_mips_16 (CORE_ADDR pc
)
1211 pc
&= 0xfffffffe; /* clear the low order bit */
1212 target_read_memory (pc
, buf
, 2);
1213 return extract_unsigned_integer (buf
, 2);
1217 unpack_mips16 (CORE_ADDR pc
,
1218 unsigned int extension
,
1220 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1225 switch (insn_format
)
1232 value
= extended_offset (extension
);
1233 value
= value
<< 11; /* rom for the original value */
1234 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1238 value
= inst
& 0x7ff;
1239 /* FIXME : Consider sign extension */
1248 { /* A register identifier and an offset */
1249 /* Most of the fields are the same as I type but the
1250 immediate value is of a different length */
1254 value
= extended_offset (extension
);
1255 value
= value
<< 8; /* from the original instruction */
1256 value
|= inst
& 0xff; /* eleven bits from instruction */
1257 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1258 if (value
& 0x4000) /* test the sign bit , bit 26 */
1260 value
&= ~0x3fff; /* remove the sign bit */
1266 value
= inst
& 0xff; /* 8 bits */
1267 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1268 /* FIXME: Do sign extension , this format needs it */
1269 if (value
& 0x80) /* THIS CONFUSES ME */
1271 value
&= 0xef; /* remove the sign bit */
1281 unsigned long value
;
1282 unsigned int nexthalf
;
1283 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1284 value
= value
<< 16;
1285 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1293 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1295 upk
->offset
= offset
;
1302 add_offset_16 (CORE_ADDR pc
, int offset
)
1304 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1308 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1309 unsigned int extension
, unsigned int insn
)
1311 int op
= (insn
>> 11);
1314 case 2: /* Branch */
1317 struct upk_mips16 upk
;
1318 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1319 offset
= upk
.offset
;
1325 pc
+= (offset
<< 1) + 2;
1328 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1330 struct upk_mips16 upk
;
1331 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1332 pc
= add_offset_16 (pc
, upk
.offset
);
1333 if ((insn
>> 10) & 0x01) /* Exchange mode */
1334 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1341 struct upk_mips16 upk
;
1343 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1344 reg
= get_frame_register_signed (frame
, upk
.regx
);
1346 pc
+= (upk
.offset
<< 1) + 2;
1353 struct upk_mips16 upk
;
1355 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1356 reg
= get_frame_register_signed (frame
, upk
.regx
);
1358 pc
+= (upk
.offset
<< 1) + 2;
1363 case 12: /* I8 Formats btez btnez */
1365 struct upk_mips16 upk
;
1367 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1368 /* upk.regx contains the opcode */
1369 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1370 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1371 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1372 /* pc = add_offset_16(pc,upk.offset) ; */
1373 pc
+= (upk
.offset
<< 1) + 2;
1378 case 29: /* RR Formats JR, JALR, JALR-RA */
1380 struct upk_mips16 upk
;
1381 /* upk.fmt = rrtype; */
1386 upk
.regx
= (insn
>> 8) & 0x07;
1387 upk
.regy
= (insn
>> 5) & 0x07;
1395 break; /* Function return instruction */
1401 break; /* BOGUS Guess */
1403 pc
= get_frame_register_signed (frame
, reg
);
1410 /* This is an instruction extension. Fetch the real instruction
1411 (which follows the extension) and decode things based on
1415 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1428 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1430 unsigned int insn
= fetch_mips_16 (pc
);
1431 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1434 /* The mips_next_pc function supports single_step when the remote
1435 target monitor or stub is not developed enough to do a single_step.
1436 It works by decoding the current instruction and predicting where a
1437 branch will go. This isnt hard because all the data is available.
1438 The MIPS32 and MIPS16 variants are quite different. */
1440 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1442 if (is_mips16_addr (pc
))
1443 return mips16_next_pc (frame
, pc
);
1445 return mips32_next_pc (frame
, pc
);
1448 struct mips_frame_cache
1451 struct trad_frame_saved_reg
*saved_regs
;
1454 /* Set a register's saved stack address in temp_saved_regs. If an
1455 address has already been set for this register, do nothing; this
1456 way we will only recognize the first save of a given register in a
1459 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1460 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1461 Strictly speaking, only the second range is used as it is only second
1462 range (the ABI instead of ISA registers) that comes into play when finding
1463 saved registers in a frame. */
1466 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1469 if (this_cache
!= NULL
1470 && this_cache
->saved_regs
[regnum
].addr
== -1)
1472 this_cache
->saved_regs
[regnum
1473 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1475 this_cache
->saved_regs
[regnum
1476 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1482 /* Fetch the immediate value from a MIPS16 instruction.
1483 If the previous instruction was an EXTEND, use it to extend
1484 the upper bits of the immediate value. This is a helper function
1485 for mips16_scan_prologue. */
1488 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1489 unsigned short inst
, /* current instruction */
1490 int nbits
, /* number of bits in imm field */
1491 int scale
, /* scale factor to be applied to imm */
1492 int is_signed
) /* is the imm field signed? */
1496 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1498 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1499 if (offset
& 0x8000) /* check for negative extend */
1500 offset
= 0 - (0x10000 - (offset
& 0xffff));
1501 return offset
| (inst
& 0x1f);
1505 int max_imm
= 1 << nbits
;
1506 int mask
= max_imm
- 1;
1507 int sign_bit
= max_imm
>> 1;
1509 offset
= inst
& mask
;
1510 if (is_signed
&& (offset
& sign_bit
))
1511 offset
= 0 - (max_imm
- offset
);
1512 return offset
* scale
;
1517 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1518 the associated FRAME_CACHE if not null.
1519 Return the address of the first instruction past the prologue. */
1522 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1523 struct frame_info
*next_frame
,
1524 struct mips_frame_cache
*this_cache
)
1527 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1529 long frame_offset
= 0; /* Size of stack frame. */
1530 long frame_adjust
= 0; /* Offset of FP from SP. */
1531 int frame_reg
= MIPS_SP_REGNUM
;
1532 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1533 unsigned inst
= 0; /* current instruction */
1534 unsigned entry_inst
= 0; /* the entry instruction */
1537 int extend_bytes
= 0;
1538 int prev_extend_bytes
;
1539 CORE_ADDR end_prologue_addr
= 0;
1541 /* Can be called when there's no process, and hence when there's no
1543 if (next_frame
!= NULL
)
1544 sp
= frame_unwind_register_signed (next_frame
,
1545 gdbarch_num_regs (current_gdbarch
)
1550 if (limit_pc
> start_pc
+ 200)
1551 limit_pc
= start_pc
+ 200;
1553 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1555 /* Save the previous instruction. If it's an EXTEND, we'll extract
1556 the immediate offset extension from it in mips16_get_imm. */
1559 /* Fetch and decode the instruction. */
1560 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1562 /* Normally we ignore extend instructions. However, if it is
1563 not followed by a valid prologue instruction, then this
1564 instruction is not part of the prologue either. We must
1565 remember in this case to adjust the end_prologue_addr back
1567 if ((inst
& 0xf800) == 0xf000) /* extend */
1569 extend_bytes
= MIPS_INSN16_SIZE
;
1573 prev_extend_bytes
= extend_bytes
;
1576 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1577 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1579 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1580 if (offset
< 0) /* negative stack adjustment? */
1581 frame_offset
-= offset
;
1583 /* Exit loop if a positive stack adjustment is found, which
1584 usually means that the stack cleanup code in the function
1585 epilogue is reached. */
1588 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1590 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1591 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1592 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1594 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1596 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1597 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1598 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1600 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1602 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1603 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1605 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1607 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1608 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1610 else if (inst
== 0x673d) /* move $s1, $sp */
1615 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1617 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1618 frame_addr
= sp
+ offset
;
1620 frame_adjust
= offset
;
1622 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1624 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1625 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1626 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1628 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1630 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1631 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1632 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1634 else if ((inst
& 0xf81f) == 0xe809
1635 && (inst
& 0x700) != 0x700) /* entry */
1636 entry_inst
= inst
; /* save for later processing */
1637 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1638 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1639 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1641 /* This instruction is part of the prologue, but we don't
1642 need to do anything special to handle it. */
1646 /* This instruction is not an instruction typically found
1647 in a prologue, so we must have reached the end of the
1649 if (end_prologue_addr
== 0)
1650 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1654 /* The entry instruction is typically the first instruction in a function,
1655 and it stores registers at offsets relative to the value of the old SP
1656 (before the prologue). But the value of the sp parameter to this
1657 function is the new SP (after the prologue has been executed). So we
1658 can't calculate those offsets until we've seen the entire prologue,
1659 and can calculate what the old SP must have been. */
1660 if (entry_inst
!= 0)
1662 int areg_count
= (entry_inst
>> 8) & 7;
1663 int sreg_count
= (entry_inst
>> 6) & 3;
1665 /* The entry instruction always subtracts 32 from the SP. */
1668 /* Now we can calculate what the SP must have been at the
1669 start of the function prologue. */
1672 /* Check if a0-a3 were saved in the caller's argument save area. */
1673 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1675 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1676 offset
+= mips_abi_regsize (current_gdbarch
);
1679 /* Check if the ra register was pushed on the stack. */
1681 if (entry_inst
& 0x20)
1683 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1684 offset
-= mips_abi_regsize (current_gdbarch
);
1687 /* Check if the s0 and s1 registers were pushed on the stack. */
1688 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1690 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1691 offset
-= mips_abi_regsize (current_gdbarch
);
1695 if (this_cache
!= NULL
)
1698 (frame_unwind_register_signed (next_frame
,
1699 gdbarch_num_regs (current_gdbarch
)
1701 + frame_offset
- frame_adjust
);
1702 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1703 be able to get rid of the assignment below, evetually. But it's
1704 still needed for now. */
1705 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1706 + mips_regnum (current_gdbarch
)->pc
]
1707 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1711 /* If we didn't reach the end of the prologue when scanning the function
1712 instructions, then set end_prologue_addr to the address of the
1713 instruction immediately after the last one we scanned. */
1714 if (end_prologue_addr
== 0)
1715 end_prologue_addr
= cur_pc
;
1717 return end_prologue_addr
;
1720 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1721 Procedures that use the 32-bit instruction set are handled by the
1722 mips_insn32 unwinder. */
1724 static struct mips_frame_cache
*
1725 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1727 struct mips_frame_cache
*cache
;
1729 if ((*this_cache
) != NULL
)
1730 return (*this_cache
);
1731 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1732 (*this_cache
) = cache
;
1733 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1735 /* Analyze the function prologue. */
1737 const CORE_ADDR pc
=
1738 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1739 CORE_ADDR start_addr
;
1741 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1742 if (start_addr
== 0)
1743 start_addr
= heuristic_proc_start (pc
);
1744 /* We can't analyze the prologue if we couldn't find the begining
1746 if (start_addr
== 0)
1749 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1752 /* gdbarch_sp_regnum contains the value and not the address. */
1753 trad_frame_set_value (cache
->saved_regs
, gdbarch_num_regs (current_gdbarch
)
1754 + MIPS_SP_REGNUM
, cache
->base
);
1756 return (*this_cache
);
1760 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1761 struct frame_id
*this_id
)
1763 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1765 (*this_id
) = frame_id_build (info
->base
,
1766 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1770 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1772 int regnum
, int *optimizedp
,
1773 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1774 int *realnump
, gdb_byte
*valuep
)
1776 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1778 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1779 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1782 static const struct frame_unwind mips_insn16_frame_unwind
=
1785 mips_insn16_frame_this_id
,
1786 mips_insn16_frame_prev_register
1789 static const struct frame_unwind
*
1790 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1792 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1793 if (mips_pc_is_mips16 (pc
))
1794 return &mips_insn16_frame_unwind
;
1799 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1802 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1807 static const struct frame_base mips_insn16_frame_base
=
1809 &mips_insn16_frame_unwind
,
1810 mips_insn16_frame_base_address
,
1811 mips_insn16_frame_base_address
,
1812 mips_insn16_frame_base_address
1815 static const struct frame_base
*
1816 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1818 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1819 return &mips_insn16_frame_base
;
1824 /* Mark all the registers as unset in the saved_regs array
1825 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1828 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1830 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1834 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1837 for (i
= 0; i
< num_regs
; i
++)
1839 this_cache
->saved_regs
[i
].addr
= -1;
1844 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1845 the associated FRAME_CACHE if not null.
1846 Return the address of the first instruction past the prologue. */
1849 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1850 struct frame_info
*next_frame
,
1851 struct mips_frame_cache
*this_cache
)
1854 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1857 int frame_reg
= MIPS_SP_REGNUM
;
1859 CORE_ADDR end_prologue_addr
= 0;
1860 int seen_sp_adjust
= 0;
1861 int load_immediate_bytes
= 0;
1863 /* Can be called when there's no process, and hence when there's no
1865 if (next_frame
!= NULL
)
1866 sp
= frame_unwind_register_signed (next_frame
,
1867 gdbarch_num_regs (current_gdbarch
)
1872 if (limit_pc
> start_pc
+ 200)
1873 limit_pc
= start_pc
+ 200;
1878 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1880 unsigned long inst
, high_word
, low_word
;
1883 /* Fetch the instruction. */
1884 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1886 /* Save some code by pre-extracting some useful fields. */
1887 high_word
= (inst
>> 16) & 0xffff;
1888 low_word
= inst
& 0xffff;
1889 reg
= high_word
& 0x1f;
1891 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1892 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1893 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1895 if (low_word
& 0x8000) /* negative stack adjustment? */
1896 frame_offset
+= 0x10000 - low_word
;
1898 /* Exit loop if a positive stack adjustment is found, which
1899 usually means that the stack cleanup code in the function
1900 epilogue is reached. */
1904 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1906 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1908 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1910 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1911 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1913 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1915 /* Old gcc frame, r30 is virtual frame pointer. */
1916 if ((long) low_word
!= frame_offset
)
1917 frame_addr
= sp
+ low_word
;
1918 else if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1920 unsigned alloca_adjust
;
1923 frame_addr
= frame_unwind_register_signed
1925 gdbarch_num_regs (current_gdbarch
) + 30);
1927 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1928 if (alloca_adjust
> 0)
1930 /* FP > SP + frame_size. This may be because of
1931 an alloca or somethings similar. Fix sp to
1932 "pre-alloca" value, and try again. */
1933 sp
+= alloca_adjust
;
1934 /* Need to reset the status of all registers. Otherwise,
1935 we will hit a guard that prevents the new address
1936 for each register to be recomputed during the second
1938 reset_saved_regs (this_cache
);
1943 /* move $30,$sp. With different versions of gas this will be either
1944 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1945 Accept any one of these. */
1946 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1948 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1949 if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1951 unsigned alloca_adjust
;
1954 frame_addr
= frame_unwind_register_signed
1956 gdbarch_num_regs (current_gdbarch
) + 30);
1958 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1959 if (alloca_adjust
> 0)
1961 /* FP > SP + frame_size. This may be because of
1962 an alloca or somethings similar. Fix sp to
1963 "pre-alloca" value, and try again. */
1965 /* Need to reset the status of all registers. Otherwise,
1966 we will hit a guard that prevents the new address
1967 for each register to be recomputed during the second
1969 reset_saved_regs (this_cache
);
1974 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1976 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1978 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1979 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1980 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1981 || high_word
== 0x3c1c /* lui $gp,n */
1982 || high_word
== 0x279c /* addiu $gp,$gp,n */
1983 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1984 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1987 /* These instructions are part of the prologue, but we don't
1988 need to do anything special to handle them. */
1990 /* The instructions below load $at or $t0 with an immediate
1991 value in preparation for a stack adjustment via
1992 subu $sp,$sp,[$at,$t0]. These instructions could also
1993 initialize a local variable, so we accept them only before
1994 a stack adjustment instruction was seen. */
1995 else if (!seen_sp_adjust
1996 && (high_word
== 0x3c01 /* lui $at,n */
1997 || high_word
== 0x3c08 /* lui $t0,n */
1998 || high_word
== 0x3421 /* ori $at,$at,n */
1999 || high_word
== 0x3508 /* ori $t0,$t0,n */
2000 || high_word
== 0x3401 /* ori $at,$zero,n */
2001 || high_word
== 0x3408 /* ori $t0,$zero,n */
2004 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2008 /* This instruction is not an instruction typically found
2009 in a prologue, so we must have reached the end of the
2011 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2012 loop now? Why would we need to continue scanning the function
2014 if (end_prologue_addr
== 0)
2015 end_prologue_addr
= cur_pc
;
2019 if (this_cache
!= NULL
)
2022 (frame_unwind_register_signed (next_frame
,
2023 gdbarch_num_regs (current_gdbarch
)
2026 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2027 this assignment below, eventually. But it's still needed
2029 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
2030 + mips_regnum (current_gdbarch
)->pc
]
2031 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
2035 /* If we didn't reach the end of the prologue when scanning the function
2036 instructions, then set end_prologue_addr to the address of the
2037 instruction immediately after the last one we scanned. */
2038 /* brobecker/2004-10-10: I don't think this would ever happen, but
2039 we may as well be careful and do our best if we have a null
2040 end_prologue_addr. */
2041 if (end_prologue_addr
== 0)
2042 end_prologue_addr
= cur_pc
;
2044 /* In a frameless function, we might have incorrectly
2045 skipped some load immediate instructions. Undo the skipping
2046 if the load immediate was not followed by a stack adjustment. */
2047 if (load_immediate_bytes
&& !seen_sp_adjust
)
2048 end_prologue_addr
-= load_immediate_bytes
;
2050 return end_prologue_addr
;
2053 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2054 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2055 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2058 static struct mips_frame_cache
*
2059 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2061 struct mips_frame_cache
*cache
;
2063 if ((*this_cache
) != NULL
)
2064 return (*this_cache
);
2066 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2067 (*this_cache
) = cache
;
2068 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2070 /* Analyze the function prologue. */
2072 const CORE_ADDR pc
=
2073 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2074 CORE_ADDR start_addr
;
2076 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2077 if (start_addr
== 0)
2078 start_addr
= heuristic_proc_start (pc
);
2079 /* We can't analyze the prologue if we couldn't find the begining
2081 if (start_addr
== 0)
2084 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2087 /* gdbarch_sp_regnum contains the value and not the address. */
2088 trad_frame_set_value (cache
->saved_regs
,
2089 gdbarch_num_regs (current_gdbarch
) + MIPS_SP_REGNUM
,
2092 return (*this_cache
);
2096 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2097 struct frame_id
*this_id
)
2099 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2101 (*this_id
) = frame_id_build (info
->base
,
2102 frame_func_unwind (next_frame
, NORMAL_FRAME
));
2106 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2108 int regnum
, int *optimizedp
,
2109 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2110 int *realnump
, gdb_byte
*valuep
)
2112 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2114 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2115 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2118 static const struct frame_unwind mips_insn32_frame_unwind
=
2121 mips_insn32_frame_this_id
,
2122 mips_insn32_frame_prev_register
2125 static const struct frame_unwind
*
2126 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2128 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2129 if (! mips_pc_is_mips16 (pc
))
2130 return &mips_insn32_frame_unwind
;
2135 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2138 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2143 static const struct frame_base mips_insn32_frame_base
=
2145 &mips_insn32_frame_unwind
,
2146 mips_insn32_frame_base_address
,
2147 mips_insn32_frame_base_address
,
2148 mips_insn32_frame_base_address
2151 static const struct frame_base
*
2152 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2154 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2155 return &mips_insn32_frame_base
;
2160 static struct trad_frame_cache
*
2161 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2164 CORE_ADDR start_addr
;
2165 CORE_ADDR stack_addr
;
2166 struct trad_frame_cache
*this_trad_cache
;
2168 if ((*this_cache
) != NULL
)
2169 return (*this_cache
);
2170 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2171 (*this_cache
) = this_trad_cache
;
2173 /* The return address is in the link register. */
2174 trad_frame_set_reg_realreg (this_trad_cache
,
2175 gdbarch_pc_regnum (current_gdbarch
),
2178 /* Frame ID, since it's a frameless / stackless function, no stack
2179 space is allocated and SP on entry is the current SP. */
2180 pc
= frame_pc_unwind (next_frame
);
2181 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2182 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2183 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2185 /* Assume that the frame's base is the same as the
2187 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2189 return this_trad_cache
;
2193 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2194 struct frame_id
*this_id
)
2196 struct trad_frame_cache
*this_trad_cache
2197 = mips_stub_frame_cache (next_frame
, this_cache
);
2198 trad_frame_get_id (this_trad_cache
, this_id
);
2202 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2204 int regnum
, int *optimizedp
,
2205 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2206 int *realnump
, gdb_byte
*valuep
)
2208 struct trad_frame_cache
*this_trad_cache
2209 = mips_stub_frame_cache (next_frame
, this_cache
);
2210 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2211 lvalp
, addrp
, realnump
, valuep
);
2214 static const struct frame_unwind mips_stub_frame_unwind
=
2217 mips_stub_frame_this_id
,
2218 mips_stub_frame_prev_register
2221 static const struct frame_unwind
*
2222 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2224 struct obj_section
*s
;
2225 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2227 if (in_plt_section (pc
, NULL
))
2228 return &mips_stub_frame_unwind
;
2230 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2231 s
= find_pc_section (pc
);
2234 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2235 ".MIPS.stubs") == 0)
2236 return &mips_stub_frame_unwind
;
2242 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2245 struct trad_frame_cache
*this_trad_cache
2246 = mips_stub_frame_cache (next_frame
, this_cache
);
2247 return trad_frame_get_this_base (this_trad_cache
);
2250 static const struct frame_base mips_stub_frame_base
=
2252 &mips_stub_frame_unwind
,
2253 mips_stub_frame_base_address
,
2254 mips_stub_frame_base_address
,
2255 mips_stub_frame_base_address
2258 static const struct frame_base
*
2259 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2261 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2262 return &mips_stub_frame_base
;
2267 /* mips_addr_bits_remove - remove useless address bits */
2270 mips_addr_bits_remove (CORE_ADDR addr
)
2272 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2273 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2274 /* This hack is a work-around for existing boards using PMON, the
2275 simulator, and any other 64-bit targets that doesn't have true
2276 64-bit addressing. On these targets, the upper 32 bits of
2277 addresses are ignored by the hardware. Thus, the PC or SP are
2278 likely to have been sign extended to all 1s by instruction
2279 sequences that load 32-bit addresses. For example, a typical
2280 piece of code that loads an address is this:
2282 lui $r2, <upper 16 bits>
2283 ori $r2, <lower 16 bits>
2285 But the lui sign-extends the value such that the upper 32 bits
2286 may be all 1s. The workaround is simply to mask off these
2287 bits. In the future, gcc may be changed to support true 64-bit
2288 addressing, and this masking will have to be disabled. */
2289 return addr
&= 0xffffffffUL
;
2294 /* mips_software_single_step() is called just before we want to resume
2295 the inferior, if we want to single-step it but there is no hardware
2296 or kernel single-step support (MIPS on GNU/Linux for example). We find
2297 the target of the coming instruction and breakpoint it. */
2300 mips_software_single_step (struct frame_info
*frame
)
2302 CORE_ADDR pc
, next_pc
;
2304 pc
= get_frame_pc (frame
);
2305 next_pc
= mips_next_pc (frame
, pc
);
2307 insert_single_step_breakpoint (next_pc
);
2311 /* Test whether the PC points to the return instruction at the
2312 end of a function. */
2315 mips_about_to_return (CORE_ADDR pc
)
2317 if (mips_pc_is_mips16 (pc
))
2318 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2319 generates a "jr $ra"; other times it generates code to load
2320 the return address from the stack to an accessible register (such
2321 as $a3), then a "jr" using that register. This second case
2322 is almost impossible to distinguish from an indirect jump
2323 used for switch statements, so we don't even try. */
2324 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2326 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2330 /* This fencepost looks highly suspicious to me. Removing it also
2331 seems suspicious as it could affect remote debugging across serial
2335 heuristic_proc_start (CORE_ADDR pc
)
2342 pc
= gdbarch_addr_bits_remove (current_gdbarch
, pc
);
2344 fence
= start_pc
- heuristic_fence_post
;
2348 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2349 fence
= VM_MIN_ADDRESS
;
2351 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2353 /* search back for previous return */
2354 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2355 if (start_pc
< fence
)
2357 /* It's not clear to me why we reach this point when
2358 stop_soon, but with this test, at least we
2359 don't print out warnings for every child forked (eg, on
2360 decstation). 22apr93 rich@cygnus.com. */
2361 if (stop_soon
== NO_STOP_QUIETLY
)
2363 static int blurb_printed
= 0;
2365 warning (_("GDB can't find the start of the function at 0x%s."),
2370 /* This actually happens frequently in embedded
2371 development, when you first connect to a board
2372 and your stack pointer and pc are nowhere in
2373 particular. This message needs to give people
2374 in that situation enough information to
2375 determine that it's no big deal. */
2376 printf_filtered ("\n\
2377 GDB is unable to find the start of the function at 0x%s\n\
2378 and thus can't determine the size of that function's stack frame.\n\
2379 This means that GDB may be unable to access that stack frame, or\n\
2380 the frames below it.\n\
2381 This problem is most likely caused by an invalid program counter or\n\
2383 However, if you think GDB should simply search farther back\n\
2384 from 0x%s for code which looks like the beginning of a\n\
2385 function, you can increase the range of the search using the `set\n\
2386 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2393 else if (mips_pc_is_mips16 (start_pc
))
2395 unsigned short inst
;
2397 /* On MIPS16, any one of the following is likely to be the
2398 start of a function:
2402 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2403 inst
= mips_fetch_instruction (start_pc
);
2404 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2405 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2406 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2407 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2409 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2410 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2415 else if (mips_about_to_return (start_pc
))
2417 /* Skip return and its delay slot. */
2418 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2425 struct mips_objfile_private
2431 /* According to the current ABI, should the type be passed in a
2432 floating-point register (assuming that there is space)? When there
2433 is no FPU, FP are not even considered as possible candidates for
2434 FP registers and, consequently this returns false - forces FP
2435 arguments into integer registers. */
2438 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2440 return ((typecode
== TYPE_CODE_FLT
2442 && (typecode
== TYPE_CODE_STRUCT
2443 || typecode
== TYPE_CODE_UNION
)
2444 && TYPE_NFIELDS (arg_type
) == 1
2445 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2447 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2450 /* On o32, argument passing in GPRs depends on the alignment of the type being
2451 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2454 mips_type_needs_double_align (struct type
*type
)
2456 enum type_code typecode
= TYPE_CODE (type
);
2458 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2460 else if (typecode
== TYPE_CODE_STRUCT
)
2462 if (TYPE_NFIELDS (type
) < 1)
2464 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2466 else if (typecode
== TYPE_CODE_UNION
)
2470 n
= TYPE_NFIELDS (type
);
2471 for (i
= 0; i
< n
; i
++)
2472 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2479 /* Adjust the address downward (direction of stack growth) so that it
2480 is correctly aligned for a new stack frame. */
2482 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2484 return align_down (addr
, 16);
2488 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2489 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2490 int nargs
, struct value
**args
, CORE_ADDR sp
,
2491 int struct_return
, CORE_ADDR struct_addr
)
2497 int stack_offset
= 0;
2498 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2499 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2500 int regsize
= mips_abi_regsize (gdbarch
);
2502 /* For shared libraries, "t9" needs to point at the function
2504 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2506 /* Set the return address register to point to the entry point of
2507 the program, where a breakpoint lies in wait. */
2508 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2510 /* First ensure that the stack and structure return address (if any)
2511 are properly aligned. The stack has to be at least 64-bit
2512 aligned even on 32-bit machines, because doubles must be 64-bit
2513 aligned. For n32 and n64, stack frames need to be 128-bit
2514 aligned, so we round to this widest known alignment. */
2516 sp
= align_down (sp
, 16);
2517 struct_addr
= align_down (struct_addr
, 16);
2519 /* Now make space on the stack for the args. We allocate more
2520 than necessary for EABI, because the first few arguments are
2521 passed in registers, but that's OK. */
2522 for (argnum
= 0; argnum
< nargs
; argnum
++)
2523 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2524 sp
-= align_up (len
, 16);
2527 fprintf_unfiltered (gdb_stdlog
,
2528 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2529 paddr_nz (sp
), (long) align_up (len
, 16));
2531 /* Initialize the integer and float register pointers. */
2532 argreg
= MIPS_A0_REGNUM
;
2533 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2535 /* The struct_return pointer occupies the first parameter-passing reg. */
2539 fprintf_unfiltered (gdb_stdlog
,
2540 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2541 argreg
, paddr_nz (struct_addr
));
2542 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2545 /* Now load as many as possible of the first arguments into
2546 registers, and push the rest onto the stack. Loop thru args
2547 from first to last. */
2548 for (argnum
= 0; argnum
< nargs
; argnum
++)
2550 const gdb_byte
*val
;
2551 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2552 struct value
*arg
= args
[argnum
];
2553 struct type
*arg_type
= check_typedef (value_type (arg
));
2554 int len
= TYPE_LENGTH (arg_type
);
2555 enum type_code typecode
= TYPE_CODE (arg_type
);
2558 fprintf_unfiltered (gdb_stdlog
,
2559 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2560 argnum
+ 1, len
, (int) typecode
);
2562 /* The EABI passes structures that do not fit in a register by
2565 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2567 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2568 typecode
= TYPE_CODE_PTR
;
2572 fprintf_unfiltered (gdb_stdlog
, " push");
2575 val
= value_contents (arg
);
2577 /* 32-bit ABIs always start floating point arguments in an
2578 even-numbered floating point register. Round the FP register
2579 up before the check to see if there are any FP registers
2580 left. Non MIPS_EABI targets also pass the FP in the integer
2581 registers so also round up normal registers. */
2582 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2584 if ((float_argreg
& 1))
2588 /* Floating point arguments passed in registers have to be
2589 treated specially. On 32-bit architectures, doubles
2590 are passed in register pairs; the even register gets
2591 the low word, and the odd register gets the high word.
2592 On non-EABI processors, the first two floating point arguments are
2593 also copied to general registers, because MIPS16 functions
2594 don't use float registers for arguments. This duplication of
2595 arguments in general registers can't hurt non-MIPS16 functions
2596 because those registers are normally skipped. */
2597 /* MIPS_EABI squeezes a struct that contains a single floating
2598 point value into an FP register instead of pushing it onto the
2600 if (fp_register_arg_p (typecode
, arg_type
)
2601 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2603 /* EABI32 will pass doubles in consecutive registers, even on
2604 64-bit cores. At one time, we used to check the size of
2605 `float_argreg' to determine whether or not to pass doubles
2606 in consecutive registers, but this is not sufficient for
2607 making the ABI determination. */
2608 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2610 int low_offset
= gdbarch_byte_order (current_gdbarch
)
2611 == BFD_ENDIAN_BIG
? 4 : 0;
2612 unsigned long regval
;
2614 /* Write the low word of the double to the even register(s). */
2615 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2617 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2618 float_argreg
, phex (regval
, 4));
2619 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2621 /* Write the high word of the double to the odd register(s). */
2622 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2624 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2625 float_argreg
, phex (regval
, 4));
2626 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2630 /* This is a floating point value that fits entirely
2631 in a single register. */
2632 /* On 32 bit ABI's the float_argreg is further adjusted
2633 above to ensure that it is even register aligned. */
2634 LONGEST regval
= extract_unsigned_integer (val
, len
);
2636 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2637 float_argreg
, phex (regval
, len
));
2638 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2643 /* Copy the argument to general registers or the stack in
2644 register-sized pieces. Large arguments are split between
2645 registers and stack. */
2646 /* Note: structs whose size is not a multiple of regsize
2647 are treated specially: Irix cc passes
2648 them in registers where gcc sometimes puts them on the
2649 stack. For maximum compatibility, we will put them in
2651 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2653 /* Note: Floating-point values that didn't fit into an FP
2654 register are only written to memory. */
2657 /* Remember if the argument was written to the stack. */
2658 int stack_used_p
= 0;
2659 int partial_len
= (len
< regsize
? len
: regsize
);
2662 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2665 /* Write this portion of the argument to the stack. */
2666 if (argreg
> MIPS_LAST_ARG_REGNUM
2668 || fp_register_arg_p (typecode
, arg_type
))
2670 /* Should shorter than int integer values be
2671 promoted to int before being stored? */
2672 int longword_offset
= 0;
2675 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2678 && (typecode
== TYPE_CODE_INT
2679 || typecode
== TYPE_CODE_PTR
2680 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2681 longword_offset
= regsize
- len
;
2682 else if ((typecode
== TYPE_CODE_STRUCT
2683 || typecode
== TYPE_CODE_UNION
)
2684 && TYPE_LENGTH (arg_type
) < regsize
)
2685 longword_offset
= regsize
- len
;
2690 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2691 paddr_nz (stack_offset
));
2692 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2693 paddr_nz (longword_offset
));
2696 addr
= sp
+ stack_offset
+ longword_offset
;
2701 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2703 for (i
= 0; i
< partial_len
; i
++)
2705 fprintf_unfiltered (gdb_stdlog
, "%02x",
2709 write_memory (addr
, val
, partial_len
);
2712 /* Note!!! This is NOT an else clause. Odd sized
2713 structs may go thru BOTH paths. Floating point
2714 arguments will not. */
2715 /* Write this portion of the argument to a general
2716 purpose register. */
2717 if (argreg
<= MIPS_LAST_ARG_REGNUM
2718 && !fp_register_arg_p (typecode
, arg_type
))
2721 extract_unsigned_integer (val
, partial_len
);
2724 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2726 phex (regval
, regsize
));
2727 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2734 /* Compute the the offset into the stack at which we
2735 will copy the next parameter.
2737 In the new EABI (and the NABI32), the stack_offset
2738 only needs to be adjusted when it has been used. */
2741 stack_offset
+= align_up (partial_len
, regsize
);
2745 fprintf_unfiltered (gdb_stdlog
, "\n");
2748 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2750 /* Return adjusted stack pointer. */
2754 /* Determine the return value convention being used. */
2756 static enum return_value_convention
2757 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2758 struct type
*type
, struct regcache
*regcache
,
2759 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2761 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2762 return RETURN_VALUE_STRUCT_CONVENTION
;
2764 memset (readbuf
, 0, TYPE_LENGTH (type
));
2765 return RETURN_VALUE_REGISTER_CONVENTION
;
2769 /* N32/N64 ABI stuff. */
2772 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2773 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2774 int nargs
, struct value
**args
, CORE_ADDR sp
,
2775 int struct_return
, CORE_ADDR struct_addr
)
2781 int stack_offset
= 0;
2782 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2783 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2785 /* For shared libraries, "t9" needs to point at the function
2787 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2789 /* Set the return address register to point to the entry point of
2790 the program, where a breakpoint lies in wait. */
2791 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2793 /* First ensure that the stack and structure return address (if any)
2794 are properly aligned. The stack has to be at least 64-bit
2795 aligned even on 32-bit machines, because doubles must be 64-bit
2796 aligned. For n32 and n64, stack frames need to be 128-bit
2797 aligned, so we round to this widest known alignment. */
2799 sp
= align_down (sp
, 16);
2800 struct_addr
= align_down (struct_addr
, 16);
2802 /* Now make space on the stack for the args. */
2803 for (argnum
= 0; argnum
< nargs
; argnum
++)
2804 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
2805 sp
-= align_up (len
, 16);
2808 fprintf_unfiltered (gdb_stdlog
,
2809 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2810 paddr_nz (sp
), (long) align_up (len
, 16));
2812 /* Initialize the integer and float register pointers. */
2813 argreg
= MIPS_A0_REGNUM
;
2814 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2816 /* The struct_return pointer occupies the first parameter-passing reg. */
2820 fprintf_unfiltered (gdb_stdlog
,
2821 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2822 argreg
, paddr_nz (struct_addr
));
2823 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2826 /* Now load as many as possible of the first arguments into
2827 registers, and push the rest onto the stack. Loop thru args
2828 from first to last. */
2829 for (argnum
= 0; argnum
< nargs
; argnum
++)
2831 const gdb_byte
*val
;
2832 struct value
*arg
= args
[argnum
];
2833 struct type
*arg_type
= check_typedef (value_type (arg
));
2834 int len
= TYPE_LENGTH (arg_type
);
2835 enum type_code typecode
= TYPE_CODE (arg_type
);
2838 fprintf_unfiltered (gdb_stdlog
,
2839 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2840 argnum
+ 1, len
, (int) typecode
);
2842 val
= value_contents (arg
);
2844 if (fp_register_arg_p (typecode
, arg_type
)
2845 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2847 /* This is a floating point value that fits entirely
2848 in a single register. */
2849 /* On 32 bit ABI's the float_argreg is further adjusted
2850 above to ensure that it is even register aligned. */
2851 LONGEST regval
= extract_unsigned_integer (val
, len
);
2853 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2854 float_argreg
, phex (regval
, len
));
2855 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2858 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2859 argreg
, phex (regval
, len
));
2860 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2865 /* Copy the argument to general registers or the stack in
2866 register-sized pieces. Large arguments are split between
2867 registers and stack. */
2868 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
2869 are treated specially: Irix cc passes them in registers
2870 where gcc sometimes puts them on the stack. For maximum
2871 compatibility, we will put them in both places. */
2872 int odd_sized_struct
= (len
> MIPS64_REGSIZE
2873 && len
% MIPS64_REGSIZE
!= 0);
2874 /* Note: Floating-point values that didn't fit into an FP
2875 register are only written to memory. */
2878 /* Remember if the argument was written to the stack. */
2879 int stack_used_p
= 0;
2880 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
2883 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2886 /* Write this portion of the argument to the stack. */
2887 if (argreg
> MIPS_LAST_ARG_REGNUM
2889 || fp_register_arg_p (typecode
, arg_type
))
2891 /* Should shorter than int integer values be
2892 promoted to int before being stored? */
2893 int longword_offset
= 0;
2896 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2898 if ((typecode
== TYPE_CODE_INT
2899 || typecode
== TYPE_CODE_PTR
2900 || typecode
== TYPE_CODE_FLT
)
2902 longword_offset
= MIPS64_REGSIZE
- len
;
2907 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2908 paddr_nz (stack_offset
));
2909 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2910 paddr_nz (longword_offset
));
2913 addr
= sp
+ stack_offset
+ longword_offset
;
2918 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2920 for (i
= 0; i
< partial_len
; i
++)
2922 fprintf_unfiltered (gdb_stdlog
, "%02x",
2926 write_memory (addr
, val
, partial_len
);
2929 /* Note!!! This is NOT an else clause. Odd sized
2930 structs may go thru BOTH paths. Floating point
2931 arguments will not. */
2932 /* Write this portion of the argument to a general
2933 purpose register. */
2934 if (argreg
<= MIPS_LAST_ARG_REGNUM
2935 && !fp_register_arg_p (typecode
, arg_type
))
2938 extract_unsigned_integer (val
, partial_len
);
2940 /* A non-floating-point argument being passed in a
2941 general register. If a struct or union, and if
2942 the remaining length is smaller than the register
2943 size, we have to adjust the register value on
2946 It does not seem to be necessary to do the
2947 same for integral types. */
2949 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
2950 && partial_len
< MIPS64_REGSIZE
2951 && (typecode
== TYPE_CODE_STRUCT
2952 || typecode
== TYPE_CODE_UNION
))
2953 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
2957 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2959 phex (regval
, MIPS64_REGSIZE
));
2960 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2967 /* Compute the the offset into the stack at which we
2968 will copy the next parameter.
2970 In N32 (N64?), the stack_offset only needs to be
2971 adjusted when it has been used. */
2974 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
2978 fprintf_unfiltered (gdb_stdlog
, "\n");
2981 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2983 /* Return adjusted stack pointer. */
2987 static enum return_value_convention
2988 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
2989 struct type
*type
, struct regcache
*regcache
,
2990 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2992 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2993 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
2994 || TYPE_CODE (type
) == TYPE_CODE_UNION
2995 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
2996 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
2997 return RETURN_VALUE_STRUCT_CONVENTION
;
2998 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
2999 && TYPE_LENGTH (type
) == 16
3000 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3002 /* A 128-bit floating-point value fills both $f0 and $f2. The
3003 two registers are used in the same as memory order, so the
3004 eight bytes with the lower memory address are in $f0. */
3006 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3007 mips_xfer_register (regcache
,
3008 gdbarch_num_regs (current_gdbarch
)
3009 + mips_regnum (current_gdbarch
)->fp0
,
3010 8, gdbarch_byte_order (current_gdbarch
),
3011 readbuf
, writebuf
, 0);
3012 mips_xfer_register (regcache
,
3013 gdbarch_num_regs (current_gdbarch
)
3014 + mips_regnum (current_gdbarch
)->fp0
+ 2,
3015 8, gdbarch_byte_order (current_gdbarch
),
3016 readbuf
? readbuf
+ 8 : readbuf
,
3017 writebuf
? writebuf
+ 8 : writebuf
, 0);
3018 return RETURN_VALUE_REGISTER_CONVENTION
;
3020 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3021 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3023 /* A floating-point value belongs in the least significant part
3026 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3027 mips_xfer_register (regcache
,
3028 gdbarch_num_regs (current_gdbarch
)
3029 + mips_regnum (current_gdbarch
)->fp0
,
3031 gdbarch_byte_order (current_gdbarch
),
3032 readbuf
, writebuf
, 0);
3033 return RETURN_VALUE_REGISTER_CONVENTION
;
3035 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3036 && TYPE_NFIELDS (type
) <= 2
3037 && TYPE_NFIELDS (type
) >= 1
3038 && ((TYPE_NFIELDS (type
) == 1
3039 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3041 || (TYPE_NFIELDS (type
) == 2
3042 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3044 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3046 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3048 /* A struct that contains one or two floats. Each value is part
3049 in the least significant part of their floating point
3053 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3054 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3056 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3059 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3061 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3063 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3064 gdbarch_byte_order (current_gdbarch
),
3065 readbuf
, writebuf
, offset
);
3067 return RETURN_VALUE_REGISTER_CONVENTION
;
3069 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3070 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3072 /* A structure or union. Extract the left justified value,
3073 regardless of the byte order. I.e. DO NOT USE
3077 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3078 offset
< TYPE_LENGTH (type
);
3079 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3081 int xfer
= register_size (current_gdbarch
, regnum
);
3082 if (offset
+ xfer
> TYPE_LENGTH (type
))
3083 xfer
= TYPE_LENGTH (type
) - offset
;
3085 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3086 offset
, xfer
, regnum
);
3087 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3089 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3091 return RETURN_VALUE_REGISTER_CONVENTION
;
3095 /* A scalar extract each part but least-significant-byte
3099 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3100 offset
< TYPE_LENGTH (type
);
3101 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3103 int xfer
= register_size (current_gdbarch
, regnum
);
3104 if (offset
+ xfer
> TYPE_LENGTH (type
))
3105 xfer
= TYPE_LENGTH (type
) - offset
;
3107 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3108 offset
, xfer
, regnum
);
3109 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3111 gdbarch_byte_order (current_gdbarch
),
3112 readbuf
, writebuf
, offset
);
3114 return RETURN_VALUE_REGISTER_CONVENTION
;
3118 /* O32 ABI stuff. */
3121 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3122 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3123 int nargs
, struct value
**args
, CORE_ADDR sp
,
3124 int struct_return
, CORE_ADDR struct_addr
)
3130 int stack_offset
= 0;
3131 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3132 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3134 /* For shared libraries, "t9" needs to point at the function
3136 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3138 /* Set the return address register to point to the entry point of
3139 the program, where a breakpoint lies in wait. */
3140 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3142 /* First ensure that the stack and structure return address (if any)
3143 are properly aligned. The stack has to be at least 64-bit
3144 aligned even on 32-bit machines, because doubles must be 64-bit
3145 aligned. For n32 and n64, stack frames need to be 128-bit
3146 aligned, so we round to this widest known alignment. */
3148 sp
= align_down (sp
, 16);
3149 struct_addr
= align_down (struct_addr
, 16);
3151 /* Now make space on the stack for the args. */
3152 for (argnum
= 0; argnum
< nargs
; argnum
++)
3154 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3155 int arglen
= TYPE_LENGTH (arg_type
);
3157 /* Align to double-word if necessary. */
3158 if (mips_type_needs_double_align (arg_type
))
3159 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3160 /* Allocate space on the stack. */
3161 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3163 sp
-= align_up (len
, 16);
3166 fprintf_unfiltered (gdb_stdlog
,
3167 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3168 paddr_nz (sp
), (long) align_up (len
, 16));
3170 /* Initialize the integer and float register pointers. */
3171 argreg
= MIPS_A0_REGNUM
;
3172 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3174 /* The struct_return pointer occupies the first parameter-passing reg. */
3178 fprintf_unfiltered (gdb_stdlog
,
3179 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3180 argreg
, paddr_nz (struct_addr
));
3181 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3182 stack_offset
+= MIPS32_REGSIZE
;
3185 /* Now load as many as possible of the first arguments into
3186 registers, and push the rest onto the stack. Loop thru args
3187 from first to last. */
3188 for (argnum
= 0; argnum
< nargs
; argnum
++)
3190 const gdb_byte
*val
;
3191 struct value
*arg
= args
[argnum
];
3192 struct type
*arg_type
= check_typedef (value_type (arg
));
3193 int len
= TYPE_LENGTH (arg_type
);
3194 enum type_code typecode
= TYPE_CODE (arg_type
);
3197 fprintf_unfiltered (gdb_stdlog
,
3198 "mips_o32_push_dummy_call: %d len=%d type=%d",
3199 argnum
+ 1, len
, (int) typecode
);
3201 val
= value_contents (arg
);
3203 /* 32-bit ABIs always start floating point arguments in an
3204 even-numbered floating point register. Round the FP register
3205 up before the check to see if there are any FP registers
3206 left. O32/O64 targets also pass the FP in the integer
3207 registers so also round up normal registers. */
3208 if (fp_register_arg_p (typecode
, arg_type
))
3210 if ((float_argreg
& 1))
3214 /* Floating point arguments passed in registers have to be
3215 treated specially. On 32-bit architectures, doubles
3216 are passed in register pairs; the even register gets
3217 the low word, and the odd register gets the high word.
3218 On O32/O64, the first two floating point arguments are
3219 also copied to general registers, because MIPS16 functions
3220 don't use float registers for arguments. This duplication of
3221 arguments in general registers can't hurt non-MIPS16 functions
3222 because those registers are normally skipped. */
3224 if (fp_register_arg_p (typecode
, arg_type
)
3225 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3227 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3229 int low_offset
= gdbarch_byte_order (current_gdbarch
)
3230 == BFD_ENDIAN_BIG
? 4 : 0;
3231 unsigned long regval
;
3233 /* Write the low word of the double to the even register(s). */
3234 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3236 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3237 float_argreg
, phex (regval
, 4));
3238 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3240 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3241 argreg
, phex (regval
, 4));
3242 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3244 /* Write the high word of the double to the odd register(s). */
3245 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3247 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3248 float_argreg
, phex (regval
, 4));
3249 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3252 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3253 argreg
, phex (regval
, 4));
3254 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3258 /* This is a floating point value that fits entirely
3259 in a single register. */
3260 /* On 32 bit ABI's the float_argreg is further adjusted
3261 above to ensure that it is even register aligned. */
3262 LONGEST regval
= extract_unsigned_integer (val
, len
);
3264 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3265 float_argreg
, phex (regval
, len
));
3266 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3267 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3268 registers for each argument. The below is (my
3269 guess) to ensure that the corresponding integer
3270 register has reserved the same space. */
3272 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3273 argreg
, phex (regval
, len
));
3274 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3277 /* Reserve space for the FP register. */
3278 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3282 /* Copy the argument to general registers or the stack in
3283 register-sized pieces. Large arguments are split between
3284 registers and stack. */
3285 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3286 are treated specially: Irix cc passes
3287 them in registers where gcc sometimes puts them on the
3288 stack. For maximum compatibility, we will put them in
3290 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3291 && len
% MIPS32_REGSIZE
!= 0);
3292 /* Structures should be aligned to eight bytes (even arg registers)
3293 on MIPS_ABI_O32, if their first member has double precision. */
3294 if (mips_type_needs_double_align (arg_type
))
3299 stack_offset
+= MIPS32_REGSIZE
;
3304 /* Remember if the argument was written to the stack. */
3305 int stack_used_p
= 0;
3306 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3309 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3312 /* Write this portion of the argument to the stack. */
3313 if (argreg
> MIPS_LAST_ARG_REGNUM
3314 || odd_sized_struct
)
3316 /* Should shorter than int integer values be
3317 promoted to int before being stored? */
3318 int longword_offset
= 0;
3324 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3325 paddr_nz (stack_offset
));
3326 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3327 paddr_nz (longword_offset
));
3330 addr
= sp
+ stack_offset
+ longword_offset
;
3335 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3337 for (i
= 0; i
< partial_len
; i
++)
3339 fprintf_unfiltered (gdb_stdlog
, "%02x",
3343 write_memory (addr
, val
, partial_len
);
3346 /* Note!!! This is NOT an else clause. Odd sized
3347 structs may go thru BOTH paths. */
3348 /* Write this portion of the argument to a general
3349 purpose register. */
3350 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3352 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3353 /* Value may need to be sign extended, because
3354 mips_isa_regsize() != mips_abi_regsize(). */
3356 /* A non-floating-point argument being passed in a
3357 general register. If a struct or union, and if
3358 the remaining length is smaller than the register
3359 size, we have to adjust the register value on
3362 It does not seem to be necessary to do the
3363 same for integral types.
3365 Also don't do this adjustment on O64 binaries.
3367 cagney/2001-07-23: gdb/179: Also, GCC, when
3368 outputting LE O32 with sizeof (struct) <
3369 mips_abi_regsize(), generates a left shift
3370 as part of storing the argument in a register
3371 (the left shift isn't generated when
3372 sizeof (struct) >= mips_abi_regsize()). Since
3373 it is quite possible that this is GCC
3374 contradicting the LE/O32 ABI, GDB has not been
3375 adjusted to accommodate this. Either someone
3376 needs to demonstrate that the LE/O32 ABI
3377 specifies such a left shift OR this new ABI gets
3378 identified as such and GDB gets tweaked
3381 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3382 && partial_len
< MIPS32_REGSIZE
3383 && (typecode
== TYPE_CODE_STRUCT
3384 || typecode
== TYPE_CODE_UNION
))
3385 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3389 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3391 phex (regval
, MIPS32_REGSIZE
));
3392 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3395 /* Prevent subsequent floating point arguments from
3396 being passed in floating point registers. */
3397 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3403 /* Compute the the offset into the stack at which we
3404 will copy the next parameter.
3406 In older ABIs, the caller reserved space for
3407 registers that contained arguments. This was loosely
3408 refered to as their "home". Consequently, space is
3409 always allocated. */
3411 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3415 fprintf_unfiltered (gdb_stdlog
, "\n");
3418 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3420 /* Return adjusted stack pointer. */
3424 static enum return_value_convention
3425 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3426 struct regcache
*regcache
,
3427 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3429 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3431 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3432 || TYPE_CODE (type
) == TYPE_CODE_UNION
3433 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3434 return RETURN_VALUE_STRUCT_CONVENTION
;
3435 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3436 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3438 /* A single-precision floating-point value. It fits in the
3439 least significant part of FP0. */
3441 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3442 mips_xfer_register (regcache
,
3443 gdbarch_num_regs (current_gdbarch
)
3444 + mips_regnum (current_gdbarch
)->fp0
,
3446 gdbarch_byte_order (current_gdbarch
),
3447 readbuf
, writebuf
, 0);
3448 return RETURN_VALUE_REGISTER_CONVENTION
;
3450 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3451 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3453 /* A double-precision floating-point value. The most
3454 significant part goes in FP1, and the least significant in
3457 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3458 switch (gdbarch_byte_order (current_gdbarch
))
3460 case BFD_ENDIAN_LITTLE
:
3461 mips_xfer_register (regcache
,
3462 gdbarch_num_regs (current_gdbarch
)
3463 + mips_regnum (current_gdbarch
)->fp0
+
3464 0, 4, gdbarch_byte_order (current_gdbarch
),
3465 readbuf
, writebuf
, 0);
3466 mips_xfer_register (regcache
,
3467 gdbarch_num_regs (current_gdbarch
)
3468 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3469 4, gdbarch_byte_order (current_gdbarch
),
3470 readbuf
, writebuf
, 4);
3472 case BFD_ENDIAN_BIG
:
3473 mips_xfer_register (regcache
,
3474 gdbarch_num_regs (current_gdbarch
)
3475 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3476 4, gdbarch_byte_order (current_gdbarch
),
3477 readbuf
, writebuf
, 0);
3478 mips_xfer_register (regcache
,
3479 gdbarch_num_regs (current_gdbarch
)
3480 + mips_regnum (current_gdbarch
)->fp0
+ 0,
3481 4, gdbarch_byte_order (current_gdbarch
),
3482 readbuf
, writebuf
, 4);
3485 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3487 return RETURN_VALUE_REGISTER_CONVENTION
;
3490 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3491 && TYPE_NFIELDS (type
) <= 2
3492 && TYPE_NFIELDS (type
) >= 1
3493 && ((TYPE_NFIELDS (type
) == 1
3494 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3496 || (TYPE_NFIELDS (type
) == 2
3497 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3499 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3501 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3503 /* A struct that contains one or two floats. Each value is part
3504 in the least significant part of their floating point
3506 gdb_byte reg
[MAX_REGISTER_SIZE
];
3509 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3510 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3512 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3515 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3517 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3519 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3520 gdbarch_byte_order (current_gdbarch
),
3521 readbuf
, writebuf
, offset
);
3523 return RETURN_VALUE_REGISTER_CONVENTION
;
3527 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3528 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3530 /* A structure or union. Extract the left justified value,
3531 regardless of the byte order. I.e. DO NOT USE
3535 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3536 offset
< TYPE_LENGTH (type
);
3537 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3539 int xfer
= register_size (current_gdbarch
, regnum
);
3540 if (offset
+ xfer
> TYPE_LENGTH (type
))
3541 xfer
= TYPE_LENGTH (type
) - offset
;
3543 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3544 offset
, xfer
, regnum
);
3545 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3547 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3549 return RETURN_VALUE_REGISTER_CONVENTION
;
3554 /* A scalar extract each part but least-significant-byte
3555 justified. o32 thinks registers are 4 byte, regardless of
3559 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3560 offset
< TYPE_LENGTH (type
);
3561 offset
+= MIPS32_REGSIZE
, regnum
++)
3563 int xfer
= MIPS32_REGSIZE
;
3564 if (offset
+ xfer
> TYPE_LENGTH (type
))
3565 xfer
= TYPE_LENGTH (type
) - offset
;
3567 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3568 offset
, xfer
, regnum
);
3569 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3571 gdbarch_byte_order (current_gdbarch
),
3572 readbuf
, writebuf
, offset
);
3574 return RETURN_VALUE_REGISTER_CONVENTION
;
3578 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3582 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3583 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3585 struct value
**args
, CORE_ADDR sp
,
3586 int struct_return
, CORE_ADDR struct_addr
)
3592 int stack_offset
= 0;
3593 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3594 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3596 /* For shared libraries, "t9" needs to point at the function
3598 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3600 /* Set the return address register to point to the entry point of
3601 the program, where a breakpoint lies in wait. */
3602 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3604 /* First ensure that the stack and structure return address (if any)
3605 are properly aligned. The stack has to be at least 64-bit
3606 aligned even on 32-bit machines, because doubles must be 64-bit
3607 aligned. For n32 and n64, stack frames need to be 128-bit
3608 aligned, so we round to this widest known alignment. */
3610 sp
= align_down (sp
, 16);
3611 struct_addr
= align_down (struct_addr
, 16);
3613 /* Now make space on the stack for the args. */
3614 for (argnum
= 0; argnum
< nargs
; argnum
++)
3616 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3617 int arglen
= TYPE_LENGTH (arg_type
);
3619 /* Allocate space on the stack. */
3620 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3622 sp
-= align_up (len
, 16);
3625 fprintf_unfiltered (gdb_stdlog
,
3626 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3627 paddr_nz (sp
), (long) align_up (len
, 16));
3629 /* Initialize the integer and float register pointers. */
3630 argreg
= MIPS_A0_REGNUM
;
3631 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3633 /* The struct_return pointer occupies the first parameter-passing reg. */
3637 fprintf_unfiltered (gdb_stdlog
,
3638 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3639 argreg
, paddr_nz (struct_addr
));
3640 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3641 stack_offset
+= MIPS64_REGSIZE
;
3644 /* Now load as many as possible of the first arguments into
3645 registers, and push the rest onto the stack. Loop thru args
3646 from first to last. */
3647 for (argnum
= 0; argnum
< nargs
; argnum
++)
3649 const gdb_byte
*val
;
3650 struct value
*arg
= args
[argnum
];
3651 struct type
*arg_type
= check_typedef (value_type (arg
));
3652 int len
= TYPE_LENGTH (arg_type
);
3653 enum type_code typecode
= TYPE_CODE (arg_type
);
3656 fprintf_unfiltered (gdb_stdlog
,
3657 "mips_o64_push_dummy_call: %d len=%d type=%d",
3658 argnum
+ 1, len
, (int) typecode
);
3660 val
= value_contents (arg
);
3662 /* Floating point arguments passed in registers have to be
3663 treated specially. On 32-bit architectures, doubles
3664 are passed in register pairs; the even register gets
3665 the low word, and the odd register gets the high word.
3666 On O32/O64, the first two floating point arguments are
3667 also copied to general registers, because MIPS16 functions
3668 don't use float registers for arguments. This duplication of
3669 arguments in general registers can't hurt non-MIPS16 functions
3670 because those registers are normally skipped. */
3672 if (fp_register_arg_p (typecode
, arg_type
)
3673 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3675 LONGEST regval
= extract_unsigned_integer (val
, len
);
3677 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3678 float_argreg
, phex (regval
, len
));
3679 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3681 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3682 argreg
, phex (regval
, len
));
3683 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3685 /* Reserve space for the FP register. */
3686 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3690 /* Copy the argument to general registers or the stack in
3691 register-sized pieces. Large arguments are split between
3692 registers and stack. */
3693 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3694 are treated specially: Irix cc passes them in registers
3695 where gcc sometimes puts them on the stack. For maximum
3696 compatibility, we will put them in both places. */
3697 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3698 && len
% MIPS64_REGSIZE
!= 0);
3701 /* Remember if the argument was written to the stack. */
3702 int stack_used_p
= 0;
3703 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3706 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3709 /* Write this portion of the argument to the stack. */
3710 if (argreg
> MIPS_LAST_ARG_REGNUM
3711 || odd_sized_struct
)
3713 /* Should shorter than int integer values be
3714 promoted to int before being stored? */
3715 int longword_offset
= 0;
3718 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3720 if ((typecode
== TYPE_CODE_INT
3721 || typecode
== TYPE_CODE_PTR
3722 || typecode
== TYPE_CODE_FLT
)
3724 longword_offset
= MIPS64_REGSIZE
- len
;
3729 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3730 paddr_nz (stack_offset
));
3731 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3732 paddr_nz (longword_offset
));
3735 addr
= sp
+ stack_offset
+ longword_offset
;
3740 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3742 for (i
= 0; i
< partial_len
; i
++)
3744 fprintf_unfiltered (gdb_stdlog
, "%02x",
3748 write_memory (addr
, val
, partial_len
);
3751 /* Note!!! This is NOT an else clause. Odd sized
3752 structs may go thru BOTH paths. */
3753 /* Write this portion of the argument to a general
3754 purpose register. */
3755 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3757 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3758 /* Value may need to be sign extended, because
3759 mips_isa_regsize() != mips_abi_regsize(). */
3761 /* A non-floating-point argument being passed in a
3762 general register. If a struct or union, and if
3763 the remaining length is smaller than the register
3764 size, we have to adjust the register value on
3767 It does not seem to be necessary to do the
3768 same for integral types. */
3770 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3771 && partial_len
< MIPS64_REGSIZE
3772 && (typecode
== TYPE_CODE_STRUCT
3773 || typecode
== TYPE_CODE_UNION
))
3774 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3778 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3780 phex (regval
, MIPS64_REGSIZE
));
3781 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3784 /* Prevent subsequent floating point arguments from
3785 being passed in floating point registers. */
3786 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3792 /* Compute the the offset into the stack at which we
3793 will copy the next parameter.
3795 In older ABIs, the caller reserved space for
3796 registers that contained arguments. This was loosely
3797 refered to as their "home". Consequently, space is
3798 always allocated. */
3800 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3804 fprintf_unfiltered (gdb_stdlog
, "\n");
3807 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3809 /* Return adjusted stack pointer. */
3813 static enum return_value_convention
3814 mips_o64_return_value (struct gdbarch
*gdbarch
,
3815 struct type
*type
, struct regcache
*regcache
,
3816 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3818 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3820 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3821 || TYPE_CODE (type
) == TYPE_CODE_UNION
3822 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3823 return RETURN_VALUE_STRUCT_CONVENTION
;
3824 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3826 /* A floating-point value. It fits in the least significant
3829 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3830 mips_xfer_register (regcache
,
3831 gdbarch_num_regs (current_gdbarch
)
3832 + mips_regnum (current_gdbarch
)->fp0
,
3834 gdbarch_byte_order (current_gdbarch
),
3835 readbuf
, writebuf
, 0);
3836 return RETURN_VALUE_REGISTER_CONVENTION
;
3840 /* A scalar extract each part but least-significant-byte
3844 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3845 offset
< TYPE_LENGTH (type
);
3846 offset
+= MIPS64_REGSIZE
, regnum
++)
3848 int xfer
= MIPS64_REGSIZE
;
3849 if (offset
+ xfer
> TYPE_LENGTH (type
))
3850 xfer
= TYPE_LENGTH (type
) - offset
;
3852 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3853 offset
, xfer
, regnum
);
3854 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3856 gdbarch_byte_order (current_gdbarch
),
3857 readbuf
, writebuf
, offset
);
3859 return RETURN_VALUE_REGISTER_CONVENTION
;
3863 /* Floating point register management.
3865 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3866 64bit operations, these early MIPS cpus treat fp register pairs
3867 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3868 registers and offer a compatibility mode that emulates the MIPS2 fp
3869 model. When operating in MIPS2 fp compat mode, later cpu's split
3870 double precision floats into two 32-bit chunks and store them in
3871 consecutive fp regs. To display 64-bit floats stored in this
3872 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3873 Throw in user-configurable endianness and you have a real mess.
3875 The way this works is:
3876 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3877 double-precision value will be split across two logical registers.
3878 The lower-numbered logical register will hold the low-order bits,
3879 regardless of the processor's endianness.
3880 - If we are on a 64-bit processor, and we are looking for a
3881 single-precision value, it will be in the low ordered bits
3882 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3883 save slot in memory.
3884 - If we are in 64-bit mode, everything is straightforward.
3886 Note that this code only deals with "live" registers at the top of the
3887 stack. We will attempt to deal with saved registers later, when
3888 the raw/cooked register interface is in place. (We need a general
3889 interface that can deal with dynamic saved register sizes -- fp
3890 regs could be 32 bits wide in one frame and 64 on the frame above
3893 static struct type
*
3894 mips_float_register_type (void)
3896 return builtin_type_ieee_single
;
3899 static struct type
*
3900 mips_double_register_type (void)
3902 return builtin_type_ieee_double
;
3905 /* Copy a 32-bit single-precision value from the current frame
3906 into rare_buffer. */
3909 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3910 gdb_byte
*rare_buffer
)
3912 int raw_size
= register_size (current_gdbarch
, regno
);
3913 gdb_byte
*raw_buffer
= alloca (raw_size
);
3915 if (!frame_register_read (frame
, regno
, raw_buffer
))
3916 error (_("can't read register %d (%s)"),
3917 regno
, gdbarch_register_name (current_gdbarch
, regno
));
3920 /* We have a 64-bit value for this register. Find the low-order
3924 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3929 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3933 memcpy (rare_buffer
, raw_buffer
, 4);
3937 /* Copy a 64-bit double-precision value from the current frame into
3938 rare_buffer. This may include getting half of it from the next
3942 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
3943 gdb_byte
*rare_buffer
)
3945 int raw_size
= register_size (current_gdbarch
, regno
);
3947 if (raw_size
== 8 && !mips2_fp_compat (frame
))
3949 /* We have a 64-bit value for this register, and we should use
3951 if (!frame_register_read (frame
, regno
, rare_buffer
))
3952 error (_("can't read register %d (%s)"),
3953 regno
, gdbarch_register_name (current_gdbarch
, regno
));
3957 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
3958 internal_error (__FILE__
, __LINE__
,
3959 _("mips_read_fp_register_double: bad access to "
3960 "odd-numbered FP register"));
3962 /* mips_read_fp_register_single will find the correct 32 bits from
3964 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3966 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
3967 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
3971 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
3972 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
3978 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
3980 { /* do values for FP (float) regs */
3981 gdb_byte
*raw_buffer
;
3982 double doub
, flt1
; /* doubles extracted from raw hex data */
3985 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
3986 mips_regnum (current_gdbarch
)->fp0
));
3988 fprintf_filtered (file
, "%s:",
3989 gdbarch_register_name (current_gdbarch
, regnum
));
3990 fprintf_filtered (file
, "%*s",
3991 4 - (int) strlen (gdbarch_register_name
3992 (current_gdbarch
, regnum
)),
3995 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
3997 /* 4-byte registers: Print hex and floating. Also print even
3998 numbered registers as doubles. */
3999 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4000 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4002 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4005 fprintf_filtered (file
, " flt: ");
4007 fprintf_filtered (file
, " <invalid float> ");
4009 fprintf_filtered (file
, "%-17.9g", flt1
);
4011 if (regnum
% 2 == 0)
4013 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4014 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4017 fprintf_filtered (file
, " dbl: ");
4019 fprintf_filtered (file
, "<invalid double>");
4021 fprintf_filtered (file
, "%-24.17g", doub
);
4026 /* Eight byte registers: print each one as hex, float and double. */
4027 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4028 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4030 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4031 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4034 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4037 fprintf_filtered (file
, " flt: ");
4039 fprintf_filtered (file
, "<invalid float>");
4041 fprintf_filtered (file
, "%-17.9g", flt1
);
4043 fprintf_filtered (file
, " dbl: ");
4045 fprintf_filtered (file
, "<invalid double>");
4047 fprintf_filtered (file
, "%-24.17g", doub
);
4052 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4055 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4056 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4059 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4061 mips_print_fp_register (file
, frame
, regnum
);
4065 /* Get the data in raw format. */
4066 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4068 fprintf_filtered (file
, "%s: [Invalid]",
4069 gdbarch_register_name (current_gdbarch
, regnum
));
4073 fputs_filtered (gdbarch_register_name (current_gdbarch
, regnum
), file
);
4075 /* The problem with printing numeric register names (r26, etc.) is that
4076 the user can't use them on input. Probably the best solution is to
4077 fix it so that either the numeric or the funky (a2, etc.) names
4078 are accepted on input. */
4079 if (regnum
< MIPS_NUMREGS
)
4080 fprintf_filtered (file
, "(r%d): ", regnum
);
4082 fprintf_filtered (file
, ": ");
4084 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4086 register_size (current_gdbarch
,
4087 regnum
) - register_size (current_gdbarch
, regnum
);
4091 print_scalar_formatted (raw_buffer
+ offset
,
4092 register_type (gdbarch
, regnum
), 'x', 0,
4096 /* Replacement for generic do_registers_info.
4097 Print regs in pretty columns. */
4100 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4103 fprintf_filtered (file
, " ");
4104 mips_print_fp_register (file
, frame
, regnum
);
4105 fprintf_filtered (file
, "\n");
4110 /* Print a row's worth of GP (int) registers, with name labels above */
4113 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4116 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4117 /* do values for GP (int) regs */
4118 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4119 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4123 /* For GP registers, we print a separate row of names above the vals */
4124 for (col
= 0, regnum
= start_regnum
;
4125 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4126 + gdbarch_num_pseudo_regs (current_gdbarch
);
4129 if (*gdbarch_register_name (current_gdbarch
, regnum
) == '\0')
4130 continue; /* unused register */
4131 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4133 break; /* end the row: reached FP register */
4134 /* Large registers are handled separately. */
4135 if (register_size (current_gdbarch
, regnum
)
4136 > mips_abi_regsize (current_gdbarch
))
4139 break; /* End the row before this register. */
4141 /* Print this register on a row by itself. */
4142 mips_print_register (file
, frame
, regnum
);
4143 fprintf_filtered (file
, "\n");
4147 fprintf_filtered (file
, " ");
4148 fprintf_filtered (file
,
4149 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4150 gdbarch_register_name (current_gdbarch
, regnum
));
4157 /* print the R0 to R31 names */
4158 if ((start_regnum
% gdbarch_num_regs (current_gdbarch
)) < MIPS_NUMREGS
)
4159 fprintf_filtered (file
, "\n R%-4d",
4160 start_regnum
% gdbarch_num_regs (current_gdbarch
));
4162 fprintf_filtered (file
, "\n ");
4164 /* now print the values in hex, 4 or 8 to the row */
4165 for (col
= 0, regnum
= start_regnum
;
4166 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4167 + gdbarch_num_pseudo_regs (current_gdbarch
);
4170 if (*gdbarch_register_name (current_gdbarch
, regnum
) == '\0')
4171 continue; /* unused register */
4172 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4174 break; /* end row: reached FP register */
4175 if (register_size (current_gdbarch
, regnum
)
4176 > mips_abi_regsize (current_gdbarch
))
4177 break; /* End row: large register. */
4179 /* OK: get the data in raw format. */
4180 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4181 error (_("can't read register %d (%s)"),
4182 regnum
, gdbarch_register_name (current_gdbarch
, regnum
));
4183 /* pad small registers */
4185 byte
< (mips_abi_regsize (current_gdbarch
)
4186 - register_size (current_gdbarch
, regnum
)); byte
++)
4187 printf_filtered (" ");
4188 /* Now print the register value in hex, endian order. */
4189 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4191 register_size (current_gdbarch
,
4192 regnum
) - register_size (current_gdbarch
, regnum
);
4193 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4194 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4196 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4198 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4199 fprintf_filtered (file
, " ");
4202 if (col
> 0) /* ie. if we actually printed anything... */
4203 fprintf_filtered (file
, "\n");
4208 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4211 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4212 struct frame_info
*frame
, int regnum
, int all
)
4214 if (regnum
!= -1) /* do one specified register */
4216 gdb_assert (regnum
>= gdbarch_num_regs (current_gdbarch
));
4217 if (*(gdbarch_register_name (current_gdbarch
, regnum
)) == '\0')
4218 error (_("Not a valid register for the current processor type"));
4220 mips_print_register (file
, frame
, regnum
);
4221 fprintf_filtered (file
, "\n");
4224 /* do all (or most) registers */
4226 regnum
= gdbarch_num_regs (current_gdbarch
);
4227 while (regnum
< gdbarch_num_regs (current_gdbarch
)
4228 + gdbarch_num_pseudo_regs (current_gdbarch
))
4230 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4233 if (all
) /* true for "INFO ALL-REGISTERS" command */
4234 regnum
= print_fp_register_row (file
, frame
, regnum
);
4236 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4239 regnum
= print_gp_register_row (file
, frame
, regnum
);
4244 /* Is this a branch with a delay slot? */
4247 is_delayed (unsigned long insn
)
4250 for (i
= 0; i
< NUMOPCODES
; ++i
)
4251 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4252 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4254 return (i
< NUMOPCODES
4255 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4256 | INSN_COND_BRANCH_DELAY
4257 | INSN_COND_BRANCH_LIKELY
)));
4261 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4262 struct frame_info
*frame
)
4264 CORE_ADDR pc
= get_frame_pc (frame
);
4265 gdb_byte buf
[MIPS_INSN32_SIZE
];
4267 /* There is no branch delay slot on MIPS16. */
4268 if (mips_pc_is_mips16 (pc
))
4271 if (!breakpoint_here_p (pc
+ 4))
4274 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4275 /* If error reading memory, guess that it is not a delayed
4278 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4281 /* To skip prologues, I use this predicate. Returns either PC itself
4282 if the code at PC does not look like a function prologue; otherwise
4283 returns an address that (if we're lucky) follows the prologue. If
4284 LENIENT, then we must skip everything which is involved in setting
4285 up the frame (it's OK to skip more, just so long as we don't skip
4286 anything which might clobber the registers which are being saved.
4287 We must skip more in the case where part of the prologue is in the
4288 delay slot of a non-prologue instruction). */
4291 mips_skip_prologue (CORE_ADDR pc
)
4294 CORE_ADDR func_addr
;
4296 /* See if we can determine the end of the prologue via the symbol table.
4297 If so, then return either PC, or the PC after the prologue, whichever
4299 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4301 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4302 if (post_prologue_pc
!= 0)
4303 return max (pc
, post_prologue_pc
);
4306 /* Can't determine prologue from the symbol table, need to examine
4309 /* Find an upper limit on the function prologue using the debug
4310 information. If the debug information could not be used to provide
4311 that bound, then use an arbitrary large number as the upper bound. */
4312 limit_pc
= skip_prologue_using_sal (pc
);
4314 limit_pc
= pc
+ 100; /* Magic. */
4316 if (mips_pc_is_mips16 (pc
))
4317 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4319 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4322 /* Root of all "set mips "/"show mips " commands. This will eventually be
4323 used for all MIPS-specific commands. */
4326 show_mips_command (char *args
, int from_tty
)
4328 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4332 set_mips_command (char *args
, int from_tty
)
4335 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4336 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4339 /* Commands to show/set the MIPS FPU type. */
4342 show_mipsfpu_command (char *args
, int from_tty
)
4345 switch (MIPS_FPU_TYPE
)
4347 case MIPS_FPU_SINGLE
:
4348 fpu
= "single-precision";
4350 case MIPS_FPU_DOUBLE
:
4351 fpu
= "double-precision";
4354 fpu
= "absent (none)";
4357 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4359 if (mips_fpu_type_auto
)
4361 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4365 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4370 set_mipsfpu_command (char *args
, int from_tty
)
4373 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4374 show_mipsfpu_command (args
, from_tty
);
4378 set_mipsfpu_single_command (char *args
, int from_tty
)
4380 struct gdbarch_info info
;
4381 gdbarch_info_init (&info
);
4382 mips_fpu_type
= MIPS_FPU_SINGLE
;
4383 mips_fpu_type_auto
= 0;
4384 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4385 instead of relying on globals. Doing that would let generic code
4386 handle the search for this specific architecture. */
4387 if (!gdbarch_update_p (info
))
4388 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4392 set_mipsfpu_double_command (char *args
, int from_tty
)
4394 struct gdbarch_info info
;
4395 gdbarch_info_init (&info
);
4396 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4397 mips_fpu_type_auto
= 0;
4398 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4399 instead of relying on globals. Doing that would let generic code
4400 handle the search for this specific architecture. */
4401 if (!gdbarch_update_p (info
))
4402 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4406 set_mipsfpu_none_command (char *args
, int from_tty
)
4408 struct gdbarch_info info
;
4409 gdbarch_info_init (&info
);
4410 mips_fpu_type
= MIPS_FPU_NONE
;
4411 mips_fpu_type_auto
= 0;
4412 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4413 instead of relying on globals. Doing that would let generic code
4414 handle the search for this specific architecture. */
4415 if (!gdbarch_update_p (info
))
4416 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4420 set_mipsfpu_auto_command (char *args
, int from_tty
)
4422 mips_fpu_type_auto
= 1;
4425 /* Attempt to identify the particular processor model by reading the
4426 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4427 the relevant processor still exists (it dates back to '94) and
4428 secondly this is not the way to do this. The processor type should
4429 be set by forcing an architecture change. */
4432 deprecated_mips_set_processor_regs_hack (void)
4434 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4437 regcache_cooked_read_unsigned (get_current_regcache (),
4438 MIPS_PRID_REGNUM
, &prid
);
4439 if ((prid
& ~0xf) == 0x700)
4440 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4443 /* Just like reinit_frame_cache, but with the right arguments to be
4444 callable as an sfunc. */
4447 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4448 struct cmd_list_element
*c
)
4450 reinit_frame_cache ();
4454 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4456 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4458 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4459 disassembler needs to be able to locally determine the ISA, and
4460 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4462 if (mips_pc_is_mips16 (memaddr
))
4463 info
->mach
= bfd_mach_mips16
;
4465 /* Round down the instruction address to the appropriate boundary. */
4466 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4468 /* Set the disassembler options. */
4469 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4471 /* Set up the disassembler info, so that we get the right
4472 register names from libopcodes. */
4473 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4474 info
->disassembler_options
= "gpr-names=n32";
4476 info
->disassembler_options
= "gpr-names=64";
4477 info
->flavour
= bfd_target_elf_flavour
;
4480 /* This string is not recognized explicitly by the disassembler,
4481 but it tells the disassembler to not try to guess the ABI from
4482 the bfd elf headers, such that, if the user overrides the ABI
4483 of a program linked as NewABI, the disassembly will follow the
4484 register naming conventions specified by the user. */
4485 info
->disassembler_options
= "gpr-names=32";
4487 /* Call the appropriate disassembler based on the target endian-ness. */
4488 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4489 return print_insn_big_mips (memaddr
, info
);
4491 return print_insn_little_mips (memaddr
, info
);
4494 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4495 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4496 It returns a pointer to a string of bytes that encode a breakpoint
4497 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4498 necessary) to point to the actual memory location where the breakpoint
4499 should be inserted. */
4501 static const gdb_byte
*
4502 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4504 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4506 if (mips_pc_is_mips16 (*pcptr
))
4508 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4509 *pcptr
= unmake_mips16_addr (*pcptr
);
4510 *lenptr
= sizeof (mips16_big_breakpoint
);
4511 return mips16_big_breakpoint
;
4515 /* The IDT board uses an unusual breakpoint value, and
4516 sometimes gets confused when it sees the usual MIPS
4517 breakpoint instruction. */
4518 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4519 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4520 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4522 *lenptr
= sizeof (big_breakpoint
);
4524 if (strcmp (target_shortname
, "mips") == 0)
4525 return idt_big_breakpoint
;
4526 else if (strcmp (target_shortname
, "ddb") == 0
4527 || strcmp (target_shortname
, "pmon") == 0
4528 || strcmp (target_shortname
, "lsi") == 0)
4529 return pmon_big_breakpoint
;
4531 return big_breakpoint
;
4536 if (mips_pc_is_mips16 (*pcptr
))
4538 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4539 *pcptr
= unmake_mips16_addr (*pcptr
);
4540 *lenptr
= sizeof (mips16_little_breakpoint
);
4541 return mips16_little_breakpoint
;
4545 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4546 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4547 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4549 *lenptr
= sizeof (little_breakpoint
);
4551 if (strcmp (target_shortname
, "mips") == 0)
4552 return idt_little_breakpoint
;
4553 else if (strcmp (target_shortname
, "ddb") == 0
4554 || strcmp (target_shortname
, "pmon") == 0
4555 || strcmp (target_shortname
, "lsi") == 0)
4556 return pmon_little_breakpoint
;
4558 return little_breakpoint
;
4563 /* If PC is in a mips16 call or return stub, return the address of the target
4564 PC, which is either the callee or the caller. There are several
4565 cases which must be handled:
4567 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4568 target PC is in $31 ($ra).
4569 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4570 and the target PC is in $2.
4571 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4572 before the jal instruction, this is effectively a call stub
4573 and the the target PC is in $2. Otherwise this is effectively
4574 a return stub and the target PC is in $18.
4576 See the source code for the stubs in gcc/config/mips/mips16.S for
4580 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
4583 CORE_ADDR start_addr
;
4585 /* Find the starting address and name of the function containing the PC. */
4586 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4589 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4590 target PC is in $31 ($ra). */
4591 if (strcmp (name
, "__mips16_ret_sf") == 0
4592 || strcmp (name
, "__mips16_ret_df") == 0)
4593 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
4595 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4597 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4598 and the target PC is in $2. */
4599 if (name
[19] >= '0' && name
[19] <= '9')
4600 return get_frame_register_signed (frame
, 2);
4602 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4603 before the jal instruction, this is effectively a call stub
4604 and the the target PC is in $2. Otherwise this is effectively
4605 a return stub and the target PC is in $18. */
4606 else if (name
[19] == 's' || name
[19] == 'd')
4608 if (pc
== start_addr
)
4610 /* Check if the target of the stub is a compiler-generated
4611 stub. Such a stub for a function bar might have a name
4612 like __fn_stub_bar, and might look like this:
4617 la $1,bar (becomes a lui/addiu pair)
4619 So scan down to the lui/addi and extract the target
4620 address from those two instructions. */
4622 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
4626 /* See if the name of the target function is __fn_stub_*. */
4627 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4630 if (strncmp (name
, "__fn_stub_", 10) != 0
4631 && strcmp (name
, "etext") != 0
4632 && strcmp (name
, "_etext") != 0)
4635 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4636 The limit on the search is arbitrarily set to 20
4637 instructions. FIXME. */
4638 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4640 inst
= mips_fetch_instruction (target_pc
);
4641 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4642 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4643 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4644 return pc
| (inst
& 0xffff); /* low word */
4647 /* Couldn't find the lui/addui pair, so return stub address. */
4651 /* This is the 'return' part of a call stub. The return
4652 address is in $r18. */
4653 return get_frame_register_signed (frame
, 18);
4656 return 0; /* not a stub */
4659 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4660 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4663 mips_stab_reg_to_regnum (int num
)
4666 if (num
>= 0 && num
< 32)
4668 else if (num
>= 38 && num
< 70)
4669 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4671 regnum
= mips_regnum (current_gdbarch
)->hi
;
4673 regnum
= mips_regnum (current_gdbarch
)->lo
;
4675 /* This will hopefully (eventually) provoke a warning. Should
4676 we be calling complaint() here? */
4677 return gdbarch_num_regs (current_gdbarch
)
4678 + gdbarch_num_pseudo_regs (current_gdbarch
);
4679 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4683 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4684 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4687 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4690 if (num
>= 0 && num
< 32)
4692 else if (num
>= 32 && num
< 64)
4693 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4695 regnum
= mips_regnum (current_gdbarch
)->hi
;
4697 regnum
= mips_regnum (current_gdbarch
)->lo
;
4699 /* This will hopefully (eventually) provoke a warning. Should we
4700 be calling complaint() here? */
4701 return gdbarch_num_regs (current_gdbarch
)
4702 + gdbarch_num_pseudo_regs (current_gdbarch
);
4703 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4707 mips_register_sim_regno (int regnum
)
4709 /* Only makes sense to supply raw registers. */
4710 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
));
4711 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4712 decide if it is valid. Should instead define a standard sim/gdb
4713 register numbering scheme. */
4714 if (gdbarch_register_name (current_gdbarch
,
4716 (current_gdbarch
) + regnum
) != NULL
4717 && gdbarch_register_name (current_gdbarch
,
4719 (current_gdbarch
) + regnum
)[0] != '\0')
4722 return LEGACY_SIM_REGNO_IGNORE
;
4726 /* Convert an integer into an address. Extracting the value signed
4727 guarantees a correctly sign extended address. */
4730 mips_integer_to_address (struct gdbarch
*gdbarch
,
4731 struct type
*type
, const gdb_byte
*buf
)
4733 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4737 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4739 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4740 const char *name
= bfd_get_section_name (abfd
, sect
);
4742 if (*abip
!= MIPS_ABI_UNKNOWN
)
4745 if (strncmp (name
, ".mdebug.", 8) != 0)
4748 if (strcmp (name
, ".mdebug.abi32") == 0)
4749 *abip
= MIPS_ABI_O32
;
4750 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4751 *abip
= MIPS_ABI_N32
;
4752 else if (strcmp (name
, ".mdebug.abi64") == 0)
4753 *abip
= MIPS_ABI_N64
;
4754 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4755 *abip
= MIPS_ABI_O64
;
4756 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4757 *abip
= MIPS_ABI_EABI32
;
4758 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4759 *abip
= MIPS_ABI_EABI64
;
4761 warning (_("unsupported ABI %s."), name
+ 8);
4765 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4767 int *lbp
= (int *) obj
;
4768 const char *name
= bfd_get_section_name (abfd
, sect
);
4770 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4772 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4774 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4775 warning (_("unrecognized .gcc_compiled_longXX"));
4778 static enum mips_abi
4779 global_mips_abi (void)
4783 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4784 if (mips_abi_strings
[i
] == mips_abi_string
)
4785 return (enum mips_abi
) i
;
4787 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4791 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4793 static struct target_desc
*tdesc_gp32
, *tdesc_gp64
;
4795 if (tdesc_gp32
== NULL
)
4797 /* Create feature sets with the appropriate properties. The values
4798 are not important. */
4800 tdesc_gp32
= allocate_target_description ();
4801 set_tdesc_property (tdesc_gp32
, PROPERTY_GP32
, "");
4803 tdesc_gp64
= allocate_target_description ();
4804 set_tdesc_property (tdesc_gp64
, PROPERTY_GP64
, "");
4807 /* If the size matches the set of 32-bit or 64-bit integer registers,
4808 assume that's what we've got. */
4809 register_remote_g_packet_guess (gdbarch
, 38 * 4, tdesc_gp32
);
4810 register_remote_g_packet_guess (gdbarch
, 38 * 8, tdesc_gp64
);
4812 /* If the size matches the full set of registers GDB traditionally
4813 knows about, including floating point, for either 32-bit or
4814 64-bit, assume that's what we've got. */
4815 register_remote_g_packet_guess (gdbarch
, 90 * 4, tdesc_gp32
);
4816 register_remote_g_packet_guess (gdbarch
, 90 * 8, tdesc_gp64
);
4818 /* Otherwise we don't have a useful guess. */
4821 static struct value
*
4822 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
4824 const int *reg_p
= baton
;
4825 return value_of_register (*reg_p
, frame
);
4828 static struct gdbarch
*
4829 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4831 struct gdbarch
*gdbarch
;
4832 struct gdbarch_tdep
*tdep
;
4834 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4836 enum mips_fpu_type fpu_type
;
4837 struct tdesc_arch_data
*tdesc_data
= NULL
;
4839 /* Check any target description for validity. */
4840 if (tdesc_has_registers (info
.target_desc
))
4842 static const char *const mips_gprs
[] = {
4843 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4844 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4845 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4846 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4848 static const char *const mips_fprs
[] = {
4849 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
4850 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
4851 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
4852 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
4855 const struct tdesc_feature
*feature
;
4858 feature
= tdesc_find_feature (info
.target_desc
,
4859 "org.gnu.gdb.mips.cpu");
4860 if (feature
== NULL
)
4863 tdesc_data
= tdesc_data_alloc ();
4866 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
4867 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
4871 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4872 MIPS_EMBED_LO_REGNUM
, "lo");
4873 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4874 MIPS_EMBED_HI_REGNUM
, "hi");
4875 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4876 MIPS_EMBED_PC_REGNUM
, "pc");
4880 tdesc_data_cleanup (tdesc_data
);
4884 feature
= tdesc_find_feature (info
.target_desc
,
4885 "org.gnu.gdb.mips.cp0");
4886 if (feature
== NULL
)
4888 tdesc_data_cleanup (tdesc_data
);
4893 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4894 MIPS_EMBED_BADVADDR_REGNUM
,
4896 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4897 MIPS_PS_REGNUM
, "status");
4898 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4899 MIPS_EMBED_CAUSE_REGNUM
, "cause");
4903 tdesc_data_cleanup (tdesc_data
);
4907 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
4908 backend is not prepared for that, though. */
4909 feature
= tdesc_find_feature (info
.target_desc
,
4910 "org.gnu.gdb.mips.fpu");
4911 if (feature
== NULL
)
4913 tdesc_data_cleanup (tdesc_data
);
4918 for (i
= 0; i
< 32; i
++)
4919 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4920 i
+ MIPS_EMBED_FP0_REGNUM
,
4923 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4924 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
4925 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4926 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
4930 tdesc_data_cleanup (tdesc_data
);
4934 /* It would be nice to detect an attempt to use a 64-bit ABI
4935 when only 32-bit registers are provided. */
4938 /* First of all, extract the elf_flags, if available. */
4939 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
4940 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
4941 else if (arches
!= NULL
)
4942 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
4946 fprintf_unfiltered (gdb_stdlog
,
4947 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
4949 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
4950 switch ((elf_flags
& EF_MIPS_ABI
))
4952 case E_MIPS_ABI_O32
:
4953 found_abi
= MIPS_ABI_O32
;
4955 case E_MIPS_ABI_O64
:
4956 found_abi
= MIPS_ABI_O64
;
4958 case E_MIPS_ABI_EABI32
:
4959 found_abi
= MIPS_ABI_EABI32
;
4961 case E_MIPS_ABI_EABI64
:
4962 found_abi
= MIPS_ABI_EABI64
;
4965 if ((elf_flags
& EF_MIPS_ABI2
))
4966 found_abi
= MIPS_ABI_N32
;
4968 found_abi
= MIPS_ABI_UNKNOWN
;
4972 /* GCC creates a pseudo-section whose name describes the ABI. */
4973 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
4974 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
4976 /* If we have no useful BFD information, use the ABI from the last
4977 MIPS architecture (if there is one). */
4978 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
4979 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
4981 /* Try the architecture for any hint of the correct ABI. */
4982 if (found_abi
== MIPS_ABI_UNKNOWN
4983 && info
.bfd_arch_info
!= NULL
4984 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4986 switch (info
.bfd_arch_info
->mach
)
4988 case bfd_mach_mips3900
:
4989 found_abi
= MIPS_ABI_EABI32
;
4991 case bfd_mach_mips4100
:
4992 case bfd_mach_mips5000
:
4993 found_abi
= MIPS_ABI_EABI64
;
4995 case bfd_mach_mips8000
:
4996 case bfd_mach_mips10000
:
4997 /* On Irix, ELF64 executables use the N64 ABI. The
4998 pseudo-sections which describe the ABI aren't present
4999 on IRIX. (Even for executables created by gcc.) */
5000 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5001 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5002 found_abi
= MIPS_ABI_N64
;
5004 found_abi
= MIPS_ABI_N32
;
5009 /* Default 64-bit objects to N64 instead of O32. */
5010 if (found_abi
== MIPS_ABI_UNKNOWN
5011 && info
.abfd
!= NULL
5012 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5013 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5014 found_abi
= MIPS_ABI_N64
;
5017 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5020 /* What has the user specified from the command line? */
5021 wanted_abi
= global_mips_abi ();
5023 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5026 /* Now that we have found what the ABI for this binary would be,
5027 check whether the user is overriding it. */
5028 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5029 mips_abi
= wanted_abi
;
5030 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5031 mips_abi
= found_abi
;
5033 mips_abi
= MIPS_ABI_O32
;
5035 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5038 /* Also used when doing an architecture lookup. */
5040 fprintf_unfiltered (gdb_stdlog
,
5041 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5042 mips64_transfers_32bit_regs_p
);
5044 /* Determine the MIPS FPU type. */
5045 if (!mips_fpu_type_auto
)
5046 fpu_type
= mips_fpu_type
;
5047 else if (info
.bfd_arch_info
!= NULL
5048 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5049 switch (info
.bfd_arch_info
->mach
)
5051 case bfd_mach_mips3900
:
5052 case bfd_mach_mips4100
:
5053 case bfd_mach_mips4111
:
5054 case bfd_mach_mips4120
:
5055 fpu_type
= MIPS_FPU_NONE
;
5057 case bfd_mach_mips4650
:
5058 fpu_type
= MIPS_FPU_SINGLE
;
5061 fpu_type
= MIPS_FPU_DOUBLE
;
5064 else if (arches
!= NULL
)
5065 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5067 fpu_type
= MIPS_FPU_DOUBLE
;
5069 fprintf_unfiltered (gdb_stdlog
,
5070 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5072 /* Check for blatant incompatibilities. */
5074 /* If we have only 32-bit registers, then we can't debug a 64-bit
5076 if (info
.target_desc
5077 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5078 && mips_abi
!= MIPS_ABI_EABI32
5079 && mips_abi
!= MIPS_ABI_O32
)
5081 if (tdesc_data
!= NULL
)
5082 tdesc_data_cleanup (tdesc_data
);
5086 /* try to find a pre-existing architecture */
5087 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5089 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5091 /* MIPS needs to be pedantic about which ABI the object is
5093 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5095 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5097 /* Need to be pedantic about which register virtual size is
5099 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5100 != mips64_transfers_32bit_regs_p
)
5102 /* Be pedantic about which FPU is selected. */
5103 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5106 if (tdesc_data
!= NULL
)
5107 tdesc_data_cleanup (tdesc_data
);
5108 return arches
->gdbarch
;
5111 /* Need a new architecture. Fill in a target specific vector. */
5112 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5113 gdbarch
= gdbarch_alloc (&info
, tdep
);
5114 tdep
->elf_flags
= elf_flags
;
5115 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5116 tdep
->found_abi
= found_abi
;
5117 tdep
->mips_abi
= mips_abi
;
5118 tdep
->mips_fpu_type
= fpu_type
;
5119 tdep
->register_size_valid_p
= 0;
5120 tdep
->register_size
= 0;
5122 if (info
.target_desc
)
5124 /* Some useful properties can be inferred from the target. */
5125 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5127 tdep
->register_size_valid_p
= 1;
5128 tdep
->register_size
= 4;
5130 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5132 tdep
->register_size_valid_p
= 1;
5133 tdep
->register_size
= 8;
5137 /* Initially set everything according to the default ABI/ISA. */
5138 set_gdbarch_short_bit (gdbarch
, 16);
5139 set_gdbarch_int_bit (gdbarch
, 32);
5140 set_gdbarch_float_bit (gdbarch
, 32);
5141 set_gdbarch_double_bit (gdbarch
, 64);
5142 set_gdbarch_long_double_bit (gdbarch
, 64);
5143 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5144 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5145 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5147 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5148 mips_elf_make_msymbol_special
);
5150 /* Fill in the OS dependant register numbers and names. */
5152 const char **reg_names
;
5153 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5154 struct mips_regnum
);
5155 if (tdesc_has_registers (info
.target_desc
))
5157 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5158 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5159 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5160 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5161 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5162 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5163 regnum
->fp_control_status
= 70;
5164 regnum
->fp_implementation_revision
= 71;
5165 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5168 else if (info
.osabi
== GDB_OSABI_IRIX
)
5173 regnum
->badvaddr
= 66;
5176 regnum
->fp_control_status
= 69;
5177 regnum
->fp_implementation_revision
= 70;
5179 reg_names
= mips_irix_reg_names
;
5183 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5184 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5185 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5186 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5187 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5188 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5189 regnum
->fp_control_status
= 70;
5190 regnum
->fp_implementation_revision
= 71;
5192 if (info
.bfd_arch_info
!= NULL
5193 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5194 reg_names
= mips_tx39_reg_names
;
5196 reg_names
= mips_generic_reg_names
;
5198 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5199 replaced by read_pc? */
5200 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5201 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5202 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5203 set_gdbarch_num_regs (gdbarch
, num_regs
);
5204 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5205 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5206 tdep
->mips_processor_reg_names
= reg_names
;
5207 tdep
->regnum
= regnum
;
5213 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5214 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5215 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5216 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5217 tdep
->default_mask_address_p
= 0;
5218 set_gdbarch_long_bit (gdbarch
, 32);
5219 set_gdbarch_ptr_bit (gdbarch
, 32);
5220 set_gdbarch_long_long_bit (gdbarch
, 64);
5223 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5224 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5225 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5226 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5227 tdep
->default_mask_address_p
= 0;
5228 set_gdbarch_long_bit (gdbarch
, 32);
5229 set_gdbarch_ptr_bit (gdbarch
, 32);
5230 set_gdbarch_long_long_bit (gdbarch
, 64);
5232 case MIPS_ABI_EABI32
:
5233 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5234 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5235 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5236 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5237 tdep
->default_mask_address_p
= 0;
5238 set_gdbarch_long_bit (gdbarch
, 32);
5239 set_gdbarch_ptr_bit (gdbarch
, 32);
5240 set_gdbarch_long_long_bit (gdbarch
, 64);
5242 case MIPS_ABI_EABI64
:
5243 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5244 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5245 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5246 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5247 tdep
->default_mask_address_p
= 0;
5248 set_gdbarch_long_bit (gdbarch
, 64);
5249 set_gdbarch_ptr_bit (gdbarch
, 64);
5250 set_gdbarch_long_long_bit (gdbarch
, 64);
5253 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5254 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5255 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5256 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5257 tdep
->default_mask_address_p
= 0;
5258 set_gdbarch_long_bit (gdbarch
, 32);
5259 set_gdbarch_ptr_bit (gdbarch
, 32);
5260 set_gdbarch_long_long_bit (gdbarch
, 64);
5261 set_gdbarch_long_double_bit (gdbarch
, 128);
5262 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5265 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5266 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5267 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5268 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5269 tdep
->default_mask_address_p
= 0;
5270 set_gdbarch_long_bit (gdbarch
, 64);
5271 set_gdbarch_ptr_bit (gdbarch
, 64);
5272 set_gdbarch_long_long_bit (gdbarch
, 64);
5273 set_gdbarch_long_double_bit (gdbarch
, 128);
5274 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5277 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5280 /* GCC creates a pseudo-section whose name specifies the size of
5281 longs, since -mlong32 or -mlong64 may be used independent of
5282 other options. How those options affect pointer sizes is ABI and
5283 architecture dependent, so use them to override the default sizes
5284 set by the ABI. This table shows the relationship between ABI,
5285 -mlongXX, and size of pointers:
5287 ABI -mlongXX ptr bits
5288 --- -------- --------
5302 Note that for o32 and eabi32, pointers are always 32 bits
5303 regardless of any -mlongXX option. For all others, pointers and
5304 longs are the same, as set by -mlongXX or set by defaults.
5307 if (info
.abfd
!= NULL
)
5311 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5314 set_gdbarch_long_bit (gdbarch
, long_bit
);
5318 case MIPS_ABI_EABI32
:
5323 case MIPS_ABI_EABI64
:
5324 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5327 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5332 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5333 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5336 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5337 flag in object files because to do so would make it impossible to
5338 link with libraries compiled without "-gp32". This is
5339 unnecessarily restrictive.
5341 We could solve this problem by adding "-gp32" multilibs to gcc,
5342 but to set this flag before gcc is built with such multilibs will
5343 break too many systems.''
5345 But even more unhelpfully, the default linker output target for
5346 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5347 for 64-bit programs - you need to change the ABI to change this,
5348 and not all gcc targets support that currently. Therefore using
5349 this flag to detect 32-bit mode would do the wrong thing given
5350 the current gcc - it would make GDB treat these 64-bit programs
5351 as 32-bit programs by default. */
5353 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5354 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5356 /* Add/remove bits from an address. The MIPS needs be careful to
5357 ensure that all 32 bit addresses are sign extended to 64 bits. */
5358 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5360 /* Unwind the frame. */
5361 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5362 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5363 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5365 /* Map debug register numbers onto internal register numbers. */
5366 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5367 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5368 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5369 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5370 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5371 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5372 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5373 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5375 /* MIPS version of CALL_DUMMY */
5377 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5378 replaced by a command, and all targets will default to on stack
5379 (regardless of the stack's execute status). */
5380 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5381 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5383 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5384 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5385 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5387 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5388 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5390 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5392 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5393 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5394 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5396 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5398 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5400 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5402 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5403 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5404 need to all be folded into the target vector. Since they are
5405 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5406 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5408 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5410 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5412 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5414 /* Virtual tables. */
5415 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5417 mips_register_g_packet_guesses (gdbarch
);
5419 /* Hook in OS ABI-specific overrides, if they have been registered. */
5420 info
.tdep_info
= (void *) tdesc_data
;
5421 gdbarch_init_osabi (info
, gdbarch
);
5423 /* Unwind the frame. */
5424 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5425 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5426 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5427 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5428 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5429 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5430 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5431 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5435 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5436 tdesc_use_registers (gdbarch
, tdesc_data
);
5438 /* Override the normal target description methods to handle our
5439 dual real and pseudo registers. */
5440 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5441 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5443 num_regs
= gdbarch_num_regs (gdbarch
);
5444 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5445 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5446 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5449 /* Add ABI-specific aliases for the registers. */
5450 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5451 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5452 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5453 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5455 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5456 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5457 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5459 /* Add some other standard aliases. */
5460 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5461 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5462 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5468 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5470 struct gdbarch_info info
;
5472 /* Force the architecture to update, and (if it's a MIPS architecture)
5473 mips_gdbarch_init will take care of the rest. */
5474 gdbarch_info_init (&info
);
5475 gdbarch_update_p (info
);
5478 /* Print out which MIPS ABI is in use. */
5481 show_mips_abi (struct ui_file
*file
,
5483 struct cmd_list_element
*ignored_cmd
,
5484 const char *ignored_value
)
5486 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5489 "The MIPS ABI is unknown because the current architecture "
5493 enum mips_abi global_abi
= global_mips_abi ();
5494 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5495 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5497 if (global_abi
== MIPS_ABI_UNKNOWN
)
5500 "The MIPS ABI is set automatically (currently \"%s\").\n",
5502 else if (global_abi
== actual_abi
)
5505 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5509 /* Probably shouldn't happen... */
5512 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5513 actual_abi_str
, mips_abi_strings
[global_abi
]);
5519 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5521 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5525 int ef_mips_32bitmode
;
5526 /* Determine the ISA. */
5527 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5545 /* Determine the size of a pointer. */
5546 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5547 fprintf_unfiltered (file
,
5548 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5550 fprintf_unfiltered (file
,
5551 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5553 fprintf_unfiltered (file
,
5554 "mips_dump_tdep: ef_mips_arch = %d\n",
5556 fprintf_unfiltered (file
,
5557 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5558 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5559 fprintf_unfiltered (file
,
5560 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5561 mips_mask_address_p (tdep
),
5562 tdep
->default_mask_address_p
);
5564 fprintf_unfiltered (file
,
5565 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5566 MIPS_DEFAULT_FPU_TYPE
,
5567 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5568 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5569 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5571 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5572 fprintf_unfiltered (file
,
5573 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5575 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5576 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5577 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5581 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5584 _initialize_mips_tdep (void)
5586 static struct cmd_list_element
*mipsfpulist
= NULL
;
5587 struct cmd_list_element
*c
;
5589 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5590 if (MIPS_ABI_LAST
+ 1
5591 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5592 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5594 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5596 mips_pdr_data
= register_objfile_data ();
5598 /* Add root prefix command for all "set mips"/"show mips" commands */
5599 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5600 _("Various MIPS specific commands."),
5601 &setmipscmdlist
, "set mips ", 0, &setlist
);
5603 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5604 _("Various MIPS specific commands."),
5605 &showmipscmdlist
, "show mips ", 0, &showlist
);
5607 /* Allow the user to override the ABI. */
5608 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5609 &mips_abi_string
, _("\
5610 Set the MIPS ABI used by this program."), _("\
5611 Show the MIPS ABI used by this program."), _("\
5612 This option can be set to one of:\n\
5613 auto - the default ABI associated with the current binary\n\
5622 &setmipscmdlist
, &showmipscmdlist
);
5624 /* Let the user turn off floating point and set the fence post for
5625 heuristic_proc_start. */
5627 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5628 _("Set use of MIPS floating-point coprocessor."),
5629 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5630 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5631 _("Select single-precision MIPS floating-point coprocessor."),
5633 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5634 _("Select double-precision MIPS floating-point coprocessor."),
5636 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5637 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5638 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5639 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5640 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5641 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5642 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5643 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5644 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5645 _("Select MIPS floating-point coprocessor automatically."),
5647 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5648 _("Show current use of MIPS floating-point coprocessor target."),
5651 /* We really would like to have both "0" and "unlimited" work, but
5652 command.c doesn't deal with that. So make it a var_zinteger
5653 because the user can always use "999999" or some such for unlimited. */
5654 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5655 &heuristic_fence_post
, _("\
5656 Set the distance searched for the start of a function."), _("\
5657 Show the distance searched for the start of a function."), _("\
5658 If you are debugging a stripped executable, GDB needs to search through the\n\
5659 program for the start of a function. This command sets the distance of the\n\
5660 search. The only need to set it is when debugging a stripped executable."),
5661 reinit_frame_cache_sfunc
,
5662 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5663 &setlist
, &showlist
);
5665 /* Allow the user to control whether the upper bits of 64-bit
5666 addresses should be zeroed. */
5667 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5668 &mask_address_var
, _("\
5669 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5670 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5671 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5672 allow GDB to determine the correct value."),
5673 NULL
, show_mask_address
,
5674 &setmipscmdlist
, &showmipscmdlist
);
5676 /* Allow the user to control the size of 32 bit registers within the
5677 raw remote packet. */
5678 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5679 &mips64_transfers_32bit_regs_p
, _("\
5680 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5682 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5684 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5685 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5686 64 bits for others. Use \"off\" to disable compatibility mode"),
5687 set_mips64_transfers_32bit_regs
,
5688 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5689 &setlist
, &showlist
);
5691 /* Debug this files internals. */
5692 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5694 Set mips debugging."), _("\
5695 Show mips debugging."), _("\
5696 When non-zero, mips specific debugging is enabled."),
5698 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5699 &setdebuglist
, &showdebuglist
);