1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* FIXME: Put this declaration in frame.h. */
42 extern struct obstack frame_cache_obstack
;
44 /* FIXME! this code assumes 4-byte instructions. */
45 #define MIPS_INSTLEN 4 /* Length of an instruction */
46 #define MIPS16_INSTLEN 2 /* Length of an instruction on MIPS16*/
47 #define MIPS_NUMREGS 32 /* Number of integer or float registers */
48 typedef unsigned long t_inst
; /* Integer big enough to hold an instruction */
51 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
54 static int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
56 static void mips_print_register
PARAMS ((int, int));
58 static mips_extra_func_info_t
59 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
61 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
63 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
65 static void mips_set_fpu_command
PARAMS ((char *, int,
66 struct cmd_list_element
*));
68 static void mips_show_fpu_command
PARAMS ((char *, int,
69 struct cmd_list_element
*));
71 void mips_set_processor_type_command
PARAMS ((char *, int));
73 int mips_set_processor_type
PARAMS ((char *));
75 static void mips_show_processor_type_command
PARAMS ((char *, int));
77 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
78 struct cmd_list_element
*));
80 static mips_extra_func_info_t
81 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
83 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
84 mips_extra_func_info_t proc_desc
));
86 /* This value is the model of MIPS in use. It is derived from the value
87 of the PrID register. */
89 char *mips_processor_type
;
91 char *tmp_mips_processor_type
;
93 /* Some MIPS boards don't support floating point, so we permit the
94 user to turn it off. */
96 enum mips_fpu_type mips_fpu
;
98 static char *mips_fpu_string
;
100 /* A set of original names, to be used when restoring back to generic
101 registers from a specific set. */
103 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
105 /* Names of IDT R3041 registers. */
107 char *mips_r3041_reg_names
[] = {
108 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
109 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
110 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
111 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
112 "sr", "lo", "hi", "bad", "cause","pc",
113 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
114 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
115 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
116 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
117 "fsr", "fir", "fp", "",
118 "", "", "bus", "ccfg", "", "", "", "",
119 "", "", "port", "cmp", "", "", "epc", "prid",
122 /* Names of IDT R3051 registers. */
124 char *mips_r3051_reg_names
[] = {
125 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
126 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
127 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
128 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
129 "sr", "lo", "hi", "bad", "cause","pc",
130 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
131 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
132 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
133 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
134 "fsr", "fir", "fp", "",
135 "inx", "rand", "elo", "", "ctxt", "", "", "",
136 "", "", "ehi", "", "", "", "epc", "prid",
139 /* Names of IDT R3081 registers. */
141 char *mips_r3081_reg_names
[] = {
142 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
143 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
144 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
145 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
146 "sr", "lo", "hi", "bad", "cause","pc",
147 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
148 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
149 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
150 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
151 "fsr", "fir", "fp", "",
152 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
153 "", "", "ehi", "", "", "", "epc", "prid",
156 /* Names of LSI 33k registers. */
158 char *mips_lsi33k_reg_names
[] = {
159 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
160 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
161 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
162 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
163 "epc", "hi", "lo", "sr", "cause","badvaddr",
164 "dcic", "bpc", "bda", "", "", "", "", "",
165 "", "", "", "", "", "", "", "",
166 "", "", "", "", "", "", "", "",
167 "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "",
170 "", "", "", "", "", "", "", "",
176 } mips_processor_type_table
[] = {
177 { "generic", mips_generic_reg_names
},
178 { "r3041", mips_r3041_reg_names
},
179 { "r3051", mips_r3051_reg_names
},
180 { "r3071", mips_r3081_reg_names
},
181 { "r3081", mips_r3081_reg_names
},
182 { "lsi33k", mips_lsi33k_reg_names
},
186 /* Table to translate MIPS16 register field to actual register number. */
187 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
189 /* Heuristic_proc_start may hunt through the text section for a long
190 time across a 2400 baud serial line. Allows the user to limit this
193 static unsigned int heuristic_fence_post
= 0;
195 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
196 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
197 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
198 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
199 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
200 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
201 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
202 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
203 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
204 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
205 #define _PROC_MAGIC_ 0x0F0F0F0F
206 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
207 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
209 struct linked_proc_info
211 struct mips_extra_func_info info
;
212 struct linked_proc_info
*next
;
213 } *linked_proc_desc_table
= NULL
;
216 /* This returns the PC of the first inst after the prologue. If we can't
217 find the prologue, then return 0. */
220 after_prologue (pc
, proc_desc
)
222 mips_extra_func_info_t proc_desc
;
224 struct symtab_and_line sal
;
225 CORE_ADDR func_addr
, func_end
;
228 proc_desc
= find_proc_desc (pc
, NULL
);
232 /* If function is frameless, then we need to do it the hard way. I
233 strongly suspect that frameless always means prologueless... */
234 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
235 && PROC_FRAME_OFFSET (proc_desc
) == 0)
239 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
240 return 0; /* Unknown */
242 sal
= find_pc_line (func_addr
, 0);
244 if (sal
.end
< func_end
)
247 /* The line after the prologue is after the end of the function. In this
248 case, tell the caller to find the prologue the hard way. */
253 /* Decode a MIPS32 instruction that saves a register in the stack, and
254 set the appropriate bit in the general register mask or float register mask
255 to indicate which register is saved. This is a helper function
256 for mips_find_saved_regs. */
259 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
261 unsigned long *gen_mask
;
262 unsigned long *float_mask
;
266 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
267 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
268 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
270 /* It might be possible to use the instruction to
271 find the offset, rather than the code below which
272 is based on things being in a certain order in the
273 frame, but figuring out what the instruction's offset
274 is relative to might be a little tricky. */
275 reg
= (inst
& 0x001f0000) >> 16;
276 *gen_mask
|= (1 << reg
);
278 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
279 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
280 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
283 reg
= ((inst
& 0x001f0000) >> 16);
284 *float_mask
|= (1 << reg
);
288 /* Decode a MIPS16 instruction that saves a register in the stack, and
289 set the appropriate bit in the general register or float register mask
290 to indicate which register is saved. This is a helper function
291 for mips_find_saved_regs. */
294 mips16_decode_reg_save (inst
, gen_mask
)
296 unsigned long *gen_mask
;
298 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
300 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
301 *gen_mask
|= (1 << reg
);
303 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
305 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
306 *gen_mask
|= (1 << reg
);
308 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
309 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
310 *gen_mask
|= (1 << 31);
313 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
317 mips_find_saved_regs (fci
)
318 struct frame_info
*fci
;
321 CORE_ADDR reg_position
;
322 /* r0 bit means kernel trap */
324 /* What registers have been saved? Bitmasks. */
325 unsigned long gen_mask
, float_mask
;
326 mips_extra_func_info_t proc_desc
;
328 fci
->saved_regs
= (struct frame_saved_regs
*)
329 obstack_alloc (&frame_cache_obstack
, sizeof(struct frame_saved_regs
));
330 memset (fci
->saved_regs
, 0, sizeof (struct frame_saved_regs
));
332 /* If it is the frame for sigtramp, the saved registers are located
333 in a sigcontext structure somewhere on the stack.
334 If the stack layout for sigtramp changes we might have to change these
335 constants and the companion fixup_sigtramp in mdebugread.c */
336 #ifndef SIGFRAME_BASE
337 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
338 above the sigtramp frame. */
339 #define SIGFRAME_BASE MIPS_REGSIZE
340 /* FIXME! Are these correct?? */
341 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
342 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
343 #define SIGFRAME_FPREGSAVE_OFF \
344 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
346 #ifndef SIGFRAME_REG_SIZE
347 /* FIXME! Is this correct?? */
348 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
350 if (fci
->signal_handler_caller
)
352 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
354 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
355 + ireg
* SIGFRAME_REG_SIZE
;
356 fci
->saved_regs
->regs
[ireg
] = reg_position
;
358 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
360 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
361 + ireg
* SIGFRAME_REG_SIZE
;
362 fci
->saved_regs
->regs
[FP0_REGNUM
+ ireg
] = reg_position
;
364 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
368 proc_desc
= fci
->proc_desc
;
369 if (proc_desc
== NULL
)
370 /* I'm not sure how/whether this can happen. Normally when we can't
371 find a proc_desc, we "synthesize" one using heuristic_proc_desc
372 and set the saved_regs right away. */
375 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
376 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
377 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
379 if (/* In any frame other than the innermost or a frame interrupted by
380 a signal, we assume that all registers have been saved.
381 This assumes that all register saves in a function happen before
382 the first function call. */
383 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
385 /* In a dummy frame we know exactly where things are saved. */
386 && !PROC_DESC_IS_DUMMY (proc_desc
)
388 /* Don't bother unless we are inside a function prologue. Outside the
389 prologue, we know where everything is. */
391 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
393 /* Not sure exactly what kernel_trap means, but if it means
394 the kernel saves the registers without a prologue doing it,
395 we better not examine the prologue to see whether registers
396 have been saved yet. */
399 /* We need to figure out whether the registers that the proc_desc
400 claims are saved have been saved yet. */
404 char buf
[MIPS_INSTLEN
];
408 /* Bitmasks; set if we have found a save for the register. */
409 unsigned long gen_save_found
= 0;
410 unsigned long float_save_found
= 0;
412 if ((addr
= PROC_LOW_ADDR (proc_desc
)) & 1)
414 instlen
= MIPS16_INSTLEN
; /* MIPS16 */
418 instlen
= MIPS_INSTLEN
; /* MIPS32 */
420 /* Scan through this function's instructions preceding the current
421 PC, and look for those that save registers. */
422 while (addr
< fci
->pc
)
424 status
= read_memory_nobpt (addr
, buf
, instlen
);
426 memory_error (status
, addr
);
427 inst
= extract_unsigned_integer (buf
, instlen
);
428 if (instlen
== MIPS16_INSTLEN
)
429 mips16_decode_reg_save (inst
, &gen_save_found
);
431 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
434 gen_mask
= gen_save_found
;
435 float_mask
= float_save_found
;
438 /* Fill in the offsets for the registers which gen_mask says
440 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
441 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
442 if (gen_mask
& 0x80000000)
444 fci
->saved_regs
->regs
[ireg
] = reg_position
;
445 reg_position
-= MIPS_REGSIZE
;
447 /* Fill in the offsets for the registers which float_mask says
449 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
451 /* The freg_offset points to where the first *double* register
452 is saved. So skip to the high-order word. */
453 if (! GDB_TARGET_IS_MIPS64
)
456 /* Fill in the offsets for the float registers which float_mask says
458 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
459 if (float_mask
& 0x80000000)
461 fci
->saved_regs
->regs
[FP0_REGNUM
+ireg
] = reg_position
;
462 reg_position
-= MIPS_REGSIZE
;
465 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->saved_regs
->regs
[RA_REGNUM
];
469 read_next_frame_reg(fi
, regno
)
470 struct frame_info
*fi
;
473 for (; fi
; fi
= fi
->next
)
475 /* We have to get the saved sp from the sigcontext
476 if it is a signal handler frame. */
477 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
481 if (fi
->saved_regs
== NULL
)
482 mips_find_saved_regs (fi
);
483 if (fi
->saved_regs
->regs
[regno
])
484 return read_memory_integer(fi
->saved_regs
->regs
[regno
], MIPS_REGSIZE
);
487 return read_register (regno
);
490 /* mips_addr_bits_remove - remove useless address bits */
493 mips_addr_bits_remove (addr
)
496 #if GDB_TARGET_IS_MIPS64
497 if ((addr
>> 32 == (CORE_ADDR
)0xffffffff)
498 && (strcmp(target_shortname
,"pmon")==0
499 || strcmp(target_shortname
,"ddb")==0
500 || strcmp(target_shortname
,"sim")==0))
502 /* This hack is a work-around for existing boards using PMON,
503 the simulator, and any other 64-bit targets that doesn't have
504 true 64-bit addressing. On these targets, the upper 32 bits
505 of addresses are ignored by the hardware. Thus, the PC or SP
506 are likely to have been sign extended to all 1s by instruction
507 sequences that load 32-bit addresses. For example, a typical
508 piece of code that loads an address is this:
509 lui $r2, <upper 16 bits>
510 ori $r2, <lower 16 bits>
511 But the lui sign-extends the value such that the upper 32 bits
512 may be all 1s. The workaround is simply to mask off these bits.
513 In the future, gcc may be changed to support true 64-bit
514 addressing, and this masking will have to be disabled. */
515 addr
&= (CORE_ADDR
)0xffffffff;
518 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
519 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
520 So we still have to mask off useless bits from addresses. */
521 addr
&= (CORE_ADDR
)0xffffffff;
528 mips_frame_saved_pc(frame
)
529 struct frame_info
*frame
;
532 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
533 /* We have to get the saved pc from the sigcontext
534 if it is a signal handler frame. */
535 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
536 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
538 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
539 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
541 saved_pc
= read_next_frame_reg(frame
, pcreg
);
543 return ADDR_BITS_REMOVE (saved_pc
);
546 static struct mips_extra_func_info temp_proc_desc
;
547 static struct frame_saved_regs temp_saved_regs
;
549 /* This fencepost looks highly suspicious to me. Removing it also
550 seems suspicious as it could affect remote debugging across serial
554 heuristic_proc_start(pc
)
562 pc
= ADDR_BITS_REMOVE (pc
);
564 fence
= start_pc
- heuristic_fence_post
;
565 if (start_pc
== 0) return 0;
567 if (heuristic_fence_post
== UINT_MAX
568 || fence
< VM_MIN_ADDRESS
)
569 fence
= VM_MIN_ADDRESS
;
571 instlen
= pc
& 1 ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
573 /* search back for previous return */
574 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
575 if (start_pc
< fence
)
577 /* It's not clear to me why we reach this point when
578 stop_soon_quietly, but with this test, at least we
579 don't print out warnings for every child forked (eg, on
580 decstation). 22apr93 rich@cygnus.com. */
581 if (!stop_soon_quietly
)
583 static int blurb_printed
= 0;
585 if (fence
== VM_MIN_ADDRESS
)
586 warning("Hit beginning of text section without finding");
588 warning("Hit heuristic-fence-post without finding");
590 warning("enclosing function for address 0x%s", paddr (pc
));
594 This warning occurs if you are debugging a function without any symbols\n\
595 (for example, in a stripped executable). In that case, you may wish to\n\
596 increase the size of the search with the `set heuristic-fence-post' command.\n\
598 Otherwise, you told GDB there was a function where there isn't one, or\n\
599 (more likely) you have encountered a bug in GDB.\n");
606 else if (start_pc
& 1)
608 /* On MIPS16, any one of the following is likely to be the
613 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
614 unsigned short inst
= read_memory_integer (start_pc
& ~1, 2);
615 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
616 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
617 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
618 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
620 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
621 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
626 else if (ABOUT_TO_RETURN(start_pc
))
628 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
633 /* skip nops (usually 1) 0 - is this */
634 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
635 start_pc
+= MIPS_INSTLEN
;
640 /* Fetch the immediate value from the current instruction.
641 If the previous instruction was an EXTEND, use it to extend
642 the upper bits of the immediate value. This is a helper function
643 for mips16_heuristic_proc_desc. */
646 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
647 unsigned short prev_inst
; /* previous instruction */
648 unsigned short inst
; /* current current instruction */
649 int nbits
; /* number of bits in imm field */
650 int scale
; /* scale factor to be applied to imm */
651 int is_signed
; /* is the imm field signed? */
655 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
657 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
658 if (offset
& 0x8000) /* check for negative extend */
659 offset
= 0 - (0x10000 - (offset
& 0xffff));
660 return offset
| (inst
& 0x1f);
664 int max_imm
= 1 << nbits
;
665 int mask
= max_imm
- 1;
666 int sign_bit
= max_imm
>> 1;
668 offset
= inst
& mask
;
669 if (is_signed
&& (offset
& sign_bit
))
670 offset
= 0 - (max_imm
- offset
);
671 return offset
* scale
;
676 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
677 stream from start_pc to limit_pc. */
680 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
681 CORE_ADDR start_pc
, limit_pc
;
682 struct frame_info
*next_frame
;
686 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
687 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
688 unsigned inst
= 0; /* current instruction */
690 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
692 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
694 char buf
[MIPS16_INSTLEN
];
695 int status
, reg
, offset
;
697 /* Save the previous instruction. If it's an EXTEND, we'll extract
698 the immediate offset extension from it in mips16_get_imm. */
701 /* Fetch the instruction. */
702 status
= read_memory_nobpt (cur_pc
& ~1, buf
, MIPS16_INSTLEN
);
703 if (status
) memory_error (status
, cur_pc
);
704 inst
= (unsigned short) extract_unsigned_integer (buf
, MIPS16_INSTLEN
);
706 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
707 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
709 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
710 if (offset
< 0) /* negative stack adjustment? */
711 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
713 /* Exit loop if a positive stack adjustment is found, which
714 usually means that the stack cleanup code in the function
715 epilogue is reached. */
718 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
720 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
721 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
722 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
723 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
725 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
727 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
728 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
729 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
730 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
732 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
734 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
735 PROC_REG_MASK(&temp_proc_desc
) |= (1 << 31);
736 temp_saved_regs
.regs
[31] = sp
+ offset
;
738 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
740 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
741 PROC_REG_MASK(&temp_proc_desc
) |= (1 << 31);
742 temp_saved_regs
.regs
[31] = sp
+ offset
;
744 else if (inst
== 0x673d) /* move $s1, $sp */
746 frame_addr
= read_next_frame_reg(next_frame
, 30);
747 PROC_FRAME_REG (&temp_proc_desc
) = 17;
749 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
751 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
752 frame_addr
= sp
+ offset
;
753 PROC_FRAME_REG (&temp_proc_desc
) = 17;
755 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
757 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
758 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
759 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
760 temp_saved_regs
.regs
[reg
] = frame_addr
+ offset
;
762 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
764 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
765 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
766 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
767 temp_saved_regs
.regs
[reg
] = frame_addr
+ offset
;
769 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
771 int areg_count
= (inst
>> 8) & 7;
772 int sreg_count
= (inst
>> 6) & 3;
774 /* The entry instruction always subtracts 32 from the SP. */
775 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
777 /* Check if a0-a3 were saved in the caller's argument save area. */
778 for (reg
= 4, offset
= 32; reg
< areg_count
+4; reg
++, offset
+= 4)
780 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
781 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
784 /* Check if the ra register was pushed on the stack. */
788 PROC_REG_MASK(&temp_proc_desc
) |= 1 << 31;
789 temp_saved_regs
.regs
[31] = sp
+ offset
;
793 /* Check if the s0 and s1 registers were pushed on the stack. */
794 for (reg
= 16; reg
< sreg_count
+16; reg
++, offset
-= 4)
796 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
797 temp_saved_regs
.regs
[reg
] = sp
+ offset
;
800 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
801 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
806 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
807 CORE_ADDR start_pc
, limit_pc
;
808 struct frame_info
*next_frame
;
812 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
814 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
815 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
817 char buf
[MIPS_INSTLEN
];
818 unsigned long inst
, high_word
, low_word
;
821 /* Fetch the instruction. */
822 status
= (unsigned long) read_memory_nobpt (cur_pc
, buf
, MIPS_INSTLEN
);
823 if (status
) memory_error (status
, cur_pc
);
824 inst
= (unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
);
826 /* Save some code by pre-extracting some useful fields. */
827 high_word
= (inst
>> 16) & 0xffff;
828 low_word
= inst
& 0xffff;
829 reg
= high_word
& 0x1f;
831 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
832 || high_word
== 0x23bd /* addi $sp,$sp,-i */
833 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
835 if (low_word
& 0x8000) /* negative stack adjustment? */
836 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
838 /* Exit loop if a positive stack adjustment is found, which
839 usually means that the stack cleanup code in the function
840 epilogue is reached. */
843 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
845 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
846 temp_saved_regs
.regs
[reg
] = sp
+ low_word
;
848 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
850 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
851 but the register size used is only 32 bits. Make the address
852 for the saved register point to the lower 32 bits. */
853 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
854 temp_saved_regs
.regs
[reg
] = sp
+ low_word
+ 8 - MIPS_REGSIZE
;
856 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
858 /* Old gcc frame, r30 is virtual frame pointer. */
859 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
860 frame_addr
= sp
+ low_word
;
861 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
863 unsigned alloca_adjust
;
864 PROC_FRAME_REG (&temp_proc_desc
) = 30;
865 frame_addr
= read_next_frame_reg(next_frame
, 30);
866 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
867 if (alloca_adjust
> 0)
869 /* FP > SP + frame_size. This may be because
870 * of an alloca or somethings similar.
871 * Fix sp to "pre-alloca" value, and try again.
878 /* move $30,$sp. With different versions of gas this will be either
879 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
880 Accept any one of these. */
881 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
883 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
884 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
886 unsigned alloca_adjust
;
887 PROC_FRAME_REG (&temp_proc_desc
) = 30;
888 frame_addr
= read_next_frame_reg(next_frame
, 30);
889 alloca_adjust
= (unsigned)(frame_addr
- sp
);
890 if (alloca_adjust
> 0)
892 /* FP > SP + frame_size. This may be because
893 * of an alloca or somethings similar.
894 * Fix sp to "pre-alloca" value, and try again.
901 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
903 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
904 temp_saved_regs
.regs
[reg
] = frame_addr
+ low_word
;
909 static mips_extra_func_info_t
910 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
911 CORE_ADDR start_pc
, limit_pc
;
912 struct frame_info
*next_frame
;
914 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
916 if (start_pc
== 0) return NULL
;
917 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
918 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
919 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
920 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
921 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
923 if (start_pc
+ 200 < limit_pc
)
924 limit_pc
= start_pc
+ 200;
926 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
928 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
929 return &temp_proc_desc
;
932 static mips_extra_func_info_t
933 find_proc_desc (pc
, next_frame
)
935 struct frame_info
*next_frame
;
937 mips_extra_func_info_t proc_desc
;
938 struct block
*b
= block_for_pc(pc
);
942 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
943 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
947 if (startaddr
> BLOCK_START (b
))
948 /* This is the "pathological" case referred to in a comment in
949 print_frame_info. It might be better to move this check into
953 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
,
957 /* If we never found a PDR for this function in symbol reading, then
958 examine prologues to find the information. */
959 if (sym
&& ((mips_extra_func_info_t
) SYMBOL_VALUE (sym
))->pdr
.framereg
== -1)
964 /* IF this is the topmost frame AND
965 * (this proc does not have debugging information OR
966 * the PC is in the procedure prologue)
967 * THEN create a "heuristic" proc_desc (by analyzing
968 * the actual code) to replace the "official" proc_desc.
970 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
971 if (next_frame
== NULL
) {
972 struct symtab_and_line val
;
973 struct symbol
*proc_symbol
=
974 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
977 val
= find_pc_line (BLOCK_START
978 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
980 val
.pc
= val
.end
? val
.end
: pc
;
982 if (!proc_symbol
|| pc
< val
.pc
) {
983 mips_extra_func_info_t found_heuristic
=
984 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
987 proc_desc
= found_heuristic
;
993 /* Is linked_proc_desc_table really necessary? It only seems to be used
994 by procedure call dummys. However, the procedures being called ought
995 to have their own proc_descs, and even if they don't,
996 heuristic_proc_desc knows how to create them! */
998 register struct linked_proc_info
*link
;
1000 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1001 if (PROC_LOW_ADDR(&link
->info
) <= pc
1002 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1006 startaddr
= heuristic_proc_start (pc
);
1009 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1015 get_frame_pointer(frame
, proc_desc
)
1016 struct frame_info
*frame
;
1017 mips_extra_func_info_t proc_desc
;
1019 return ADDR_BITS_REMOVE (read_next_frame_reg (frame
,
1020 PROC_FRAME_REG(proc_desc
)) + PROC_FRAME_OFFSET(proc_desc
));
1023 mips_extra_func_info_t cached_proc_desc
;
1026 mips_frame_chain(frame
)
1027 struct frame_info
*frame
;
1029 mips_extra_func_info_t proc_desc
;
1030 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1032 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1035 proc_desc
= find_proc_desc(saved_pc
, frame
);
1039 cached_proc_desc
= proc_desc
;
1041 /* If no frame pointer and frame size is zero, we must be at end
1042 of stack (or otherwise hosed). If we don't check frame size,
1043 we loop forever if we see a zero size frame. */
1044 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1045 && PROC_FRAME_OFFSET (proc_desc
) == 0
1046 /* The previous frame from a sigtramp frame might be frameless
1047 and have frame size zero. */
1048 && !frame
->signal_handler_caller
)
1051 return get_frame_pointer (frame
, proc_desc
);
1055 init_extra_frame_info(fci
)
1056 struct frame_info
*fci
;
1060 /* Use proc_desc calculated in frame_chain */
1061 mips_extra_func_info_t proc_desc
=
1062 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1064 fci
->saved_regs
= NULL
;
1066 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1069 /* Fixup frame-pointer - only needed for top frame */
1070 /* This may not be quite right, if proc has a real frame register.
1071 Get the value of the frame relative sp, procedure might have been
1072 interrupted by a signal at it's very start. */
1073 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1074 && !PROC_DESC_IS_DUMMY (proc_desc
))
1075 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1077 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1079 if (proc_desc
== &temp_proc_desc
)
1083 /* Do not set the saved registers for a sigtramp frame,
1084 mips_find_saved_registers will do that for us.
1085 We can't use fci->signal_handler_caller, it is not yet set. */
1086 find_pc_partial_function (fci
->pc
, &name
,
1087 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1088 if (!IN_SIGTRAMP (fci
->pc
, name
))
1090 fci
->saved_regs
= (struct frame_saved_regs
*)
1091 obstack_alloc (&frame_cache_obstack
,
1092 sizeof (struct frame_saved_regs
));
1093 *fci
->saved_regs
= temp_saved_regs
;
1094 fci
->saved_regs
->regs
[PC_REGNUM
]
1095 = fci
->saved_regs
->regs
[RA_REGNUM
];
1099 /* hack: if argument regs are saved, guess these contain args */
1100 fci
->num_args
= -1; /* assume we can't tell how many args for now */
1101 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1103 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1105 fci
->num_args
= regnum
- A0_REGNUM
+ 1;
1112 /* MIPS stack frames are almost impenetrable. When execution stops,
1113 we basically have to look at symbol information for the function
1114 that we stopped in, which tells us *which* register (if any) is
1115 the base of the frame pointer, and what offset from that register
1116 the frame itself is at.
1118 This presents a problem when trying to examine a stack in memory
1119 (that isn't executing at the moment), using the "frame" command. We
1120 don't have a PC, nor do we have any registers except SP.
1122 This routine takes two arguments, SP and PC, and tries to make the
1123 cached frames look as if these two arguments defined a frame on the
1124 cache. This allows the rest of info frame to extract the important
1125 arguments without difficulty. */
1128 setup_arbitrary_frame (argc
, argv
)
1133 error ("MIPS frame specifications require two arguments: sp and pc");
1135 return create_new_frame (argv
[0], argv
[1]);
1139 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1144 CORE_ADDR struct_addr
;
1152 /* Macros to round N up or down to the next A boundary; A must be
1154 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1155 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1157 /* First ensure that the stack and structure return address (if any)
1158 are properly aligned. The stack has to be 64-bit aligned even
1159 on 32-bit machines, because doubles must be 64-bit aligned. */
1160 sp
= ROUND_DOWN (sp
, 8);
1161 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_REGSIZE
);
1163 /* Now make space on the stack for the args. We allocate more
1164 than necessary for EABI, because the first few arguments are
1165 passed in registers, but that's OK. */
1166 for (argnum
= 0; argnum
< nargs
; argnum
++)
1167 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_REGSIZE
);
1168 sp
-= ROUND_UP (len
, 8);
1170 /* Initialize the integer and float register pointers. */
1172 float_argreg
= FPA0_REGNUM
;
1174 /* the struct_return pointer occupies the first parameter-passing reg */
1176 write_register (argreg
++, struct_addr
);
1178 /* The offset onto the stack at which we will start copying parameters
1179 (after the registers are used up) begins at 16 in the old ABI.
1180 This leaves room for the "home" area for register parameters. */
1181 stack_offset
= MIPS_EABI
? 0 : MIPS_REGSIZE
* 4;
1183 /* Now load as many as possible of the first arguments into
1184 registers, and push the rest onto the stack. Loop thru args
1185 from first to last. */
1186 for (argnum
= 0; argnum
< nargs
; argnum
++)
1189 char valbuf
[REGISTER_RAW_SIZE(A0_REGNUM
)];
1190 value_ptr arg
= args
[argnum
];
1191 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1192 int len
= TYPE_LENGTH (arg_type
);
1193 enum type_code typecode
= TYPE_CODE (arg_type
);
1195 /* The EABI passes structures that do not fit in a register by
1196 reference. In all other cases, pass the structure by value. */
1197 if (typecode
== TYPE_CODE_STRUCT
&& MIPS_EABI
&& len
> MIPS_REGSIZE
)
1199 store_address (valbuf
, MIPS_REGSIZE
, VALUE_ADDRESS (arg
));
1204 val
= (char *)VALUE_CONTENTS (arg
);
1206 /* 32-bit ABIs always start floating point arguments in an
1207 even-numbered floating point register. */
1208 if (!GDB_TARGET_IS_MIPS64
&& typecode
== TYPE_CODE_FLT
1209 && (float_argreg
& 1))
1212 /* Floating point arguments passed in registers have to be
1213 treated specially. On 32-bit architectures, doubles
1214 are passed in register pairs; the even register gets
1215 the low word, and the odd register gets the high word. */
1216 if (typecode
== TYPE_CODE_FLT
1217 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1218 && mips_fpu
!= MIPS_FPU_NONE
)
1220 if (!GDB_TARGET_IS_MIPS64
&& len
== 8)
1222 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1223 unsigned long regval
;
1225 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1226 write_register (float_argreg
++, regval
); /* low word */
1227 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1228 write_register (float_argreg
++, regval
); /* high word */
1233 CORE_ADDR regval
= extract_address (val
, len
);
1234 write_register (float_argreg
++, regval
);
1237 /* If this is the old ABI, skip one or two general registers. */
1239 argreg
+= GDB_TARGET_IS_MIPS64
? 1 : 2;
1243 /* Copy the argument to general registers or the stack in
1244 register-sized pieces. Large arguments are split between
1245 registers and stack. */
1248 int partial_len
= len
< MIPS_REGSIZE
? len
: MIPS_REGSIZE
;
1250 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1252 CORE_ADDR regval
= extract_address (val
, partial_len
);
1254 /* It's a simple argument being passed in a general
1256 If the argument length is smaller than the register size,
1257 we have to adjust the argument on big endian targets.
1258 But don't do this adjustment on EABI targets. */
1259 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
1260 && partial_len
< MIPS_REGSIZE
1262 regval
<<= ((MIPS_REGSIZE
- partial_len
) * TARGET_CHAR_BIT
);
1263 write_register (argreg
, regval
);
1266 /* If this is the old ABI, prevent subsequent floating
1267 point arguments from being passed in floating point
1270 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
1274 /* Write this portion of the argument to the stack. */
1276 write_memory (sp
+ stack_offset
, val
, partial_len
);
1277 stack_offset
+= ROUND_UP (partial_len
, MIPS_REGSIZE
);
1286 /* Set the return address register to point to the entry
1287 point of the program, where a breakpoint lies in wait. */
1288 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
1290 /* Return adjusted stack pointer. */
1295 mips_push_register(CORE_ADDR
*sp
, int regno
)
1297 char buffer
[MAX_REGISTER_RAW_SIZE
];
1298 int regsize
= REGISTER_RAW_SIZE (regno
);
1301 read_register_gen (regno
, buffer
);
1302 write_memory (*sp
, buffer
, regsize
);
1305 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
1306 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
1309 mips_push_dummy_frame()
1312 struct linked_proc_info
*link
= (struct linked_proc_info
*)
1313 xmalloc(sizeof(struct linked_proc_info
));
1314 mips_extra_func_info_t proc_desc
= &link
->info
;
1315 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
1316 CORE_ADDR old_sp
= sp
;
1317 link
->next
= linked_proc_desc_table
;
1318 linked_proc_desc_table
= link
;
1320 /* FIXME! are these correct ? */
1321 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
1322 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
1323 #define FLOAT_REG_SAVE_MASK MASK(0,19)
1324 #define FLOAT_SINGLE_REG_SAVE_MASK \
1325 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
1327 * The registers we must save are all those not preserved across
1328 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
1329 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
1330 * and FP Control/Status registers.
1333 * Dummy frame layout:
1336 * Saved MMHI, MMLO, FPC_CSR
1341 * Saved D18 (i.e. F19, F18)
1343 * Saved D0 (i.e. F1, F0)
1344 * Argument build area and stack arguments written via mips_push_arguments
1348 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
1349 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
1350 PROC_FRAME_OFFSET(proc_desc
) = 0;
1351 mips_push_register (&sp
, PC_REGNUM
);
1352 mips_push_register (&sp
, HI_REGNUM
);
1353 mips_push_register (&sp
, LO_REGNUM
);
1354 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
1356 /* Save general CPU registers */
1357 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
1358 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved R31) from FP */
1359 for (ireg
= 32; --ireg
>= 0; )
1360 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
1361 mips_push_register (&sp
, ireg
);
1363 /* Save floating point registers starting with high order word */
1364 PROC_FREG_MASK(proc_desc
) =
1365 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
1366 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
1367 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved D18) from FP */
1368 for (ireg
= 32; --ireg
>= 0; )
1369 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
1370 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
1372 /* Update the frame pointer for the call dummy and the stack pointer.
1373 Set the procedure's starting and ending addresses to point to the
1374 call dummy address at the entry point. */
1375 write_register (PUSH_FP_REGNUM
, old_sp
);
1376 write_register (SP_REGNUM
, sp
);
1377 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
1378 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
1379 SET_PROC_DESC_IS_DUMMY(proc_desc
);
1380 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
1386 register int regnum
;
1387 struct frame_info
*frame
= get_current_frame ();
1388 CORE_ADDR new_sp
= FRAME_FP (frame
);
1390 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1392 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
1393 if (frame
->saved_regs
== NULL
)
1394 mips_find_saved_regs (frame
);
1395 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1397 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
1398 && frame
->saved_regs
->regs
[regnum
])
1399 write_register (regnum
,
1400 read_memory_integer (frame
->saved_regs
->regs
[regnum
],
1403 write_register (SP_REGNUM
, new_sp
);
1404 flush_cached_frames ();
1406 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1408 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
1410 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
1412 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
1414 if (&pi_ptr
->info
== proc_desc
)
1419 error ("Can't locate dummy extra frame info\n");
1421 if (prev_ptr
!= NULL
)
1422 prev_ptr
->next
= pi_ptr
->next
;
1424 linked_proc_desc_table
= pi_ptr
->next
;
1428 write_register (HI_REGNUM
,
1429 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
1430 write_register (LO_REGNUM
,
1431 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
1432 if (mips_fpu
!= MIPS_FPU_NONE
)
1433 write_register (FCRCS_REGNUM
,
1434 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
1439 mips_print_register (regnum
, all
)
1442 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1444 /* Get the data in raw format. */
1445 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
1447 printf_filtered ("%s: [Invalid]", reg_names
[regnum
]);
1451 /* If an even floating pointer register, also print as double. */
1452 if (regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+MIPS_NUMREGS
1453 && !((regnum
-FP0_REGNUM
) & 1))
1455 char dbuffer
[MAX_REGISTER_RAW_SIZE
];
1457 read_relative_register_raw_bytes (regnum
, dbuffer
);
1458 read_relative_register_raw_bytes (regnum
+1, dbuffer
+4); /* FIXME!! */
1459 #ifdef REGISTER_CONVERT_TO_TYPE
1460 REGISTER_CONVERT_TO_TYPE(regnum
, builtin_type_double
, dbuffer
);
1462 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
1463 val_print (builtin_type_double
, dbuffer
, 0,
1464 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1465 printf_filtered ("); ");
1467 fputs_filtered (reg_names
[regnum
], gdb_stdout
);
1469 /* The problem with printing numeric register names (r26, etc.) is that
1470 the user can't use them on input. Probably the best solution is to
1471 fix it so that either the numeric or the funky (a2, etc.) names
1472 are accepted on input. */
1473 if (regnum
< MIPS_NUMREGS
)
1474 printf_filtered ("(r%d): ", regnum
);
1476 printf_filtered (": ");
1478 /* If virtual format is floating, print it that way. */
1479 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1480 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
1481 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1482 /* Else print as integer in hex. */
1484 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
1485 'x', 0, gdb_stdout
);
1488 /* Replacement for generic do_registers_info. */
1491 mips_do_registers_info (regnum
, fpregs
)
1497 if (*(reg_names
[regnum
]) == '\0')
1498 error ("Not a valid register for the current processor type");
1500 mips_print_register (regnum
, 0);
1501 printf_filtered ("\n");
1505 int did_newline
= 0;
1507 for (regnum
= 0; regnum
< NUM_REGS
; )
1509 if (((!fpregs
) && regnum
>= FP0_REGNUM
&& regnum
<= FCRIR_REGNUM
)
1510 || *(reg_names
[regnum
]) == '\0')
1515 mips_print_register (regnum
, 1);
1517 printf_filtered ("; ");
1519 if ((regnum
& 3) == 0)
1521 printf_filtered ("\n");
1526 printf_filtered ("\n");
1530 /* Return number of args passed to a frame. described by FIP.
1531 Can return -1, meaning no way to tell. */
1534 mips_frame_num_args (frame
)
1535 struct frame_info
*frame
;
1537 #if 0 /* FIXME Use or lose this! */
1538 struct chain_info_t
*p
;
1540 p
= mips_find_cached_frame (FRAME_FP (frame
));
1542 return p
->the_info
.numargs
;
1547 /* Is this a branch with a delay slot? */
1549 static int is_delayed
PARAMS ((unsigned long));
1556 for (i
= 0; i
< NUMOPCODES
; ++i
)
1557 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
1558 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
1560 return (i
< NUMOPCODES
1561 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
1562 | INSN_COND_BRANCH_DELAY
1563 | INSN_COND_BRANCH_LIKELY
)));
1567 mips_step_skips_delay (pc
)
1570 char buf
[MIPS_INSTLEN
];
1572 /* There is no branch delay slot on MIPS16. */
1576 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
1577 /* If error reading memory, guess that it is not a delayed branch. */
1579 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
1583 /* Skip the PC past function prologue instructions (32-bit version).
1584 This is a helper function for mips_skip_prologue. */
1587 mips32_skip_prologue (pc
, lenient
)
1588 CORE_ADDR pc
; /* starting PC to search from */
1593 int seen_sp_adjust
= 0;
1594 int load_immediate_bytes
= 0;
1596 /* Skip the typical prologue instructions. These are the stack adjustment
1597 instruction and the instructions that save registers on the stack
1598 or in the gcc frame. */
1599 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
1601 char buf
[MIPS_INSTLEN
];
1603 unsigned long high_word
;
1605 status
= read_memory_nobpt (pc
, buf
, MIPS_INSTLEN
);
1607 memory_error (status
, pc
);
1608 inst
= (unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
);
1609 high_word
= (inst
>> 16) & 0xffff;
1612 if (lenient
&& is_delayed (inst
))
1616 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
1617 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
1619 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
1620 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
1622 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
1623 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
1624 && (inst
& 0x001F0000)) /* reg != $zero */
1627 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
1629 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
1631 continue; /* reg != $zero */
1633 /* move $s8,$sp. With different versions of gas this will be either
1634 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
1635 Accept any one of these. */
1636 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1639 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
1641 else if (high_word
== 0x3c1c) /* lui $gp,n */
1643 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
1645 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1646 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
1648 /* The following instructions load $at or $t0 with an immediate
1649 value in preparation for a stack adjustment via
1650 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
1651 a local variable, so we accept them only before a stack adjustment
1652 instruction was seen. */
1653 else if (!seen_sp_adjust
)
1655 if (high_word
== 0x3c01 || /* lui $at,n */
1656 high_word
== 0x3c08) /* lui $t0,n */
1658 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1661 else if (high_word
== 0x3421 || /* ori $at,$at,n */
1662 high_word
== 0x3508 || /* ori $t0,$t0,n */
1663 high_word
== 0x3401 || /* ori $at,$zero,n */
1664 high_word
== 0x3408) /* ori $t0,$zero,n */
1666 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1676 /* In a frameless function, we might have incorrectly
1677 skipped some load immediate instructions. Undo the skipping
1678 if the load immediate was not followed by a stack adjustment. */
1679 if (load_immediate_bytes
&& !seen_sp_adjust
)
1680 pc
-= load_immediate_bytes
;
1684 /* Skip the PC past function prologue instructions (16-bit version).
1685 This is a helper function for mips_skip_prologue. */
1688 mips16_skip_prologue (pc
, lenient
)
1689 CORE_ADDR pc
; /* starting PC to search from */
1694 /* Table of instructions likely to be found in a function prologue. */
1697 unsigned short inst
;
1698 unsigned short mask
;
1701 { 0x6300, 0xff00 }, /* addiu $sp,offset */
1702 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
1703 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
1704 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
1705 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
1706 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
1707 { 0x673d, 0xffff }, /* move $s1,sp */
1708 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
1709 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
1710 { 0xe809, 0xf81f }, /* entry pseudo-op */
1711 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
1712 { 0, 0 } /* end of table marker */
1715 /* Skip the typical prologue instructions. These are the stack adjustment
1716 instruction and the instructions that save registers on the stack
1717 or in the gcc frame. */
1718 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
1720 char buf
[MIPS16_INSTLEN
];
1722 unsigned short inst
;
1723 int extend_bytes
= 0;
1724 int prev_extend_bytes
;
1727 status
= read_memory_nobpt (pc
& ~1, buf
, MIPS16_INSTLEN
);
1729 memory_error (status
, pc
);
1730 inst
= (unsigned long)extract_unsigned_integer (buf
, MIPS16_INSTLEN
);
1733 if (lenient
&& is_delayed (inst
))
1737 /* Normally we ignore an extend instruction. However, if it is
1738 not followed by a valid prologue instruction, we must adjust
1739 the pc back over the extend so that it won't be considered
1740 part of the prologue. */
1741 if ((inst
& 0xf800) == 0xf000) /* extend */
1743 extend_bytes
= MIPS16_INSTLEN
;
1746 prev_extend_bytes
= extend_bytes
;
1749 /* Check for other valid prologue instructions besides extend. */
1750 for (i
= 0; table
[i
].mask
!= 0; i
++)
1751 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
1753 if (table
[i
].mask
!= 0) /* it was in table? */
1754 continue; /* ignore it */
1755 else /* non-prologue */
1757 /* Return the current pc, adjusted backwards by 2 if
1758 the previous instruction was an extend. */
1759 return pc
- prev_extend_bytes
;
1765 /* To skip prologues, I use this predicate. Returns either PC itself
1766 if the code at PC does not look like a function prologue; otherwise
1767 returns an address that (if we're lucky) follows the prologue. If
1768 LENIENT, then we must skip everything which is involved in setting
1769 up the frame (it's OK to skip more, just so long as we don't skip
1770 anything which might clobber the registers which are being saved.
1771 We must skip more in the case where part of the prologue is in the
1772 delay slot of a non-prologue instruction). */
1775 mips_skip_prologue (pc
, lenient
)
1779 /* See if we can determine the end of the prologue via the symbol table.
1780 If so, then return either PC, or the PC after the prologue, whichever
1783 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
1785 if (post_prologue_pc
!= 0)
1786 return max (pc
, post_prologue_pc
);
1788 /* Can't determine prologue from the symbol table, need to examine
1792 return mips16_skip_prologue (pc
, lenient
);
1794 return mips32_skip_prologue (pc
, lenient
);
1798 /* The lenient prologue stuff should be superseded by the code in
1799 init_extra_frame_info which looks to see whether the stores mentioned
1800 in the proc_desc have actually taken place. */
1802 /* Is address PC in the prologue (loosely defined) for function at
1806 mips_in_lenient_prologue (startaddr
, pc
)
1807 CORE_ADDR startaddr
;
1810 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
1811 return pc
>= startaddr
&& pc
< end_prologue
;
1815 /* Given a return value in `regbuf' with a type `valtype',
1816 extract and copy its value into `valbuf'. */
1818 mips_extract_return_value (valtype
, regbuf
, valbuf
)
1819 struct type
*valtype
;
1820 char regbuf
[REGISTER_BYTES
];
1827 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
1828 && (mips_fpu
== MIPS_FPU_DOUBLE
1829 || (mips_fpu
== MIPS_FPU_SINGLE
&& TYPE_LENGTH (valtype
) <= 4))) /* FIXME!! */
1830 regnum
= FP0_REGNUM
;
1832 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
1833 && TYPE_CODE (valtype
) != TYPE_CODE_FLT
1834 && TYPE_LENGTH (valtype
) < REGISTER_RAW_SIZE (regnum
))
1835 offset
= REGISTER_RAW_SIZE (regnum
) - TYPE_LENGTH (valtype
);
1837 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
,
1838 TYPE_LENGTH (valtype
));
1839 #ifdef REGISTER_CONVERT_TO_TYPE
1840 REGISTER_CONVERT_TO_TYPE(regnum
, valtype
, valbuf
);
1844 /* Given a return value in `regbuf' with a type `valtype',
1845 write it's value into the appropriate register. */
1847 mips_store_return_value (valtype
, valbuf
)
1848 struct type
*valtype
;
1852 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1855 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
1856 && (mips_fpu
== MIPS_FPU_DOUBLE
1857 || (mips_fpu
== MIPS_FPU_SINGLE
&& TYPE_LENGTH (valtype
) <= 4))) /* FIXME!! */
1858 regnum
= FP0_REGNUM
;
1860 memcpy(raw_buffer
, valbuf
, TYPE_LENGTH (valtype
));
1862 #ifdef REGISTER_CONVERT_FROM_TYPE
1863 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
1866 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
, TYPE_LENGTH (valtype
));
1869 /* Exported procedure: Is PC in the signal trampoline code */
1872 in_sigtramp (pc
, ignore
)
1874 char *ignore
; /* function name */
1876 if (sigtramp_address
== 0)
1878 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
1881 /* Command to set FPU type. mips_fpu_string will have been set to the
1882 user's argument. Set mips_fpu based on mips_fpu_string, and then
1883 canonicalize mips_fpu_string. */
1887 mips_set_fpu_command (args
, from_tty
, c
)
1890 struct cmd_list_element
*c
;
1894 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
1895 mips_fpu
= MIPS_FPU_DOUBLE
;
1896 else if (strcasecmp (mips_fpu_string
, "double") == 0
1897 || strcasecmp (mips_fpu_string
, "on") == 0
1898 || strcasecmp (mips_fpu_string
, "1") == 0
1899 || strcasecmp (mips_fpu_string
, "yes") == 0)
1900 mips_fpu
= MIPS_FPU_DOUBLE
;
1901 else if (strcasecmp (mips_fpu_string
, "none") == 0
1902 || strcasecmp (mips_fpu_string
, "off") == 0
1903 || strcasecmp (mips_fpu_string
, "0") == 0
1904 || strcasecmp (mips_fpu_string
, "no") == 0)
1905 mips_fpu
= MIPS_FPU_NONE
;
1906 else if (strcasecmp (mips_fpu_string
, "single") == 0)
1907 mips_fpu
= MIPS_FPU_SINGLE
;
1909 err
= strsave (mips_fpu_string
);
1911 if (mips_fpu_string
!= NULL
)
1912 free (mips_fpu_string
);
1916 case MIPS_FPU_DOUBLE
:
1917 mips_fpu_string
= strsave ("double");
1919 case MIPS_FPU_SINGLE
:
1920 mips_fpu_string
= strsave ("single");
1923 mips_fpu_string
= strsave ("none");
1929 struct cleanup
*cleanups
= make_cleanup (free
, err
);
1930 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
1932 do_cleanups (cleanups
);
1937 mips_show_fpu_command (args
, from_tty
, c
)
1940 struct cmd_list_element
*c
;
1944 /* Command to set the processor type. */
1947 mips_set_processor_type_command (args
, from_tty
)
1953 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
1955 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
1956 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
1957 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
1959 /* Restore the value. */
1960 tmp_mips_processor_type
= strsave (mips_processor_type
);
1965 if (!mips_set_processor_type (tmp_mips_processor_type
))
1967 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
1968 /* Restore its value. */
1969 tmp_mips_processor_type
= strsave (mips_processor_type
);
1974 mips_show_processor_type_command (args
, from_tty
)
1980 /* Modify the actual processor type. */
1983 mips_set_processor_type (str
)
1991 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
1993 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
1995 mips_processor_type
= str
;
1997 for (j
= 0; j
< NUM_REGS
; ++j
)
1998 reg_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
2002 /* FIXME tweak fpu flag too */
2009 /* Attempt to identify the particular processor model by reading the
2013 mips_read_processor_type ()
2017 prid
= read_register (PRID_REGNUM
);
2019 if ((prid
& ~0xf) == 0x700)
2020 return savestring ("r3041", strlen("r3041"));
2025 /* Just like reinit_frame_cache, but with the right arguments to be
2026 callable as an sfunc. */
2029 reinit_frame_cache_sfunc (args
, from_tty
, c
)
2032 struct cmd_list_element
*c
;
2034 reinit_frame_cache ();
2038 gdb_print_insn_mips (memaddr
, info
)
2040 disassemble_info
*info
;
2042 mips_extra_func_info_t proc_desc
;
2044 /* Search for the function containing this address. Set the low bit
2045 of the address when searching, in case we were given an even address
2046 that is the start of a 16-bit function. If we didn't do this,
2047 the search would fail because the symbol table says the function
2048 starts at an odd address, i.e. 1 byte past the given address. */
2049 proc_desc
= find_proc_desc (memaddr
| 1, NULL
);
2051 /* Make an attempt to determine if this is a 16-bit function. If
2052 the procedure descriptor exists and the address therein is odd,
2053 it's definitely a 16-bit function. Otherwise, we have to just
2054 guess that if the address passed in is odd, it's 16-bits. */
2056 info
->mach
= PROC_LOW_ADDR (proc_desc
) & 1 ? 16 : 0;
2058 info
->mach
= memaddr
& 1 ? 16 : 0;
2060 /* Round down the instruction address to the appropriate boundary.
2061 Save the amount rounded down and subtract it from the returned size of
2062 the instruction so that the next time through the address won't
2064 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
2066 /* Call the appropriate disassembler based on the target endian-ness. */
2067 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2068 return print_insn_big_mips (memaddr
, info
);
2070 return print_insn_little_mips (memaddr
, info
);
2073 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
2074 counter value to determine whether a 16- or 32-bit breakpoint should be
2075 used. It returns a pointer to a string of bytes that encode a breakpoint
2076 instruction, stores the length of the string to *lenptr, and adjusts pc
2077 (if necessary) to point to the actual memory location where the
2078 breakpoint should be inserted. */
2080 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
2084 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2088 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
2090 *lenptr
= sizeof(mips16_big_breakpoint
);
2091 return mips16_big_breakpoint
;
2095 static char big_breakpoint
[] = BIG_BREAKPOINT
;
2096 *lenptr
= sizeof(big_breakpoint
);
2097 return big_breakpoint
;
2104 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
2106 *lenptr
= sizeof(mips16_little_breakpoint
);
2107 return mips16_little_breakpoint
;
2111 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
2112 *lenptr
= sizeof(little_breakpoint
);
2113 return little_breakpoint
;
2118 /* Test whether the PC points to the return instruction at the
2119 end of a function. This implements the ABOUT_TO_RETURN macro. */
2122 mips_about_to_return (pc
)
2126 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2127 generates a "jr $ra"; other times it generates code to load
2128 the return address from the stack to an accessible register (such
2129 as $a3), then a "jr" using that register. This second case
2130 is almost impossible to distinguish from an indirect jump
2131 used for switch statements, so we don't even try. */
2132 return read_memory_integer (pc
& ~1, 2) == 0xe820; /* jr $ra */
2134 return read_memory_integer (pc
, 4) == 0x3e00008; /* jr $ra */
2139 _initialize_mips_tdep ()
2141 struct cmd_list_element
*c
;
2143 tm_print_insn
= gdb_print_insn_mips
;
2145 /* Let the user turn off floating point and set the fence post for
2146 heuristic_proc_start. */
2148 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
2149 (char *) &mips_fpu_string
,
2150 "Set use of floating point coprocessor.\n\
2151 Set to `none' to avoid using floating point instructions when calling\n\
2152 functions or dealing with return values. Set to `single' to use only\n\
2153 single precision floating point as on the R4650. Set to `double' for\n\
2154 normal floating point support.",
2156 c
->function
.sfunc
= mips_set_fpu_command
;
2157 c
= add_show_from_set (c
, &showlist
);
2158 c
->function
.sfunc
= mips_show_fpu_command
;
2160 mips_fpu
= MIPS_FPU_DOUBLE
;
2161 mips_fpu_string
= strsave ("double");
2163 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
2164 (char *) &tmp_mips_processor_type
,
2165 "Set the type of MIPS processor in use.\n\
2166 Set this to be able to access processor-type-specific registers.\n\
2169 c
->function
.cfunc
= mips_set_processor_type_command
;
2170 c
= add_show_from_set (c
, &showlist
);
2171 c
->function
.cfunc
= mips_show_processor_type_command
;
2173 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
2174 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
2176 /* We really would like to have both "0" and "unlimited" work, but
2177 command.c doesn't deal with that. So make it a var_zinteger
2178 because the user can always use "999999" or some such for unlimited. */
2179 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
2180 (char *) &heuristic_fence_post
,
2182 Set the distance searched for the start of a function.\n\
2183 If you are debugging a stripped executable, GDB needs to search through the\n\
2184 program for the start of a function. This command sets the distance of the\n\
2185 search. The only need to set it is when debugging a stripped executable.",
2187 /* We need to throw away the frame cache when we set this, since it
2188 might change our ability to get backtraces. */
2189 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
2190 add_show_from_set (c
, &showlist
);