1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *const mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 const struct register_alias mips_numeric_register_aliases
[] = {
146 #define R(n) { #n, n }
147 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
148 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
149 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
150 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
154 #ifndef MIPS_DEFAULT_FPU_TYPE
155 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
157 static int mips_fpu_type_auto
= 1;
158 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
160 static int mips_debug
= 0;
162 /* Properties (for struct target_desc) describing the g/G packet
164 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
165 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
167 struct target_desc
*mips_tdesc_gp32
;
168 struct target_desc
*mips_tdesc_gp64
;
170 const struct mips_regnum
*
171 mips_regnum (struct gdbarch
*gdbarch
)
173 return gdbarch_tdep (gdbarch
)->regnum
;
177 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
179 return mips_regnum (gdbarch
)->fp0
+ 12;
182 /* Return 1 if REGNUM refers to a floating-point general register, raw
183 or cooked. Otherwise return 0. */
186 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
188 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
190 return (rawnum
>= mips_regnum (gdbarch
)->fp0
191 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
194 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
196 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
198 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
199 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
201 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
202 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
204 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
206 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
207 functions to test, set, or clear bit 0 of addresses. */
210 is_mips16_addr (CORE_ADDR addr
)
216 unmake_mips16_addr (CORE_ADDR addr
)
218 return ((addr
) & ~(CORE_ADDR
) 1);
222 make_mips16_addr (CORE_ADDR addr
)
224 return ((addr
) | (CORE_ADDR
) 1);
227 /* Return the MIPS ABI associated with GDBARCH. */
229 mips_abi (struct gdbarch
*gdbarch
)
231 return gdbarch_tdep (gdbarch
)->mips_abi
;
235 mips_isa_regsize (struct gdbarch
*gdbarch
)
237 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
239 /* If we know how big the registers are, use that size. */
240 if (tdep
->register_size_valid_p
)
241 return tdep
->register_size
;
243 /* Fall back to the previous behavior. */
244 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
245 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
248 /* Return the currently configured (or set) saved register size. */
251 mips_abi_regsize (struct gdbarch
*gdbarch
)
253 switch (mips_abi (gdbarch
))
255 case MIPS_ABI_EABI32
:
261 case MIPS_ABI_EABI64
:
263 case MIPS_ABI_UNKNOWN
:
266 internal_error (__FILE__
, __LINE__
, _("bad switch"));
270 /* Functions for setting and testing a bit in a minimal symbol that
271 marks it as 16-bit function. The MSB of the minimal symbol's
272 "info" field is used for this purpose.
274 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
275 i.e. refers to a 16-bit function, and sets a "special" bit in a
276 minimal symbol to mark it as a 16-bit function
278 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
281 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
283 if (ELF_ST_IS_MIPS16 (((elf_symbol_type
*)
284 (sym
))->internal_elf_sym
.st_other
))
286 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
291 msymbol_is_special (struct minimal_symbol
*msym
)
293 return MSYMBOL_TARGET_FLAG_1 (msym
);
296 /* XFER a value from the big/little/left end of the register.
297 Depending on the size of the value it might occupy the entire
298 register or just part of it. Make an allowance for this, aligning
299 things accordingly. */
302 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
303 int reg_num
, int length
,
304 enum bfd_endian endian
, gdb_byte
*in
,
305 const gdb_byte
*out
, int buf_offset
)
309 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
310 /* Need to transfer the left or right part of the register, based on
311 the targets byte order. */
315 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
317 case BFD_ENDIAN_LITTLE
:
320 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
324 internal_error (__FILE__
, __LINE__
, _("bad switch"));
327 fprintf_unfiltered (gdb_stderr
,
328 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
329 reg_num
, reg_offset
, buf_offset
, length
);
330 if (mips_debug
&& out
!= NULL
)
333 fprintf_unfiltered (gdb_stdlog
, "out ");
334 for (i
= 0; i
< length
; i
++)
335 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
338 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
341 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
343 if (mips_debug
&& in
!= NULL
)
346 fprintf_unfiltered (gdb_stdlog
, "in ");
347 for (i
= 0; i
< length
; i
++)
348 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
351 fprintf_unfiltered (gdb_stdlog
, "\n");
354 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
355 compatiblity mode. A return value of 1 means that we have
356 physical 64-bit registers, but should treat them as 32-bit registers. */
359 mips2_fp_compat (struct frame_info
*frame
)
361 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
362 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
364 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
368 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
369 in all the places we deal with FP registers. PR gdb/413. */
370 /* Otherwise check the FR bit in the status register - it controls
371 the FP compatiblity mode. If it is clear we are in compatibility
373 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
380 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
382 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
384 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
386 /* The list of available "set mips " and "show mips " commands. */
388 static struct cmd_list_element
*setmipscmdlist
= NULL
;
389 static struct cmd_list_element
*showmipscmdlist
= NULL
;
391 /* Integer registers 0 thru 31 are handled explicitly by
392 mips_register_name(). Processor specific registers 32 and above
393 are listed in the following tables. */
396 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
400 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
401 "sr", "lo", "hi", "bad", "cause", "pc",
402 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
403 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
404 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
405 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
409 /* Names of IDT R3041 registers. */
411 static const char *mips_r3041_reg_names
[] = {
412 "sr", "lo", "hi", "bad", "cause", "pc",
413 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
414 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
415 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
416 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
417 "fsr", "fir", "", /*"fp" */ "",
418 "", "", "bus", "ccfg", "", "", "", "",
419 "", "", "port", "cmp", "", "", "epc", "prid",
422 /* Names of tx39 registers. */
424 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
425 "sr", "lo", "hi", "bad", "cause", "pc",
426 "", "", "", "", "", "", "", "",
427 "", "", "", "", "", "", "", "",
428 "", "", "", "", "", "", "", "",
429 "", "", "", "", "", "", "", "",
431 "", "", "", "", "", "", "", "",
432 "", "", "config", "cache", "debug", "depc", "epc",
435 /* Names of IRIX registers. */
436 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
437 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
438 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
439 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
440 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
441 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
444 /* Names of registers with Linux kernels. */
445 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
446 "sr", "lo", "hi", "bad", "cause", "pc",
447 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
448 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
449 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
450 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
455 /* Return the name of the register corresponding to REGNO. */
457 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
459 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
460 /* GPR names for all ABIs other than n32/n64. */
461 static char *mips_gpr_names
[] = {
462 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
463 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
464 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
465 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
468 /* GPR names for n32 and n64 ABIs. */
469 static char *mips_n32_n64_gpr_names
[] = {
470 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
471 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
472 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
473 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
476 enum mips_abi abi
= mips_abi (gdbarch
);
478 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
479 but then don't make the raw register names visible. This (upper)
480 range of user visible register numbers are the pseudo-registers.
482 This approach was adopted accommodate the following scenario:
483 It is possible to debug a 64-bit device using a 32-bit
484 programming model. In such instances, the raw registers are
485 configured to be 64-bits wide, while the pseudo registers are
486 configured to be 32-bits wide. The registers that the user
487 sees - the pseudo registers - match the users expectations
488 given the programming model being used. */
489 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
490 if (regno
< gdbarch_num_regs (gdbarch
))
493 /* The MIPS integer registers are always mapped from 0 to 31. The
494 names of the registers (which reflects the conventions regarding
495 register use) vary depending on the ABI. */
496 if (0 <= rawnum
&& rawnum
< 32)
498 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
499 return mips_n32_n64_gpr_names
[rawnum
];
501 return mips_gpr_names
[rawnum
];
503 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
504 return tdesc_register_name (gdbarch
, rawnum
);
505 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
507 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
508 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
509 return tdep
->mips_processor_reg_names
[rawnum
- 32];
513 internal_error (__FILE__
, __LINE__
,
514 _("mips_register_name: bad register number %d"), rawnum
);
517 /* Return the groups that a MIPS register can be categorised into. */
520 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
521 struct reggroup
*reggroup
)
526 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
527 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
528 if (reggroup
== all_reggroup
)
530 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
531 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
532 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
533 (gdbarch), as not all architectures are multi-arch. */
534 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
535 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
536 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
538 if (reggroup
== float_reggroup
)
539 return float_p
&& pseudo
;
540 if (reggroup
== vector_reggroup
)
541 return vector_p
&& pseudo
;
542 if (reggroup
== general_reggroup
)
543 return (!vector_p
&& !float_p
) && pseudo
;
544 /* Save the pseudo registers. Need to make certain that any code
545 extracting register values from a saved register cache also uses
547 if (reggroup
== save_reggroup
)
548 return raw_p
&& pseudo
;
549 /* Restore the same pseudo register. */
550 if (reggroup
== restore_reggroup
)
551 return raw_p
&& pseudo
;
555 /* Return the groups that a MIPS register can be categorised into.
556 This version is only used if we have a target description which
557 describes real registers (and their groups). */
560 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
561 struct reggroup
*reggroup
)
563 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
564 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
567 /* Only save, restore, and display the pseudo registers. Need to
568 make certain that any code extracting register values from a
569 saved register cache also uses pseudo registers.
571 Note: saving and restoring the pseudo registers is slightly
572 strange; if we have 64 bits, we should save and restore all
573 64 bits. But this is hard and has little benefit. */
577 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
581 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
584 /* Map the symbol table registers which live in the range [1 *
585 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
586 registers. Take care of alignment and size problems. */
588 static enum register_status
589 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
590 int cookednum
, gdb_byte
*buf
)
592 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
593 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
594 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
595 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
596 return regcache_raw_read (regcache
, rawnum
, buf
);
597 else if (register_size (gdbarch
, rawnum
) >
598 register_size (gdbarch
, cookednum
))
600 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
601 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
604 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
606 enum register_status status
;
608 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
609 if (status
== REG_VALID
)
610 store_signed_integer (buf
, 4, byte_order
, regval
);
615 internal_error (__FILE__
, __LINE__
, _("bad register size"));
619 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
620 struct regcache
*regcache
, int cookednum
,
623 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
624 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
625 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
626 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
627 regcache_raw_write (regcache
, rawnum
, buf
);
628 else if (register_size (gdbarch
, rawnum
) >
629 register_size (gdbarch
, cookednum
))
631 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
632 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
635 /* Sign extend the shortened version of the register prior
636 to placing it in the raw register. This is required for
637 some mips64 parts in order to avoid unpredictable behavior. */
638 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
639 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
640 regcache_raw_write_signed (regcache
, rawnum
, regval
);
644 internal_error (__FILE__
, __LINE__
, _("bad register size"));
648 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
649 struct agent_expr
*ax
, int reg
)
651 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
652 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
653 && reg
< 2 * gdbarch_num_regs (gdbarch
));
655 ax_reg_mask (ax
, rawnum
);
661 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
662 struct agent_expr
*ax
, int reg
)
664 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
665 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
666 && reg
< 2 * gdbarch_num_regs (gdbarch
));
667 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
671 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
673 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
674 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
677 ax_simple (ax
, aop_lsh
);
680 ax_simple (ax
, aop_rsh_signed
);
684 internal_error (__FILE__
, __LINE__
, _("bad register size"));
689 /* Table to translate MIPS16 register field to actual register number. */
690 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
692 /* Heuristic_proc_start may hunt through the text section for a long
693 time across a 2400 baud serial line. Allows the user to limit this
696 static unsigned int heuristic_fence_post
= 0;
698 /* Number of bytes of storage in the actual machine representation for
699 register N. NOTE: This defines the pseudo register type so need to
700 rebuild the architecture vector. */
702 static int mips64_transfers_32bit_regs_p
= 0;
705 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
706 struct cmd_list_element
*c
)
708 struct gdbarch_info info
;
709 gdbarch_info_init (&info
);
710 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
711 instead of relying on globals. Doing that would let generic code
712 handle the search for this specific architecture. */
713 if (!gdbarch_update_p (info
))
715 mips64_transfers_32bit_regs_p
= 0;
716 error (_("32-bit compatibility mode not supported"));
720 /* Convert to/from a register and the corresponding memory value. */
722 /* This predicate tests for the case of an 8 byte floating point
723 value that is being transferred to or from a pair of floating point
724 registers each of which are (or are considered to be) only 4 bytes
727 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
730 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
731 && register_size (gdbarch
, regnum
) == 4
732 && mips_float_register_p (gdbarch
, regnum
)
733 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
736 /* This predicate tests for the case of a value of less than 8
737 bytes in width that is being transfered to or from an 8 byte
738 general purpose register. */
740 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
743 int num_regs
= gdbarch_num_regs (gdbarch
);
745 return (register_size (gdbarch
, regnum
) == 8
746 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
747 && TYPE_LENGTH (type
) < 8);
751 mips_convert_register_p (struct gdbarch
*gdbarch
,
752 int regnum
, struct type
*type
)
754 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
755 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
759 mips_register_to_value (struct frame_info
*frame
, int regnum
,
760 struct type
*type
, gdb_byte
*to
,
761 int *optimizedp
, int *unavailablep
)
763 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
765 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
767 get_frame_register (frame
, regnum
+ 0, to
+ 4);
768 get_frame_register (frame
, regnum
+ 1, to
+ 0);
770 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
771 optimizedp
, unavailablep
))
774 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
775 optimizedp
, unavailablep
))
777 *optimizedp
= *unavailablep
= 0;
780 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
782 int len
= TYPE_LENGTH (type
);
785 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
786 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
787 optimizedp
, unavailablep
))
790 *optimizedp
= *unavailablep
= 0;
795 internal_error (__FILE__
, __LINE__
,
796 _("mips_register_to_value: unrecognized case"));
801 mips_value_to_register (struct frame_info
*frame
, int regnum
,
802 struct type
*type
, const gdb_byte
*from
)
804 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
806 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
808 put_frame_register (frame
, regnum
+ 0, from
+ 4);
809 put_frame_register (frame
, regnum
+ 1, from
+ 0);
811 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
814 int len
= TYPE_LENGTH (type
);
816 /* Sign extend values, irrespective of type, that are stored to
817 a 64-bit general purpose register. (32-bit unsigned values
818 are stored as signed quantities within a 64-bit register.
819 When performing an operation, in compiled code, that combines
820 a 32-bit unsigned value with a signed 64-bit value, a type
821 conversion is first performed that zeroes out the high 32 bits.) */
822 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
825 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
827 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
828 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
829 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
833 if (from
[len
-1] & 0x80)
834 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
836 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
837 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
838 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
843 internal_error (__FILE__
, __LINE__
,
844 _("mips_value_to_register: unrecognized case"));
848 /* Return the GDB type object for the "standard" data type of data in
852 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
854 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
855 if (mips_float_register_p (gdbarch
, regnum
))
857 /* The floating-point registers raw, or cooked, always match
858 mips_isa_regsize(), and also map 1:1, byte for byte. */
859 if (mips_isa_regsize (gdbarch
) == 4)
860 return builtin_type (gdbarch
)->builtin_float
;
862 return builtin_type (gdbarch
)->builtin_double
;
864 else if (regnum
< gdbarch_num_regs (gdbarch
))
866 /* The raw or ISA registers. These are all sized according to
868 if (mips_isa_regsize (gdbarch
) == 4)
869 return builtin_type (gdbarch
)->builtin_int32
;
871 return builtin_type (gdbarch
)->builtin_int64
;
875 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
877 /* The cooked or ABI registers. These are sized according to
878 the ABI (with a few complications). */
879 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
880 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
881 return builtin_type (gdbarch
)->builtin_int32
;
882 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
883 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
884 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
885 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
886 /* The pseudo/cooked view of the embedded registers is always
887 32-bit. The raw view is handled below. */
888 return builtin_type (gdbarch
)->builtin_int32
;
889 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
890 /* The target, while possibly using a 64-bit register buffer,
891 is only transfering 32-bits of each integer register.
892 Reflect this in the cooked/pseudo (ABI) register value. */
893 return builtin_type (gdbarch
)->builtin_int32
;
894 else if (mips_abi_regsize (gdbarch
) == 4)
895 /* The ABI is restricted to 32-bit registers (the ISA could be
897 return builtin_type (gdbarch
)->builtin_int32
;
900 return builtin_type (gdbarch
)->builtin_int64
;
904 /* Return the GDB type for the pseudo register REGNUM, which is the
905 ABI-level view. This function is only called if there is a target
906 description which includes registers, so we know precisely the
907 types of hardware registers. */
910 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
912 const int num_regs
= gdbarch_num_regs (gdbarch
);
913 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
914 int rawnum
= regnum
% num_regs
;
915 struct type
*rawtype
;
917 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
919 /* Absent registers are still absent. */
920 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
921 if (TYPE_LENGTH (rawtype
) == 0)
924 if (rawnum
>= mips_regnum (gdbarch
)->fp0
925 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32)
926 /* Present the floating point registers however the hardware did;
927 do not try to convert between FPU layouts. */
930 /* Use pointer types for registers if we can. For n32 we can not,
931 since we do not have a 64-bit pointer type. */
932 if (mips_abi_regsize (gdbarch
)
933 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
935 if (rawnum
== MIPS_SP_REGNUM
936 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
937 return builtin_type (gdbarch
)->builtin_data_ptr
;
938 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
939 return builtin_type (gdbarch
)->builtin_func_ptr
;
942 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
943 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
944 || rawnum
== mips_regnum (gdbarch
)->lo
945 || rawnum
== mips_regnum (gdbarch
)->hi
946 || rawnum
== mips_regnum (gdbarch
)->badvaddr
947 || rawnum
== mips_regnum (gdbarch
)->cause
948 || rawnum
== mips_regnum (gdbarch
)->pc
949 || (mips_regnum (gdbarch
)->dspacc
!= -1
950 && rawnum
>= mips_regnum (gdbarch
)->dspacc
951 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
952 return builtin_type (gdbarch
)->builtin_int32
;
954 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
955 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
956 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
957 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
959 /* The pseudo/cooked view of embedded registers is always
960 32-bit, even if the target transfers 64-bit values for them.
961 New targets relying on XML descriptions should only transfer
962 the necessary 32 bits, but older versions of GDB expected 64,
963 so allow the target to provide 64 bits without interfering
964 with the displayed type. */
965 return builtin_type (gdbarch
)->builtin_int32
;
968 /* For all other registers, pass through the hardware type. */
972 /* Should the upper word of 64-bit addresses be zeroed? */
973 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
976 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
978 switch (mask_address_var
)
980 case AUTO_BOOLEAN_TRUE
:
982 case AUTO_BOOLEAN_FALSE
:
985 case AUTO_BOOLEAN_AUTO
:
986 return tdep
->default_mask_address_p
;
988 internal_error (__FILE__
, __LINE__
,
989 _("mips_mask_address_p: bad switch"));
995 show_mask_address (struct ui_file
*file
, int from_tty
,
996 struct cmd_list_element
*c
, const char *value
)
998 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
1000 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1001 switch (mask_address_var
)
1003 case AUTO_BOOLEAN_TRUE
:
1004 printf_filtered ("The 32 bit mips address mask is enabled\n");
1006 case AUTO_BOOLEAN_FALSE
:
1007 printf_filtered ("The 32 bit mips address mask is disabled\n");
1009 case AUTO_BOOLEAN_AUTO
:
1011 ("The 32 bit address mask is set automatically. Currently %s\n",
1012 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1015 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1020 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1023 mips_pc_is_mips16 (CORE_ADDR memaddr
)
1025 struct minimal_symbol
*sym
;
1027 /* A flag indicating that this is a MIPS16 function is stored by
1028 elfread.c in the high bit of the info field. Use this to decide
1029 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of
1030 the address is set, assume this is a MIPS16 address. */
1031 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1033 return msymbol_is_special (sym
);
1035 return is_mips16_addr (memaddr
);
1038 /* MIPS believes that the PC has a sign extended value. Perhaps the
1039 all registers should be sign extended for simplicity? */
1042 mips_read_pc (struct regcache
*regcache
)
1045 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1046 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1047 if (is_mips16_addr (pc
))
1048 pc
= unmake_mips16_addr (pc
);
1053 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1057 pc
= frame_unwind_register_signed
1058 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1059 if (is_mips16_addr (pc
))
1060 pc
= unmake_mips16_addr (pc
);
1065 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1067 return frame_unwind_register_signed
1068 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1071 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1072 dummy frame. The frame ID's base needs to match the TOS value
1073 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1076 static struct frame_id
1077 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1079 return frame_id_build
1080 (get_frame_register_signed (this_frame
,
1081 gdbarch_num_regs (gdbarch
)
1083 get_frame_pc (this_frame
));
1087 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1089 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1090 if (mips_pc_is_mips16 (pc
))
1091 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1093 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1096 /* Fetch and return instruction from the specified location. If the PC
1097 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1100 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1102 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1103 gdb_byte buf
[MIPS_INSN32_SIZE
];
1107 if (mips_pc_is_mips16 (addr
))
1109 instlen
= MIPS_INSN16_SIZE
;
1110 addr
= unmake_mips16_addr (addr
);
1113 instlen
= MIPS_INSN32_SIZE
;
1114 status
= target_read_memory (addr
, buf
, instlen
);
1116 memory_error (status
, addr
);
1117 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1120 /* These are the fields of 32 bit mips instructions. */
1121 #define mips32_op(x) (x >> 26)
1122 #define itype_op(x) (x >> 26)
1123 #define itype_rs(x) ((x >> 21) & 0x1f)
1124 #define itype_rt(x) ((x >> 16) & 0x1f)
1125 #define itype_immediate(x) (x & 0xffff)
1127 #define jtype_op(x) (x >> 26)
1128 #define jtype_target(x) (x & 0x03ffffff)
1130 #define rtype_op(x) (x >> 26)
1131 #define rtype_rs(x) ((x >> 21) & 0x1f)
1132 #define rtype_rt(x) ((x >> 16) & 0x1f)
1133 #define rtype_rd(x) ((x >> 11) & 0x1f)
1134 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1135 #define rtype_funct(x) (x & 0x3f)
1138 mips32_relative_offset (ULONGEST inst
)
1140 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1143 /* Determine the address of the next instruction executed after the INST
1144 floating condition branch instruction at PC. COUNT specifies the
1145 number of the floating condition bits tested by the branch. */
1148 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1149 ULONGEST inst
, CORE_ADDR pc
, int count
)
1151 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1152 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1153 int tf
= itype_rt (inst
) & 1;
1154 int mask
= (1 << count
) - 1;
1159 /* No way to handle; it'll most likely trap anyway. */
1162 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1163 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1165 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1166 pc
+= mips32_relative_offset (inst
);
1173 /* Determine where to set a single step breakpoint while considering
1174 branch prediction. */
1176 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1178 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1181 inst
= mips_fetch_instruction (gdbarch
, pc
);
1182 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1185 if (itype_op (inst
) >> 2 == 5)
1186 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1188 op
= (itype_op (inst
) & 0x03);
1198 goto greater_branch
;
1203 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1204 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1205 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1206 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 9
1207 && (itype_rt (inst
) & 2) == 0)
1208 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1209 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1210 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 10
1211 && (itype_rt (inst
) & 2) == 0)
1212 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1213 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1214 else if (itype_op (inst
) == 29)
1216 /* The new PC will be alternate mode. */
1220 reg
= jtype_target (inst
) << 2;
1221 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1222 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1225 pc
+= 4; /* Not a branch, next instruction is easy. */
1228 { /* This gets way messy. */
1230 /* Further subdivide into SPECIAL, REGIMM and other. */
1231 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1233 case 0: /* SPECIAL */
1234 op
= rtype_funct (inst
);
1239 /* Set PC to that address. */
1240 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1242 case 12: /* SYSCALL */
1244 struct gdbarch_tdep
*tdep
;
1246 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1247 if (tdep
->syscall_next_pc
!= NULL
)
1248 pc
= tdep
->syscall_next_pc (frame
);
1257 break; /* end SPECIAL */
1258 case 1: /* REGIMM */
1260 op
= itype_rt (inst
); /* branch condition */
1265 case 16: /* BLTZAL */
1266 case 18: /* BLTZALL */
1268 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1269 pc
+= mips32_relative_offset (inst
) + 4;
1271 pc
+= 8; /* after the delay slot */
1275 case 17: /* BGEZAL */
1276 case 19: /* BGEZALL */
1277 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1278 pc
+= mips32_relative_offset (inst
) + 4;
1280 pc
+= 8; /* after the delay slot */
1282 case 0x1c: /* BPOSGE32 */
1283 case 0x1e: /* BPOSGE64 */
1285 if (itype_rs (inst
) == 0)
1287 unsigned int pos
= (op
& 2) ? 64 : 32;
1288 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1291 /* No way to handle; it'll most likely trap anyway. */
1294 if ((get_frame_register_unsigned (frame
,
1295 dspctl
) & 0x7f) >= pos
)
1296 pc
+= mips32_relative_offset (inst
);
1301 /* All of the other instructions in the REGIMM category */
1306 break; /* end REGIMM */
1311 reg
= jtype_target (inst
) << 2;
1312 /* Upper four bits get never changed... */
1313 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1316 case 4: /* BEQ, BEQL */
1318 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1319 get_frame_register_signed (frame
, itype_rt (inst
)))
1320 pc
+= mips32_relative_offset (inst
) + 4;
1324 case 5: /* BNE, BNEL */
1326 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1327 get_frame_register_signed (frame
, itype_rt (inst
)))
1328 pc
+= mips32_relative_offset (inst
) + 4;
1332 case 6: /* BLEZ, BLEZL */
1333 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1334 pc
+= mips32_relative_offset (inst
) + 4;
1340 greater_branch
: /* BGTZ, BGTZL */
1341 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1342 pc
+= mips32_relative_offset (inst
) + 4;
1349 } /* mips32_next_pc */
1351 /* Decoding the next place to set a breakpoint is irregular for the
1352 mips 16 variant, but fortunately, there fewer instructions. We have
1353 to cope ith extensions for 16 bit instructions and a pair of actual
1354 32 bit instructions. We dont want to set a single step instruction
1355 on the extend instruction either. */
1357 /* Lots of mips16 instruction formats */
1358 /* Predicting jumps requires itype,ritype,i8type
1359 and their extensions extItype,extritype,extI8type. */
1360 enum mips16_inst_fmts
1362 itype
, /* 0 immediate 5,10 */
1363 ritype
, /* 1 5,3,8 */
1364 rrtype
, /* 2 5,3,3,5 */
1365 rritype
, /* 3 5,3,3,5 */
1366 rrrtype
, /* 4 5,3,3,3,2 */
1367 rriatype
, /* 5 5,3,3,1,4 */
1368 shifttype
, /* 6 5,3,3,3,2 */
1369 i8type
, /* 7 5,3,8 */
1370 i8movtype
, /* 8 5,3,3,5 */
1371 i8mov32rtype
, /* 9 5,3,5,3 */
1372 i64type
, /* 10 5,3,8 */
1373 ri64type
, /* 11 5,3,3,5 */
1374 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1375 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1376 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1377 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1378 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1379 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1380 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1381 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1382 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1383 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1385 /* I am heaping all the fields of the formats into one structure and
1386 then, only the fields which are involved in instruction extension. */
1390 unsigned int regx
; /* Function in i8 type. */
1395 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1396 for the bits which make up the immediate extension. */
1399 extended_offset (unsigned int extension
)
1403 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1405 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1407 value
|= extension
& 0x1f; /* Extract 4:0. */
1412 /* Only call this function if you know that this is an extendable
1413 instruction. It won't malfunction, but why make excess remote memory
1414 references? If the immediate operands get sign extended or something,
1415 do it after the extension is performed. */
1416 /* FIXME: Every one of these cases needs to worry about sign extension
1417 when the offset is to be used in relative addressing. */
1420 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1422 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1424 pc
&= 0xfffffffe; /* Clear the low order bit. */
1425 target_read_memory (pc
, buf
, 2);
1426 return extract_unsigned_integer (buf
, 2, byte_order
);
1430 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1431 unsigned int extension
,
1433 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1438 switch (insn_format
)
1445 value
= extended_offset ((extension
<< 16) | inst
);
1446 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1450 value
= inst
& 0x7ff;
1451 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
1460 { /* A register identifier and an offset. */
1461 /* Most of the fields are the same as I type but the
1462 immediate value is of a different length. */
1466 value
= extended_offset ((extension
<< 16) | inst
);
1467 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1471 value
= inst
& 0xff; /* 8 bits */
1472 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
1475 regx
= (inst
>> 8) & 0x07; /* i8 funct */
1481 unsigned long value
;
1482 unsigned int nexthalf
;
1483 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1484 value
= value
<< 16;
1485 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1494 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1496 upk
->offset
= offset
;
1503 add_offset_16 (CORE_ADDR pc
, int offset
)
1505 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1509 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1510 unsigned int extension
, unsigned int insn
)
1512 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1513 int op
= (insn
>> 11);
1516 case 2: /* Branch */
1519 struct upk_mips16 upk
;
1520 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1521 pc
+= (upk
.offset
<< 1) + 2;
1524 case 3: /* JAL , JALX - Watch out, these are 32 bit
1527 struct upk_mips16 upk
;
1528 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1529 pc
= add_offset_16 (pc
, upk
.offset
);
1530 if ((insn
>> 10) & 0x01) /* Exchange mode */
1531 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1538 struct upk_mips16 upk
;
1540 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1541 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1543 pc
+= (upk
.offset
<< 1) + 2;
1550 struct upk_mips16 upk
;
1552 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1553 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1555 pc
+= (upk
.offset
<< 1) + 2;
1560 case 12: /* I8 Formats btez btnez */
1562 struct upk_mips16 upk
;
1564 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1565 /* upk.regx contains the opcode */
1566 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1567 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1568 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1569 /* pc = add_offset_16(pc,upk.offset) ; */
1570 pc
+= (upk
.offset
<< 1) + 2;
1575 case 29: /* RR Formats JR, JALR, JALR-RA */
1577 struct upk_mips16 upk
;
1578 /* upk.fmt = rrtype; */
1583 upk
.regx
= (insn
>> 8) & 0x07;
1584 upk
.regy
= (insn
>> 5) & 0x07;
1585 if ((upk
.regy
& 1) == 0)
1586 reg
= mips16_to_32_reg
[upk
.regx
];
1588 reg
= 31; /* Function return instruction. */
1589 pc
= get_frame_register_signed (frame
, reg
);
1596 /* This is an instruction extension. Fetch the real instruction
1597 (which follows the extension) and decode things based on
1601 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1602 fetch_mips_16 (gdbarch
, pc
));
1615 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1617 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1618 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1619 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1622 /* The mips_next_pc function supports single_step when the remote
1623 target monitor or stub is not developed enough to do a single_step.
1624 It works by decoding the current instruction and predicting where a
1625 branch will go. This isnt hard because all the data is available.
1626 The MIPS32 and MIPS16 variants are quite different. */
1628 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1630 if (mips_pc_is_mips16 (pc
))
1631 return mips16_next_pc (frame
, pc
);
1633 return mips32_next_pc (frame
, pc
);
1636 struct mips_frame_cache
1639 struct trad_frame_saved_reg
*saved_regs
;
1642 /* Set a register's saved stack address in temp_saved_regs. If an
1643 address has already been set for this register, do nothing; this
1644 way we will only recognize the first save of a given register in a
1647 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1648 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1649 Strictly speaking, only the second range is used as it is only second
1650 range (the ABI instead of ISA registers) that comes into play when finding
1651 saved registers in a frame. */
1654 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1655 int regnum
, CORE_ADDR offset
)
1657 if (this_cache
!= NULL
1658 && this_cache
->saved_regs
[regnum
].addr
== -1)
1660 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1662 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1668 /* Fetch the immediate value from a MIPS16 instruction.
1669 If the previous instruction was an EXTEND, use it to extend
1670 the upper bits of the immediate value. This is a helper function
1671 for mips16_scan_prologue. */
1674 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1675 unsigned short inst
, /* current instruction */
1676 int nbits
, /* number of bits in imm field */
1677 int scale
, /* scale factor to be applied to imm */
1678 int is_signed
) /* is the imm field signed? */
1682 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1684 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1685 if (offset
& 0x8000) /* check for negative extend */
1686 offset
= 0 - (0x10000 - (offset
& 0xffff));
1687 return offset
| (inst
& 0x1f);
1691 int max_imm
= 1 << nbits
;
1692 int mask
= max_imm
- 1;
1693 int sign_bit
= max_imm
>> 1;
1695 offset
= inst
& mask
;
1696 if (is_signed
&& (offset
& sign_bit
))
1697 offset
= 0 - (max_imm
- offset
);
1698 return offset
* scale
;
1703 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1704 the associated FRAME_CACHE if not null.
1705 Return the address of the first instruction past the prologue. */
1708 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1709 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1710 struct frame_info
*this_frame
,
1711 struct mips_frame_cache
*this_cache
)
1714 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1716 long frame_offset
= 0; /* Size of stack frame. */
1717 long frame_adjust
= 0; /* Offset of FP from SP. */
1718 int frame_reg
= MIPS_SP_REGNUM
;
1719 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1720 unsigned inst
= 0; /* current instruction */
1721 unsigned entry_inst
= 0; /* the entry instruction */
1722 unsigned save_inst
= 0; /* the save instruction */
1725 int extend_bytes
= 0;
1726 int prev_extend_bytes
;
1727 CORE_ADDR end_prologue_addr
= 0;
1729 /* Can be called when there's no process, and hence when there's no
1731 if (this_frame
!= NULL
)
1732 sp
= get_frame_register_signed (this_frame
,
1733 gdbarch_num_regs (gdbarch
)
1738 if (limit_pc
> start_pc
+ 200)
1739 limit_pc
= start_pc
+ 200;
1741 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1743 /* Save the previous instruction. If it's an EXTEND, we'll extract
1744 the immediate offset extension from it in mips16_get_imm. */
1747 /* Fetch and decode the instruction. */
1748 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1750 /* Normally we ignore extend instructions. However, if it is
1751 not followed by a valid prologue instruction, then this
1752 instruction is not part of the prologue either. We must
1753 remember in this case to adjust the end_prologue_addr back
1755 if ((inst
& 0xf800) == 0xf000) /* extend */
1757 extend_bytes
= MIPS_INSN16_SIZE
;
1761 prev_extend_bytes
= extend_bytes
;
1764 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1765 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1767 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1768 if (offset
< 0) /* Negative stack adjustment? */
1769 frame_offset
-= offset
;
1771 /* Exit loop if a positive stack adjustment is found, which
1772 usually means that the stack cleanup code in the function
1773 epilogue is reached. */
1776 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1778 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1779 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1780 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1782 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1784 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1785 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1786 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1788 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1790 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1791 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1793 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1795 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1796 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1798 else if (inst
== 0x673d) /* move $s1, $sp */
1803 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1805 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1806 frame_addr
= sp
+ offset
;
1808 frame_adjust
= offset
;
1810 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1812 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1813 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1814 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1816 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1818 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1819 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1820 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1822 else if ((inst
& 0xf81f) == 0xe809
1823 && (inst
& 0x700) != 0x700) /* entry */
1824 entry_inst
= inst
; /* Save for later processing. */
1825 else if ((inst
& 0xff80) == 0x6480) /* save */
1827 save_inst
= inst
; /* Save for later processing. */
1828 if (prev_extend_bytes
) /* extend */
1829 save_inst
|= prev_inst
<< 16;
1831 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1832 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1833 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1835 /* This instruction is part of the prologue, but we don't
1836 need to do anything special to handle it. */
1840 /* This instruction is not an instruction typically found
1841 in a prologue, so we must have reached the end of the
1843 if (end_prologue_addr
== 0)
1844 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1848 /* The entry instruction is typically the first instruction in a function,
1849 and it stores registers at offsets relative to the value of the old SP
1850 (before the prologue). But the value of the sp parameter to this
1851 function is the new SP (after the prologue has been executed). So we
1852 can't calculate those offsets until we've seen the entire prologue,
1853 and can calculate what the old SP must have been. */
1854 if (entry_inst
!= 0)
1856 int areg_count
= (entry_inst
>> 8) & 7;
1857 int sreg_count
= (entry_inst
>> 6) & 3;
1859 /* The entry instruction always subtracts 32 from the SP. */
1862 /* Now we can calculate what the SP must have been at the
1863 start of the function prologue. */
1866 /* Check if a0-a3 were saved in the caller's argument save area. */
1867 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1869 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1870 offset
+= mips_abi_regsize (gdbarch
);
1873 /* Check if the ra register was pushed on the stack. */
1875 if (entry_inst
& 0x20)
1877 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1878 offset
-= mips_abi_regsize (gdbarch
);
1881 /* Check if the s0 and s1 registers were pushed on the stack. */
1882 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1884 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1885 offset
-= mips_abi_regsize (gdbarch
);
1889 /* The SAVE instruction is similar to ENTRY, except that defined by the
1890 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1891 size of the frame is specified as an immediate field of instruction
1892 and an extended variation exists which lets additional registers and
1893 frame space to be specified. The instruction always treats registers
1894 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1895 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1897 static int args_table
[16] = {
1898 0, 0, 0, 0, 1, 1, 1, 1,
1899 2, 2, 2, 0, 3, 3, 4, -1,
1901 static int astatic_table
[16] = {
1902 0, 1, 2, 3, 0, 1, 2, 3,
1903 0, 1, 2, 4, 0, 1, 0, -1,
1905 int aregs
= (save_inst
>> 16) & 0xf;
1906 int xsregs
= (save_inst
>> 24) & 0x7;
1907 int args
= args_table
[aregs
];
1908 int astatic
= astatic_table
[aregs
];
1913 warning (_("Invalid number of argument registers encoded in SAVE."));
1918 warning (_("Invalid number of static registers encoded in SAVE."));
1922 /* For standard SAVE the frame size of 0 means 128. */
1923 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1924 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1927 frame_offset
+= frame_size
;
1929 /* Now we can calculate what the SP must have been at the
1930 start of the function prologue. */
1933 /* Check if A0-A3 were saved in the caller's argument save area. */
1934 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1936 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1937 offset
+= mips_abi_regsize (gdbarch
);
1942 /* Check if the RA register was pushed on the stack. */
1943 if (save_inst
& 0x40)
1945 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1946 offset
-= mips_abi_regsize (gdbarch
);
1949 /* Check if the S8 register was pushed on the stack. */
1952 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1953 offset
-= mips_abi_regsize (gdbarch
);
1956 /* Check if S2-S7 were pushed on the stack. */
1957 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1959 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1960 offset
-= mips_abi_regsize (gdbarch
);
1963 /* Check if the S1 register was pushed on the stack. */
1964 if (save_inst
& 0x10)
1966 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1967 offset
-= mips_abi_regsize (gdbarch
);
1969 /* Check if the S0 register was pushed on the stack. */
1970 if (save_inst
& 0x20)
1972 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1973 offset
-= mips_abi_regsize (gdbarch
);
1976 /* Check if A0-A3 were pushed on the stack. */
1977 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1979 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1980 offset
-= mips_abi_regsize (gdbarch
);
1984 if (this_cache
!= NULL
)
1987 (get_frame_register_signed (this_frame
,
1988 gdbarch_num_regs (gdbarch
) + frame_reg
)
1989 + frame_offset
- frame_adjust
);
1990 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1991 be able to get rid of the assignment below, evetually. But it's
1992 still needed for now. */
1993 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1994 + mips_regnum (gdbarch
)->pc
]
1995 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1998 /* If we didn't reach the end of the prologue when scanning the function
1999 instructions, then set end_prologue_addr to the address of the
2000 instruction immediately after the last one we scanned. */
2001 if (end_prologue_addr
== 0)
2002 end_prologue_addr
= cur_pc
;
2004 return end_prologue_addr
;
2007 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2008 Procedures that use the 32-bit instruction set are handled by the
2009 mips_insn32 unwinder. */
2011 static struct mips_frame_cache
*
2012 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2014 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2015 struct mips_frame_cache
*cache
;
2017 if ((*this_cache
) != NULL
)
2018 return (*this_cache
);
2019 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2020 (*this_cache
) = cache
;
2021 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2023 /* Analyze the function prologue. */
2025 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2026 CORE_ADDR start_addr
;
2028 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2029 if (start_addr
== 0)
2030 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2031 /* We can't analyze the prologue if we couldn't find the begining
2033 if (start_addr
== 0)
2036 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2039 /* gdbarch_sp_regnum contains the value and not the address. */
2040 trad_frame_set_value (cache
->saved_regs
,
2041 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2044 return (*this_cache
);
2048 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2049 struct frame_id
*this_id
)
2051 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2053 /* This marks the outermost frame. */
2054 if (info
->base
== 0)
2056 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2059 static struct value
*
2060 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2061 void **this_cache
, int regnum
)
2063 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2065 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2069 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2070 struct frame_info
*this_frame
, void **this_cache
)
2072 CORE_ADDR pc
= get_frame_pc (this_frame
);
2073 if (mips_pc_is_mips16 (pc
))
2078 static const struct frame_unwind mips_insn16_frame_unwind
=
2081 default_frame_unwind_stop_reason
,
2082 mips_insn16_frame_this_id
,
2083 mips_insn16_frame_prev_register
,
2085 mips_insn16_frame_sniffer
2089 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2092 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2097 static const struct frame_base mips_insn16_frame_base
=
2099 &mips_insn16_frame_unwind
,
2100 mips_insn16_frame_base_address
,
2101 mips_insn16_frame_base_address
,
2102 mips_insn16_frame_base_address
2105 static const struct frame_base
*
2106 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2108 CORE_ADDR pc
= get_frame_pc (this_frame
);
2109 if (mips_pc_is_mips16 (pc
))
2110 return &mips_insn16_frame_base
;
2115 /* Mark all the registers as unset in the saved_regs array
2116 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2119 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2121 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2125 const int num_regs
= gdbarch_num_regs (gdbarch
);
2128 for (i
= 0; i
< num_regs
; i
++)
2130 this_cache
->saved_regs
[i
].addr
= -1;
2135 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2136 the associated FRAME_CACHE if not null.
2137 Return the address of the first instruction past the prologue. */
2140 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2141 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2142 struct frame_info
*this_frame
,
2143 struct mips_frame_cache
*this_cache
)
2146 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2150 int frame_reg
= MIPS_SP_REGNUM
;
2152 CORE_ADDR end_prologue_addr
= 0;
2153 int seen_sp_adjust
= 0;
2154 int load_immediate_bytes
= 0;
2155 int in_delay_slot
= 0;
2156 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2158 /* Can be called when there's no process, and hence when there's no
2160 if (this_frame
!= NULL
)
2161 sp
= get_frame_register_signed (this_frame
,
2162 gdbarch_num_regs (gdbarch
)
2167 if (limit_pc
> start_pc
+ 200)
2168 limit_pc
= start_pc
+ 200;
2173 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2175 unsigned long inst
, high_word
, low_word
;
2178 /* Fetch the instruction. */
2179 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2181 /* Save some code by pre-extracting some useful fields. */
2182 high_word
= (inst
>> 16) & 0xffff;
2183 low_word
= inst
& 0xffff;
2184 reg
= high_word
& 0x1f;
2186 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2187 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2188 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2190 if (low_word
& 0x8000) /* Negative stack adjustment? */
2191 frame_offset
+= 0x10000 - low_word
;
2193 /* Exit loop if a positive stack adjustment is found, which
2194 usually means that the stack cleanup code in the function
2195 epilogue is reached. */
2199 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2200 && !regsize_is_64_bits
)
2202 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2204 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2205 && regsize_is_64_bits
)
2207 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2208 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2210 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2212 /* Old gcc frame, r30 is virtual frame pointer. */
2213 if ((long) low_word
!= frame_offset
)
2214 frame_addr
= sp
+ low_word
;
2215 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2217 unsigned alloca_adjust
;
2220 frame_addr
= get_frame_register_signed
2221 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2223 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2224 if (alloca_adjust
> 0)
2226 /* FP > SP + frame_size. This may be because of
2227 an alloca or somethings similar. Fix sp to
2228 "pre-alloca" value, and try again. */
2229 sp
+= alloca_adjust
;
2230 /* Need to reset the status of all registers. Otherwise,
2231 we will hit a guard that prevents the new address
2232 for each register to be recomputed during the second
2234 reset_saved_regs (gdbarch
, this_cache
);
2239 /* move $30,$sp. With different versions of gas this will be either
2240 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2241 Accept any one of these. */
2242 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2244 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2245 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2247 unsigned alloca_adjust
;
2250 frame_addr
= get_frame_register_signed
2251 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2253 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2254 if (alloca_adjust
> 0)
2256 /* FP > SP + frame_size. This may be because of
2257 an alloca or somethings similar. Fix sp to
2258 "pre-alloca" value, and try again. */
2260 /* Need to reset the status of all registers. Otherwise,
2261 we will hit a guard that prevents the new address
2262 for each register to be recomputed during the second
2264 reset_saved_regs (gdbarch
, this_cache
);
2269 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2270 && !regsize_is_64_bits
)
2272 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2274 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2275 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2276 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2277 || high_word
== 0x3c1c /* lui $gp,n */
2278 || high_word
== 0x279c /* addiu $gp,$gp,n */
2279 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2280 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2283 /* These instructions are part of the prologue, but we don't
2284 need to do anything special to handle them. */
2286 /* The instructions below load $at or $t0 with an immediate
2287 value in preparation for a stack adjustment via
2288 subu $sp,$sp,[$at,$t0]. These instructions could also
2289 initialize a local variable, so we accept them only before
2290 a stack adjustment instruction was seen. */
2291 else if (!seen_sp_adjust
2292 && (high_word
== 0x3c01 /* lui $at,n */
2293 || high_word
== 0x3c08 /* lui $t0,n */
2294 || high_word
== 0x3421 /* ori $at,$at,n */
2295 || high_word
== 0x3508 /* ori $t0,$t0,n */
2296 || high_word
== 0x3401 /* ori $at,$zero,n */
2297 || high_word
== 0x3408 /* ori $t0,$zero,n */
2300 if (end_prologue_addr
== 0)
2301 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2305 /* This instruction is not an instruction typically found
2306 in a prologue, so we must have reached the end of the
2308 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2309 loop now? Why would we need to continue scanning the function
2311 if (end_prologue_addr
== 0)
2312 end_prologue_addr
= cur_pc
;
2314 /* Check for branches and jumps. For now, only jump to
2315 register are caught (i.e. returns). */
2316 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2320 /* If the previous instruction was a jump, we must have reached
2321 the end of the prologue by now. Stop scanning so that we do
2322 not go past the function return. */
2327 if (this_cache
!= NULL
)
2330 (get_frame_register_signed (this_frame
,
2331 gdbarch_num_regs (gdbarch
) + frame_reg
)
2333 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2334 this assignment below, eventually. But it's still needed
2336 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2337 + mips_regnum (gdbarch
)->pc
]
2338 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2342 /* If we didn't reach the end of the prologue when scanning the function
2343 instructions, then set end_prologue_addr to the address of the
2344 instruction immediately after the last one we scanned. */
2345 /* brobecker/2004-10-10: I don't think this would ever happen, but
2346 we may as well be careful and do our best if we have a null
2347 end_prologue_addr. */
2348 if (end_prologue_addr
== 0)
2349 end_prologue_addr
= cur_pc
;
2351 /* In a frameless function, we might have incorrectly
2352 skipped some load immediate instructions. Undo the skipping
2353 if the load immediate was not followed by a stack adjustment. */
2354 if (load_immediate_bytes
&& !seen_sp_adjust
)
2355 end_prologue_addr
-= load_immediate_bytes
;
2357 return end_prologue_addr
;
2360 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2361 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2362 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2365 static struct mips_frame_cache
*
2366 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2368 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2369 struct mips_frame_cache
*cache
;
2371 if ((*this_cache
) != NULL
)
2372 return (*this_cache
);
2374 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2375 (*this_cache
) = cache
;
2376 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2378 /* Analyze the function prologue. */
2380 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2381 CORE_ADDR start_addr
;
2383 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2384 if (start_addr
== 0)
2385 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2386 /* We can't analyze the prologue if we couldn't find the begining
2388 if (start_addr
== 0)
2391 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2394 /* gdbarch_sp_regnum contains the value and not the address. */
2395 trad_frame_set_value (cache
->saved_regs
,
2396 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2399 return (*this_cache
);
2403 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2404 struct frame_id
*this_id
)
2406 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2408 /* This marks the outermost frame. */
2409 if (info
->base
== 0)
2411 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2414 static struct value
*
2415 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2416 void **this_cache
, int regnum
)
2418 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2420 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2424 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2425 struct frame_info
*this_frame
, void **this_cache
)
2427 CORE_ADDR pc
= get_frame_pc (this_frame
);
2428 if (! mips_pc_is_mips16 (pc
))
2433 static const struct frame_unwind mips_insn32_frame_unwind
=
2436 default_frame_unwind_stop_reason
,
2437 mips_insn32_frame_this_id
,
2438 mips_insn32_frame_prev_register
,
2440 mips_insn32_frame_sniffer
2444 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2447 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2452 static const struct frame_base mips_insn32_frame_base
=
2454 &mips_insn32_frame_unwind
,
2455 mips_insn32_frame_base_address
,
2456 mips_insn32_frame_base_address
,
2457 mips_insn32_frame_base_address
2460 static const struct frame_base
*
2461 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2463 CORE_ADDR pc
= get_frame_pc (this_frame
);
2464 if (! mips_pc_is_mips16 (pc
))
2465 return &mips_insn32_frame_base
;
2470 static struct trad_frame_cache
*
2471 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2474 CORE_ADDR start_addr
;
2475 CORE_ADDR stack_addr
;
2476 struct trad_frame_cache
*this_trad_cache
;
2477 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2478 int num_regs
= gdbarch_num_regs (gdbarch
);
2480 if ((*this_cache
) != NULL
)
2481 return (*this_cache
);
2482 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2483 (*this_cache
) = this_trad_cache
;
2485 /* The return address is in the link register. */
2486 trad_frame_set_reg_realreg (this_trad_cache
,
2487 gdbarch_pc_regnum (gdbarch
),
2488 num_regs
+ MIPS_RA_REGNUM
);
2490 /* Frame ID, since it's a frameless / stackless function, no stack
2491 space is allocated and SP on entry is the current SP. */
2492 pc
= get_frame_pc (this_frame
);
2493 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2494 stack_addr
= get_frame_register_signed (this_frame
,
2495 num_regs
+ MIPS_SP_REGNUM
);
2496 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2498 /* Assume that the frame's base is the same as the
2500 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2502 return this_trad_cache
;
2506 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2507 struct frame_id
*this_id
)
2509 struct trad_frame_cache
*this_trad_cache
2510 = mips_stub_frame_cache (this_frame
, this_cache
);
2511 trad_frame_get_id (this_trad_cache
, this_id
);
2514 static struct value
*
2515 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2516 void **this_cache
, int regnum
)
2518 struct trad_frame_cache
*this_trad_cache
2519 = mips_stub_frame_cache (this_frame
, this_cache
);
2520 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2524 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2525 struct frame_info
*this_frame
, void **this_cache
)
2528 struct obj_section
*s
;
2529 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2530 struct minimal_symbol
*msym
;
2532 /* Use the stub unwinder for unreadable code. */
2533 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2536 if (in_plt_section (pc
, NULL
))
2539 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2540 s
= find_pc_section (pc
);
2543 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2544 ".MIPS.stubs") == 0)
2547 /* Calling a PIC function from a non-PIC function passes through a
2548 stub. The stub for foo is named ".pic.foo". */
2549 msym
= lookup_minimal_symbol_by_pc (pc
);
2551 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2552 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2558 static const struct frame_unwind mips_stub_frame_unwind
=
2561 default_frame_unwind_stop_reason
,
2562 mips_stub_frame_this_id
,
2563 mips_stub_frame_prev_register
,
2565 mips_stub_frame_sniffer
2569 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2572 struct trad_frame_cache
*this_trad_cache
2573 = mips_stub_frame_cache (this_frame
, this_cache
);
2574 return trad_frame_get_this_base (this_trad_cache
);
2577 static const struct frame_base mips_stub_frame_base
=
2579 &mips_stub_frame_unwind
,
2580 mips_stub_frame_base_address
,
2581 mips_stub_frame_base_address
,
2582 mips_stub_frame_base_address
2585 static const struct frame_base
*
2586 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2588 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2589 return &mips_stub_frame_base
;
2594 /* mips_addr_bits_remove - remove useless address bits */
2597 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2599 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2601 if (is_mips16_addr (addr
))
2602 addr
= unmake_mips16_addr (addr
);
2604 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2605 /* This hack is a work-around for existing boards using PMON, the
2606 simulator, and any other 64-bit targets that doesn't have true
2607 64-bit addressing. On these targets, the upper 32 bits of
2608 addresses are ignored by the hardware. Thus, the PC or SP are
2609 likely to have been sign extended to all 1s by instruction
2610 sequences that load 32-bit addresses. For example, a typical
2611 piece of code that loads an address is this:
2613 lui $r2, <upper 16 bits>
2614 ori $r2, <lower 16 bits>
2616 But the lui sign-extends the value such that the upper 32 bits
2617 may be all 1s. The workaround is simply to mask off these
2618 bits. In the future, gcc may be changed to support true 64-bit
2619 addressing, and this masking will have to be disabled. */
2620 return addr
&= 0xffffffffUL
;
2625 /* Instructions used during single-stepping of atomic sequences. */
2626 #define LL_OPCODE 0x30
2627 #define LLD_OPCODE 0x34
2628 #define SC_OPCODE 0x38
2629 #define SCD_OPCODE 0x3c
2631 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2632 instruction and ending with a SC/SCD instruction. If such a sequence
2633 is found, attempt to step through it. A breakpoint is placed at the end of
2637 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2638 struct address_space
*aspace
, CORE_ADDR pc
)
2640 CORE_ADDR breaks
[2] = {-1, -1};
2642 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2646 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2647 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2652 insn
= mips_fetch_instruction (gdbarch
, loc
);
2653 /* Assume all atomic sequences start with a ll/lld instruction. */
2654 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2657 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2659 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2662 loc
+= MIPS_INSN32_SIZE
;
2663 insn
= mips_fetch_instruction (gdbarch
, loc
);
2665 /* Assume that there is at most one branch in the atomic
2666 sequence. If a branch is found, put a breakpoint in its
2667 destination address. */
2668 switch (itype_op (insn
))
2670 case 0: /* SPECIAL */
2671 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2672 return 0; /* fallback to the standard single-step code. */
2674 case 1: /* REGIMM */
2675 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
2676 || ((itype_rt (insn
) & 0x1e) == 0
2677 && itype_rs (insn
) == 0)); /* BPOSGE* */
2681 return 0; /* fallback to the standard single-step code. */
2688 case 22: /* BLEZL */
2689 case 23: /* BGTTL */
2693 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
2694 && (itype_rt (insn
) & 0x2) == 0);
2695 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
2700 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2705 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2706 if (last_breakpoint
>= 1)
2707 return 0; /* More than one branch found, fallback to the
2708 standard single-step code. */
2709 breaks
[1] = branch_bp
;
2713 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2717 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2718 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2721 loc
+= MIPS_INSN32_SIZE
;
2723 /* Insert a breakpoint right after the end of the atomic sequence. */
2726 /* Check for duplicated breakpoints. Check also for a breakpoint
2727 placed (branch instruction's destination) in the atomic sequence. */
2728 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2729 last_breakpoint
= 0;
2731 /* Effectively inserts the breakpoints. */
2732 for (index
= 0; index
<= last_breakpoint
; index
++)
2733 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2738 /* mips_software_single_step() is called just before we want to resume
2739 the inferior, if we want to single-step it but there is no hardware
2740 or kernel single-step support (MIPS on GNU/Linux for example). We find
2741 the target of the coming instruction and breakpoint it. */
2744 mips_software_single_step (struct frame_info
*frame
)
2746 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2747 struct address_space
*aspace
= get_frame_address_space (frame
);
2748 CORE_ADDR pc
, next_pc
;
2750 pc
= get_frame_pc (frame
);
2751 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2754 next_pc
= mips_next_pc (frame
, pc
);
2756 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2760 /* Test whether the PC points to the return instruction at the
2761 end of a function. */
2764 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2766 if (mips_pc_is_mips16 (pc
))
2767 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2768 generates a "jr $ra"; other times it generates code to load
2769 the return address from the stack to an accessible register (such
2770 as $a3), then a "jr" using that register. This second case
2771 is almost impossible to distinguish from an indirect jump
2772 used for switch statements, so we don't even try. */
2773 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2775 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2779 /* This fencepost looks highly suspicious to me. Removing it also
2780 seems suspicious as it could affect remote debugging across serial
2784 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2790 struct inferior
*inf
;
2792 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2794 fence
= start_pc
- heuristic_fence_post
;
2798 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2799 fence
= VM_MIN_ADDRESS
;
2801 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2803 inf
= current_inferior ();
2805 /* Search back for previous return. */
2806 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2807 if (start_pc
< fence
)
2809 /* It's not clear to me why we reach this point when
2810 stop_soon, but with this test, at least we
2811 don't print out warnings for every child forked (eg, on
2812 decstation). 22apr93 rich@cygnus.com. */
2813 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2815 static int blurb_printed
= 0;
2817 warning (_("GDB can't find the start of the function at %s."),
2818 paddress (gdbarch
, pc
));
2822 /* This actually happens frequently in embedded
2823 development, when you first connect to a board
2824 and your stack pointer and pc are nowhere in
2825 particular. This message needs to give people
2826 in that situation enough information to
2827 determine that it's no big deal. */
2828 printf_filtered ("\n\
2829 GDB is unable to find the start of the function at %s\n\
2830 and thus can't determine the size of that function's stack frame.\n\
2831 This means that GDB may be unable to access that stack frame, or\n\
2832 the frames below it.\n\
2833 This problem is most likely caused by an invalid program counter or\n\
2835 However, if you think GDB should simply search farther back\n\
2836 from %s for code which looks like the beginning of a\n\
2837 function, you can increase the range of the search using the `set\n\
2838 heuristic-fence-post' command.\n",
2839 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2846 else if (mips_pc_is_mips16 (start_pc
))
2848 unsigned short inst
;
2850 /* On MIPS16, any one of the following is likely to be the
2851 start of a function:
2857 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2858 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2859 if ((inst
& 0xff80) == 0x6480) /* save */
2861 if (start_pc
- instlen
>= fence
)
2863 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2864 if ((inst
& 0xf800) == 0xf000) /* extend */
2865 start_pc
-= instlen
;
2869 else if (((inst
& 0xf81f) == 0xe809
2870 && (inst
& 0x700) != 0x700) /* entry */
2871 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2872 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2873 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2875 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2876 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2881 else if (mips_about_to_return (gdbarch
, start_pc
))
2883 /* Skip return and its delay slot. */
2884 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2891 struct mips_objfile_private
2897 /* According to the current ABI, should the type be passed in a
2898 floating-point register (assuming that there is space)? When there
2899 is no FPU, FP are not even considered as possible candidates for
2900 FP registers and, consequently this returns false - forces FP
2901 arguments into integer registers. */
2904 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2905 struct type
*arg_type
)
2907 return ((typecode
== TYPE_CODE_FLT
2908 || (MIPS_EABI (gdbarch
)
2909 && (typecode
== TYPE_CODE_STRUCT
2910 || typecode
== TYPE_CODE_UNION
)
2911 && TYPE_NFIELDS (arg_type
) == 1
2912 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2914 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2917 /* On o32, argument passing in GPRs depends on the alignment of the type being
2918 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2921 mips_type_needs_double_align (struct type
*type
)
2923 enum type_code typecode
= TYPE_CODE (type
);
2925 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2927 else if (typecode
== TYPE_CODE_STRUCT
)
2929 if (TYPE_NFIELDS (type
) < 1)
2931 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2933 else if (typecode
== TYPE_CODE_UNION
)
2937 n
= TYPE_NFIELDS (type
);
2938 for (i
= 0; i
< n
; i
++)
2939 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2946 /* Adjust the address downward (direction of stack growth) so that it
2947 is correctly aligned for a new stack frame. */
2949 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2951 return align_down (addr
, 16);
2955 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2956 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2957 int nargs
, struct value
**args
, CORE_ADDR sp
,
2958 int struct_return
, CORE_ADDR struct_addr
)
2964 int stack_offset
= 0;
2965 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2966 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2967 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2968 int regsize
= mips_abi_regsize (gdbarch
);
2970 /* For shared libraries, "t9" needs to point at the function
2972 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2974 /* Set the return address register to point to the entry point of
2975 the program, where a breakpoint lies in wait. */
2976 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2978 /* First ensure that the stack and structure return address (if any)
2979 are properly aligned. The stack has to be at least 64-bit
2980 aligned even on 32-bit machines, because doubles must be 64-bit
2981 aligned. For n32 and n64, stack frames need to be 128-bit
2982 aligned, so we round to this widest known alignment. */
2984 sp
= align_down (sp
, 16);
2985 struct_addr
= align_down (struct_addr
, 16);
2987 /* Now make space on the stack for the args. We allocate more
2988 than necessary for EABI, because the first few arguments are
2989 passed in registers, but that's OK. */
2990 for (argnum
= 0; argnum
< nargs
; argnum
++)
2991 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2992 sp
-= align_up (len
, 16);
2995 fprintf_unfiltered (gdb_stdlog
,
2996 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2997 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2999 /* Initialize the integer and float register pointers. */
3000 argreg
= MIPS_A0_REGNUM
;
3001 float_argreg
= mips_fpa0_regnum (gdbarch
);
3003 /* The struct_return pointer occupies the first parameter-passing reg. */
3007 fprintf_unfiltered (gdb_stdlog
,
3008 "mips_eabi_push_dummy_call: "
3009 "struct_return reg=%d %s\n",
3010 argreg
, paddress (gdbarch
, struct_addr
));
3011 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3014 /* Now load as many as possible of the first arguments into
3015 registers, and push the rest onto the stack. Loop thru args
3016 from first to last. */
3017 for (argnum
= 0; argnum
< nargs
; argnum
++)
3019 const gdb_byte
*val
;
3020 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
3021 struct value
*arg
= args
[argnum
];
3022 struct type
*arg_type
= check_typedef (value_type (arg
));
3023 int len
= TYPE_LENGTH (arg_type
);
3024 enum type_code typecode
= TYPE_CODE (arg_type
);
3027 fprintf_unfiltered (gdb_stdlog
,
3028 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3029 argnum
+ 1, len
, (int) typecode
);
3031 /* Function pointer arguments to mips16 code need to be made into
3033 if (typecode
== TYPE_CODE_PTR
3034 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
3036 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
3038 if (mips_pc_is_mips16 (addr
))
3040 store_signed_integer (valbuf
, len
, byte_order
,
3041 make_mips16_addr (addr
));
3045 val
= value_contents (arg
);
3047 /* The EABI passes structures that do not fit in a register by
3049 else if (len
> regsize
3050 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3052 store_unsigned_integer (valbuf
, regsize
, byte_order
,
3053 value_address (arg
));
3054 typecode
= TYPE_CODE_PTR
;
3058 fprintf_unfiltered (gdb_stdlog
, " push");
3061 val
= value_contents (arg
);
3063 /* 32-bit ABIs always start floating point arguments in an
3064 even-numbered floating point register. Round the FP register
3065 up before the check to see if there are any FP registers
3066 left. Non MIPS_EABI targets also pass the FP in the integer
3067 registers so also round up normal registers. */
3068 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3070 if ((float_argreg
& 1))
3074 /* Floating point arguments passed in registers have to be
3075 treated specially. On 32-bit architectures, doubles
3076 are passed in register pairs; the even register gets
3077 the low word, and the odd register gets the high word.
3078 On non-EABI processors, the first two floating point arguments are
3079 also copied to general registers, because MIPS16 functions
3080 don't use float registers for arguments. This duplication of
3081 arguments in general registers can't hurt non-MIPS16 functions
3082 because those registers are normally skipped. */
3083 /* MIPS_EABI squeezes a struct that contains a single floating
3084 point value into an FP register instead of pushing it onto the
3086 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3087 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3089 /* EABI32 will pass doubles in consecutive registers, even on
3090 64-bit cores. At one time, we used to check the size of
3091 `float_argreg' to determine whether or not to pass doubles
3092 in consecutive registers, but this is not sufficient for
3093 making the ABI determination. */
3094 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3096 int low_offset
= gdbarch_byte_order (gdbarch
)
3097 == BFD_ENDIAN_BIG
? 4 : 0;
3100 /* Write the low word of the double to the even register(s). */
3101 regval
= extract_signed_integer (val
+ low_offset
,
3104 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3105 float_argreg
, phex (regval
, 4));
3106 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3108 /* Write the high word of the double to the odd register(s). */
3109 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3112 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3113 float_argreg
, phex (regval
, 4));
3114 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3118 /* This is a floating point value that fits entirely
3119 in a single register. */
3120 /* On 32 bit ABI's the float_argreg is further adjusted
3121 above to ensure that it is even register aligned. */
3122 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3124 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3125 float_argreg
, phex (regval
, len
));
3126 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3131 /* Copy the argument to general registers or the stack in
3132 register-sized pieces. Large arguments are split between
3133 registers and stack. */
3134 /* Note: structs whose size is not a multiple of regsize
3135 are treated specially: Irix cc passes
3136 them in registers where gcc sometimes puts them on the
3137 stack. For maximum compatibility, we will put them in
3139 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3141 /* Note: Floating-point values that didn't fit into an FP
3142 register are only written to memory. */
3145 /* Remember if the argument was written to the stack. */
3146 int stack_used_p
= 0;
3147 int partial_len
= (len
< regsize
? len
: regsize
);
3150 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3153 /* Write this portion of the argument to the stack. */
3154 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3156 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3158 /* Should shorter than int integer values be
3159 promoted to int before being stored? */
3160 int longword_offset
= 0;
3163 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3166 && (typecode
== TYPE_CODE_INT
3167 || typecode
== TYPE_CODE_PTR
3168 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3169 longword_offset
= regsize
- len
;
3170 else if ((typecode
== TYPE_CODE_STRUCT
3171 || typecode
== TYPE_CODE_UNION
)
3172 && TYPE_LENGTH (arg_type
) < regsize
)
3173 longword_offset
= regsize
- len
;
3178 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3179 paddress (gdbarch
, stack_offset
));
3180 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3181 paddress (gdbarch
, longword_offset
));
3184 addr
= sp
+ stack_offset
+ longword_offset
;
3189 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3190 paddress (gdbarch
, addr
));
3191 for (i
= 0; i
< partial_len
; i
++)
3193 fprintf_unfiltered (gdb_stdlog
, "%02x",
3197 write_memory (addr
, val
, partial_len
);
3200 /* Note!!! This is NOT an else clause. Odd sized
3201 structs may go thru BOTH paths. Floating point
3202 arguments will not. */
3203 /* Write this portion of the argument to a general
3204 purpose register. */
3205 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3206 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3209 extract_signed_integer (val
, partial_len
, byte_order
);
3212 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3214 phex (regval
, regsize
));
3215 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3222 /* Compute the offset into the stack at which we will
3223 copy the next parameter.
3225 In the new EABI (and the NABI32), the stack_offset
3226 only needs to be adjusted when it has been used. */
3229 stack_offset
+= align_up (partial_len
, regsize
);
3233 fprintf_unfiltered (gdb_stdlog
, "\n");
3236 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3238 /* Return adjusted stack pointer. */
3242 /* Determine the return value convention being used. */
3244 static enum return_value_convention
3245 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3246 struct type
*type
, struct regcache
*regcache
,
3247 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3249 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3250 int fp_return_type
= 0;
3251 int offset
, regnum
, xfer
;
3253 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3254 return RETURN_VALUE_STRUCT_CONVENTION
;
3256 /* Floating point type? */
3257 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3259 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3261 /* Structs with a single field of float type
3262 are returned in a floating point register. */
3263 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3264 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3265 && TYPE_NFIELDS (type
) == 1)
3267 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3269 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3276 /* A floating-point value belongs in the least significant part
3279 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3280 regnum
= mips_regnum (gdbarch
)->fp0
;
3284 /* An integer value goes in V0/V1. */
3286 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3287 regnum
= MIPS_V0_REGNUM
;
3290 offset
< TYPE_LENGTH (type
);
3291 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3293 xfer
= mips_abi_regsize (gdbarch
);
3294 if (offset
+ xfer
> TYPE_LENGTH (type
))
3295 xfer
= TYPE_LENGTH (type
) - offset
;
3296 mips_xfer_register (gdbarch
, regcache
,
3297 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3298 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3302 return RETURN_VALUE_REGISTER_CONVENTION
;
3306 /* N32/N64 ABI stuff. */
3308 /* Search for a naturally aligned double at OFFSET inside a struct
3309 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3313 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3318 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3321 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3324 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3327 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3330 struct type
*field_type
;
3332 /* We're only looking at normal fields. */
3333 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3334 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3337 /* If we have gone past the offset, there is no double to pass. */
3338 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3342 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3344 /* If this field is entirely before the requested offset, go
3345 on to the next one. */
3346 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3349 /* If this is our special aligned double, we can stop. */
3350 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3351 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3354 /* This field starts at or before the requested offset, and
3355 overlaps it. If it is a structure, recurse inwards. */
3356 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3363 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3364 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3365 int nargs
, struct value
**args
, CORE_ADDR sp
,
3366 int struct_return
, CORE_ADDR struct_addr
)
3372 int stack_offset
= 0;
3373 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3374 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3375 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3377 /* For shared libraries, "t9" needs to point at the function
3379 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3381 /* Set the return address register to point to the entry point of
3382 the program, where a breakpoint lies in wait. */
3383 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3385 /* First ensure that the stack and structure return address (if any)
3386 are properly aligned. The stack has to be at least 64-bit
3387 aligned even on 32-bit machines, because doubles must be 64-bit
3388 aligned. For n32 and n64, stack frames need to be 128-bit
3389 aligned, so we round to this widest known alignment. */
3391 sp
= align_down (sp
, 16);
3392 struct_addr
= align_down (struct_addr
, 16);
3394 /* Now make space on the stack for the args. */
3395 for (argnum
= 0; argnum
< nargs
; argnum
++)
3396 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3397 sp
-= align_up (len
, 16);
3400 fprintf_unfiltered (gdb_stdlog
,
3401 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3402 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3404 /* Initialize the integer and float register pointers. */
3405 argreg
= MIPS_A0_REGNUM
;
3406 float_argreg
= mips_fpa0_regnum (gdbarch
);
3408 /* The struct_return pointer occupies the first parameter-passing reg. */
3412 fprintf_unfiltered (gdb_stdlog
,
3413 "mips_n32n64_push_dummy_call: "
3414 "struct_return reg=%d %s\n",
3415 argreg
, paddress (gdbarch
, struct_addr
));
3416 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3419 /* Now load as many as possible of the first arguments into
3420 registers, and push the rest onto the stack. Loop thru args
3421 from first to last. */
3422 for (argnum
= 0; argnum
< nargs
; argnum
++)
3424 const gdb_byte
*val
;
3425 struct value
*arg
= args
[argnum
];
3426 struct type
*arg_type
= check_typedef (value_type (arg
));
3427 int len
= TYPE_LENGTH (arg_type
);
3428 enum type_code typecode
= TYPE_CODE (arg_type
);
3431 fprintf_unfiltered (gdb_stdlog
,
3432 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3433 argnum
+ 1, len
, (int) typecode
);
3435 val
= value_contents (arg
);
3437 /* A 128-bit long double value requires an even-odd pair of
3438 floating-point registers. */
3440 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3441 && (float_argreg
& 1))
3447 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3448 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3450 /* This is a floating point value that fits entirely
3451 in a single register or a pair of registers. */
3452 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3453 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3455 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3456 float_argreg
, phex (regval
, reglen
));
3457 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3460 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3461 argreg
, phex (regval
, reglen
));
3462 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3467 regval
= extract_unsigned_integer (val
+ reglen
,
3468 reglen
, byte_order
);
3470 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3471 float_argreg
, phex (regval
, reglen
));
3472 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3475 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3476 argreg
, phex (regval
, reglen
));
3477 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3484 /* Copy the argument to general registers or the stack in
3485 register-sized pieces. Large arguments are split between
3486 registers and stack. */
3487 /* For N32/N64, structs, unions, or other composite types are
3488 treated as a sequence of doublewords, and are passed in integer
3489 or floating point registers as though they were simple scalar
3490 parameters to the extent that they fit, with any excess on the
3491 stack packed according to the normal memory layout of the
3493 The caller does not reserve space for the register arguments;
3494 the callee is responsible for reserving it if required. */
3495 /* Note: Floating-point values that didn't fit into an FP
3496 register are only written to memory. */
3499 /* Remember if the argument was written to the stack. */
3500 int stack_used_p
= 0;
3501 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3504 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3507 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3508 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3510 /* Write this portion of the argument to the stack. */
3511 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3513 /* Should shorter than int integer values be
3514 promoted to int before being stored? */
3515 int longword_offset
= 0;
3518 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3520 if ((typecode
== TYPE_CODE_INT
3521 || typecode
== TYPE_CODE_PTR
)
3523 longword_offset
= MIPS64_REGSIZE
- len
;
3528 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3529 paddress (gdbarch
, stack_offset
));
3530 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3531 paddress (gdbarch
, longword_offset
));
3534 addr
= sp
+ stack_offset
+ longword_offset
;
3539 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3540 paddress (gdbarch
, addr
));
3541 for (i
= 0; i
< partial_len
; i
++)
3543 fprintf_unfiltered (gdb_stdlog
, "%02x",
3547 write_memory (addr
, val
, partial_len
);
3550 /* Note!!! This is NOT an else clause. Odd sized
3551 structs may go thru BOTH paths. */
3552 /* Write this portion of the argument to a general
3553 purpose register. */
3554 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3558 /* Sign extend pointers, 32-bit integers and signed
3559 16-bit and 8-bit integers; everything else is taken
3562 if ((partial_len
== 4
3563 && (typecode
== TYPE_CODE_PTR
3564 || typecode
== TYPE_CODE_INT
))
3566 && typecode
== TYPE_CODE_INT
3567 && !TYPE_UNSIGNED (arg_type
)))
3568 regval
= extract_signed_integer (val
, partial_len
,
3571 regval
= extract_unsigned_integer (val
, partial_len
,
3574 /* A non-floating-point argument being passed in a
3575 general register. If a struct or union, and if
3576 the remaining length is smaller than the register
3577 size, we have to adjust the register value on
3580 It does not seem to be necessary to do the
3581 same for integral types. */
3583 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3584 && partial_len
< MIPS64_REGSIZE
3585 && (typecode
== TYPE_CODE_STRUCT
3586 || typecode
== TYPE_CODE_UNION
))
3587 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3591 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3593 phex (regval
, MIPS64_REGSIZE
));
3594 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3596 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3597 TYPE_LENGTH (arg_type
) - len
))
3600 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3602 phex (regval
, MIPS64_REGSIZE
));
3603 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3614 /* Compute the offset into the stack at which we will
3615 copy the next parameter.
3617 In N32 (N64?), the stack_offset only needs to be
3618 adjusted when it has been used. */
3621 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3625 fprintf_unfiltered (gdb_stdlog
, "\n");
3628 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3630 /* Return adjusted stack pointer. */
3634 static enum return_value_convention
3635 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3636 struct type
*type
, struct regcache
*regcache
,
3637 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3639 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3641 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3643 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3644 if needed), as appropriate for the type. Composite results (struct,
3645 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3648 * A struct with only one or two floating point fields is returned in $f0
3649 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3652 * Any other composite results of at most 128 bits are returned in
3653 $2 (first 64 bits) and $3 (remainder, if necessary).
3655 * Larger composite results are handled by converting the function to a
3656 procedure with an implicit first parameter, which is a pointer to an area
3657 reserved by the caller to receive the result. [The o32-bit ABI requires
3658 that all composite results be handled by conversion to implicit first
3659 parameters. The MIPS/SGI Fortran implementation has always made a
3660 specific exception to return COMPLEX results in the floating point
3663 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3664 return RETURN_VALUE_STRUCT_CONVENTION
;
3665 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3666 && TYPE_LENGTH (type
) == 16
3667 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3669 /* A 128-bit floating-point value fills both $f0 and $f2. The
3670 two registers are used in the same as memory order, so the
3671 eight bytes with the lower memory address are in $f0. */
3673 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3674 mips_xfer_register (gdbarch
, regcache
,
3675 gdbarch_num_regs (gdbarch
)
3676 + mips_regnum (gdbarch
)->fp0
,
3677 8, gdbarch_byte_order (gdbarch
),
3678 readbuf
, writebuf
, 0);
3679 mips_xfer_register (gdbarch
, regcache
,
3680 gdbarch_num_regs (gdbarch
)
3681 + mips_regnum (gdbarch
)->fp0
+ 2,
3682 8, gdbarch_byte_order (gdbarch
),
3683 readbuf
? readbuf
+ 8 : readbuf
,
3684 writebuf
? writebuf
+ 8 : writebuf
, 0);
3685 return RETURN_VALUE_REGISTER_CONVENTION
;
3687 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3688 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3690 /* A single or double floating-point value that fits in FP0. */
3692 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3693 mips_xfer_register (gdbarch
, regcache
,
3694 gdbarch_num_regs (gdbarch
)
3695 + mips_regnum (gdbarch
)->fp0
,
3697 gdbarch_byte_order (gdbarch
),
3698 readbuf
, writebuf
, 0);
3699 return RETURN_VALUE_REGISTER_CONVENTION
;
3701 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3702 && TYPE_NFIELDS (type
) <= 2
3703 && TYPE_NFIELDS (type
) >= 1
3704 && ((TYPE_NFIELDS (type
) == 1
3705 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3707 || (TYPE_NFIELDS (type
) == 2
3708 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3710 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3711 == TYPE_CODE_FLT
))))
3713 /* A struct that contains one or two floats. Each value is part
3714 in the least significant part of their floating point
3715 register (or GPR, for soft float). */
3718 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3719 ? mips_regnum (gdbarch
)->fp0
3721 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3723 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3726 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3728 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3730 /* A 16-byte long double field goes in two consecutive
3732 mips_xfer_register (gdbarch
, regcache
,
3733 gdbarch_num_regs (gdbarch
) + regnum
,
3735 gdbarch_byte_order (gdbarch
),
3736 readbuf
, writebuf
, offset
);
3737 mips_xfer_register (gdbarch
, regcache
,
3738 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3740 gdbarch_byte_order (gdbarch
),
3741 readbuf
, writebuf
, offset
+ 8);
3744 mips_xfer_register (gdbarch
, regcache
,
3745 gdbarch_num_regs (gdbarch
) + regnum
,
3746 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3747 gdbarch_byte_order (gdbarch
),
3748 readbuf
, writebuf
, offset
);
3750 return RETURN_VALUE_REGISTER_CONVENTION
;
3752 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3753 || TYPE_CODE (type
) == TYPE_CODE_UNION
3754 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3756 /* A composite type. Extract the left justified value,
3757 regardless of the byte order. I.e. DO NOT USE
3761 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3762 offset
< TYPE_LENGTH (type
);
3763 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3765 int xfer
= register_size (gdbarch
, regnum
);
3766 if (offset
+ xfer
> TYPE_LENGTH (type
))
3767 xfer
= TYPE_LENGTH (type
) - offset
;
3769 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3770 offset
, xfer
, regnum
);
3771 mips_xfer_register (gdbarch
, regcache
,
3772 gdbarch_num_regs (gdbarch
) + regnum
,
3773 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3776 return RETURN_VALUE_REGISTER_CONVENTION
;
3780 /* A scalar extract each part but least-significant-byte
3784 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3785 offset
< TYPE_LENGTH (type
);
3786 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3788 int xfer
= register_size (gdbarch
, regnum
);
3789 if (offset
+ xfer
> TYPE_LENGTH (type
))
3790 xfer
= TYPE_LENGTH (type
) - offset
;
3792 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3793 offset
, xfer
, regnum
);
3794 mips_xfer_register (gdbarch
, regcache
,
3795 gdbarch_num_regs (gdbarch
) + regnum
,
3796 xfer
, gdbarch_byte_order (gdbarch
),
3797 readbuf
, writebuf
, offset
);
3799 return RETURN_VALUE_REGISTER_CONVENTION
;
3803 /* O32 ABI stuff. */
3806 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3807 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3808 int nargs
, struct value
**args
, CORE_ADDR sp
,
3809 int struct_return
, CORE_ADDR struct_addr
)
3815 int stack_offset
= 0;
3816 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3817 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3818 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3820 /* For shared libraries, "t9" needs to point at the function
3822 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3824 /* Set the return address register to point to the entry point of
3825 the program, where a breakpoint lies in wait. */
3826 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3828 /* First ensure that the stack and structure return address (if any)
3829 are properly aligned. The stack has to be at least 64-bit
3830 aligned even on 32-bit machines, because doubles must be 64-bit
3831 aligned. For n32 and n64, stack frames need to be 128-bit
3832 aligned, so we round to this widest known alignment. */
3834 sp
= align_down (sp
, 16);
3835 struct_addr
= align_down (struct_addr
, 16);
3837 /* Now make space on the stack for the args. */
3838 for (argnum
= 0; argnum
< nargs
; argnum
++)
3840 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3841 int arglen
= TYPE_LENGTH (arg_type
);
3843 /* Align to double-word if necessary. */
3844 if (mips_type_needs_double_align (arg_type
))
3845 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3846 /* Allocate space on the stack. */
3847 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3849 sp
-= align_up (len
, 16);
3852 fprintf_unfiltered (gdb_stdlog
,
3853 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3854 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3856 /* Initialize the integer and float register pointers. */
3857 argreg
= MIPS_A0_REGNUM
;
3858 float_argreg
= mips_fpa0_regnum (gdbarch
);
3860 /* The struct_return pointer occupies the first parameter-passing reg. */
3864 fprintf_unfiltered (gdb_stdlog
,
3865 "mips_o32_push_dummy_call: "
3866 "struct_return reg=%d %s\n",
3867 argreg
, paddress (gdbarch
, struct_addr
));
3868 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3869 stack_offset
+= MIPS32_REGSIZE
;
3872 /* Now load as many as possible of the first arguments into
3873 registers, and push the rest onto the stack. Loop thru args
3874 from first to last. */
3875 for (argnum
= 0; argnum
< nargs
; argnum
++)
3877 const gdb_byte
*val
;
3878 struct value
*arg
= args
[argnum
];
3879 struct type
*arg_type
= check_typedef (value_type (arg
));
3880 int len
= TYPE_LENGTH (arg_type
);
3881 enum type_code typecode
= TYPE_CODE (arg_type
);
3884 fprintf_unfiltered (gdb_stdlog
,
3885 "mips_o32_push_dummy_call: %d len=%d type=%d",
3886 argnum
+ 1, len
, (int) typecode
);
3888 val
= value_contents (arg
);
3890 /* 32-bit ABIs always start floating point arguments in an
3891 even-numbered floating point register. Round the FP register
3892 up before the check to see if there are any FP registers
3893 left. O32/O64 targets also pass the FP in the integer
3894 registers so also round up normal registers. */
3895 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3897 if ((float_argreg
& 1))
3901 /* Floating point arguments passed in registers have to be
3902 treated specially. On 32-bit architectures, doubles
3903 are passed in register pairs; the even register gets
3904 the low word, and the odd register gets the high word.
3905 On O32/O64, the first two floating point arguments are
3906 also copied to general registers, because MIPS16 functions
3907 don't use float registers for arguments. This duplication of
3908 arguments in general registers can't hurt non-MIPS16 functions
3909 because those registers are normally skipped. */
3911 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3912 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3914 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3916 int low_offset
= gdbarch_byte_order (gdbarch
)
3917 == BFD_ENDIAN_BIG
? 4 : 0;
3918 unsigned long regval
;
3920 /* Write the low word of the double to the even register(s). */
3921 regval
= extract_unsigned_integer (val
+ low_offset
,
3924 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3925 float_argreg
, phex (regval
, 4));
3926 regcache_cooked_write_unsigned (regcache
,
3927 float_argreg
++, regval
);
3929 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3930 argreg
, phex (regval
, 4));
3931 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3933 /* Write the high word of the double to the odd register(s). */
3934 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3937 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3938 float_argreg
, phex (regval
, 4));
3939 regcache_cooked_write_unsigned (regcache
,
3940 float_argreg
++, regval
);
3943 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3944 argreg
, phex (regval
, 4));
3945 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3949 /* This is a floating point value that fits entirely
3950 in a single register. */
3951 /* On 32 bit ABI's the float_argreg is further adjusted
3952 above to ensure that it is even register aligned. */
3953 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3955 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3956 float_argreg
, phex (regval
, len
));
3957 regcache_cooked_write_unsigned (regcache
,
3958 float_argreg
++, regval
);
3959 /* Although two FP registers are reserved for each
3960 argument, only one corresponding integer register is
3963 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3964 argreg
, phex (regval
, len
));
3965 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3967 /* Reserve space for the FP register. */
3968 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3972 /* Copy the argument to general registers or the stack in
3973 register-sized pieces. Large arguments are split between
3974 registers and stack. */
3975 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3976 are treated specially: Irix cc passes
3977 them in registers where gcc sometimes puts them on the
3978 stack. For maximum compatibility, we will put them in
3980 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3981 && len
% MIPS32_REGSIZE
!= 0);
3982 /* Structures should be aligned to eight bytes (even arg registers)
3983 on MIPS_ABI_O32, if their first member has double precision. */
3984 if (mips_type_needs_double_align (arg_type
))
3989 stack_offset
+= MIPS32_REGSIZE
;
3994 /* Remember if the argument was written to the stack. */
3995 int stack_used_p
= 0;
3996 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3999 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4002 /* Write this portion of the argument to the stack. */
4003 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4004 || odd_sized_struct
)
4006 /* Should shorter than int integer values be
4007 promoted to int before being stored? */
4008 int longword_offset
= 0;
4014 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4015 paddress (gdbarch
, stack_offset
));
4016 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4017 paddress (gdbarch
, longword_offset
));
4020 addr
= sp
+ stack_offset
+ longword_offset
;
4025 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4026 paddress (gdbarch
, addr
));
4027 for (i
= 0; i
< partial_len
; i
++)
4029 fprintf_unfiltered (gdb_stdlog
, "%02x",
4033 write_memory (addr
, val
, partial_len
);
4036 /* Note!!! This is NOT an else clause. Odd sized
4037 structs may go thru BOTH paths. */
4038 /* Write this portion of the argument to a general
4039 purpose register. */
4040 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4042 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4044 /* Value may need to be sign extended, because
4045 mips_isa_regsize() != mips_abi_regsize(). */
4047 /* A non-floating-point argument being passed in a
4048 general register. If a struct or union, and if
4049 the remaining length is smaller than the register
4050 size, we have to adjust the register value on
4053 It does not seem to be necessary to do the
4054 same for integral types.
4056 Also don't do this adjustment on O64 binaries.
4058 cagney/2001-07-23: gdb/179: Also, GCC, when
4059 outputting LE O32 with sizeof (struct) <
4060 mips_abi_regsize(), generates a left shift
4061 as part of storing the argument in a register
4062 (the left shift isn't generated when
4063 sizeof (struct) >= mips_abi_regsize()). Since
4064 it is quite possible that this is GCC
4065 contradicting the LE/O32 ABI, GDB has not been
4066 adjusted to accommodate this. Either someone
4067 needs to demonstrate that the LE/O32 ABI
4068 specifies such a left shift OR this new ABI gets
4069 identified as such and GDB gets tweaked
4072 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4073 && partial_len
< MIPS32_REGSIZE
4074 && (typecode
== TYPE_CODE_STRUCT
4075 || typecode
== TYPE_CODE_UNION
))
4076 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4080 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4082 phex (regval
, MIPS32_REGSIZE
));
4083 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4086 /* Prevent subsequent floating point arguments from
4087 being passed in floating point registers. */
4088 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4094 /* Compute the offset into the stack at which we will
4095 copy the next parameter.
4097 In older ABIs, the caller reserved space for
4098 registers that contained arguments. This was loosely
4099 refered to as their "home". Consequently, space is
4100 always allocated. */
4102 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4106 fprintf_unfiltered (gdb_stdlog
, "\n");
4109 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4111 /* Return adjusted stack pointer. */
4115 static enum return_value_convention
4116 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4117 struct type
*type
, struct regcache
*regcache
,
4118 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4120 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4122 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4123 || TYPE_CODE (type
) == TYPE_CODE_UNION
4124 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4125 return RETURN_VALUE_STRUCT_CONVENTION
;
4126 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4127 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4129 /* A single-precision floating-point value. It fits in the
4130 least significant part of FP0. */
4132 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4133 mips_xfer_register (gdbarch
, regcache
,
4134 gdbarch_num_regs (gdbarch
)
4135 + mips_regnum (gdbarch
)->fp0
,
4137 gdbarch_byte_order (gdbarch
),
4138 readbuf
, writebuf
, 0);
4139 return RETURN_VALUE_REGISTER_CONVENTION
;
4141 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4142 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4144 /* A double-precision floating-point value. The most
4145 significant part goes in FP1, and the least significant in
4148 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4149 switch (gdbarch_byte_order (gdbarch
))
4151 case BFD_ENDIAN_LITTLE
:
4152 mips_xfer_register (gdbarch
, regcache
,
4153 gdbarch_num_regs (gdbarch
)
4154 + mips_regnum (gdbarch
)->fp0
+
4155 0, 4, gdbarch_byte_order (gdbarch
),
4156 readbuf
, writebuf
, 0);
4157 mips_xfer_register (gdbarch
, regcache
,
4158 gdbarch_num_regs (gdbarch
)
4159 + mips_regnum (gdbarch
)->fp0
+ 1,
4160 4, gdbarch_byte_order (gdbarch
),
4161 readbuf
, writebuf
, 4);
4163 case BFD_ENDIAN_BIG
:
4164 mips_xfer_register (gdbarch
, regcache
,
4165 gdbarch_num_regs (gdbarch
)
4166 + mips_regnum (gdbarch
)->fp0
+ 1,
4167 4, gdbarch_byte_order (gdbarch
),
4168 readbuf
, writebuf
, 0);
4169 mips_xfer_register (gdbarch
, regcache
,
4170 gdbarch_num_regs (gdbarch
)
4171 + mips_regnum (gdbarch
)->fp0
+ 0,
4172 4, gdbarch_byte_order (gdbarch
),
4173 readbuf
, writebuf
, 4);
4176 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4178 return RETURN_VALUE_REGISTER_CONVENTION
;
4181 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4182 && TYPE_NFIELDS (type
) <= 2
4183 && TYPE_NFIELDS (type
) >= 1
4184 && ((TYPE_NFIELDS (type
) == 1
4185 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4187 || (TYPE_NFIELDS (type
) == 2
4188 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4190 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4192 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4194 /* A struct that contains one or two floats. Each value is part
4195 in the least significant part of their floating point
4197 gdb_byte reg
[MAX_REGISTER_SIZE
];
4200 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4201 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4203 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4206 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4208 mips_xfer_register (gdbarch
, regcache
,
4209 gdbarch_num_regs (gdbarch
) + regnum
,
4210 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4211 gdbarch_byte_order (gdbarch
),
4212 readbuf
, writebuf
, offset
);
4214 return RETURN_VALUE_REGISTER_CONVENTION
;
4218 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4219 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4221 /* A structure or union. Extract the left justified value,
4222 regardless of the byte order. I.e. DO NOT USE
4226 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4227 offset
< TYPE_LENGTH (type
);
4228 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4230 int xfer
= register_size (gdbarch
, regnum
);
4231 if (offset
+ xfer
> TYPE_LENGTH (type
))
4232 xfer
= TYPE_LENGTH (type
) - offset
;
4234 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4235 offset
, xfer
, regnum
);
4236 mips_xfer_register (gdbarch
, regcache
,
4237 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4238 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4240 return RETURN_VALUE_REGISTER_CONVENTION
;
4245 /* A scalar extract each part but least-significant-byte
4246 justified. o32 thinks registers are 4 byte, regardless of
4250 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4251 offset
< TYPE_LENGTH (type
);
4252 offset
+= MIPS32_REGSIZE
, regnum
++)
4254 int xfer
= MIPS32_REGSIZE
;
4255 if (offset
+ xfer
> TYPE_LENGTH (type
))
4256 xfer
= TYPE_LENGTH (type
) - offset
;
4258 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4259 offset
, xfer
, regnum
);
4260 mips_xfer_register (gdbarch
, regcache
,
4261 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4262 gdbarch_byte_order (gdbarch
),
4263 readbuf
, writebuf
, offset
);
4265 return RETURN_VALUE_REGISTER_CONVENTION
;
4269 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4273 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4274 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4276 struct value
**args
, CORE_ADDR sp
,
4277 int struct_return
, CORE_ADDR struct_addr
)
4283 int stack_offset
= 0;
4284 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4285 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4286 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4288 /* For shared libraries, "t9" needs to point at the function
4290 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4292 /* Set the return address register to point to the entry point of
4293 the program, where a breakpoint lies in wait. */
4294 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4296 /* First ensure that the stack and structure return address (if any)
4297 are properly aligned. The stack has to be at least 64-bit
4298 aligned even on 32-bit machines, because doubles must be 64-bit
4299 aligned. For n32 and n64, stack frames need to be 128-bit
4300 aligned, so we round to this widest known alignment. */
4302 sp
= align_down (sp
, 16);
4303 struct_addr
= align_down (struct_addr
, 16);
4305 /* Now make space on the stack for the args. */
4306 for (argnum
= 0; argnum
< nargs
; argnum
++)
4308 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4309 int arglen
= TYPE_LENGTH (arg_type
);
4311 /* Allocate space on the stack. */
4312 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4314 sp
-= align_up (len
, 16);
4317 fprintf_unfiltered (gdb_stdlog
,
4318 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4319 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4321 /* Initialize the integer and float register pointers. */
4322 argreg
= MIPS_A0_REGNUM
;
4323 float_argreg
= mips_fpa0_regnum (gdbarch
);
4325 /* The struct_return pointer occupies the first parameter-passing reg. */
4329 fprintf_unfiltered (gdb_stdlog
,
4330 "mips_o64_push_dummy_call: "
4331 "struct_return reg=%d %s\n",
4332 argreg
, paddress (gdbarch
, struct_addr
));
4333 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4334 stack_offset
+= MIPS64_REGSIZE
;
4337 /* Now load as many as possible of the first arguments into
4338 registers, and push the rest onto the stack. Loop thru args
4339 from first to last. */
4340 for (argnum
= 0; argnum
< nargs
; argnum
++)
4342 const gdb_byte
*val
;
4343 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4344 struct value
*arg
= args
[argnum
];
4345 struct type
*arg_type
= check_typedef (value_type (arg
));
4346 int len
= TYPE_LENGTH (arg_type
);
4347 enum type_code typecode
= TYPE_CODE (arg_type
);
4350 fprintf_unfiltered (gdb_stdlog
,
4351 "mips_o64_push_dummy_call: %d len=%d type=%d",
4352 argnum
+ 1, len
, (int) typecode
);
4354 val
= value_contents (arg
);
4356 /* Function pointer arguments to mips16 code need to be made into
4358 if (typecode
== TYPE_CODE_PTR
4359 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4361 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4363 if (mips_pc_is_mips16 (addr
))
4365 store_signed_integer (valbuf
, len
, byte_order
,
4366 make_mips16_addr (addr
));
4371 /* Floating point arguments passed in registers have to be
4372 treated specially. On 32-bit architectures, doubles
4373 are passed in register pairs; the even register gets
4374 the low word, and the odd register gets the high word.
4375 On O32/O64, the first two floating point arguments are
4376 also copied to general registers, because MIPS16 functions
4377 don't use float registers for arguments. This duplication of
4378 arguments in general registers can't hurt non-MIPS16 functions
4379 because those registers are normally skipped. */
4381 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4382 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4384 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4386 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4387 float_argreg
, phex (regval
, len
));
4388 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4390 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4391 argreg
, phex (regval
, len
));
4392 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4394 /* Reserve space for the FP register. */
4395 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4399 /* Copy the argument to general registers or the stack in
4400 register-sized pieces. Large arguments are split between
4401 registers and stack. */
4402 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4403 are treated specially: Irix cc passes them in registers
4404 where gcc sometimes puts them on the stack. For maximum
4405 compatibility, we will put them in both places. */
4406 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4407 && len
% MIPS64_REGSIZE
!= 0);
4410 /* Remember if the argument was written to the stack. */
4411 int stack_used_p
= 0;
4412 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4415 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4418 /* Write this portion of the argument to the stack. */
4419 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4420 || odd_sized_struct
)
4422 /* Should shorter than int integer values be
4423 promoted to int before being stored? */
4424 int longword_offset
= 0;
4427 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4429 if ((typecode
== TYPE_CODE_INT
4430 || typecode
== TYPE_CODE_PTR
4431 || typecode
== TYPE_CODE_FLT
)
4433 longword_offset
= MIPS64_REGSIZE
- len
;
4438 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4439 paddress (gdbarch
, stack_offset
));
4440 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4441 paddress (gdbarch
, longword_offset
));
4444 addr
= sp
+ stack_offset
+ longword_offset
;
4449 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4450 paddress (gdbarch
, addr
));
4451 for (i
= 0; i
< partial_len
; i
++)
4453 fprintf_unfiltered (gdb_stdlog
, "%02x",
4457 write_memory (addr
, val
, partial_len
);
4460 /* Note!!! This is NOT an else clause. Odd sized
4461 structs may go thru BOTH paths. */
4462 /* Write this portion of the argument to a general
4463 purpose register. */
4464 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4466 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4468 /* Value may need to be sign extended, because
4469 mips_isa_regsize() != mips_abi_regsize(). */
4471 /* A non-floating-point argument being passed in a
4472 general register. If a struct or union, and if
4473 the remaining length is smaller than the register
4474 size, we have to adjust the register value on
4477 It does not seem to be necessary to do the
4478 same for integral types. */
4480 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4481 && partial_len
< MIPS64_REGSIZE
4482 && (typecode
== TYPE_CODE_STRUCT
4483 || typecode
== TYPE_CODE_UNION
))
4484 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4488 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4490 phex (regval
, MIPS64_REGSIZE
));
4491 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4494 /* Prevent subsequent floating point arguments from
4495 being passed in floating point registers. */
4496 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4502 /* Compute the offset into the stack at which we will
4503 copy the next parameter.
4505 In older ABIs, the caller reserved space for
4506 registers that contained arguments. This was loosely
4507 refered to as their "home". Consequently, space is
4508 always allocated. */
4510 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4514 fprintf_unfiltered (gdb_stdlog
, "\n");
4517 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4519 /* Return adjusted stack pointer. */
4523 static enum return_value_convention
4524 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4525 struct type
*type
, struct regcache
*regcache
,
4526 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4528 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4530 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4531 || TYPE_CODE (type
) == TYPE_CODE_UNION
4532 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4533 return RETURN_VALUE_STRUCT_CONVENTION
;
4534 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4536 /* A floating-point value. It fits in the least significant
4539 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4540 mips_xfer_register (gdbarch
, regcache
,
4541 gdbarch_num_regs (gdbarch
)
4542 + mips_regnum (gdbarch
)->fp0
,
4544 gdbarch_byte_order (gdbarch
),
4545 readbuf
, writebuf
, 0);
4546 return RETURN_VALUE_REGISTER_CONVENTION
;
4550 /* A scalar extract each part but least-significant-byte
4554 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4555 offset
< TYPE_LENGTH (type
);
4556 offset
+= MIPS64_REGSIZE
, regnum
++)
4558 int xfer
= MIPS64_REGSIZE
;
4559 if (offset
+ xfer
> TYPE_LENGTH (type
))
4560 xfer
= TYPE_LENGTH (type
) - offset
;
4562 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4563 offset
, xfer
, regnum
);
4564 mips_xfer_register (gdbarch
, regcache
,
4565 gdbarch_num_regs (gdbarch
) + regnum
,
4566 xfer
, gdbarch_byte_order (gdbarch
),
4567 readbuf
, writebuf
, offset
);
4569 return RETURN_VALUE_REGISTER_CONVENTION
;
4573 /* Floating point register management.
4575 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4576 64bit operations, these early MIPS cpus treat fp register pairs
4577 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4578 registers and offer a compatibility mode that emulates the MIPS2 fp
4579 model. When operating in MIPS2 fp compat mode, later cpu's split
4580 double precision floats into two 32-bit chunks and store them in
4581 consecutive fp regs. To display 64-bit floats stored in this
4582 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4583 Throw in user-configurable endianness and you have a real mess.
4585 The way this works is:
4586 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4587 double-precision value will be split across two logical registers.
4588 The lower-numbered logical register will hold the low-order bits,
4589 regardless of the processor's endianness.
4590 - If we are on a 64-bit processor, and we are looking for a
4591 single-precision value, it will be in the low ordered bits
4592 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4593 save slot in memory.
4594 - If we are in 64-bit mode, everything is straightforward.
4596 Note that this code only deals with "live" registers at the top of the
4597 stack. We will attempt to deal with saved registers later, when
4598 the raw/cooked register interface is in place. (We need a general
4599 interface that can deal with dynamic saved register sizes -- fp
4600 regs could be 32 bits wide in one frame and 64 on the frame above
4603 /* Copy a 32-bit single-precision value from the current frame
4604 into rare_buffer. */
4607 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4608 gdb_byte
*rare_buffer
)
4610 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4611 int raw_size
= register_size (gdbarch
, regno
);
4612 gdb_byte
*raw_buffer
= alloca (raw_size
);
4614 if (!frame_register_read (frame
, regno
, raw_buffer
))
4615 error (_("can't read register %d (%s)"),
4616 regno
, gdbarch_register_name (gdbarch
, regno
));
4619 /* We have a 64-bit value for this register. Find the low-order
4623 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4628 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4632 memcpy (rare_buffer
, raw_buffer
, 4);
4636 /* Copy a 64-bit double-precision value from the current frame into
4637 rare_buffer. This may include getting half of it from the next
4641 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4642 gdb_byte
*rare_buffer
)
4644 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4645 int raw_size
= register_size (gdbarch
, regno
);
4647 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4649 /* We have a 64-bit value for this register, and we should use
4651 if (!frame_register_read (frame
, regno
, rare_buffer
))
4652 error (_("can't read register %d (%s)"),
4653 regno
, gdbarch_register_name (gdbarch
, regno
));
4657 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4659 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4660 internal_error (__FILE__
, __LINE__
,
4661 _("mips_read_fp_register_double: bad access to "
4662 "odd-numbered FP register"));
4664 /* mips_read_fp_register_single will find the correct 32 bits from
4666 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4668 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4669 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4673 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4674 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4680 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4682 { /* Do values for FP (float) regs. */
4683 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4684 gdb_byte
*raw_buffer
;
4685 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4688 raw_buffer
= alloca (2 * register_size (gdbarch
,
4689 mips_regnum (gdbarch
)->fp0
));
4691 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4692 fprintf_filtered (file
, "%*s",
4693 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4696 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4698 struct value_print_options opts
;
4700 /* 4-byte registers: Print hex and floating. Also print even
4701 numbered registers as doubles. */
4702 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4703 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4706 get_formatted_print_options (&opts
, 'x');
4707 print_scalar_formatted (raw_buffer
,
4708 builtin_type (gdbarch
)->builtin_uint32
,
4711 fprintf_filtered (file
, " flt: ");
4713 fprintf_filtered (file
, " <invalid float> ");
4715 fprintf_filtered (file
, "%-17.9g", flt1
);
4717 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4719 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4720 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4723 fprintf_filtered (file
, " dbl: ");
4725 fprintf_filtered (file
, "<invalid double>");
4727 fprintf_filtered (file
, "%-24.17g", doub
);
4732 struct value_print_options opts
;
4734 /* Eight byte registers: print each one as hex, float and double. */
4735 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4736 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4739 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4740 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4743 get_formatted_print_options (&opts
, 'x');
4744 print_scalar_formatted (raw_buffer
,
4745 builtin_type (gdbarch
)->builtin_uint64
,
4748 fprintf_filtered (file
, " flt: ");
4750 fprintf_filtered (file
, "<invalid float>");
4752 fprintf_filtered (file
, "%-17.9g", flt1
);
4754 fprintf_filtered (file
, " dbl: ");
4756 fprintf_filtered (file
, "<invalid double>");
4758 fprintf_filtered (file
, "%-24.17g", doub
);
4763 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4766 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4768 struct value_print_options opts
;
4771 if (mips_float_register_p (gdbarch
, regnum
))
4773 mips_print_fp_register (file
, frame
, regnum
);
4777 val
= get_frame_register_value (frame
, regnum
);
4778 if (value_optimized_out (val
))
4780 fprintf_filtered (file
, "%s: [Invalid]",
4781 gdbarch_register_name (gdbarch
, regnum
));
4785 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4787 /* The problem with printing numeric register names (r26, etc.) is that
4788 the user can't use them on input. Probably the best solution is to
4789 fix it so that either the numeric or the funky (a2, etc.) names
4790 are accepted on input. */
4791 if (regnum
< MIPS_NUMREGS
)
4792 fprintf_filtered (file
, "(r%d): ", regnum
);
4794 fprintf_filtered (file
, ": ");
4796 get_formatted_print_options (&opts
, 'x');
4797 val_print_scalar_formatted (value_type (val
),
4798 value_contents_for_printing (val
),
4799 value_embedded_offset (val
),
4804 /* Replacement for generic do_registers_info.
4805 Print regs in pretty columns. */
4808 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4811 fprintf_filtered (file
, " ");
4812 mips_print_fp_register (file
, frame
, regnum
);
4813 fprintf_filtered (file
, "\n");
4818 /* Print a row's worth of GP (int) registers, with name labels above. */
4821 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4824 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4825 /* Do values for GP (int) regs. */
4826 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4827 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4832 /* For GP registers, we print a separate row of names above the vals. */
4833 for (col
= 0, regnum
= start_regnum
;
4834 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4835 + gdbarch_num_pseudo_regs (gdbarch
);
4838 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4839 continue; /* unused register */
4840 if (mips_float_register_p (gdbarch
, regnum
))
4841 break; /* End the row: reached FP register. */
4842 /* Large registers are handled separately. */
4843 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4846 break; /* End the row before this register. */
4848 /* Print this register on a row by itself. */
4849 mips_print_register (file
, frame
, regnum
);
4850 fprintf_filtered (file
, "\n");
4854 fprintf_filtered (file
, " ");
4855 fprintf_filtered (file
,
4856 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4857 gdbarch_register_name (gdbarch
, regnum
));
4864 /* Print the R0 to R31 names. */
4865 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4866 fprintf_filtered (file
, "\n R%-4d",
4867 start_regnum
% gdbarch_num_regs (gdbarch
));
4869 fprintf_filtered (file
, "\n ");
4871 /* Now print the values in hex, 4 or 8 to the row. */
4872 for (col
= 0, regnum
= start_regnum
;
4873 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4874 + gdbarch_num_pseudo_regs (gdbarch
);
4877 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4878 continue; /* unused register */
4879 if (mips_float_register_p (gdbarch
, regnum
))
4880 break; /* End row: reached FP register. */
4881 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4882 break; /* End row: large register. */
4884 /* OK: get the data in raw format. */
4885 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4886 error (_("can't read register %d (%s)"),
4887 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4888 /* pad small registers */
4890 byte
< (mips_abi_regsize (gdbarch
)
4891 - register_size (gdbarch
, regnum
)); byte
++)
4892 printf_filtered (" ");
4893 /* Now print the register value in hex, endian order. */
4894 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4896 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4897 byte
< register_size (gdbarch
, regnum
); byte
++)
4898 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4900 for (byte
= register_size (gdbarch
, regnum
) - 1;
4902 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4903 fprintf_filtered (file
, " ");
4906 if (col
> 0) /* ie. if we actually printed anything... */
4907 fprintf_filtered (file
, "\n");
4912 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4915 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4916 struct frame_info
*frame
, int regnum
, int all
)
4918 if (regnum
!= -1) /* Do one specified register. */
4920 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4921 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4922 error (_("Not a valid register for the current processor type"));
4924 mips_print_register (file
, frame
, regnum
);
4925 fprintf_filtered (file
, "\n");
4928 /* Do all (or most) registers. */
4930 regnum
= gdbarch_num_regs (gdbarch
);
4931 while (regnum
< gdbarch_num_regs (gdbarch
)
4932 + gdbarch_num_pseudo_regs (gdbarch
))
4934 if (mips_float_register_p (gdbarch
, regnum
))
4936 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4937 regnum
= print_fp_register_row (file
, frame
, regnum
);
4939 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
4942 regnum
= print_gp_register_row (file
, frame
, regnum
);
4947 /* Is this a branch with a delay slot? */
4950 is_delayed (unsigned long insn
)
4953 for (i
= 0; i
< NUMOPCODES
; ++i
)
4954 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4955 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4957 return (i
< NUMOPCODES
4958 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4959 | INSN_COND_BRANCH_DELAY
4960 | INSN_COND_BRANCH_LIKELY
)));
4964 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4965 struct frame_info
*frame
)
4967 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4968 CORE_ADDR pc
= get_frame_pc (frame
);
4969 gdb_byte buf
[MIPS_INSN32_SIZE
];
4971 /* There is no branch delay slot on MIPS16. */
4972 if (mips_pc_is_mips16 (pc
))
4975 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4978 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4979 /* If error reading memory, guess that it is not a delayed
4982 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4985 /* To skip prologues, I use this predicate. Returns either PC itself
4986 if the code at PC does not look like a function prologue; otherwise
4987 returns an address that (if we're lucky) follows the prologue. If
4988 LENIENT, then we must skip everything which is involved in setting
4989 up the frame (it's OK to skip more, just so long as we don't skip
4990 anything which might clobber the registers which are being saved.
4991 We must skip more in the case where part of the prologue is in the
4992 delay slot of a non-prologue instruction). */
4995 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4998 CORE_ADDR func_addr
;
5000 /* See if we can determine the end of the prologue via the symbol table.
5001 If so, then return either PC, or the PC after the prologue, whichever
5003 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
5005 CORE_ADDR post_prologue_pc
5006 = skip_prologue_using_sal (gdbarch
, func_addr
);
5007 if (post_prologue_pc
!= 0)
5008 return max (pc
, post_prologue_pc
);
5011 /* Can't determine prologue from the symbol table, need to examine
5014 /* Find an upper limit on the function prologue using the debug
5015 information. If the debug information could not be used to provide
5016 that bound, then use an arbitrary large number as the upper bound. */
5017 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
5019 limit_pc
= pc
+ 100; /* Magic. */
5021 if (mips_pc_is_mips16 (pc
))
5022 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5024 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5027 /* Check whether the PC is in a function epilogue (32-bit version).
5028 This is a helper function for mips_in_function_epilogue_p. */
5030 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5032 CORE_ADDR func_addr
= 0, func_end
= 0;
5034 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5036 /* The MIPS epilogue is max. 12 bytes long. */
5037 CORE_ADDR addr
= func_end
- 12;
5039 if (addr
< func_addr
+ 4)
5040 addr
= func_addr
+ 4;
5044 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
5046 unsigned long high_word
;
5049 inst
= mips_fetch_instruction (gdbarch
, pc
);
5050 high_word
= (inst
>> 16) & 0xffff;
5052 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
5053 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
5054 && inst
!= 0x03e00008 /* jr $ra */
5055 && inst
!= 0x00000000) /* nop */
5065 /* Check whether the PC is in a function epilogue (16-bit version).
5066 This is a helper function for mips_in_function_epilogue_p. */
5068 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5070 CORE_ADDR func_addr
= 0, func_end
= 0;
5072 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5074 /* The MIPS epilogue is max. 12 bytes long. */
5075 CORE_ADDR addr
= func_end
- 12;
5077 if (addr
< func_addr
+ 4)
5078 addr
= func_addr
+ 4;
5082 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5084 unsigned short inst
;
5086 inst
= mips_fetch_instruction (gdbarch
, pc
);
5088 if ((inst
& 0xf800) == 0xf000) /* extend */
5091 if (inst
!= 0x6300 /* addiu $sp,offset */
5092 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5093 && inst
!= 0xe820 /* jr $ra */
5094 && inst
!= 0xe8a0 /* jrc $ra */
5095 && inst
!= 0x6500) /* nop */
5105 /* The epilogue is defined here as the area at the end of a function,
5106 after an instruction which destroys the function's stack frame. */
5108 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5110 if (mips_pc_is_mips16 (pc
))
5111 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5113 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5116 /* Root of all "set mips "/"show mips " commands. This will eventually be
5117 used for all MIPS-specific commands. */
5120 show_mips_command (char *args
, int from_tty
)
5122 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5126 set_mips_command (char *args
, int from_tty
)
5129 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5130 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5133 /* Commands to show/set the MIPS FPU type. */
5136 show_mipsfpu_command (char *args
, int from_tty
)
5140 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5143 ("The MIPS floating-point coprocessor is unknown "
5144 "because the current architecture is not MIPS.\n");
5148 switch (MIPS_FPU_TYPE (target_gdbarch
))
5150 case MIPS_FPU_SINGLE
:
5151 fpu
= "single-precision";
5153 case MIPS_FPU_DOUBLE
:
5154 fpu
= "double-precision";
5157 fpu
= "absent (none)";
5160 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5162 if (mips_fpu_type_auto
)
5163 printf_unfiltered ("The MIPS floating-point coprocessor "
5164 "is set automatically (currently %s)\n",
5168 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5173 set_mipsfpu_command (char *args
, int from_tty
)
5175 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5176 "\"single\",\"none\" or \"auto\".\n");
5177 show_mipsfpu_command (args
, from_tty
);
5181 set_mipsfpu_single_command (char *args
, int from_tty
)
5183 struct gdbarch_info info
;
5184 gdbarch_info_init (&info
);
5185 mips_fpu_type
= MIPS_FPU_SINGLE
;
5186 mips_fpu_type_auto
= 0;
5187 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5188 instead of relying on globals. Doing that would let generic code
5189 handle the search for this specific architecture. */
5190 if (!gdbarch_update_p (info
))
5191 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5195 set_mipsfpu_double_command (char *args
, int from_tty
)
5197 struct gdbarch_info info
;
5198 gdbarch_info_init (&info
);
5199 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5200 mips_fpu_type_auto
= 0;
5201 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5202 instead of relying on globals. Doing that would let generic code
5203 handle the search for this specific architecture. */
5204 if (!gdbarch_update_p (info
))
5205 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5209 set_mipsfpu_none_command (char *args
, int from_tty
)
5211 struct gdbarch_info info
;
5212 gdbarch_info_init (&info
);
5213 mips_fpu_type
= MIPS_FPU_NONE
;
5214 mips_fpu_type_auto
= 0;
5215 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5216 instead of relying on globals. Doing that would let generic code
5217 handle the search for this specific architecture. */
5218 if (!gdbarch_update_p (info
))
5219 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5223 set_mipsfpu_auto_command (char *args
, int from_tty
)
5225 mips_fpu_type_auto
= 1;
5228 /* Attempt to identify the particular processor model by reading the
5229 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5230 the relevant processor still exists (it dates back to '94) and
5231 secondly this is not the way to do this. The processor type should
5232 be set by forcing an architecture change. */
5235 deprecated_mips_set_processor_regs_hack (void)
5237 struct regcache
*regcache
= get_current_regcache ();
5238 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5239 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5242 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5243 if ((prid
& ~0xf) == 0x700)
5244 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5247 /* Just like reinit_frame_cache, but with the right arguments to be
5248 callable as an sfunc. */
5251 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5252 struct cmd_list_element
*c
)
5254 reinit_frame_cache ();
5258 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5260 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5261 disassembler needs to be able to locally determine the ISA, and
5262 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5264 if (mips_pc_is_mips16 (memaddr
))
5265 info
->mach
= bfd_mach_mips16
;
5267 /* Round down the instruction address to the appropriate boundary. */
5268 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5270 /* Set the disassembler options. */
5271 if (!info
->disassembler_options
)
5272 /* This string is not recognized explicitly by the disassembler,
5273 but it tells the disassembler to not try to guess the ABI from
5274 the bfd elf headers, such that, if the user overrides the ABI
5275 of a program linked as NewABI, the disassembly will follow the
5276 register naming conventions specified by the user. */
5277 info
->disassembler_options
= "gpr-names=32";
5279 /* Call the appropriate disassembler based on the target endian-ness. */
5280 if (info
->endian
== BFD_ENDIAN_BIG
)
5281 return print_insn_big_mips (memaddr
, info
);
5283 return print_insn_little_mips (memaddr
, info
);
5287 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5289 /* Set up the disassembler info, so that we get the right
5290 register names from libopcodes. */
5291 info
->disassembler_options
= "gpr-names=n32";
5292 info
->flavour
= bfd_target_elf_flavour
;
5294 return gdb_print_insn_mips (memaddr
, info
);
5298 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5300 /* Set up the disassembler info, so that we get the right
5301 register names from libopcodes. */
5302 info
->disassembler_options
= "gpr-names=64";
5303 info
->flavour
= bfd_target_elf_flavour
;
5305 return gdb_print_insn_mips (memaddr
, info
);
5308 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5309 program counter value to determine whether a 16- or 32-bit breakpoint
5310 should be used. It returns a pointer to a string of bytes that encode a
5311 breakpoint instruction, stores the length of the string to *lenptr, and
5312 adjusts pc (if necessary) to point to the actual memory location where
5313 the breakpoint should be inserted. */
5315 static const gdb_byte
*
5316 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5317 CORE_ADDR
*pcptr
, int *lenptr
)
5319 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5321 if (mips_pc_is_mips16 (*pcptr
))
5323 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5324 *pcptr
= unmake_mips16_addr (*pcptr
);
5325 *lenptr
= sizeof (mips16_big_breakpoint
);
5326 return mips16_big_breakpoint
;
5330 /* The IDT board uses an unusual breakpoint value, and
5331 sometimes gets confused when it sees the usual MIPS
5332 breakpoint instruction. */
5333 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5334 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5335 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5336 /* Likewise, IRIX appears to expect a different breakpoint,
5337 although this is not apparent until you try to use pthreads. */
5338 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5340 *lenptr
= sizeof (big_breakpoint
);
5342 if (strcmp (target_shortname
, "mips") == 0)
5343 return idt_big_breakpoint
;
5344 else if (strcmp (target_shortname
, "ddb") == 0
5345 || strcmp (target_shortname
, "pmon") == 0
5346 || strcmp (target_shortname
, "lsi") == 0)
5347 return pmon_big_breakpoint
;
5348 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5349 return irix_big_breakpoint
;
5351 return big_breakpoint
;
5356 if (mips_pc_is_mips16 (*pcptr
))
5358 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5359 *pcptr
= unmake_mips16_addr (*pcptr
);
5360 *lenptr
= sizeof (mips16_little_breakpoint
);
5361 return mips16_little_breakpoint
;
5365 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5366 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5367 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5369 *lenptr
= sizeof (little_breakpoint
);
5371 if (strcmp (target_shortname
, "mips") == 0)
5372 return idt_little_breakpoint
;
5373 else if (strcmp (target_shortname
, "ddb") == 0
5374 || strcmp (target_shortname
, "pmon") == 0
5375 || strcmp (target_shortname
, "lsi") == 0)
5376 return pmon_little_breakpoint
;
5378 return little_breakpoint
;
5383 /* Return non-zero if the ADDR instruction has a branch delay slot
5384 (i.e. it is a jump or branch instruction). This function is based
5385 on mips32_next_pc. */
5388 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
5390 gdb_byte buf
[MIPS_INSN32_SIZE
];
5397 status
= target_read_memory (addr
, buf
, MIPS_INSN32_SIZE
);
5401 inst
= mips_fetch_instruction (gdbarch
, addr
);
5402 op
= itype_op (inst
);
5403 if ((inst
& 0xe0000000) != 0)
5405 rs
= itype_rs (inst
);
5406 rt
= itype_rt (inst
);
5407 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
5408 || op
== 29 /* JALX: bits 011101 */
5411 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
5412 || (rs
== 9 && (rt
& 0x2) == 0)
5413 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
5414 || (rs
== 10 && (rt
& 0x2) == 0))));
5415 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
5418 switch (op
& 0x07) /* extract bits 28,27,26 */
5420 case 0: /* SPECIAL */
5421 op
= rtype_funct (inst
);
5422 return (op
== 8 /* JR */
5423 || op
== 9); /* JALR */
5424 break; /* end SPECIAL */
5425 case 1: /* REGIMM */
5426 rs
= itype_rs (inst
);
5427 rt
= itype_rt (inst
); /* branch condition */
5428 return ((rt
& 0xc) == 0
5429 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
5430 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
5431 || ((rt
& 0x1e) == 0x1c && rs
== 0));
5432 /* BPOSGE32, BPOSGE64: bits 1110x */
5433 break; /* end REGIMM */
5434 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
5440 /* Return non-zero if the ADDR instruction, which must be a 32-bit
5441 instruction if MUSTBE32 is set or can be any instruction otherwise,
5442 has a branch delay slot (i.e. it is a non-compact jump instruction). */
5445 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
5448 gdb_byte buf
[MIPS_INSN16_SIZE
];
5449 unsigned short inst
;
5452 status
= target_read_memory (addr
, buf
, MIPS_INSN16_SIZE
);
5456 inst
= mips_fetch_instruction (gdbarch
, addr
);
5458 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
5459 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
5462 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
5463 This assumes KSSEG exists. */
5466 mips_segment_boundary (CORE_ADDR bpaddr
)
5468 CORE_ADDR mask
= CORE_ADDR_MAX
;
5471 if (sizeof (CORE_ADDR
) == 8)
5472 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
5473 a compiler warning produced where CORE_ADDR is a 32-bit type even
5474 though in that case this is dead code). */
5475 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
5478 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
5479 segsize
= 29; /* 32-bit compatibility segment */
5481 segsize
= 62; /* xkseg */
5483 case 2: /* xkphys */
5486 default: /* xksseg (1), xkuseg/kuseg (0) */
5490 else if (bpaddr
& 0x80000000) /* kernel segment */
5493 segsize
= 31; /* user segment */
5495 return bpaddr
& mask
;
5498 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
5499 it backwards if necessary. Return the address of the new location. */
5502 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5504 CORE_ADDR prev_addr
, next_addr
;
5506 CORE_ADDR func_addr
;
5508 /* If a breakpoint is set on the instruction in a branch delay slot,
5509 GDB gets confused. When the breakpoint is hit, the PC isn't on
5510 the instruction in the branch delay slot, the PC will point to
5511 the branch instruction. Since the PC doesn't match any known
5512 breakpoints, GDB reports a trap exception.
5514 There are two possible fixes for this problem.
5516 1) When the breakpoint gets hit, see if the BD bit is set in the
5517 Cause register (which indicates the last exception occurred in a
5518 branch delay slot). If the BD bit is set, fix the PC to point to
5519 the instruction in the branch delay slot.
5521 2) When the user sets the breakpoint, don't allow him to set the
5522 breakpoint on the instruction in the branch delay slot. Instead
5523 move the breakpoint to the branch instruction (which will have
5526 The problem with the first solution is that if the user then
5527 single-steps the processor, the branch instruction will get
5528 skipped (since GDB thinks the PC is on the instruction in the
5531 So, we'll use the second solution. To do this we need to know if
5532 the instruction we're trying to set the breakpoint on is in the
5533 branch delay slot. */
5535 boundary
= mips_segment_boundary (bpaddr
);
5537 /* Make sure we don't scan back before the beginning of the current
5538 function, since we may fetch constant data or insns that look like
5539 a jump. Of course we might do that anyway if the compiler has
5540 moved constants inline. :-( */
5541 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
5542 && func_addr
> boundary
&& func_addr
<= bpaddr
)
5543 boundary
= func_addr
;
5545 if (!mips_pc_is_mips16 (bpaddr
))
5547 if (bpaddr
== boundary
)
5550 /* If the previous instruction has a branch delay slot, we have
5551 to move the breakpoint to the branch instruction. */
5552 prev_addr
= bpaddr
- 4;
5553 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
5558 struct minimal_symbol
*sym
;
5559 CORE_ADDR addr
, jmpaddr
;
5562 boundary
= unmake_mips16_addr (boundary
);
5564 /* The only MIPS16 instructions with delay slots are JAL, JALX,
5565 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
5566 so try for that first, then try the 2 byte JALR/JR.
5567 FIXME: We have to assume that bpaddr is not the second half
5568 of an extended instruction. */
5572 for (i
= 1; i
< 4; i
++)
5574 if (unmake_mips16_addr (addr
) == boundary
)
5577 if (i
== 1 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 0))
5578 /* Looks like a JR/JALR at [target-1], but it could be
5579 the second word of a previous JAL/JALX, so record it
5580 and check back one more. */
5583 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 1))
5586 /* Looks like a JAL/JALX at [target-2], but it could also
5587 be the second word of a previous JAL/JALX, record it,
5588 and check back one more. */
5591 /* Looks like a JAL/JALX at [target-3], so any previously
5592 recorded JAL/JALX or JR/JALR must be wrong, because:
5595 -2: JAL-ext (can't be JAL/JALX)
5596 -1: bdslot (can't be JR/JALR)
5599 Of course it could be another JAL-ext which looks
5600 like a JAL, but in that case we'd have broken out
5601 of this loop at [target-2]:
5605 -2: bdslot (can't be jmp)
5612 /* Not a jump instruction: if we're at [target-1] this
5613 could be the second word of a JAL/JALX, so continue;
5614 otherwise we're done. */
5627 /* If PC is in a mips16 call or return stub, return the address of the target
5628 PC, which is either the callee or the caller. There are several
5629 cases which must be handled:
5631 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5632 target PC is in $31 ($ra).
5633 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5634 and the target PC is in $2.
5635 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5636 before the jal instruction, this is effectively a call stub
5637 and the target PC is in $2. Otherwise this is effectively
5638 a return stub and the target PC is in $18.
5640 See the source code for the stubs in gcc/config/mips/mips16.S for
5644 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5646 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5648 CORE_ADDR start_addr
;
5650 /* Find the starting address and name of the function containing the PC. */
5651 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5654 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5655 target PC is in $31 ($ra). */
5656 if (strcmp (name
, "__mips16_ret_sf") == 0
5657 || strcmp (name
, "__mips16_ret_df") == 0)
5658 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5660 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5662 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5663 and the target PC is in $2. */
5664 if (name
[19] >= '0' && name
[19] <= '9')
5665 return get_frame_register_signed (frame
, 2);
5667 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5668 before the jal instruction, this is effectively a call stub
5669 and the target PC is in $2. Otherwise this is effectively
5670 a return stub and the target PC is in $18. */
5671 else if (name
[19] == 's' || name
[19] == 'd')
5673 if (pc
== start_addr
)
5675 /* Check if the target of the stub is a compiler-generated
5676 stub. Such a stub for a function bar might have a name
5677 like __fn_stub_bar, and might look like this:
5682 la $1,bar (becomes a lui/addiu pair)
5684 So scan down to the lui/addi and extract the target
5685 address from those two instructions. */
5687 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5690 /* See if the name of the target function is __fn_stub_*. */
5691 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5694 if (strncmp (name
, "__fn_stub_", 10) != 0
5695 && strcmp (name
, "etext") != 0
5696 && strcmp (name
, "_etext") != 0)
5699 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5700 The limit on the search is arbitrarily set to 20
5701 instructions. FIXME. */
5702 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5704 ULONGEST inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5705 CORE_ADDR addr
= inst
;
5707 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5708 pc
= (((addr
& 0xffff) ^ 0x8000) - 0x8000) << 16;
5710 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5711 return pc
+ ((addr
& 0xffff) ^ 0x8000) - 0x8000;
5715 /* Couldn't find the lui/addui pair, so return stub address. */
5719 /* This is the 'return' part of a call stub. The return
5720 address is in $r18. */
5721 return get_frame_register_signed (frame
, 18);
5724 return 0; /* not a stub */
5727 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5728 PC of the stub target. The stub just loads $t9 and jumps to it,
5729 so that $t9 has the correct value at function entry. */
5732 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5734 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5735 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5736 struct minimal_symbol
*msym
;
5738 gdb_byte stub_code
[16];
5739 int32_t stub_words
[4];
5741 /* The stub for foo is named ".pic.foo", and is either two
5742 instructions inserted before foo or a three instruction sequence
5743 which jumps to foo. */
5744 msym
= lookup_minimal_symbol_by_pc (pc
);
5746 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5747 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5748 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5751 /* A two-instruction header. */
5752 if (MSYMBOL_SIZE (msym
) == 8)
5755 /* A three-instruction (plus delay slot) trampoline. */
5756 if (MSYMBOL_SIZE (msym
) == 16)
5758 if (target_read_memory (pc
, stub_code
, 16) != 0)
5760 for (i
= 0; i
< 4; i
++)
5761 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5764 /* A stub contains these instructions:
5767 addiu t9, t9, %lo(target)
5770 This works even for N64, since stubs are only generated with
5772 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5773 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5774 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5775 && stub_words
[3] == 0x00000000)
5776 return ((((stub_words
[0] & 0x0000ffff) << 16)
5777 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
5780 /* Not a recognized stub. */
5785 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5787 CORE_ADDR target_pc
;
5789 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5793 target_pc
= find_solib_trampoline_target (frame
, pc
);
5797 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5804 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5805 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5808 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5811 if (num
>= 0 && num
< 32)
5813 else if (num
>= 38 && num
< 70)
5814 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5816 regnum
= mips_regnum (gdbarch
)->hi
;
5818 regnum
= mips_regnum (gdbarch
)->lo
;
5819 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
5820 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
5822 /* This will hopefully (eventually) provoke a warning. Should
5823 we be calling complaint() here? */
5824 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5825 return gdbarch_num_regs (gdbarch
) + regnum
;
5829 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5830 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5833 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5836 if (num
>= 0 && num
< 32)
5838 else if (num
>= 32 && num
< 64)
5839 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5841 regnum
= mips_regnum (gdbarch
)->hi
;
5843 regnum
= mips_regnum (gdbarch
)->lo
;
5844 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
5845 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
5847 /* This will hopefully (eventually) provoke a warning. Should we
5848 be calling complaint() here? */
5849 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5850 return gdbarch_num_regs (gdbarch
) + regnum
;
5854 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5856 /* Only makes sense to supply raw registers. */
5857 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5858 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5859 decide if it is valid. Should instead define a standard sim/gdb
5860 register numbering scheme. */
5861 if (gdbarch_register_name (gdbarch
,
5862 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5863 && gdbarch_register_name (gdbarch
,
5864 gdbarch_num_regs (gdbarch
)
5865 + regnum
)[0] != '\0')
5868 return LEGACY_SIM_REGNO_IGNORE
;
5872 /* Convert an integer into an address. Extracting the value signed
5873 guarantees a correctly sign extended address. */
5876 mips_integer_to_address (struct gdbarch
*gdbarch
,
5877 struct type
*type
, const gdb_byte
*buf
)
5879 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5880 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5883 /* Dummy virtual frame pointer method. This is no more or less accurate
5884 than most other architectures; we just need to be explicit about it,
5885 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5886 an assertion failure. */
5889 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5890 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5892 *reg
= MIPS_SP_REGNUM
;
5897 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5899 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5900 const char *name
= bfd_get_section_name (abfd
, sect
);
5902 if (*abip
!= MIPS_ABI_UNKNOWN
)
5905 if (strncmp (name
, ".mdebug.", 8) != 0)
5908 if (strcmp (name
, ".mdebug.abi32") == 0)
5909 *abip
= MIPS_ABI_O32
;
5910 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5911 *abip
= MIPS_ABI_N32
;
5912 else if (strcmp (name
, ".mdebug.abi64") == 0)
5913 *abip
= MIPS_ABI_N64
;
5914 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5915 *abip
= MIPS_ABI_O64
;
5916 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5917 *abip
= MIPS_ABI_EABI32
;
5918 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5919 *abip
= MIPS_ABI_EABI64
;
5921 warning (_("unsupported ABI %s."), name
+ 8);
5925 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5927 int *lbp
= (int *) obj
;
5928 const char *name
= bfd_get_section_name (abfd
, sect
);
5930 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5932 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5934 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5935 warning (_("unrecognized .gcc_compiled_longXX"));
5938 static enum mips_abi
5939 global_mips_abi (void)
5943 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5944 if (mips_abi_strings
[i
] == mips_abi_string
)
5945 return (enum mips_abi
) i
;
5947 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5951 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5953 /* If the size matches the set of 32-bit or 64-bit integer registers,
5954 assume that's what we've got. */
5955 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5956 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5958 /* If the size matches the full set of registers GDB traditionally
5959 knows about, including floating point, for either 32-bit or
5960 64-bit, assume that's what we've got. */
5961 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5962 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5964 /* Otherwise we don't have a useful guess. */
5967 static struct value
*
5968 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5970 const int *reg_p
= baton
;
5971 return value_of_register (*reg_p
, frame
);
5974 static struct gdbarch
*
5975 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5977 struct gdbarch
*gdbarch
;
5978 struct gdbarch_tdep
*tdep
;
5980 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5982 enum mips_fpu_type fpu_type
;
5983 struct tdesc_arch_data
*tdesc_data
= NULL
;
5984 int elf_fpu_type
= 0;
5985 const char **reg_names
;
5986 struct mips_regnum mips_regnum
, *regnum
;
5990 /* Fill in the OS dependent register numbers and names. */
5991 if (info
.osabi
== GDB_OSABI_IRIX
)
5993 mips_regnum
.fp0
= 32;
5994 mips_regnum
.pc
= 64;
5995 mips_regnum
.cause
= 65;
5996 mips_regnum
.badvaddr
= 66;
5997 mips_regnum
.hi
= 67;
5998 mips_regnum
.lo
= 68;
5999 mips_regnum
.fp_control_status
= 69;
6000 mips_regnum
.fp_implementation_revision
= 70;
6001 mips_regnum
.dspacc
= dspacc
= -1;
6002 mips_regnum
.dspctl
= dspctl
= -1;
6004 reg_names
= mips_irix_reg_names
;
6006 else if (info
.osabi
== GDB_OSABI_LINUX
)
6008 mips_regnum
.fp0
= 38;
6009 mips_regnum
.pc
= 37;
6010 mips_regnum
.cause
= 36;
6011 mips_regnum
.badvaddr
= 35;
6012 mips_regnum
.hi
= 34;
6013 mips_regnum
.lo
= 33;
6014 mips_regnum
.fp_control_status
= 70;
6015 mips_regnum
.fp_implementation_revision
= 71;
6016 mips_regnum
.dspacc
= -1;
6017 mips_regnum
.dspctl
= -1;
6021 reg_names
= mips_linux_reg_names
;
6025 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
6026 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
6027 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6028 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
6029 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
6030 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
6031 mips_regnum
.fp_control_status
= 70;
6032 mips_regnum
.fp_implementation_revision
= 71;
6033 mips_regnum
.dspacc
= dspacc
= -1;
6034 mips_regnum
.dspctl
= dspctl
= -1;
6035 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6036 if (info
.bfd_arch_info
!= NULL
6037 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6038 reg_names
= mips_tx39_reg_names
;
6040 reg_names
= mips_generic_reg_names
;
6043 /* Check any target description for validity. */
6044 if (tdesc_has_registers (info
.target_desc
))
6046 static const char *const mips_gprs
[] = {
6047 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6048 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6049 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6050 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6052 static const char *const mips_fprs
[] = {
6053 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6054 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6055 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6056 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
6059 const struct tdesc_feature
*feature
;
6062 feature
= tdesc_find_feature (info
.target_desc
,
6063 "org.gnu.gdb.mips.cpu");
6064 if (feature
== NULL
)
6067 tdesc_data
= tdesc_data_alloc ();
6070 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
6071 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6075 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6076 mips_regnum
.lo
, "lo");
6077 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6078 mips_regnum
.hi
, "hi");
6079 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6080 mips_regnum
.pc
, "pc");
6084 tdesc_data_cleanup (tdesc_data
);
6088 feature
= tdesc_find_feature (info
.target_desc
,
6089 "org.gnu.gdb.mips.cp0");
6090 if (feature
== NULL
)
6092 tdesc_data_cleanup (tdesc_data
);
6097 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6098 mips_regnum
.badvaddr
, "badvaddr");
6099 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6100 MIPS_PS_REGNUM
, "status");
6101 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6102 mips_regnum
.cause
, "cause");
6106 tdesc_data_cleanup (tdesc_data
);
6110 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
6111 backend is not prepared for that, though. */
6112 feature
= tdesc_find_feature (info
.target_desc
,
6113 "org.gnu.gdb.mips.fpu");
6114 if (feature
== NULL
)
6116 tdesc_data_cleanup (tdesc_data
);
6121 for (i
= 0; i
< 32; i
++)
6122 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6123 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
6125 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6126 mips_regnum
.fp_control_status
,
6129 &= tdesc_numbered_register (feature
, tdesc_data
,
6130 mips_regnum
.fp_implementation_revision
,
6135 tdesc_data_cleanup (tdesc_data
);
6141 feature
= tdesc_find_feature (info
.target_desc
,
6142 "org.gnu.gdb.mips.dsp");
6143 /* The DSP registers are optional; it's OK if they are absent. */
6144 if (feature
!= NULL
)
6148 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6149 dspacc
+ i
++, "hi1");
6150 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6151 dspacc
+ i
++, "lo1");
6152 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6153 dspacc
+ i
++, "hi2");
6154 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6155 dspacc
+ i
++, "lo2");
6156 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6157 dspacc
+ i
++, "hi3");
6158 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6159 dspacc
+ i
++, "lo3");
6161 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6166 tdesc_data_cleanup (tdesc_data
);
6170 mips_regnum
.dspacc
= dspacc
;
6171 mips_regnum
.dspctl
= dspctl
;
6175 /* It would be nice to detect an attempt to use a 64-bit ABI
6176 when only 32-bit registers are provided. */
6180 /* First of all, extract the elf_flags, if available. */
6181 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6182 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6183 else if (arches
!= NULL
)
6184 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6188 fprintf_unfiltered (gdb_stdlog
,
6189 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6191 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6192 switch ((elf_flags
& EF_MIPS_ABI
))
6194 case E_MIPS_ABI_O32
:
6195 found_abi
= MIPS_ABI_O32
;
6197 case E_MIPS_ABI_O64
:
6198 found_abi
= MIPS_ABI_O64
;
6200 case E_MIPS_ABI_EABI32
:
6201 found_abi
= MIPS_ABI_EABI32
;
6203 case E_MIPS_ABI_EABI64
:
6204 found_abi
= MIPS_ABI_EABI64
;
6207 if ((elf_flags
& EF_MIPS_ABI2
))
6208 found_abi
= MIPS_ABI_N32
;
6210 found_abi
= MIPS_ABI_UNKNOWN
;
6214 /* GCC creates a pseudo-section whose name describes the ABI. */
6215 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6216 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6218 /* If we have no useful BFD information, use the ABI from the last
6219 MIPS architecture (if there is one). */
6220 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6221 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6223 /* Try the architecture for any hint of the correct ABI. */
6224 if (found_abi
== MIPS_ABI_UNKNOWN
6225 && info
.bfd_arch_info
!= NULL
6226 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6228 switch (info
.bfd_arch_info
->mach
)
6230 case bfd_mach_mips3900
:
6231 found_abi
= MIPS_ABI_EABI32
;
6233 case bfd_mach_mips4100
:
6234 case bfd_mach_mips5000
:
6235 found_abi
= MIPS_ABI_EABI64
;
6237 case bfd_mach_mips8000
:
6238 case bfd_mach_mips10000
:
6239 /* On Irix, ELF64 executables use the N64 ABI. The
6240 pseudo-sections which describe the ABI aren't present
6241 on IRIX. (Even for executables created by gcc.) */
6242 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6243 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6244 found_abi
= MIPS_ABI_N64
;
6246 found_abi
= MIPS_ABI_N32
;
6251 /* Default 64-bit objects to N64 instead of O32. */
6252 if (found_abi
== MIPS_ABI_UNKNOWN
6253 && info
.abfd
!= NULL
6254 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6255 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6256 found_abi
= MIPS_ABI_N64
;
6259 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6262 /* What has the user specified from the command line? */
6263 wanted_abi
= global_mips_abi ();
6265 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6268 /* Now that we have found what the ABI for this binary would be,
6269 check whether the user is overriding it. */
6270 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6271 mips_abi
= wanted_abi
;
6272 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6273 mips_abi
= found_abi
;
6275 mips_abi
= MIPS_ABI_O32
;
6277 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6280 /* Also used when doing an architecture lookup. */
6282 fprintf_unfiltered (gdb_stdlog
,
6283 "mips_gdbarch_init: "
6284 "mips64_transfers_32bit_regs_p = %d\n",
6285 mips64_transfers_32bit_regs_p
);
6287 /* Determine the MIPS FPU type. */
6290 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6291 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6292 Tag_GNU_MIPS_ABI_FP
);
6293 #endif /* HAVE_ELF */
6295 if (!mips_fpu_type_auto
)
6296 fpu_type
= mips_fpu_type
;
6297 else if (elf_fpu_type
!= 0)
6299 switch (elf_fpu_type
)
6302 fpu_type
= MIPS_FPU_DOUBLE
;
6305 fpu_type
= MIPS_FPU_SINGLE
;
6309 /* Soft float or unknown. */
6310 fpu_type
= MIPS_FPU_NONE
;
6314 else if (info
.bfd_arch_info
!= NULL
6315 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6316 switch (info
.bfd_arch_info
->mach
)
6318 case bfd_mach_mips3900
:
6319 case bfd_mach_mips4100
:
6320 case bfd_mach_mips4111
:
6321 case bfd_mach_mips4120
:
6322 fpu_type
= MIPS_FPU_NONE
;
6324 case bfd_mach_mips4650
:
6325 fpu_type
= MIPS_FPU_SINGLE
;
6328 fpu_type
= MIPS_FPU_DOUBLE
;
6331 else if (arches
!= NULL
)
6332 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6334 fpu_type
= MIPS_FPU_DOUBLE
;
6336 fprintf_unfiltered (gdb_stdlog
,
6337 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6339 /* Check for blatant incompatibilities. */
6341 /* If we have only 32-bit registers, then we can't debug a 64-bit
6343 if (info
.target_desc
6344 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
6345 && mips_abi
!= MIPS_ABI_EABI32
6346 && mips_abi
!= MIPS_ABI_O32
)
6348 if (tdesc_data
!= NULL
)
6349 tdesc_data_cleanup (tdesc_data
);
6353 /* Try to find a pre-existing architecture. */
6354 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6356 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6358 /* MIPS needs to be pedantic about which ABI the object is
6360 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6362 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6364 /* Need to be pedantic about which register virtual size is
6366 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6367 != mips64_transfers_32bit_regs_p
)
6369 /* Be pedantic about which FPU is selected. */
6370 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6373 if (tdesc_data
!= NULL
)
6374 tdesc_data_cleanup (tdesc_data
);
6375 return arches
->gdbarch
;
6378 /* Need a new architecture. Fill in a target specific vector. */
6379 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6380 gdbarch
= gdbarch_alloc (&info
, tdep
);
6381 tdep
->elf_flags
= elf_flags
;
6382 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6383 tdep
->found_abi
= found_abi
;
6384 tdep
->mips_abi
= mips_abi
;
6385 tdep
->mips_fpu_type
= fpu_type
;
6386 tdep
->register_size_valid_p
= 0;
6387 tdep
->register_size
= 0;
6388 tdep
->gregset
= NULL
;
6389 tdep
->gregset64
= NULL
;
6390 tdep
->fpregset
= NULL
;
6391 tdep
->fpregset64
= NULL
;
6393 if (info
.target_desc
)
6395 /* Some useful properties can be inferred from the target. */
6396 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
6398 tdep
->register_size_valid_p
= 1;
6399 tdep
->register_size
= 4;
6401 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
6403 tdep
->register_size_valid_p
= 1;
6404 tdep
->register_size
= 8;
6408 /* Initially set everything according to the default ABI/ISA. */
6409 set_gdbarch_short_bit (gdbarch
, 16);
6410 set_gdbarch_int_bit (gdbarch
, 32);
6411 set_gdbarch_float_bit (gdbarch
, 32);
6412 set_gdbarch_double_bit (gdbarch
, 64);
6413 set_gdbarch_long_double_bit (gdbarch
, 64);
6414 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6415 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6416 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6418 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6419 mips_ax_pseudo_register_collect
);
6420 set_gdbarch_ax_pseudo_register_push_stack
6421 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6423 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6424 mips_elf_make_msymbol_special
);
6426 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
6427 *regnum
= mips_regnum
;
6428 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6429 set_gdbarch_num_regs (gdbarch
, num_regs
);
6430 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6431 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6432 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6433 tdep
->mips_processor_reg_names
= reg_names
;
6434 tdep
->regnum
= regnum
;
6439 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6440 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6441 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6442 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6443 tdep
->default_mask_address_p
= 0;
6444 set_gdbarch_long_bit (gdbarch
, 32);
6445 set_gdbarch_ptr_bit (gdbarch
, 32);
6446 set_gdbarch_long_long_bit (gdbarch
, 64);
6449 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6450 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6451 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6452 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6453 tdep
->default_mask_address_p
= 0;
6454 set_gdbarch_long_bit (gdbarch
, 32);
6455 set_gdbarch_ptr_bit (gdbarch
, 32);
6456 set_gdbarch_long_long_bit (gdbarch
, 64);
6458 case MIPS_ABI_EABI32
:
6459 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6460 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6461 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6462 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6463 tdep
->default_mask_address_p
= 0;
6464 set_gdbarch_long_bit (gdbarch
, 32);
6465 set_gdbarch_ptr_bit (gdbarch
, 32);
6466 set_gdbarch_long_long_bit (gdbarch
, 64);
6468 case MIPS_ABI_EABI64
:
6469 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6470 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6471 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6472 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6473 tdep
->default_mask_address_p
= 0;
6474 set_gdbarch_long_bit (gdbarch
, 64);
6475 set_gdbarch_ptr_bit (gdbarch
, 64);
6476 set_gdbarch_long_long_bit (gdbarch
, 64);
6479 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6480 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6481 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6482 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6483 tdep
->default_mask_address_p
= 0;
6484 set_gdbarch_long_bit (gdbarch
, 32);
6485 set_gdbarch_ptr_bit (gdbarch
, 32);
6486 set_gdbarch_long_long_bit (gdbarch
, 64);
6487 set_gdbarch_long_double_bit (gdbarch
, 128);
6488 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6491 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6492 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6493 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6494 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6495 tdep
->default_mask_address_p
= 0;
6496 set_gdbarch_long_bit (gdbarch
, 64);
6497 set_gdbarch_ptr_bit (gdbarch
, 64);
6498 set_gdbarch_long_long_bit (gdbarch
, 64);
6499 set_gdbarch_long_double_bit (gdbarch
, 128);
6500 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6503 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6506 /* GCC creates a pseudo-section whose name specifies the size of
6507 longs, since -mlong32 or -mlong64 may be used independent of
6508 other options. How those options affect pointer sizes is ABI and
6509 architecture dependent, so use them to override the default sizes
6510 set by the ABI. This table shows the relationship between ABI,
6511 -mlongXX, and size of pointers:
6513 ABI -mlongXX ptr bits
6514 --- -------- --------
6528 Note that for o32 and eabi32, pointers are always 32 bits
6529 regardless of any -mlongXX option. For all others, pointers and
6530 longs are the same, as set by -mlongXX or set by defaults. */
6532 if (info
.abfd
!= NULL
)
6536 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6539 set_gdbarch_long_bit (gdbarch
, long_bit
);
6543 case MIPS_ABI_EABI32
:
6548 case MIPS_ABI_EABI64
:
6549 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6552 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6557 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6558 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6561 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6562 flag in object files because to do so would make it impossible to
6563 link with libraries compiled without "-gp32". This is
6564 unnecessarily restrictive.
6566 We could solve this problem by adding "-gp32" multilibs to gcc,
6567 but to set this flag before gcc is built with such multilibs will
6568 break too many systems.''
6570 But even more unhelpfully, the default linker output target for
6571 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6572 for 64-bit programs - you need to change the ABI to change this,
6573 and not all gcc targets support that currently. Therefore using
6574 this flag to detect 32-bit mode would do the wrong thing given
6575 the current gcc - it would make GDB treat these 64-bit programs
6576 as 32-bit programs by default. */
6578 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6579 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6581 /* Add/remove bits from an address. The MIPS needs be careful to
6582 ensure that all 32 bit addresses are sign extended to 64 bits. */
6583 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6585 /* Unwind the frame. */
6586 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6587 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6588 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6590 /* Map debug register numbers onto internal register numbers. */
6591 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6592 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6593 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6594 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6595 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6596 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6598 /* MIPS version of CALL_DUMMY. */
6600 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6601 replaced by a command, and all targets will default to on stack
6602 (regardless of the stack's execute status). */
6603 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6604 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6606 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6607 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6608 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6610 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6611 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6612 set_gdbarch_adjust_breakpoint_address (gdbarch
,
6613 mips_adjust_breakpoint_address
);
6615 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6617 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6619 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6620 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6621 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6623 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6625 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6627 if (mips_abi
== MIPS_ABI_N32
)
6628 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6629 else if (mips_abi
== MIPS_ABI_N64
)
6630 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6632 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6634 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6635 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6636 need to all be folded into the target vector. Since they are
6637 being used as guards for target_stopped_by_watchpoint, why not have
6638 target_stopped_by_watchpoint return the type of watchpoint that the code
6640 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6642 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6644 set_gdbarch_single_step_through_delay (gdbarch
,
6645 mips_single_step_through_delay
);
6647 /* Virtual tables. */
6648 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6650 mips_register_g_packet_guesses (gdbarch
);
6652 /* Hook in OS ABI-specific overrides, if they have been registered. */
6653 info
.tdep_info
= (void *) tdesc_data
;
6654 gdbarch_init_osabi (info
, gdbarch
);
6656 /* The hook may have adjusted num_regs, fetch the final value and
6657 set pc_regnum and sp_regnum now that it has been fixed. */
6658 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6659 replaced by gdbarch_read_pc? */
6660 num_regs
= gdbarch_num_regs (gdbarch
);
6661 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6662 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6664 /* Unwind the frame. */
6665 dwarf2_append_unwinders (gdbarch
);
6666 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6667 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6668 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6669 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6670 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6671 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6672 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6676 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6677 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6679 /* Override the normal target description methods to handle our
6680 dual real and pseudo registers. */
6681 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6682 set_gdbarch_register_reggroup_p (gdbarch
,
6683 mips_tdesc_register_reggroup_p
);
6685 num_regs
= gdbarch_num_regs (gdbarch
);
6686 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6687 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6688 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6691 /* Add ABI-specific aliases for the registers. */
6692 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6693 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6694 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6695 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6697 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6698 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6699 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6701 /* Add some other standard aliases. */
6702 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6703 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6704 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6706 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6707 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6708 value_of_mips_user_reg
,
6709 &mips_numeric_register_aliases
[i
].regnum
);
6715 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6717 struct gdbarch_info info
;
6719 /* Force the architecture to update, and (if it's a MIPS architecture)
6720 mips_gdbarch_init will take care of the rest. */
6721 gdbarch_info_init (&info
);
6722 gdbarch_update_p (info
);
6725 /* Print out which MIPS ABI is in use. */
6728 show_mips_abi (struct ui_file
*file
,
6730 struct cmd_list_element
*ignored_cmd
,
6731 const char *ignored_value
)
6733 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6736 "The MIPS ABI is unknown because the current architecture "
6740 enum mips_abi global_abi
= global_mips_abi ();
6741 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6742 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6744 if (global_abi
== MIPS_ABI_UNKNOWN
)
6747 "The MIPS ABI is set automatically (currently \"%s\").\n",
6749 else if (global_abi
== actual_abi
)
6752 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6756 /* Probably shouldn't happen... */
6757 fprintf_filtered (file
,
6758 "The (auto detected) MIPS ABI \"%s\" is in use "
6759 "even though the user setting was \"%s\".\n",
6760 actual_abi_str
, mips_abi_strings
[global_abi
]);
6766 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6768 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6772 int ef_mips_32bitmode
;
6773 /* Determine the ISA. */
6774 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6792 /* Determine the size of a pointer. */
6793 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6794 fprintf_unfiltered (file
,
6795 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6797 fprintf_unfiltered (file
,
6798 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6800 fprintf_unfiltered (file
,
6801 "mips_dump_tdep: ef_mips_arch = %d\n",
6803 fprintf_unfiltered (file
,
6804 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6805 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6806 fprintf_unfiltered (file
,
6808 "mips_mask_address_p() %d (default %d)\n",
6809 mips_mask_address_p (tdep
),
6810 tdep
->default_mask_address_p
);
6812 fprintf_unfiltered (file
,
6813 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6814 MIPS_DEFAULT_FPU_TYPE
,
6815 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6816 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6817 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6819 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6820 MIPS_EABI (gdbarch
));
6821 fprintf_unfiltered (file
,
6822 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6823 MIPS_FPU_TYPE (gdbarch
),
6824 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6825 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6826 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6830 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6833 _initialize_mips_tdep (void)
6835 static struct cmd_list_element
*mipsfpulist
= NULL
;
6836 struct cmd_list_element
*c
;
6838 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6839 if (MIPS_ABI_LAST
+ 1
6840 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6841 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6843 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6845 mips_pdr_data
= register_objfile_data ();
6847 /* Create feature sets with the appropriate properties. The values
6848 are not important. */
6849 mips_tdesc_gp32
= allocate_target_description ();
6850 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6852 mips_tdesc_gp64
= allocate_target_description ();
6853 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6855 /* Add root prefix command for all "set mips"/"show mips" commands. */
6856 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6857 _("Various MIPS specific commands."),
6858 &setmipscmdlist
, "set mips ", 0, &setlist
);
6860 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6861 _("Various MIPS specific commands."),
6862 &showmipscmdlist
, "show mips ", 0, &showlist
);
6864 /* Allow the user to override the ABI. */
6865 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6866 &mips_abi_string
, _("\
6867 Set the MIPS ABI used by this program."), _("\
6868 Show the MIPS ABI used by this program."), _("\
6869 This option can be set to one of:\n\
6870 auto - the default ABI associated with the current binary\n\
6879 &setmipscmdlist
, &showmipscmdlist
);
6881 /* Let the user turn off floating point and set the fence post for
6882 heuristic_proc_start. */
6884 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6885 _("Set use of MIPS floating-point coprocessor."),
6886 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6887 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6888 _("Select single-precision MIPS floating-point coprocessor."),
6890 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6891 _("Select double-precision MIPS floating-point coprocessor."),
6893 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6894 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6895 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6896 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6897 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6898 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6899 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6900 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6901 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6902 _("Select MIPS floating-point coprocessor automatically."),
6904 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6905 _("Show current use of MIPS floating-point coprocessor target."),
6908 /* We really would like to have both "0" and "unlimited" work, but
6909 command.c doesn't deal with that. So make it a var_zinteger
6910 because the user can always use "999999" or some such for unlimited. */
6911 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6912 &heuristic_fence_post
, _("\
6913 Set the distance searched for the start of a function."), _("\
6914 Show the distance searched for the start of a function."), _("\
6915 If you are debugging a stripped executable, GDB needs to search through the\n\
6916 program for the start of a function. This command sets the distance of the\n\
6917 search. The only need to set it is when debugging a stripped executable."),
6918 reinit_frame_cache_sfunc
,
6919 NULL
, /* FIXME: i18n: The distance searched for
6920 the start of a function is %s. */
6921 &setlist
, &showlist
);
6923 /* Allow the user to control whether the upper bits of 64-bit
6924 addresses should be zeroed. */
6925 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6926 &mask_address_var
, _("\
6927 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6928 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6929 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6930 allow GDB to determine the correct value."),
6931 NULL
, show_mask_address
,
6932 &setmipscmdlist
, &showmipscmdlist
);
6934 /* Allow the user to control the size of 32 bit registers within the
6935 raw remote packet. */
6936 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6937 &mips64_transfers_32bit_regs_p
, _("\
6938 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6940 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6942 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6943 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6944 64 bits for others. Use \"off\" to disable compatibility mode"),
6945 set_mips64_transfers_32bit_regs
,
6946 NULL
, /* FIXME: i18n: Compatibility with 64-bit
6947 MIPS target that transfers 32-bit
6948 quantities is %s. */
6949 &setlist
, &showlist
);
6951 /* Debug this files internals. */
6952 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6954 Set mips debugging."), _("\
6955 Show mips debugging."), _("\
6956 When non-zero, mips specific debugging is enabled."),
6958 NULL
, /* FIXME: i18n: Mips debugging is
6960 &setdebuglist
, &showdebuglist
);