1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 struct frame_extra_info
41 mips_extra_func_info_t proc_desc
;
45 /* Some MIPS boards don't support floating point while others only
46 support single-precision floating-point operations. See also
47 FP_REGISTER_DOUBLE. */
51 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
52 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
53 MIPS_FPU_NONE
/* No floating point. */
56 #ifndef MIPS_DEFAULT_FPU_TYPE
57 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
59 static int mips_fpu_type_auto
= 1;
60 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
61 #define MIPS_FPU_TYPE mips_fpu_type
63 #ifndef MIPS_SAVED_REGSIZE
64 #define MIPS_SAVED_REGSIZE MIPS_REGSIZE
67 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
68 #ifndef FP_REGISTER_DOUBLE
69 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
73 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
76 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
79 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
81 static void mips_print_register
PARAMS ((int, int));
83 static mips_extra_func_info_t
84 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
86 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
88 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
90 void mips_set_processor_type_command
PARAMS ((char *, int));
92 int mips_set_processor_type
PARAMS ((char *));
94 static void mips_show_processor_type_command
PARAMS ((char *, int));
96 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
97 struct cmd_list_element
*));
99 static mips_extra_func_info_t
100 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
102 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
103 mips_extra_func_info_t proc_desc
));
105 /* This value is the model of MIPS in use. It is derived from the value
106 of the PrID register. */
108 char *mips_processor_type
;
110 char *tmp_mips_processor_type
;
112 /* A set of original names, to be used when restoring back to generic
113 registers from a specific set. */
115 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
116 char **mips_processor_reg_names
= mips_generic_reg_names
;
119 mips_register_name (i
)
122 return mips_processor_reg_names
[i
];
126 /* Names of IDT R3041 registers. */
128 char *mips_r3041_reg_names
[] = {
129 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
130 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
131 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
132 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
133 "sr", "lo", "hi", "bad", "cause","pc",
134 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
135 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
136 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
137 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
138 "fsr", "fir", "fp", "",
139 "", "", "bus", "ccfg", "", "", "", "",
140 "", "", "port", "cmp", "", "", "epc", "prid",
143 /* Names of IDT R3051 registers. */
145 char *mips_r3051_reg_names
[] = {
146 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
147 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
148 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
149 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
150 "sr", "lo", "hi", "bad", "cause","pc",
151 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
152 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
153 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
154 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
155 "fsr", "fir", "fp", "",
156 "inx", "rand", "elo", "", "ctxt", "", "", "",
157 "", "", "ehi", "", "", "", "epc", "prid",
160 /* Names of IDT R3081 registers. */
162 char *mips_r3081_reg_names
[] = {
163 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
164 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
165 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
166 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
167 "sr", "lo", "hi", "bad", "cause","pc",
168 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
169 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
170 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
171 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
172 "fsr", "fir", "fp", "",
173 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
174 "", "", "ehi", "", "", "", "epc", "prid",
177 /* Names of LSI 33k registers. */
179 char *mips_lsi33k_reg_names
[] = {
180 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
181 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
182 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
183 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
184 "epc", "hi", "lo", "sr", "cause","badvaddr",
185 "dcic", "bpc", "bda", "", "", "", "", "",
186 "", "", "", "", "", "", "", "",
187 "", "", "", "", "", "", "", "",
188 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
191 "", "", "", "", "", "", "", "",
197 } mips_processor_type_table
[] = {
198 { "generic", mips_generic_reg_names
},
199 { "r3041", mips_r3041_reg_names
},
200 { "r3051", mips_r3051_reg_names
},
201 { "r3071", mips_r3081_reg_names
},
202 { "r3081", mips_r3081_reg_names
},
203 { "lsi33k", mips_lsi33k_reg_names
},
207 /* Table to translate MIPS16 register field to actual register number. */
208 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
210 /* Heuristic_proc_start may hunt through the text section for a long
211 time across a 2400 baud serial line. Allows the user to limit this
214 static unsigned int heuristic_fence_post
= 0;
216 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
217 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
218 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
219 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
220 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
221 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
222 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
223 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
224 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
225 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
226 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
227 #define _PROC_MAGIC_ 0x0F0F0F0F
228 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
229 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
231 struct linked_proc_info
233 struct mips_extra_func_info info
;
234 struct linked_proc_info
*next
;
235 } *linked_proc_desc_table
= NULL
;
238 mips_print_extra_frame_info (fi
)
239 struct frame_info
*fi
;
243 && fi
->extra_info
->proc_desc
244 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
245 printf_filtered (" frame pointer is at %s+%d\n",
246 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
247 fi
->extra_info
->proc_desc
->pdr
.frameoffset
);
250 /* Should the upper word of 64-bit addresses be zeroed? */
251 static int mask_address_p
= 1;
253 /* Should call_function allocate stack space for a struct return? */
255 mips_use_struct_convention (gcc_p
, type
)
260 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
262 return 1; /* Structures are returned by ref in extra arg0 */
265 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
268 pc_is_mips16 (bfd_vma memaddr
)
270 struct minimal_symbol
*sym
;
272 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
273 if (IS_MIPS16_ADDR (memaddr
))
276 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
277 the high bit of the info field. Use this to decide if the function is
278 MIPS16 or normal MIPS. */
279 sym
= lookup_minimal_symbol_by_pc (memaddr
);
281 return MSYMBOL_IS_SPECIAL (sym
);
287 /* This returns the PC of the first inst after the prologue. If we can't
288 find the prologue, then return 0. */
291 after_prologue (pc
, proc_desc
)
293 mips_extra_func_info_t proc_desc
;
295 struct symtab_and_line sal
;
296 CORE_ADDR func_addr
, func_end
;
299 proc_desc
= find_proc_desc (pc
, NULL
);
303 /* If function is frameless, then we need to do it the hard way. I
304 strongly suspect that frameless always means prologueless... */
305 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
306 && PROC_FRAME_OFFSET (proc_desc
) == 0)
310 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
311 return 0; /* Unknown */
313 sal
= find_pc_line (func_addr
, 0);
315 if (sal
.end
< func_end
)
318 /* The line after the prologue is after the end of the function. In this
319 case, tell the caller to find the prologue the hard way. */
324 /* Decode a MIPS32 instruction that saves a register in the stack, and
325 set the appropriate bit in the general register mask or float register mask
326 to indicate which register is saved. This is a helper function
327 for mips_find_saved_regs. */
330 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
332 unsigned long *gen_mask
;
333 unsigned long *float_mask
;
337 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
338 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
339 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
341 /* It might be possible to use the instruction to
342 find the offset, rather than the code below which
343 is based on things being in a certain order in the
344 frame, but figuring out what the instruction's offset
345 is relative to might be a little tricky. */
346 reg
= (inst
& 0x001f0000) >> 16;
347 *gen_mask
|= (1 << reg
);
349 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
350 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
351 || (inst
& 0xffe00000) == 0xf7a00000)/* sdc1 freg,n($sp) */
354 reg
= ((inst
& 0x001f0000) >> 16);
355 *float_mask
|= (1 << reg
);
359 /* Decode a MIPS16 instruction that saves a register in the stack, and
360 set the appropriate bit in the general register or float register mask
361 to indicate which register is saved. This is a helper function
362 for mips_find_saved_regs. */
365 mips16_decode_reg_save (inst
, gen_mask
)
367 unsigned long *gen_mask
;
369 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
371 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
372 *gen_mask
|= (1 << reg
);
374 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
376 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
377 *gen_mask
|= (1 << reg
);
379 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
380 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
381 *gen_mask
|= (1 << RA_REGNUM
);
385 /* Fetch and return instruction from the specified location. If the PC
386 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
389 mips_fetch_instruction (addr
)
392 char buf
[MIPS_INSTLEN
];
396 if (pc_is_mips16 (addr
))
398 instlen
= MIPS16_INSTLEN
;
399 addr
= UNMAKE_MIPS16_ADDR (addr
);
402 instlen
= MIPS_INSTLEN
;
403 status
= read_memory_nobpt (addr
, buf
, instlen
);
405 memory_error (status
, addr
);
406 return extract_unsigned_integer (buf
, instlen
);
410 /* These the fields of 32 bit mips instructions */
411 #define mips32_op(x) (x >> 25)
412 #define itype_op(x) (x >> 25)
413 #define itype_rs(x) ((x >> 21)& 0x1f)
414 #define itype_rt(x) ((x >> 16) & 0x1f)
415 #define itype_immediate(x) ( x & 0xffff)
417 #define jtype_op(x) (x >> 25)
418 #define jtype_target(x) ( x & 0x03fffff)
420 #define rtype_op(x) (x >>25)
421 #define rtype_rs(x) ((x>>21) & 0x1f)
422 #define rtype_rt(x) ((x>>16) & 0x1f)
423 #define rtype_rd(x) ((x>>11) & 0x1f)
424 #define rtype_shamt(x) ((x>>6) & 0x1f)
425 #define rtype_funct(x) (x & 0x3f )
428 mips32_relative_offset(unsigned long inst
)
430 x
= itype_immediate(inst
) ;
431 if (x
& 0x8000) /* sign bit set */
433 x
|= 0xffff0000 ; /* sign extension */
439 /* Determine whate to set a single step breakpoint while considering
442 mips32_next_pc(CORE_ADDR pc
)
446 inst
= mips_fetch_instruction(pc
) ;
447 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
448 { if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
449 { op
= ((inst
>> 25) & 0x03) ;
452 case 0 : goto equal_branch
; /* BEQL */
453 case 1 : goto neq_branch
; /* BNEZ */
454 case 2 : goto less_branch
; /* BLEZ */
455 case 3 : goto greater_branch
; /* BGTZ */
459 else pc
+= 4 ; /* Not a branch, next instruction is easy */
462 { /* This gets way messy */
464 /* Further subdivide into SPECIAL, REGIMM and other */
465 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
467 case 0 : /* SPECIAL */
468 op
= rtype_funct(inst
) ;
473 pc
= read_register(rtype_rs(inst
)) ; /* Set PC to that address */
478 break ; /* end special */
479 case 1 : /* REGIMM */
481 op
= jtype_op(inst
) ; /* branch condition */
482 switch (jtype_op(inst
))
486 case 16 : /* BLTZALL */
487 case 18 : /* BLTZALL */
489 if (read_register(itype_rs(inst
)) < 0)
490 pc
+= mips32_relative_offset(inst
) + 4 ;
491 else pc
+= 8 ; /* after the delay slot */
495 case 17 : /* BGEZAL */
496 case 19 : /* BGEZALL */
497 greater_equal_branch
:
498 if (read_register(itype_rs(inst
)) >= 0)
499 pc
+= mips32_relative_offset(inst
) + 4 ;
500 else pc
+= 8 ; /* after the delay slot */
502 /* All of the other intructions in the REGIMM catagory */
506 break ; /* end REGIMM */
509 { unsigned long reg
;
510 reg
= jtype_target(inst
) << 2 ;
511 pc
= reg
+ ((pc
+4) & 0xf0000000) ;
512 /* Whats this mysterious 0xf000000 adjustment ??? */
515 /* FIXME case JALX :*/
516 { unsigned long reg
;
517 reg
= jtype_target(inst
) << 2 ;
518 pc
= reg
+ ((pc
+4) & 0xf0000000) + 1 ; /* yes, +1 */
519 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
521 break ; /* The new PC will be alternate mode */
522 case 4 : /* BEQ , BEQL */
524 if (read_register(itype_rs(inst
)) ==
525 read_register(itype_rt(inst
)))
526 pc
+= mips32_relative_offset(inst
) + 4 ;
529 case 5 : /* BNE , BNEL */
531 if (read_register(itype_rs(inst
)) !=
532 read_register(itype_rs(inst
)))
533 pc
+= mips32_relative_offset(inst
) + 4 ;
536 case 6 : /* BLEZ , BLEZL */
538 if (read_register(itype_rs(inst
) <= 0))
539 pc
+= mips32_relative_offset(inst
) + 4 ;
543 greater_branch
: /* BGTZ BGTZL */
544 if (read_register(itype_rs(inst
) > 0))
545 pc
+= mips32_relative_offset(inst
) + 4 ;
552 } /* mips32_next_pc */
554 /* Decoding the next place to set a breakpoint is irregular for the
555 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
556 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
557 We dont want to set a single step instruction on the extend instruction
561 /* Lots of mips16 instruction formats */
562 /* Predicting jumps requires itype,ritype,i8type
563 and their extensions extItype,extritype,extI8type
565 enum mips16_inst_fmts
567 itype
, /* 0 immediate 5,10 */
568 ritype
, /* 1 5,3,8 */
569 rrtype
, /* 2 5,3,3,5 */
570 rritype
, /* 3 5,3,3,5 */
571 rrrtype
, /* 4 5,3,3,3,2 */
572 rriatype
, /* 5 5,3,3,1,4 */
573 shifttype
, /* 6 5,3,3,3,2 */
574 i8type
, /* 7 5,3,8 */
575 i8movtype
, /* 8 5,3,3,5 */
576 i8mov32rtype
, /* 9 5,3,5,3 */
577 i64type
, /* 10 5,3,8 */
578 ri64type
, /* 11 5,3,3,5 */
579 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
580 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
581 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
582 extRRItype
, /* 15 5,5,5,5,3,3,5 */
583 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
584 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
585 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
586 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
587 extRi64type
, /* 20 5,6,5,5,3,3,5 */
588 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
590 /* I am heaping all the fields of the formats into one structure and then,
591 only the fields which are involved in instruction extension */
594 unsigned short inst
;
595 enum mips16_inst_fmts fmt
;
596 unsigned long offset
;
597 unsigned int regx
; /* Function in i8 type */
603 static void print_unpack(char * comment
,
604 struct upk_mips16
* u
)
606 printf("%s %04x ,f(%d) off(%08x) (x(%x) y(%x)\n",
607 comment
,u
->inst
,u
->fmt
,u
->offset
,u
->regx
,u
->regy
) ;
610 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
611 format for the bits which make up the immediatate extension.
614 extended_offset(unsigned long extension
)
616 unsigned long value
;
617 value
= (extension
>> 21) & 0x3f ; /* * extract 15:11 */
619 value
|= (extension
>> 16) & 0x1f ; /* extrace 10:5 */
621 value
|= extension
& 0x01f ; /* extract 4:0 */
625 /* Only call this function if you know that this is an extendable
626 instruction, It wont malfunction, but why make excess remote memory references?
627 If the immediate operands get sign extended or somthing, do it after
628 the extension is performed.
630 /* FIXME: Every one of these cases needs to worry about sign extension
631 when the offset is to be used in relative addressing */
634 static unsigned short fetch_mips_16(CORE_ADDR pc
)
637 pc
&= 0xfffffffe ; /* clear the low order bit */
638 target_read_memory(pc
,buf
,2) ;
639 return extract_unsigned_integer(buf
,2) ;
643 unpack_mips16(CORE_ADDR pc
,
644 struct upk_mips16
* upk
)
647 unsigned long extension
;
649 extpc
= (pc
- 4) & ~0x01 ; /* Extensions are 32 bit instructions */
650 /* Decrement to previous address and loose the 16bit mode flag */
651 /* return if the instruction was extendable, but not actually extended */
652 extended
= ((mips32_op(extension
) == 30) ? 1 : 0) ;
653 if (extended
) { extension
= mips_fetch_instruction(extpc
) ;}
658 unsigned long value
;
660 { value
= extended_offset(extension
) ;
661 value
= value
<< 11 ; /* rom for the original value */
662 value
|= upk
->inst
& 0x7ff ; /* eleven bits from instruction */
665 { value
= upk
->inst
& 0x7ff ;
666 /* FIXME : Consider sign extension */
668 upk
->offset
= value
;
673 { /* A register identifier and an offset */
674 /* Most of the fields are the same as I type but the
675 immediate value is of a different length */
676 unsigned long value
;
679 value
= extended_offset(extension
) ;
680 value
= value
<< 8 ; /* from the original instruction */
681 value
|= upk
->inst
& 0xff ; /* eleven bits from instruction */
682 upk
->regx
= (extension
>> 8) & 0x07 ; /* or i8 funct */
683 if (value
& 0x4000) /* test the sign bit , bit 26 */
684 { value
&= ~ 0x3fff ; /* remove the sign bit */
689 value
= upk
->inst
& 0xff ; /* 8 bits */
690 upk
->regx
= (upk
->inst
>> 8) & 0x07 ; /* or i8 funct */
691 /* FIXME: Do sign extension , this format needs it */
692 if (value
& 0x80) /* THIS CONFUSES ME */
693 { value
&= 0xef ; /* remove the sign bit */
698 upk
->offset
= value
;
703 unsigned long value
;
704 unsigned short nexthalf
;
705 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f) ;
706 value
= value
<< 16 ;
707 nexthalf
= mips_fetch_instruction(pc
+2) ; /* low bit still set */
709 upk
->offset
= value
;
713 printf_filtered("Decoding unimplemented instruction format type\n") ;
716 /* print_unpack("UPK",upk) ; */
720 #define mips16_op(x) (x >> 11)
722 /* This is a map of the opcodes which ae known to perform branches */
723 static unsigned char map16
[32] =
730 static CORE_ADDR
add_offset_16(CORE_ADDR pc
, int offset
)
732 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000))) ;
738 static struct upk_mips16 upk
;
740 CORE_ADDR
mips16_next_pc(CORE_ADDR pc
)
744 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
745 inst
= fetch_mips_16(pc
) ;
747 op
= mips16_op(upk
.inst
) ;
753 case 2 : /* Branch */
755 unpack_mips16(pc
,&upk
) ;
757 offset
= upk
.offset
;
762 pc
+= (offset
<< 1) + 2 ;
765 case 3 : /* JAL , JALX - Watch out, these are 32 bit instruction*/
767 unpack_mips16(pc
,&upk
) ;
768 pc
= add_offset_16(pc
,upk
.offset
) ;
769 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
770 pc
= pc
& ~ 0x01 ; /* Clear low bit, indicate 32 bit mode */
775 unpack_mips16(pc
,&upk
) ;
776 reg
= read_register(upk
.regx
) ;
778 pc
+= (upk
.offset
<< 1) + 2 ;
783 unpack_mips16(pc
,&upk
) ;
784 reg
= read_register(upk
.regx
) ;
786 pc
+= (upk
.offset
<< 1) + 2 ;
789 case 12 : /* I8 Formats btez btnez */
791 unpack_mips16(pc
,&upk
) ;
792 /* upk.regx contains the opcode */
793 reg
= read_register(24) ; /* Test register is 24 */
794 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
795 || ((upk
.regx
== 1 ) && (reg
!= 0))) /* BTNEZ */
796 /* pc = add_offset_16(pc,upk.offset) ; */
797 pc
+= (upk
.offset
<< 1) + 2 ;
800 case 29 : /* RR Formats JR, JALR, JALR-RA */
802 op
= upk
.inst
& 0x1f ;
805 upk
.regx
= (upk
.inst
>> 8) & 0x07 ;
806 upk
.regy
= (upk
.inst
>> 5) & 0x07 ;
809 case 0 : reg
= upk
.regx
; break ;
810 case 1 : reg
= 31 ; break ; /* Function return instruction*/
811 case 2 : reg
= upk
.regx
; break ;
812 default: reg
= 31 ; break ; /* BOGUS Guess */
814 pc
= read_register(reg
) ;
818 case 30 : /* This is an extend instruction */
819 pc
+= 4 ; /* Dont be setting breakpints on the second half */
822 printf("Filtered - next PC probably incorrrect due to jump inst\n");
827 else pc
+= 2 ; /* just a good old instruction */
828 /* See if we CAN actually break on the next instruction */
829 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
831 } /* mips16_next_pc */
833 /* The mips_next_pc function supports single_tep when the remote target monitor or
834 stub is not developed enough to so a single_step.
835 It works by decoding the current instruction and predicting where a branch
836 will go. This isnt hard because all the data is available.
837 The MIPS32 and MIPS16 variants are quite different
839 CORE_ADDR
mips_next_pc(CORE_ADDR pc
)
842 /* inst = mips_fetch_instruction(pc) ; */
843 /* if (pc_is_mips16) <----- This is failing */
845 return mips16_next_pc(pc
) ;
846 else return mips32_next_pc(pc
) ;
849 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
853 mips_find_saved_regs (fci
)
854 struct frame_info
*fci
;
857 CORE_ADDR reg_position
;
858 /* r0 bit means kernel trap */
860 /* What registers have been saved? Bitmasks. */
861 unsigned long gen_mask
, float_mask
;
862 mips_extra_func_info_t proc_desc
;
865 frame_saved_regs_zalloc (fci
);
867 /* If it is the frame for sigtramp, the saved registers are located
868 in a sigcontext structure somewhere on the stack.
869 If the stack layout for sigtramp changes we might have to change these
870 constants and the companion fixup_sigtramp in mdebugread.c */
871 #ifndef SIGFRAME_BASE
872 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
873 above the sigtramp frame. */
874 #define SIGFRAME_BASE MIPS_REGSIZE
875 /* FIXME! Are these correct?? */
876 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
877 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
878 #define SIGFRAME_FPREGSAVE_OFF \
879 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
881 #ifndef SIGFRAME_REG_SIZE
882 /* FIXME! Is this correct?? */
883 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
885 if (fci
->signal_handler_caller
)
887 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
889 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
890 + ireg
* SIGFRAME_REG_SIZE
;
891 fci
->saved_regs
[ireg
] = reg_position
;
893 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
895 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
896 + ireg
* SIGFRAME_REG_SIZE
;
897 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
899 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
903 proc_desc
= fci
->extra_info
->proc_desc
;
904 if (proc_desc
== NULL
)
905 /* I'm not sure how/whether this can happen. Normally when we can't
906 find a proc_desc, we "synthesize" one using heuristic_proc_desc
907 and set the saved_regs right away. */
910 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
911 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
912 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
914 if (/* In any frame other than the innermost or a frame interrupted by
915 a signal, we assume that all registers have been saved.
916 This assumes that all register saves in a function happen before
917 the first function call. */
918 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
920 /* In a dummy frame we know exactly where things are saved. */
921 && !PROC_DESC_IS_DUMMY (proc_desc
)
923 /* Don't bother unless we are inside a function prologue. Outside the
924 prologue, we know where everything is. */
926 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
928 /* Not sure exactly what kernel_trap means, but if it means
929 the kernel saves the registers without a prologue doing it,
930 we better not examine the prologue to see whether registers
931 have been saved yet. */
934 /* We need to figure out whether the registers that the proc_desc
935 claims are saved have been saved yet. */
939 /* Bitmasks; set if we have found a save for the register. */
940 unsigned long gen_save_found
= 0;
941 unsigned long float_save_found
= 0;
944 /* If the address is odd, assume this is MIPS16 code. */
945 addr
= PROC_LOW_ADDR (proc_desc
);
946 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
948 /* Scan through this function's instructions preceding the current
949 PC, and look for those that save registers. */
950 while (addr
< fci
->pc
)
952 inst
= mips_fetch_instruction (addr
);
953 if (pc_is_mips16 (addr
))
954 mips16_decode_reg_save (inst
, &gen_save_found
);
956 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
959 gen_mask
= gen_save_found
;
960 float_mask
= float_save_found
;
963 /* Fill in the offsets for the registers which gen_mask says
965 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
966 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
967 if (gen_mask
& 0x80000000)
969 fci
->saved_regs
[ireg
] = reg_position
;
970 reg_position
-= MIPS_SAVED_REGSIZE
;
973 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
974 of that normally used by gcc. Therefore, we have to fetch the first
975 instruction of the function, and if it's an entry instruction that
976 saves $s0 or $s1, correct their saved addresses. */
977 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
979 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
980 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
983 int sreg_count
= (inst
>> 6) & 3;
985 /* Check if the ra register was pushed on the stack. */
986 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
988 reg_position
-= MIPS_SAVED_REGSIZE
;
990 /* Check if the s0 and s1 registers were pushed on the stack. */
991 for (reg
= 16; reg
< sreg_count
+16; reg
++)
993 fci
->saved_regs
[reg
] = reg_position
;
994 reg_position
-= MIPS_SAVED_REGSIZE
;
999 /* Fill in the offsets for the registers which float_mask says
1001 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1003 /* The freg_offset points to where the first *double* register
1004 is saved. So skip to the high-order word. */
1005 if (! GDB_TARGET_IS_MIPS64
)
1006 reg_position
+= MIPS_SAVED_REGSIZE
;
1008 /* Fill in the offsets for the float registers which float_mask says
1010 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
1011 if (float_mask
& 0x80000000)
1013 fci
->saved_regs
[FP0_REGNUM
+ireg
] = reg_position
;
1014 reg_position
-= MIPS_SAVED_REGSIZE
;
1017 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1021 read_next_frame_reg(fi
, regno
)
1022 struct frame_info
*fi
;
1025 for (; fi
; fi
= fi
->next
)
1027 /* We have to get the saved sp from the sigcontext
1028 if it is a signal handler frame. */
1029 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1033 if (fi
->saved_regs
== NULL
)
1034 mips_find_saved_regs (fi
);
1035 if (fi
->saved_regs
[regno
])
1036 return read_memory_integer(fi
->saved_regs
[regno
], MIPS_SAVED_REGSIZE
);
1039 return read_register (regno
);
1042 /* mips_addr_bits_remove - remove useless address bits */
1045 mips_addr_bits_remove (addr
)
1048 #if GDB_TARGET_IS_MIPS64
1049 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
)0xffffffff))
1051 /* This hack is a work-around for existing boards using PMON,
1052 the simulator, and any other 64-bit targets that doesn't have
1053 true 64-bit addressing. On these targets, the upper 32 bits
1054 of addresses are ignored by the hardware. Thus, the PC or SP
1055 are likely to have been sign extended to all 1s by instruction
1056 sequences that load 32-bit addresses. For example, a typical
1057 piece of code that loads an address is this:
1058 lui $r2, <upper 16 bits>
1059 ori $r2, <lower 16 bits>
1060 But the lui sign-extends the value such that the upper 32 bits
1061 may be all 1s. The workaround is simply to mask off these bits.
1062 In the future, gcc may be changed to support true 64-bit
1063 addressing, and this masking will have to be disabled. */
1064 addr
&= (CORE_ADDR
)0xffffffff;
1067 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1068 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1069 So we still have to mask off useless bits from addresses. */
1070 addr
&= (CORE_ADDR
)0xffffffff;
1077 mips_init_frame_pc_first (fromleaf
, prev
)
1079 struct frame_info
*prev
;
1083 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1084 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1085 tmp
= mips_skip_stub (pc
);
1086 prev
->pc
= tmp
? tmp
: pc
;
1091 mips_frame_saved_pc(frame
)
1092 struct frame_info
*frame
;
1095 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1096 /* We have to get the saved pc from the sigcontext
1097 if it is a signal handler frame. */
1098 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1099 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
1101 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1102 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1104 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1106 return ADDR_BITS_REMOVE (saved_pc
);
1109 static struct mips_extra_func_info temp_proc_desc
;
1110 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1112 /* Set a register's saved stack address in temp_saved_regs. If an address
1113 has already been set for this register, do nothing; this way we will
1114 only recognize the first save of a given register in a function prologue.
1115 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1118 set_reg_offset (regno
, offset
)
1122 if (temp_saved_regs
[regno
] == 0)
1123 temp_saved_regs
[regno
] = offset
;
1127 /* Test whether the PC points to the return instruction at the
1128 end of a function. */
1131 mips_about_to_return (pc
)
1134 if (pc_is_mips16 (pc
))
1135 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1136 generates a "jr $ra"; other times it generates code to load
1137 the return address from the stack to an accessible register (such
1138 as $a3), then a "jr" using that register. This second case
1139 is almost impossible to distinguish from an indirect jump
1140 used for switch statements, so we don't even try. */
1141 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1143 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1147 /* This fencepost looks highly suspicious to me. Removing it also
1148 seems suspicious as it could affect remote debugging across serial
1152 heuristic_proc_start (pc
)
1160 pc
= ADDR_BITS_REMOVE (pc
);
1162 fence
= start_pc
- heuristic_fence_post
;
1163 if (start_pc
== 0) return 0;
1165 if (heuristic_fence_post
== UINT_MAX
1166 || fence
< VM_MIN_ADDRESS
)
1167 fence
= VM_MIN_ADDRESS
;
1169 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1171 /* search back for previous return */
1172 for (start_pc
-= instlen
; ; start_pc
-= instlen
)
1173 if (start_pc
< fence
)
1175 /* It's not clear to me why we reach this point when
1176 stop_soon_quietly, but with this test, at least we
1177 don't print out warnings for every child forked (eg, on
1178 decstation). 22apr93 rich@cygnus.com. */
1179 if (!stop_soon_quietly
)
1181 static int blurb_printed
= 0;
1183 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1188 /* This actually happens frequently in embedded
1189 development, when you first connect to a board
1190 and your stack pointer and pc are nowhere in
1191 particular. This message needs to give people
1192 in that situation enough information to
1193 determine that it's no big deal. */
1194 printf_filtered ("\n\
1195 GDB is unable to find the start of the function at 0x%s\n\
1196 and thus can't determine the size of that function's stack frame.\n\
1197 This means that GDB may be unable to access that stack frame, or\n\
1198 the frames below it.\n\
1199 This problem is most likely caused by an invalid program counter or\n\
1201 However, if you think GDB should simply search farther back\n\
1202 from 0x%s for code which looks like the beginning of a\n\
1203 function, you can increase the range of the search using the `set\n\
1204 heuristic-fence-post' command.\n",
1205 paddr_nz (pc
), paddr_nz (pc
));
1212 else if (pc_is_mips16 (start_pc
))
1214 unsigned short inst
;
1216 /* On MIPS16, any one of the following is likely to be the
1217 start of a function:
1221 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1222 inst
= mips_fetch_instruction (start_pc
);
1223 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1224 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1225 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1226 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1228 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1229 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1234 else if (mips_about_to_return (start_pc
))
1236 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1241 /* skip nops (usually 1) 0 - is this */
1242 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1243 start_pc
+= MIPS_INSTLEN
;
1248 /* Fetch the immediate value from a MIPS16 instruction.
1249 If the previous instruction was an EXTEND, use it to extend
1250 the upper bits of the immediate value. This is a helper function
1251 for mips16_heuristic_proc_desc. */
1254 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1255 unsigned short prev_inst
; /* previous instruction */
1256 unsigned short inst
; /* current instruction */
1257 int nbits
; /* number of bits in imm field */
1258 int scale
; /* scale factor to be applied to imm */
1259 int is_signed
; /* is the imm field signed? */
1263 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1265 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1266 if (offset
& 0x8000) /* check for negative extend */
1267 offset
= 0 - (0x10000 - (offset
& 0xffff));
1268 return offset
| (inst
& 0x1f);
1272 int max_imm
= 1 << nbits
;
1273 int mask
= max_imm
- 1;
1274 int sign_bit
= max_imm
>> 1;
1276 offset
= inst
& mask
;
1277 if (is_signed
&& (offset
& sign_bit
))
1278 offset
= 0 - (max_imm
- offset
);
1279 return offset
* scale
;
1284 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1285 stream from start_pc to limit_pc. */
1288 mips16_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1289 CORE_ADDR start_pc
, limit_pc
;
1290 struct frame_info
*next_frame
;
1294 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1295 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1296 unsigned inst
= 0; /* current instruction */
1297 unsigned entry_inst
= 0; /* the entry instruction */
1300 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0; /* size of stack frame */
1301 PROC_FRAME_ADJUST(&temp_proc_desc
) = 0; /* offset of FP from SP */
1303 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1305 /* Save the previous instruction. If it's an EXTEND, we'll extract
1306 the immediate offset extension from it in mips16_get_imm. */
1309 /* Fetch and decode the instruction. */
1310 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1311 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1312 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1314 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1315 if (offset
< 0) /* negative stack adjustment? */
1316 PROC_FRAME_OFFSET(&temp_proc_desc
) -= offset
;
1318 /* Exit loop if a positive stack adjustment is found, which
1319 usually means that the stack cleanup code in the function
1320 epilogue is reached. */
1323 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1325 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1326 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1327 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1328 set_reg_offset (reg
, sp
+ offset
);
1330 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1332 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1333 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1334 PROC_REG_MASK(&temp_proc_desc
) |= (1 << reg
);
1335 set_reg_offset (reg
, sp
+ offset
);
1337 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1339 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1340 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1341 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1343 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1345 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1346 PROC_REG_MASK(&temp_proc_desc
) |= (1 << RA_REGNUM
);
1347 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1349 else if (inst
== 0x673d) /* move $s1, $sp */
1352 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1354 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1356 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1357 frame_addr
= sp
+ offset
;
1358 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1359 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1361 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1363 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1364 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1365 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1366 set_reg_offset (reg
, frame_addr
+ offset
);
1368 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1370 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1371 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1372 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1373 set_reg_offset (reg
, frame_addr
+ offset
);
1375 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1376 entry_inst
= inst
; /* save for later processing */
1377 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1378 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1381 /* The entry instruction is typically the first instruction in a function,
1382 and it stores registers at offsets relative to the value of the old SP
1383 (before the prologue). But the value of the sp parameter to this
1384 function is the new SP (after the prologue has been executed). So we
1385 can't calculate those offsets until we've seen the entire prologue,
1386 and can calculate what the old SP must have been. */
1387 if (entry_inst
!= 0)
1389 int areg_count
= (entry_inst
>> 8) & 7;
1390 int sreg_count
= (entry_inst
>> 6) & 3;
1392 /* The entry instruction always subtracts 32 from the SP. */
1393 PROC_FRAME_OFFSET(&temp_proc_desc
) += 32;
1395 /* Now we can calculate what the SP must have been at the
1396 start of the function prologue. */
1397 sp
+= PROC_FRAME_OFFSET(&temp_proc_desc
);
1399 /* Check if a0-a3 were saved in the caller's argument save area. */
1400 for (reg
= 4, offset
= 0; reg
< areg_count
+4; reg
++)
1402 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1403 set_reg_offset (reg
, sp
+ offset
);
1404 offset
+= MIPS_SAVED_REGSIZE
;
1407 /* Check if the ra register was pushed on the stack. */
1409 if (entry_inst
& 0x20)
1411 PROC_REG_MASK(&temp_proc_desc
) |= 1 << RA_REGNUM
;
1412 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1413 offset
-= MIPS_SAVED_REGSIZE
;
1416 /* Check if the s0 and s1 registers were pushed on the stack. */
1417 for (reg
= 16; reg
< sreg_count
+16; reg
++)
1419 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1420 set_reg_offset (reg
, sp
+ offset
);
1421 offset
-= MIPS_SAVED_REGSIZE
;
1427 mips32_heuristic_proc_desc(start_pc
, limit_pc
, next_frame
, sp
)
1428 CORE_ADDR start_pc
, limit_pc
;
1429 struct frame_info
*next_frame
;
1433 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1435 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1436 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
1437 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1438 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1440 unsigned long inst
, high_word
, low_word
;
1443 /* Fetch the instruction. */
1444 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1446 /* Save some code by pre-extracting some useful fields. */
1447 high_word
= (inst
>> 16) & 0xffff;
1448 low_word
= inst
& 0xffff;
1449 reg
= high_word
& 0x1f;
1451 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1452 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1453 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1455 if (low_word
& 0x8000) /* negative stack adjustment? */
1456 PROC_FRAME_OFFSET(&temp_proc_desc
) += 0x10000 - low_word
;
1458 /* Exit loop if a positive stack adjustment is found, which
1459 usually means that the stack cleanup code in the function
1460 epilogue is reached. */
1463 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1465 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1466 set_reg_offset (reg
, sp
+ low_word
);
1468 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1470 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1471 but the register size used is only 32 bits. Make the address
1472 for the saved register point to the lower 32 bits. */
1473 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1474 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1476 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1478 /* Old gcc frame, r30 is virtual frame pointer. */
1479 if ((long)low_word
!= PROC_FRAME_OFFSET(&temp_proc_desc
))
1480 frame_addr
= sp
+ low_word
;
1481 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1483 unsigned alloca_adjust
;
1484 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1485 frame_addr
= read_next_frame_reg(next_frame
, 30);
1486 alloca_adjust
= (unsigned)(frame_addr
- (sp
+ low_word
));
1487 if (alloca_adjust
> 0)
1489 /* FP > SP + frame_size. This may be because
1490 * of an alloca or somethings similar.
1491 * Fix sp to "pre-alloca" value, and try again.
1493 sp
+= alloca_adjust
;
1498 /* move $30,$sp. With different versions of gas this will be either
1499 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1500 Accept any one of these. */
1501 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1503 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1504 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1506 unsigned alloca_adjust
;
1507 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1508 frame_addr
= read_next_frame_reg(next_frame
, 30);
1509 alloca_adjust
= (unsigned)(frame_addr
- sp
);
1510 if (alloca_adjust
> 0)
1512 /* FP > SP + frame_size. This may be because
1513 * of an alloca or somethings similar.
1514 * Fix sp to "pre-alloca" value, and try again.
1516 sp
+= alloca_adjust
;
1521 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1523 PROC_REG_MASK(&temp_proc_desc
) |= 1 << reg
;
1524 set_reg_offset (reg
, frame_addr
+ low_word
);
1529 static mips_extra_func_info_t
1530 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
1531 CORE_ADDR start_pc
, limit_pc
;
1532 struct frame_info
*next_frame
;
1534 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1536 if (start_pc
== 0) return NULL
;
1537 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
1538 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1539 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1540 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1541 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1543 if (start_pc
+ 200 < limit_pc
)
1544 limit_pc
= start_pc
+ 200;
1545 if (pc_is_mips16 (start_pc
))
1546 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1548 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1549 return &temp_proc_desc
;
1552 static mips_extra_func_info_t
1553 non_heuristic_proc_desc (pc
, addrptr
)
1557 CORE_ADDR startaddr
;
1558 mips_extra_func_info_t proc_desc
;
1559 struct block
*b
= block_for_pc(pc
);
1562 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1564 *addrptr
= startaddr
;
1565 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1569 if (startaddr
> BLOCK_START (b
))
1570 /* This is the "pathological" case referred to in a comment in
1571 print_frame_info. It might be better to move this check into
1575 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1578 /* If we never found a PDR for this function in symbol reading, then
1579 examine prologues to find the information. */
1582 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1583 if (PROC_FRAME_REG (proc_desc
) == -1)
1593 static mips_extra_func_info_t
1594 find_proc_desc (pc
, next_frame
)
1596 struct frame_info
*next_frame
;
1598 mips_extra_func_info_t proc_desc
;
1599 CORE_ADDR startaddr
;
1601 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1605 /* IF this is the topmost frame AND
1606 * (this proc does not have debugging information OR
1607 * the PC is in the procedure prologue)
1608 * THEN create a "heuristic" proc_desc (by analyzing
1609 * the actual code) to replace the "official" proc_desc.
1611 if (next_frame
== NULL
)
1613 struct symtab_and_line val
;
1614 struct symbol
*proc_symbol
=
1615 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
1619 val
= find_pc_line (BLOCK_START
1620 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
1622 val
.pc
= val
.end
? val
.end
: pc
;
1624 if (!proc_symbol
|| pc
< val
.pc
)
1626 mips_extra_func_info_t found_heuristic
=
1627 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1629 if (found_heuristic
)
1630 proc_desc
= found_heuristic
;
1636 /* Is linked_proc_desc_table really necessary? It only seems to be used
1637 by procedure call dummys. However, the procedures being called ought
1638 to have their own proc_descs, and even if they don't,
1639 heuristic_proc_desc knows how to create them! */
1641 register struct linked_proc_info
*link
;
1643 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1644 if (PROC_LOW_ADDR(&link
->info
) <= pc
1645 && PROC_HIGH_ADDR(&link
->info
) > pc
)
1649 startaddr
= heuristic_proc_start (pc
);
1652 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1658 get_frame_pointer(frame
, proc_desc
)
1659 struct frame_info
*frame
;
1660 mips_extra_func_info_t proc_desc
;
1662 return ADDR_BITS_REMOVE (
1663 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1664 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1667 mips_extra_func_info_t cached_proc_desc
;
1670 mips_frame_chain(frame
)
1671 struct frame_info
*frame
;
1673 mips_extra_func_info_t proc_desc
;
1675 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
1677 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1680 /* Check if the PC is inside a call stub. If it is, fetch the
1681 PC of the caller of that stub. */
1682 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1685 /* Look up the procedure descriptor for this PC. */
1686 proc_desc
= find_proc_desc(saved_pc
, frame
);
1690 cached_proc_desc
= proc_desc
;
1692 /* If no frame pointer and frame size is zero, we must be at end
1693 of stack (or otherwise hosed). If we don't check frame size,
1694 we loop forever if we see a zero size frame. */
1695 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1696 && PROC_FRAME_OFFSET (proc_desc
) == 0
1697 /* The previous frame from a sigtramp frame might be frameless
1698 and have frame size zero. */
1699 && !frame
->signal_handler_caller
)
1702 return get_frame_pointer (frame
, proc_desc
);
1706 mips_init_extra_frame_info(fromleaf
, fci
)
1708 struct frame_info
*fci
;
1712 /* Use proc_desc calculated in frame_chain */
1713 mips_extra_func_info_t proc_desc
=
1714 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
1716 fci
->extra_info
= (struct frame_extra_info
*)
1717 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1719 fci
->saved_regs
= NULL
;
1720 fci
->extra_info
->proc_desc
=
1721 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1724 /* Fixup frame-pointer - only needed for top frame */
1725 /* This may not be quite right, if proc has a real frame register.
1726 Get the value of the frame relative sp, procedure might have been
1727 interrupted by a signal at it's very start. */
1728 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1729 && !PROC_DESC_IS_DUMMY (proc_desc
))
1730 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1732 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1734 if (proc_desc
== &temp_proc_desc
)
1738 /* Do not set the saved registers for a sigtramp frame,
1739 mips_find_saved_registers will do that for us.
1740 We can't use fci->signal_handler_caller, it is not yet set. */
1741 find_pc_partial_function (fci
->pc
, &name
,
1742 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
1743 if (!IN_SIGTRAMP (fci
->pc
, name
))
1745 frame_saved_regs_zalloc (fci
);
1746 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
1747 fci
->saved_regs
[PC_REGNUM
]
1748 = fci
->saved_regs
[RA_REGNUM
];
1752 /* hack: if argument regs are saved, guess these contain args */
1753 /* assume we can't tell how many args for now */
1754 fci
->extra_info
->num_args
= -1;
1755 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1757 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1759 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
1766 /* MIPS stack frames are almost impenetrable. When execution stops,
1767 we basically have to look at symbol information for the function
1768 that we stopped in, which tells us *which* register (if any) is
1769 the base of the frame pointer, and what offset from that register
1770 the frame itself is at.
1772 This presents a problem when trying to examine a stack in memory
1773 (that isn't executing at the moment), using the "frame" command. We
1774 don't have a PC, nor do we have any registers except SP.
1776 This routine takes two arguments, SP and PC, and tries to make the
1777 cached frames look as if these two arguments defined a frame on the
1778 cache. This allows the rest of info frame to extract the important
1779 arguments without difficulty. */
1782 setup_arbitrary_frame (argc
, argv
)
1787 error ("MIPS frame specifications require two arguments: sp and pc");
1789 return create_new_frame (argv
[0], argv
[1]);
1793 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1795 * For n32 ABI, eight.
1796 * For all others, he same as the size of a general register.
1798 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1799 #define MIPS_NABI32 1
1800 #define STACK_ARGSIZE 8
1802 #define MIPS_NABI32 0
1803 #define STACK_ARGSIZE MIPS_SAVED_REGSIZE
1807 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
1812 CORE_ADDR struct_addr
;
1818 int stack_offset
= 0;
1820 /* Macros to round N up or down to the next A boundary; A must be
1822 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1823 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1825 /* First ensure that the stack and structure return address (if any)
1826 are properly aligned. The stack has to be at least 64-bit aligned
1827 even on 32-bit machines, because doubles must be 64-bit aligned.
1828 On at least one MIPS variant, stack frames need to be 128-bit
1829 aligned, so we round to this widest known alignment. */
1830 sp
= ROUND_DOWN (sp
, 16);
1831 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
1833 /* Now make space on the stack for the args. We allocate more
1834 than necessary for EABI, because the first few arguments are
1835 passed in registers, but that's OK. */
1836 for (argnum
= 0; argnum
< nargs
; argnum
++)
1837 len
+= ROUND_UP (TYPE_LENGTH(VALUE_TYPE(args
[argnum
])), MIPS_SAVED_REGSIZE
);
1838 sp
-= ROUND_UP (len
, 16);
1840 /* Initialize the integer and float register pointers. */
1842 float_argreg
= FPA0_REGNUM
;
1844 /* the struct_return pointer occupies the first parameter-passing reg */
1846 write_register (argreg
++, struct_addr
);
1848 /* Now load as many as possible of the first arguments into
1849 registers, and push the rest onto the stack. Loop thru args
1850 from first to last. */
1851 for (argnum
= 0; argnum
< nargs
; argnum
++)
1854 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1855 value_ptr arg
= args
[argnum
];
1856 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1857 int len
= TYPE_LENGTH (arg_type
);
1858 enum type_code typecode
= TYPE_CODE (arg_type
);
1860 /* The EABI passes structures that do not fit in a register by
1861 reference. In all other cases, pass the structure by value. */
1862 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
1863 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1865 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
1866 typecode
= TYPE_CODE_PTR
;
1867 len
= MIPS_SAVED_REGSIZE
;
1871 val
= (char *)VALUE_CONTENTS (arg
);
1873 /* 32-bit ABIs always start floating point arguments in an
1874 even-numbered floating point register. */
1875 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1876 && (float_argreg
& 1))
1879 /* Floating point arguments passed in registers have to be
1880 treated specially. On 32-bit architectures, doubles
1881 are passed in register pairs; the even register gets
1882 the low word, and the odd register gets the high word.
1883 On non-EABI processors, the first two floating point arguments are
1884 also copied to general registers, because MIPS16 functions
1885 don't use float registers for arguments. This duplication of
1886 arguments in general registers can't hurt non-MIPS16 functions
1887 because those registers are normally skipped. */
1888 if (typecode
== TYPE_CODE_FLT
1889 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
1890 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
1892 if (!FP_REGISTER_DOUBLE
&& len
== 8)
1894 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
1895 unsigned long regval
;
1897 /* Write the low word of the double to the even register(s). */
1898 regval
= extract_unsigned_integer (val
+low_offset
, 4);
1899 write_register (float_argreg
++, regval
);
1901 write_register (argreg
+1, regval
);
1903 /* Write the high word of the double to the odd register(s). */
1904 regval
= extract_unsigned_integer (val
+4-low_offset
, 4);
1905 write_register (float_argreg
++, regval
);
1908 write_register (argreg
, regval
);
1915 /* This is a floating point value that fits entirely
1916 in a single register. */
1917 CORE_ADDR regval
= extract_address (val
, len
);
1918 write_register (float_argreg
++, regval
);
1921 write_register (argreg
, regval
);
1922 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
1928 /* Copy the argument to general registers or the stack in
1929 register-sized pieces. Large arguments are split between
1930 registers and stack. */
1931 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
1932 are treated specially: Irix cc passes them in registers
1933 where gcc sometimes puts them on the stack. For maximum
1934 compatibility, we will put them in both places. */
1936 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
1937 (len
% MIPS_SAVED_REGSIZE
!= 0));
1940 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
1942 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
1944 /* Write this portion of the argument to the stack. */
1945 /* Should shorter than int integer values be
1946 promoted to int before being stored? */
1948 int longword_offset
= 0;
1949 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1951 if (STACK_ARGSIZE
== 8 &&
1952 (typecode
== TYPE_CODE_INT
||
1953 typecode
== TYPE_CODE_PTR
||
1954 typecode
== TYPE_CODE_FLT
) && len
<= 4)
1955 longword_offset
= STACK_ARGSIZE
- len
;
1956 else if ((typecode
== TYPE_CODE_STRUCT
||
1957 typecode
== TYPE_CODE_UNION
) &&
1958 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
1959 longword_offset
= STACK_ARGSIZE
- len
;
1962 write_memory (sp
+ stack_offset
+ longword_offset
,
1966 /* Note!!! This is NOT an else clause.
1967 Odd sized structs may go thru BOTH paths. */
1968 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
1970 CORE_ADDR regval
= extract_address (val
, partial_len
);
1972 /* A non-floating-point argument being passed in a
1973 general register. If a struct or union, and if
1974 the remaining length is smaller than the register
1975 size, we have to adjust the register value on
1978 It does not seem to be necessary to do the
1979 same for integral types.
1981 Also don't do this adjustment on EABI and O64
1985 && MIPS_SAVED_REGSIZE
< 8
1986 && TARGET_BYTE_ORDER
== BIG_ENDIAN
1987 && partial_len
< MIPS_SAVED_REGSIZE
1988 && (typecode
== TYPE_CODE_STRUCT
||
1989 typecode
== TYPE_CODE_UNION
))
1990 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
1993 write_register (argreg
, regval
);
1996 /* If this is the old ABI, prevent subsequent floating
1997 point arguments from being passed in floating point
2000 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2006 /* The offset onto the stack at which we will start
2007 copying parameters (after the registers are used up)
2008 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2009 leaves room for the "home" area for register parameters.
2011 In the new EABI (and the NABI32), the 8 register parameters
2012 do not have "home" stack space reserved for them, so the
2013 stack offset does not get incremented until after
2014 we have used up the 8 parameter registers. */
2016 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
2018 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
2023 /* Return adjusted stack pointer. */
2028 mips_push_return_address (pc
, sp
)
2032 /* Set the return address register to point to the entry
2033 point of the program, where a breakpoint lies in wait. */
2034 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS());
2039 mips_push_register (CORE_ADDR
*sp
, int regno
)
2041 char buffer
[MAX_REGISTER_RAW_SIZE
];
2044 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2046 regsize
= MIPS_SAVED_REGSIZE
;
2047 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2048 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2053 regsize
= REGISTER_RAW_SIZE (regno
);
2057 read_register_gen (regno
, buffer
);
2058 write_memory (*sp
, buffer
+ offset
, regsize
);
2061 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2062 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2065 mips_push_dummy_frame ()
2068 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2069 xmalloc(sizeof(struct linked_proc_info
));
2070 mips_extra_func_info_t proc_desc
= &link
->info
;
2071 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2072 CORE_ADDR old_sp
= sp
;
2073 link
->next
= linked_proc_desc_table
;
2074 linked_proc_desc_table
= link
;
2076 /* FIXME! are these correct ? */
2077 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2078 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2079 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2080 #define FLOAT_SINGLE_REG_SAVE_MASK \
2081 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2083 * The registers we must save are all those not preserved across
2084 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2085 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2086 * and FP Control/Status registers.
2089 * Dummy frame layout:
2092 * Saved MMHI, MMLO, FPC_CSR
2097 * Saved D18 (i.e. F19, F18)
2099 * Saved D0 (i.e. F1, F0)
2100 * Argument build area and stack arguments written via mips_push_arguments
2104 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2105 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
2106 PROC_FRAME_OFFSET(proc_desc
) = 0;
2107 PROC_FRAME_ADJUST(proc_desc
) = 0;
2108 mips_push_register (&sp
, PC_REGNUM
);
2109 mips_push_register (&sp
, HI_REGNUM
);
2110 mips_push_register (&sp
, LO_REGNUM
);
2111 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2113 /* Save general CPU registers */
2114 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
2115 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2116 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2117 for (ireg
= 32; --ireg
>= 0; )
2118 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
2119 mips_push_register (&sp
, ireg
);
2121 /* Save floating point registers starting with high order word */
2122 PROC_FREG_MASK(proc_desc
) =
2123 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2124 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2125 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2127 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
- 8;
2128 for (ireg
= 32; --ireg
>= 0; )
2129 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
2130 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2132 /* Update the frame pointer for the call dummy and the stack pointer.
2133 Set the procedure's starting and ending addresses to point to the
2134 call dummy address at the entry point. */
2135 write_register (PUSH_FP_REGNUM
, old_sp
);
2136 write_register (SP_REGNUM
, sp
);
2137 PROC_LOW_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS();
2138 PROC_HIGH_ADDR(proc_desc
) = CALL_DUMMY_ADDRESS() + 4;
2139 SET_PROC_DESC_IS_DUMMY(proc_desc
);
2140 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
2146 register int regnum
;
2147 struct frame_info
*frame
= get_current_frame ();
2148 CORE_ADDR new_sp
= FRAME_FP (frame
);
2150 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2152 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
2153 if (frame
->saved_regs
== NULL
)
2154 mips_find_saved_regs (frame
);
2155 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2157 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2158 && frame
->saved_regs
[regnum
])
2159 write_register (regnum
,
2160 read_memory_integer (frame
->saved_regs
[regnum
],
2161 MIPS_SAVED_REGSIZE
));
2163 write_register (SP_REGNUM
, new_sp
);
2164 flush_cached_frames ();
2166 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
2168 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2170 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2172 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2174 if (&pi_ptr
->info
== proc_desc
)
2179 error ("Can't locate dummy extra frame info\n");
2181 if (prev_ptr
!= NULL
)
2182 prev_ptr
->next
= pi_ptr
->next
;
2184 linked_proc_desc_table
= pi_ptr
->next
;
2188 write_register (HI_REGNUM
,
2189 read_memory_integer (new_sp
- 2*MIPS_SAVED_REGSIZE
,
2190 MIPS_SAVED_REGSIZE
));
2191 write_register (LO_REGNUM
,
2192 read_memory_integer (new_sp
- 3*MIPS_SAVED_REGSIZE
,
2193 MIPS_SAVED_REGSIZE
));
2194 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2195 write_register (FCRCS_REGNUM
,
2196 read_memory_integer (new_sp
- 4*MIPS_SAVED_REGSIZE
,
2197 MIPS_SAVED_REGSIZE
));
2202 mips_print_register (regnum
, all
)
2205 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2207 /* Get the data in raw format. */
2208 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2210 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2214 /* If an even floating point register, also print as double. */
2215 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2216 && !((regnum
-FP0_REGNUM
) & 1))
2217 if (REGISTER_RAW_SIZE(regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2219 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2221 read_relative_register_raw_bytes (regnum
, dbuffer
);
2222 read_relative_register_raw_bytes (regnum
+1, dbuffer
+MIPS_REGSIZE
);
2223 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2225 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
2226 val_print (builtin_type_double
, dbuffer
, 0, 0,
2227 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2228 printf_filtered ("); ");
2230 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2232 /* The problem with printing numeric register names (r26, etc.) is that
2233 the user can't use them on input. Probably the best solution is to
2234 fix it so that either the numeric or the funky (a2, etc.) names
2235 are accepted on input. */
2236 if (regnum
< MIPS_NUMREGS
)
2237 printf_filtered ("(r%d): ", regnum
);
2239 printf_filtered (": ");
2241 /* If virtual format is floating, print it that way. */
2242 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2243 if (FP_REGISTER_DOUBLE
)
2244 { /* show 8-byte floats as float AND double: */
2245 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2247 printf_filtered (" (float) ");
2248 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2249 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2250 printf_filtered (", (double) ");
2251 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2252 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2255 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2256 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2257 /* Else print as integer in hex. */
2259 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2260 'x', 0, gdb_stdout
);
2263 /* Replacement for generic do_registers_info.
2264 Print regs in pretty columns. */
2267 do_fp_register_row (regnum
)
2269 { /* do values for FP (float) regs */
2270 char *raw_buffer
[2];
2272 /* use HI and LO to control the order of combining two flt regs */
2273 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2274 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2275 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2276 int inv1
, inv2
, inv3
;
2278 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2279 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2280 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2282 /* Get the data in raw format. */
2283 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2284 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2285 if (REGISTER_RAW_SIZE(regnum
) == 4)
2287 /* 4-byte registers: we can fit two registers per row. */
2288 /* Also print every pair of 4-byte regs as an 8-byte double. */
2289 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2290 error ("can't read register %d (%s)",
2291 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2293 /* copy the two floats into one double, and unpack both */
2294 memcpy (dbl_buffer
, raw_buffer
, sizeof(dbl_buffer
));
2295 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2296 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2297 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2299 printf_filtered (inv1
? " %-5s: <invalid float>" :
2300 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2301 printf_filtered (inv2
? " %-5s: <invalid float>" :
2302 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2303 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2304 " dbl: %-24.17g\n", doub
);
2305 /* may want to do hex display here (future enhancement) */
2309 { /* eight byte registers: print each one as float AND as double. */
2310 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2312 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof(dbl_buffer
));
2313 flt1
= unpack_double (builtin_type_float
,
2314 &raw_buffer
[HI
][offset
], &inv1
);
2315 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2317 printf_filtered (inv1
? " %-5s: <invalid float>" :
2318 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2319 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2320 " dbl: %-24.17g\n", doub
);
2321 /* may want to do hex display here (future enhancement) */
2327 /* Print a row's worth of GP (int) registers, with name labels above */
2330 do_gp_register_row (regnum
)
2333 /* do values for GP (int) regs */
2334 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2335 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2337 int start_regnum
= regnum
;
2338 int numregs
= NUM_REGS
;
2341 /* For GP registers, we print a separate row of names above the vals */
2342 printf_filtered (" ");
2343 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2345 if (*REGISTER_NAME (regnum
) == '\0')
2346 continue; /* unused register */
2347 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2348 break; /* end the row: reached FP register */
2349 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2350 REGISTER_NAME (regnum
));
2353 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2354 start_regnum
); /* print the R0 to R31 names */
2356 regnum
= start_regnum
; /* go back to start of row */
2357 /* now print the values in hex, 4 or 8 to the row */
2358 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2360 if (*REGISTER_NAME (regnum
) == '\0')
2361 continue; /* unused register */
2362 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2363 break; /* end row: reached FP register */
2364 /* OK: get the data in raw format. */
2365 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2366 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2367 /* pad small registers */
2368 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_RAW_SIZE (regnum
)); byte
++)
2369 printf_filtered (" ");
2370 /* Now print the register value in hex, endian order. */
2371 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2372 for (byte
= 0; byte
< REGISTER_RAW_SIZE (regnum
); byte
++)
2373 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2375 for (byte
= REGISTER_RAW_SIZE (regnum
) - 1; byte
>= 0; byte
--)
2376 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2377 printf_filtered (" ");
2380 if (col
> 0) /* ie. if we actually printed anything... */
2381 printf_filtered ("\n");
2386 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2389 mips_do_registers_info (regnum
, fpregs
)
2393 if (regnum
!= -1) /* do one specified register */
2395 if (*(REGISTER_NAME (regnum
)) == '\0')
2396 error ("Not a valid register for the current processor type");
2398 mips_print_register (regnum
, 0);
2399 printf_filtered ("\n");
2401 else /* do all (or most) registers */
2404 while (regnum
< NUM_REGS
)
2406 if (TYPE_CODE(REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2407 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2408 regnum
= do_fp_register_row (regnum
); /* FP regs */
2410 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2412 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2417 /* Return number of args passed to a frame. described by FIP.
2418 Can return -1, meaning no way to tell. */
2421 mips_frame_num_args (frame
)
2422 struct frame_info
*frame
;
2424 #if 0 /* FIXME Use or lose this! */
2425 struct chain_info_t
*p
;
2427 p
= mips_find_cached_frame (FRAME_FP (frame
));
2429 return p
->the_info
.numargs
;
2434 /* Is this a branch with a delay slot? */
2436 static int is_delayed
PARAMS ((unsigned long));
2443 for (i
= 0; i
< NUMOPCODES
; ++i
)
2444 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2445 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2447 return (i
< NUMOPCODES
2448 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2449 | INSN_COND_BRANCH_DELAY
2450 | INSN_COND_BRANCH_LIKELY
)));
2454 mips_step_skips_delay (pc
)
2457 char buf
[MIPS_INSTLEN
];
2459 /* There is no branch delay slot on MIPS16. */
2460 if (pc_is_mips16 (pc
))
2463 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2464 /* If error reading memory, guess that it is not a delayed branch. */
2466 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2470 /* Skip the PC past function prologue instructions (32-bit version).
2471 This is a helper function for mips_skip_prologue. */
2474 mips32_skip_prologue (pc
, lenient
)
2475 CORE_ADDR pc
; /* starting PC to search from */
2480 int seen_sp_adjust
= 0;
2481 int load_immediate_bytes
= 0;
2483 /* Skip the typical prologue instructions. These are the stack adjustment
2484 instruction and the instructions that save registers on the stack
2485 or in the gcc frame. */
2486 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2488 unsigned long high_word
;
2490 inst
= mips_fetch_instruction (pc
);
2491 high_word
= (inst
>> 16) & 0xffff;
2494 if (lenient
&& is_delayed (inst
))
2498 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2499 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2501 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2502 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2504 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2505 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2506 && (inst
& 0x001F0000)) /* reg != $zero */
2509 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2511 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2513 continue; /* reg != $zero */
2515 /* move $s8,$sp. With different versions of gas this will be either
2516 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2517 Accept any one of these. */
2518 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2521 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2523 else if (high_word
== 0x3c1c) /* lui $gp,n */
2525 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2527 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2528 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2530 /* The following instructions load $at or $t0 with an immediate
2531 value in preparation for a stack adjustment via
2532 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2533 a local variable, so we accept them only before a stack adjustment
2534 instruction was seen. */
2535 else if (!seen_sp_adjust
)
2537 if (high_word
== 0x3c01 || /* lui $at,n */
2538 high_word
== 0x3c08) /* lui $t0,n */
2540 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2543 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2544 high_word
== 0x3508 || /* ori $t0,$t0,n */
2545 high_word
== 0x3401 || /* ori $at,$zero,n */
2546 high_word
== 0x3408) /* ori $t0,$zero,n */
2548 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2558 /* In a frameless function, we might have incorrectly
2559 skipped some load immediate instructions. Undo the skipping
2560 if the load immediate was not followed by a stack adjustment. */
2561 if (load_immediate_bytes
&& !seen_sp_adjust
)
2562 pc
-= load_immediate_bytes
;
2566 /* Skip the PC past function prologue instructions (16-bit version).
2567 This is a helper function for mips_skip_prologue. */
2570 mips16_skip_prologue (pc
, lenient
)
2571 CORE_ADDR pc
; /* starting PC to search from */
2575 int extend_bytes
= 0;
2576 int prev_extend_bytes
;
2578 /* Table of instructions likely to be found in a function prologue. */
2581 unsigned short inst
;
2582 unsigned short mask
;
2585 { 0x6300, 0xff00 }, /* addiu $sp,offset */
2586 { 0xfb00, 0xff00 }, /* daddiu $sp,offset */
2587 { 0xd000, 0xf800 }, /* sw reg,n($sp) */
2588 { 0xf900, 0xff00 }, /* sd reg,n($sp) */
2589 { 0x6200, 0xff00 }, /* sw $ra,n($sp) */
2590 { 0xfa00, 0xff00 }, /* sd $ra,n($sp) */
2591 { 0x673d, 0xffff }, /* move $s1,sp */
2592 { 0xd980, 0xff80 }, /* sw $a0-$a3,n($s1) */
2593 { 0x6704, 0xff1c }, /* move reg,$a0-$a3 */
2594 { 0xe809, 0xf81f }, /* entry pseudo-op */
2595 { 0x0100, 0xff00 }, /* addiu $s1,$sp,n */
2596 { 0, 0 } /* end of table marker */
2599 /* Skip the typical prologue instructions. These are the stack adjustment
2600 instruction and the instructions that save registers on the stack
2601 or in the gcc frame. */
2602 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2604 unsigned short inst
;
2607 inst
= mips_fetch_instruction (pc
);
2609 /* Normally we ignore an extend instruction. However, if it is
2610 not followed by a valid prologue instruction, we must adjust
2611 the pc back over the extend so that it won't be considered
2612 part of the prologue. */
2613 if ((inst
& 0xf800) == 0xf000) /* extend */
2615 extend_bytes
= MIPS16_INSTLEN
;
2618 prev_extend_bytes
= extend_bytes
;
2621 /* Check for other valid prologue instructions besides extend. */
2622 for (i
= 0; table
[i
].mask
!= 0; i
++)
2623 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2625 if (table
[i
].mask
!= 0) /* it was in table? */
2626 continue; /* ignore it */
2627 else /* non-prologue */
2629 /* Return the current pc, adjusted backwards by 2 if
2630 the previous instruction was an extend. */
2631 return pc
- prev_extend_bytes
;
2637 /* To skip prologues, I use this predicate. Returns either PC itself
2638 if the code at PC does not look like a function prologue; otherwise
2639 returns an address that (if we're lucky) follows the prologue. If
2640 LENIENT, then we must skip everything which is involved in setting
2641 up the frame (it's OK to skip more, just so long as we don't skip
2642 anything which might clobber the registers which are being saved.
2643 We must skip more in the case where part of the prologue is in the
2644 delay slot of a non-prologue instruction). */
2647 mips_skip_prologue (pc
, lenient
)
2651 /* See if we can determine the end of the prologue via the symbol table.
2652 If so, then return either PC, or the PC after the prologue, whichever
2655 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2657 if (post_prologue_pc
!= 0)
2658 return max (pc
, post_prologue_pc
);
2660 /* Can't determine prologue from the symbol table, need to examine
2663 if (pc_is_mips16 (pc
))
2664 return mips16_skip_prologue (pc
, lenient
);
2666 return mips32_skip_prologue (pc
, lenient
);
2670 /* The lenient prologue stuff should be superseded by the code in
2671 init_extra_frame_info which looks to see whether the stores mentioned
2672 in the proc_desc have actually taken place. */
2674 /* Is address PC in the prologue (loosely defined) for function at
2678 mips_in_lenient_prologue (startaddr
, pc
)
2679 CORE_ADDR startaddr
;
2682 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2683 return pc
>= startaddr
&& pc
< end_prologue
;
2687 /* Determine how a return value is stored within the MIPS register
2688 file, given the return type `valtype'. */
2690 struct return_value_word
2698 static void return_value_location
PARAMS ((struct type
*, struct return_value_word
*, struct return_value_word
*));
2701 return_value_location (valtype
, hi
, lo
)
2702 struct type
*valtype
;
2703 struct return_value_word
*hi
;
2704 struct return_value_word
*lo
;
2706 int len
= TYPE_LENGTH (valtype
);
2708 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2709 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2710 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2712 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2714 /* We need to break a 64bit float in two 32 bit halves and
2715 spread them across a floating-point register pair. */
2716 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2717 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
2718 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2719 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
2721 hi
->reg_offset
= lo
->reg_offset
;
2722 lo
->reg
= FP0_REGNUM
+ 0;
2723 hi
->reg
= FP0_REGNUM
+ 1;
2729 /* The floating point value fits in a single floating-point
2731 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2732 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
2735 lo
->reg
= FP0_REGNUM
;
2746 /* Locate a result possibly spread across two registers. */
2748 lo
->reg
= regnum
+ 0;
2749 hi
->reg
= regnum
+ 1;
2750 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2751 && len
< MIPS_SAVED_REGSIZE
)
2753 /* "un-left-justify" the value in the low register */
2754 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
2759 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2760 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
2761 && len
< MIPS_SAVED_REGSIZE
* 2
2762 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2763 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2765 /* "un-left-justify" the value spread across two registers. */
2766 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
2767 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
2769 hi
->len
= len
- lo
->len
;
2773 /* Only perform a partial copy of the second register. */
2776 if (len
> MIPS_SAVED_REGSIZE
)
2778 lo
->len
= MIPS_SAVED_REGSIZE
;
2779 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
2787 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2788 && REGISTER_RAW_SIZE (regnum
) == 8
2789 && MIPS_SAVED_REGSIZE
== 4)
2791 /* Account for the fact that only the least-signficant part
2792 of the register is being used */
2793 lo
->reg_offset
+= 4;
2794 hi
->reg_offset
+= 4;
2797 hi
->buf_offset
= lo
->len
;
2801 /* Given a return value in `regbuf' with a type `valtype', extract and
2802 copy its value into `valbuf'. */
2805 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2806 struct type
*valtype
;
2807 char regbuf
[REGISTER_BYTES
];
2810 struct return_value_word lo
;
2811 struct return_value_word hi
;
2812 return_value_location (valtype
, &lo
, &hi
);
2814 memcpy (valbuf
+ lo
.buf_offset
,
2815 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
2819 memcpy (valbuf
+ hi
.buf_offset
,
2820 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
2826 int len
= TYPE_LENGTH (valtype
);
2829 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2830 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2831 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2832 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2833 regnum
= FP0_REGNUM
;
2835 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2836 { /* "un-left-justify" the value from the register */
2837 if (len
< REGISTER_RAW_SIZE (regnum
))
2838 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2839 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2840 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2841 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2842 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2843 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2845 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
2846 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
2850 /* Given a return value in `valbuf' with a type `valtype', write it's
2851 value into the appropriate register. */
2854 mips_store_return_value (valtype
, valbuf
)
2855 struct type
*valtype
;
2858 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2859 struct return_value_word lo
;
2860 struct return_value_word hi
;
2861 return_value_location (valtype
, &lo
, &hi
);
2863 memset (raw_buffer
, 0, sizeof (raw_buffer
));
2864 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
2865 write_register_bytes (REGISTER_BYTE (lo
.reg
),
2867 REGISTER_RAW_SIZE (lo
.reg
));
2871 memset (raw_buffer
, 0, sizeof (raw_buffer
));
2872 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
2873 write_register_bytes (REGISTER_BYTE (hi
.reg
),
2875 REGISTER_RAW_SIZE (hi
.reg
));
2881 int len
= TYPE_LENGTH (valtype
);
2882 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2885 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2886 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2887 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2888 && len
<= MIPS_REGSIZE
)))
2889 regnum
= FP0_REGNUM
;
2891 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2892 { /* "left-justify" the value in the register */
2893 if (len
< REGISTER_RAW_SIZE (regnum
))
2894 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
2895 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
2896 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
2897 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2898 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2899 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
2901 memcpy(raw_buffer
+ offset
, valbuf
, len
);
2902 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
2903 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
,
2904 len
> REGISTER_RAW_SIZE (regnum
) ?
2905 len
: REGISTER_RAW_SIZE (regnum
));
2909 /* Exported procedure: Is PC in the signal trampoline code */
2912 in_sigtramp (pc
, ignore
)
2914 char *ignore
; /* function name */
2916 if (sigtramp_address
== 0)
2918 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
2921 /* Commands to show/set the MIPS FPU type. */
2923 static void show_mipsfpu_command
PARAMS ((char *, int));
2925 show_mipsfpu_command (args
, from_tty
)
2931 switch (MIPS_FPU_TYPE
)
2933 case MIPS_FPU_SINGLE
:
2934 fpu
= "single-precision";
2936 case MIPS_FPU_DOUBLE
:
2937 fpu
= "double-precision";
2940 fpu
= "absent (none)";
2943 if (mips_fpu_type_auto
)
2944 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
2947 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
2952 static void set_mipsfpu_command
PARAMS ((char *, int));
2954 set_mipsfpu_command (args
, from_tty
)
2958 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
2959 show_mipsfpu_command (args
, from_tty
);
2962 static void set_mipsfpu_single_command
PARAMS ((char *, int));
2964 set_mipsfpu_single_command (args
, from_tty
)
2968 mips_fpu_type
= MIPS_FPU_SINGLE
;
2969 mips_fpu_type_auto
= 0;
2972 static void set_mipsfpu_double_command
PARAMS ((char *, int));
2974 set_mipsfpu_double_command (args
, from_tty
)
2978 mips_fpu_type
= MIPS_FPU_DOUBLE
;
2979 mips_fpu_type_auto
= 0;
2982 static void set_mipsfpu_none_command
PARAMS ((char *, int));
2984 set_mipsfpu_none_command (args
, from_tty
)
2988 mips_fpu_type
= MIPS_FPU_NONE
;
2989 mips_fpu_type_auto
= 0;
2992 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
2994 set_mipsfpu_auto_command (args
, from_tty
)
2998 mips_fpu_type_auto
= 1;
3001 /* Command to set the processor type. */
3004 mips_set_processor_type_command (args
, from_tty
)
3010 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3012 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3013 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3014 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3016 /* Restore the value. */
3017 tmp_mips_processor_type
= strsave (mips_processor_type
);
3022 if (!mips_set_processor_type (tmp_mips_processor_type
))
3024 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3025 /* Restore its value. */
3026 tmp_mips_processor_type
= strsave (mips_processor_type
);
3031 mips_show_processor_type_command (args
, from_tty
)
3037 /* Modify the actual processor type. */
3040 mips_set_processor_type (str
)
3048 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3050 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3052 mips_processor_type
= str
;
3053 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3055 /* FIXME tweak fpu flag too */
3062 /* Attempt to identify the particular processor model by reading the
3066 mips_read_processor_type ()
3070 prid
= read_register (PRID_REGNUM
);
3072 if ((prid
& ~0xf) == 0x700)
3073 return savestring ("r3041", strlen("r3041"));
3078 /* Just like reinit_frame_cache, but with the right arguments to be
3079 callable as an sfunc. */
3082 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3085 struct cmd_list_element
*c
;
3087 reinit_frame_cache ();
3091 gdb_print_insn_mips (memaddr
, info
)
3093 disassemble_info
*info
;
3095 mips_extra_func_info_t proc_desc
;
3097 /* Search for the function containing this address. Set the low bit
3098 of the address when searching, in case we were given an even address
3099 that is the start of a 16-bit function. If we didn't do this,
3100 the search would fail because the symbol table says the function
3101 starts at an odd address, i.e. 1 byte past the given address. */
3102 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3103 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3105 /* Make an attempt to determine if this is a 16-bit function. If
3106 the procedure descriptor exists and the address therein is odd,
3107 it's definitely a 16-bit function. Otherwise, we have to just
3108 guess that if the address passed in is odd, it's 16-bits. */
3110 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3112 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3114 /* Round down the instruction address to the appropriate boundary. */
3115 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3117 /* Call the appropriate disassembler based on the target endian-ness. */
3118 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3119 return print_insn_big_mips (memaddr
, info
);
3121 return print_insn_little_mips (memaddr
, info
);
3124 /* Old-style breakpoint macros.
3125 The IDT board uses an unusual breakpoint value, and sometimes gets
3126 confused when it sees the usual MIPS breakpoint instruction. */
3128 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3129 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3130 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3131 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3132 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3133 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3134 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3135 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3137 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3138 counter value to determine whether a 16- or 32-bit breakpoint should be
3139 used. It returns a pointer to a string of bytes that encode a breakpoint
3140 instruction, stores the length of the string to *lenptr, and adjusts pc
3141 (if necessary) to point to the actual memory location where the
3142 breakpoint should be inserted. */
3144 unsigned char *mips_breakpoint_from_pc (pcptr
, lenptr
)
3148 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3150 if (pc_is_mips16 (*pcptr
))
3152 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3153 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3154 *lenptr
= sizeof(mips16_big_breakpoint
);
3155 return mips16_big_breakpoint
;
3159 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3160 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3161 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3163 *lenptr
= sizeof(big_breakpoint
);
3165 if (strcmp (target_shortname
, "mips") == 0)
3166 return idt_big_breakpoint
;
3167 else if (strcmp (target_shortname
, "ddb") == 0
3168 || strcmp (target_shortname
, "pmon") == 0
3169 || strcmp (target_shortname
, "lsi") == 0)
3170 return pmon_big_breakpoint
;
3172 return big_breakpoint
;
3177 if (pc_is_mips16 (*pcptr
))
3179 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3180 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3181 *lenptr
= sizeof(mips16_little_breakpoint
);
3182 return mips16_little_breakpoint
;
3186 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3187 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3188 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3190 *lenptr
= sizeof(little_breakpoint
);
3192 if (strcmp (target_shortname
, "mips") == 0)
3193 return idt_little_breakpoint
;
3194 else if (strcmp (target_shortname
, "ddb") == 0
3195 || strcmp (target_shortname
, "pmon") == 0
3196 || strcmp (target_shortname
, "lsi") == 0)
3197 return pmon_little_breakpoint
;
3199 return little_breakpoint
;
3204 /* If PC is in a mips16 call or return stub, return the address of the target
3205 PC, which is either the callee or the caller. There are several
3206 cases which must be handled:
3208 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3209 target PC is in $31 ($ra).
3210 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3211 and the target PC is in $2.
3212 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3213 before the jal instruction, this is effectively a call stub
3214 and the the target PC is in $2. Otherwise this is effectively
3215 a return stub and the target PC is in $18.
3217 See the source code for the stubs in gcc/config/mips/mips16.S for
3220 This function implements the SKIP_TRAMPOLINE_CODE macro.
3228 CORE_ADDR start_addr
;
3230 /* Find the starting address and name of the function containing the PC. */
3231 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3234 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3235 target PC is in $31 ($ra). */
3236 if (strcmp (name
, "__mips16_ret_sf") == 0
3237 || strcmp (name
, "__mips16_ret_df") == 0)
3238 return read_register (RA_REGNUM
);
3240 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3242 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3243 and the target PC is in $2. */
3244 if (name
[19] >= '0' && name
[19] <= '9')
3245 return read_register (2);
3247 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3248 before the jal instruction, this is effectively a call stub
3249 and the the target PC is in $2. Otherwise this is effectively
3250 a return stub and the target PC is in $18. */
3251 else if (name
[19] == 's' || name
[19] == 'd')
3253 if (pc
== start_addr
)
3255 /* Check if the target of the stub is a compiler-generated
3256 stub. Such a stub for a function bar might have a name
3257 like __fn_stub_bar, and might look like this:
3262 la $1,bar (becomes a lui/addiu pair)
3264 So scan down to the lui/addi and extract the target
3265 address from those two instructions. */
3267 CORE_ADDR target_pc
= read_register (2);
3271 /* See if the name of the target function is __fn_stub_*. */
3272 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3274 if (strncmp (name
, "__fn_stub_", 10) != 0
3275 && strcmp (name
, "etext") != 0
3276 && strcmp (name
, "_etext") != 0)
3279 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3280 The limit on the search is arbitrarily set to 20
3281 instructions. FIXME. */
3282 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3284 inst
= mips_fetch_instruction (target_pc
);
3285 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3286 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3287 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3288 return pc
| (inst
& 0xffff); /* low word */
3291 /* Couldn't find the lui/addui pair, so return stub address. */
3295 /* This is the 'return' part of a call stub. The return
3296 address is in $r18. */
3297 return read_register (18);
3300 return 0; /* not a stub */
3304 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3305 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3308 mips_in_call_stub (pc
, name
)
3312 CORE_ADDR start_addr
;
3314 /* Find the starting address of the function containing the PC. If the
3315 caller didn't give us a name, look it up at the same time. */
3316 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3319 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3321 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3322 if (name
[19] >= '0' && name
[19] <= '9')
3324 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3325 before the jal instruction, this is effectively a call stub. */
3326 else if (name
[19] == 's' || name
[19] == 'd')
3327 return pc
== start_addr
;
3330 return 0; /* not a stub */
3334 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3335 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3338 mips_in_return_stub (pc
, name
)
3342 CORE_ADDR start_addr
;
3344 /* Find the starting address of the function containing the PC. */
3345 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3348 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3349 if (strcmp (name
, "__mips16_ret_sf") == 0
3350 || strcmp (name
, "__mips16_ret_df") == 0)
3353 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3354 i.e. after the jal instruction, this is effectively a return stub. */
3355 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3356 && (name
[19] == 's' || name
[19] == 'd')
3357 && pc
!= start_addr
)
3360 return 0; /* not a stub */
3364 /* Return non-zero if the PC is in a library helper function that should
3365 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3368 mips_ignore_helper (pc
)
3373 /* Find the starting address and name of the function containing the PC. */
3374 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3377 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3378 that we want to ignore. */
3379 return (strcmp (name
, "__mips16_ret_sf") == 0
3380 || strcmp (name
, "__mips16_ret_df") == 0);
3384 /* Return a location where we can set a breakpoint that will be hit
3385 when an inferior function call returns. This is normally the
3386 program's entry point. Executables that don't have an entry
3387 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3388 whose address is the location where the breakpoint should be placed. */
3391 mips_call_dummy_address ()
3393 struct minimal_symbol
*sym
;
3395 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3397 return SYMBOL_VALUE_ADDRESS (sym
);
3399 return entry_point_address ();
3404 _initialize_mips_tdep ()
3406 static struct cmd_list_element
*mipsfpulist
= NULL
;
3407 struct cmd_list_element
*c
;
3409 if (!tm_print_insn
) /* Someone may have already set it */
3410 tm_print_insn
= gdb_print_insn_mips
;
3412 /* Let the user turn off floating point and set the fence post for
3413 heuristic_proc_start. */
3415 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
3416 "Set use of MIPS floating-point coprocessor.",
3417 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
3418 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
3419 "Select single-precision MIPS floating-point coprocessor.",
3421 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
3422 "Select double-precision MIPS floating-point coprocessor .",
3424 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
3425 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
3426 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
3427 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
3428 "Select no MIPS floating-point coprocessor.",
3430 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
3431 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
3432 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
3433 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
3434 "Select MIPS floating-point coprocessor automatically.",
3436 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
3437 "Show current use of MIPS floating-point coprocessor target.",
3440 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3441 (char *) &tmp_mips_processor_type
,
3442 "Set the type of MIPS processor in use.\n\
3443 Set this to be able to access processor-type-specific registers.\n\
3446 c
->function
.cfunc
= mips_set_processor_type_command
;
3447 c
= add_show_from_set (c
, &showlist
);
3448 c
->function
.cfunc
= mips_show_processor_type_command
;
3450 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3451 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3453 /* We really would like to have both "0" and "unlimited" work, but
3454 command.c doesn't deal with that. So make it a var_zinteger
3455 because the user can always use "999999" or some such for unlimited. */
3456 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3457 (char *) &heuristic_fence_post
,
3459 Set the distance searched for the start of a function.\n\
3460 If you are debugging a stripped executable, GDB needs to search through the\n\
3461 program for the start of a function. This command sets the distance of the\n\
3462 search. The only need to set it is when debugging a stripped executable.",
3464 /* We need to throw away the frame cache when we set this, since it
3465 might change our ability to get backtraces. */
3466 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3467 add_show_from_set (c
, &showlist
);
3469 /* Allow the user to control whether the upper bits of 64-bit
3470 addresses should be zeroed. */
3472 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *)&mask_address_p
,
3473 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3474 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3475 Without an argument, zeroing of upper address bits is enabled.", &setlist
),