1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE
/* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 /* MIPS specific per-architecture information */
171 /* from the elf header */
175 enum mips_abi mips_abi
;
176 enum mips_abi found_abi
;
177 enum mips_fpu_type mips_fpu_type
;
178 int mips_last_arg_regnum
;
179 int mips_last_fp_arg_regnum
;
180 int default_mask_address_p
;
181 /* Is the target using 64-bit raw integer registers but only
182 storing a left-aligned 32-bit value in each? */
183 int mips64_transfers_32bit_regs_p
;
184 /* Indexes for various registers. IRIX and embedded have
185 different values. This contains the "public" fields. Don't
186 add any that do not need to be public. */
187 const struct mips_regnum
*regnum
;
188 /* Register names table for the current register set. */
189 const char **mips_processor_reg_names
;
191 /* The size of register data available from the target, if known.
192 This doesn't quite obsolete the manual
193 mips64_transfers_32bit_regs_p, since that is documented to force
194 left alignment even for big endian (very strange). */
195 int register_size_valid_p
;
200 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
206 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
207 They are implemented as a pair of 64bit doubles where the high
208 part holds the result of the operation rounded to double, and
209 the low double holds the difference between the exact result and
210 the rounded result. So "high" + "low" contains the result with
211 added precision. Unfortunately, the floatformat structure used
212 by GDB is not powerful enough to describe this format. As a temporary
213 measure, we define a 128bit floatformat that only uses the high part.
214 We lose a bit of precision but that's probably the best we can do
215 for now with the current infrastructure. */
217 static const struct floatformat floatformat_n32n64_long_double_big
=
219 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
220 floatformat_intbit_no
,
221 "floatformat_n32n64_long_double_big",
222 n32n64_floatformat_always_valid
225 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
227 &floatformat_n32n64_long_double_big
,
228 &floatformat_n32n64_long_double_big
231 const struct mips_regnum
*
232 mips_regnum (struct gdbarch
*gdbarch
)
234 return gdbarch_tdep (gdbarch
)->regnum
;
238 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
240 return mips_regnum (gdbarch
)->fp0
+ 12;
243 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
244 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
246 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
248 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
250 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
252 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
253 functions to test, set, or clear bit 0 of addresses. */
256 is_mips16_addr (CORE_ADDR addr
)
262 unmake_mips16_addr (CORE_ADDR addr
)
264 return ((addr
) & ~(CORE_ADDR
) 1);
267 /* Return the MIPS ABI associated with GDBARCH. */
269 mips_abi (struct gdbarch
*gdbarch
)
271 return gdbarch_tdep (gdbarch
)->mips_abi
;
275 mips_isa_regsize (struct gdbarch
*gdbarch
)
277 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
279 /* If we know how big the registers are, use that size. */
280 if (tdep
->register_size_valid_p
)
281 return tdep
->register_size
;
283 /* Fall back to the previous behavior. */
284 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
285 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
288 /* Return the currently configured (or set) saved register size. */
291 mips_abi_regsize (struct gdbarch
*gdbarch
)
293 switch (mips_abi (gdbarch
))
295 case MIPS_ABI_EABI32
:
301 case MIPS_ABI_EABI64
:
303 case MIPS_ABI_UNKNOWN
:
306 internal_error (__FILE__
, __LINE__
, _("bad switch"));
310 /* Functions for setting and testing a bit in a minimal symbol that
311 marks it as 16-bit function. The MSB of the minimal symbol's
312 "info" field is used for this purpose.
314 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
315 i.e. refers to a 16-bit function, and sets a "special" bit in a
316 minimal symbol to mark it as a 16-bit function
318 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
321 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
323 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
325 MSYMBOL_INFO (msym
) = (char *)
326 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
327 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
332 msymbol_is_special (struct minimal_symbol
*msym
)
334 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
337 /* XFER a value from the big/little/left end of the register.
338 Depending on the size of the value it might occupy the entire
339 register or just part of it. Make an allowance for this, aligning
340 things accordingly. */
343 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
344 enum bfd_endian endian
, gdb_byte
*in
,
345 const gdb_byte
*out
, int buf_offset
)
348 gdb_assert (reg_num
>= gdbarch_num_regs (current_gdbarch
));
349 /* Need to transfer the left or right part of the register, based on
350 the targets byte order. */
354 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
356 case BFD_ENDIAN_LITTLE
:
359 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
363 internal_error (__FILE__
, __LINE__
, _("bad switch"));
366 fprintf_unfiltered (gdb_stderr
,
367 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
368 reg_num
, reg_offset
, buf_offset
, length
);
369 if (mips_debug
&& out
!= NULL
)
372 fprintf_unfiltered (gdb_stdlog
, "out ");
373 for (i
= 0; i
< length
; i
++)
374 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
377 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
380 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
382 if (mips_debug
&& in
!= NULL
)
385 fprintf_unfiltered (gdb_stdlog
, "in ");
386 for (i
= 0; i
< length
; i
++)
387 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
390 fprintf_unfiltered (gdb_stdlog
, "\n");
393 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
394 compatiblity mode. A return value of 1 means that we have
395 physical 64-bit registers, but should treat them as 32-bit registers. */
398 mips2_fp_compat (struct frame_info
*frame
)
400 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
402 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
407 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
408 in all the places we deal with FP registers. PR gdb/413. */
409 /* Otherwise check the FR bit in the status register - it controls
410 the FP compatiblity mode. If it is clear we are in compatibility
412 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
419 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
421 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
423 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
425 static struct type
*mips_float_register_type (void);
426 static struct type
*mips_double_register_type (void);
428 /* The list of available "set mips " and "show mips " commands */
430 static struct cmd_list_element
*setmipscmdlist
= NULL
;
431 static struct cmd_list_element
*showmipscmdlist
= NULL
;
433 /* Integer registers 0 thru 31 are handled explicitly by
434 mips_register_name(). Processor specific registers 32 and above
435 are listed in the following tables. */
438 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
442 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
443 "sr", "lo", "hi", "bad", "cause", "pc",
444 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
445 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
446 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
447 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
448 "fsr", "fir", "" /*"fp" */ , "",
449 "", "", "", "", "", "", "", "",
450 "", "", "", "", "", "", "", "",
453 /* Names of IDT R3041 registers. */
455 static const char *mips_r3041_reg_names
[] = {
456 "sr", "lo", "hi", "bad", "cause", "pc",
457 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
458 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
459 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
460 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
461 "fsr", "fir", "", /*"fp" */ "",
462 "", "", "bus", "ccfg", "", "", "", "",
463 "", "", "port", "cmp", "", "", "epc", "prid",
466 /* Names of tx39 registers. */
468 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
469 "sr", "lo", "hi", "bad", "cause", "pc",
470 "", "", "", "", "", "", "", "",
471 "", "", "", "", "", "", "", "",
472 "", "", "", "", "", "", "", "",
473 "", "", "", "", "", "", "", "",
475 "", "", "", "", "", "", "", "",
476 "", "", "config", "cache", "debug", "depc", "epc", ""
479 /* Names of IRIX registers. */
480 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
481 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
482 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
483 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
484 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
485 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
489 /* Return the name of the register corresponding to REGNO. */
491 mips_register_name (int regno
)
493 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
494 /* GPR names for all ABIs other than n32/n64. */
495 static char *mips_gpr_names
[] = {
496 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
497 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
498 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
499 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
502 /* GPR names for n32 and n64 ABIs. */
503 static char *mips_n32_n64_gpr_names
[] = {
504 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
505 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
506 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
507 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
510 enum mips_abi abi
= mips_abi (current_gdbarch
);
512 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
513 but then don't make the raw register names visible. */
514 int rawnum
= regno
% gdbarch_num_regs (current_gdbarch
);
515 if (regno
< gdbarch_num_regs (current_gdbarch
))
518 /* The MIPS integer registers are always mapped from 0 to 31. The
519 names of the registers (which reflects the conventions regarding
520 register use) vary depending on the ABI. */
521 if (0 <= rawnum
&& rawnum
< 32)
523 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
524 return mips_n32_n64_gpr_names
[rawnum
];
526 return mips_gpr_names
[rawnum
];
528 else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch
)))
529 return tdesc_register_name (rawnum
);
530 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (current_gdbarch
))
532 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
533 return tdep
->mips_processor_reg_names
[rawnum
- 32];
536 internal_error (__FILE__
, __LINE__
,
537 _("mips_register_name: bad register number %d"), rawnum
);
540 /* Return the groups that a MIPS register can be categorised into. */
543 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
544 struct reggroup
*reggroup
)
549 int rawnum
= regnum
% gdbarch_num_regs (current_gdbarch
);
550 int pseudo
= regnum
/ gdbarch_num_regs (current_gdbarch
);
551 if (reggroup
== all_reggroup
)
553 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
554 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
555 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
556 (gdbarch), as not all architectures are multi-arch. */
557 raw_p
= rawnum
< gdbarch_num_regs (current_gdbarch
);
558 if (gdbarch_register_name (current_gdbarch
, regnum
) == NULL
559 || gdbarch_register_name (current_gdbarch
, regnum
)[0] == '\0')
561 if (reggroup
== float_reggroup
)
562 return float_p
&& pseudo
;
563 if (reggroup
== vector_reggroup
)
564 return vector_p
&& pseudo
;
565 if (reggroup
== general_reggroup
)
566 return (!vector_p
&& !float_p
) && pseudo
;
567 /* Save the pseudo registers. Need to make certain that any code
568 extracting register values from a saved register cache also uses
570 if (reggroup
== save_reggroup
)
571 return raw_p
&& pseudo
;
572 /* Restore the same pseudo register. */
573 if (reggroup
== restore_reggroup
)
574 return raw_p
&& pseudo
;
578 /* Return the groups that a MIPS register can be categorised into.
579 This version is only used if we have a target description which
580 describes real registers (and their groups). */
583 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
584 struct reggroup
*reggroup
)
586 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
587 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
590 /* Only save, restore, and display the pseudo registers. Need to
591 make certain that any code extracting register values from a
592 saved register cache also uses pseudo registers.
594 Note: saving and restoring the pseudo registers is slightly
595 strange; if we have 64 bits, we should save and restore all
596 64 bits. But this is hard and has little benefit. */
600 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
604 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
607 /* Map the symbol table registers which live in the range [1 *
608 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
609 registers. Take care of alignment and size problems. */
612 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
613 int cookednum
, gdb_byte
*buf
)
615 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
616 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
617 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
618 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
619 regcache_raw_read (regcache
, rawnum
, buf
);
620 else if (register_size (gdbarch
, rawnum
) >
621 register_size (gdbarch
, cookednum
))
623 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
624 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
625 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
627 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
630 internal_error (__FILE__
, __LINE__
, _("bad register size"));
634 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
635 struct regcache
*regcache
, int cookednum
,
638 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
639 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
640 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
641 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
642 regcache_raw_write (regcache
, rawnum
, buf
);
643 else if (register_size (gdbarch
, rawnum
) >
644 register_size (gdbarch
, cookednum
))
646 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
647 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
648 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
650 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
653 internal_error (__FILE__
, __LINE__
, _("bad register size"));
656 /* Table to translate MIPS16 register field to actual register number. */
657 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
659 /* Heuristic_proc_start may hunt through the text section for a long
660 time across a 2400 baud serial line. Allows the user to limit this
663 static unsigned int heuristic_fence_post
= 0;
665 /* Number of bytes of storage in the actual machine representation for
666 register N. NOTE: This defines the pseudo register type so need to
667 rebuild the architecture vector. */
669 static int mips64_transfers_32bit_regs_p
= 0;
672 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
673 struct cmd_list_element
*c
)
675 struct gdbarch_info info
;
676 gdbarch_info_init (&info
);
677 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
678 instead of relying on globals. Doing that would let generic code
679 handle the search for this specific architecture. */
680 if (!gdbarch_update_p (info
))
682 mips64_transfers_32bit_regs_p
= 0;
683 error (_("32-bit compatibility mode not supported"));
687 /* Convert to/from a register and the corresponding memory value. */
690 mips_convert_register_p (int regnum
, struct type
*type
)
692 return (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
693 && register_size (current_gdbarch
, regnum
) == 4
694 && (regnum
% gdbarch_num_regs (current_gdbarch
))
695 >= mips_regnum (current_gdbarch
)->fp0
696 && (regnum
% gdbarch_num_regs (current_gdbarch
))
697 < mips_regnum (current_gdbarch
)->fp0
+ 32
698 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
702 mips_register_to_value (struct frame_info
*frame
, int regnum
,
703 struct type
*type
, gdb_byte
*to
)
705 get_frame_register (frame
, regnum
+ 0, to
+ 4);
706 get_frame_register (frame
, regnum
+ 1, to
+ 0);
710 mips_value_to_register (struct frame_info
*frame
, int regnum
,
711 struct type
*type
, const gdb_byte
*from
)
713 put_frame_register (frame
, regnum
+ 0, from
+ 4);
714 put_frame_register (frame
, regnum
+ 1, from
+ 0);
717 /* Return the GDB type object for the "standard" data type of data in
721 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
723 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (current_gdbarch
));
724 if ((regnum
% gdbarch_num_regs (current_gdbarch
))
725 >= mips_regnum (current_gdbarch
)->fp0
726 && (regnum
% gdbarch_num_regs (current_gdbarch
))
727 < mips_regnum (current_gdbarch
)->fp0
+ 32)
729 /* The floating-point registers raw, or cooked, always match
730 mips_isa_regsize(), and also map 1:1, byte for byte. */
731 if (mips_isa_regsize (gdbarch
) == 4)
732 return builtin_type_ieee_single
;
734 return builtin_type_ieee_double
;
736 else if (regnum
< gdbarch_num_regs (current_gdbarch
))
738 /* The raw or ISA registers. These are all sized according to
740 if (mips_isa_regsize (gdbarch
) == 4)
741 return builtin_type_int32
;
743 return builtin_type_int64
;
747 /* The cooked or ABI registers. These are sized according to
748 the ABI (with a few complications). */
749 if (regnum
>= (gdbarch_num_regs (current_gdbarch
)
750 + mips_regnum (current_gdbarch
)->fp_control_status
)
751 && regnum
<= gdbarch_num_regs (current_gdbarch
)
752 + MIPS_LAST_EMBED_REGNUM
)
753 /* The pseudo/cooked view of the embedded registers is always
754 32-bit. The raw view is handled below. */
755 return builtin_type_int32
;
756 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
757 /* The target, while possibly using a 64-bit register buffer,
758 is only transfering 32-bits of each integer register.
759 Reflect this in the cooked/pseudo (ABI) register value. */
760 return builtin_type_int32
;
761 else if (mips_abi_regsize (gdbarch
) == 4)
762 /* The ABI is restricted to 32-bit registers (the ISA could be
764 return builtin_type_int32
;
767 return builtin_type_int64
;
771 /* Return the GDB type for the pseudo register REGNUM, which is the
772 ABI-level view. This function is only called if there is a target
773 description which includes registers, so we know precisely the
774 types of hardware registers. */
777 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
779 const int num_regs
= gdbarch_num_regs (gdbarch
);
780 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
781 int rawnum
= regnum
% num_regs
;
782 struct type
*rawtype
;
784 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
786 /* Absent registers are still absent. */
787 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
788 if (TYPE_LENGTH (rawtype
) == 0)
791 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
792 /* Present the floating point registers however the hardware did;
793 do not try to convert between FPU layouts. */
796 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
798 /* The pseudo/cooked view of embedded registers is always
799 32-bit, even if the target transfers 64-bit values for them.
800 New targets relying on XML descriptions should only transfer
801 the necessary 32 bits, but older versions of GDB expected 64,
802 so allow the target to provide 64 bits without interfering
803 with the displayed type. */
804 return builtin_type_int32
;
807 /* Use pointer types for registers if we can. For n32 we can not,
808 since we do not have a 64-bit pointer type. */
809 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
811 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
812 return builtin_type_void_data_ptr
;
813 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
814 return builtin_type_void_func_ptr
;
817 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
818 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
819 return builtin_type_int32
;
821 /* For all other registers, pass through the hardware type. */
825 /* Should the upper word of 64-bit addresses be zeroed? */
826 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
829 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
831 switch (mask_address_var
)
833 case AUTO_BOOLEAN_TRUE
:
835 case AUTO_BOOLEAN_FALSE
:
838 case AUTO_BOOLEAN_AUTO
:
839 return tdep
->default_mask_address_p
;
841 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
847 show_mask_address (struct ui_file
*file
, int from_tty
,
848 struct cmd_list_element
*c
, const char *value
)
850 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
852 deprecated_show_value_hack (file
, from_tty
, c
, value
);
853 switch (mask_address_var
)
855 case AUTO_BOOLEAN_TRUE
:
856 printf_filtered ("The 32 bit mips address mask is enabled\n");
858 case AUTO_BOOLEAN_FALSE
:
859 printf_filtered ("The 32 bit mips address mask is disabled\n");
861 case AUTO_BOOLEAN_AUTO
:
863 ("The 32 bit address mask is set automatically. Currently %s\n",
864 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
867 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
872 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
875 mips_pc_is_mips16 (CORE_ADDR memaddr
)
877 struct minimal_symbol
*sym
;
879 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
880 if (is_mips16_addr (memaddr
))
883 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
884 the high bit of the info field. Use this to decide if the function is
885 MIPS16 or normal MIPS. */
886 sym
= lookup_minimal_symbol_by_pc (memaddr
);
888 return msymbol_is_special (sym
);
893 /* MIPS believes that the PC has a sign extended value. Perhaps the
894 all registers should be sign extended for simplicity? */
897 mips_read_pc (struct regcache
*regcache
)
900 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
901 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
906 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
908 return frame_unwind_register_signed (next_frame
,
909 gdbarch_num_regs (current_gdbarch
)
910 + mips_regnum (gdbarch
)->pc
);
914 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
916 return frame_unwind_register_signed (next_frame
,
917 gdbarch_num_regs (current_gdbarch
)
921 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
922 dummy frame. The frame ID's base needs to match the TOS value
923 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
926 static struct frame_id
927 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
929 return frame_id_build
930 (frame_unwind_register_signed (next_frame
,
931 gdbarch_num_regs (current_gdbarch
)
933 frame_pc_unwind (next_frame
));
937 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
939 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
940 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
943 /* Fetch and return instruction from the specified location. If the PC
944 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
947 mips_fetch_instruction (CORE_ADDR addr
)
949 gdb_byte buf
[MIPS_INSN32_SIZE
];
953 if (mips_pc_is_mips16 (addr
))
955 instlen
= MIPS_INSN16_SIZE
;
956 addr
= unmake_mips16_addr (addr
);
959 instlen
= MIPS_INSN32_SIZE
;
960 status
= read_memory_nobpt (addr
, buf
, instlen
);
962 memory_error (status
, addr
);
963 return extract_unsigned_integer (buf
, instlen
);
966 /* These the fields of 32 bit mips instructions */
967 #define mips32_op(x) (x >> 26)
968 #define itype_op(x) (x >> 26)
969 #define itype_rs(x) ((x >> 21) & 0x1f)
970 #define itype_rt(x) ((x >> 16) & 0x1f)
971 #define itype_immediate(x) (x & 0xffff)
973 #define jtype_op(x) (x >> 26)
974 #define jtype_target(x) (x & 0x03ffffff)
976 #define rtype_op(x) (x >> 26)
977 #define rtype_rs(x) ((x >> 21) & 0x1f)
978 #define rtype_rt(x) ((x >> 16) & 0x1f)
979 #define rtype_rd(x) ((x >> 11) & 0x1f)
980 #define rtype_shamt(x) ((x >> 6) & 0x1f)
981 #define rtype_funct(x) (x & 0x3f)
984 mips32_relative_offset (ULONGEST inst
)
986 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
989 /* Determine where to set a single step breakpoint while considering
990 branch prediction. */
992 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
996 inst
= mips_fetch_instruction (pc
);
997 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
999 if (itype_op (inst
) >> 2 == 5)
1000 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1002 op
= (itype_op (inst
) & 0x03);
1012 goto greater_branch
;
1017 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1018 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1020 int tf
= itype_rt (inst
) & 0x01;
1021 int cnum
= itype_rt (inst
) >> 2;
1023 get_frame_register_signed (frame
, mips_regnum (current_gdbarch
)->
1025 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1027 if (((cond
>> cnum
) & 0x01) == tf
)
1028 pc
+= mips32_relative_offset (inst
) + 4;
1033 pc
+= 4; /* Not a branch, next instruction is easy */
1036 { /* This gets way messy */
1038 /* Further subdivide into SPECIAL, REGIMM and other */
1039 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1041 case 0: /* SPECIAL */
1042 op
= rtype_funct (inst
);
1047 /* Set PC to that address */
1048 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1054 break; /* end SPECIAL */
1055 case 1: /* REGIMM */
1057 op
= itype_rt (inst
); /* branch condition */
1062 case 16: /* BLTZAL */
1063 case 18: /* BLTZALL */
1065 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1066 pc
+= mips32_relative_offset (inst
) + 4;
1068 pc
+= 8; /* after the delay slot */
1072 case 17: /* BGEZAL */
1073 case 19: /* BGEZALL */
1074 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1075 pc
+= mips32_relative_offset (inst
) + 4;
1077 pc
+= 8; /* after the delay slot */
1079 /* All of the other instructions in the REGIMM category */
1084 break; /* end REGIMM */
1089 reg
= jtype_target (inst
) << 2;
1090 /* Upper four bits get never changed... */
1091 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1094 /* FIXME case JALX : */
1097 reg
= jtype_target (inst
) << 2;
1098 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1099 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1101 break; /* The new PC will be alternate mode */
1102 case 4: /* BEQ, BEQL */
1104 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1105 get_frame_register_signed (frame
, itype_rt (inst
)))
1106 pc
+= mips32_relative_offset (inst
) + 4;
1110 case 5: /* BNE, BNEL */
1112 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1113 get_frame_register_signed (frame
, itype_rt (inst
)))
1114 pc
+= mips32_relative_offset (inst
) + 4;
1118 case 6: /* BLEZ, BLEZL */
1119 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1120 pc
+= mips32_relative_offset (inst
) + 4;
1126 greater_branch
: /* BGTZ, BGTZL */
1127 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1128 pc
+= mips32_relative_offset (inst
) + 4;
1135 } /* mips32_next_pc */
1137 /* Decoding the next place to set a breakpoint is irregular for the
1138 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1139 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1140 We dont want to set a single step instruction on the extend instruction
1144 /* Lots of mips16 instruction formats */
1145 /* Predicting jumps requires itype,ritype,i8type
1146 and their extensions extItype,extritype,extI8type
1148 enum mips16_inst_fmts
1150 itype
, /* 0 immediate 5,10 */
1151 ritype
, /* 1 5,3,8 */
1152 rrtype
, /* 2 5,3,3,5 */
1153 rritype
, /* 3 5,3,3,5 */
1154 rrrtype
, /* 4 5,3,3,3,2 */
1155 rriatype
, /* 5 5,3,3,1,4 */
1156 shifttype
, /* 6 5,3,3,3,2 */
1157 i8type
, /* 7 5,3,8 */
1158 i8movtype
, /* 8 5,3,3,5 */
1159 i8mov32rtype
, /* 9 5,3,5,3 */
1160 i64type
, /* 10 5,3,8 */
1161 ri64type
, /* 11 5,3,3,5 */
1162 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1163 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1164 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1165 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1166 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1167 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1168 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1169 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1170 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1171 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1173 /* I am heaping all the fields of the formats into one structure and
1174 then, only the fields which are involved in instruction extension */
1178 unsigned int regx
; /* Function in i8 type */
1183 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1184 for the bits which make up the immediatate extension. */
1187 extended_offset (unsigned int extension
)
1190 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1192 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1194 value
|= extension
& 0x01f; /* extract 4:0 */
1198 /* Only call this function if you know that this is an extendable
1199 instruction. It won't malfunction, but why make excess remote memory
1200 references? If the immediate operands get sign extended or something,
1201 do it after the extension is performed. */
1202 /* FIXME: Every one of these cases needs to worry about sign extension
1203 when the offset is to be used in relative addressing. */
1206 fetch_mips_16 (CORE_ADDR pc
)
1209 pc
&= 0xfffffffe; /* clear the low order bit */
1210 target_read_memory (pc
, buf
, 2);
1211 return extract_unsigned_integer (buf
, 2);
1215 unpack_mips16 (CORE_ADDR pc
,
1216 unsigned int extension
,
1218 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1223 switch (insn_format
)
1230 value
= extended_offset (extension
);
1231 value
= value
<< 11; /* rom for the original value */
1232 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1236 value
= inst
& 0x7ff;
1237 /* FIXME : Consider sign extension */
1246 { /* A register identifier and an offset */
1247 /* Most of the fields are the same as I type but the
1248 immediate value is of a different length */
1252 value
= extended_offset (extension
);
1253 value
= value
<< 8; /* from the original instruction */
1254 value
|= inst
& 0xff; /* eleven bits from instruction */
1255 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1256 if (value
& 0x4000) /* test the sign bit , bit 26 */
1258 value
&= ~0x3fff; /* remove the sign bit */
1264 value
= inst
& 0xff; /* 8 bits */
1265 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1266 /* FIXME: Do sign extension , this format needs it */
1267 if (value
& 0x80) /* THIS CONFUSES ME */
1269 value
&= 0xef; /* remove the sign bit */
1279 unsigned long value
;
1280 unsigned int nexthalf
;
1281 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1282 value
= value
<< 16;
1283 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1291 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1293 upk
->offset
= offset
;
1300 add_offset_16 (CORE_ADDR pc
, int offset
)
1302 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1306 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1307 unsigned int extension
, unsigned int insn
)
1309 int op
= (insn
>> 11);
1312 case 2: /* Branch */
1315 struct upk_mips16 upk
;
1316 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1317 offset
= upk
.offset
;
1323 pc
+= (offset
<< 1) + 2;
1326 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1328 struct upk_mips16 upk
;
1329 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1330 pc
= add_offset_16 (pc
, upk
.offset
);
1331 if ((insn
>> 10) & 0x01) /* Exchange mode */
1332 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1339 struct upk_mips16 upk
;
1341 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1342 reg
= get_frame_register_signed (frame
, upk
.regx
);
1344 pc
+= (upk
.offset
<< 1) + 2;
1351 struct upk_mips16 upk
;
1353 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1354 reg
= get_frame_register_signed (frame
, upk
.regx
);
1356 pc
+= (upk
.offset
<< 1) + 2;
1361 case 12: /* I8 Formats btez btnez */
1363 struct upk_mips16 upk
;
1365 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1366 /* upk.regx contains the opcode */
1367 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1368 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1369 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1370 /* pc = add_offset_16(pc,upk.offset) ; */
1371 pc
+= (upk
.offset
<< 1) + 2;
1376 case 29: /* RR Formats JR, JALR, JALR-RA */
1378 struct upk_mips16 upk
;
1379 /* upk.fmt = rrtype; */
1384 upk
.regx
= (insn
>> 8) & 0x07;
1385 upk
.regy
= (insn
>> 5) & 0x07;
1393 break; /* Function return instruction */
1399 break; /* BOGUS Guess */
1401 pc
= get_frame_register_signed (frame
, reg
);
1408 /* This is an instruction extension. Fetch the real instruction
1409 (which follows the extension) and decode things based on
1413 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1426 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1428 unsigned int insn
= fetch_mips_16 (pc
);
1429 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1432 /* The mips_next_pc function supports single_step when the remote
1433 target monitor or stub is not developed enough to do a single_step.
1434 It works by decoding the current instruction and predicting where a
1435 branch will go. This isnt hard because all the data is available.
1436 The MIPS32 and MIPS16 variants are quite different. */
1438 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1440 if (is_mips16_addr (pc
))
1441 return mips16_next_pc (frame
, pc
);
1443 return mips32_next_pc (frame
, pc
);
1446 struct mips_frame_cache
1449 struct trad_frame_saved_reg
*saved_regs
;
1452 /* Set a register's saved stack address in temp_saved_regs. If an
1453 address has already been set for this register, do nothing; this
1454 way we will only recognize the first save of a given register in a
1457 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1458 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1459 Strictly speaking, only the second range is used as it is only second
1460 range (the ABI instead of ISA registers) that comes into play when finding
1461 saved registers in a frame. */
1464 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1467 if (this_cache
!= NULL
1468 && this_cache
->saved_regs
[regnum
].addr
== -1)
1470 this_cache
->saved_regs
[regnum
1471 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1473 this_cache
->saved_regs
[regnum
1474 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1480 /* Fetch the immediate value from a MIPS16 instruction.
1481 If the previous instruction was an EXTEND, use it to extend
1482 the upper bits of the immediate value. This is a helper function
1483 for mips16_scan_prologue. */
1486 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1487 unsigned short inst
, /* current instruction */
1488 int nbits
, /* number of bits in imm field */
1489 int scale
, /* scale factor to be applied to imm */
1490 int is_signed
) /* is the imm field signed? */
1494 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1496 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1497 if (offset
& 0x8000) /* check for negative extend */
1498 offset
= 0 - (0x10000 - (offset
& 0xffff));
1499 return offset
| (inst
& 0x1f);
1503 int max_imm
= 1 << nbits
;
1504 int mask
= max_imm
- 1;
1505 int sign_bit
= max_imm
>> 1;
1507 offset
= inst
& mask
;
1508 if (is_signed
&& (offset
& sign_bit
))
1509 offset
= 0 - (max_imm
- offset
);
1510 return offset
* scale
;
1515 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1516 the associated FRAME_CACHE if not null.
1517 Return the address of the first instruction past the prologue. */
1520 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1521 struct frame_info
*next_frame
,
1522 struct mips_frame_cache
*this_cache
)
1525 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1527 long frame_offset
= 0; /* Size of stack frame. */
1528 long frame_adjust
= 0; /* Offset of FP from SP. */
1529 int frame_reg
= MIPS_SP_REGNUM
;
1530 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1531 unsigned inst
= 0; /* current instruction */
1532 unsigned entry_inst
= 0; /* the entry instruction */
1535 int extend_bytes
= 0;
1536 int prev_extend_bytes
;
1537 CORE_ADDR end_prologue_addr
= 0;
1539 /* Can be called when there's no process, and hence when there's no
1541 if (next_frame
!= NULL
)
1542 sp
= frame_unwind_register_signed (next_frame
,
1543 gdbarch_num_regs (current_gdbarch
)
1548 if (limit_pc
> start_pc
+ 200)
1549 limit_pc
= start_pc
+ 200;
1551 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1553 /* Save the previous instruction. If it's an EXTEND, we'll extract
1554 the immediate offset extension from it in mips16_get_imm. */
1557 /* Fetch and decode the instruction. */
1558 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1560 /* Normally we ignore extend instructions. However, if it is
1561 not followed by a valid prologue instruction, then this
1562 instruction is not part of the prologue either. We must
1563 remember in this case to adjust the end_prologue_addr back
1565 if ((inst
& 0xf800) == 0xf000) /* extend */
1567 extend_bytes
= MIPS_INSN16_SIZE
;
1571 prev_extend_bytes
= extend_bytes
;
1574 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1575 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1577 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1578 if (offset
< 0) /* negative stack adjustment? */
1579 frame_offset
-= offset
;
1581 /* Exit loop if a positive stack adjustment is found, which
1582 usually means that the stack cleanup code in the function
1583 epilogue is reached. */
1586 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1588 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1589 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1590 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1592 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1594 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1595 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1596 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1598 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1600 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1601 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1603 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1605 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1606 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1608 else if (inst
== 0x673d) /* move $s1, $sp */
1613 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1615 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1616 frame_addr
= sp
+ offset
;
1618 frame_adjust
= offset
;
1620 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1622 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1623 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1624 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1626 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1628 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1629 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1630 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1632 else if ((inst
& 0xf81f) == 0xe809
1633 && (inst
& 0x700) != 0x700) /* entry */
1634 entry_inst
= inst
; /* save for later processing */
1635 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1636 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1637 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1639 /* This instruction is part of the prologue, but we don't
1640 need to do anything special to handle it. */
1644 /* This instruction is not an instruction typically found
1645 in a prologue, so we must have reached the end of the
1647 if (end_prologue_addr
== 0)
1648 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1652 /* The entry instruction is typically the first instruction in a function,
1653 and it stores registers at offsets relative to the value of the old SP
1654 (before the prologue). But the value of the sp parameter to this
1655 function is the new SP (after the prologue has been executed). So we
1656 can't calculate those offsets until we've seen the entire prologue,
1657 and can calculate what the old SP must have been. */
1658 if (entry_inst
!= 0)
1660 int areg_count
= (entry_inst
>> 8) & 7;
1661 int sreg_count
= (entry_inst
>> 6) & 3;
1663 /* The entry instruction always subtracts 32 from the SP. */
1666 /* Now we can calculate what the SP must have been at the
1667 start of the function prologue. */
1670 /* Check if a0-a3 were saved in the caller's argument save area. */
1671 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1673 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1674 offset
+= mips_abi_regsize (current_gdbarch
);
1677 /* Check if the ra register was pushed on the stack. */
1679 if (entry_inst
& 0x20)
1681 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1682 offset
-= mips_abi_regsize (current_gdbarch
);
1685 /* Check if the s0 and s1 registers were pushed on the stack. */
1686 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1688 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1689 offset
-= mips_abi_regsize (current_gdbarch
);
1693 if (this_cache
!= NULL
)
1696 (frame_unwind_register_signed (next_frame
,
1697 gdbarch_num_regs (current_gdbarch
)
1699 + frame_offset
- frame_adjust
);
1700 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1701 be able to get rid of the assignment below, evetually. But it's
1702 still needed for now. */
1703 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1704 + mips_regnum (current_gdbarch
)->pc
]
1705 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1709 /* If we didn't reach the end of the prologue when scanning the function
1710 instructions, then set end_prologue_addr to the address of the
1711 instruction immediately after the last one we scanned. */
1712 if (end_prologue_addr
== 0)
1713 end_prologue_addr
= cur_pc
;
1715 return end_prologue_addr
;
1718 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1719 Procedures that use the 32-bit instruction set are handled by the
1720 mips_insn32 unwinder. */
1722 static struct mips_frame_cache
*
1723 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1725 struct mips_frame_cache
*cache
;
1727 if ((*this_cache
) != NULL
)
1728 return (*this_cache
);
1729 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1730 (*this_cache
) = cache
;
1731 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1733 /* Analyze the function prologue. */
1735 const CORE_ADDR pc
=
1736 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1737 CORE_ADDR start_addr
;
1739 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1740 if (start_addr
== 0)
1741 start_addr
= heuristic_proc_start (pc
);
1742 /* We can't analyze the prologue if we couldn't find the begining
1744 if (start_addr
== 0)
1747 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1750 /* gdbarch_sp_regnum contains the value and not the address. */
1751 trad_frame_set_value (cache
->saved_regs
, gdbarch_num_regs (current_gdbarch
)
1752 + MIPS_SP_REGNUM
, cache
->base
);
1754 return (*this_cache
);
1758 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1759 struct frame_id
*this_id
)
1761 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1763 (*this_id
) = frame_id_build (info
->base
,
1764 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1768 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1770 int regnum
, int *optimizedp
,
1771 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1772 int *realnump
, gdb_byte
*valuep
)
1774 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1776 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1777 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1780 static const struct frame_unwind mips_insn16_frame_unwind
=
1783 mips_insn16_frame_this_id
,
1784 mips_insn16_frame_prev_register
1787 static const struct frame_unwind
*
1788 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1790 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1791 if (mips_pc_is_mips16 (pc
))
1792 return &mips_insn16_frame_unwind
;
1797 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1800 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1805 static const struct frame_base mips_insn16_frame_base
=
1807 &mips_insn16_frame_unwind
,
1808 mips_insn16_frame_base_address
,
1809 mips_insn16_frame_base_address
,
1810 mips_insn16_frame_base_address
1813 static const struct frame_base
*
1814 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1816 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1817 return &mips_insn16_frame_base
;
1822 /* Mark all the registers as unset in the saved_regs array
1823 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1826 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1828 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1832 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1835 for (i
= 0; i
< num_regs
; i
++)
1837 this_cache
->saved_regs
[i
].addr
= -1;
1842 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1843 the associated FRAME_CACHE if not null.
1844 Return the address of the first instruction past the prologue. */
1847 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1848 struct frame_info
*next_frame
,
1849 struct mips_frame_cache
*this_cache
)
1852 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1855 int frame_reg
= MIPS_SP_REGNUM
;
1857 CORE_ADDR end_prologue_addr
= 0;
1858 int seen_sp_adjust
= 0;
1859 int load_immediate_bytes
= 0;
1861 /* Can be called when there's no process, and hence when there's no
1863 if (next_frame
!= NULL
)
1864 sp
= frame_unwind_register_signed (next_frame
,
1865 gdbarch_num_regs (current_gdbarch
)
1870 if (limit_pc
> start_pc
+ 200)
1871 limit_pc
= start_pc
+ 200;
1876 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1878 unsigned long inst
, high_word
, low_word
;
1881 /* Fetch the instruction. */
1882 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1884 /* Save some code by pre-extracting some useful fields. */
1885 high_word
= (inst
>> 16) & 0xffff;
1886 low_word
= inst
& 0xffff;
1887 reg
= high_word
& 0x1f;
1889 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1890 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1891 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1893 if (low_word
& 0x8000) /* negative stack adjustment? */
1894 frame_offset
+= 0x10000 - low_word
;
1896 /* Exit loop if a positive stack adjustment is found, which
1897 usually means that the stack cleanup code in the function
1898 epilogue is reached. */
1902 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1904 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1906 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1908 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1909 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1911 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1913 /* Old gcc frame, r30 is virtual frame pointer. */
1914 if ((long) low_word
!= frame_offset
)
1915 frame_addr
= sp
+ low_word
;
1916 else if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1918 unsigned alloca_adjust
;
1921 frame_addr
= frame_unwind_register_signed
1923 gdbarch_num_regs (current_gdbarch
) + 30);
1925 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1926 if (alloca_adjust
> 0)
1928 /* FP > SP + frame_size. This may be because of
1929 an alloca or somethings similar. Fix sp to
1930 "pre-alloca" value, and try again. */
1931 sp
+= alloca_adjust
;
1932 /* Need to reset the status of all registers. Otherwise,
1933 we will hit a guard that prevents the new address
1934 for each register to be recomputed during the second
1936 reset_saved_regs (this_cache
);
1941 /* move $30,$sp. With different versions of gas this will be either
1942 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1943 Accept any one of these. */
1944 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1946 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1947 if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1949 unsigned alloca_adjust
;
1952 frame_addr
= frame_unwind_register_signed
1954 gdbarch_num_regs (current_gdbarch
) + 30);
1956 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1957 if (alloca_adjust
> 0)
1959 /* FP > SP + frame_size. This may be because of
1960 an alloca or somethings similar. Fix sp to
1961 "pre-alloca" value, and try again. */
1963 /* Need to reset the status of all registers. Otherwise,
1964 we will hit a guard that prevents the new address
1965 for each register to be recomputed during the second
1967 reset_saved_regs (this_cache
);
1972 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1974 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1976 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1977 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1978 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1979 || high_word
== 0x3c1c /* lui $gp,n */
1980 || high_word
== 0x279c /* addiu $gp,$gp,n */
1981 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1982 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1985 /* These instructions are part of the prologue, but we don't
1986 need to do anything special to handle them. */
1988 /* The instructions below load $at or $t0 with an immediate
1989 value in preparation for a stack adjustment via
1990 subu $sp,$sp,[$at,$t0]. These instructions could also
1991 initialize a local variable, so we accept them only before
1992 a stack adjustment instruction was seen. */
1993 else if (!seen_sp_adjust
1994 && (high_word
== 0x3c01 /* lui $at,n */
1995 || high_word
== 0x3c08 /* lui $t0,n */
1996 || high_word
== 0x3421 /* ori $at,$at,n */
1997 || high_word
== 0x3508 /* ori $t0,$t0,n */
1998 || high_word
== 0x3401 /* ori $at,$zero,n */
1999 || high_word
== 0x3408 /* ori $t0,$zero,n */
2002 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2006 /* This instruction is not an instruction typically found
2007 in a prologue, so we must have reached the end of the
2009 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2010 loop now? Why would we need to continue scanning the function
2012 if (end_prologue_addr
== 0)
2013 end_prologue_addr
= cur_pc
;
2017 if (this_cache
!= NULL
)
2020 (frame_unwind_register_signed (next_frame
,
2021 gdbarch_num_regs (current_gdbarch
)
2024 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2025 this assignment below, eventually. But it's still needed
2027 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
2028 + mips_regnum (current_gdbarch
)->pc
]
2029 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
2033 /* If we didn't reach the end of the prologue when scanning the function
2034 instructions, then set end_prologue_addr to the address of the
2035 instruction immediately after the last one we scanned. */
2036 /* brobecker/2004-10-10: I don't think this would ever happen, but
2037 we may as well be careful and do our best if we have a null
2038 end_prologue_addr. */
2039 if (end_prologue_addr
== 0)
2040 end_prologue_addr
= cur_pc
;
2042 /* In a frameless function, we might have incorrectly
2043 skipped some load immediate instructions. Undo the skipping
2044 if the load immediate was not followed by a stack adjustment. */
2045 if (load_immediate_bytes
&& !seen_sp_adjust
)
2046 end_prologue_addr
-= load_immediate_bytes
;
2048 return end_prologue_addr
;
2051 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2052 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2053 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2056 static struct mips_frame_cache
*
2057 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2059 struct mips_frame_cache
*cache
;
2061 if ((*this_cache
) != NULL
)
2062 return (*this_cache
);
2064 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2065 (*this_cache
) = cache
;
2066 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2068 /* Analyze the function prologue. */
2070 const CORE_ADDR pc
=
2071 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2072 CORE_ADDR start_addr
;
2074 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2075 if (start_addr
== 0)
2076 start_addr
= heuristic_proc_start (pc
);
2077 /* We can't analyze the prologue if we couldn't find the begining
2079 if (start_addr
== 0)
2082 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2085 /* gdbarch_sp_regnum contains the value and not the address. */
2086 trad_frame_set_value (cache
->saved_regs
,
2087 gdbarch_num_regs (current_gdbarch
) + MIPS_SP_REGNUM
,
2090 return (*this_cache
);
2094 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2095 struct frame_id
*this_id
)
2097 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2099 (*this_id
) = frame_id_build (info
->base
,
2100 frame_func_unwind (next_frame
, NORMAL_FRAME
));
2104 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2106 int regnum
, int *optimizedp
,
2107 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2108 int *realnump
, gdb_byte
*valuep
)
2110 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2112 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2113 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2116 static const struct frame_unwind mips_insn32_frame_unwind
=
2119 mips_insn32_frame_this_id
,
2120 mips_insn32_frame_prev_register
2123 static const struct frame_unwind
*
2124 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2126 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2127 if (! mips_pc_is_mips16 (pc
))
2128 return &mips_insn32_frame_unwind
;
2133 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2136 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2141 static const struct frame_base mips_insn32_frame_base
=
2143 &mips_insn32_frame_unwind
,
2144 mips_insn32_frame_base_address
,
2145 mips_insn32_frame_base_address
,
2146 mips_insn32_frame_base_address
2149 static const struct frame_base
*
2150 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2152 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2153 return &mips_insn32_frame_base
;
2158 static struct trad_frame_cache
*
2159 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2162 CORE_ADDR start_addr
;
2163 CORE_ADDR stack_addr
;
2164 struct trad_frame_cache
*this_trad_cache
;
2166 if ((*this_cache
) != NULL
)
2167 return (*this_cache
);
2168 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2169 (*this_cache
) = this_trad_cache
;
2171 /* The return address is in the link register. */
2172 trad_frame_set_reg_realreg (this_trad_cache
,
2173 gdbarch_pc_regnum (current_gdbarch
),
2176 /* Frame ID, since it's a frameless / stackless function, no stack
2177 space is allocated and SP on entry is the current SP. */
2178 pc
= frame_pc_unwind (next_frame
);
2179 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2180 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2181 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2183 /* Assume that the frame's base is the same as the
2185 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2187 return this_trad_cache
;
2191 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2192 struct frame_id
*this_id
)
2194 struct trad_frame_cache
*this_trad_cache
2195 = mips_stub_frame_cache (next_frame
, this_cache
);
2196 trad_frame_get_id (this_trad_cache
, this_id
);
2200 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2202 int regnum
, int *optimizedp
,
2203 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2204 int *realnump
, gdb_byte
*valuep
)
2206 struct trad_frame_cache
*this_trad_cache
2207 = mips_stub_frame_cache (next_frame
, this_cache
);
2208 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2209 lvalp
, addrp
, realnump
, valuep
);
2212 static const struct frame_unwind mips_stub_frame_unwind
=
2215 mips_stub_frame_this_id
,
2216 mips_stub_frame_prev_register
2219 static const struct frame_unwind
*
2220 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2222 struct obj_section
*s
;
2223 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2225 if (in_plt_section (pc
, NULL
))
2226 return &mips_stub_frame_unwind
;
2228 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2229 s
= find_pc_section (pc
);
2232 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2233 ".MIPS.stubs") == 0)
2234 return &mips_stub_frame_unwind
;
2240 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2243 struct trad_frame_cache
*this_trad_cache
2244 = mips_stub_frame_cache (next_frame
, this_cache
);
2245 return trad_frame_get_this_base (this_trad_cache
);
2248 static const struct frame_base mips_stub_frame_base
=
2250 &mips_stub_frame_unwind
,
2251 mips_stub_frame_base_address
,
2252 mips_stub_frame_base_address
,
2253 mips_stub_frame_base_address
2256 static const struct frame_base
*
2257 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2259 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2260 return &mips_stub_frame_base
;
2265 /* mips_addr_bits_remove - remove useless address bits */
2268 mips_addr_bits_remove (CORE_ADDR addr
)
2270 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2271 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2272 /* This hack is a work-around for existing boards using PMON, the
2273 simulator, and any other 64-bit targets that doesn't have true
2274 64-bit addressing. On these targets, the upper 32 bits of
2275 addresses are ignored by the hardware. Thus, the PC or SP are
2276 likely to have been sign extended to all 1s by instruction
2277 sequences that load 32-bit addresses. For example, a typical
2278 piece of code that loads an address is this:
2280 lui $r2, <upper 16 bits>
2281 ori $r2, <lower 16 bits>
2283 But the lui sign-extends the value such that the upper 32 bits
2284 may be all 1s. The workaround is simply to mask off these
2285 bits. In the future, gcc may be changed to support true 64-bit
2286 addressing, and this masking will have to be disabled. */
2287 return addr
&= 0xffffffffUL
;
2292 /* mips_software_single_step() is called just before we want to resume
2293 the inferior, if we want to single-step it but there is no hardware
2294 or kernel single-step support (MIPS on GNU/Linux for example). We find
2295 the target of the coming instruction and breakpoint it. */
2298 mips_software_single_step (struct frame_info
*frame
)
2300 CORE_ADDR pc
, next_pc
;
2302 pc
= get_frame_pc (frame
);
2303 next_pc
= mips_next_pc (frame
, pc
);
2305 insert_single_step_breakpoint (next_pc
);
2309 /* Test whether the PC points to the return instruction at the
2310 end of a function. */
2313 mips_about_to_return (CORE_ADDR pc
)
2315 if (mips_pc_is_mips16 (pc
))
2316 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2317 generates a "jr $ra"; other times it generates code to load
2318 the return address from the stack to an accessible register (such
2319 as $a3), then a "jr" using that register. This second case
2320 is almost impossible to distinguish from an indirect jump
2321 used for switch statements, so we don't even try. */
2322 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2324 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2328 /* This fencepost looks highly suspicious to me. Removing it also
2329 seems suspicious as it could affect remote debugging across serial
2333 heuristic_proc_start (CORE_ADDR pc
)
2340 pc
= gdbarch_addr_bits_remove (current_gdbarch
, pc
);
2342 fence
= start_pc
- heuristic_fence_post
;
2346 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2347 fence
= VM_MIN_ADDRESS
;
2349 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2351 /* search back for previous return */
2352 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2353 if (start_pc
< fence
)
2355 /* It's not clear to me why we reach this point when
2356 stop_soon, but with this test, at least we
2357 don't print out warnings for every child forked (eg, on
2358 decstation). 22apr93 rich@cygnus.com. */
2359 if (stop_soon
== NO_STOP_QUIETLY
)
2361 static int blurb_printed
= 0;
2363 warning (_("GDB can't find the start of the function at 0x%s."),
2368 /* This actually happens frequently in embedded
2369 development, when you first connect to a board
2370 and your stack pointer and pc are nowhere in
2371 particular. This message needs to give people
2372 in that situation enough information to
2373 determine that it's no big deal. */
2374 printf_filtered ("\n\
2375 GDB is unable to find the start of the function at 0x%s\n\
2376 and thus can't determine the size of that function's stack frame.\n\
2377 This means that GDB may be unable to access that stack frame, or\n\
2378 the frames below it.\n\
2379 This problem is most likely caused by an invalid program counter or\n\
2381 However, if you think GDB should simply search farther back\n\
2382 from 0x%s for code which looks like the beginning of a\n\
2383 function, you can increase the range of the search using the `set\n\
2384 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2391 else if (mips_pc_is_mips16 (start_pc
))
2393 unsigned short inst
;
2395 /* On MIPS16, any one of the following is likely to be the
2396 start of a function:
2402 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2403 inst
= mips_fetch_instruction (start_pc
);
2404 if ((inst
& 0xff80) == 0x6480) /* save */
2406 if (start_pc
- instlen
>= fence
)
2408 inst
= mips_fetch_instruction (start_pc
- instlen
);
2409 if ((inst
& 0xf800) == 0xf000) /* extend */
2410 start_pc
-= instlen
;
2414 else if (((inst
& 0xf81f) == 0xe809
2415 && (inst
& 0x700) != 0x700) /* entry */
2416 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2417 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2418 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2420 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2421 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2426 else if (mips_about_to_return (start_pc
))
2428 /* Skip return and its delay slot. */
2429 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2436 struct mips_objfile_private
2442 /* According to the current ABI, should the type be passed in a
2443 floating-point register (assuming that there is space)? When there
2444 is no FPU, FP are not even considered as possible candidates for
2445 FP registers and, consequently this returns false - forces FP
2446 arguments into integer registers. */
2449 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2451 return ((typecode
== TYPE_CODE_FLT
2453 && (typecode
== TYPE_CODE_STRUCT
2454 || typecode
== TYPE_CODE_UNION
)
2455 && TYPE_NFIELDS (arg_type
) == 1
2456 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2458 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2461 /* On o32, argument passing in GPRs depends on the alignment of the type being
2462 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2465 mips_type_needs_double_align (struct type
*type
)
2467 enum type_code typecode
= TYPE_CODE (type
);
2469 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2471 else if (typecode
== TYPE_CODE_STRUCT
)
2473 if (TYPE_NFIELDS (type
) < 1)
2475 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2477 else if (typecode
== TYPE_CODE_UNION
)
2481 n
= TYPE_NFIELDS (type
);
2482 for (i
= 0; i
< n
; i
++)
2483 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2490 /* Adjust the address downward (direction of stack growth) so that it
2491 is correctly aligned for a new stack frame. */
2493 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2495 return align_down (addr
, 16);
2499 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2500 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2501 int nargs
, struct value
**args
, CORE_ADDR sp
,
2502 int struct_return
, CORE_ADDR struct_addr
)
2508 int stack_offset
= 0;
2509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2510 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2511 int regsize
= mips_abi_regsize (gdbarch
);
2513 /* For shared libraries, "t9" needs to point at the function
2515 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2517 /* Set the return address register to point to the entry point of
2518 the program, where a breakpoint lies in wait. */
2519 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2521 /* First ensure that the stack and structure return address (if any)
2522 are properly aligned. The stack has to be at least 64-bit
2523 aligned even on 32-bit machines, because doubles must be 64-bit
2524 aligned. For n32 and n64, stack frames need to be 128-bit
2525 aligned, so we round to this widest known alignment. */
2527 sp
= align_down (sp
, 16);
2528 struct_addr
= align_down (struct_addr
, 16);
2530 /* Now make space on the stack for the args. We allocate more
2531 than necessary for EABI, because the first few arguments are
2532 passed in registers, but that's OK. */
2533 for (argnum
= 0; argnum
< nargs
; argnum
++)
2534 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2535 sp
-= align_up (len
, 16);
2538 fprintf_unfiltered (gdb_stdlog
,
2539 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2540 paddr_nz (sp
), (long) align_up (len
, 16));
2542 /* Initialize the integer and float register pointers. */
2543 argreg
= MIPS_A0_REGNUM
;
2544 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2546 /* The struct_return pointer occupies the first parameter-passing reg. */
2550 fprintf_unfiltered (gdb_stdlog
,
2551 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2552 argreg
, paddr_nz (struct_addr
));
2553 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2556 /* Now load as many as possible of the first arguments into
2557 registers, and push the rest onto the stack. Loop thru args
2558 from first to last. */
2559 for (argnum
= 0; argnum
< nargs
; argnum
++)
2561 const gdb_byte
*val
;
2562 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2563 struct value
*arg
= args
[argnum
];
2564 struct type
*arg_type
= check_typedef (value_type (arg
));
2565 int len
= TYPE_LENGTH (arg_type
);
2566 enum type_code typecode
= TYPE_CODE (arg_type
);
2569 fprintf_unfiltered (gdb_stdlog
,
2570 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2571 argnum
+ 1, len
, (int) typecode
);
2573 /* The EABI passes structures that do not fit in a register by
2576 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2578 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2579 typecode
= TYPE_CODE_PTR
;
2583 fprintf_unfiltered (gdb_stdlog
, " push");
2586 val
= value_contents (arg
);
2588 /* 32-bit ABIs always start floating point arguments in an
2589 even-numbered floating point register. Round the FP register
2590 up before the check to see if there are any FP registers
2591 left. Non MIPS_EABI targets also pass the FP in the integer
2592 registers so also round up normal registers. */
2593 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2595 if ((float_argreg
& 1))
2599 /* Floating point arguments passed in registers have to be
2600 treated specially. On 32-bit architectures, doubles
2601 are passed in register pairs; the even register gets
2602 the low word, and the odd register gets the high word.
2603 On non-EABI processors, the first two floating point arguments are
2604 also copied to general registers, because MIPS16 functions
2605 don't use float registers for arguments. This duplication of
2606 arguments in general registers can't hurt non-MIPS16 functions
2607 because those registers are normally skipped. */
2608 /* MIPS_EABI squeezes a struct that contains a single floating
2609 point value into an FP register instead of pushing it onto the
2611 if (fp_register_arg_p (typecode
, arg_type
)
2612 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2614 /* EABI32 will pass doubles in consecutive registers, even on
2615 64-bit cores. At one time, we used to check the size of
2616 `float_argreg' to determine whether or not to pass doubles
2617 in consecutive registers, but this is not sufficient for
2618 making the ABI determination. */
2619 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2621 int low_offset
= gdbarch_byte_order (current_gdbarch
)
2622 == BFD_ENDIAN_BIG
? 4 : 0;
2623 unsigned long regval
;
2625 /* Write the low word of the double to the even register(s). */
2626 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2628 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2629 float_argreg
, phex (regval
, 4));
2630 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2632 /* Write the high word of the double to the odd register(s). */
2633 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2635 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2636 float_argreg
, phex (regval
, 4));
2637 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2641 /* This is a floating point value that fits entirely
2642 in a single register. */
2643 /* On 32 bit ABI's the float_argreg is further adjusted
2644 above to ensure that it is even register aligned. */
2645 LONGEST regval
= extract_unsigned_integer (val
, len
);
2647 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2648 float_argreg
, phex (regval
, len
));
2649 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2654 /* Copy the argument to general registers or the stack in
2655 register-sized pieces. Large arguments are split between
2656 registers and stack. */
2657 /* Note: structs whose size is not a multiple of regsize
2658 are treated specially: Irix cc passes
2659 them in registers where gcc sometimes puts them on the
2660 stack. For maximum compatibility, we will put them in
2662 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2664 /* Note: Floating-point values that didn't fit into an FP
2665 register are only written to memory. */
2668 /* Remember if the argument was written to the stack. */
2669 int stack_used_p
= 0;
2670 int partial_len
= (len
< regsize
? len
: regsize
);
2673 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2676 /* Write this portion of the argument to the stack. */
2677 if (argreg
> MIPS_LAST_ARG_REGNUM
2679 || fp_register_arg_p (typecode
, arg_type
))
2681 /* Should shorter than int integer values be
2682 promoted to int before being stored? */
2683 int longword_offset
= 0;
2686 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2689 && (typecode
== TYPE_CODE_INT
2690 || typecode
== TYPE_CODE_PTR
2691 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2692 longword_offset
= regsize
- len
;
2693 else if ((typecode
== TYPE_CODE_STRUCT
2694 || typecode
== TYPE_CODE_UNION
)
2695 && TYPE_LENGTH (arg_type
) < regsize
)
2696 longword_offset
= regsize
- len
;
2701 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2702 paddr_nz (stack_offset
));
2703 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2704 paddr_nz (longword_offset
));
2707 addr
= sp
+ stack_offset
+ longword_offset
;
2712 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2714 for (i
= 0; i
< partial_len
; i
++)
2716 fprintf_unfiltered (gdb_stdlog
, "%02x",
2720 write_memory (addr
, val
, partial_len
);
2723 /* Note!!! This is NOT an else clause. Odd sized
2724 structs may go thru BOTH paths. Floating point
2725 arguments will not. */
2726 /* Write this portion of the argument to a general
2727 purpose register. */
2728 if (argreg
<= MIPS_LAST_ARG_REGNUM
2729 && !fp_register_arg_p (typecode
, arg_type
))
2732 extract_unsigned_integer (val
, partial_len
);
2735 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2737 phex (regval
, regsize
));
2738 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2745 /* Compute the the offset into the stack at which we
2746 will copy the next parameter.
2748 In the new EABI (and the NABI32), the stack_offset
2749 only needs to be adjusted when it has been used. */
2752 stack_offset
+= align_up (partial_len
, regsize
);
2756 fprintf_unfiltered (gdb_stdlog
, "\n");
2759 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2761 /* Return adjusted stack pointer. */
2765 /* Determine the return value convention being used. */
2767 static enum return_value_convention
2768 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2769 struct type
*type
, struct regcache
*regcache
,
2770 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2772 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2773 return RETURN_VALUE_STRUCT_CONVENTION
;
2775 memset (readbuf
, 0, TYPE_LENGTH (type
));
2776 return RETURN_VALUE_REGISTER_CONVENTION
;
2780 /* N32/N64 ABI stuff. */
2782 /* Search for a naturally aligned double at OFFSET inside a struct
2783 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
2787 mips_n32n64_fp_arg_chunk_p (struct type
*arg_type
, int offset
)
2791 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
2794 if (MIPS_FPU_TYPE
!= MIPS_FPU_DOUBLE
)
2797 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
2800 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
2803 struct type
*field_type
;
2805 /* We're only looking at normal fields. */
2806 if (TYPE_FIELD_STATIC (arg_type
, i
)
2807 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
2810 /* If we have gone past the offset, there is no double to pass. */
2811 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
2815 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
2817 /* If this field is entirely before the requested offset, go
2818 on to the next one. */
2819 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
2822 /* If this is our special aligned double, we can stop. */
2823 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
2824 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
2827 /* This field starts at or before the requested offset, and
2828 overlaps it. If it is a structure, recurse inwards. */
2829 return mips_n32n64_fp_arg_chunk_p (field_type
, offset
- pos
);
2836 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2837 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2838 int nargs
, struct value
**args
, CORE_ADDR sp
,
2839 int struct_return
, CORE_ADDR struct_addr
)
2845 int stack_offset
= 0;
2846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2847 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2849 /* For shared libraries, "t9" needs to point at the function
2851 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2853 /* Set the return address register to point to the entry point of
2854 the program, where a breakpoint lies in wait. */
2855 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2857 /* First ensure that the stack and structure return address (if any)
2858 are properly aligned. The stack has to be at least 64-bit
2859 aligned even on 32-bit machines, because doubles must be 64-bit
2860 aligned. For n32 and n64, stack frames need to be 128-bit
2861 aligned, so we round to this widest known alignment. */
2863 sp
= align_down (sp
, 16);
2864 struct_addr
= align_down (struct_addr
, 16);
2866 /* Now make space on the stack for the args. */
2867 for (argnum
= 0; argnum
< nargs
; argnum
++)
2868 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
2869 sp
-= align_up (len
, 16);
2872 fprintf_unfiltered (gdb_stdlog
,
2873 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2874 paddr_nz (sp
), (long) align_up (len
, 16));
2876 /* Initialize the integer and float register pointers. */
2877 argreg
= MIPS_A0_REGNUM
;
2878 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2880 /* The struct_return pointer occupies the first parameter-passing reg. */
2884 fprintf_unfiltered (gdb_stdlog
,
2885 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2886 argreg
, paddr_nz (struct_addr
));
2887 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2890 /* Now load as many as possible of the first arguments into
2891 registers, and push the rest onto the stack. Loop thru args
2892 from first to last. */
2893 for (argnum
= 0; argnum
< nargs
; argnum
++)
2895 const gdb_byte
*val
;
2896 struct value
*arg
= args
[argnum
];
2897 struct type
*arg_type
= check_typedef (value_type (arg
));
2898 int len
= TYPE_LENGTH (arg_type
);
2899 enum type_code typecode
= TYPE_CODE (arg_type
);
2902 fprintf_unfiltered (gdb_stdlog
,
2903 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2904 argnum
+ 1, len
, (int) typecode
);
2906 val
= value_contents (arg
);
2908 if (fp_register_arg_p (typecode
, arg_type
)
2909 && argreg
<= MIPS_LAST_ARG_REGNUM
)
2911 /* This is a floating point value that fits entirely
2912 in a single register. */
2913 LONGEST regval
= extract_unsigned_integer (val
, len
);
2915 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2916 float_argreg
, phex (regval
, len
));
2917 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
2920 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2921 argreg
, phex (regval
, len
));
2922 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2928 /* Copy the argument to general registers or the stack in
2929 register-sized pieces. Large arguments are split between
2930 registers and stack. */
2931 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
2932 are treated specially: Irix cc passes them in registers
2933 where gcc sometimes puts them on the stack. For maximum
2934 compatibility, we will put them in both places. */
2935 int odd_sized_struct
= (len
> MIPS64_REGSIZE
2936 && len
% MIPS64_REGSIZE
!= 0);
2937 /* Note: Floating-point values that didn't fit into an FP
2938 register are only written to memory. */
2941 /* Remember if the argument was written to the stack. */
2942 int stack_used_p
= 0;
2943 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
2946 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2949 if (fp_register_arg_p (typecode
, arg_type
))
2950 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM
);
2952 /* Write this portion of the argument to the stack. */
2953 if (argreg
> MIPS_LAST_ARG_REGNUM
2954 || odd_sized_struct
)
2956 /* Should shorter than int integer values be
2957 promoted to int before being stored? */
2958 int longword_offset
= 0;
2961 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2963 if ((typecode
== TYPE_CODE_INT
2964 || typecode
== TYPE_CODE_PTR
2965 || typecode
== TYPE_CODE_FLT
)
2967 longword_offset
= MIPS64_REGSIZE
- len
;
2972 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2973 paddr_nz (stack_offset
));
2974 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2975 paddr_nz (longword_offset
));
2978 addr
= sp
+ stack_offset
+ longword_offset
;
2983 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2985 for (i
= 0; i
< partial_len
; i
++)
2987 fprintf_unfiltered (gdb_stdlog
, "%02x",
2991 write_memory (addr
, val
, partial_len
);
2994 /* Note!!! This is NOT an else clause. Odd sized
2995 structs may go thru BOTH paths. */
2996 /* Write this portion of the argument to a general
2997 purpose register. */
2998 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3001 extract_unsigned_integer (val
, partial_len
);
3003 /* A non-floating-point argument being passed in a
3004 general register. If a struct or union, and if
3005 the remaining length is smaller than the register
3006 size, we have to adjust the register value on
3009 It does not seem to be necessary to do the
3010 same for integral types. */
3012 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3013 && partial_len
< MIPS64_REGSIZE
3014 && (typecode
== TYPE_CODE_STRUCT
3015 || typecode
== TYPE_CODE_UNION
))
3016 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3020 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3022 phex (regval
, MIPS64_REGSIZE
));
3023 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3025 if (mips_n32n64_fp_arg_chunk_p (arg_type
,
3026 TYPE_LENGTH (arg_type
) - len
))
3029 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3031 phex (regval
, MIPS64_REGSIZE
));
3032 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3043 /* Compute the the offset into the stack at which we
3044 will copy the next parameter.
3046 In N32 (N64?), the stack_offset only needs to be
3047 adjusted when it has been used. */
3050 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3054 fprintf_unfiltered (gdb_stdlog
, "\n");
3057 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3059 /* Return adjusted stack pointer. */
3063 static enum return_value_convention
3064 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3065 struct type
*type
, struct regcache
*regcache
,
3066 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3068 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3069 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3070 || TYPE_CODE (type
) == TYPE_CODE_UNION
3071 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3072 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3073 return RETURN_VALUE_STRUCT_CONVENTION
;
3074 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3075 && TYPE_LENGTH (type
) == 16
3076 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3078 /* A 128-bit floating-point value fills both $f0 and $f2. The
3079 two registers are used in the same as memory order, so the
3080 eight bytes with the lower memory address are in $f0. */
3082 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3083 mips_xfer_register (regcache
,
3084 gdbarch_num_regs (current_gdbarch
)
3085 + mips_regnum (current_gdbarch
)->fp0
,
3086 8, gdbarch_byte_order (current_gdbarch
),
3087 readbuf
, writebuf
, 0);
3088 mips_xfer_register (regcache
,
3089 gdbarch_num_regs (current_gdbarch
)
3090 + mips_regnum (current_gdbarch
)->fp0
+ 2,
3091 8, gdbarch_byte_order (current_gdbarch
),
3092 readbuf
? readbuf
+ 8 : readbuf
,
3093 writebuf
? writebuf
+ 8 : writebuf
, 0);
3094 return RETURN_VALUE_REGISTER_CONVENTION
;
3096 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3097 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3099 /* A floating-point value belongs in the least significant part
3102 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3103 mips_xfer_register (regcache
,
3104 gdbarch_num_regs (current_gdbarch
)
3105 + mips_regnum (current_gdbarch
)->fp0
,
3107 gdbarch_byte_order (current_gdbarch
),
3108 readbuf
, writebuf
, 0);
3109 return RETURN_VALUE_REGISTER_CONVENTION
;
3111 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3112 && TYPE_NFIELDS (type
) <= 2
3113 && TYPE_NFIELDS (type
) >= 1
3114 && ((TYPE_NFIELDS (type
) == 1
3115 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3117 || (TYPE_NFIELDS (type
) == 2
3118 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3120 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3122 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3124 /* A struct that contains one or two floats. Each value is part
3125 in the least significant part of their floating point
3129 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3130 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3132 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3135 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3137 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3139 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3140 gdbarch_byte_order (current_gdbarch
),
3141 readbuf
, writebuf
, offset
);
3143 return RETURN_VALUE_REGISTER_CONVENTION
;
3145 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3146 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3148 /* A structure or union. Extract the left justified value,
3149 regardless of the byte order. I.e. DO NOT USE
3153 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3154 offset
< TYPE_LENGTH (type
);
3155 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3157 int xfer
= register_size (current_gdbarch
, regnum
);
3158 if (offset
+ xfer
> TYPE_LENGTH (type
))
3159 xfer
= TYPE_LENGTH (type
) - offset
;
3161 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3162 offset
, xfer
, regnum
);
3163 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3165 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3167 return RETURN_VALUE_REGISTER_CONVENTION
;
3171 /* A scalar extract each part but least-significant-byte
3175 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3176 offset
< TYPE_LENGTH (type
);
3177 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3179 int xfer
= register_size (current_gdbarch
, regnum
);
3180 if (offset
+ xfer
> TYPE_LENGTH (type
))
3181 xfer
= TYPE_LENGTH (type
) - offset
;
3183 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3184 offset
, xfer
, regnum
);
3185 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3187 gdbarch_byte_order (current_gdbarch
),
3188 readbuf
, writebuf
, offset
);
3190 return RETURN_VALUE_REGISTER_CONVENTION
;
3194 /* O32 ABI stuff. */
3197 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3198 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3199 int nargs
, struct value
**args
, CORE_ADDR sp
,
3200 int struct_return
, CORE_ADDR struct_addr
)
3206 int stack_offset
= 0;
3207 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3208 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3210 /* For shared libraries, "t9" needs to point at the function
3212 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3214 /* Set the return address register to point to the entry point of
3215 the program, where a breakpoint lies in wait. */
3216 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3218 /* First ensure that the stack and structure return address (if any)
3219 are properly aligned. The stack has to be at least 64-bit
3220 aligned even on 32-bit machines, because doubles must be 64-bit
3221 aligned. For n32 and n64, stack frames need to be 128-bit
3222 aligned, so we round to this widest known alignment. */
3224 sp
= align_down (sp
, 16);
3225 struct_addr
= align_down (struct_addr
, 16);
3227 /* Now make space on the stack for the args. */
3228 for (argnum
= 0; argnum
< nargs
; argnum
++)
3230 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3231 int arglen
= TYPE_LENGTH (arg_type
);
3233 /* Align to double-word if necessary. */
3234 if (mips_type_needs_double_align (arg_type
))
3235 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3236 /* Allocate space on the stack. */
3237 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3239 sp
-= align_up (len
, 16);
3242 fprintf_unfiltered (gdb_stdlog
,
3243 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3244 paddr_nz (sp
), (long) align_up (len
, 16));
3246 /* Initialize the integer and float register pointers. */
3247 argreg
= MIPS_A0_REGNUM
;
3248 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3250 /* The struct_return pointer occupies the first parameter-passing reg. */
3254 fprintf_unfiltered (gdb_stdlog
,
3255 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3256 argreg
, paddr_nz (struct_addr
));
3257 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3258 stack_offset
+= MIPS32_REGSIZE
;
3261 /* Now load as many as possible of the first arguments into
3262 registers, and push the rest onto the stack. Loop thru args
3263 from first to last. */
3264 for (argnum
= 0; argnum
< nargs
; argnum
++)
3266 const gdb_byte
*val
;
3267 struct value
*arg
= args
[argnum
];
3268 struct type
*arg_type
= check_typedef (value_type (arg
));
3269 int len
= TYPE_LENGTH (arg_type
);
3270 enum type_code typecode
= TYPE_CODE (arg_type
);
3273 fprintf_unfiltered (gdb_stdlog
,
3274 "mips_o32_push_dummy_call: %d len=%d type=%d",
3275 argnum
+ 1, len
, (int) typecode
);
3277 val
= value_contents (arg
);
3279 /* 32-bit ABIs always start floating point arguments in an
3280 even-numbered floating point register. Round the FP register
3281 up before the check to see if there are any FP registers
3282 left. O32/O64 targets also pass the FP in the integer
3283 registers so also round up normal registers. */
3284 if (fp_register_arg_p (typecode
, arg_type
))
3286 if ((float_argreg
& 1))
3290 /* Floating point arguments passed in registers have to be
3291 treated specially. On 32-bit architectures, doubles
3292 are passed in register pairs; the even register gets
3293 the low word, and the odd register gets the high word.
3294 On O32/O64, the first two floating point arguments are
3295 also copied to general registers, because MIPS16 functions
3296 don't use float registers for arguments. This duplication of
3297 arguments in general registers can't hurt non-MIPS16 functions
3298 because those registers are normally skipped. */
3300 if (fp_register_arg_p (typecode
, arg_type
)
3301 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3303 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3305 int low_offset
= gdbarch_byte_order (current_gdbarch
)
3306 == BFD_ENDIAN_BIG
? 4 : 0;
3307 unsigned long regval
;
3309 /* Write the low word of the double to the even register(s). */
3310 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3312 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3313 float_argreg
, phex (regval
, 4));
3314 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3316 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3317 argreg
, phex (regval
, 4));
3318 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3320 /* Write the high word of the double to the odd register(s). */
3321 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3323 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3324 float_argreg
, phex (regval
, 4));
3325 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3328 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3329 argreg
, phex (regval
, 4));
3330 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3334 /* This is a floating point value that fits entirely
3335 in a single register. */
3336 /* On 32 bit ABI's the float_argreg is further adjusted
3337 above to ensure that it is even register aligned. */
3338 LONGEST regval
= extract_unsigned_integer (val
, len
);
3340 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3341 float_argreg
, phex (regval
, len
));
3342 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3343 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3344 registers for each argument. The below is (my
3345 guess) to ensure that the corresponding integer
3346 register has reserved the same space. */
3348 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3349 argreg
, phex (regval
, len
));
3350 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3353 /* Reserve space for the FP register. */
3354 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3358 /* Copy the argument to general registers or the stack in
3359 register-sized pieces. Large arguments are split between
3360 registers and stack. */
3361 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3362 are treated specially: Irix cc passes
3363 them in registers where gcc sometimes puts them on the
3364 stack. For maximum compatibility, we will put them in
3366 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3367 && len
% MIPS32_REGSIZE
!= 0);
3368 /* Structures should be aligned to eight bytes (even arg registers)
3369 on MIPS_ABI_O32, if their first member has double precision. */
3370 if (mips_type_needs_double_align (arg_type
))
3375 stack_offset
+= MIPS32_REGSIZE
;
3380 /* Remember if the argument was written to the stack. */
3381 int stack_used_p
= 0;
3382 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3385 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3388 /* Write this portion of the argument to the stack. */
3389 if (argreg
> MIPS_LAST_ARG_REGNUM
3390 || odd_sized_struct
)
3392 /* Should shorter than int integer values be
3393 promoted to int before being stored? */
3394 int longword_offset
= 0;
3400 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3401 paddr_nz (stack_offset
));
3402 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3403 paddr_nz (longword_offset
));
3406 addr
= sp
+ stack_offset
+ longword_offset
;
3411 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3413 for (i
= 0; i
< partial_len
; i
++)
3415 fprintf_unfiltered (gdb_stdlog
, "%02x",
3419 write_memory (addr
, val
, partial_len
);
3422 /* Note!!! This is NOT an else clause. Odd sized
3423 structs may go thru BOTH paths. */
3424 /* Write this portion of the argument to a general
3425 purpose register. */
3426 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3428 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3429 /* Value may need to be sign extended, because
3430 mips_isa_regsize() != mips_abi_regsize(). */
3432 /* A non-floating-point argument being passed in a
3433 general register. If a struct or union, and if
3434 the remaining length is smaller than the register
3435 size, we have to adjust the register value on
3438 It does not seem to be necessary to do the
3439 same for integral types.
3441 Also don't do this adjustment on O64 binaries.
3443 cagney/2001-07-23: gdb/179: Also, GCC, when
3444 outputting LE O32 with sizeof (struct) <
3445 mips_abi_regsize(), generates a left shift
3446 as part of storing the argument in a register
3447 (the left shift isn't generated when
3448 sizeof (struct) >= mips_abi_regsize()). Since
3449 it is quite possible that this is GCC
3450 contradicting the LE/O32 ABI, GDB has not been
3451 adjusted to accommodate this. Either someone
3452 needs to demonstrate that the LE/O32 ABI
3453 specifies such a left shift OR this new ABI gets
3454 identified as such and GDB gets tweaked
3457 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3458 && partial_len
< MIPS32_REGSIZE
3459 && (typecode
== TYPE_CODE_STRUCT
3460 || typecode
== TYPE_CODE_UNION
))
3461 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3465 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3467 phex (regval
, MIPS32_REGSIZE
));
3468 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3471 /* Prevent subsequent floating point arguments from
3472 being passed in floating point registers. */
3473 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3479 /* Compute the the offset into the stack at which we
3480 will copy the next parameter.
3482 In older ABIs, the caller reserved space for
3483 registers that contained arguments. This was loosely
3484 refered to as their "home". Consequently, space is
3485 always allocated. */
3487 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3491 fprintf_unfiltered (gdb_stdlog
, "\n");
3494 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3496 /* Return adjusted stack pointer. */
3500 static enum return_value_convention
3501 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3502 struct regcache
*regcache
,
3503 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3507 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3508 || TYPE_CODE (type
) == TYPE_CODE_UNION
3509 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3510 return RETURN_VALUE_STRUCT_CONVENTION
;
3511 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3512 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3514 /* A single-precision floating-point value. It fits in the
3515 least significant part of FP0. */
3517 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3518 mips_xfer_register (regcache
,
3519 gdbarch_num_regs (current_gdbarch
)
3520 + mips_regnum (current_gdbarch
)->fp0
,
3522 gdbarch_byte_order (current_gdbarch
),
3523 readbuf
, writebuf
, 0);
3524 return RETURN_VALUE_REGISTER_CONVENTION
;
3526 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3527 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3529 /* A double-precision floating-point value. The most
3530 significant part goes in FP1, and the least significant in
3533 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3534 switch (gdbarch_byte_order (current_gdbarch
))
3536 case BFD_ENDIAN_LITTLE
:
3537 mips_xfer_register (regcache
,
3538 gdbarch_num_regs (current_gdbarch
)
3539 + mips_regnum (current_gdbarch
)->fp0
+
3540 0, 4, gdbarch_byte_order (current_gdbarch
),
3541 readbuf
, writebuf
, 0);
3542 mips_xfer_register (regcache
,
3543 gdbarch_num_regs (current_gdbarch
)
3544 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3545 4, gdbarch_byte_order (current_gdbarch
),
3546 readbuf
, writebuf
, 4);
3548 case BFD_ENDIAN_BIG
:
3549 mips_xfer_register (regcache
,
3550 gdbarch_num_regs (current_gdbarch
)
3551 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3552 4, gdbarch_byte_order (current_gdbarch
),
3553 readbuf
, writebuf
, 0);
3554 mips_xfer_register (regcache
,
3555 gdbarch_num_regs (current_gdbarch
)
3556 + mips_regnum (current_gdbarch
)->fp0
+ 0,
3557 4, gdbarch_byte_order (current_gdbarch
),
3558 readbuf
, writebuf
, 4);
3561 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3563 return RETURN_VALUE_REGISTER_CONVENTION
;
3566 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3567 && TYPE_NFIELDS (type
) <= 2
3568 && TYPE_NFIELDS (type
) >= 1
3569 && ((TYPE_NFIELDS (type
) == 1
3570 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3572 || (TYPE_NFIELDS (type
) == 2
3573 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3575 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3577 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3579 /* A struct that contains one or two floats. Each value is part
3580 in the least significant part of their floating point
3582 gdb_byte reg
[MAX_REGISTER_SIZE
];
3585 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3586 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3588 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3591 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3593 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3595 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3596 gdbarch_byte_order (current_gdbarch
),
3597 readbuf
, writebuf
, offset
);
3599 return RETURN_VALUE_REGISTER_CONVENTION
;
3603 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3604 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3606 /* A structure or union. Extract the left justified value,
3607 regardless of the byte order. I.e. DO NOT USE
3611 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3612 offset
< TYPE_LENGTH (type
);
3613 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3615 int xfer
= register_size (current_gdbarch
, regnum
);
3616 if (offset
+ xfer
> TYPE_LENGTH (type
))
3617 xfer
= TYPE_LENGTH (type
) - offset
;
3619 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3620 offset
, xfer
, regnum
);
3621 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3623 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3625 return RETURN_VALUE_REGISTER_CONVENTION
;
3630 /* A scalar extract each part but least-significant-byte
3631 justified. o32 thinks registers are 4 byte, regardless of
3635 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3636 offset
< TYPE_LENGTH (type
);
3637 offset
+= MIPS32_REGSIZE
, regnum
++)
3639 int xfer
= MIPS32_REGSIZE
;
3640 if (offset
+ xfer
> TYPE_LENGTH (type
))
3641 xfer
= TYPE_LENGTH (type
) - offset
;
3643 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3644 offset
, xfer
, regnum
);
3645 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3647 gdbarch_byte_order (current_gdbarch
),
3648 readbuf
, writebuf
, offset
);
3650 return RETURN_VALUE_REGISTER_CONVENTION
;
3654 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3658 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3659 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3661 struct value
**args
, CORE_ADDR sp
,
3662 int struct_return
, CORE_ADDR struct_addr
)
3668 int stack_offset
= 0;
3669 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3670 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3672 /* For shared libraries, "t9" needs to point at the function
3674 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3676 /* Set the return address register to point to the entry point of
3677 the program, where a breakpoint lies in wait. */
3678 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3680 /* First ensure that the stack and structure return address (if any)
3681 are properly aligned. The stack has to be at least 64-bit
3682 aligned even on 32-bit machines, because doubles must be 64-bit
3683 aligned. For n32 and n64, stack frames need to be 128-bit
3684 aligned, so we round to this widest known alignment. */
3686 sp
= align_down (sp
, 16);
3687 struct_addr
= align_down (struct_addr
, 16);
3689 /* Now make space on the stack for the args. */
3690 for (argnum
= 0; argnum
< nargs
; argnum
++)
3692 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3693 int arglen
= TYPE_LENGTH (arg_type
);
3695 /* Allocate space on the stack. */
3696 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3698 sp
-= align_up (len
, 16);
3701 fprintf_unfiltered (gdb_stdlog
,
3702 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3703 paddr_nz (sp
), (long) align_up (len
, 16));
3705 /* Initialize the integer and float register pointers. */
3706 argreg
= MIPS_A0_REGNUM
;
3707 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3709 /* The struct_return pointer occupies the first parameter-passing reg. */
3713 fprintf_unfiltered (gdb_stdlog
,
3714 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3715 argreg
, paddr_nz (struct_addr
));
3716 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3717 stack_offset
+= MIPS64_REGSIZE
;
3720 /* Now load as many as possible of the first arguments into
3721 registers, and push the rest onto the stack. Loop thru args
3722 from first to last. */
3723 for (argnum
= 0; argnum
< nargs
; argnum
++)
3725 const gdb_byte
*val
;
3726 struct value
*arg
= args
[argnum
];
3727 struct type
*arg_type
= check_typedef (value_type (arg
));
3728 int len
= TYPE_LENGTH (arg_type
);
3729 enum type_code typecode
= TYPE_CODE (arg_type
);
3732 fprintf_unfiltered (gdb_stdlog
,
3733 "mips_o64_push_dummy_call: %d len=%d type=%d",
3734 argnum
+ 1, len
, (int) typecode
);
3736 val
= value_contents (arg
);
3738 /* Floating point arguments passed in registers have to be
3739 treated specially. On 32-bit architectures, doubles
3740 are passed in register pairs; the even register gets
3741 the low word, and the odd register gets the high word.
3742 On O32/O64, the first two floating point arguments are
3743 also copied to general registers, because MIPS16 functions
3744 don't use float registers for arguments. This duplication of
3745 arguments in general registers can't hurt non-MIPS16 functions
3746 because those registers are normally skipped. */
3748 if (fp_register_arg_p (typecode
, arg_type
)
3749 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3751 LONGEST regval
= extract_unsigned_integer (val
, len
);
3753 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3754 float_argreg
, phex (regval
, len
));
3755 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3757 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3758 argreg
, phex (regval
, len
));
3759 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3761 /* Reserve space for the FP register. */
3762 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3766 /* Copy the argument to general registers or the stack in
3767 register-sized pieces. Large arguments are split between
3768 registers and stack. */
3769 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3770 are treated specially: Irix cc passes them in registers
3771 where gcc sometimes puts them on the stack. For maximum
3772 compatibility, we will put them in both places. */
3773 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3774 && len
% MIPS64_REGSIZE
!= 0);
3777 /* Remember if the argument was written to the stack. */
3778 int stack_used_p
= 0;
3779 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3782 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3785 /* Write this portion of the argument to the stack. */
3786 if (argreg
> MIPS_LAST_ARG_REGNUM
3787 || odd_sized_struct
)
3789 /* Should shorter than int integer values be
3790 promoted to int before being stored? */
3791 int longword_offset
= 0;
3794 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3796 if ((typecode
== TYPE_CODE_INT
3797 || typecode
== TYPE_CODE_PTR
3798 || typecode
== TYPE_CODE_FLT
)
3800 longword_offset
= MIPS64_REGSIZE
- len
;
3805 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3806 paddr_nz (stack_offset
));
3807 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3808 paddr_nz (longword_offset
));
3811 addr
= sp
+ stack_offset
+ longword_offset
;
3816 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3818 for (i
= 0; i
< partial_len
; i
++)
3820 fprintf_unfiltered (gdb_stdlog
, "%02x",
3824 write_memory (addr
, val
, partial_len
);
3827 /* Note!!! This is NOT an else clause. Odd sized
3828 structs may go thru BOTH paths. */
3829 /* Write this portion of the argument to a general
3830 purpose register. */
3831 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3833 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3834 /* Value may need to be sign extended, because
3835 mips_isa_regsize() != mips_abi_regsize(). */
3837 /* A non-floating-point argument being passed in a
3838 general register. If a struct or union, and if
3839 the remaining length is smaller than the register
3840 size, we have to adjust the register value on
3843 It does not seem to be necessary to do the
3844 same for integral types. */
3846 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3847 && partial_len
< MIPS64_REGSIZE
3848 && (typecode
== TYPE_CODE_STRUCT
3849 || typecode
== TYPE_CODE_UNION
))
3850 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3854 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3856 phex (regval
, MIPS64_REGSIZE
));
3857 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3860 /* Prevent subsequent floating point arguments from
3861 being passed in floating point registers. */
3862 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3868 /* Compute the the offset into the stack at which we
3869 will copy the next parameter.
3871 In older ABIs, the caller reserved space for
3872 registers that contained arguments. This was loosely
3873 refered to as their "home". Consequently, space is
3874 always allocated. */
3876 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3880 fprintf_unfiltered (gdb_stdlog
, "\n");
3883 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3885 /* Return adjusted stack pointer. */
3889 static enum return_value_convention
3890 mips_o64_return_value (struct gdbarch
*gdbarch
,
3891 struct type
*type
, struct regcache
*regcache
,
3892 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3894 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3896 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3897 || TYPE_CODE (type
) == TYPE_CODE_UNION
3898 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3899 return RETURN_VALUE_STRUCT_CONVENTION
;
3900 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3902 /* A floating-point value. It fits in the least significant
3905 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3906 mips_xfer_register (regcache
,
3907 gdbarch_num_regs (current_gdbarch
)
3908 + mips_regnum (current_gdbarch
)->fp0
,
3910 gdbarch_byte_order (current_gdbarch
),
3911 readbuf
, writebuf
, 0);
3912 return RETURN_VALUE_REGISTER_CONVENTION
;
3916 /* A scalar extract each part but least-significant-byte
3920 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3921 offset
< TYPE_LENGTH (type
);
3922 offset
+= MIPS64_REGSIZE
, regnum
++)
3924 int xfer
= MIPS64_REGSIZE
;
3925 if (offset
+ xfer
> TYPE_LENGTH (type
))
3926 xfer
= TYPE_LENGTH (type
) - offset
;
3928 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3929 offset
, xfer
, regnum
);
3930 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3932 gdbarch_byte_order (current_gdbarch
),
3933 readbuf
, writebuf
, offset
);
3935 return RETURN_VALUE_REGISTER_CONVENTION
;
3939 /* Floating point register management.
3941 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3942 64bit operations, these early MIPS cpus treat fp register pairs
3943 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3944 registers and offer a compatibility mode that emulates the MIPS2 fp
3945 model. When operating in MIPS2 fp compat mode, later cpu's split
3946 double precision floats into two 32-bit chunks and store them in
3947 consecutive fp regs. To display 64-bit floats stored in this
3948 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3949 Throw in user-configurable endianness and you have a real mess.
3951 The way this works is:
3952 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3953 double-precision value will be split across two logical registers.
3954 The lower-numbered logical register will hold the low-order bits,
3955 regardless of the processor's endianness.
3956 - If we are on a 64-bit processor, and we are looking for a
3957 single-precision value, it will be in the low ordered bits
3958 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3959 save slot in memory.
3960 - If we are in 64-bit mode, everything is straightforward.
3962 Note that this code only deals with "live" registers at the top of the
3963 stack. We will attempt to deal with saved registers later, when
3964 the raw/cooked register interface is in place. (We need a general
3965 interface that can deal with dynamic saved register sizes -- fp
3966 regs could be 32 bits wide in one frame and 64 on the frame above
3969 static struct type
*
3970 mips_float_register_type (void)
3972 return builtin_type_ieee_single
;
3975 static struct type
*
3976 mips_double_register_type (void)
3978 return builtin_type_ieee_double
;
3981 /* Copy a 32-bit single-precision value from the current frame
3982 into rare_buffer. */
3985 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
3986 gdb_byte
*rare_buffer
)
3988 int raw_size
= register_size (current_gdbarch
, regno
);
3989 gdb_byte
*raw_buffer
= alloca (raw_size
);
3991 if (!frame_register_read (frame
, regno
, raw_buffer
))
3992 error (_("can't read register %d (%s)"),
3993 regno
, gdbarch_register_name (current_gdbarch
, regno
));
3996 /* We have a 64-bit value for this register. Find the low-order
4000 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4005 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4009 memcpy (rare_buffer
, raw_buffer
, 4);
4013 /* Copy a 64-bit double-precision value from the current frame into
4014 rare_buffer. This may include getting half of it from the next
4018 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4019 gdb_byte
*rare_buffer
)
4021 int raw_size
= register_size (current_gdbarch
, regno
);
4023 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4025 /* We have a 64-bit value for this register, and we should use
4027 if (!frame_register_read (frame
, regno
, rare_buffer
))
4028 error (_("can't read register %d (%s)"),
4029 regno
, gdbarch_register_name (current_gdbarch
, regno
));
4033 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4034 internal_error (__FILE__
, __LINE__
,
4035 _("mips_read_fp_register_double: bad access to "
4036 "odd-numbered FP register"));
4038 /* mips_read_fp_register_single will find the correct 32 bits from
4040 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4042 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4043 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4047 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4048 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4054 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4056 { /* do values for FP (float) regs */
4057 gdb_byte
*raw_buffer
;
4058 double doub
, flt1
; /* doubles extracted from raw hex data */
4061 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
4062 mips_regnum (current_gdbarch
)->fp0
));
4064 fprintf_filtered (file
, "%s:",
4065 gdbarch_register_name (current_gdbarch
, regnum
));
4066 fprintf_filtered (file
, "%*s",
4067 4 - (int) strlen (gdbarch_register_name
4068 (current_gdbarch
, regnum
)),
4071 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4073 /* 4-byte registers: Print hex and floating. Also print even
4074 numbered registers as doubles. */
4075 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4076 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4078 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4081 fprintf_filtered (file
, " flt: ");
4083 fprintf_filtered (file
, " <invalid float> ");
4085 fprintf_filtered (file
, "%-17.9g", flt1
);
4087 if (regnum
% 2 == 0)
4089 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4090 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4093 fprintf_filtered (file
, " dbl: ");
4095 fprintf_filtered (file
, "<invalid double>");
4097 fprintf_filtered (file
, "%-24.17g", doub
);
4102 /* Eight byte registers: print each one as hex, float and double. */
4103 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4104 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4106 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4107 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4110 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4113 fprintf_filtered (file
, " flt: ");
4115 fprintf_filtered (file
, "<invalid float>");
4117 fprintf_filtered (file
, "%-17.9g", flt1
);
4119 fprintf_filtered (file
, " dbl: ");
4121 fprintf_filtered (file
, "<invalid double>");
4123 fprintf_filtered (file
, "%-24.17g", doub
);
4128 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4131 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4132 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4135 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4137 mips_print_fp_register (file
, frame
, regnum
);
4141 /* Get the data in raw format. */
4142 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4144 fprintf_filtered (file
, "%s: [Invalid]",
4145 gdbarch_register_name (current_gdbarch
, regnum
));
4149 fputs_filtered (gdbarch_register_name (current_gdbarch
, regnum
), file
);
4151 /* The problem with printing numeric register names (r26, etc.) is that
4152 the user can't use them on input. Probably the best solution is to
4153 fix it so that either the numeric or the funky (a2, etc.) names
4154 are accepted on input. */
4155 if (regnum
< MIPS_NUMREGS
)
4156 fprintf_filtered (file
, "(r%d): ", regnum
);
4158 fprintf_filtered (file
, ": ");
4160 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4162 register_size (current_gdbarch
,
4163 regnum
) - register_size (current_gdbarch
, regnum
);
4167 print_scalar_formatted (raw_buffer
+ offset
,
4168 register_type (gdbarch
, regnum
), 'x', 0,
4172 /* Replacement for generic do_registers_info.
4173 Print regs in pretty columns. */
4176 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4179 fprintf_filtered (file
, " ");
4180 mips_print_fp_register (file
, frame
, regnum
);
4181 fprintf_filtered (file
, "\n");
4186 /* Print a row's worth of GP (int) registers, with name labels above */
4189 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4192 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4193 /* do values for GP (int) regs */
4194 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4195 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4199 /* For GP registers, we print a separate row of names above the vals */
4200 for (col
= 0, regnum
= start_regnum
;
4201 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4202 + gdbarch_num_pseudo_regs (current_gdbarch
);
4205 if (*gdbarch_register_name (current_gdbarch
, regnum
) == '\0')
4206 continue; /* unused register */
4207 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4209 break; /* end the row: reached FP register */
4210 /* Large registers are handled separately. */
4211 if (register_size (current_gdbarch
, regnum
)
4212 > mips_abi_regsize (current_gdbarch
))
4215 break; /* End the row before this register. */
4217 /* Print this register on a row by itself. */
4218 mips_print_register (file
, frame
, regnum
);
4219 fprintf_filtered (file
, "\n");
4223 fprintf_filtered (file
, " ");
4224 fprintf_filtered (file
,
4225 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4226 gdbarch_register_name (current_gdbarch
, regnum
));
4233 /* print the R0 to R31 names */
4234 if ((start_regnum
% gdbarch_num_regs (current_gdbarch
)) < MIPS_NUMREGS
)
4235 fprintf_filtered (file
, "\n R%-4d",
4236 start_regnum
% gdbarch_num_regs (current_gdbarch
));
4238 fprintf_filtered (file
, "\n ");
4240 /* now print the values in hex, 4 or 8 to the row */
4241 for (col
= 0, regnum
= start_regnum
;
4242 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4243 + gdbarch_num_pseudo_regs (current_gdbarch
);
4246 if (*gdbarch_register_name (current_gdbarch
, regnum
) == '\0')
4247 continue; /* unused register */
4248 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4250 break; /* end row: reached FP register */
4251 if (register_size (current_gdbarch
, regnum
)
4252 > mips_abi_regsize (current_gdbarch
))
4253 break; /* End row: large register. */
4255 /* OK: get the data in raw format. */
4256 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4257 error (_("can't read register %d (%s)"),
4258 regnum
, gdbarch_register_name (current_gdbarch
, regnum
));
4259 /* pad small registers */
4261 byte
< (mips_abi_regsize (current_gdbarch
)
4262 - register_size (current_gdbarch
, regnum
)); byte
++)
4263 printf_filtered (" ");
4264 /* Now print the register value in hex, endian order. */
4265 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4267 register_size (current_gdbarch
,
4268 regnum
) - register_size (current_gdbarch
, regnum
);
4269 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4270 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4272 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4274 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4275 fprintf_filtered (file
, " ");
4278 if (col
> 0) /* ie. if we actually printed anything... */
4279 fprintf_filtered (file
, "\n");
4284 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4287 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4288 struct frame_info
*frame
, int regnum
, int all
)
4290 if (regnum
!= -1) /* do one specified register */
4292 gdb_assert (regnum
>= gdbarch_num_regs (current_gdbarch
));
4293 if (*(gdbarch_register_name (current_gdbarch
, regnum
)) == '\0')
4294 error (_("Not a valid register for the current processor type"));
4296 mips_print_register (file
, frame
, regnum
);
4297 fprintf_filtered (file
, "\n");
4300 /* do all (or most) registers */
4302 regnum
= gdbarch_num_regs (current_gdbarch
);
4303 while (regnum
< gdbarch_num_regs (current_gdbarch
)
4304 + gdbarch_num_pseudo_regs (current_gdbarch
))
4306 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4309 if (all
) /* true for "INFO ALL-REGISTERS" command */
4310 regnum
= print_fp_register_row (file
, frame
, regnum
);
4312 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4315 regnum
= print_gp_register_row (file
, frame
, regnum
);
4320 /* Is this a branch with a delay slot? */
4323 is_delayed (unsigned long insn
)
4326 for (i
= 0; i
< NUMOPCODES
; ++i
)
4327 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4328 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4330 return (i
< NUMOPCODES
4331 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4332 | INSN_COND_BRANCH_DELAY
4333 | INSN_COND_BRANCH_LIKELY
)));
4337 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4338 struct frame_info
*frame
)
4340 CORE_ADDR pc
= get_frame_pc (frame
);
4341 gdb_byte buf
[MIPS_INSN32_SIZE
];
4343 /* There is no branch delay slot on MIPS16. */
4344 if (mips_pc_is_mips16 (pc
))
4347 if (!breakpoint_here_p (pc
+ 4))
4350 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4351 /* If error reading memory, guess that it is not a delayed
4354 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4357 /* To skip prologues, I use this predicate. Returns either PC itself
4358 if the code at PC does not look like a function prologue; otherwise
4359 returns an address that (if we're lucky) follows the prologue. If
4360 LENIENT, then we must skip everything which is involved in setting
4361 up the frame (it's OK to skip more, just so long as we don't skip
4362 anything which might clobber the registers which are being saved.
4363 We must skip more in the case where part of the prologue is in the
4364 delay slot of a non-prologue instruction). */
4367 mips_skip_prologue (CORE_ADDR pc
)
4370 CORE_ADDR func_addr
;
4372 /* See if we can determine the end of the prologue via the symbol table.
4373 If so, then return either PC, or the PC after the prologue, whichever
4375 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4377 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4378 if (post_prologue_pc
!= 0)
4379 return max (pc
, post_prologue_pc
);
4382 /* Can't determine prologue from the symbol table, need to examine
4385 /* Find an upper limit on the function prologue using the debug
4386 information. If the debug information could not be used to provide
4387 that bound, then use an arbitrary large number as the upper bound. */
4388 limit_pc
= skip_prologue_using_sal (pc
);
4390 limit_pc
= pc
+ 100; /* Magic. */
4392 if (mips_pc_is_mips16 (pc
))
4393 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4395 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4398 /* Root of all "set mips "/"show mips " commands. This will eventually be
4399 used for all MIPS-specific commands. */
4402 show_mips_command (char *args
, int from_tty
)
4404 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4408 set_mips_command (char *args
, int from_tty
)
4411 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4412 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4415 /* Commands to show/set the MIPS FPU type. */
4418 show_mipsfpu_command (char *args
, int from_tty
)
4421 switch (MIPS_FPU_TYPE
)
4423 case MIPS_FPU_SINGLE
:
4424 fpu
= "single-precision";
4426 case MIPS_FPU_DOUBLE
:
4427 fpu
= "double-precision";
4430 fpu
= "absent (none)";
4433 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4435 if (mips_fpu_type_auto
)
4437 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4441 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4446 set_mipsfpu_command (char *args
, int from_tty
)
4449 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4450 show_mipsfpu_command (args
, from_tty
);
4454 set_mipsfpu_single_command (char *args
, int from_tty
)
4456 struct gdbarch_info info
;
4457 gdbarch_info_init (&info
);
4458 mips_fpu_type
= MIPS_FPU_SINGLE
;
4459 mips_fpu_type_auto
= 0;
4460 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4461 instead of relying on globals. Doing that would let generic code
4462 handle the search for this specific architecture. */
4463 if (!gdbarch_update_p (info
))
4464 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4468 set_mipsfpu_double_command (char *args
, int from_tty
)
4470 struct gdbarch_info info
;
4471 gdbarch_info_init (&info
);
4472 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4473 mips_fpu_type_auto
= 0;
4474 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4475 instead of relying on globals. Doing that would let generic code
4476 handle the search for this specific architecture. */
4477 if (!gdbarch_update_p (info
))
4478 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4482 set_mipsfpu_none_command (char *args
, int from_tty
)
4484 struct gdbarch_info info
;
4485 gdbarch_info_init (&info
);
4486 mips_fpu_type
= MIPS_FPU_NONE
;
4487 mips_fpu_type_auto
= 0;
4488 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4489 instead of relying on globals. Doing that would let generic code
4490 handle the search for this specific architecture. */
4491 if (!gdbarch_update_p (info
))
4492 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4496 set_mipsfpu_auto_command (char *args
, int from_tty
)
4498 mips_fpu_type_auto
= 1;
4501 /* Attempt to identify the particular processor model by reading the
4502 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4503 the relevant processor still exists (it dates back to '94) and
4504 secondly this is not the way to do this. The processor type should
4505 be set by forcing an architecture change. */
4508 deprecated_mips_set_processor_regs_hack (void)
4510 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4513 regcache_cooked_read_unsigned (get_current_regcache (),
4514 MIPS_PRID_REGNUM
, &prid
);
4515 if ((prid
& ~0xf) == 0x700)
4516 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4519 /* Just like reinit_frame_cache, but with the right arguments to be
4520 callable as an sfunc. */
4523 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4524 struct cmd_list_element
*c
)
4526 reinit_frame_cache ();
4530 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4532 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4534 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4535 disassembler needs to be able to locally determine the ISA, and
4536 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4538 if (mips_pc_is_mips16 (memaddr
))
4539 info
->mach
= bfd_mach_mips16
;
4541 /* Round down the instruction address to the appropriate boundary. */
4542 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4544 /* Set the disassembler options. */
4545 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4547 /* Set up the disassembler info, so that we get the right
4548 register names from libopcodes. */
4549 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4550 info
->disassembler_options
= "gpr-names=n32";
4552 info
->disassembler_options
= "gpr-names=64";
4553 info
->flavour
= bfd_target_elf_flavour
;
4556 /* This string is not recognized explicitly by the disassembler,
4557 but it tells the disassembler to not try to guess the ABI from
4558 the bfd elf headers, such that, if the user overrides the ABI
4559 of a program linked as NewABI, the disassembly will follow the
4560 register naming conventions specified by the user. */
4561 info
->disassembler_options
= "gpr-names=32";
4563 /* Call the appropriate disassembler based on the target endian-ness. */
4564 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4565 return print_insn_big_mips (memaddr
, info
);
4567 return print_insn_little_mips (memaddr
, info
);
4570 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4571 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4572 It returns a pointer to a string of bytes that encode a breakpoint
4573 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4574 necessary) to point to the actual memory location where the breakpoint
4575 should be inserted. */
4577 static const gdb_byte
*
4578 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4580 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4582 if (mips_pc_is_mips16 (*pcptr
))
4584 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4585 *pcptr
= unmake_mips16_addr (*pcptr
);
4586 *lenptr
= sizeof (mips16_big_breakpoint
);
4587 return mips16_big_breakpoint
;
4591 /* The IDT board uses an unusual breakpoint value, and
4592 sometimes gets confused when it sees the usual MIPS
4593 breakpoint instruction. */
4594 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4595 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4596 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4598 *lenptr
= sizeof (big_breakpoint
);
4600 if (strcmp (target_shortname
, "mips") == 0)
4601 return idt_big_breakpoint
;
4602 else if (strcmp (target_shortname
, "ddb") == 0
4603 || strcmp (target_shortname
, "pmon") == 0
4604 || strcmp (target_shortname
, "lsi") == 0)
4605 return pmon_big_breakpoint
;
4607 return big_breakpoint
;
4612 if (mips_pc_is_mips16 (*pcptr
))
4614 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4615 *pcptr
= unmake_mips16_addr (*pcptr
);
4616 *lenptr
= sizeof (mips16_little_breakpoint
);
4617 return mips16_little_breakpoint
;
4621 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4622 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4623 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4625 *lenptr
= sizeof (little_breakpoint
);
4627 if (strcmp (target_shortname
, "mips") == 0)
4628 return idt_little_breakpoint
;
4629 else if (strcmp (target_shortname
, "ddb") == 0
4630 || strcmp (target_shortname
, "pmon") == 0
4631 || strcmp (target_shortname
, "lsi") == 0)
4632 return pmon_little_breakpoint
;
4634 return little_breakpoint
;
4639 /* If PC is in a mips16 call or return stub, return the address of the target
4640 PC, which is either the callee or the caller. There are several
4641 cases which must be handled:
4643 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4644 target PC is in $31 ($ra).
4645 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4646 and the target PC is in $2.
4647 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4648 before the jal instruction, this is effectively a call stub
4649 and the the target PC is in $2. Otherwise this is effectively
4650 a return stub and the target PC is in $18.
4652 See the source code for the stubs in gcc/config/mips/mips16.S for
4656 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
4659 CORE_ADDR start_addr
;
4661 /* Find the starting address and name of the function containing the PC. */
4662 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4665 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4666 target PC is in $31 ($ra). */
4667 if (strcmp (name
, "__mips16_ret_sf") == 0
4668 || strcmp (name
, "__mips16_ret_df") == 0)
4669 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
4671 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4673 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4674 and the target PC is in $2. */
4675 if (name
[19] >= '0' && name
[19] <= '9')
4676 return get_frame_register_signed (frame
, 2);
4678 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4679 before the jal instruction, this is effectively a call stub
4680 and the the target PC is in $2. Otherwise this is effectively
4681 a return stub and the target PC is in $18. */
4682 else if (name
[19] == 's' || name
[19] == 'd')
4684 if (pc
== start_addr
)
4686 /* Check if the target of the stub is a compiler-generated
4687 stub. Such a stub for a function bar might have a name
4688 like __fn_stub_bar, and might look like this:
4693 la $1,bar (becomes a lui/addiu pair)
4695 So scan down to the lui/addi and extract the target
4696 address from those two instructions. */
4698 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
4702 /* See if the name of the target function is __fn_stub_*. */
4703 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4706 if (strncmp (name
, "__fn_stub_", 10) != 0
4707 && strcmp (name
, "etext") != 0
4708 && strcmp (name
, "_etext") != 0)
4711 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4712 The limit on the search is arbitrarily set to 20
4713 instructions. FIXME. */
4714 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4716 inst
= mips_fetch_instruction (target_pc
);
4717 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4718 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4719 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4720 return pc
| (inst
& 0xffff); /* low word */
4723 /* Couldn't find the lui/addui pair, so return stub address. */
4727 /* This is the 'return' part of a call stub. The return
4728 address is in $r18. */
4729 return get_frame_register_signed (frame
, 18);
4732 return 0; /* not a stub */
4735 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4736 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4739 mips_stab_reg_to_regnum (int num
)
4742 if (num
>= 0 && num
< 32)
4744 else if (num
>= 38 && num
< 70)
4745 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4747 regnum
= mips_regnum (current_gdbarch
)->hi
;
4749 regnum
= mips_regnum (current_gdbarch
)->lo
;
4751 /* This will hopefully (eventually) provoke a warning. Should
4752 we be calling complaint() here? */
4753 return gdbarch_num_regs (current_gdbarch
)
4754 + gdbarch_num_pseudo_regs (current_gdbarch
);
4755 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4759 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4760 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4763 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4766 if (num
>= 0 && num
< 32)
4768 else if (num
>= 32 && num
< 64)
4769 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4771 regnum
= mips_regnum (current_gdbarch
)->hi
;
4773 regnum
= mips_regnum (current_gdbarch
)->lo
;
4775 /* This will hopefully (eventually) provoke a warning. Should we
4776 be calling complaint() here? */
4777 return gdbarch_num_regs (current_gdbarch
)
4778 + gdbarch_num_pseudo_regs (current_gdbarch
);
4779 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4783 mips_register_sim_regno (int regnum
)
4785 /* Only makes sense to supply raw registers. */
4786 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
));
4787 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4788 decide if it is valid. Should instead define a standard sim/gdb
4789 register numbering scheme. */
4790 if (gdbarch_register_name (current_gdbarch
,
4792 (current_gdbarch
) + regnum
) != NULL
4793 && gdbarch_register_name (current_gdbarch
,
4795 (current_gdbarch
) + regnum
)[0] != '\0')
4798 return LEGACY_SIM_REGNO_IGNORE
;
4802 /* Convert an integer into an address. Extracting the value signed
4803 guarantees a correctly sign extended address. */
4806 mips_integer_to_address (struct gdbarch
*gdbarch
,
4807 struct type
*type
, const gdb_byte
*buf
)
4809 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4813 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4815 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4816 const char *name
= bfd_get_section_name (abfd
, sect
);
4818 if (*abip
!= MIPS_ABI_UNKNOWN
)
4821 if (strncmp (name
, ".mdebug.", 8) != 0)
4824 if (strcmp (name
, ".mdebug.abi32") == 0)
4825 *abip
= MIPS_ABI_O32
;
4826 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4827 *abip
= MIPS_ABI_N32
;
4828 else if (strcmp (name
, ".mdebug.abi64") == 0)
4829 *abip
= MIPS_ABI_N64
;
4830 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4831 *abip
= MIPS_ABI_O64
;
4832 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4833 *abip
= MIPS_ABI_EABI32
;
4834 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4835 *abip
= MIPS_ABI_EABI64
;
4837 warning (_("unsupported ABI %s."), name
+ 8);
4841 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4843 int *lbp
= (int *) obj
;
4844 const char *name
= bfd_get_section_name (abfd
, sect
);
4846 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4848 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4850 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4851 warning (_("unrecognized .gcc_compiled_longXX"));
4854 static enum mips_abi
4855 global_mips_abi (void)
4859 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4860 if (mips_abi_strings
[i
] == mips_abi_string
)
4861 return (enum mips_abi
) i
;
4863 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4867 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4869 static struct target_desc
*tdesc_gp32
, *tdesc_gp64
;
4871 if (tdesc_gp32
== NULL
)
4873 /* Create feature sets with the appropriate properties. The values
4874 are not important. */
4876 tdesc_gp32
= allocate_target_description ();
4877 set_tdesc_property (tdesc_gp32
, PROPERTY_GP32
, "");
4879 tdesc_gp64
= allocate_target_description ();
4880 set_tdesc_property (tdesc_gp64
, PROPERTY_GP64
, "");
4883 /* If the size matches the set of 32-bit or 64-bit integer registers,
4884 assume that's what we've got. */
4885 register_remote_g_packet_guess (gdbarch
, 38 * 4, tdesc_gp32
);
4886 register_remote_g_packet_guess (gdbarch
, 38 * 8, tdesc_gp64
);
4888 /* If the size matches the full set of registers GDB traditionally
4889 knows about, including floating point, for either 32-bit or
4890 64-bit, assume that's what we've got. */
4891 register_remote_g_packet_guess (gdbarch
, 90 * 4, tdesc_gp32
);
4892 register_remote_g_packet_guess (gdbarch
, 90 * 8, tdesc_gp64
);
4894 /* Otherwise we don't have a useful guess. */
4897 static struct value
*
4898 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
4900 const int *reg_p
= baton
;
4901 return value_of_register (*reg_p
, frame
);
4904 static struct gdbarch
*
4905 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4907 struct gdbarch
*gdbarch
;
4908 struct gdbarch_tdep
*tdep
;
4910 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
4912 enum mips_fpu_type fpu_type
;
4913 struct tdesc_arch_data
*tdesc_data
= NULL
;
4914 int elf_fpu_type
= 0;
4916 /* Check any target description for validity. */
4917 if (tdesc_has_registers (info
.target_desc
))
4919 static const char *const mips_gprs
[] = {
4920 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4921 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4922 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4923 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4925 static const char *const mips_fprs
[] = {
4926 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
4927 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
4928 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
4929 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
4932 const struct tdesc_feature
*feature
;
4935 feature
= tdesc_find_feature (info
.target_desc
,
4936 "org.gnu.gdb.mips.cpu");
4937 if (feature
== NULL
)
4940 tdesc_data
= tdesc_data_alloc ();
4943 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
4944 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
4948 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4949 MIPS_EMBED_LO_REGNUM
, "lo");
4950 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4951 MIPS_EMBED_HI_REGNUM
, "hi");
4952 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4953 MIPS_EMBED_PC_REGNUM
, "pc");
4957 tdesc_data_cleanup (tdesc_data
);
4961 feature
= tdesc_find_feature (info
.target_desc
,
4962 "org.gnu.gdb.mips.cp0");
4963 if (feature
== NULL
)
4965 tdesc_data_cleanup (tdesc_data
);
4970 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4971 MIPS_EMBED_BADVADDR_REGNUM
,
4973 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4974 MIPS_PS_REGNUM
, "status");
4975 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4976 MIPS_EMBED_CAUSE_REGNUM
, "cause");
4980 tdesc_data_cleanup (tdesc_data
);
4984 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
4985 backend is not prepared for that, though. */
4986 feature
= tdesc_find_feature (info
.target_desc
,
4987 "org.gnu.gdb.mips.fpu");
4988 if (feature
== NULL
)
4990 tdesc_data_cleanup (tdesc_data
);
4995 for (i
= 0; i
< 32; i
++)
4996 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
4997 i
+ MIPS_EMBED_FP0_REGNUM
,
5000 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5001 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5002 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5003 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5007 tdesc_data_cleanup (tdesc_data
);
5011 /* It would be nice to detect an attempt to use a 64-bit ABI
5012 when only 32-bit registers are provided. */
5015 /* First of all, extract the elf_flags, if available. */
5016 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5017 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5018 else if (arches
!= NULL
)
5019 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5023 fprintf_unfiltered (gdb_stdlog
,
5024 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5026 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5027 switch ((elf_flags
& EF_MIPS_ABI
))
5029 case E_MIPS_ABI_O32
:
5030 found_abi
= MIPS_ABI_O32
;
5032 case E_MIPS_ABI_O64
:
5033 found_abi
= MIPS_ABI_O64
;
5035 case E_MIPS_ABI_EABI32
:
5036 found_abi
= MIPS_ABI_EABI32
;
5038 case E_MIPS_ABI_EABI64
:
5039 found_abi
= MIPS_ABI_EABI64
;
5042 if ((elf_flags
& EF_MIPS_ABI2
))
5043 found_abi
= MIPS_ABI_N32
;
5045 found_abi
= MIPS_ABI_UNKNOWN
;
5049 /* GCC creates a pseudo-section whose name describes the ABI. */
5050 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5051 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5053 /* If we have no useful BFD information, use the ABI from the last
5054 MIPS architecture (if there is one). */
5055 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5056 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5058 /* Try the architecture for any hint of the correct ABI. */
5059 if (found_abi
== MIPS_ABI_UNKNOWN
5060 && info
.bfd_arch_info
!= NULL
5061 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5063 switch (info
.bfd_arch_info
->mach
)
5065 case bfd_mach_mips3900
:
5066 found_abi
= MIPS_ABI_EABI32
;
5068 case bfd_mach_mips4100
:
5069 case bfd_mach_mips5000
:
5070 found_abi
= MIPS_ABI_EABI64
;
5072 case bfd_mach_mips8000
:
5073 case bfd_mach_mips10000
:
5074 /* On Irix, ELF64 executables use the N64 ABI. The
5075 pseudo-sections which describe the ABI aren't present
5076 on IRIX. (Even for executables created by gcc.) */
5077 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5078 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5079 found_abi
= MIPS_ABI_N64
;
5081 found_abi
= MIPS_ABI_N32
;
5086 /* Default 64-bit objects to N64 instead of O32. */
5087 if (found_abi
== MIPS_ABI_UNKNOWN
5088 && info
.abfd
!= NULL
5089 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5090 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5091 found_abi
= MIPS_ABI_N64
;
5094 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5097 /* What has the user specified from the command line? */
5098 wanted_abi
= global_mips_abi ();
5100 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5103 /* Now that we have found what the ABI for this binary would be,
5104 check whether the user is overriding it. */
5105 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5106 mips_abi
= wanted_abi
;
5107 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5108 mips_abi
= found_abi
;
5110 mips_abi
= MIPS_ABI_O32
;
5112 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5115 /* Also used when doing an architecture lookup. */
5117 fprintf_unfiltered (gdb_stdlog
,
5118 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5119 mips64_transfers_32bit_regs_p
);
5121 /* Determine the MIPS FPU type. */
5124 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5125 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5126 Tag_GNU_MIPS_ABI_FP
);
5127 #endif /* HAVE_ELF */
5129 if (!mips_fpu_type_auto
)
5130 fpu_type
= mips_fpu_type
;
5131 else if (elf_fpu_type
!= 0)
5133 switch (elf_fpu_type
)
5136 fpu_type
= MIPS_FPU_DOUBLE
;
5139 fpu_type
= MIPS_FPU_SINGLE
;
5143 /* Soft float or unknown. */
5144 fpu_type
= MIPS_FPU_NONE
;
5148 else if (info
.bfd_arch_info
!= NULL
5149 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5150 switch (info
.bfd_arch_info
->mach
)
5152 case bfd_mach_mips3900
:
5153 case bfd_mach_mips4100
:
5154 case bfd_mach_mips4111
:
5155 case bfd_mach_mips4120
:
5156 fpu_type
= MIPS_FPU_NONE
;
5158 case bfd_mach_mips4650
:
5159 fpu_type
= MIPS_FPU_SINGLE
;
5162 fpu_type
= MIPS_FPU_DOUBLE
;
5165 else if (arches
!= NULL
)
5166 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5168 fpu_type
= MIPS_FPU_DOUBLE
;
5170 fprintf_unfiltered (gdb_stdlog
,
5171 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5173 /* Check for blatant incompatibilities. */
5175 /* If we have only 32-bit registers, then we can't debug a 64-bit
5177 if (info
.target_desc
5178 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5179 && mips_abi
!= MIPS_ABI_EABI32
5180 && mips_abi
!= MIPS_ABI_O32
)
5182 if (tdesc_data
!= NULL
)
5183 tdesc_data_cleanup (tdesc_data
);
5187 /* try to find a pre-existing architecture */
5188 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5190 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5192 /* MIPS needs to be pedantic about which ABI the object is
5194 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5196 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5198 /* Need to be pedantic about which register virtual size is
5200 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5201 != mips64_transfers_32bit_regs_p
)
5203 /* Be pedantic about which FPU is selected. */
5204 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5207 if (tdesc_data
!= NULL
)
5208 tdesc_data_cleanup (tdesc_data
);
5209 return arches
->gdbarch
;
5212 /* Need a new architecture. Fill in a target specific vector. */
5213 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5214 gdbarch
= gdbarch_alloc (&info
, tdep
);
5215 tdep
->elf_flags
= elf_flags
;
5216 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5217 tdep
->found_abi
= found_abi
;
5218 tdep
->mips_abi
= mips_abi
;
5219 tdep
->mips_fpu_type
= fpu_type
;
5220 tdep
->register_size_valid_p
= 0;
5221 tdep
->register_size
= 0;
5223 if (info
.target_desc
)
5225 /* Some useful properties can be inferred from the target. */
5226 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5228 tdep
->register_size_valid_p
= 1;
5229 tdep
->register_size
= 4;
5231 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5233 tdep
->register_size_valid_p
= 1;
5234 tdep
->register_size
= 8;
5238 /* Initially set everything according to the default ABI/ISA. */
5239 set_gdbarch_short_bit (gdbarch
, 16);
5240 set_gdbarch_int_bit (gdbarch
, 32);
5241 set_gdbarch_float_bit (gdbarch
, 32);
5242 set_gdbarch_double_bit (gdbarch
, 64);
5243 set_gdbarch_long_double_bit (gdbarch
, 64);
5244 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5245 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5246 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5248 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5249 mips_elf_make_msymbol_special
);
5251 /* Fill in the OS dependant register numbers and names. */
5253 const char **reg_names
;
5254 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5255 struct mips_regnum
);
5256 if (tdesc_has_registers (info
.target_desc
))
5258 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5259 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5260 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5261 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5262 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5263 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5264 regnum
->fp_control_status
= 70;
5265 regnum
->fp_implementation_revision
= 71;
5266 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5269 else if (info
.osabi
== GDB_OSABI_IRIX
)
5274 regnum
->badvaddr
= 66;
5277 regnum
->fp_control_status
= 69;
5278 regnum
->fp_implementation_revision
= 70;
5280 reg_names
= mips_irix_reg_names
;
5284 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5285 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5286 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5287 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5288 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5289 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5290 regnum
->fp_control_status
= 70;
5291 regnum
->fp_implementation_revision
= 71;
5293 if (info
.bfd_arch_info
!= NULL
5294 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5295 reg_names
= mips_tx39_reg_names
;
5297 reg_names
= mips_generic_reg_names
;
5299 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5300 replaced by read_pc? */
5301 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5302 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5303 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5304 set_gdbarch_num_regs (gdbarch
, num_regs
);
5305 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5306 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5307 tdep
->mips_processor_reg_names
= reg_names
;
5308 tdep
->regnum
= regnum
;
5314 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5315 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5316 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5317 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5318 tdep
->default_mask_address_p
= 0;
5319 set_gdbarch_long_bit (gdbarch
, 32);
5320 set_gdbarch_ptr_bit (gdbarch
, 32);
5321 set_gdbarch_long_long_bit (gdbarch
, 64);
5324 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5325 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5326 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5327 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5328 tdep
->default_mask_address_p
= 0;
5329 set_gdbarch_long_bit (gdbarch
, 32);
5330 set_gdbarch_ptr_bit (gdbarch
, 32);
5331 set_gdbarch_long_long_bit (gdbarch
, 64);
5333 case MIPS_ABI_EABI32
:
5334 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5335 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5336 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5337 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5338 tdep
->default_mask_address_p
= 0;
5339 set_gdbarch_long_bit (gdbarch
, 32);
5340 set_gdbarch_ptr_bit (gdbarch
, 32);
5341 set_gdbarch_long_long_bit (gdbarch
, 64);
5343 case MIPS_ABI_EABI64
:
5344 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5345 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5346 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5347 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5348 tdep
->default_mask_address_p
= 0;
5349 set_gdbarch_long_bit (gdbarch
, 64);
5350 set_gdbarch_ptr_bit (gdbarch
, 64);
5351 set_gdbarch_long_long_bit (gdbarch
, 64);
5354 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5355 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5356 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5357 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5358 tdep
->default_mask_address_p
= 0;
5359 set_gdbarch_long_bit (gdbarch
, 32);
5360 set_gdbarch_ptr_bit (gdbarch
, 32);
5361 set_gdbarch_long_long_bit (gdbarch
, 64);
5362 set_gdbarch_long_double_bit (gdbarch
, 128);
5363 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5366 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5367 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5368 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5369 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5370 tdep
->default_mask_address_p
= 0;
5371 set_gdbarch_long_bit (gdbarch
, 64);
5372 set_gdbarch_ptr_bit (gdbarch
, 64);
5373 set_gdbarch_long_long_bit (gdbarch
, 64);
5374 set_gdbarch_long_double_bit (gdbarch
, 128);
5375 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5378 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5381 /* GCC creates a pseudo-section whose name specifies the size of
5382 longs, since -mlong32 or -mlong64 may be used independent of
5383 other options. How those options affect pointer sizes is ABI and
5384 architecture dependent, so use them to override the default sizes
5385 set by the ABI. This table shows the relationship between ABI,
5386 -mlongXX, and size of pointers:
5388 ABI -mlongXX ptr bits
5389 --- -------- --------
5403 Note that for o32 and eabi32, pointers are always 32 bits
5404 regardless of any -mlongXX option. For all others, pointers and
5405 longs are the same, as set by -mlongXX or set by defaults.
5408 if (info
.abfd
!= NULL
)
5412 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5415 set_gdbarch_long_bit (gdbarch
, long_bit
);
5419 case MIPS_ABI_EABI32
:
5424 case MIPS_ABI_EABI64
:
5425 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5428 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5433 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5434 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5437 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5438 flag in object files because to do so would make it impossible to
5439 link with libraries compiled without "-gp32". This is
5440 unnecessarily restrictive.
5442 We could solve this problem by adding "-gp32" multilibs to gcc,
5443 but to set this flag before gcc is built with such multilibs will
5444 break too many systems.''
5446 But even more unhelpfully, the default linker output target for
5447 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5448 for 64-bit programs - you need to change the ABI to change this,
5449 and not all gcc targets support that currently. Therefore using
5450 this flag to detect 32-bit mode would do the wrong thing given
5451 the current gcc - it would make GDB treat these 64-bit programs
5452 as 32-bit programs by default. */
5454 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5455 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5457 /* Add/remove bits from an address. The MIPS needs be careful to
5458 ensure that all 32 bit addresses are sign extended to 64 bits. */
5459 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5461 /* Unwind the frame. */
5462 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5463 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5464 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5466 /* Map debug register numbers onto internal register numbers. */
5467 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5468 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5469 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5470 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5471 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5472 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5473 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5474 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5476 /* MIPS version of CALL_DUMMY */
5478 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5479 replaced by a command, and all targets will default to on stack
5480 (regardless of the stack's execute status). */
5481 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5482 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5484 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5485 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5486 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5488 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5489 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5491 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5493 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5494 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5495 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5497 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5499 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5501 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5503 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5504 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5505 need to all be folded into the target vector. Since they are
5506 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5507 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5509 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5511 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5513 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5515 /* Virtual tables. */
5516 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5518 mips_register_g_packet_guesses (gdbarch
);
5520 /* Hook in OS ABI-specific overrides, if they have been registered. */
5521 info
.tdep_info
= (void *) tdesc_data
;
5522 gdbarch_init_osabi (info
, gdbarch
);
5524 /* Unwind the frame. */
5525 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5526 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5527 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5528 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5529 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5530 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5531 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5532 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5536 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5537 tdesc_use_registers (gdbarch
, tdesc_data
);
5539 /* Override the normal target description methods to handle our
5540 dual real and pseudo registers. */
5541 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5542 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5544 num_regs
= gdbarch_num_regs (gdbarch
);
5545 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5546 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5547 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5550 /* Add ABI-specific aliases for the registers. */
5551 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5552 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5553 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5554 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5556 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5557 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5558 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5560 /* Add some other standard aliases. */
5561 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5562 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5563 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5569 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5571 struct gdbarch_info info
;
5573 /* Force the architecture to update, and (if it's a MIPS architecture)
5574 mips_gdbarch_init will take care of the rest. */
5575 gdbarch_info_init (&info
);
5576 gdbarch_update_p (info
);
5579 /* Print out which MIPS ABI is in use. */
5582 show_mips_abi (struct ui_file
*file
,
5584 struct cmd_list_element
*ignored_cmd
,
5585 const char *ignored_value
)
5587 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5590 "The MIPS ABI is unknown because the current architecture "
5594 enum mips_abi global_abi
= global_mips_abi ();
5595 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5596 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5598 if (global_abi
== MIPS_ABI_UNKNOWN
)
5601 "The MIPS ABI is set automatically (currently \"%s\").\n",
5603 else if (global_abi
== actual_abi
)
5606 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5610 /* Probably shouldn't happen... */
5613 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5614 actual_abi_str
, mips_abi_strings
[global_abi
]);
5620 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5622 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5626 int ef_mips_32bitmode
;
5627 /* Determine the ISA. */
5628 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5646 /* Determine the size of a pointer. */
5647 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5648 fprintf_unfiltered (file
,
5649 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5651 fprintf_unfiltered (file
,
5652 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5654 fprintf_unfiltered (file
,
5655 "mips_dump_tdep: ef_mips_arch = %d\n",
5657 fprintf_unfiltered (file
,
5658 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5659 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5660 fprintf_unfiltered (file
,
5661 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5662 mips_mask_address_p (tdep
),
5663 tdep
->default_mask_address_p
);
5665 fprintf_unfiltered (file
,
5666 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5667 MIPS_DEFAULT_FPU_TYPE
,
5668 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5669 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5670 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5672 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5673 fprintf_unfiltered (file
,
5674 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5676 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5677 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5678 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5682 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5685 _initialize_mips_tdep (void)
5687 static struct cmd_list_element
*mipsfpulist
= NULL
;
5688 struct cmd_list_element
*c
;
5690 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5691 if (MIPS_ABI_LAST
+ 1
5692 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5693 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5695 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5697 mips_pdr_data
= register_objfile_data ();
5699 /* Add root prefix command for all "set mips"/"show mips" commands */
5700 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5701 _("Various MIPS specific commands."),
5702 &setmipscmdlist
, "set mips ", 0, &setlist
);
5704 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5705 _("Various MIPS specific commands."),
5706 &showmipscmdlist
, "show mips ", 0, &showlist
);
5708 /* Allow the user to override the ABI. */
5709 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5710 &mips_abi_string
, _("\
5711 Set the MIPS ABI used by this program."), _("\
5712 Show the MIPS ABI used by this program."), _("\
5713 This option can be set to one of:\n\
5714 auto - the default ABI associated with the current binary\n\
5723 &setmipscmdlist
, &showmipscmdlist
);
5725 /* Let the user turn off floating point and set the fence post for
5726 heuristic_proc_start. */
5728 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5729 _("Set use of MIPS floating-point coprocessor."),
5730 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5731 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5732 _("Select single-precision MIPS floating-point coprocessor."),
5734 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5735 _("Select double-precision MIPS floating-point coprocessor."),
5737 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5738 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5739 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5740 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5741 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5742 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5743 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5744 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5745 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5746 _("Select MIPS floating-point coprocessor automatically."),
5748 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5749 _("Show current use of MIPS floating-point coprocessor target."),
5752 /* We really would like to have both "0" and "unlimited" work, but
5753 command.c doesn't deal with that. So make it a var_zinteger
5754 because the user can always use "999999" or some such for unlimited. */
5755 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5756 &heuristic_fence_post
, _("\
5757 Set the distance searched for the start of a function."), _("\
5758 Show the distance searched for the start of a function."), _("\
5759 If you are debugging a stripped executable, GDB needs to search through the\n\
5760 program for the start of a function. This command sets the distance of the\n\
5761 search. The only need to set it is when debugging a stripped executable."),
5762 reinit_frame_cache_sfunc
,
5763 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5764 &setlist
, &showlist
);
5766 /* Allow the user to control whether the upper bits of 64-bit
5767 addresses should be zeroed. */
5768 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5769 &mask_address_var
, _("\
5770 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5771 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5772 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5773 allow GDB to determine the correct value."),
5774 NULL
, show_mask_address
,
5775 &setmipscmdlist
, &showmipscmdlist
);
5777 /* Allow the user to control the size of 32 bit registers within the
5778 raw remote packet. */
5779 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5780 &mips64_transfers_32bit_regs_p
, _("\
5781 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5783 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5785 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5786 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5787 64 bits for others. Use \"off\" to disable compatibility mode"),
5788 set_mips64_transfers_32bit_regs
,
5789 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5790 &setlist
, &showlist
);
5792 /* Debug this files internals. */
5793 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5795 Set mips debugging."), _("\
5796 Show mips debugging."), _("\
5797 When non-zero, mips specific debugging is enabled."),
5799 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5800 &setdebuglist
, &showdebuglist
);