1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995
3 Free Software Foundation, Inc.
4 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
5 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
41 /* FIXME: Put this declaration in frame.h. */
42 extern struct obstack frame_cache_obstack
;
44 /* FIXME! this code assumes 4-byte instructions. */
45 #define MIPS_INSTLEN 4
46 #define MIPS_NUMREGS 32 /* FIXME! how many on 64-bit mips? */
47 typedef unsigned long t_inst
;
51 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
54 static int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
56 static void mips_print_register
PARAMS ((int, int));
58 static mips_extra_func_info_t
59 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
61 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
63 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
65 static void mips_set_fpu_command
PARAMS ((char *, int,
66 struct cmd_list_element
*));
68 static void mips_show_fpu_command
PARAMS ((char *, int,
69 struct cmd_list_element
*));
71 void mips_set_processor_type_command
PARAMS ((char *, int));
73 int mips_set_processor_type
PARAMS ((char *));
75 static void mips_show_processor_type_command
PARAMS ((char *, int));
77 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
78 struct cmd_list_element
*));
80 static mips_extra_func_info_t
81 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
*next_frame
));
83 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
84 mips_extra_func_info_t proc_desc
));
86 /* This value is the model of MIPS in use. It is derived from the value
87 of the PrID register. */
89 char *mips_processor_type
;
91 char *tmp_mips_processor_type
;
93 /* Some MIPS boards don't support floating point, so we permit the
94 user to turn it off. */
96 enum mips_fpu_type mips_fpu
;
98 static char *mips_fpu_string
;
100 /* A set of original names, to be used when restoring back to generic
101 registers from a specific set. */
103 char *mips_generic_reg_names
[] = REGISTER_NAMES
;
105 /* Names of IDT R3041 registers. */
107 char *mips_r3041_reg_names
[] = {
108 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
109 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
110 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
111 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
112 "sr", "lo", "hi", "bad", "cause","pc",
113 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
114 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
115 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
116 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
117 "fsr", "fir", "fp", "",
118 "", "", "bus", "ccfg", "", "", "", "",
119 "", "", "port", "cmp", "", "", "epc", "prid",
122 /* Names of IDT R3051 registers. */
124 char *mips_r3051_reg_names
[] = {
125 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
126 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
127 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
128 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
129 "sr", "lo", "hi", "bad", "cause","pc",
130 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
131 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
132 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
133 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
134 "fsr", "fir", "fp", "",
135 "inx", "rand", "elo", "", "ctxt", "", "", "",
136 "", "", "ehi", "", "", "", "epc", "prid",
139 /* Names of IDT R3081 registers. */
141 char *mips_r3081_reg_names
[] = {
142 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
143 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
144 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
145 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
146 "sr", "lo", "hi", "bad", "cause","pc",
147 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
148 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
149 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
150 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
151 "fsr", "fir", "fp", "",
152 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
153 "", "", "ehi", "", "", "", "epc", "prid",
156 /* Names of LSI 33k registers. */
158 char *mips_lsi33k_reg_names
[] = {
159 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
160 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
161 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
162 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
163 "epc", "hi", "lo", "sr", "cause","badvaddr",
164 "dcic", "bpc", "bda", "", "", "", "", "",
165 "", "", "", "", "", "", "", "",
166 "", "", "", "", "", "", "", "",
167 "", "", "", "", "", "", "", "",
169 "", "", "", "", "", "", "", "",
170 "", "", "", "", "", "", "", "",
176 } mips_processor_type_table
[] = {
177 { "generic", mips_generic_reg_names
},
178 { "r3041", mips_r3041_reg_names
},
179 { "r3051", mips_r3051_reg_names
},
180 { "r3071", mips_r3081_reg_names
},
181 { "r3081", mips_r3081_reg_names
},
182 { "lsi33k", mips_lsi33k_reg_names
},
186 /* Heuristic_proc_start may hunt through the text section for a long
187 time across a 2400 baud serial line. Allows the user to limit this
190 static unsigned int heuristic_fence_post
= 0;
192 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
193 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
194 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
195 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
196 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
197 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
198 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
199 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
200 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
201 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
202 #define _PROC_MAGIC_ 0x0F0F0F0F
203 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
204 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
206 struct linked_proc_info
208 struct mips_extra_func_info info
;
209 struct linked_proc_info
*next
;
210 } *linked_proc_desc_table
= NULL
;
214 /* This returns the PC of the first inst after the prologue. If we can't
215 find the prologue, then return 0. */
218 after_prologue (pc
, proc_desc
)
220 mips_extra_func_info_t proc_desc
;
222 struct symtab_and_line sal
;
223 CORE_ADDR func_addr
, func_end
;
226 proc_desc
= find_proc_desc (pc
, NULL
);
230 /* If function is frameless, then we need to do it the hard way. I
231 strongly suspect that frameless always means prologueless... */
232 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
233 && PROC_FRAME_OFFSET (proc_desc
) == 0)
237 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
238 return 0; /* Unknown */
240 sal
= find_pc_line (func_addr
, 0);
242 if (sal
.end
< func_end
)
245 /* The line after the prologue is after the end of the function. In this
246 case, tell the caller to find the prologue the hard way. */
251 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
255 mips_find_saved_regs (fci
)
256 struct frame_info
*fci
;
259 CORE_ADDR reg_position
;
260 /* r0 bit means kernel trap */
262 /* What registers have been saved? Bitmasks. */
263 unsigned long gen_mask
, float_mask
;
264 mips_extra_func_info_t proc_desc
;
266 fci
->saved_regs
= (struct frame_saved_regs
*)
267 obstack_alloc (&frame_cache_obstack
, sizeof(struct frame_saved_regs
));
268 memset (fci
->saved_regs
, 0, sizeof (struct frame_saved_regs
));
270 /* If it is the frame for sigtramp, the saved registers are located
271 in a sigcontext structure somewhere on the stack.
272 If the stack layout for sigtramp changes we might have to change these
273 constants and the companion fixup_sigtramp in mdebugread.c */
274 #ifndef SIGFRAME_BASE
275 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
276 above the sigtramp frame. */
277 #define SIGFRAME_BASE MIPS_REGSIZE
278 /* FIXME! Are these correct?? */
279 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
280 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
281 #define SIGFRAME_FPREGSAVE_OFF \
282 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
284 #ifndef SIGFRAME_REG_SIZE
285 /* FIXME! Is this correct?? */
286 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
288 if (fci
->signal_handler_caller
)
290 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
292 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
293 + ireg
* SIGFRAME_REG_SIZE
;
294 fci
->saved_regs
->regs
[ireg
] = reg_position
;
296 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
298 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
299 + ireg
* SIGFRAME_REG_SIZE
;
300 fci
->saved_regs
->regs
[FP0_REGNUM
+ ireg
] = reg_position
;
302 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
306 proc_desc
= fci
->proc_desc
;
307 if (proc_desc
== NULL
)
308 /* I'm not sure how/whether this can happen. Normally when we can't
309 find a proc_desc, we "synthesize" one using heuristic_proc_desc
310 and set the saved_regs right away. */
313 kernel_trap
= PROC_REG_MASK(proc_desc
) & 1;
314 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK(proc_desc
);
315 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK(proc_desc
);
317 if (/* In any frame other than the innermost, we assume that all
318 registers have been saved. This assumes that all register
319 saves in a function happen before the first function
323 /* In a dummy frame we know exactly where things are saved. */
324 && !PROC_DESC_IS_DUMMY (proc_desc
)
326 /* Don't bother unless we are inside a function prologue. Outside the
327 prologue, we know where everything is. */
329 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
331 /* Not sure exactly what kernel_trap means, but if it means
332 the kernel saves the registers without a prologue doing it,
333 we better not examine the prologue to see whether registers
334 have been saved yet. */
337 /* We need to figure out whether the registers that the proc_desc
338 claims are saved have been saved yet. */
342 char buf
[MIPS_INSTLEN
];
345 /* Bitmasks; set if we have found a save for the register. */
346 unsigned long gen_save_found
= 0;
347 unsigned long float_save_found
= 0;
349 for (addr
= PROC_LOW_ADDR (proc_desc
);
350 addr
< fci
->pc
/*&& (gen_mask != gen_save_found
351 || float_mask != float_save_found)*/;
352 addr
+= MIPS_INSTLEN
)
354 status
= read_memory_nobpt (addr
, buf
, MIPS_INSTLEN
);
356 memory_error (status
, addr
);
357 inst
= extract_unsigned_integer (buf
, MIPS_INSTLEN
);
358 if (/* sw reg,n($sp) */
359 (inst
& 0xffe00000) == 0xafa00000
362 || (inst
& 0xffe00000) == 0xafc00000
365 || (inst
& 0xffe00000) == 0xffa00000)
367 /* It might be possible to use the instruction to
368 find the offset, rather than the code below which
369 is based on things being in a certain order in the
370 frame, but figuring out what the instruction's offset
371 is relative to might be a little tricky. */
372 int reg
= (inst
& 0x001f0000) >> 16;
373 gen_save_found
|= (1 << reg
);
375 else if (/* swc1 freg,n($sp) */
376 (inst
& 0xffe00000) == 0xe7a00000
378 /* swc1 freg,n($r30) */
379 || (inst
& 0xffe00000) == 0xe7c00000
381 /* sdc1 freg,n($sp) */
382 || (inst
& 0xffe00000) == 0xf7a00000)
385 int reg
= ((inst
& 0x001f0000) >> 16);
386 float_save_found
|= (1 << reg
);
389 gen_mask
= gen_save_found
;
390 float_mask
= float_save_found
;
393 /* Fill in the offsets for the registers which gen_mask says
395 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
396 for (ireg
= MIPS_NUMREGS
-1; gen_mask
; --ireg
, gen_mask
<<= 1)
397 if (gen_mask
& 0x80000000)
399 fci
->saved_regs
->regs
[ireg
] = reg_position
;
400 reg_position
-= MIPS_REGSIZE
;
402 /* Fill in the offsets for the registers which float_mask says
404 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
406 /* The freg_offset points to where the first *double* register
407 is saved. So skip to the high-order word. */
408 if (! GDB_TARGET_IS_MIPS64
)
411 /* FIXME! this code looks scary...
412 * Looks like it's trying to do stuff with a register,
415 for (ireg
= MIPS_NUMREGS
-1; float_mask
; --ireg
, float_mask
<<= 1)
416 if (float_mask
& 0x80000000)
418 fci
->saved_regs
->regs
[FP0_REGNUM
+ireg
] = reg_position
;
419 reg_position
-= MIPS_REGSIZE
;
422 fci
->saved_regs
->regs
[PC_REGNUM
] = fci
->saved_regs
->regs
[RA_REGNUM
];
426 read_next_frame_reg(fi
, regno
)
427 struct frame_info
*fi
;
430 for (; fi
; fi
= fi
->next
)
432 /* We have to get the saved sp from the sigcontext
433 if it is a signal handler frame. */
434 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
438 if (fi
->saved_regs
== NULL
)
439 mips_find_saved_regs (fi
);
440 if (fi
->saved_regs
->regs
[regno
])
441 return read_memory_integer(fi
->saved_regs
->regs
[regno
], MIPS_REGSIZE
);
444 return read_register (regno
);
448 mips_frame_saved_pc(frame
)
449 struct frame_info
*frame
;
452 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
453 /* We have to get the saved pc from the sigcontext
454 if it is a signal handler frame. */
455 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
456 : (proc_desc
? PROC_PC_REG(proc_desc
) : RA_REGNUM
);
458 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
459 saved_pc
= read_memory_integer(frame
->frame
- MIPS_REGSIZE
, MIPS_REGSIZE
);
461 saved_pc
= read_next_frame_reg(frame
, pcreg
);
463 if (GDB_TARGET_IS_MIPS64
&& strcmp(current_target
.to_shortname
,"pmon")==0)
465 /* This hack is a work-around for PMON.
466 * The PMON version in the Vr4300 board has been
467 * compiled without the 64bit register access commands.
468 * Thus, the upper word of the PC may be sign extended to all 1s.
469 * If so, change it to zero. */
470 if (saved_pc
>> 32 == (CORE_ADDR
)0xffffffff)
471 saved_pc
&= (CORE_ADDR
)0xffffffff;
477 static struct mips_extra_func_info temp_proc_desc
;
478 static struct frame_saved_regs temp_saved_regs
;
480 /* This fencepost looks highly suspicious to me. Removing it also
481 seems suspicious as it could affect remote debugging across serial
485 heuristic_proc_start(pc
)
488 CORE_ADDR start_pc
= pc
;
489 CORE_ADDR fence
= start_pc
- heuristic_fence_post
;
491 if (start_pc
== 0) return 0;
493 if (heuristic_fence_post
== UINT_MAX
494 || fence
< VM_MIN_ADDRESS
)
495 fence
= VM_MIN_ADDRESS
;
497 /* search back for previous return */
498 for (start_pc
-= MIPS_INSTLEN
; ; start_pc
-= MIPS_INSTLEN
) /* FIXME!! */
499 if (start_pc
< fence
)
501 /* It's not clear to me why we reach this point when
502 stop_soon_quietly, but with this test, at least we
503 don't print out warnings for every child forked (eg, on
504 decstation). 22apr93 rich@cygnus.com. */
505 if (!stop_soon_quietly
)
507 static int blurb_printed
= 0;
509 if (fence
== VM_MIN_ADDRESS
)
510 warning("Hit beginning of text section without finding");
512 warning("Hit heuristic-fence-post without finding");
514 warning("enclosing function for address 0x%x", pc
);
518 This warning occurs if you are debugging a function without any symbols\n\
519 (for example, in a stripped executable). In that case, you may wish to\n\
520 increase the size of the search with the `set heuristic-fence-post' command.\n\
522 Otherwise, you told GDB there was a function where there isn't one, or\n\
523 (more likely) you have encountered a bug in GDB.\n");
530 else if (ABOUT_TO_RETURN(start_pc
))
533 start_pc
+= 8; /* skip return, and its delay slot */ /* FIXME!! */
535 /* skip nops (usually 1) 0 - is this */
536 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
537 start_pc
+= MIPS_INSTLEN
;
542 static mips_extra_func_info_t
543 heuristic_proc_desc(start_pc
, limit_pc
, next_frame
)
544 CORE_ADDR start_pc
, limit_pc
;
545 struct frame_info
*next_frame
;
547 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
549 unsigned long frame_size
;
550 int has_frame_reg
= 0;
551 CORE_ADDR reg30
= 0; /* Value of $r30. Used by gcc for frame-pointer */
552 unsigned long reg_mask
= 0;
554 if (start_pc
== 0) return NULL
;
555 memset (&temp_proc_desc
, '\0', sizeof(temp_proc_desc
));
556 memset (&temp_saved_regs
, '\0', sizeof(struct frame_saved_regs
));
557 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
559 if (start_pc
+ 200 < limit_pc
)
560 limit_pc
= start_pc
+ 200;
563 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
) {
564 char buf
[MIPS_INSTLEN
];
568 status
= (unsigned long) read_memory_nobpt (cur_pc
, buf
, MIPS_INSTLEN
); /* FIXME!! */
569 if (status
) memory_error (status
, cur_pc
);
570 word
= (unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
); /* FIXME!! */
572 if ((word
& 0xFFFF0000) == 0x27bd0000) /* addiu $sp,$sp,-i */
573 frame_size
+= (-word
) & 0xFFFF;
574 else if ((word
& 0xFFFF0000) == 0x23bd0000) /* addu $sp,$sp,-i */
575 frame_size
+= (-word
) & 0xFFFF;
576 else if ((word
& 0xFFE00000) == 0xafa00000) { /* sw reg,offset($sp) */
577 int reg
= (word
& 0x001F0000) >> 16;
578 reg_mask
|= 1 << reg
;
579 temp_saved_regs
.regs
[reg
] = sp
+ (word
& 0xffff);
581 else if ((word
& 0xFFFF0000) == 0x27be0000) { /* addiu $30,$sp,size */
582 if ((word
& 0xffff) != frame_size
)
583 reg30
= sp
+ (word
& 0xffff);
584 else if (!has_frame_reg
) {
585 unsigned alloca_adjust
;
587 reg30
= read_next_frame_reg(next_frame
, 30);
588 alloca_adjust
= (unsigned)(reg30
- (sp
+ (word
& 0xffff)));
589 if (alloca_adjust
> 0) {
590 /* FP > SP + frame_size. This may be because
591 * of an alloca or somethings similar.
592 * Fix sp to "pre-alloca" value, and try again.
599 else if ((word
& 0xFFE00000) == 0xafc00000) { /* sw reg,offset($30) */
600 int reg
= (word
& 0x001F0000) >> 16;
601 reg_mask
|= 1 << reg
;
602 temp_saved_regs
.regs
[reg
] = reg30
+ (word
& 0xffff);
606 PROC_FRAME_REG(&temp_proc_desc
) = 30;
607 PROC_FRAME_OFFSET(&temp_proc_desc
) = 0;
610 PROC_FRAME_REG(&temp_proc_desc
) = SP_REGNUM
;
611 PROC_FRAME_OFFSET(&temp_proc_desc
) = frame_size
;
613 PROC_REG_MASK(&temp_proc_desc
) = reg_mask
;
614 PROC_PC_REG(&temp_proc_desc
) = RA_REGNUM
;
615 return &temp_proc_desc
;
618 static mips_extra_func_info_t
619 find_proc_desc (pc
, next_frame
)
621 struct frame_info
*next_frame
;
623 mips_extra_func_info_t proc_desc
;
624 struct block
*b
= block_for_pc(pc
);
628 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
633 if (startaddr
> BLOCK_START (b
))
634 /* This is the "pathological" case referred to in a comment in
635 print_frame_info. It might be better to move this check into
639 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
,
643 /* If we never found a PDR for this function in symbol reading, then
644 examine prologues to find the information. */
645 if (sym
&& ((mips_extra_func_info_t
) SYMBOL_VALUE (sym
))->pdr
.framereg
== -1)
650 /* IF this is the topmost frame AND
651 * (this proc does not have debugging information OR
652 * the PC is in the procedure prologue)
653 * THEN create a "heuristic" proc_desc (by analyzing
654 * the actual code) to replace the "official" proc_desc.
656 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
657 if (next_frame
== NULL
) {
658 struct symtab_and_line val
;
659 struct symbol
*proc_symbol
=
660 PROC_DESC_IS_DUMMY(proc_desc
) ? 0 : PROC_SYMBOL(proc_desc
);
663 val
= find_pc_line (BLOCK_START
664 (SYMBOL_BLOCK_VALUE(proc_symbol
)),
666 val
.pc
= val
.end
? val
.end
: pc
;
668 if (!proc_symbol
|| pc
< val
.pc
) {
669 mips_extra_func_info_t found_heuristic
=
670 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
673 proc_desc
= found_heuristic
;
679 /* Is linked_proc_desc_table really necessary? It only seems to be used
680 by procedure call dummys. However, the procedures being called ought
681 to have their own proc_descs, and even if they don't,
682 heuristic_proc_desc knows how to create them! */
684 register struct linked_proc_info
*link
;
686 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
687 if (PROC_LOW_ADDR(&link
->info
) <= pc
688 && PROC_HIGH_ADDR(&link
->info
) > pc
)
692 startaddr
= heuristic_proc_start (pc
);
695 heuristic_proc_desc (startaddr
, pc
, next_frame
);
700 mips_extra_func_info_t cached_proc_desc
;
703 mips_frame_chain(frame
)
704 struct frame_info
*frame
;
706 mips_extra_func_info_t proc_desc
;
707 CORE_ADDR saved_pc
= FRAME_SAVED_PC(frame
);
709 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
712 proc_desc
= find_proc_desc(saved_pc
, frame
);
716 cached_proc_desc
= proc_desc
;
718 /* If no frame pointer and frame size is zero, we must be at end
719 of stack (or otherwise hosed). If we don't check frame size,
720 we loop forever if we see a zero size frame. */
721 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
722 && PROC_FRAME_OFFSET (proc_desc
) == 0
723 /* The previous frame from a sigtramp frame might be frameless
724 and have frame size zero. */
725 && !frame
->signal_handler_caller
)
728 return read_next_frame_reg(frame
, PROC_FRAME_REG(proc_desc
))
729 + PROC_FRAME_OFFSET(proc_desc
);
733 init_extra_frame_info(fci
)
734 struct frame_info
*fci
;
736 /* Use proc_desc calculated in frame_chain */
737 mips_extra_func_info_t proc_desc
=
738 fci
->next
? cached_proc_desc
: find_proc_desc(fci
->pc
, fci
->next
);
740 fci
->saved_regs
= NULL
;
742 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
745 /* Fixup frame-pointer - only needed for top frame */
746 /* This may not be quite right, if proc has a real frame register.
747 Get the value of the frame relative sp, procedure might have been
748 interrupted by a signal at it's very start. */
749 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
750 && !PROC_DESC_IS_DUMMY (proc_desc
))
751 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
754 read_next_frame_reg (fci
->next
, PROC_FRAME_REG (proc_desc
))
755 + PROC_FRAME_OFFSET (proc_desc
);
757 if (proc_desc
== &temp_proc_desc
)
761 /* Do not set the saved registers for a sigtramp frame,
762 mips_find_saved_registers will do that for us.
763 We can't use fci->signal_handler_caller, it is not yet set. */
764 find_pc_partial_function (fci
->pc
, &name
,
765 (CORE_ADDR
*)NULL
,(CORE_ADDR
*)NULL
);
766 if (!IN_SIGTRAMP (fci
->pc
, name
))
768 fci
->saved_regs
= (struct frame_saved_regs
*)
769 obstack_alloc (&frame_cache_obstack
,
770 sizeof (struct frame_saved_regs
));
771 *fci
->saved_regs
= temp_saved_regs
;
772 fci
->saved_regs
->regs
[PC_REGNUM
]
773 = fci
->saved_regs
->regs
[RA_REGNUM
];
777 /* hack: if argument regs are saved, guess these contain args */
778 if ((PROC_REG_MASK(proc_desc
) & 0xF0) == 0) fci
->num_args
= -1;
779 /* FIXME! Increase this for MIPS EABI */
780 else if ((PROC_REG_MASK(proc_desc
) & 0x80) == 0) fci
->num_args
= 4;
781 else if ((PROC_REG_MASK(proc_desc
) & 0x40) == 0) fci
->num_args
= 3;
782 else if ((PROC_REG_MASK(proc_desc
) & 0x20) == 0) fci
->num_args
= 2;
783 else if ((PROC_REG_MASK(proc_desc
) & 0x10) == 0) fci
->num_args
= 1;
787 /* MIPS stack frames are almost impenetrable. When execution stops,
788 we basically have to look at symbol information for the function
789 that we stopped in, which tells us *which* register (if any) is
790 the base of the frame pointer, and what offset from that register
791 the frame itself is at.
793 This presents a problem when trying to examine a stack in memory
794 (that isn't executing at the moment), using the "frame" command. We
795 don't have a PC, nor do we have any registers except SP.
797 This routine takes two arguments, SP and PC, and tries to make the
798 cached frames look as if these two arguments defined a frame on the
799 cache. This allows the rest of info frame to extract the important
800 arguments without difficulty. */
803 setup_arbitrary_frame (argc
, argv
)
808 error ("MIPS frame specifications require two arguments: sp and pc");
810 return create_new_frame (argv
[0], argv
[1]);
815 mips_push_arguments(nargs
, args
, sp
, struct_return
, struct_addr
)
820 CORE_ADDR struct_addr
;
824 struct mips_arg
{ char *contents
; int len
; int offset
; };
825 struct mips_arg
*mips_args
;
826 register struct mips_arg
*m_arg
;
830 /* Macro to round n up to the next a boundary (a must be a power of two) */
831 #define ALIGN(n,a) (((n)+(a)-1) & ~((a)-1))
833 /* First ensure that the stack and structure return address (if any)
834 are properly aligned. */
836 sp
= ALIGN (sp
, MIPS_REGSIZE
);
837 struct_addr
= ALIGN (struct_addr
, MIPS_REGSIZE
);
839 accumulate_size
= struct_return
? MIPS_REGSIZE
: 0;
841 /* Allocate descriptors for each argument, plus some extras for the
842 dummies we will create to zero-fill the holes left when we align
843 arguments passed in registers that are smaller than a register. */
844 mips_args
= /* FIXME! Should this 4 be increased for MIPS64? */
845 (struct mips_arg
*) alloca ((nargs
+ 4) * sizeof (struct mips_arg
));
847 /* Build up the list of argument descriptors. */
848 for (i
= 0, m_arg
= mips_args
; i
< nargs
; i
++, m_arg
++) {
849 value_ptr arg
= args
[i
];
850 len
= m_arg
->len
= TYPE_LENGTH (VALUE_TYPE (arg
));
851 /* This entire mips-specific routine is because doubles must be aligned
852 * on 8-byte boundaries. It still isn't quite right, because MIPS decided
853 * to align 'struct {int a, b}' on 4-byte boundaries (even though this
854 * breaks their varargs implementation...). A correct solution
855 * requires an simulation of gcc's 'alignof' (and use of 'alignof'
856 * in stdarg.h/varargs.h).
857 * On the 64 bit r4000 we always pass the first four arguments
858 * using eight bytes each, so that we can load them up correctly
861 if (len
> 4) /* FIXME? */
862 accumulate_size
= ALIGN (accumulate_size
, 8);
863 m_arg
->offset
= accumulate_size
;
864 m_arg
->contents
= VALUE_CONTENTS(arg
);
865 if (! GDB_TARGET_IS_MIPS64
)
866 /* For 32-bit targets, align the next argument on a 32-bit boundary. */
867 accumulate_size
= ALIGN (accumulate_size
+ len
, 4);
870 /* If the argument is being passed on the stack, not a register,
871 adjust the size of the argument upward to account for stack
872 alignment. The EABI allows 8 arguments to be passed in
873 registers; the old ABI allows only four. This code seems
874 bogus to me: shouldn't we be right-aligning small arguments
875 as we do below for the args-in-registers case? FIXME!! */
877 if (accumulate_size
>= 8 * MIPS_REGSIZE
) /* Ignores FP. FIXME!! */
878 accumulate_size
= ALIGN (accumulate_size
+ len
, 8);
880 if (accumulate_size
>= 4 * MIPS_REGSIZE
)
881 accumulate_size
= ALIGN (accumulate_size
+ len
, 4);
885 if (len
< MIPS_REGSIZE
)
887 /* The argument is being passed in a register, but is smaller
888 than a register. So it it must be right-aligned in the
889 register image being placed in the stack, and the rest
890 of the register image must be zero-filled. */
891 static char zeroes
[MIPS_REGSIZE
] = { 0 };
893 /* Align the arg in the rightmost part of the 64-bit word. */
894 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
895 m_arg
->offset
+= MIPS_REGSIZE
- len
;
897 /* Create a fake argument to zero-fill the unsused part
898 of the 64-bit word. */
900 m_arg
->len
= MIPS_REGSIZE
- len
;
901 m_arg
->contents
= zeroes
;
902 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
903 m_arg
->offset
= accumulate_size
;
905 m_arg
->offset
= accumulate_size
+ len
;
908 accumulate_size
= ALIGN (accumulate_size
+ len
, MIPS_REGSIZE
);
912 accumulate_size
= ALIGN (accumulate_size
, 8);
913 if (accumulate_size
< 4 * MIPS_REGSIZE
)
914 accumulate_size
= 4 * MIPS_REGSIZE
;
915 sp
-= accumulate_size
;
916 for (i
= nargs
+ fake_args
; m_arg
--, --i
>= 0; )
917 write_memory(sp
+ m_arg
->offset
, m_arg
->contents
, m_arg
->len
);
920 char buf
[TARGET_PTR_BIT
/ HOST_CHAR_BIT
];
922 store_address (buf
, sizeof buf
, struct_addr
);
923 write_memory (sp
, buf
, sizeof buf
);
929 mips_push_register(CORE_ADDR
*sp
, int regno
)
931 char buffer
[MAX_REGISTER_RAW_SIZE
];
932 int regsize
= REGISTER_RAW_SIZE (regno
);
935 read_register_gen (regno
, buffer
);
936 write_memory (*sp
, buffer
, regsize
);
939 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
940 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
943 mips_push_dummy_frame()
946 struct linked_proc_info
*link
= (struct linked_proc_info
*)
947 xmalloc(sizeof(struct linked_proc_info
));
948 mips_extra_func_info_t proc_desc
= &link
->info
;
949 CORE_ADDR sp
= read_register (SP_REGNUM
);
950 CORE_ADDR old_sp
= sp
;
951 link
->next
= linked_proc_desc_table
;
952 linked_proc_desc_table
= link
;
954 /* FIXME! are these correct ? */
955 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
956 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
957 #define GEN_REG_SAVE_COUNT 22
958 #define FLOAT_REG_SAVE_MASK MASK(0,19)
959 #define FLOAT_REG_SAVE_COUNT 20
960 #define FLOAT_SINGLE_REG_SAVE_MASK \
961 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
962 #define FLOAT_SINGLE_REG_SAVE_COUNT 10
963 #define SPECIAL_REG_SAVE_COUNT 4
965 * The registers we must save are all those not preserved across
966 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
967 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
968 * and FP Control/Status registers.
971 * Dummy frame layout:
974 * Saved MMHI, MMLO, FPC_CSR
979 * Saved D18 (i.e. F19, F18)
981 * Saved D0 (i.e. F1, F0)
982 * CALL_DUMMY (subroutine stub; see tm-mips.h)
983 * Parameter build area (not yet implemented)
987 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
988 write_register (PUSH_FP_REGNUM
, sp
);
989 PROC_FRAME_REG(proc_desc
) = PUSH_FP_REGNUM
;
990 PROC_FRAME_OFFSET(proc_desc
) = 0;
991 mips_push_register (&sp
, PC_REGNUM
);
992 mips_push_register (&sp
, HI_REGNUM
);
993 mips_push_register (&sp
, LO_REGNUM
);
994 mips_push_register (&sp
, mips_fpu
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
996 /* Save general CPU registers */
997 PROC_REG_MASK(proc_desc
) = GEN_REG_SAVE_MASK
;
998 PROC_REG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved R31) from FP */
999 for (ireg
= 32; --ireg
>= 0; )
1000 if (PROC_REG_MASK(proc_desc
) & (1 << ireg
))
1001 mips_push_register (&sp
, ireg
);
1003 /* Save floating point registers starting with high order word */
1004 PROC_FREG_MASK(proc_desc
) =
1005 mips_fpu
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
1006 : mips_fpu
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
1007 PROC_FREG_OFFSET(proc_desc
) = sp
- old_sp
; /* offset of (Saved D18) from FP */
1008 for (ireg
= 32; --ireg
>= 0; )
1009 if (PROC_FREG_MASK(proc_desc
) & (1 << ireg
))
1010 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
1012 /* Update the stack pointer. Set the procedure's starting and ending
1013 addresses to point to the place on the stack where we'll be writing the
1014 dummy code (in mips_push_arguments). */
1015 write_register (SP_REGNUM
, sp
);
1016 PROC_LOW_ADDR(proc_desc
) = sp
- CALL_DUMMY_SIZE
+ CALL_DUMMY_START_OFFSET
;
1017 PROC_HIGH_ADDR(proc_desc
) = sp
;
1018 SET_PROC_DESC_IS_DUMMY(proc_desc
);
1019 PROC_PC_REG(proc_desc
) = RA_REGNUM
;
1025 register int regnum
;
1026 struct frame_info
*frame
= get_current_frame ();
1027 CORE_ADDR new_sp
= FRAME_FP (frame
);
1029 mips_extra_func_info_t proc_desc
= frame
->proc_desc
;
1031 write_register (PC_REGNUM
, FRAME_SAVED_PC(frame
));
1032 if (frame
->saved_regs
== NULL
)
1033 mips_find_saved_regs (frame
);
1036 for (regnum
= MIPS_NUMREGS
; --regnum
>= 0; )
1037 if (PROC_REG_MASK(proc_desc
) & (1 << regnum
))
1038 write_register (regnum
,
1039 read_memory_integer (frame
->saved_regs
->regs
[regnum
],
1041 for (regnum
= MIPS_NUMREGS
; --regnum
>= 0; )
1042 if (PROC_FREG_MASK(proc_desc
) & (1 << regnum
))
1043 write_register (regnum
+ FP0_REGNUM
,
1044 read_memory_integer (frame
->saved_regs
->regs
[regnum
+ FP0_REGNUM
], MIPS_REGSIZE
));
1046 write_register (SP_REGNUM
, new_sp
);
1047 flush_cached_frames ();
1049 if (proc_desc
&& PROC_DESC_IS_DUMMY(proc_desc
))
1051 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
1053 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
1055 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
1057 if (&pi_ptr
->info
== proc_desc
)
1062 error ("Can't locate dummy extra frame info\n");
1064 if (prev_ptr
!= NULL
)
1065 prev_ptr
->next
= pi_ptr
->next
;
1067 linked_proc_desc_table
= pi_ptr
->next
;
1071 write_register (HI_REGNUM
,
1072 read_memory_integer (new_sp
- 2*MIPS_REGSIZE
, MIPS_REGSIZE
));
1073 write_register (LO_REGNUM
,
1074 read_memory_integer (new_sp
- 3*MIPS_REGSIZE
, MIPS_REGSIZE
));
1075 if (mips_fpu
!= MIPS_FPU_NONE
)
1076 write_register (FCRCS_REGNUM
,
1077 read_memory_integer (new_sp
- 4*MIPS_REGSIZE
, MIPS_REGSIZE
));
1082 mips_print_register (regnum
, all
)
1085 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1087 /* Get the data in raw format. */
1088 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
1090 printf_filtered ("%s: [Invalid]", reg_names
[regnum
]);
1094 /* If an even floating pointer register, also print as double. */
1095 if (regnum
>= FP0_REGNUM
&& regnum
< FP0_REGNUM
+MIPS_NUMREGS
1096 && !((regnum
-FP0_REGNUM
) & 1))
1098 char dbuffer
[MAX_REGISTER_RAW_SIZE
];
1100 read_relative_register_raw_bytes (regnum
, dbuffer
);
1101 read_relative_register_raw_bytes (regnum
+1, dbuffer
+4); /* FIXME!! */
1102 #ifdef REGISTER_CONVERT_TO_TYPE
1103 REGISTER_CONVERT_TO_TYPE(regnum
, builtin_type_double
, dbuffer
);
1105 printf_filtered ("(d%d: ", regnum
-FP0_REGNUM
);
1106 val_print (builtin_type_double
, dbuffer
, 0,
1107 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1108 printf_filtered ("); ");
1110 fputs_filtered (reg_names
[regnum
], gdb_stdout
);
1112 /* The problem with printing numeric register names (r26, etc.) is that
1113 the user can't use them on input. Probably the best solution is to
1114 fix it so that either the numeric or the funky (a2, etc.) names
1115 are accepted on input. */
1116 if (regnum
< MIPS_NUMREGS
)
1117 printf_filtered ("(r%d): ", regnum
);
1119 printf_filtered (": ");
1121 /* If virtual format is floating, print it that way. */
1122 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
1123 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0,
1124 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
1125 /* Else print as integer in hex. */
1127 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
1128 'x', 0, gdb_stdout
);
1131 /* Replacement for generic do_registers_info. */
1134 mips_do_registers_info (regnum
, fpregs
)
1140 if (*(reg_names
[regnum
]) == '\0')
1141 error ("Not a valid register for the current processor type");
1143 mips_print_register (regnum
, 0);
1144 printf_filtered ("\n");
1148 int did_newline
= 0;
1150 for (regnum
= 0; regnum
< NUM_REGS
; )
1152 if (((!fpregs
) && regnum
>= FP0_REGNUM
&& regnum
<= FCRIR_REGNUM
)
1153 || *(reg_names
[regnum
]) == '\0')
1158 mips_print_register (regnum
, 1);
1160 printf_filtered ("; ");
1162 if ((regnum
& 3) == 0)
1164 printf_filtered ("\n");
1169 printf_filtered ("\n");
1173 /* Return number of args passed to a frame. described by FIP.
1174 Can return -1, meaning no way to tell. */
1177 mips_frame_num_args (frame
)
1178 struct frame_info
*frame
;
1180 #if 0 /* FIXME Use or lose this! */
1181 struct chain_info_t
*p
;
1183 p
= mips_find_cached_frame (FRAME_FP (frame
));
1185 return p
->the_info
.numargs
;
1190 /* Is this a branch with a delay slot? */
1192 static int is_delayed
PARAMS ((unsigned long));
1199 for (i
= 0; i
< NUMOPCODES
; ++i
)
1200 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
1201 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
1203 return (i
< NUMOPCODES
1204 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
1205 | INSN_COND_BRANCH_DELAY
1206 | INSN_COND_BRANCH_LIKELY
)));
1210 mips_step_skips_delay (pc
)
1213 char buf
[4]; /* FIXME!! */
1215 if (target_read_memory (pc
, buf
, 4) != 0) /* FIXME!! */
1216 /* If error reading memory, guess that it is not a delayed branch. */
1218 return is_delayed ((unsigned long)extract_unsigned_integer (buf
, 4)); /* FIXME */
1221 /* To skip prologues, I use this predicate. Returns either PC itself
1222 if the code at PC does not look like a function prologue; otherwise
1223 returns an address that (if we're lucky) follows the prologue. If
1224 LENIENT, then we must skip everything which is involved in setting
1225 up the frame (it's OK to skip more, just so long as we don't skip
1226 anything which might clobber the registers which are being saved.
1227 We must skip more in the case where part of the prologue is in the
1228 delay slot of a non-prologue instruction). */
1231 mips_skip_prologue (pc
, lenient
)
1237 int seen_sp_adjust
= 0;
1238 int load_immediate_bytes
= 0;
1239 CORE_ADDR post_prologue_pc
;
1241 /* See if we can determine the end of the prologue via the symbol table.
1242 If so, then return either PC, or the PC after the prologue, whichever
1245 post_prologue_pc
= after_prologue (pc
, NULL
);
1247 if (post_prologue_pc
!= 0)
1248 return max (pc
, post_prologue_pc
);
1250 /* Can't determine prologue from the symbol table, need to examine
1253 /* Skip the typical prologue instructions. These are the stack adjustment
1254 instruction and the instructions that save registers on the stack
1255 or in the gcc frame. */
1256 for (offset
= 0; offset
< 100; offset
+= MIPS_INSTLEN
) /* FIXME!! */
1258 char buf
[MIPS_INSTLEN
];
1261 status
= read_memory_nobpt (pc
+ offset
, buf
, MIPS_INSTLEN
);
1263 memory_error (status
, pc
+ offset
);
1264 inst
= (unsigned long)extract_unsigned_integer (buf
, MIPS_INSTLEN
);
1267 if (lenient
&& is_delayed (inst
))
1271 if ((inst
& 0xffff0000) == 0x27bd0000) /* addiu $sp,$sp,offset */
1273 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
1274 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
1276 else if ((inst
& 0xFFE00000) == 0xAFA00000 && (inst
& 0x001F0000))
1277 continue; /* sw reg,n($sp) */
1279 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
1281 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
1283 continue; /* reg != $zero */
1285 /* move $s8,$sp. With different versions of gas this will be either
1286 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero'. Accept either. */
1287 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025)
1290 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
1292 else if ((inst
& 0xffff0000) == 0x3c1c0000) /* lui $gp,n */
1294 else if ((inst
& 0xffff0000) == 0x279c0000) /* addiu $gp,$gp,n */
1296 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1297 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
1299 /* The following instructions load $at or $t0 with an immediate
1300 value in preparation for a stack adjustment via
1301 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
1302 a local variable, so we accept them only before a stack adjustment
1303 instruction was seen. */
1304 else if (!seen_sp_adjust
)
1306 if ((inst
& 0xffff0000) == 0x3c010000 || /* lui $at,n */
1307 (inst
& 0xffff0000) == 0x3c080000) /* lui $t0,n */
1309 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1312 else if ((inst
& 0xffff0000) == 0x34210000 || /* ori $at,$at,n */
1313 (inst
& 0xffff0000) == 0x35080000 || /* ori $t0,$t0,n */
1314 (inst
& 0xffff0000) == 0x34010000 || /* ori $at,$zero,n */
1315 (inst
& 0xffff0000) == 0x34080000) /* ori $t0,$zero,n */
1317 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
1327 /* In a frameless function, we might have incorrectly
1328 skipped some load immediate instructions. Undo the skipping
1329 if the load immediate was not followed by a stack adjustment. */
1330 if (load_immediate_bytes
&& !seen_sp_adjust
)
1331 offset
-= load_immediate_bytes
;
1336 /* The lenient prologue stuff should be superceded by the code in
1337 init_extra_frame_info which looks to see whether the stores mentioned
1338 in the proc_desc have actually taken place. */
1340 /* Is address PC in the prologue (loosely defined) for function at
1344 mips_in_lenient_prologue (startaddr
, pc
)
1345 CORE_ADDR startaddr
;
1348 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
1349 return pc
>= startaddr
&& pc
< end_prologue
;
1353 /* Given a return value in `regbuf' with a type `valtype',
1354 extract and copy its value into `valbuf'. */
1356 mips_extract_return_value (valtype
, regbuf
, valbuf
)
1357 struct type
*valtype
;
1358 char regbuf
[REGISTER_BYTES
];
1365 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
1366 && (mips_fpu
== MIPS_FPU_DOUBLE
1367 || (mips_fpu
== MIPS_FPU_SINGLE
&& TYPE_LENGTH (valtype
) <= 4))) /* FIXME!! */
1368 regnum
= FP0_REGNUM
;
1370 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
1371 && TYPE_CODE (valtype
) != TYPE_CODE_FLT
1372 && TYPE_LENGTH (valtype
) < REGISTER_RAW_SIZE (regnum
))
1373 offset
= REGISTER_RAW_SIZE (regnum
) - TYPE_LENGTH (valtype
);
1375 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
,
1376 TYPE_LENGTH (valtype
));
1377 #ifdef REGISTER_CONVERT_TO_TYPE
1378 REGISTER_CONVERT_TO_TYPE(regnum
, valtype
, valbuf
);
1382 /* Given a return value in `regbuf' with a type `valtype',
1383 write it's value into the appropriate register. */
1385 mips_store_return_value (valtype
, valbuf
)
1386 struct type
*valtype
;
1390 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
1393 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
1394 && (mips_fpu
== MIPS_FPU_DOUBLE
1395 || (mips_fpu
== MIPS_FPU_SINGLE
&& TYPE_LENGTH (valtype
) <= 4))) /* FIXME!! */
1396 regnum
= FP0_REGNUM
;
1398 memcpy(raw_buffer
, valbuf
, TYPE_LENGTH (valtype
));
1400 #ifdef REGISTER_CONVERT_FROM_TYPE
1401 REGISTER_CONVERT_FROM_TYPE(regnum
, valtype
, raw_buffer
);
1404 write_register_bytes(REGISTER_BYTE (regnum
), raw_buffer
, TYPE_LENGTH (valtype
));
1407 /* Exported procedure: Is PC in the signal trampoline code */
1410 in_sigtramp (pc
, ignore
)
1412 char *ignore
; /* function name */
1414 if (sigtramp_address
== 0)
1416 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
1419 /* Command to set FPU type. mips_fpu_string will have been set to the
1420 user's argument. Set mips_fpu based on mips_fpu_string, and then
1421 canonicalize mips_fpu_string. */
1425 mips_set_fpu_command (args
, from_tty
, c
)
1428 struct cmd_list_element
*c
;
1432 if (mips_fpu_string
== NULL
|| *mips_fpu_string
== '\0')
1433 mips_fpu
= MIPS_FPU_DOUBLE
;
1434 else if (strcasecmp (mips_fpu_string
, "double") == 0
1435 || strcasecmp (mips_fpu_string
, "on") == 0
1436 || strcasecmp (mips_fpu_string
, "1") == 0
1437 || strcasecmp (mips_fpu_string
, "yes") == 0)
1438 mips_fpu
= MIPS_FPU_DOUBLE
;
1439 else if (strcasecmp (mips_fpu_string
, "none") == 0
1440 || strcasecmp (mips_fpu_string
, "off") == 0
1441 || strcasecmp (mips_fpu_string
, "0") == 0
1442 || strcasecmp (mips_fpu_string
, "no") == 0)
1443 mips_fpu
= MIPS_FPU_NONE
;
1444 else if (strcasecmp (mips_fpu_string
, "single") == 0)
1445 mips_fpu
= MIPS_FPU_SINGLE
;
1447 err
= strsave (mips_fpu_string
);
1449 if (mips_fpu_string
!= NULL
)
1450 free (mips_fpu_string
);
1454 case MIPS_FPU_DOUBLE
:
1455 mips_fpu_string
= strsave ("double");
1457 case MIPS_FPU_SINGLE
:
1458 mips_fpu_string
= strsave ("single");
1461 mips_fpu_string
= strsave ("none");
1467 struct cleanup
*cleanups
= make_cleanup (free
, err
);
1468 error ("Unknown FPU type `%s'. Use `double', `none', or `single'.",
1470 do_cleanups (cleanups
);
1475 mips_show_fpu_command (args
, from_tty
, c
)
1478 struct cmd_list_element
*c
;
1482 /* Command to set the processor type. */
1485 mips_set_processor_type_command (args
, from_tty
)
1491 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
1493 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
1494 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
1495 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
1497 /* Restore the value. */
1498 tmp_mips_processor_type
= strsave (mips_processor_type
);
1503 if (!mips_set_processor_type (tmp_mips_processor_type
))
1505 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
1506 /* Restore its value. */
1507 tmp_mips_processor_type
= strsave (mips_processor_type
);
1512 mips_show_processor_type_command (args
, from_tty
)
1518 /* Modify the actual processor type. */
1521 mips_set_processor_type (str
)
1529 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
1531 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
1533 mips_processor_type
= str
;
1535 for (j
= 0; j
< NUM_REGS
; ++j
)
1536 reg_names
[j
] = mips_processor_type_table
[i
].regnames
[j
];
1540 /* FIXME tweak fpu flag too */
1547 /* Attempt to identify the particular processor model by reading the
1551 mips_read_processor_type ()
1555 prid
= read_register (PRID_REGNUM
);
1557 if ((prid
& ~0xf) == 0x700)
1558 return savestring ("r3041", strlen("r3041"));
1563 /* Just like reinit_frame_cache, but with the right arguments to be
1564 callable as an sfunc. */
1567 reinit_frame_cache_sfunc (args
, from_tty
, c
)
1570 struct cmd_list_element
*c
;
1572 reinit_frame_cache ();
1576 gdb_print_insn_mips (memaddr
, info
)
1578 disassemble_info
*info
;
1580 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1581 return print_insn_big_mips (memaddr
, info
);
1583 return print_insn_little_mips (memaddr
, info
);
1587 _initialize_mips_tdep ()
1589 struct cmd_list_element
*c
;
1591 tm_print_insn
= gdb_print_insn_mips
;
1593 /* Let the user turn off floating point and set the fence post for
1594 heuristic_proc_start. */
1596 c
= add_set_cmd ("mipsfpu", class_support
, var_string_noescape
,
1597 (char *) &mips_fpu_string
,
1598 "Set use of floating point coprocessor.\n\
1599 Set to `none' to avoid using floating point instructions when calling\n\
1600 functions or dealing with return values. Set to `single' to use only\n\
1601 single precision floating point as on the R4650. Set to `double' for\n\
1602 normal floating point support.",
1604 c
->function
.sfunc
= mips_set_fpu_command
;
1605 c
= add_show_from_set (c
, &showlist
);
1606 c
->function
.sfunc
= mips_show_fpu_command
;
1608 mips_fpu
= MIPS_FPU_DOUBLE
;
1609 mips_fpu_string
= strsave ("double");
1611 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
1612 (char *) &tmp_mips_processor_type
,
1613 "Set the type of MIPS processor in use.\n\
1614 Set this to be able to access processor-type-specific registers.\n\
1617 c
->function
.cfunc
= mips_set_processor_type_command
;
1618 c
= add_show_from_set (c
, &showlist
);
1619 c
->function
.cfunc
= mips_show_processor_type_command
;
1621 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
1622 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
1624 /* We really would like to have both "0" and "unlimited" work, but
1625 command.c doesn't deal with that. So make it a var_zinteger
1626 because the user can always use "999999" or some such for unlimited. */
1627 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
1628 (char *) &heuristic_fence_post
,
1630 Set the distance searched for the start of a function.\n\
1631 If you are debugging a stripped executable, GDB needs to search through the\n\
1632 program for the start of a function. This command sets the distance of the\n\
1633 search. The only need to set it is when debugging a stripped executable.",
1635 /* We need to throw away the frame cache when we set this, since it
1636 might change our ability to get backtraces. */
1637 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
1638 add_show_from_set (c
, &showlist
);