1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 make_mips16_addr (CORE_ADDR addr
)
215 unmake_mips16_addr (CORE_ADDR addr
)
217 return ((addr
) & ~1);
220 /* Return the contents of register REGNUM as a signed integer. */
223 read_signed_register (int regnum
)
225 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
226 deprecated_read_register_gen (regnum
, buf
);
227 return (extract_signed_integer
228 (buf
, register_size (current_gdbarch
, regnum
)));
232 read_signed_register_pid (int regnum
, ptid_t ptid
)
237 if (ptid_equal (ptid
, inferior_ptid
))
238 return read_signed_register (regnum
);
240 save_ptid
= inferior_ptid
;
242 inferior_ptid
= ptid
;
244 retval
= read_signed_register (regnum
);
246 inferior_ptid
= save_ptid
;
251 /* Return the MIPS ABI associated with GDBARCH. */
253 mips_abi (struct gdbarch
*gdbarch
)
255 return gdbarch_tdep (gdbarch
)->mips_abi
;
259 mips_isa_regsize (struct gdbarch
*gdbarch
)
261 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
262 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
265 /* Return the currently configured (or set) saved register size. */
267 static const char *mips_abi_regsize_string
= size_auto
;
270 mips_abi_regsize (struct gdbarch
*gdbarch
)
272 if (mips_abi_regsize_string
== size_auto
)
273 switch (mips_abi (gdbarch
))
275 case MIPS_ABI_EABI32
:
281 case MIPS_ABI_EABI64
:
283 case MIPS_ABI_UNKNOWN
:
286 internal_error (__FILE__
, __LINE__
, "bad switch");
288 else if (mips_abi_regsize_string
== size_64
)
290 else /* if (mips_abi_regsize_string == size_32) */
294 /* Functions for setting and testing a bit in a minimal symbol that
295 marks it as 16-bit function. The MSB of the minimal symbol's
296 "info" field is used for this purpose.
298 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
299 i.e. refers to a 16-bit function, and sets a "special" bit in a
300 minimal symbol to mark it as a 16-bit function
302 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
305 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
307 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
309 MSYMBOL_INFO (msym
) = (char *)
310 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
311 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
316 msymbol_is_special (struct minimal_symbol
*msym
)
318 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
321 /* XFER a value from the big/little/left end of the register.
322 Depending on the size of the value it might occupy the entire
323 register or just part of it. Make an allowance for this, aligning
324 things accordingly. */
327 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
328 enum bfd_endian endian
, bfd_byte
* in
,
329 const bfd_byte
* out
, int buf_offset
)
332 gdb_assert (reg_num
>= NUM_REGS
);
333 /* Need to transfer the left or right part of the register, based on
334 the targets byte order. */
338 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
340 case BFD_ENDIAN_LITTLE
:
343 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
347 internal_error (__FILE__
, __LINE__
, "bad switch");
350 fprintf_unfiltered (gdb_stderr
,
351 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
352 reg_num
, reg_offset
, buf_offset
, length
);
353 if (mips_debug
&& out
!= NULL
)
356 fprintf_unfiltered (gdb_stdlog
, "out ");
357 for (i
= 0; i
< length
; i
++)
358 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
361 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
364 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
366 if (mips_debug
&& in
!= NULL
)
369 fprintf_unfiltered (gdb_stdlog
, "in ");
370 for (i
= 0; i
< length
; i
++)
371 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
374 fprintf_unfiltered (gdb_stdlog
, "\n");
377 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
378 compatiblity mode. A return value of 1 means that we have
379 physical 64-bit registers, but should treat them as 32-bit registers. */
382 mips2_fp_compat (void)
384 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
386 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
391 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
392 in all the places we deal with FP registers. PR gdb/413. */
393 /* Otherwise check the FR bit in the status register - it controls
394 the FP compatiblity mode. If it is clear we are in compatibility
396 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
403 /* The amount of space reserved on the stack for registers. This is
404 different to MIPS_ABI_REGSIZE as it determines the alignment of
405 data allocated after the registers have run out. */
407 static const char *mips_stack_argsize_string
= size_auto
;
410 mips_stack_argsize (struct gdbarch
*gdbarch
)
412 if (mips_stack_argsize_string
== size_auto
)
413 return mips_abi_regsize (gdbarch
);
414 else if (mips_stack_argsize_string
== size_64
)
416 else /* if (mips_stack_argsize_string == size_32) */
420 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
422 struct mips_frame_cache
;
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
425 struct mips_frame_cache
*);
426 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
429 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
431 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
433 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
435 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
437 static struct type
*mips_float_register_type (void);
438 static struct type
*mips_double_register_type (void);
440 /* The list of available "set mips " and "show mips " commands */
442 static struct cmd_list_element
*setmipscmdlist
= NULL
;
443 static struct cmd_list_element
*showmipscmdlist
= NULL
;
445 /* Integer registers 0 thru 31 are handled explicitly by
446 mips_register_name(). Processor specific registers 32 and above
447 are listed in the followign tables. */
450 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
454 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
455 "sr", "lo", "hi", "bad", "cause", "pc",
456 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
457 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
458 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
459 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
460 "fsr", "fir", "" /*"fp" */ , "",
461 "", "", "", "", "", "", "", "",
462 "", "", "", "", "", "", "", "",
465 /* Names of IDT R3041 registers. */
467 static const char *mips_r3041_reg_names
[] = {
468 "sr", "lo", "hi", "bad", "cause", "pc",
469 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
470 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
471 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
472 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
473 "fsr", "fir", "", /*"fp" */ "",
474 "", "", "bus", "ccfg", "", "", "", "",
475 "", "", "port", "cmp", "", "", "epc", "prid",
478 /* Names of tx39 registers. */
480 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
481 "sr", "lo", "hi", "bad", "cause", "pc",
482 "", "", "", "", "", "", "", "",
483 "", "", "", "", "", "", "", "",
484 "", "", "", "", "", "", "", "",
485 "", "", "", "", "", "", "", "",
487 "", "", "", "", "", "", "", "",
488 "", "", "config", "cache", "debug", "depc", "epc", ""
491 /* Names of IRIX registers. */
492 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
493 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
494 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
495 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
496 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
497 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
501 /* Return the name of the register corresponding to REGNO. */
503 mips_register_name (int regno
)
505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
506 /* GPR names for all ABIs other than n32/n64. */
507 static char *mips_gpr_names
[] = {
508 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
509 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
510 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
511 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
514 /* GPR names for n32 and n64 ABIs. */
515 static char *mips_n32_n64_gpr_names
[] = {
516 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
517 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
518 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
519 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
522 enum mips_abi abi
= mips_abi (current_gdbarch
);
524 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
525 don't make the raw register names visible. */
526 int rawnum
= regno
% NUM_REGS
;
527 if (regno
< NUM_REGS
)
530 /* The MIPS integer registers are always mapped from 0 to 31. The
531 names of the registers (which reflects the conventions regarding
532 register use) vary depending on the ABI. */
533 if (0 <= rawnum
&& rawnum
< 32)
535 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
536 return mips_n32_n64_gpr_names
[rawnum
];
538 return mips_gpr_names
[rawnum
];
540 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
542 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
543 return tdep
->mips_processor_reg_names
[rawnum
- 32];
546 internal_error (__FILE__
, __LINE__
,
547 "mips_register_name: bad register number %d", rawnum
);
550 /* Return the groups that a MIPS register can be categorised into. */
553 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
554 struct reggroup
*reggroup
)
559 int rawnum
= regnum
% NUM_REGS
;
560 int pseudo
= regnum
/ NUM_REGS
;
561 if (reggroup
== all_reggroup
)
563 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
564 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
565 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
566 (gdbarch), as not all architectures are multi-arch. */
567 raw_p
= rawnum
< NUM_REGS
;
568 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
570 if (reggroup
== float_reggroup
)
571 return float_p
&& pseudo
;
572 if (reggroup
== vector_reggroup
)
573 return vector_p
&& pseudo
;
574 if (reggroup
== general_reggroup
)
575 return (!vector_p
&& !float_p
) && pseudo
;
576 /* Save the pseudo registers. Need to make certain that any code
577 extracting register values from a saved register cache also uses
579 if (reggroup
== save_reggroup
)
580 return raw_p
&& pseudo
;
581 /* Restore the same pseudo register. */
582 if (reggroup
== restore_reggroup
)
583 return raw_p
&& pseudo
;
587 /* Map the symbol table registers which live in the range [1 *
588 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
589 registers. Take care of alignment and size problems. */
592 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
593 int cookednum
, void *buf
)
595 int rawnum
= cookednum
% NUM_REGS
;
596 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
597 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
598 regcache_raw_read (regcache
, rawnum
, buf
);
599 else if (register_size (gdbarch
, rawnum
) >
600 register_size (gdbarch
, cookednum
))
602 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
603 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
604 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
606 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
609 internal_error (__FILE__
, __LINE__
, "bad register size");
613 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
614 struct regcache
*regcache
, int cookednum
,
617 int rawnum
= cookednum
% NUM_REGS
;
618 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
619 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
620 regcache_raw_write (regcache
, rawnum
, buf
);
621 else if (register_size (gdbarch
, rawnum
) >
622 register_size (gdbarch
, cookednum
))
624 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
625 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
626 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
628 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
631 internal_error (__FILE__
, __LINE__
, "bad register size");
634 /* Table to translate MIPS16 register field to actual register number. */
635 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
637 /* Heuristic_proc_start may hunt through the text section for a long
638 time across a 2400 baud serial line. Allows the user to limit this
641 static unsigned int heuristic_fence_post
= 0;
643 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
644 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
645 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
646 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
647 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
648 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
649 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
650 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
651 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
652 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
653 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
654 this will corrupt pdr.iline. Fortunately we don't use it. */
655 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
656 #define _PROC_MAGIC_ 0x0F0F0F0F
658 /* Number of bytes of storage in the actual machine representation for
659 register N. NOTE: This defines the pseudo register type so need to
660 rebuild the architecture vector. */
662 static int mips64_transfers_32bit_regs_p
= 0;
665 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
666 struct cmd_list_element
*c
)
668 struct gdbarch_info info
;
669 gdbarch_info_init (&info
);
670 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
671 instead of relying on globals. Doing that would let generic code
672 handle the search for this specific architecture. */
673 if (!gdbarch_update_p (info
))
675 mips64_transfers_32bit_regs_p
= 0;
676 error ("32-bit compatibility mode not supported");
680 /* Convert to/from a register and the corresponding memory value. */
683 mips_convert_register_p (int regnum
, struct type
*type
)
685 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
686 && register_size (current_gdbarch
, regnum
) == 4
687 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
688 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
689 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
693 mips_register_to_value (struct frame_info
*frame
, int regnum
,
694 struct type
*type
, void *to
)
696 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
697 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
701 mips_value_to_register (struct frame_info
*frame
, int regnum
,
702 struct type
*type
, const void *from
)
704 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
705 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
708 /* Return the GDB type object for the "standard" data type of data in
712 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
714 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
715 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
716 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
718 /* The floating-point registers raw, or cooked, always match
719 mips_isa_regsize(), and also map 1:1, byte for byte. */
720 switch (gdbarch_byte_order (gdbarch
))
723 if (mips_isa_regsize (gdbarch
) == 4)
724 return builtin_type_ieee_single_big
;
726 return builtin_type_ieee_double_big
;
727 case BFD_ENDIAN_LITTLE
:
728 if (mips_isa_regsize (gdbarch
) == 4)
729 return builtin_type_ieee_single_little
;
731 return builtin_type_ieee_double_little
;
732 case BFD_ENDIAN_UNKNOWN
:
734 internal_error (__FILE__
, __LINE__
, "bad switch");
737 else if (regnum
< NUM_REGS
)
739 /* The raw or ISA registers. These are all sized according to
741 if (mips_isa_regsize (gdbarch
) == 4)
742 return builtin_type_int32
;
744 return builtin_type_int64
;
748 /* The cooked or ABI registers. These are sized according to
749 the ABI (with a few complications). */
750 if (regnum
>= (NUM_REGS
751 + mips_regnum (current_gdbarch
)->fp_control_status
)
752 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
753 /* The pseudo/cooked view of the embedded registers is always
754 32-bit. The raw view is handled below. */
755 return builtin_type_int32
;
756 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
757 /* The target, while possibly using a 64-bit register buffer,
758 is only transfering 32-bits of each integer register.
759 Reflect this in the cooked/pseudo (ABI) register value. */
760 return builtin_type_int32
;
761 else if (mips_abi_regsize (gdbarch
) == 4)
762 /* The ABI is restricted to 32-bit registers (the ISA could be
764 return builtin_type_int32
;
767 return builtin_type_int64
;
771 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
776 return read_signed_register (MIPS_SP_REGNUM
);
779 /* Should the upper word of 64-bit addresses be zeroed? */
780 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
783 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
785 switch (mask_address_var
)
787 case AUTO_BOOLEAN_TRUE
:
789 case AUTO_BOOLEAN_FALSE
:
792 case AUTO_BOOLEAN_AUTO
:
793 return tdep
->default_mask_address_p
;
795 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
801 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
804 switch (mask_address_var
)
806 case AUTO_BOOLEAN_TRUE
:
807 printf_filtered ("The 32 bit mips address mask is enabled\n");
809 case AUTO_BOOLEAN_FALSE
:
810 printf_filtered ("The 32 bit mips address mask is disabled\n");
812 case AUTO_BOOLEAN_AUTO
:
814 ("The 32 bit address mask is set automatically. Currently %s\n",
815 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
818 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
823 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
826 pc_is_mips16 (bfd_vma memaddr
)
828 struct minimal_symbol
*sym
;
830 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
831 if (is_mips16_addr (memaddr
))
834 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
835 the high bit of the info field. Use this to decide if the function is
836 MIPS16 or normal MIPS. */
837 sym
= lookup_minimal_symbol_by_pc (memaddr
);
839 return msymbol_is_special (sym
);
844 /* MIPS believes that the PC has a sign extended value. Perhaps the
845 all registers should be sign extended for simplicity? */
848 mips_read_pc (ptid_t ptid
)
850 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
854 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
856 return frame_unwind_register_signed (next_frame
,
857 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
860 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
861 dummy frame. The frame ID's base needs to match the TOS value
862 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
865 static struct frame_id
866 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
868 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
869 frame_pc_unwind (next_frame
));
873 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
875 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
878 /* This returns the PC of the first inst after the prologue. If we can't
879 find the prologue, then return 0. */
882 after_prologue (CORE_ADDR pc
)
884 mips_extra_func_info_t proc_desc
;
885 struct symtab_and_line sal
;
886 CORE_ADDR func_addr
, func_end
;
887 CORE_ADDR startaddr
= 0;
889 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
890 attempt to read the stack pointer from the current machine state,
891 because the current machine state has nothing to do with the
892 information we need from the proc_desc; and the process may or
893 may not exist right now. */
894 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
897 /* IF this is the topmost frame AND (this proc does not have
898 debugging information OR the PC is in the procedure prologue)
899 THEN create a "heuristic" proc_desc (by analyzing the actual
900 code) to replace the "official" proc_desc. */
901 struct symtab_and_line val
;
902 if (PROC_SYMBOL (proc_desc
))
904 val
= find_pc_line (BLOCK_START
905 (SYMBOL_BLOCK_VALUE (PROC_SYMBOL (proc_desc
))),
907 val
.pc
= val
.end
? val
.end
: pc
;
909 if (!PROC_SYMBOL (proc_desc
) || pc
< val
.pc
)
911 mips_extra_func_info_t found_heuristic
=
912 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
, NULL
);
914 proc_desc
= found_heuristic
;
920 startaddr
= heuristic_proc_start (pc
);
922 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
, NULL
);
927 /* If function is frameless, then we need to do it the hard way. I
928 strongly suspect that frameless always means prologueless... */
929 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
930 && PROC_FRAME_OFFSET (proc_desc
) == 0)
934 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
935 return 0; /* Unknown */
937 sal
= find_pc_line (func_addr
, 0);
939 if (sal
.end
< func_end
)
942 /* The line after the prologue is after the end of the function. In this
943 case, tell the caller to find the prologue the hard way. */
948 /* Fetch and return instruction from the specified location. If the PC
949 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
952 mips_fetch_instruction (CORE_ADDR addr
)
954 char buf
[MIPS_INSTLEN
];
958 if (pc_is_mips16 (addr
))
960 instlen
= MIPS16_INSTLEN
;
961 addr
= unmake_mips16_addr (addr
);
964 instlen
= MIPS_INSTLEN
;
965 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
967 memory_error (status
, addr
);
968 return extract_unsigned_integer (buf
, instlen
);
972 mips16_fetch_instruction (CORE_ADDR addr
)
974 char buf
[MIPS_INSTLEN
];
978 instlen
= MIPS16_INSTLEN
;
979 addr
= unmake_mips16_addr (addr
);
980 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
982 memory_error (status
, addr
);
983 return extract_unsigned_integer (buf
, instlen
);
986 /* These the fields of 32 bit mips instructions */
987 #define mips32_op(x) (x >> 26)
988 #define itype_op(x) (x >> 26)
989 #define itype_rs(x) ((x >> 21) & 0x1f)
990 #define itype_rt(x) ((x >> 16) & 0x1f)
991 #define itype_immediate(x) (x & 0xffff)
993 #define jtype_op(x) (x >> 26)
994 #define jtype_target(x) (x & 0x03ffffff)
996 #define rtype_op(x) (x >> 26)
997 #define rtype_rs(x) ((x >> 21) & 0x1f)
998 #define rtype_rt(x) ((x >> 16) & 0x1f)
999 #define rtype_rd(x) ((x >> 11) & 0x1f)
1000 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1001 #define rtype_funct(x) (x & 0x3f)
1004 mips32_relative_offset (unsigned long inst
)
1007 x
= itype_immediate (inst
);
1008 if (x
& 0x8000) /* sign bit set */
1010 x
|= 0xffff0000; /* sign extension */
1016 /* Determine whate to set a single step breakpoint while considering
1017 branch prediction */
1019 mips32_next_pc (CORE_ADDR pc
)
1023 inst
= mips_fetch_instruction (pc
);
1024 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1026 if (itype_op (inst
) >> 2 == 5)
1027 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1029 op
= (itype_op (inst
) & 0x03);
1039 goto greater_branch
;
1044 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1045 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1047 int tf
= itype_rt (inst
) & 0x01;
1048 int cnum
= itype_rt (inst
) >> 2;
1050 read_signed_register (mips_regnum (current_gdbarch
)->
1052 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1054 if (((cond
>> cnum
) & 0x01) == tf
)
1055 pc
+= mips32_relative_offset (inst
) + 4;
1060 pc
+= 4; /* Not a branch, next instruction is easy */
1063 { /* This gets way messy */
1065 /* Further subdivide into SPECIAL, REGIMM and other */
1066 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1068 case 0: /* SPECIAL */
1069 op
= rtype_funct (inst
);
1074 /* Set PC to that address */
1075 pc
= read_signed_register (rtype_rs (inst
));
1081 break; /* end SPECIAL */
1082 case 1: /* REGIMM */
1084 op
= itype_rt (inst
); /* branch condition */
1089 case 16: /* BLTZAL */
1090 case 18: /* BLTZALL */
1092 if (read_signed_register (itype_rs (inst
)) < 0)
1093 pc
+= mips32_relative_offset (inst
) + 4;
1095 pc
+= 8; /* after the delay slot */
1099 case 17: /* BGEZAL */
1100 case 19: /* BGEZALL */
1101 if (read_signed_register (itype_rs (inst
)) >= 0)
1102 pc
+= mips32_relative_offset (inst
) + 4;
1104 pc
+= 8; /* after the delay slot */
1106 /* All of the other instructions in the REGIMM category */
1111 break; /* end REGIMM */
1116 reg
= jtype_target (inst
) << 2;
1117 /* Upper four bits get never changed... */
1118 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1121 /* FIXME case JALX : */
1124 reg
= jtype_target (inst
) << 2;
1125 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1126 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1128 break; /* The new PC will be alternate mode */
1129 case 4: /* BEQ, BEQL */
1131 if (read_signed_register (itype_rs (inst
)) ==
1132 read_signed_register (itype_rt (inst
)))
1133 pc
+= mips32_relative_offset (inst
) + 4;
1137 case 5: /* BNE, BNEL */
1139 if (read_signed_register (itype_rs (inst
)) !=
1140 read_signed_register (itype_rt (inst
)))
1141 pc
+= mips32_relative_offset (inst
) + 4;
1145 case 6: /* BLEZ, BLEZL */
1146 if (read_signed_register (itype_rs (inst
)) <= 0)
1147 pc
+= mips32_relative_offset (inst
) + 4;
1153 greater_branch
: /* BGTZ, BGTZL */
1154 if (read_signed_register (itype_rs (inst
)) > 0)
1155 pc
+= mips32_relative_offset (inst
) + 4;
1162 } /* mips32_next_pc */
1164 /* Decoding the next place to set a breakpoint is irregular for the
1165 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1166 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1167 We dont want to set a single step instruction on the extend instruction
1171 /* Lots of mips16 instruction formats */
1172 /* Predicting jumps requires itype,ritype,i8type
1173 and their extensions extItype,extritype,extI8type
1175 enum mips16_inst_fmts
1177 itype
, /* 0 immediate 5,10 */
1178 ritype
, /* 1 5,3,8 */
1179 rrtype
, /* 2 5,3,3,5 */
1180 rritype
, /* 3 5,3,3,5 */
1181 rrrtype
, /* 4 5,3,3,3,2 */
1182 rriatype
, /* 5 5,3,3,1,4 */
1183 shifttype
, /* 6 5,3,3,3,2 */
1184 i8type
, /* 7 5,3,8 */
1185 i8movtype
, /* 8 5,3,3,5 */
1186 i8mov32rtype
, /* 9 5,3,5,3 */
1187 i64type
, /* 10 5,3,8 */
1188 ri64type
, /* 11 5,3,3,5 */
1189 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1190 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1191 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1192 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1193 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1194 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1195 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1196 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1197 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1198 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1200 /* I am heaping all the fields of the formats into one structure and
1201 then, only the fields which are involved in instruction extension */
1205 unsigned int regx
; /* Function in i8 type */
1210 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1211 for the bits which make up the immediatate extension. */
1214 extended_offset (unsigned int extension
)
1217 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1219 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1221 value
|= extension
& 0x01f; /* extract 4:0 */
1225 /* Only call this function if you know that this is an extendable
1226 instruction, It wont malfunction, but why make excess remote memory references?
1227 If the immediate operands get sign extended or somthing, do it after
1228 the extension is performed.
1230 /* FIXME: Every one of these cases needs to worry about sign extension
1231 when the offset is to be used in relative addressing */
1235 fetch_mips_16 (CORE_ADDR pc
)
1238 pc
&= 0xfffffffe; /* clear the low order bit */
1239 target_read_memory (pc
, buf
, 2);
1240 return extract_unsigned_integer (buf
, 2);
1244 unpack_mips16 (CORE_ADDR pc
,
1245 unsigned int extension
,
1247 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1252 switch (insn_format
)
1259 value
= extended_offset (extension
);
1260 value
= value
<< 11; /* rom for the original value */
1261 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1265 value
= inst
& 0x7ff;
1266 /* FIXME : Consider sign extension */
1275 { /* A register identifier and an offset */
1276 /* Most of the fields are the same as I type but the
1277 immediate value is of a different length */
1281 value
= extended_offset (extension
);
1282 value
= value
<< 8; /* from the original instruction */
1283 value
|= inst
& 0xff; /* eleven bits from instruction */
1284 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1285 if (value
& 0x4000) /* test the sign bit , bit 26 */
1287 value
&= ~0x3fff; /* remove the sign bit */
1293 value
= inst
& 0xff; /* 8 bits */
1294 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1295 /* FIXME: Do sign extension , this format needs it */
1296 if (value
& 0x80) /* THIS CONFUSES ME */
1298 value
&= 0xef; /* remove the sign bit */
1308 unsigned long value
;
1309 unsigned int nexthalf
;
1310 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1311 value
= value
<< 16;
1312 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1320 internal_error (__FILE__
, __LINE__
, "bad switch");
1322 upk
->offset
= offset
;
1329 add_offset_16 (CORE_ADDR pc
, int offset
)
1331 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1335 extended_mips16_next_pc (CORE_ADDR pc
,
1336 unsigned int extension
, unsigned int insn
)
1338 int op
= (insn
>> 11);
1341 case 2: /* Branch */
1344 struct upk_mips16 upk
;
1345 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1346 offset
= upk
.offset
;
1352 pc
+= (offset
<< 1) + 2;
1355 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1357 struct upk_mips16 upk
;
1358 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1359 pc
= add_offset_16 (pc
, upk
.offset
);
1360 if ((insn
>> 10) & 0x01) /* Exchange mode */
1361 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1368 struct upk_mips16 upk
;
1370 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1371 reg
= read_signed_register (upk
.regx
);
1373 pc
+= (upk
.offset
<< 1) + 2;
1380 struct upk_mips16 upk
;
1382 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1383 reg
= read_signed_register (upk
.regx
);
1385 pc
+= (upk
.offset
<< 1) + 2;
1390 case 12: /* I8 Formats btez btnez */
1392 struct upk_mips16 upk
;
1394 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1395 /* upk.regx contains the opcode */
1396 reg
= read_signed_register (24); /* Test register is 24 */
1397 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1398 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1399 /* pc = add_offset_16(pc,upk.offset) ; */
1400 pc
+= (upk
.offset
<< 1) + 2;
1405 case 29: /* RR Formats JR, JALR, JALR-RA */
1407 struct upk_mips16 upk
;
1408 /* upk.fmt = rrtype; */
1413 upk
.regx
= (insn
>> 8) & 0x07;
1414 upk
.regy
= (insn
>> 5) & 0x07;
1422 break; /* Function return instruction */
1428 break; /* BOGUS Guess */
1430 pc
= read_signed_register (reg
);
1437 /* This is an instruction extension. Fetch the real instruction
1438 (which follows the extension) and decode things based on
1442 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1455 mips16_next_pc (CORE_ADDR pc
)
1457 unsigned int insn
= fetch_mips_16 (pc
);
1458 return extended_mips16_next_pc (pc
, 0, insn
);
1461 /* The mips_next_pc function supports single_step when the remote
1462 target monitor or stub is not developed enough to do a single_step.
1463 It works by decoding the current instruction and predicting where a
1464 branch will go. This isnt hard because all the data is available.
1465 The MIPS32 and MIPS16 variants are quite different */
1467 mips_next_pc (CORE_ADDR pc
)
1470 return mips16_next_pc (pc
);
1472 return mips32_next_pc (pc
);
1475 struct mips_frame_cache
1478 struct trad_frame_saved_reg
*saved_regs
;
1482 static struct mips_frame_cache
*
1483 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1485 CORE_ADDR startaddr
= 0;
1486 mips_extra_func_info_t proc_desc
;
1487 struct mips_frame_cache
*cache
;
1488 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1489 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1490 /* r0 bit means kernel trap */
1492 /* What registers have been saved? Bitmasks. */
1493 unsigned long gen_mask
, float_mask
;
1495 if ((*this_cache
) != NULL
)
1496 return (*this_cache
);
1497 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1498 (*this_cache
) = cache
;
1499 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1501 /* Get the mdebug proc descriptor. */
1502 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1504 /* Must be true. This is only called when the sniffer detected a
1506 gdb_assert (proc_desc
!= NULL
);
1508 /* Extract the frame's base. */
1509 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1510 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1512 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1513 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1514 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1516 /* Must be true. The in_prologue case is left for the heuristic
1517 unwinder. This is always used on kernel traps. */
1518 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1521 /* Fill in the offsets for the registers which gen_mask says were
1524 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1527 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1528 if (gen_mask
& 0x80000000)
1530 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1531 reg_position
-= mips_abi_regsize (gdbarch
);
1535 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1536 order of that normally used by gcc. Therefore, we have to fetch
1537 the first instruction of the function, and if it's an entry
1538 instruction that saves $s0 or $s1, correct their saved addresses. */
1539 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1541 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1542 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1546 int sreg_count
= (inst
>> 6) & 3;
1548 /* Check if the ra register was pushed on the stack. */
1549 CORE_ADDR reg_position
= (cache
->base
1550 + PROC_REG_OFFSET (proc_desc
));
1552 reg_position
-= mips_abi_regsize (gdbarch
);
1554 /* Check if the s0 and s1 registers were pushed on the
1556 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1558 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1560 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1561 reg_position
-= mips_abi_regsize (gdbarch
);
1566 /* Fill in the offsets for the registers which float_mask says were
1569 CORE_ADDR reg_position
= (cache
->base
1570 + PROC_FREG_OFFSET (proc_desc
));
1572 /* Fill in the offsets for the float registers which float_mask
1574 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1575 if (float_mask
& 0x80000000)
1577 if (mips_abi_regsize (gdbarch
) == 4
1578 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1580 /* On a big endian 32 bit ABI, floating point registers
1581 are paired to form doubles such that the most
1582 significant part is in $f[N+1] and the least
1583 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1584 registers are also spilled as a pair and stored as a
1587 When little-endian the least significant part is
1588 stored first leading to the memory order $f[N] and
1591 Unfortunately, when big-endian the most significant
1592 part of the double is stored first, and the least
1593 significant is stored second. This leads to the
1594 registers being ordered in memory as firt $f[N+1] and
1597 For the big-endian case make certain that the
1598 addresses point at the correct (swapped) locations
1599 $f[N] and $f[N+1] pair (keep in mind that
1600 reg_position is decremented each time through the
1603 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1604 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1606 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1607 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1610 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1611 .addr
= reg_position
;
1612 reg_position
-= mips_abi_regsize (gdbarch
);
1615 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1616 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1619 /* SP_REGNUM, contains the value and not the address. */
1620 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1622 return (*this_cache
);
1626 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1627 struct frame_id
*this_id
)
1629 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1631 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1635 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1637 int regnum
, int *optimizedp
,
1638 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1639 int *realnump
, void *valuep
)
1641 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1643 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1644 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1647 static const struct frame_unwind mips_mdebug_frame_unwind
=
1650 mips_mdebug_frame_this_id
,
1651 mips_mdebug_frame_prev_register
1654 static const struct frame_unwind
*
1655 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1657 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1658 CORE_ADDR startaddr
= 0;
1659 mips_extra_func_info_t proc_desc
;
1662 /* Only use the mdebug frame unwinder on mdebug frames where all the
1663 registers have been saved. Leave hard cases such as no mdebug or
1664 in prologue for the heuristic unwinders. */
1666 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1667 if (proc_desc
== NULL
)
1670 /* Not sure exactly what kernel_trap means, but if it means the
1671 kernel saves the registers without a prologue doing it, we better
1672 not examine the prologue to see whether registers have been saved
1674 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1676 return &mips_mdebug_frame_unwind
;
1678 /* In any frame other than the innermost or a frame interrupted by a
1679 signal, we assume that all registers have been saved. This
1680 assumes that all register saves in a function happen before the
1681 first function call. */
1682 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1683 return &mips_mdebug_frame_unwind
;
1689 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1692 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1697 static const struct frame_base mips_mdebug_frame_base
= {
1698 &mips_mdebug_frame_unwind
,
1699 mips_mdebug_frame_base_address
,
1700 mips_mdebug_frame_base_address
,
1701 mips_mdebug_frame_base_address
1704 static const struct frame_base
*
1705 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1707 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1708 return &mips_mdebug_frame_base
;
1713 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1714 Procedures that use the 32-bit instruction set are handled by the
1715 mips_insn32 unwinder. */
1717 static struct mips_frame_cache
*
1718 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1720 mips_extra_func_info_t proc_desc
;
1721 struct mips_frame_cache
*cache
;
1722 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1723 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1724 /* r0 bit means kernel trap */
1726 /* What registers have been saved? Bitmasks. */
1727 unsigned long gen_mask
, float_mask
;
1729 if ((*this_cache
) != NULL
)
1730 return (*this_cache
);
1731 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1732 (*this_cache
) = cache
;
1733 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1735 /* Synthesize a proc descriptor. */
1737 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1738 CORE_ADDR start_addr
;
1740 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1741 if (start_addr
== 0)
1742 start_addr
= heuristic_proc_start (pc
);
1744 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, *this_cache
);
1747 /* SP_REGNUM, contains the value and not the address. */
1748 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1750 return (*this_cache
);
1754 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1755 struct frame_id
*this_id
)
1757 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1759 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1763 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1765 int regnum
, int *optimizedp
,
1766 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1767 int *realnump
, void *valuep
)
1769 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1771 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1772 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1775 static const struct frame_unwind mips_insn16_frame_unwind
=
1778 mips_insn16_frame_this_id
,
1779 mips_insn16_frame_prev_register
1782 static const struct frame_unwind
*
1783 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1785 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1786 if (pc_is_mips16 (pc
))
1787 return &mips_insn16_frame_unwind
;
1792 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1795 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1800 static const struct frame_base mips_insn16_frame_base
=
1802 &mips_insn16_frame_unwind
,
1803 mips_insn16_frame_base_address
,
1804 mips_insn16_frame_base_address
,
1805 mips_insn16_frame_base_address
1808 static const struct frame_base
*
1809 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1811 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1812 return &mips_insn16_frame_base
;
1817 /* Heuristic unwinder for procedures using 32-bit instructions (covers
1818 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
1819 instructions (a.k.a. MIPS16) are handled by the mips_insn16
1822 static struct mips_frame_cache
*
1823 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1825 mips_extra_func_info_t proc_desc
;
1826 struct mips_frame_cache
*cache
;
1827 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1828 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1829 /* r0 bit means kernel trap */
1831 /* What registers have been saved? Bitmasks. */
1832 unsigned long gen_mask
, float_mask
;
1834 if ((*this_cache
) != NULL
)
1835 return (*this_cache
);
1837 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1838 (*this_cache
) = cache
;
1839 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1841 /* Synthesize a proc descriptor. */
1843 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1844 CORE_ADDR start_addr
;
1846 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1847 if (start_addr
== 0)
1848 start_addr
= heuristic_proc_start (pc
);
1850 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
, *this_cache
);
1853 if (proc_desc
== NULL
)
1854 /* I'm not sure how/whether this can happen. Normally when we
1855 can't find a proc_desc, we "synthesize" one using
1856 heuristic_proc_desc and set the saved_regs right away. */
1859 /* SP_REGNUM, contains the value and not the address. */
1860 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1862 return (*this_cache
);
1866 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1867 struct frame_id
*this_id
)
1869 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1871 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1875 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
1877 int regnum
, int *optimizedp
,
1878 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1879 int *realnump
, void *valuep
)
1881 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1883 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1884 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1887 static const struct frame_unwind mips_insn32_frame_unwind
=
1890 mips_insn32_frame_this_id
,
1891 mips_insn32_frame_prev_register
1894 static const struct frame_unwind
*
1895 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
1897 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1898 if (! pc_is_mips16 (pc
))
1899 return &mips_insn32_frame_unwind
;
1904 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
1907 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
1912 static const struct frame_base mips_insn32_frame_base
=
1914 &mips_insn32_frame_unwind
,
1915 mips_insn32_frame_base_address
,
1916 mips_insn32_frame_base_address
,
1917 mips_insn32_frame_base_address
1920 static const struct frame_base
*
1921 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
1923 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
1924 return &mips_insn32_frame_base
;
1929 static struct trad_frame_cache
*
1930 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1933 CORE_ADDR start_addr
;
1934 CORE_ADDR stack_addr
;
1935 struct trad_frame_cache
*this_trad_cache
;
1937 if ((*this_cache
) != NULL
)
1938 return (*this_cache
);
1939 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
1940 (*this_cache
) = this_trad_cache
;
1942 /* The return address is in the link register. */
1943 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
1945 /* Frame ID, since it's a frameless / stackless function, no stack
1946 space is allocated and SP on entry is the current SP. */
1947 pc
= frame_pc_unwind (next_frame
);
1948 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1949 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
1950 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
1952 /* Assume that the frame's base is the same as the
1954 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
1956 return this_trad_cache
;
1960 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1961 struct frame_id
*this_id
)
1963 struct trad_frame_cache
*this_trad_cache
1964 = mips_stub_frame_cache (next_frame
, this_cache
);
1965 trad_frame_get_id (this_trad_cache
, this_id
);
1969 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
1971 int regnum
, int *optimizedp
,
1972 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1973 int *realnump
, void *valuep
)
1975 struct trad_frame_cache
*this_trad_cache
1976 = mips_stub_frame_cache (next_frame
, this_cache
);
1977 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
1978 lvalp
, addrp
, realnump
, valuep
);
1981 static const struct frame_unwind mips_stub_frame_unwind
=
1984 mips_stub_frame_this_id
,
1985 mips_stub_frame_prev_register
1988 static const struct frame_unwind
*
1989 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
1991 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1992 if (in_plt_section (pc
, NULL
))
1993 return &mips_stub_frame_unwind
;
1999 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2002 struct trad_frame_cache
*this_trad_cache
2003 = mips_stub_frame_cache (next_frame
, this_cache
);
2004 return trad_frame_get_this_base (this_trad_cache
);
2007 static const struct frame_base mips_stub_frame_base
=
2009 &mips_stub_frame_unwind
,
2010 mips_stub_frame_base_address
,
2011 mips_stub_frame_base_address
,
2012 mips_stub_frame_base_address
2015 static const struct frame_base
*
2016 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2018 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2019 return &mips_stub_frame_base
;
2025 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2027 /* Always a pseudo. */
2028 gdb_assert (regno
>= NUM_REGS
);
2032 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2036 return frame_unwind_register_signed (fi
, regno
);
2040 /* mips_addr_bits_remove - remove useless address bits */
2043 mips_addr_bits_remove (CORE_ADDR addr
)
2045 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2046 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2047 /* This hack is a work-around for existing boards using PMON, the
2048 simulator, and any other 64-bit targets that doesn't have true
2049 64-bit addressing. On these targets, the upper 32 bits of
2050 addresses are ignored by the hardware. Thus, the PC or SP are
2051 likely to have been sign extended to all 1s by instruction
2052 sequences that load 32-bit addresses. For example, a typical
2053 piece of code that loads an address is this:
2055 lui $r2, <upper 16 bits>
2056 ori $r2, <lower 16 bits>
2058 But the lui sign-extends the value such that the upper 32 bits
2059 may be all 1s. The workaround is simply to mask off these
2060 bits. In the future, gcc may be changed to support true 64-bit
2061 addressing, and this masking will have to be disabled. */
2062 return addr
&= 0xffffffffUL
;
2067 /* mips_software_single_step() is called just before we want to resume
2068 the inferior, if we want to single-step it but there is no hardware
2069 or kernel single-step support (MIPS on GNU/Linux for example). We find
2070 the target of the coming instruction and breakpoint it.
2072 single_step is also called just after the inferior stops. If we had
2073 set up a simulated single-step, we undo our damage. */
2076 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2078 static CORE_ADDR next_pc
;
2079 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2080 static binsn_quantum break_mem
;
2083 if (insert_breakpoints_p
)
2085 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2086 next_pc
= mips_next_pc (pc
);
2088 target_insert_breakpoint (next_pc
, break_mem
);
2091 target_remove_breakpoint (next_pc
, break_mem
);
2094 static struct mips_extra_func_info temp_proc_desc
;
2096 /* Set a register's saved stack address in temp_saved_regs. If an
2097 address has already been set for this register, do nothing; this
2098 way we will only recognize the first save of a given register in a
2101 For simplicity, save the address in both [0 .. NUM_REGS) and
2102 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2103 is used as it is only second range (the ABI instead of ISA
2104 registers) that comes into play when finding saved registers in a
2108 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
2111 if (this_cache
!= NULL
2112 && this_cache
->saved_regs
[regnum
].addr
== -1)
2114 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
2115 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
2120 /* Test whether the PC points to the return instruction at the
2121 end of a function. */
2124 mips_about_to_return (CORE_ADDR pc
)
2126 if (pc_is_mips16 (pc
))
2127 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2128 generates a "jr $ra"; other times it generates code to load
2129 the return address from the stack to an accessible register (such
2130 as $a3), then a "jr" using that register. This second case
2131 is almost impossible to distinguish from an indirect jump
2132 used for switch statements, so we don't even try. */
2133 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2135 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2139 /* This fencepost looks highly suspicious to me. Removing it also
2140 seems suspicious as it could affect remote debugging across serial
2144 heuristic_proc_start (CORE_ADDR pc
)
2151 pc
= ADDR_BITS_REMOVE (pc
);
2153 fence
= start_pc
- heuristic_fence_post
;
2157 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2158 fence
= VM_MIN_ADDRESS
;
2160 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2162 /* search back for previous return */
2163 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2164 if (start_pc
< fence
)
2166 /* It's not clear to me why we reach this point when
2167 stop_soon, but with this test, at least we
2168 don't print out warnings for every child forked (eg, on
2169 decstation). 22apr93 rich@cygnus.com. */
2170 if (stop_soon
== NO_STOP_QUIETLY
)
2172 static int blurb_printed
= 0;
2174 warning ("GDB can't find the start of the function at 0x%s.",
2179 /* This actually happens frequently in embedded
2180 development, when you first connect to a board
2181 and your stack pointer and pc are nowhere in
2182 particular. This message needs to give people
2183 in that situation enough information to
2184 determine that it's no big deal. */
2185 printf_filtered ("\n\
2186 GDB is unable to find the start of the function at 0x%s\n\
2187 and thus can't determine the size of that function's stack frame.\n\
2188 This means that GDB may be unable to access that stack frame, or\n\
2189 the frames below it.\n\
2190 This problem is most likely caused by an invalid program counter or\n\
2192 However, if you think GDB should simply search farther back\n\
2193 from 0x%s for code which looks like the beginning of a\n\
2194 function, you can increase the range of the search using the `set\n\
2195 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2202 else if (pc_is_mips16 (start_pc
))
2204 unsigned short inst
;
2206 /* On MIPS16, any one of the following is likely to be the
2207 start of a function:
2211 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2212 inst
= mips_fetch_instruction (start_pc
);
2213 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2214 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2215 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2216 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2218 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2219 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2224 else if (mips_about_to_return (start_pc
))
2226 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2233 /* Fetch the immediate value from a MIPS16 instruction.
2234 If the previous instruction was an EXTEND, use it to extend
2235 the upper bits of the immediate value. This is a helper function
2236 for mips16_heuristic_proc_desc. */
2239 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2240 unsigned short inst
, /* current instruction */
2241 int nbits
, /* number of bits in imm field */
2242 int scale
, /* scale factor to be applied to imm */
2243 int is_signed
) /* is the imm field signed? */
2247 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2249 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2250 if (offset
& 0x8000) /* check for negative extend */
2251 offset
= 0 - (0x10000 - (offset
& 0xffff));
2252 return offset
| (inst
& 0x1f);
2256 int max_imm
= 1 << nbits
;
2257 int mask
= max_imm
- 1;
2258 int sign_bit
= max_imm
>> 1;
2260 offset
= inst
& mask
;
2261 if (is_signed
&& (offset
& sign_bit
))
2262 offset
= 0 - (max_imm
- offset
);
2263 return offset
* scale
;
2268 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2269 stream from start_pc to limit_pc. */
2272 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2274 struct frame_info
*next_frame
,
2275 struct mips_frame_cache
*this_cache
)
2278 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2279 long frame_offset
= 0; /* Size of stack frame. */
2280 long frame_adjust
= 0; /* Offset of FP from SP. */
2281 int frame_reg
= MIPS_SP_REGNUM
;
2282 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2283 unsigned inst
= 0; /* current instruction */
2284 unsigned entry_inst
= 0; /* the entry instruction */
2287 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2289 /* Save the previous instruction. If it's an EXTEND, we'll extract
2290 the immediate offset extension from it in mips16_get_imm. */
2293 /* Fetch and decode the instruction. */
2294 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2295 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2296 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2298 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2299 if (offset
< 0) /* negative stack adjustment? */
2300 frame_offset
-= offset
;
2302 /* Exit loop if a positive stack adjustment is found, which
2303 usually means that the stack cleanup code in the function
2304 epilogue is reached. */
2307 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2309 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2310 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2311 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2313 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2315 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2316 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2317 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2319 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2321 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2322 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2324 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2326 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2327 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2329 else if (inst
== 0x673d) /* move $s1, $sp */
2334 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2336 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2337 frame_addr
= sp
+ offset
;
2339 frame_adjust
= offset
;
2341 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2343 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2344 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2345 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2347 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2349 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2350 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2351 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
2353 else if ((inst
& 0xf81f) == 0xe809
2354 && (inst
& 0x700) != 0x700) /* entry */
2355 entry_inst
= inst
; /* save for later processing */
2356 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2357 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2360 /* The entry instruction is typically the first instruction in a function,
2361 and it stores registers at offsets relative to the value of the old SP
2362 (before the prologue). But the value of the sp parameter to this
2363 function is the new SP (after the prologue has been executed). So we
2364 can't calculate those offsets until we've seen the entire prologue,
2365 and can calculate what the old SP must have been. */
2366 if (entry_inst
!= 0)
2368 int areg_count
= (entry_inst
>> 8) & 7;
2369 int sreg_count
= (entry_inst
>> 6) & 3;
2371 /* The entry instruction always subtracts 32 from the SP. */
2374 /* Now we can calculate what the SP must have been at the
2375 start of the function prologue. */
2378 /* Check if a0-a3 were saved in the caller's argument save area. */
2379 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2381 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2382 offset
+= mips_abi_regsize (current_gdbarch
);
2385 /* Check if the ra register was pushed on the stack. */
2387 if (entry_inst
& 0x20)
2389 set_reg_offset (this_cache
, RA_REGNUM
, sp
+ offset
);
2390 offset
-= mips_abi_regsize (current_gdbarch
);
2393 /* Check if the s0 and s1 registers were pushed on the stack. */
2394 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2396 set_reg_offset (this_cache
, reg
, sp
+ offset
);
2397 offset
-= mips_abi_regsize (current_gdbarch
);
2401 if (this_cache
!= NULL
)
2404 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2405 + frame_offset
- frame_adjust
);
2406 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2407 be able to get rid of the assignment below, evetually. But it's
2408 still needed for now. */
2409 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2410 = this_cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2413 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
2414 order of that normally used by gcc. Therefore, we have to fetch
2415 the first instruction of the function, and if it's an entry
2416 instruction that saves $s0 or $s1, correct their saved addresses. */
2417 /* FIXME: brobecker/2004-10-10: This code was moved here from
2418 mips_insn16_frame_cache(), but can be merged with the block above
2419 handling entry_inst. Will be done in a separate pass, to make changes
2420 more atomic. Actually, this code seems completely redundant! */
2422 ULONGEST inst
= mips16_fetch_instruction (start_pc
);
2423 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2426 int sreg_count
= (inst
>> 6) & 3;
2427 CORE_ADDR reg_position
= (this_cache
->base
);
2429 /* Check if the ra register was pushed on the stack. */
2431 reg_position
-= mips_abi_regsize (current_gdbarch
);
2433 /* Check if the s0 and s1 registers were pushed on the stack. */
2434 /* NOTE: cagney/2004-02-08: Huh? This is doing no such check. */
2435 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2437 this_cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
2438 reg_position
-= mips_abi_regsize (current_gdbarch
);
2444 /* Mark all the registers as unset in the saved_regs array
2445 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2448 reset_saved_regs (struct mips_frame_cache
*this_cache
)
2450 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2454 const int num_regs
= NUM_REGS
;
2457 for (i
= 0; i
< num_regs
; i
++)
2459 this_cache
->saved_regs
[i
].addr
= -1;
2465 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2466 CORE_ADDR sp
, struct frame_info
*next_frame
,
2467 struct mips_frame_cache
*this_cache
)
2470 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2472 int frame_reg
= MIPS_SP_REGNUM
;
2477 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2479 unsigned long inst
, high_word
, low_word
;
2482 /* Fetch the instruction. */
2483 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2485 /* Save some code by pre-extracting some useful fields. */
2486 high_word
= (inst
>> 16) & 0xffff;
2487 low_word
= inst
& 0xffff;
2488 reg
= high_word
& 0x1f;
2490 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2491 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2492 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2494 if (low_word
& 0x8000) /* negative stack adjustment? */
2495 frame_offset
+= 0x10000 - low_word
;
2497 /* Exit loop if a positive stack adjustment is found, which
2498 usually means that the stack cleanup code in the function
2499 epilogue is reached. */
2502 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2504 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2506 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2508 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2510 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2512 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2514 /* Old gcc frame, r30 is virtual frame pointer. */
2515 if ((long) low_word
!= frame_offset
)
2516 frame_addr
= sp
+ low_word
;
2517 else if (frame_reg
== MIPS_SP_REGNUM
)
2519 unsigned alloca_adjust
;
2522 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2523 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2524 if (alloca_adjust
> 0)
2526 /* FP > SP + frame_size. This may be because of
2527 an alloca or somethings similar. Fix sp to
2528 "pre-alloca" value, and try again. */
2529 sp
+= alloca_adjust
;
2530 /* Need to reset the status of all registers. Otherwise,
2531 we will hit a guard that prevents the new address
2532 for each register to be recomputed during the second
2534 reset_saved_regs (this_cache
);
2539 /* move $30,$sp. With different versions of gas this will be either
2540 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2541 Accept any one of these. */
2542 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2544 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2545 if (frame_reg
== MIPS_SP_REGNUM
)
2547 unsigned alloca_adjust
;
2550 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2551 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2552 if (alloca_adjust
> 0)
2554 /* FP > SP + frame_size. This may be because of
2555 an alloca or somethings similar. Fix sp to
2556 "pre-alloca" value, and try again. */
2558 /* Need to reset the status of all registers. Otherwise,
2559 we will hit a guard that prevents the new address
2560 for each register to be recomputed during the second
2562 reset_saved_regs (this_cache
);
2567 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2569 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2573 if (this_cache
!= NULL
)
2576 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2578 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2579 this assignment below, eventually. But it's still needed
2581 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2582 = this_cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2586 static mips_extra_func_info_t
2587 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2588 struct frame_info
*next_frame
,
2589 struct mips_frame_cache
*this_cache
)
2593 /* Can be called when there's no process, and hence when there's no
2595 if (next_frame
!= NULL
)
2596 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2602 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2603 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2604 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2605 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2607 if (start_pc
+ 200 < limit_pc
)
2608 limit_pc
= start_pc
+ 200;
2609 if (pc_is_mips16 (start_pc
))
2610 mips16_heuristic_proc_desc (start_pc
, limit_pc
, sp
,
2611 next_frame
, this_cache
);
2613 mips32_heuristic_proc_desc (start_pc
, limit_pc
, sp
,
2614 next_frame
, this_cache
);
2615 return &temp_proc_desc
;
2618 struct mips_objfile_private
2624 /* Global used to communicate between non_heuristic_proc_desc and
2625 compare_pdr_entries within qsort (). */
2626 static bfd
*the_bfd
;
2629 compare_pdr_entries (const void *a
, const void *b
)
2631 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2632 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2636 else if (lhs
== rhs
)
2642 static mips_extra_func_info_t
2643 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2645 CORE_ADDR startaddr
;
2646 mips_extra_func_info_t proc_desc
;
2647 struct block
*b
= block_for_pc (pc
);
2649 struct obj_section
*sec
;
2650 struct mips_objfile_private
*priv
;
2652 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2654 *addrptr
= startaddr
;
2658 sec
= find_pc_section (pc
);
2661 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2663 /* Search the ".pdr" section generated by GAS. This includes most of
2664 the information normally found in ECOFF PDRs. */
2666 the_bfd
= sec
->objfile
->obfd
;
2668 && (the_bfd
->format
== bfd_object
2669 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2670 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2672 /* Right now GAS only outputs the address as a four-byte sequence.
2673 This means that we should not bother with this method on 64-bit
2674 targets (until that is fixed). */
2676 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2677 sizeof (struct mips_objfile_private
));
2679 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2681 else if (priv
== NULL
)
2685 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2686 sizeof (struct mips_objfile_private
));
2688 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2691 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2692 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2694 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2695 priv
->contents
, 0, priv
->size
);
2697 /* In general, the .pdr section is sorted. However, in the
2698 presence of multiple code sections (and other corner cases)
2699 it can become unsorted. Sort it so that we can use a faster
2701 qsort (priv
->contents
, priv
->size
/ 32, 32,
2702 compare_pdr_entries
);
2707 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2711 if (priv
->size
!= 0)
2718 high
= priv
->size
/ 32;
2720 /* We've found a .pdr section describing this objfile. We want to
2721 find the entry which describes this code address. The .pdr
2722 information is not very descriptive; we have only a function
2723 start address. We have to look for the closest entry, because
2724 the local symbol at the beginning of this function may have
2725 been stripped - so if we ask the symbol table for the start
2726 address we may get a preceding global function. */
2728 /* First, find the last .pdr entry starting at or before PC. */
2731 mid
= (low
+ high
) / 2;
2733 ptr
= priv
->contents
+ mid
* 32;
2734 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2735 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2736 SECT_OFF_TEXT (sec
->objfile
));
2743 while (low
!= high
);
2745 /* Both low and high point one past the PDR of interest. If
2746 both are zero, that means this PC is before any region
2747 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2751 ptr
= priv
->contents
+ (low
- 1) * 32;
2752 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2753 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2754 SECT_OFF_TEXT (sec
->objfile
));
2757 /* We don't have a range, so we have no way to know for sure
2758 whether we're in the correct PDR or a PDR for a preceding
2759 function and the current function was a stripped local
2760 symbol. But if the PDR's PC is at least as great as the
2761 best guess from the symbol table, assume that it does cover
2762 the right area; if a .pdr section is present at all then
2763 nearly every function will have an entry. The biggest exception
2764 will be the dynamic linker stubs; conveniently these are
2765 placed before .text instead of after. */
2767 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2769 struct symbol
*sym
= find_pc_function (pc
);
2774 /* Fill in what we need of the proc_desc. */
2775 proc_desc
= (mips_extra_func_info_t
)
2776 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2777 sizeof (struct mips_extra_func_info
));
2778 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2780 /* Only used for dummy frames. */
2781 PROC_HIGH_ADDR (proc_desc
) = 0;
2783 PROC_FRAME_OFFSET (proc_desc
)
2784 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2785 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2787 PROC_FRAME_ADJUST (proc_desc
) = 0;
2788 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2790 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2792 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2794 PROC_FREG_OFFSET (proc_desc
)
2795 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2796 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2798 proc_desc
->pdr
.isym
= (long) sym
;
2808 if (startaddr
> BLOCK_START (b
))
2810 /* This is the "pathological" case referred to in a comment in
2811 print_frame_info. It might be better to move this check into
2816 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2818 /* If we never found a PDR for this function in symbol reading, then
2819 examine prologues to find the information. */
2822 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2823 if (PROC_FRAME_REG (proc_desc
) == -1)
2832 /* MIPS stack frames are almost impenetrable. When execution stops,
2833 we basically have to look at symbol information for the function
2834 that we stopped in, which tells us *which* register (if any) is
2835 the base of the frame pointer, and what offset from that register
2836 the frame itself is at.
2838 This presents a problem when trying to examine a stack in memory
2839 (that isn't executing at the moment), using the "frame" command. We
2840 don't have a PC, nor do we have any registers except SP.
2842 This routine takes two arguments, SP and PC, and tries to make the
2843 cached frames look as if these two arguments defined a frame on the
2844 cache. This allows the rest of info frame to extract the important
2845 arguments without difficulty. */
2848 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2851 error ("MIPS frame specifications require two arguments: sp and pc");
2853 return create_new_frame (argv
[0], argv
[1]);
2856 /* According to the current ABI, should the type be passed in a
2857 floating-point register (assuming that there is space)? When there
2858 is no FPU, FP are not even considered as possibile candidates for
2859 FP registers and, consequently this returns false - forces FP
2860 arguments into integer registers. */
2863 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2865 return ((typecode
== TYPE_CODE_FLT
2867 && (typecode
== TYPE_CODE_STRUCT
2868 || typecode
== TYPE_CODE_UNION
)
2869 && TYPE_NFIELDS (arg_type
) == 1
2870 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2871 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2874 /* On o32, argument passing in GPRs depends on the alignment of the type being
2875 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2878 mips_type_needs_double_align (struct type
*type
)
2880 enum type_code typecode
= TYPE_CODE (type
);
2882 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2884 else if (typecode
== TYPE_CODE_STRUCT
)
2886 if (TYPE_NFIELDS (type
) < 1)
2888 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2890 else if (typecode
== TYPE_CODE_UNION
)
2894 n
= TYPE_NFIELDS (type
);
2895 for (i
= 0; i
< n
; i
++)
2896 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2903 /* Adjust the address downward (direction of stack growth) so that it
2904 is correctly aligned for a new stack frame. */
2906 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2908 return align_down (addr
, 16);
2911 /* Determine how a return value is stored within the MIPS register
2912 file, given the return type `valtype'. */
2914 struct return_value_word
2923 return_value_location (struct type
*valtype
,
2924 struct return_value_word
*hi
,
2925 struct return_value_word
*lo
)
2927 int len
= TYPE_LENGTH (valtype
);
2928 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2930 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2931 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2932 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2934 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
2936 /* We need to break a 64bit float in two 32 bit halves and
2937 spread them across a floating-point register pair. */
2938 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2939 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
2940 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2941 && register_size (current_gdbarch
,
2942 mips_regnum (current_gdbarch
)->
2943 fp0
) == 8) ? 4 : 0);
2944 hi
->reg_offset
= lo
->reg_offset
;
2945 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
2946 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
2952 /* The floating point value fits in a single floating-point
2954 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2955 && register_size (current_gdbarch
,
2956 mips_regnum (current_gdbarch
)->
2958 && len
== 4) ? 4 : 0);
2959 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
2970 /* Locate a result possibly spread across two registers. */
2972 lo
->reg
= regnum
+ 0;
2973 hi
->reg
= regnum
+ 1;
2974 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2975 && len
< mips_abi_regsize (current_gdbarch
))
2977 /* "un-left-justify" the value in the low register */
2978 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
2983 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
2984 && len
< mips_abi_regsize (current_gdbarch
) * 2
2985 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2986 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2988 /* "un-left-justify" the value spread across two registers. */
2989 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
2990 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
2992 hi
->len
= len
- lo
->len
;
2996 /* Only perform a partial copy of the second register. */
2999 if (len
> mips_abi_regsize (current_gdbarch
))
3001 lo
->len
= mips_abi_regsize (current_gdbarch
);
3002 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3010 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3011 && register_size (current_gdbarch
, regnum
) == 8
3012 && mips_abi_regsize (current_gdbarch
) == 4)
3014 /* Account for the fact that only the least-signficant part
3015 of the register is being used */
3016 lo
->reg_offset
+= 4;
3017 hi
->reg_offset
+= 4;
3020 hi
->buf_offset
= lo
->len
;
3024 /* Should call_function allocate stack space for a struct return? */
3027 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3029 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3030 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3033 /* Should call_function pass struct by reference?
3034 For each architecture, structs are passed either by
3035 value or by reference, depending on their size. */
3038 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3040 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3041 int len
= TYPE_LENGTH (check_typedef (type
));
3042 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3044 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3045 return (len
> mips_abi_regsize (current_gdbarch
));
3051 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3052 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3053 int nargs
, struct value
**args
, CORE_ADDR sp
,
3054 int struct_return
, CORE_ADDR struct_addr
)
3060 int stack_offset
= 0;
3061 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3062 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3064 /* For shared libraries, "t9" needs to point at the function
3066 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3068 /* Set the return address register to point to the entry point of
3069 the program, where a breakpoint lies in wait. */
3070 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3072 /* First ensure that the stack and structure return address (if any)
3073 are properly aligned. The stack has to be at least 64-bit
3074 aligned even on 32-bit machines, because doubles must be 64-bit
3075 aligned. For n32 and n64, stack frames need to be 128-bit
3076 aligned, so we round to this widest known alignment. */
3078 sp
= align_down (sp
, 16);
3079 struct_addr
= align_down (struct_addr
, 16);
3081 /* Now make space on the stack for the args. We allocate more
3082 than necessary for EABI, because the first few arguments are
3083 passed in registers, but that's OK. */
3084 for (argnum
= 0; argnum
< nargs
; argnum
++)
3085 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3086 mips_stack_argsize (gdbarch
));
3087 sp
-= align_up (len
, 16);
3090 fprintf_unfiltered (gdb_stdlog
,
3091 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3092 paddr_nz (sp
), (long) align_up (len
, 16));
3094 /* Initialize the integer and float register pointers. */
3096 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3098 /* The struct_return pointer occupies the first parameter-passing reg. */
3102 fprintf_unfiltered (gdb_stdlog
,
3103 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3104 argreg
, paddr_nz (struct_addr
));
3105 write_register (argreg
++, struct_addr
);
3108 /* Now load as many as possible of the first arguments into
3109 registers, and push the rest onto the stack. Loop thru args
3110 from first to last. */
3111 for (argnum
= 0; argnum
< nargs
; argnum
++)
3114 char valbuf
[MAX_REGISTER_SIZE
];
3115 struct value
*arg
= args
[argnum
];
3116 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3117 int len
= TYPE_LENGTH (arg_type
);
3118 enum type_code typecode
= TYPE_CODE (arg_type
);
3121 fprintf_unfiltered (gdb_stdlog
,
3122 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3123 argnum
+ 1, len
, (int) typecode
);
3125 /* The EABI passes structures that do not fit in a register by
3127 if (len
> mips_abi_regsize (gdbarch
)
3128 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3130 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3131 VALUE_ADDRESS (arg
));
3132 typecode
= TYPE_CODE_PTR
;
3133 len
= mips_abi_regsize (gdbarch
);
3136 fprintf_unfiltered (gdb_stdlog
, " push");
3139 val
= (char *) VALUE_CONTENTS (arg
);
3141 /* 32-bit ABIs always start floating point arguments in an
3142 even-numbered floating point register. Round the FP register
3143 up before the check to see if there are any FP registers
3144 left. Non MIPS_EABI targets also pass the FP in the integer
3145 registers so also round up normal registers. */
3146 if (mips_abi_regsize (gdbarch
) < 8
3147 && fp_register_arg_p (typecode
, arg_type
))
3149 if ((float_argreg
& 1))
3153 /* Floating point arguments passed in registers have to be
3154 treated specially. On 32-bit architectures, doubles
3155 are passed in register pairs; the even register gets
3156 the low word, and the odd register gets the high word.
3157 On non-EABI processors, the first two floating point arguments are
3158 also copied to general registers, because MIPS16 functions
3159 don't use float registers for arguments. This duplication of
3160 arguments in general registers can't hurt non-MIPS16 functions
3161 because those registers are normally skipped. */
3162 /* MIPS_EABI squeezes a struct that contains a single floating
3163 point value into an FP register instead of pushing it onto the
3165 if (fp_register_arg_p (typecode
, arg_type
)
3166 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3168 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3170 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3171 unsigned long regval
;
3173 /* Write the low word of the double to the even register(s). */
3174 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3176 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3177 float_argreg
, phex (regval
, 4));
3178 write_register (float_argreg
++, regval
);
3180 /* Write the high word of the double to the odd register(s). */
3181 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3183 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3184 float_argreg
, phex (regval
, 4));
3185 write_register (float_argreg
++, regval
);
3189 /* This is a floating point value that fits entirely
3190 in a single register. */
3191 /* On 32 bit ABI's the float_argreg is further adjusted
3192 above to ensure that it is even register aligned. */
3193 LONGEST regval
= extract_unsigned_integer (val
, len
);
3195 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3196 float_argreg
, phex (regval
, len
));
3197 write_register (float_argreg
++, regval
);
3202 /* Copy the argument to general registers or the stack in
3203 register-sized pieces. Large arguments are split between
3204 registers and stack. */
3205 /* Note: structs whose size is not a multiple of
3206 mips_abi_regsize() are treated specially: Irix cc passes
3207 them in registers where gcc sometimes puts them on the
3208 stack. For maximum compatibility, we will put them in
3210 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3211 && (len
% mips_abi_regsize (gdbarch
) != 0));
3213 /* Note: Floating-point values that didn't fit into an FP
3214 register are only written to memory. */
3217 /* Remember if the argument was written to the stack. */
3218 int stack_used_p
= 0;
3219 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3220 ? len
: mips_abi_regsize (gdbarch
));
3223 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3226 /* Write this portion of the argument to the stack. */
3227 if (argreg
> MIPS_LAST_ARG_REGNUM
3229 || fp_register_arg_p (typecode
, arg_type
))
3231 /* Should shorter than int integer values be
3232 promoted to int before being stored? */
3233 int longword_offset
= 0;
3236 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3238 if (mips_stack_argsize (gdbarch
) == 8
3239 && (typecode
== TYPE_CODE_INT
3240 || typecode
== TYPE_CODE_PTR
3241 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3242 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3243 else if ((typecode
== TYPE_CODE_STRUCT
3244 || typecode
== TYPE_CODE_UNION
)
3245 && (TYPE_LENGTH (arg_type
)
3246 < mips_stack_argsize (gdbarch
)))
3247 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3252 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3253 paddr_nz (stack_offset
));
3254 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3255 paddr_nz (longword_offset
));
3258 addr
= sp
+ stack_offset
+ longword_offset
;
3263 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3265 for (i
= 0; i
< partial_len
; i
++)
3267 fprintf_unfiltered (gdb_stdlog
, "%02x",
3271 write_memory (addr
, val
, partial_len
);
3274 /* Note!!! This is NOT an else clause. Odd sized
3275 structs may go thru BOTH paths. Floating point
3276 arguments will not. */
3277 /* Write this portion of the argument to a general
3278 purpose register. */
3279 if (argreg
<= MIPS_LAST_ARG_REGNUM
3280 && !fp_register_arg_p (typecode
, arg_type
))
3283 extract_unsigned_integer (val
, partial_len
);
3286 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3289 mips_abi_regsize (gdbarch
)));
3290 write_register (argreg
, regval
);
3297 /* Compute the the offset into the stack at which we
3298 will copy the next parameter.
3300 In the new EABI (and the NABI32), the stack_offset
3301 only needs to be adjusted when it has been used. */
3304 stack_offset
+= align_up (partial_len
,
3305 mips_stack_argsize (gdbarch
));
3309 fprintf_unfiltered (gdb_stdlog
, "\n");
3312 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3314 /* Return adjusted stack pointer. */
3318 /* Given a return value in `regbuf' with a type `valtype', extract and
3319 copy its value into `valbuf'. */
3322 mips_eabi_extract_return_value (struct type
*valtype
,
3323 char regbuf
[], char *valbuf
)
3325 struct return_value_word lo
;
3326 struct return_value_word hi
;
3327 return_value_location (valtype
, &hi
, &lo
);
3329 memcpy (valbuf
+ lo
.buf_offset
,
3330 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3331 lo
.reg_offset
, lo
.len
);
3334 memcpy (valbuf
+ hi
.buf_offset
,
3335 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3336 hi
.reg_offset
, hi
.len
);
3339 /* Given a return value in `valbuf' with a type `valtype', write it's
3340 value into the appropriate register. */
3343 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3345 char raw_buffer
[MAX_REGISTER_SIZE
];
3346 struct return_value_word lo
;
3347 struct return_value_word hi
;
3348 return_value_location (valtype
, &hi
, &lo
);
3350 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3351 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3352 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3353 raw_buffer
, register_size (current_gdbarch
,
3358 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3359 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3360 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3362 register_size (current_gdbarch
,
3367 /* N32/N64 ABI stuff. */
3370 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3371 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3372 int nargs
, struct value
**args
, CORE_ADDR sp
,
3373 int struct_return
, CORE_ADDR struct_addr
)
3379 int stack_offset
= 0;
3380 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3381 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3383 /* For shared libraries, "t9" needs to point at the function
3385 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3387 /* Set the return address register to point to the entry point of
3388 the program, where a breakpoint lies in wait. */
3389 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3391 /* First ensure that the stack and structure return address (if any)
3392 are properly aligned. The stack has to be at least 64-bit
3393 aligned even on 32-bit machines, because doubles must be 64-bit
3394 aligned. For n32 and n64, stack frames need to be 128-bit
3395 aligned, so we round to this widest known alignment. */
3397 sp
= align_down (sp
, 16);
3398 struct_addr
= align_down (struct_addr
, 16);
3400 /* Now make space on the stack for the args. */
3401 for (argnum
= 0; argnum
< nargs
; argnum
++)
3402 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3403 mips_stack_argsize (gdbarch
));
3404 sp
-= align_up (len
, 16);
3407 fprintf_unfiltered (gdb_stdlog
,
3408 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3409 paddr_nz (sp
), (long) align_up (len
, 16));
3411 /* Initialize the integer and float register pointers. */
3413 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3415 /* The struct_return pointer occupies the first parameter-passing reg. */
3419 fprintf_unfiltered (gdb_stdlog
,
3420 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3421 argreg
, paddr_nz (struct_addr
));
3422 write_register (argreg
++, struct_addr
);
3425 /* Now load as many as possible of the first arguments into
3426 registers, and push the rest onto the stack. Loop thru args
3427 from first to last. */
3428 for (argnum
= 0; argnum
< nargs
; argnum
++)
3431 struct value
*arg
= args
[argnum
];
3432 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3433 int len
= TYPE_LENGTH (arg_type
);
3434 enum type_code typecode
= TYPE_CODE (arg_type
);
3437 fprintf_unfiltered (gdb_stdlog
,
3438 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3439 argnum
+ 1, len
, (int) typecode
);
3441 val
= (char *) VALUE_CONTENTS (arg
);
3443 if (fp_register_arg_p (typecode
, arg_type
)
3444 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3446 /* This is a floating point value that fits entirely
3447 in a single register. */
3448 /* On 32 bit ABI's the float_argreg is further adjusted
3449 above to ensure that it is even register aligned. */
3450 LONGEST regval
= extract_unsigned_integer (val
, len
);
3452 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3453 float_argreg
, phex (regval
, len
));
3454 write_register (float_argreg
++, regval
);
3457 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3458 argreg
, phex (regval
, len
));
3459 write_register (argreg
, regval
);
3464 /* Copy the argument to general registers or the stack in
3465 register-sized pieces. Large arguments are split between
3466 registers and stack. */
3467 /* Note: structs whose size is not a multiple of
3468 mips_abi_regsize() are treated specially: Irix cc passes
3469 them in registers where gcc sometimes puts them on the
3470 stack. For maximum compatibility, we will put them in
3472 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3473 && (len
% mips_abi_regsize (gdbarch
) != 0));
3474 /* Note: Floating-point values that didn't fit into an FP
3475 register are only written to memory. */
3478 /* Rememer if the argument was written to the stack. */
3479 int stack_used_p
= 0;
3480 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3481 ? len
: mips_abi_regsize (gdbarch
));
3484 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3487 /* Write this portion of the argument to the stack. */
3488 if (argreg
> MIPS_LAST_ARG_REGNUM
3490 || fp_register_arg_p (typecode
, arg_type
))
3492 /* Should shorter than int integer values be
3493 promoted to int before being stored? */
3494 int longword_offset
= 0;
3497 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3499 if (mips_stack_argsize (gdbarch
) == 8
3500 && (typecode
== TYPE_CODE_INT
3501 || typecode
== TYPE_CODE_PTR
3502 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3503 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3508 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3509 paddr_nz (stack_offset
));
3510 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3511 paddr_nz (longword_offset
));
3514 addr
= sp
+ stack_offset
+ longword_offset
;
3519 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3521 for (i
= 0; i
< partial_len
; i
++)
3523 fprintf_unfiltered (gdb_stdlog
, "%02x",
3527 write_memory (addr
, val
, partial_len
);
3530 /* Note!!! This is NOT an else clause. Odd sized
3531 structs may go thru BOTH paths. Floating point
3532 arguments will not. */
3533 /* Write this portion of the argument to a general
3534 purpose register. */
3535 if (argreg
<= MIPS_LAST_ARG_REGNUM
3536 && !fp_register_arg_p (typecode
, arg_type
))
3539 extract_unsigned_integer (val
, partial_len
);
3541 /* A non-floating-point argument being passed in a
3542 general register. If a struct or union, and if
3543 the remaining length is smaller than the register
3544 size, we have to adjust the register value on
3547 It does not seem to be necessary to do the
3548 same for integral types.
3550 cagney/2001-07-23: gdb/179: Also, GCC, when
3551 outputting LE O32 with sizeof (struct) <
3552 mips_abi_regsize(), generates a left shift as
3553 part of storing the argument in a register a
3554 register (the left shift isn't generated when
3555 sizeof (struct) >= mips_abi_regsize()). Since
3556 it is quite possible that this is GCC
3557 contradicting the LE/O32 ABI, GDB has not been
3558 adjusted to accommodate this. Either someone
3559 needs to demonstrate that the LE/O32 ABI
3560 specifies such a left shift OR this new ABI gets
3561 identified as such and GDB gets tweaked
3564 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3565 && partial_len
< mips_abi_regsize (gdbarch
)
3566 && (typecode
== TYPE_CODE_STRUCT
||
3567 typecode
== TYPE_CODE_UNION
))
3568 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3572 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3575 mips_abi_regsize (gdbarch
)));
3576 write_register (argreg
, regval
);
3583 /* Compute the the offset into the stack at which we
3584 will copy the next parameter.
3586 In N32 (N64?), the stack_offset only needs to be
3587 adjusted when it has been used. */
3590 stack_offset
+= align_up (partial_len
,
3591 mips_stack_argsize (gdbarch
));
3595 fprintf_unfiltered (gdb_stdlog
, "\n");
3598 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3600 /* Return adjusted stack pointer. */
3604 static enum return_value_convention
3605 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3606 struct type
*type
, struct regcache
*regcache
,
3607 void *readbuf
, const void *writebuf
)
3609 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3610 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3611 || TYPE_CODE (type
) == TYPE_CODE_UNION
3612 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3613 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3614 return RETURN_VALUE_STRUCT_CONVENTION
;
3615 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3616 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3618 /* A floating-point value belongs in the least significant part
3621 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3622 mips_xfer_register (regcache
,
3623 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3625 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3626 return RETURN_VALUE_REGISTER_CONVENTION
;
3628 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3629 && TYPE_NFIELDS (type
) <= 2
3630 && TYPE_NFIELDS (type
) >= 1
3631 && ((TYPE_NFIELDS (type
) == 1
3632 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3634 || (TYPE_NFIELDS (type
) == 2
3635 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3637 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3639 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3641 /* A struct that contains one or two floats. Each value is part
3642 in the least significant part of their floating point
3646 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3647 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3649 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3652 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3654 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3655 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3656 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3658 return RETURN_VALUE_REGISTER_CONVENTION
;
3660 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3661 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3663 /* A structure or union. Extract the left justified value,
3664 regardless of the byte order. I.e. DO NOT USE
3668 for (offset
= 0, regnum
= V0_REGNUM
;
3669 offset
< TYPE_LENGTH (type
);
3670 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3672 int xfer
= register_size (current_gdbarch
, regnum
);
3673 if (offset
+ xfer
> TYPE_LENGTH (type
))
3674 xfer
= TYPE_LENGTH (type
) - offset
;
3676 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3677 offset
, xfer
, regnum
);
3678 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3679 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3681 return RETURN_VALUE_REGISTER_CONVENTION
;
3685 /* A scalar extract each part but least-significant-byte
3689 for (offset
= 0, regnum
= V0_REGNUM
;
3690 offset
< TYPE_LENGTH (type
);
3691 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3693 int xfer
= register_size (current_gdbarch
, regnum
);
3694 if (offset
+ xfer
> TYPE_LENGTH (type
))
3695 xfer
= TYPE_LENGTH (type
) - offset
;
3697 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3698 offset
, xfer
, regnum
);
3699 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3700 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3702 return RETURN_VALUE_REGISTER_CONVENTION
;
3706 /* O32 ABI stuff. */
3709 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3710 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3711 int nargs
, struct value
**args
, CORE_ADDR sp
,
3712 int struct_return
, CORE_ADDR struct_addr
)
3718 int stack_offset
= 0;
3719 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3720 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3722 /* For shared libraries, "t9" needs to point at the function
3724 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3726 /* Set the return address register to point to the entry point of
3727 the program, where a breakpoint lies in wait. */
3728 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3730 /* First ensure that the stack and structure return address (if any)
3731 are properly aligned. The stack has to be at least 64-bit
3732 aligned even on 32-bit machines, because doubles must be 64-bit
3733 aligned. For n32 and n64, stack frames need to be 128-bit
3734 aligned, so we round to this widest known alignment. */
3736 sp
= align_down (sp
, 16);
3737 struct_addr
= align_down (struct_addr
, 16);
3739 /* Now make space on the stack for the args. */
3740 for (argnum
= 0; argnum
< nargs
; argnum
++)
3741 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3742 mips_stack_argsize (gdbarch
));
3743 sp
-= align_up (len
, 16);
3746 fprintf_unfiltered (gdb_stdlog
,
3747 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3748 paddr_nz (sp
), (long) align_up (len
, 16));
3750 /* Initialize the integer and float register pointers. */
3752 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3754 /* The struct_return pointer occupies the first parameter-passing reg. */
3758 fprintf_unfiltered (gdb_stdlog
,
3759 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3760 argreg
, paddr_nz (struct_addr
));
3761 write_register (argreg
++, struct_addr
);
3762 stack_offset
+= mips_stack_argsize (gdbarch
);
3765 /* Now load as many as possible of the first arguments into
3766 registers, and push the rest onto the stack. Loop thru args
3767 from first to last. */
3768 for (argnum
= 0; argnum
< nargs
; argnum
++)
3771 struct value
*arg
= args
[argnum
];
3772 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3773 int len
= TYPE_LENGTH (arg_type
);
3774 enum type_code typecode
= TYPE_CODE (arg_type
);
3777 fprintf_unfiltered (gdb_stdlog
,
3778 "mips_o32_push_dummy_call: %d len=%d type=%d",
3779 argnum
+ 1, len
, (int) typecode
);
3781 val
= (char *) VALUE_CONTENTS (arg
);
3783 /* 32-bit ABIs always start floating point arguments in an
3784 even-numbered floating point register. Round the FP register
3785 up before the check to see if there are any FP registers
3786 left. O32/O64 targets also pass the FP in the integer
3787 registers so also round up normal registers. */
3788 if (mips_abi_regsize (gdbarch
) < 8
3789 && fp_register_arg_p (typecode
, arg_type
))
3791 if ((float_argreg
& 1))
3795 /* Floating point arguments passed in registers have to be
3796 treated specially. On 32-bit architectures, doubles
3797 are passed in register pairs; the even register gets
3798 the low word, and the odd register gets the high word.
3799 On O32/O64, the first two floating point arguments are
3800 also copied to general registers, because MIPS16 functions
3801 don't use float registers for arguments. This duplication of
3802 arguments in general registers can't hurt non-MIPS16 functions
3803 because those registers are normally skipped. */
3805 if (fp_register_arg_p (typecode
, arg_type
)
3806 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3808 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3810 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3811 unsigned long regval
;
3813 /* Write the low word of the double to the even register(s). */
3814 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3816 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3817 float_argreg
, phex (regval
, 4));
3818 write_register (float_argreg
++, regval
);
3820 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3821 argreg
, phex (regval
, 4));
3822 write_register (argreg
++, regval
);
3824 /* Write the high word of the double to the odd register(s). */
3825 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3827 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3828 float_argreg
, phex (regval
, 4));
3829 write_register (float_argreg
++, regval
);
3832 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3833 argreg
, phex (regval
, 4));
3834 write_register (argreg
++, regval
);
3838 /* This is a floating point value that fits entirely
3839 in a single register. */
3840 /* On 32 bit ABI's the float_argreg is further adjusted
3841 above to ensure that it is even register aligned. */
3842 LONGEST regval
= extract_unsigned_integer (val
, len
);
3844 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3845 float_argreg
, phex (regval
, len
));
3846 write_register (float_argreg
++, regval
);
3847 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3848 registers for each argument. The below is (my
3849 guess) to ensure that the corresponding integer
3850 register has reserved the same space. */
3852 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3853 argreg
, phex (regval
, len
));
3854 write_register (argreg
, regval
);
3855 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3857 /* Reserve space for the FP register. */
3858 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3862 /* Copy the argument to general registers or the stack in
3863 register-sized pieces. Large arguments are split between
3864 registers and stack. */
3865 /* Note: structs whose size is not a multiple of
3866 mips_abi_regsize() are treated specially: Irix cc passes
3867 them in registers where gcc sometimes puts them on the
3868 stack. For maximum compatibility, we will put them in
3870 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3871 && (len
% mips_abi_regsize (gdbarch
) != 0));
3872 /* Structures should be aligned to eight bytes (even arg registers)
3873 on MIPS_ABI_O32, if their first member has double precision. */
3874 if (mips_abi_regsize (gdbarch
) < 8
3875 && mips_type_needs_double_align (arg_type
))
3880 /* Note: Floating-point values that didn't fit into an FP
3881 register are only written to memory. */
3884 /* Remember if the argument was written to the stack. */
3885 int stack_used_p
= 0;
3886 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3887 ? len
: mips_abi_regsize (gdbarch
));
3890 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3893 /* Write this portion of the argument to the stack. */
3894 if (argreg
> MIPS_LAST_ARG_REGNUM
3896 || fp_register_arg_p (typecode
, arg_type
))
3898 /* Should shorter than int integer values be
3899 promoted to int before being stored? */
3900 int longword_offset
= 0;
3903 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3905 if (mips_stack_argsize (gdbarch
) == 8
3906 && (typecode
== TYPE_CODE_INT
3907 || typecode
== TYPE_CODE_PTR
3908 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3909 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3914 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3915 paddr_nz (stack_offset
));
3916 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3917 paddr_nz (longword_offset
));
3920 addr
= sp
+ stack_offset
+ longword_offset
;
3925 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3927 for (i
= 0; i
< partial_len
; i
++)
3929 fprintf_unfiltered (gdb_stdlog
, "%02x",
3933 write_memory (addr
, val
, partial_len
);
3936 /* Note!!! This is NOT an else clause. Odd sized
3937 structs may go thru BOTH paths. Floating point
3938 arguments will not. */
3939 /* Write this portion of the argument to a general
3940 purpose register. */
3941 if (argreg
<= MIPS_LAST_ARG_REGNUM
3942 && !fp_register_arg_p (typecode
, arg_type
))
3944 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3945 /* Value may need to be sign extended, because
3946 mips_isa_regsize() != mips_abi_regsize(). */
3948 /* A non-floating-point argument being passed in a
3949 general register. If a struct or union, and if
3950 the remaining length is smaller than the register
3951 size, we have to adjust the register value on
3954 It does not seem to be necessary to do the
3955 same for integral types.
3957 Also don't do this adjustment on O64 binaries.
3959 cagney/2001-07-23: gdb/179: Also, GCC, when
3960 outputting LE O32 with sizeof (struct) <
3961 mips_abi_regsize(), generates a left shift as
3962 part of storing the argument in a register a
3963 register (the left shift isn't generated when
3964 sizeof (struct) >= mips_abi_regsize()). Since
3965 it is quite possible that this is GCC
3966 contradicting the LE/O32 ABI, GDB has not been
3967 adjusted to accommodate this. Either someone
3968 needs to demonstrate that the LE/O32 ABI
3969 specifies such a left shift OR this new ABI gets
3970 identified as such and GDB gets tweaked
3973 if (mips_abi_regsize (gdbarch
) < 8
3974 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3975 && partial_len
< mips_abi_regsize (gdbarch
)
3976 && (typecode
== TYPE_CODE_STRUCT
||
3977 typecode
== TYPE_CODE_UNION
))
3978 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3982 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3985 mips_abi_regsize (gdbarch
)));
3986 write_register (argreg
, regval
);
3989 /* Prevent subsequent floating point arguments from
3990 being passed in floating point registers. */
3991 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3997 /* Compute the the offset into the stack at which we
3998 will copy the next parameter.
4000 In older ABIs, the caller reserved space for
4001 registers that contained arguments. This was loosely
4002 refered to as their "home". Consequently, space is
4003 always allocated. */
4005 stack_offset
+= align_up (partial_len
,
4006 mips_stack_argsize (gdbarch
));
4010 fprintf_unfiltered (gdb_stdlog
, "\n");
4013 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4015 /* Return adjusted stack pointer. */
4019 static enum return_value_convention
4020 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4021 struct regcache
*regcache
,
4022 void *readbuf
, const void *writebuf
)
4024 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4026 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4027 || TYPE_CODE (type
) == TYPE_CODE_UNION
4028 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4029 return RETURN_VALUE_STRUCT_CONVENTION
;
4030 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4031 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4033 /* A single-precision floating-point value. It fits in the
4034 least significant part of FP0. */
4036 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4037 mips_xfer_register (regcache
,
4038 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4040 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4041 return RETURN_VALUE_REGISTER_CONVENTION
;
4043 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4044 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4046 /* A double-precision floating-point value. The most
4047 significant part goes in FP1, and the least significant in
4050 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4051 switch (TARGET_BYTE_ORDER
)
4053 case BFD_ENDIAN_LITTLE
:
4054 mips_xfer_register (regcache
,
4055 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4056 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4057 mips_xfer_register (regcache
,
4058 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4059 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4061 case BFD_ENDIAN_BIG
:
4062 mips_xfer_register (regcache
,
4063 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4064 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4065 mips_xfer_register (regcache
,
4066 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4067 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4070 internal_error (__FILE__
, __LINE__
, "bad switch");
4072 return RETURN_VALUE_REGISTER_CONVENTION
;
4075 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4076 && TYPE_NFIELDS (type
) <= 2
4077 && TYPE_NFIELDS (type
) >= 1
4078 && ((TYPE_NFIELDS (type
) == 1
4079 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4081 || (TYPE_NFIELDS (type
) == 2
4082 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4084 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4086 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4088 /* A struct that contains one or two floats. Each value is part
4089 in the least significant part of their floating point
4091 bfd_byte reg
[MAX_REGISTER_SIZE
];
4094 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4095 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4097 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4100 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4102 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4103 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4104 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4106 return RETURN_VALUE_REGISTER_CONVENTION
;
4110 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4111 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4113 /* A structure or union. Extract the left justified value,
4114 regardless of the byte order. I.e. DO NOT USE
4118 for (offset
= 0, regnum
= V0_REGNUM
;
4119 offset
< TYPE_LENGTH (type
);
4120 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4122 int xfer
= register_size (current_gdbarch
, regnum
);
4123 if (offset
+ xfer
> TYPE_LENGTH (type
))
4124 xfer
= TYPE_LENGTH (type
) - offset
;
4126 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4127 offset
, xfer
, regnum
);
4128 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4129 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4131 return RETURN_VALUE_REGISTER_CONVENTION
;
4136 /* A scalar extract each part but least-significant-byte
4137 justified. o32 thinks registers are 4 byte, regardless of
4138 the ISA. mips_stack_argsize controls this. */
4141 for (offset
= 0, regnum
= V0_REGNUM
;
4142 offset
< TYPE_LENGTH (type
);
4143 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4145 int xfer
= mips_stack_argsize (gdbarch
);
4146 if (offset
+ xfer
> TYPE_LENGTH (type
))
4147 xfer
= TYPE_LENGTH (type
) - offset
;
4149 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4150 offset
, xfer
, regnum
);
4151 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4152 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4154 return RETURN_VALUE_REGISTER_CONVENTION
;
4158 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4162 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4163 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4165 struct value
**args
, CORE_ADDR sp
,
4166 int struct_return
, CORE_ADDR struct_addr
)
4172 int stack_offset
= 0;
4173 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4174 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4176 /* For shared libraries, "t9" needs to point at the function
4178 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4180 /* Set the return address register to point to the entry point of
4181 the program, where a breakpoint lies in wait. */
4182 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4184 /* First ensure that the stack and structure return address (if any)
4185 are properly aligned. The stack has to be at least 64-bit
4186 aligned even on 32-bit machines, because doubles must be 64-bit
4187 aligned. For n32 and n64, stack frames need to be 128-bit
4188 aligned, so we round to this widest known alignment. */
4190 sp
= align_down (sp
, 16);
4191 struct_addr
= align_down (struct_addr
, 16);
4193 /* Now make space on the stack for the args. */
4194 for (argnum
= 0; argnum
< nargs
; argnum
++)
4195 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4196 mips_stack_argsize (gdbarch
));
4197 sp
-= align_up (len
, 16);
4200 fprintf_unfiltered (gdb_stdlog
,
4201 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4202 paddr_nz (sp
), (long) align_up (len
, 16));
4204 /* Initialize the integer and float register pointers. */
4206 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4208 /* The struct_return pointer occupies the first parameter-passing reg. */
4212 fprintf_unfiltered (gdb_stdlog
,
4213 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4214 argreg
, paddr_nz (struct_addr
));
4215 write_register (argreg
++, struct_addr
);
4216 stack_offset
+= mips_stack_argsize (gdbarch
);
4219 /* Now load as many as possible of the first arguments into
4220 registers, and push the rest onto the stack. Loop thru args
4221 from first to last. */
4222 for (argnum
= 0; argnum
< nargs
; argnum
++)
4225 struct value
*arg
= args
[argnum
];
4226 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4227 int len
= TYPE_LENGTH (arg_type
);
4228 enum type_code typecode
= TYPE_CODE (arg_type
);
4231 fprintf_unfiltered (gdb_stdlog
,
4232 "mips_o64_push_dummy_call: %d len=%d type=%d",
4233 argnum
+ 1, len
, (int) typecode
);
4235 val
= (char *) VALUE_CONTENTS (arg
);
4237 /* 32-bit ABIs always start floating point arguments in an
4238 even-numbered floating point register. Round the FP register
4239 up before the check to see if there are any FP registers
4240 left. O32/O64 targets also pass the FP in the integer
4241 registers so also round up normal registers. */
4242 if (mips_abi_regsize (gdbarch
) < 8
4243 && fp_register_arg_p (typecode
, arg_type
))
4245 if ((float_argreg
& 1))
4249 /* Floating point arguments passed in registers have to be
4250 treated specially. On 32-bit architectures, doubles
4251 are passed in register pairs; the even register gets
4252 the low word, and the odd register gets the high word.
4253 On O32/O64, the first two floating point arguments are
4254 also copied to general registers, because MIPS16 functions
4255 don't use float registers for arguments. This duplication of
4256 arguments in general registers can't hurt non-MIPS16 functions
4257 because those registers are normally skipped. */
4259 if (fp_register_arg_p (typecode
, arg_type
)
4260 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4262 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4264 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4265 unsigned long regval
;
4267 /* Write the low word of the double to the even register(s). */
4268 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4270 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4271 float_argreg
, phex (regval
, 4));
4272 write_register (float_argreg
++, regval
);
4274 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4275 argreg
, phex (regval
, 4));
4276 write_register (argreg
++, regval
);
4278 /* Write the high word of the double to the odd register(s). */
4279 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4281 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4282 float_argreg
, phex (regval
, 4));
4283 write_register (float_argreg
++, regval
);
4286 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4287 argreg
, phex (regval
, 4));
4288 write_register (argreg
++, regval
);
4292 /* This is a floating point value that fits entirely
4293 in a single register. */
4294 /* On 32 bit ABI's the float_argreg is further adjusted
4295 above to ensure that it is even register aligned. */
4296 LONGEST regval
= extract_unsigned_integer (val
, len
);
4298 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4299 float_argreg
, phex (regval
, len
));
4300 write_register (float_argreg
++, regval
);
4301 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4302 registers for each argument. The below is (my
4303 guess) to ensure that the corresponding integer
4304 register has reserved the same space. */
4306 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4307 argreg
, phex (regval
, len
));
4308 write_register (argreg
, regval
);
4309 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4311 /* Reserve space for the FP register. */
4312 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4316 /* Copy the argument to general registers or the stack in
4317 register-sized pieces. Large arguments are split between
4318 registers and stack. */
4319 /* Note: structs whose size is not a multiple of
4320 mips_abi_regsize() are treated specially: Irix cc passes
4321 them in registers where gcc sometimes puts them on the
4322 stack. For maximum compatibility, we will put them in
4324 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4325 && (len
% mips_abi_regsize (gdbarch
) != 0));
4326 /* Structures should be aligned to eight bytes (even arg registers)
4327 on MIPS_ABI_O32, if their first member has double precision. */
4328 if (mips_abi_regsize (gdbarch
) < 8
4329 && mips_type_needs_double_align (arg_type
))
4334 /* Note: Floating-point values that didn't fit into an FP
4335 register are only written to memory. */
4338 /* Remember if the argument was written to the stack. */
4339 int stack_used_p
= 0;
4340 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4341 ? len
: mips_abi_regsize (gdbarch
));
4344 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4347 /* Write this portion of the argument to the stack. */
4348 if (argreg
> MIPS_LAST_ARG_REGNUM
4350 || fp_register_arg_p (typecode
, arg_type
))
4352 /* Should shorter than int integer values be
4353 promoted to int before being stored? */
4354 int longword_offset
= 0;
4357 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4359 if (mips_stack_argsize (gdbarch
) == 8
4360 && (typecode
== TYPE_CODE_INT
4361 || typecode
== TYPE_CODE_PTR
4362 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4363 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4368 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4369 paddr_nz (stack_offset
));
4370 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4371 paddr_nz (longword_offset
));
4374 addr
= sp
+ stack_offset
+ longword_offset
;
4379 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4381 for (i
= 0; i
< partial_len
; i
++)
4383 fprintf_unfiltered (gdb_stdlog
, "%02x",
4387 write_memory (addr
, val
, partial_len
);
4390 /* Note!!! This is NOT an else clause. Odd sized
4391 structs may go thru BOTH paths. Floating point
4392 arguments will not. */
4393 /* Write this portion of the argument to a general
4394 purpose register. */
4395 if (argreg
<= MIPS_LAST_ARG_REGNUM
4396 && !fp_register_arg_p (typecode
, arg_type
))
4398 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4399 /* Value may need to be sign extended, because
4400 mips_isa_regsize() != mips_abi_regsize(). */
4402 /* A non-floating-point argument being passed in a
4403 general register. If a struct or union, and if
4404 the remaining length is smaller than the register
4405 size, we have to adjust the register value on
4408 It does not seem to be necessary to do the
4409 same for integral types.
4411 Also don't do this adjustment on O64 binaries.
4413 cagney/2001-07-23: gdb/179: Also, GCC, when
4414 outputting LE O32 with sizeof (struct) <
4415 mips_abi_regsize(), generates a left shift as
4416 part of storing the argument in a register a
4417 register (the left shift isn't generated when
4418 sizeof (struct) >= mips_abi_regsize()). Since
4419 it is quite possible that this is GCC
4420 contradicting the LE/O32 ABI, GDB has not been
4421 adjusted to accommodate this. Either someone
4422 needs to demonstrate that the LE/O32 ABI
4423 specifies such a left shift OR this new ABI gets
4424 identified as such and GDB gets tweaked
4427 if (mips_abi_regsize (gdbarch
) < 8
4428 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4429 && partial_len
< mips_abi_regsize (gdbarch
)
4430 && (typecode
== TYPE_CODE_STRUCT
||
4431 typecode
== TYPE_CODE_UNION
))
4432 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4436 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4439 mips_abi_regsize (gdbarch
)));
4440 write_register (argreg
, regval
);
4443 /* Prevent subsequent floating point arguments from
4444 being passed in floating point registers. */
4445 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4451 /* Compute the the offset into the stack at which we
4452 will copy the next parameter.
4454 In older ABIs, the caller reserved space for
4455 registers that contained arguments. This was loosely
4456 refered to as their "home". Consequently, space is
4457 always allocated. */
4459 stack_offset
+= align_up (partial_len
,
4460 mips_stack_argsize (gdbarch
));
4464 fprintf_unfiltered (gdb_stdlog
, "\n");
4467 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4469 /* Return adjusted stack pointer. */
4474 mips_o64_extract_return_value (struct type
*valtype
,
4475 char regbuf
[], char *valbuf
)
4477 struct return_value_word lo
;
4478 struct return_value_word hi
;
4479 return_value_location (valtype
, &hi
, &lo
);
4481 memcpy (valbuf
+ lo
.buf_offset
,
4482 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4483 lo
.reg_offset
, lo
.len
);
4486 memcpy (valbuf
+ hi
.buf_offset
,
4487 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4488 hi
.reg_offset
, hi
.len
);
4492 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4494 char raw_buffer
[MAX_REGISTER_SIZE
];
4495 struct return_value_word lo
;
4496 struct return_value_word hi
;
4497 return_value_location (valtype
, &hi
, &lo
);
4499 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4500 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4501 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4502 raw_buffer
, register_size (current_gdbarch
,
4507 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4508 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4509 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4511 register_size (current_gdbarch
,
4516 /* Floating point register management.
4518 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4519 64bit operations, these early MIPS cpus treat fp register pairs
4520 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4521 registers and offer a compatibility mode that emulates the MIPS2 fp
4522 model. When operating in MIPS2 fp compat mode, later cpu's split
4523 double precision floats into two 32-bit chunks and store them in
4524 consecutive fp regs. To display 64-bit floats stored in this
4525 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4526 Throw in user-configurable endianness and you have a real mess.
4528 The way this works is:
4529 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4530 double-precision value will be split across two logical registers.
4531 The lower-numbered logical register will hold the low-order bits,
4532 regardless of the processor's endianness.
4533 - If we are on a 64-bit processor, and we are looking for a
4534 single-precision value, it will be in the low ordered bits
4535 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4536 save slot in memory.
4537 - If we are in 64-bit mode, everything is straightforward.
4539 Note that this code only deals with "live" registers at the top of the
4540 stack. We will attempt to deal with saved registers later, when
4541 the raw/cooked register interface is in place. (We need a general
4542 interface that can deal with dynamic saved register sizes -- fp
4543 regs could be 32 bits wide in one frame and 64 on the frame above
4546 static struct type
*
4547 mips_float_register_type (void)
4549 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4550 return builtin_type_ieee_single_big
;
4552 return builtin_type_ieee_single_little
;
4555 static struct type
*
4556 mips_double_register_type (void)
4558 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4559 return builtin_type_ieee_double_big
;
4561 return builtin_type_ieee_double_little
;
4564 /* Copy a 32-bit single-precision value from the current frame
4565 into rare_buffer. */
4568 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4571 int raw_size
= register_size (current_gdbarch
, regno
);
4572 char *raw_buffer
= alloca (raw_size
);
4574 if (!frame_register_read (frame
, regno
, raw_buffer
))
4575 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4578 /* We have a 64-bit value for this register. Find the low-order
4582 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4587 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4591 memcpy (rare_buffer
, raw_buffer
, 4);
4595 /* Copy a 64-bit double-precision value from the current frame into
4596 rare_buffer. This may include getting half of it from the next
4600 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4603 int raw_size
= register_size (current_gdbarch
, regno
);
4605 if (raw_size
== 8 && !mips2_fp_compat ())
4607 /* We have a 64-bit value for this register, and we should use
4609 if (!frame_register_read (frame
, regno
, rare_buffer
))
4610 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4614 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4615 internal_error (__FILE__
, __LINE__
,
4616 "mips_read_fp_register_double: bad access to "
4617 "odd-numbered FP register");
4619 /* mips_read_fp_register_single will find the correct 32 bits from
4621 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4623 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4624 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4628 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4629 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4635 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4637 { /* do values for FP (float) regs */
4639 double doub
, flt1
; /* doubles extracted from raw hex data */
4643 (char *) alloca (2 *
4644 register_size (current_gdbarch
,
4645 mips_regnum (current_gdbarch
)->fp0
));
4647 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4648 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4651 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4653 /* 4-byte registers: Print hex and floating. Also print even
4654 numbered registers as doubles. */
4655 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4656 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4658 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4661 fprintf_filtered (file
, " flt: ");
4663 fprintf_filtered (file
, " <invalid float> ");
4665 fprintf_filtered (file
, "%-17.9g", flt1
);
4667 if (regnum
% 2 == 0)
4669 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4670 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4673 fprintf_filtered (file
, " dbl: ");
4675 fprintf_filtered (file
, "<invalid double>");
4677 fprintf_filtered (file
, "%-24.17g", doub
);
4682 /* Eight byte registers: print each one as hex, float and double. */
4683 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4684 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4686 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4687 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4690 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4693 fprintf_filtered (file
, " flt: ");
4695 fprintf_filtered (file
, "<invalid float>");
4697 fprintf_filtered (file
, "%-17.9g", flt1
);
4699 fprintf_filtered (file
, " dbl: ");
4701 fprintf_filtered (file
, "<invalid double>");
4703 fprintf_filtered (file
, "%-24.17g", doub
);
4708 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4709 int regnum
, int all
)
4711 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4712 char raw_buffer
[MAX_REGISTER_SIZE
];
4715 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4717 mips_print_fp_register (file
, frame
, regnum
);
4721 /* Get the data in raw format. */
4722 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4724 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4728 fputs_filtered (REGISTER_NAME (regnum
), file
);
4730 /* The problem with printing numeric register names (r26, etc.) is that
4731 the user can't use them on input. Probably the best solution is to
4732 fix it so that either the numeric or the funky (a2, etc.) names
4733 are accepted on input. */
4734 if (regnum
< MIPS_NUMREGS
)
4735 fprintf_filtered (file
, "(r%d): ", regnum
);
4737 fprintf_filtered (file
, ": ");
4739 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4741 register_size (current_gdbarch
,
4742 regnum
) - register_size (current_gdbarch
, regnum
);
4746 print_scalar_formatted (raw_buffer
+ offset
,
4747 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4751 /* Replacement for generic do_registers_info.
4752 Print regs in pretty columns. */
4755 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4758 fprintf_filtered (file
, " ");
4759 mips_print_fp_register (file
, frame
, regnum
);
4760 fprintf_filtered (file
, "\n");
4765 /* Print a row's worth of GP (int) registers, with name labels above */
4768 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4771 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4772 /* do values for GP (int) regs */
4773 char raw_buffer
[MAX_REGISTER_SIZE
];
4774 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4778 /* For GP registers, we print a separate row of names above the vals */
4779 fprintf_filtered (file
, " ");
4780 for (col
= 0, regnum
= start_regnum
;
4781 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4783 if (*REGISTER_NAME (regnum
) == '\0')
4784 continue; /* unused register */
4785 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4787 break; /* end the row: reached FP register */
4788 fprintf_filtered (file
,
4789 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4790 REGISTER_NAME (regnum
));
4793 /* print the R0 to R31 names */
4794 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4795 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4797 fprintf_filtered (file
, "\n ");
4799 /* now print the values in hex, 4 or 8 to the row */
4800 for (col
= 0, regnum
= start_regnum
;
4801 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4803 if (*REGISTER_NAME (regnum
) == '\0')
4804 continue; /* unused register */
4805 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4807 break; /* end row: reached FP register */
4808 /* OK: get the data in raw format. */
4809 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4810 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4811 /* pad small registers */
4813 byte
< (mips_abi_regsize (current_gdbarch
)
4814 - register_size (current_gdbarch
, regnum
)); byte
++)
4815 printf_filtered (" ");
4816 /* Now print the register value in hex, endian order. */
4817 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4819 register_size (current_gdbarch
,
4820 regnum
) - register_size (current_gdbarch
, regnum
);
4821 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4822 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4824 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4826 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4827 fprintf_filtered (file
, " ");
4830 if (col
> 0) /* ie. if we actually printed anything... */
4831 fprintf_filtered (file
, "\n");
4836 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4839 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4840 struct frame_info
*frame
, int regnum
, int all
)
4842 if (regnum
!= -1) /* do one specified register */
4844 gdb_assert (regnum
>= NUM_REGS
);
4845 if (*(REGISTER_NAME (regnum
)) == '\0')
4846 error ("Not a valid register for the current processor type");
4848 mips_print_register (file
, frame
, regnum
, 0);
4849 fprintf_filtered (file
, "\n");
4852 /* do all (or most) registers */
4855 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4857 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4860 if (all
) /* true for "INFO ALL-REGISTERS" command */
4861 regnum
= print_fp_register_row (file
, frame
, regnum
);
4863 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4866 regnum
= print_gp_register_row (file
, frame
, regnum
);
4871 /* Is this a branch with a delay slot? */
4873 static int is_delayed (unsigned long);
4876 is_delayed (unsigned long insn
)
4879 for (i
= 0; i
< NUMOPCODES
; ++i
)
4880 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4881 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4883 return (i
< NUMOPCODES
4884 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4885 | INSN_COND_BRANCH_DELAY
4886 | INSN_COND_BRANCH_LIKELY
)));
4890 mips_step_skips_delay (CORE_ADDR pc
)
4892 char buf
[MIPS_INSTLEN
];
4894 /* There is no branch delay slot on MIPS16. */
4895 if (pc_is_mips16 (pc
))
4898 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4899 /* If error reading memory, guess that it is not a delayed branch. */
4901 return is_delayed ((unsigned long)
4902 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4905 /* Skip the PC past function prologue instructions (32-bit version).
4906 This is a helper function for mips_skip_prologue. */
4909 mips32_skip_prologue (CORE_ADDR pc
)
4913 int seen_sp_adjust
= 0;
4914 int load_immediate_bytes
= 0;
4916 /* Find an upper bound on the prologue. */
4917 end_pc
= skip_prologue_using_sal (pc
);
4919 end_pc
= pc
+ 100; /* Magic. */
4921 /* Skip the typical prologue instructions. These are the stack adjustment
4922 instruction and the instructions that save registers on the stack
4923 or in the gcc frame. */
4924 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4926 unsigned long high_word
;
4928 inst
= mips_fetch_instruction (pc
);
4929 high_word
= (inst
>> 16) & 0xffff;
4931 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4932 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4934 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4935 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4937 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4938 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4939 && (inst
& 0x001F0000)) /* reg != $zero */
4942 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4944 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4946 continue; /* reg != $zero */
4948 /* move $s8,$sp. With different versions of gas this will be either
4949 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4950 Accept any one of these. */
4951 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4954 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4956 else if (high_word
== 0x3c1c) /* lui $gp,n */
4958 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4960 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4961 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4963 /* The following instructions load $at or $t0 with an immediate
4964 value in preparation for a stack adjustment via
4965 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4966 a local variable, so we accept them only before a stack adjustment
4967 instruction was seen. */
4968 else if (!seen_sp_adjust
)
4970 if (high_word
== 0x3c01 || /* lui $at,n */
4971 high_word
== 0x3c08) /* lui $t0,n */
4973 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4976 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4977 high_word
== 0x3508 || /* ori $t0,$t0,n */
4978 high_word
== 0x3401 || /* ori $at,$zero,n */
4979 high_word
== 0x3408) /* ori $t0,$zero,n */
4981 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4991 /* In a frameless function, we might have incorrectly
4992 skipped some load immediate instructions. Undo the skipping
4993 if the load immediate was not followed by a stack adjustment. */
4994 if (load_immediate_bytes
&& !seen_sp_adjust
)
4995 pc
-= load_immediate_bytes
;
4999 /* Skip the PC past function prologue instructions (16-bit version).
5000 This is a helper function for mips_skip_prologue. */
5003 mips16_skip_prologue (CORE_ADDR pc
)
5006 int extend_bytes
= 0;
5007 int prev_extend_bytes
;
5009 /* Table of instructions likely to be found in a function prologue. */
5012 unsigned short inst
;
5013 unsigned short mask
;
5019 , /* addiu $sp,offset */
5022 , /* daddiu $sp,offset */
5025 , /* sw reg,n($sp) */
5028 , /* sd reg,n($sp) */
5031 , /* sw $ra,n($sp) */
5034 , /* sd $ra,n($sp) */
5040 , /* sw $a0-$a3,n($s1) */
5043 , /* move reg,$a0-$a3 */
5046 , /* entry pseudo-op */
5049 , /* addiu $s1,$sp,n */
5051 0, 0} /* end of table marker */
5054 /* Find an upper bound on the prologue. */
5055 end_pc
= skip_prologue_using_sal (pc
);
5057 end_pc
= pc
+ 100; /* Magic. */
5059 /* Skip the typical prologue instructions. These are the stack adjustment
5060 instruction and the instructions that save registers on the stack
5061 or in the gcc frame. */
5062 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5064 unsigned short inst
;
5067 inst
= mips_fetch_instruction (pc
);
5069 /* Normally we ignore an extend instruction. However, if it is
5070 not followed by a valid prologue instruction, we must adjust
5071 the pc back over the extend so that it won't be considered
5072 part of the prologue. */
5073 if ((inst
& 0xf800) == 0xf000) /* extend */
5075 extend_bytes
= MIPS16_INSTLEN
;
5078 prev_extend_bytes
= extend_bytes
;
5081 /* Check for other valid prologue instructions besides extend. */
5082 for (i
= 0; table
[i
].mask
!= 0; i
++)
5083 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5085 if (table
[i
].mask
!= 0) /* it was in table? */
5086 continue; /* ignore it */
5090 /* Return the current pc, adjusted backwards by 2 if
5091 the previous instruction was an extend. */
5092 return pc
- prev_extend_bytes
;
5098 /* To skip prologues, I use this predicate. Returns either PC itself
5099 if the code at PC does not look like a function prologue; otherwise
5100 returns an address that (if we're lucky) follows the prologue. If
5101 LENIENT, then we must skip everything which is involved in setting
5102 up the frame (it's OK to skip more, just so long as we don't skip
5103 anything which might clobber the registers which are being saved.
5104 We must skip more in the case where part of the prologue is in the
5105 delay slot of a non-prologue instruction). */
5108 mips_skip_prologue (CORE_ADDR pc
)
5110 /* See if we can determine the end of the prologue via the symbol table.
5111 If so, then return either PC, or the PC after the prologue, whichever
5114 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
5116 if (post_prologue_pc
!= 0)
5117 return max (pc
, post_prologue_pc
);
5119 /* Can't determine prologue from the symbol table, need to examine
5122 if (pc_is_mips16 (pc
))
5123 return mips16_skip_prologue (pc
);
5125 return mips32_skip_prologue (pc
);
5128 /* Root of all "set mips "/"show mips " commands. This will eventually be
5129 used for all MIPS-specific commands. */
5132 show_mips_command (char *args
, int from_tty
)
5134 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5138 set_mips_command (char *args
, int from_tty
)
5141 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5142 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5145 /* Commands to show/set the MIPS FPU type. */
5148 show_mipsfpu_command (char *args
, int from_tty
)
5151 switch (MIPS_FPU_TYPE
)
5153 case MIPS_FPU_SINGLE
:
5154 fpu
= "single-precision";
5156 case MIPS_FPU_DOUBLE
:
5157 fpu
= "double-precision";
5160 fpu
= "absent (none)";
5163 internal_error (__FILE__
, __LINE__
, "bad switch");
5165 if (mips_fpu_type_auto
)
5167 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5171 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5176 set_mipsfpu_command (char *args
, int from_tty
)
5179 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5180 show_mipsfpu_command (args
, from_tty
);
5184 set_mipsfpu_single_command (char *args
, int from_tty
)
5186 struct gdbarch_info info
;
5187 gdbarch_info_init (&info
);
5188 mips_fpu_type
= MIPS_FPU_SINGLE
;
5189 mips_fpu_type_auto
= 0;
5190 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5191 instead of relying on globals. Doing that would let generic code
5192 handle the search for this specific architecture. */
5193 if (!gdbarch_update_p (info
))
5194 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5198 set_mipsfpu_double_command (char *args
, int from_tty
)
5200 struct gdbarch_info info
;
5201 gdbarch_info_init (&info
);
5202 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5203 mips_fpu_type_auto
= 0;
5204 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5205 instead of relying on globals. Doing that would let generic code
5206 handle the search for this specific architecture. */
5207 if (!gdbarch_update_p (info
))
5208 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5212 set_mipsfpu_none_command (char *args
, int from_tty
)
5214 struct gdbarch_info info
;
5215 gdbarch_info_init (&info
);
5216 mips_fpu_type
= MIPS_FPU_NONE
;
5217 mips_fpu_type_auto
= 0;
5218 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5219 instead of relying on globals. Doing that would let generic code
5220 handle the search for this specific architecture. */
5221 if (!gdbarch_update_p (info
))
5222 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5226 set_mipsfpu_auto_command (char *args
, int from_tty
)
5228 mips_fpu_type_auto
= 1;
5231 /* Attempt to identify the particular processor model by reading the
5232 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5233 the relevant processor still exists (it dates back to '94) and
5234 secondly this is not the way to do this. The processor type should
5235 be set by forcing an architecture change. */
5238 deprecated_mips_set_processor_regs_hack (void)
5240 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5243 prid
= read_register (PRID_REGNUM
);
5245 if ((prid
& ~0xf) == 0x700)
5246 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5249 /* Just like reinit_frame_cache, but with the right arguments to be
5250 callable as an sfunc. */
5253 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5254 struct cmd_list_element
*c
)
5256 reinit_frame_cache ();
5260 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5262 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5263 mips_extra_func_info_t proc_desc
;
5265 /* Search for the function containing this address. Set the low bit
5266 of the address when searching, in case we were given an even address
5267 that is the start of a 16-bit function. If we didn't do this,
5268 the search would fail because the symbol table says the function
5269 starts at an odd address, i.e. 1 byte past the given address. */
5270 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5271 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5273 /* Make an attempt to determine if this is a 16-bit function. If
5274 the procedure descriptor exists and the address therein is odd,
5275 it's definitely a 16-bit function. Otherwise, we have to just
5276 guess that if the address passed in is odd, it's 16-bits. */
5277 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5278 disassembler needs to be able to locally determine the ISA, and
5279 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5283 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5284 info
->mach
= bfd_mach_mips16
;
5288 if (pc_is_mips16 (memaddr
))
5289 info
->mach
= bfd_mach_mips16
;
5292 /* Round down the instruction address to the appropriate boundary. */
5293 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5295 /* Set the disassembler options. */
5296 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5298 /* Set up the disassembler info, so that we get the right
5299 register names from libopcodes. */
5300 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5301 info
->disassembler_options
= "gpr-names=n32";
5303 info
->disassembler_options
= "gpr-names=64";
5304 info
->flavour
= bfd_target_elf_flavour
;
5307 /* This string is not recognized explicitly by the disassembler,
5308 but it tells the disassembler to not try to guess the ABI from
5309 the bfd elf headers, such that, if the user overrides the ABI
5310 of a program linked as NewABI, the disassembly will follow the
5311 register naming conventions specified by the user. */
5312 info
->disassembler_options
= "gpr-names=32";
5314 /* Call the appropriate disassembler based on the target endian-ness. */
5315 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5316 return print_insn_big_mips (memaddr
, info
);
5318 return print_insn_little_mips (memaddr
, info
);
5321 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5322 counter value to determine whether a 16- or 32-bit breakpoint should be
5323 used. It returns a pointer to a string of bytes that encode a breakpoint
5324 instruction, stores the length of the string to *lenptr, and adjusts pc
5325 (if necessary) to point to the actual memory location where the
5326 breakpoint should be inserted. */
5328 static const unsigned char *
5329 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5331 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5333 if (pc_is_mips16 (*pcptr
))
5335 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5336 *pcptr
= unmake_mips16_addr (*pcptr
);
5337 *lenptr
= sizeof (mips16_big_breakpoint
);
5338 return mips16_big_breakpoint
;
5342 /* The IDT board uses an unusual breakpoint value, and
5343 sometimes gets confused when it sees the usual MIPS
5344 breakpoint instruction. */
5345 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5346 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5347 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5349 *lenptr
= sizeof (big_breakpoint
);
5351 if (strcmp (target_shortname
, "mips") == 0)
5352 return idt_big_breakpoint
;
5353 else if (strcmp (target_shortname
, "ddb") == 0
5354 || strcmp (target_shortname
, "pmon") == 0
5355 || strcmp (target_shortname
, "lsi") == 0)
5356 return pmon_big_breakpoint
;
5358 return big_breakpoint
;
5363 if (pc_is_mips16 (*pcptr
))
5365 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5366 *pcptr
= unmake_mips16_addr (*pcptr
);
5367 *lenptr
= sizeof (mips16_little_breakpoint
);
5368 return mips16_little_breakpoint
;
5372 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5373 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5374 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5376 *lenptr
= sizeof (little_breakpoint
);
5378 if (strcmp (target_shortname
, "mips") == 0)
5379 return idt_little_breakpoint
;
5380 else if (strcmp (target_shortname
, "ddb") == 0
5381 || strcmp (target_shortname
, "pmon") == 0
5382 || strcmp (target_shortname
, "lsi") == 0)
5383 return pmon_little_breakpoint
;
5385 return little_breakpoint
;
5390 /* If PC is in a mips16 call or return stub, return the address of the target
5391 PC, which is either the callee or the caller. There are several
5392 cases which must be handled:
5394 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5395 target PC is in $31 ($ra).
5396 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5397 and the target PC is in $2.
5398 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5399 before the jal instruction, this is effectively a call stub
5400 and the the target PC is in $2. Otherwise this is effectively
5401 a return stub and the target PC is in $18.
5403 See the source code for the stubs in gcc/config/mips/mips16.S for
5406 This function implements the SKIP_TRAMPOLINE_CODE macro.
5410 mips_skip_stub (CORE_ADDR pc
)
5413 CORE_ADDR start_addr
;
5415 /* Find the starting address and name of the function containing the PC. */
5416 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5419 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5420 target PC is in $31 ($ra). */
5421 if (strcmp (name
, "__mips16_ret_sf") == 0
5422 || strcmp (name
, "__mips16_ret_df") == 0)
5423 return read_signed_register (RA_REGNUM
);
5425 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5427 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5428 and the target PC is in $2. */
5429 if (name
[19] >= '0' && name
[19] <= '9')
5430 return read_signed_register (2);
5432 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5433 before the jal instruction, this is effectively a call stub
5434 and the the target PC is in $2. Otherwise this is effectively
5435 a return stub and the target PC is in $18. */
5436 else if (name
[19] == 's' || name
[19] == 'd')
5438 if (pc
== start_addr
)
5440 /* Check if the target of the stub is a compiler-generated
5441 stub. Such a stub for a function bar might have a name
5442 like __fn_stub_bar, and might look like this:
5447 la $1,bar (becomes a lui/addiu pair)
5449 So scan down to the lui/addi and extract the target
5450 address from those two instructions. */
5452 CORE_ADDR target_pc
= read_signed_register (2);
5456 /* See if the name of the target function is __fn_stub_*. */
5457 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5460 if (strncmp (name
, "__fn_stub_", 10) != 0
5461 && strcmp (name
, "etext") != 0
5462 && strcmp (name
, "_etext") != 0)
5465 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5466 The limit on the search is arbitrarily set to 20
5467 instructions. FIXME. */
5468 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5470 inst
= mips_fetch_instruction (target_pc
);
5471 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5472 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5473 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5474 return pc
| (inst
& 0xffff); /* low word */
5477 /* Couldn't find the lui/addui pair, so return stub address. */
5481 /* This is the 'return' part of a call stub. The return
5482 address is in $r18. */
5483 return read_signed_register (18);
5486 return 0; /* not a stub */
5490 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5491 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5494 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5496 CORE_ADDR start_addr
;
5498 /* Find the starting address of the function containing the PC. If the
5499 caller didn't give us a name, look it up at the same time. */
5500 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5504 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5506 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5507 if (name
[19] >= '0' && name
[19] <= '9')
5509 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5510 before the jal instruction, this is effectively a call stub. */
5511 else if (name
[19] == 's' || name
[19] == 'd')
5512 return pc
== start_addr
;
5515 return 0; /* not a stub */
5519 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5520 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5523 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5525 CORE_ADDR start_addr
;
5527 /* Find the starting address of the function containing the PC. */
5528 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5531 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5532 if (strcmp (name
, "__mips16_ret_sf") == 0
5533 || strcmp (name
, "__mips16_ret_df") == 0)
5536 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5537 i.e. after the jal instruction, this is effectively a return stub. */
5538 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5539 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5542 return 0; /* not a stub */
5546 /* Return non-zero if the PC is in a library helper function that
5547 should be ignored. This implements the
5548 DEPRECATED_IGNORE_HELPER_CALL macro. */
5551 mips_ignore_helper (CORE_ADDR pc
)
5555 /* Find the starting address and name of the function containing the PC. */
5556 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5559 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5560 that we want to ignore. */
5561 return (strcmp (name
, "__mips16_ret_sf") == 0
5562 || strcmp (name
, "__mips16_ret_df") == 0);
5566 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5567 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5570 mips_stab_reg_to_regnum (int num
)
5573 if (num
>= 0 && num
< 32)
5575 else if (num
>= 38 && num
< 70)
5576 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5578 regnum
= mips_regnum (current_gdbarch
)->hi
;
5580 regnum
= mips_regnum (current_gdbarch
)->lo
;
5582 /* This will hopefully (eventually) provoke a warning. Should
5583 we be calling complaint() here? */
5584 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5585 return NUM_REGS
+ regnum
;
5589 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5590 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5593 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5596 if (num
>= 0 && num
< 32)
5598 else if (num
>= 32 && num
< 64)
5599 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5601 regnum
= mips_regnum (current_gdbarch
)->hi
;
5603 regnum
= mips_regnum (current_gdbarch
)->lo
;
5605 /* This will hopefully (eventually) provoke a warning. Should we
5606 be calling complaint() here? */
5607 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5608 return NUM_REGS
+ regnum
;
5612 mips_register_sim_regno (int regnum
)
5614 /* Only makes sense to supply raw registers. */
5615 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5616 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5617 decide if it is valid. Should instead define a standard sim/gdb
5618 register numbering scheme. */
5619 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5620 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5623 return LEGACY_SIM_REGNO_IGNORE
;
5627 /* Convert an integer into an address. By first converting the value
5628 into a pointer and then extracting it signed, the address is
5629 guarenteed to be correctly sign extended. */
5632 mips_integer_to_address (struct type
*type
, void *buf
)
5634 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5635 LONGEST val
= unpack_long (type
, buf
);
5636 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5637 return extract_signed_integer (tmp
,
5638 TYPE_LENGTH (builtin_type_void_data_ptr
));
5642 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5644 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5645 const char *name
= bfd_get_section_name (abfd
, sect
);
5647 if (*abip
!= MIPS_ABI_UNKNOWN
)
5650 if (strncmp (name
, ".mdebug.", 8) != 0)
5653 if (strcmp (name
, ".mdebug.abi32") == 0)
5654 *abip
= MIPS_ABI_O32
;
5655 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5656 *abip
= MIPS_ABI_N32
;
5657 else if (strcmp (name
, ".mdebug.abi64") == 0)
5658 *abip
= MIPS_ABI_N64
;
5659 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5660 *abip
= MIPS_ABI_O64
;
5661 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5662 *abip
= MIPS_ABI_EABI32
;
5663 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5664 *abip
= MIPS_ABI_EABI64
;
5666 warning ("unsupported ABI %s.", name
+ 8);
5669 static enum mips_abi
5670 global_mips_abi (void)
5674 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5675 if (mips_abi_strings
[i
] == mips_abi_string
)
5676 return (enum mips_abi
) i
;
5678 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5681 static struct gdbarch
*
5682 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5684 struct gdbarch
*gdbarch
;
5685 struct gdbarch_tdep
*tdep
;
5687 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5689 enum mips_fpu_type fpu_type
;
5691 /* First of all, extract the elf_flags, if available. */
5692 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5693 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5694 else if (arches
!= NULL
)
5695 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5699 fprintf_unfiltered (gdb_stdlog
,
5700 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5702 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5703 switch ((elf_flags
& EF_MIPS_ABI
))
5705 case E_MIPS_ABI_O32
:
5706 found_abi
= MIPS_ABI_O32
;
5708 case E_MIPS_ABI_O64
:
5709 found_abi
= MIPS_ABI_O64
;
5711 case E_MIPS_ABI_EABI32
:
5712 found_abi
= MIPS_ABI_EABI32
;
5714 case E_MIPS_ABI_EABI64
:
5715 found_abi
= MIPS_ABI_EABI64
;
5718 if ((elf_flags
& EF_MIPS_ABI2
))
5719 found_abi
= MIPS_ABI_N32
;
5721 found_abi
= MIPS_ABI_UNKNOWN
;
5725 /* GCC creates a pseudo-section whose name describes the ABI. */
5726 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5727 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5729 /* If we have no useful BFD information, use the ABI from the last
5730 MIPS architecture (if there is one). */
5731 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5732 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5734 /* Try the architecture for any hint of the correct ABI. */
5735 if (found_abi
== MIPS_ABI_UNKNOWN
5736 && info
.bfd_arch_info
!= NULL
5737 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5739 switch (info
.bfd_arch_info
->mach
)
5741 case bfd_mach_mips3900
:
5742 found_abi
= MIPS_ABI_EABI32
;
5744 case bfd_mach_mips4100
:
5745 case bfd_mach_mips5000
:
5746 found_abi
= MIPS_ABI_EABI64
;
5748 case bfd_mach_mips8000
:
5749 case bfd_mach_mips10000
:
5750 /* On Irix, ELF64 executables use the N64 ABI. The
5751 pseudo-sections which describe the ABI aren't present
5752 on IRIX. (Even for executables created by gcc.) */
5753 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5754 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5755 found_abi
= MIPS_ABI_N64
;
5757 found_abi
= MIPS_ABI_N32
;
5763 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5766 /* What has the user specified from the command line? */
5767 wanted_abi
= global_mips_abi ();
5769 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5772 /* Now that we have found what the ABI for this binary would be,
5773 check whether the user is overriding it. */
5774 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5775 mips_abi
= wanted_abi
;
5776 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5777 mips_abi
= found_abi
;
5779 mips_abi
= MIPS_ABI_O32
;
5781 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5784 /* Also used when doing an architecture lookup. */
5786 fprintf_unfiltered (gdb_stdlog
,
5787 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5788 mips64_transfers_32bit_regs_p
);
5790 /* Determine the MIPS FPU type. */
5791 if (!mips_fpu_type_auto
)
5792 fpu_type
= mips_fpu_type
;
5793 else if (info
.bfd_arch_info
!= NULL
5794 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5795 switch (info
.bfd_arch_info
->mach
)
5797 case bfd_mach_mips3900
:
5798 case bfd_mach_mips4100
:
5799 case bfd_mach_mips4111
:
5800 case bfd_mach_mips4120
:
5801 fpu_type
= MIPS_FPU_NONE
;
5803 case bfd_mach_mips4650
:
5804 fpu_type
= MIPS_FPU_SINGLE
;
5807 fpu_type
= MIPS_FPU_DOUBLE
;
5810 else if (arches
!= NULL
)
5811 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5813 fpu_type
= MIPS_FPU_DOUBLE
;
5815 fprintf_unfiltered (gdb_stdlog
,
5816 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5818 /* try to find a pre-existing architecture */
5819 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5821 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5823 /* MIPS needs to be pedantic about which ABI the object is
5825 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5827 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5829 /* Need to be pedantic about which register virtual size is
5831 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5832 != mips64_transfers_32bit_regs_p
)
5834 /* Be pedantic about which FPU is selected. */
5835 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5837 return arches
->gdbarch
;
5840 /* Need a new architecture. Fill in a target specific vector. */
5841 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5842 gdbarch
= gdbarch_alloc (&info
, tdep
);
5843 tdep
->elf_flags
= elf_flags
;
5844 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5845 tdep
->found_abi
= found_abi
;
5846 tdep
->mips_abi
= mips_abi
;
5847 tdep
->mips_fpu_type
= fpu_type
;
5849 /* Initially set everything according to the default ABI/ISA. */
5850 set_gdbarch_short_bit (gdbarch
, 16);
5851 set_gdbarch_int_bit (gdbarch
, 32);
5852 set_gdbarch_float_bit (gdbarch
, 32);
5853 set_gdbarch_double_bit (gdbarch
, 64);
5854 set_gdbarch_long_double_bit (gdbarch
, 64);
5855 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5856 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5857 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5859 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5860 mips_elf_make_msymbol_special
);
5862 /* Fill in the OS dependant register numbers and names. */
5864 const char **reg_names
;
5865 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5866 struct mips_regnum
);
5867 if (info
.osabi
== GDB_OSABI_IRIX
)
5872 regnum
->badvaddr
= 66;
5875 regnum
->fp_control_status
= 69;
5876 regnum
->fp_implementation_revision
= 70;
5878 reg_names
= mips_irix_reg_names
;
5882 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5883 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5884 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5885 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5886 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5887 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5888 regnum
->fp_control_status
= 70;
5889 regnum
->fp_implementation_revision
= 71;
5891 if (info
.bfd_arch_info
!= NULL
5892 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5893 reg_names
= mips_tx39_reg_names
;
5895 reg_names
= mips_generic_reg_names
;
5897 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5898 replaced by read_pc? */
5899 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5900 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5901 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5902 set_gdbarch_num_regs (gdbarch
, num_regs
);
5903 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5904 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5905 tdep
->mips_processor_reg_names
= reg_names
;
5906 tdep
->regnum
= regnum
;
5912 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5913 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5914 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5915 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5916 tdep
->default_mask_address_p
= 0;
5917 set_gdbarch_long_bit (gdbarch
, 32);
5918 set_gdbarch_ptr_bit (gdbarch
, 32);
5919 set_gdbarch_long_long_bit (gdbarch
, 64);
5922 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5923 set_gdbarch_deprecated_store_return_value (gdbarch
,
5924 mips_o64_store_return_value
);
5925 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5926 mips_o64_extract_return_value
);
5927 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5928 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5929 tdep
->default_mask_address_p
= 0;
5930 set_gdbarch_long_bit (gdbarch
, 32);
5931 set_gdbarch_ptr_bit (gdbarch
, 32);
5932 set_gdbarch_long_long_bit (gdbarch
, 64);
5933 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
5935 case MIPS_ABI_EABI32
:
5936 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5937 set_gdbarch_deprecated_store_return_value (gdbarch
,
5938 mips_eabi_store_return_value
);
5939 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5940 mips_eabi_extract_return_value
);
5941 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5942 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5943 tdep
->default_mask_address_p
= 0;
5944 set_gdbarch_long_bit (gdbarch
, 32);
5945 set_gdbarch_ptr_bit (gdbarch
, 32);
5946 set_gdbarch_long_long_bit (gdbarch
, 64);
5947 set_gdbarch_deprecated_reg_struct_has_addr
5948 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5949 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
5951 case MIPS_ABI_EABI64
:
5952 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5953 set_gdbarch_deprecated_store_return_value (gdbarch
,
5954 mips_eabi_store_return_value
);
5955 set_gdbarch_deprecated_extract_return_value (gdbarch
,
5956 mips_eabi_extract_return_value
);
5957 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5958 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5959 tdep
->default_mask_address_p
= 0;
5960 set_gdbarch_long_bit (gdbarch
, 64);
5961 set_gdbarch_ptr_bit (gdbarch
, 64);
5962 set_gdbarch_long_long_bit (gdbarch
, 64);
5963 set_gdbarch_deprecated_reg_struct_has_addr
5964 (gdbarch
, mips_eabi_reg_struct_has_addr
);
5965 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
5968 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5969 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5970 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5971 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5972 tdep
->default_mask_address_p
= 0;
5973 set_gdbarch_long_bit (gdbarch
, 32);
5974 set_gdbarch_ptr_bit (gdbarch
, 32);
5975 set_gdbarch_long_long_bit (gdbarch
, 64);
5976 set_gdbarch_long_double_bit (gdbarch
, 128);
5977 set_gdbarch_long_double_format (gdbarch
,
5978 &floatformat_n32n64_long_double_big
);
5981 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5982 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5983 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5984 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5985 tdep
->default_mask_address_p
= 0;
5986 set_gdbarch_long_bit (gdbarch
, 64);
5987 set_gdbarch_ptr_bit (gdbarch
, 64);
5988 set_gdbarch_long_long_bit (gdbarch
, 64);
5989 set_gdbarch_long_double_bit (gdbarch
, 128);
5990 set_gdbarch_long_double_format (gdbarch
,
5991 &floatformat_n32n64_long_double_big
);
5994 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5997 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5998 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6001 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6002 flag in object files because to do so would make it impossible to
6003 link with libraries compiled without "-gp32". This is
6004 unnecessarily restrictive.
6006 We could solve this problem by adding "-gp32" multilibs to gcc,
6007 but to set this flag before gcc is built with such multilibs will
6008 break too many systems.''
6010 But even more unhelpfully, the default linker output target for
6011 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6012 for 64-bit programs - you need to change the ABI to change this,
6013 and not all gcc targets support that currently. Therefore using
6014 this flag to detect 32-bit mode would do the wrong thing given
6015 the current gcc - it would make GDB treat these 64-bit programs
6016 as 32-bit programs by default. */
6018 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6019 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6020 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6022 /* Add/remove bits from an address. The MIPS needs be careful to
6023 ensure that all 32 bit addresses are sign extended to 64 bits. */
6024 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6026 /* Unwind the frame. */
6027 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6028 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6030 /* Map debug register numbers onto internal register numbers. */
6031 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6032 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6033 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6034 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6035 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6036 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6037 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6038 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6040 /* MIPS version of CALL_DUMMY */
6042 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6043 replaced by a command, and all targets will default to on stack
6044 (regardless of the stack's execute status). */
6045 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6046 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6048 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6049 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6050 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6052 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6053 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6055 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6057 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6058 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6059 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6061 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6063 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6065 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6067 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6068 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6069 need to all be folded into the target vector. Since they are
6070 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6071 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6073 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6075 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6077 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6078 to support MIPS16. This is a bad thing. Make sure not to do it
6079 if we have an OS ABI that actually supports shared libraries, since
6080 shared library support is more important. If we have an OS someday
6081 that supports both shared libraries and MIPS16, we'll have to find
6082 a better place for these. */
6083 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6085 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6086 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6089 /* Hook in OS ABI-specific overrides, if they have been registered. */
6090 gdbarch_init_osabi (info
, gdbarch
);
6092 /* Unwind the frame. */
6093 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6094 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6095 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
6096 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
6097 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6098 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6099 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6100 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6106 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6108 struct gdbarch_info info
;
6110 /* Force the architecture to update, and (if it's a MIPS architecture)
6111 mips_gdbarch_init will take care of the rest. */
6112 gdbarch_info_init (&info
);
6113 gdbarch_update_p (info
);
6116 /* Print out which MIPS ABI is in use. */
6119 show_mips_abi (char *ignore_args
, int from_tty
)
6121 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6123 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6126 enum mips_abi global_abi
= global_mips_abi ();
6127 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6128 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6130 if (global_abi
== MIPS_ABI_UNKNOWN
)
6132 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6134 else if (global_abi
== actual_abi
)
6136 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6140 /* Probably shouldn't happen... */
6142 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6143 actual_abi_str
, mips_abi_strings
[global_abi
]);
6149 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6151 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6155 int ef_mips_32bitmode
;
6156 /* determine the ISA */
6157 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6175 /* determine the size of a pointer */
6176 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6177 fprintf_unfiltered (file
,
6178 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6180 fprintf_unfiltered (file
,
6181 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6183 fprintf_unfiltered (file
,
6184 "mips_dump_tdep: ef_mips_arch = %d\n",
6186 fprintf_unfiltered (file
,
6187 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6188 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6189 fprintf_unfiltered (file
,
6190 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6191 mips_mask_address_p (tdep
),
6192 tdep
->default_mask_address_p
);
6194 fprintf_unfiltered (file
,
6195 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6196 MIPS_DEFAULT_FPU_TYPE
,
6197 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6198 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6199 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6201 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6202 fprintf_unfiltered (file
,
6203 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6205 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6206 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6207 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6209 fprintf_unfiltered (file
,
6210 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6211 mips_stack_argsize (current_gdbarch
));
6212 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6213 fprintf_unfiltered (file
,
6214 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6215 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6216 fprintf_unfiltered (file
,
6217 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6218 XSTRING (ATTACH_DETACH
));
6219 fprintf_unfiltered (file
,
6220 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6221 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6222 fprintf_unfiltered (file
,
6223 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6224 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6225 fprintf_unfiltered (file
,
6226 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6227 FIRST_EMBED_REGNUM
);
6228 fprintf_unfiltered (file
,
6229 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6230 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6231 fprintf_unfiltered (file
,
6232 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6233 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6234 fprintf_unfiltered (file
,
6235 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6236 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6237 fprintf_unfiltered (file
,
6238 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6240 #ifdef MACHINE_CPROC_FP_OFFSET
6241 fprintf_unfiltered (file
,
6242 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6243 MACHINE_CPROC_FP_OFFSET
);
6245 #ifdef MACHINE_CPROC_PC_OFFSET
6246 fprintf_unfiltered (file
,
6247 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6248 MACHINE_CPROC_PC_OFFSET
);
6250 #ifdef MACHINE_CPROC_SP_OFFSET
6251 fprintf_unfiltered (file
,
6252 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6253 MACHINE_CPROC_SP_OFFSET
);
6255 fprintf_unfiltered (file
,
6256 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6258 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6259 fprintf_unfiltered (file
,
6260 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6261 fprintf_unfiltered (file
,
6262 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6263 fprintf_unfiltered (file
,
6264 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6265 MIPS_LAST_ARG_REGNUM
,
6266 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6267 fprintf_unfiltered (file
,
6268 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6269 fprintf_unfiltered (file
,
6270 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6271 mips_abi_regsize (current_gdbarch
));
6272 fprintf_unfiltered (file
,
6273 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6274 fprintf_unfiltered (file
,
6275 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6276 fprintf_unfiltered (file
,
6277 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6278 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6279 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6280 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6281 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6282 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6283 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6284 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6285 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6286 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6287 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6288 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6290 fprintf_unfiltered (file
,
6291 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6294 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6297 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6299 fprintf_unfiltered (file
,
6300 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6301 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6302 fprintf_unfiltered (file
,
6303 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6304 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6305 fprintf_unfiltered (file
,
6306 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6307 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6308 fprintf_unfiltered (file
,
6309 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6310 SOFTWARE_SINGLE_STEP_P ());
6311 fprintf_unfiltered (file
,
6312 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6313 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6314 #ifdef STACK_END_ADDR
6315 fprintf_unfiltered (file
,
6316 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6319 fprintf_unfiltered (file
,
6320 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6321 XSTRING (STEP_SKIPS_DELAY (PC
)));
6322 fprintf_unfiltered (file
,
6323 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6324 STEP_SKIPS_DELAY_P
);
6325 fprintf_unfiltered (file
,
6326 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6327 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6328 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6329 fprintf_unfiltered (file
,
6330 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6331 fprintf_unfiltered (file
,
6332 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6333 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6334 (TYPE
, CNT
, OTHERTYPE
)));
6336 fprintf_unfiltered (file
,
6337 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6338 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6341 fprintf_unfiltered (file
,
6342 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6344 #ifdef TRACE_FLAVOR_SIZE
6345 fprintf_unfiltered (file
,
6346 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6350 fprintf_unfiltered (file
,
6351 "mips_dump_tdep: TRACE_SET # %s\n",
6352 XSTRING (TRACE_SET (X
, STATE
)));
6354 #ifdef UNUSED_REGNUM
6355 fprintf_unfiltered (file
,
6356 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6358 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6359 fprintf_unfiltered (file
,
6360 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6361 (long) VM_MIN_ADDRESS
);
6362 fprintf_unfiltered (file
,
6363 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6366 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6369 _initialize_mips_tdep (void)
6371 static struct cmd_list_element
*mipsfpulist
= NULL
;
6372 struct cmd_list_element
*c
;
6374 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6375 if (MIPS_ABI_LAST
+ 1
6376 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6377 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6379 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6381 mips_pdr_data
= register_objfile_data ();
6383 /* Add root prefix command for all "set mips"/"show mips" commands */
6384 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6385 "Various MIPS specific commands.",
6386 &setmipscmdlist
, "set mips ", 0, &setlist
);
6388 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6389 "Various MIPS specific commands.",
6390 &showmipscmdlist
, "show mips ", 0, &showlist
);
6392 /* Allow the user to override the saved register size. */
6393 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6396 &mips_abi_regsize_string
, "\
6397 Set size of general purpose registers saved on the stack.\n\
6398 This option can be set to one of:\n\
6399 32 - Force GDB to treat saved GP registers as 32-bit\n\
6400 64 - Force GDB to treat saved GP registers as 64-bit\n\
6401 auto - Allow GDB to use the target's default setting or autodetect the\n\
6402 saved GP register size from information contained in the executable.\n\
6403 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6405 /* Allow the user to override the argument stack size. */
6406 deprecated_add_show_from_set
6407 (add_set_enum_cmd ("stack-arg-size",
6410 &mips_stack_argsize_string
, "\
6411 Set the amount of stack space reserved for each argument.\n\
6412 This option can be set to one of:\n\
6413 32 - Force GDB to allocate 32-bit chunks per argument\n\
6414 64 - Force GDB to allocate 64-bit chunks per argument\n\
6415 auto - Allow GDB to determine the correct setting from the current\n\
6416 target and executable (default)", &setmipscmdlist
),
6419 /* Allow the user to override the ABI. */
6420 c
= add_set_enum_cmd
6421 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6422 "Set the ABI used by this program.\n"
6423 "This option can be set to one of:\n"
6424 " auto - the default ABI associated with the current binary\n"
6426 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6427 set_cmd_sfunc (c
, mips_abi_update
);
6428 add_cmd ("abi", class_obscure
, show_mips_abi
,
6429 "Show ABI in use by MIPS target", &showmipscmdlist
);
6431 /* Let the user turn off floating point and set the fence post for
6432 heuristic_proc_start. */
6434 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6435 "Set use of MIPS floating-point coprocessor.",
6436 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6437 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6438 "Select single-precision MIPS floating-point coprocessor.",
6440 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6441 "Select double-precision MIPS floating-point coprocessor.",
6443 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6444 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6445 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6446 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6447 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6448 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6449 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6450 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6451 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6452 "Select MIPS floating-point coprocessor automatically.",
6454 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6455 "Show current use of MIPS floating-point coprocessor target.",
6458 /* We really would like to have both "0" and "unlimited" work, but
6459 command.c doesn't deal with that. So make it a var_zinteger
6460 because the user can always use "999999" or some such for unlimited. */
6461 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6462 (char *) &heuristic_fence_post
, "\
6463 Set the distance searched for the start of a function.\n\
6464 If you are debugging a stripped executable, GDB needs to search through the\n\
6465 program for the start of a function. This command sets the distance of the\n\
6466 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6467 /* We need to throw away the frame cache when we set this, since it
6468 might change our ability to get backtraces. */
6469 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6470 deprecated_add_show_from_set (c
, &showlist
);
6472 /* Allow the user to control whether the upper bits of 64-bit
6473 addresses should be zeroed. */
6474 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6475 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6476 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6477 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6478 allow GDB to determine the correct value.\n", "\
6479 Zerroing of upper 32 bits of 64-bit address is %s.",
6480 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6482 /* Allow the user to control the size of 32 bit registers within the
6483 raw remote packet. */
6484 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6485 &mips64_transfers_32bit_regs_p
, "\
6486 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6487 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6488 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6489 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6490 64 bits for others. Use \"off\" to disable compatibility mode", "\
6491 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6492 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6494 /* Debug this files internals. */
6495 deprecated_add_show_from_set
6496 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6497 &mips_debug
, "Set mips debugging.\n\
6498 When non-zero, mips specific debugging is enabled.", &setdebuglist
),