1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *const mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 const struct register_alias mips_numeric_register_aliases
[] = {
146 #define R(n) { #n, n }
147 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
148 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
149 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
150 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
154 #ifndef MIPS_DEFAULT_FPU_TYPE
155 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
157 static int mips_fpu_type_auto
= 1;
158 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
160 static int mips_debug
= 0;
162 /* Properties (for struct target_desc) describing the g/G packet
164 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
165 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
167 struct target_desc
*mips_tdesc_gp32
;
168 struct target_desc
*mips_tdesc_gp64
;
170 const struct mips_regnum
*
171 mips_regnum (struct gdbarch
*gdbarch
)
173 return gdbarch_tdep (gdbarch
)->regnum
;
177 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
179 return mips_regnum (gdbarch
)->fp0
+ 12;
182 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
184 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
186 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
187 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
190 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
192 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
194 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
195 functions to test, set, or clear bit 0 of addresses. */
198 is_mips16_addr (CORE_ADDR addr
)
204 unmake_mips16_addr (CORE_ADDR addr
)
206 return ((addr
) & ~(CORE_ADDR
) 1);
210 make_mips16_addr (CORE_ADDR addr
)
212 return ((addr
) | (CORE_ADDR
) 1);
215 /* Return the MIPS ABI associated with GDBARCH. */
217 mips_abi (struct gdbarch
*gdbarch
)
219 return gdbarch_tdep (gdbarch
)->mips_abi
;
223 mips_isa_regsize (struct gdbarch
*gdbarch
)
225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 /* If we know how big the registers are, use that size. */
228 if (tdep
->register_size_valid_p
)
229 return tdep
->register_size
;
231 /* Fall back to the previous behavior. */
232 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
233 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
236 /* Return the currently configured (or set) saved register size. */
239 mips_abi_regsize (struct gdbarch
*gdbarch
)
241 switch (mips_abi (gdbarch
))
243 case MIPS_ABI_EABI32
:
249 case MIPS_ABI_EABI64
:
251 case MIPS_ABI_UNKNOWN
:
254 internal_error (__FILE__
, __LINE__
, _("bad switch"));
258 /* Functions for setting and testing a bit in a minimal symbol that
259 marks it as 16-bit function. The MSB of the minimal symbol's
260 "info" field is used for this purpose.
262 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
263 i.e. refers to a 16-bit function, and sets a "special" bit in a
264 minimal symbol to mark it as a 16-bit function
266 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
269 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
271 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
273 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
278 msymbol_is_special (struct minimal_symbol
*msym
)
280 return MSYMBOL_TARGET_FLAG_1 (msym
);
283 /* XFER a value from the big/little/left end of the register.
284 Depending on the size of the value it might occupy the entire
285 register or just part of it. Make an allowance for this, aligning
286 things accordingly. */
289 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
290 int reg_num
, int length
,
291 enum bfd_endian endian
, gdb_byte
*in
,
292 const gdb_byte
*out
, int buf_offset
)
296 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
297 /* Need to transfer the left or right part of the register, based on
298 the targets byte order. */
302 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
304 case BFD_ENDIAN_LITTLE
:
307 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
311 internal_error (__FILE__
, __LINE__
, _("bad switch"));
314 fprintf_unfiltered (gdb_stderr
,
315 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
316 reg_num
, reg_offset
, buf_offset
, length
);
317 if (mips_debug
&& out
!= NULL
)
320 fprintf_unfiltered (gdb_stdlog
, "out ");
321 for (i
= 0; i
< length
; i
++)
322 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
325 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
328 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
330 if (mips_debug
&& in
!= NULL
)
333 fprintf_unfiltered (gdb_stdlog
, "in ");
334 for (i
= 0; i
< length
; i
++)
335 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
338 fprintf_unfiltered (gdb_stdlog
, "\n");
341 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
342 compatiblity mode. A return value of 1 means that we have
343 physical 64-bit registers, but should treat them as 32-bit registers. */
346 mips2_fp_compat (struct frame_info
*frame
)
348 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
349 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
351 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
355 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
356 in all the places we deal with FP registers. PR gdb/413. */
357 /* Otherwise check the FR bit in the status register - it controls
358 the FP compatiblity mode. If it is clear we are in compatibility
360 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
367 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
369 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
371 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
373 /* The list of available "set mips " and "show mips " commands. */
375 static struct cmd_list_element
*setmipscmdlist
= NULL
;
376 static struct cmd_list_element
*showmipscmdlist
= NULL
;
378 /* Integer registers 0 thru 31 are handled explicitly by
379 mips_register_name(). Processor specific registers 32 and above
380 are listed in the following tables. */
383 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
387 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
388 "sr", "lo", "hi", "bad", "cause", "pc",
389 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
390 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
391 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
392 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
396 /* Names of IDT R3041 registers. */
398 static const char *mips_r3041_reg_names
[] = {
399 "sr", "lo", "hi", "bad", "cause", "pc",
400 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
401 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
402 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
403 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
404 "fsr", "fir", "", /*"fp" */ "",
405 "", "", "bus", "ccfg", "", "", "", "",
406 "", "", "port", "cmp", "", "", "epc", "prid",
409 /* Names of tx39 registers. */
411 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
412 "sr", "lo", "hi", "bad", "cause", "pc",
413 "", "", "", "", "", "", "", "",
414 "", "", "", "", "", "", "", "",
415 "", "", "", "", "", "", "", "",
416 "", "", "", "", "", "", "", "",
418 "", "", "", "", "", "", "", "",
419 "", "", "config", "cache", "debug", "depc", "epc",
422 /* Names of IRIX registers. */
423 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
424 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
425 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
426 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
427 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
428 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
431 /* Names of Linux registers. */
432 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
433 "sr", "lo", "hi", "bad", "cause", "pc",
434 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
435 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
436 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
437 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
442 /* Return the name of the register corresponding to REGNO. */
444 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
446 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
447 /* GPR names for all ABIs other than n32/n64. */
448 static char *mips_gpr_names
[] = {
449 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
450 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
451 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
452 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
455 /* GPR names for n32 and n64 ABIs. */
456 static char *mips_n32_n64_gpr_names
[] = {
457 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
458 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
459 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
460 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
463 enum mips_abi abi
= mips_abi (gdbarch
);
465 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
466 but then don't make the raw register names visible. This (upper)
467 range of user visible register numbers are the pseudo-registers.
469 This approach was adopted accommodate the following scenario:
470 It is possible to debug a 64-bit device using a 32-bit
471 programming model. In such instances, the raw registers are
472 configured to be 64-bits wide, while the pseudo registers are
473 configured to be 32-bits wide. The registers that the user
474 sees - the pseudo registers - match the users expectations
475 given the programming model being used. */
476 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
477 if (regno
< gdbarch_num_regs (gdbarch
))
480 /* The MIPS integer registers are always mapped from 0 to 31. The
481 names of the registers (which reflects the conventions regarding
482 register use) vary depending on the ABI. */
483 if (0 <= rawnum
&& rawnum
< 32)
485 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
486 return mips_n32_n64_gpr_names
[rawnum
];
488 return mips_gpr_names
[rawnum
];
490 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
491 return tdesc_register_name (gdbarch
, rawnum
);
492 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
494 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
495 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
496 return tdep
->mips_processor_reg_names
[rawnum
- 32];
500 internal_error (__FILE__
, __LINE__
,
501 _("mips_register_name: bad register number %d"), rawnum
);
504 /* Return the groups that a MIPS register can be categorised into. */
507 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
508 struct reggroup
*reggroup
)
513 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
514 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
515 if (reggroup
== all_reggroup
)
517 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
518 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
519 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
520 (gdbarch), as not all architectures are multi-arch. */
521 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
522 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
523 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
525 if (reggroup
== float_reggroup
)
526 return float_p
&& pseudo
;
527 if (reggroup
== vector_reggroup
)
528 return vector_p
&& pseudo
;
529 if (reggroup
== general_reggroup
)
530 return (!vector_p
&& !float_p
) && pseudo
;
531 /* Save the pseudo registers. Need to make certain that any code
532 extracting register values from a saved register cache also uses
534 if (reggroup
== save_reggroup
)
535 return raw_p
&& pseudo
;
536 /* Restore the same pseudo register. */
537 if (reggroup
== restore_reggroup
)
538 return raw_p
&& pseudo
;
542 /* Return the groups that a MIPS register can be categorised into.
543 This version is only used if we have a target description which
544 describes real registers (and their groups). */
547 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
548 struct reggroup
*reggroup
)
550 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
551 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
554 /* Only save, restore, and display the pseudo registers. Need to
555 make certain that any code extracting register values from a
556 saved register cache also uses pseudo registers.
558 Note: saving and restoring the pseudo registers is slightly
559 strange; if we have 64 bits, we should save and restore all
560 64 bits. But this is hard and has little benefit. */
564 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
568 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
571 /* Map the symbol table registers which live in the range [1 *
572 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
573 registers. Take care of alignment and size problems. */
575 static enum register_status
576 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
577 int cookednum
, gdb_byte
*buf
)
579 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
580 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
581 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
582 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
583 return regcache_raw_read (regcache
, rawnum
, buf
);
584 else if (register_size (gdbarch
, rawnum
) >
585 register_size (gdbarch
, cookednum
))
587 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
588 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
591 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
593 enum register_status status
;
595 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
596 if (status
== REG_VALID
)
597 store_signed_integer (buf
, 4, byte_order
, regval
);
602 internal_error (__FILE__
, __LINE__
, _("bad register size"));
606 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
607 struct regcache
*regcache
, int cookednum
,
610 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
611 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
612 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
613 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
614 regcache_raw_write (regcache
, rawnum
, buf
);
615 else if (register_size (gdbarch
, rawnum
) >
616 register_size (gdbarch
, cookednum
))
618 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
619 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
622 /* Sign extend the shortened version of the register prior
623 to placing it in the raw register. This is required for
624 some mips64 parts in order to avoid unpredictable behavior. */
625 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
626 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
627 regcache_raw_write_signed (regcache
, rawnum
, regval
);
631 internal_error (__FILE__
, __LINE__
, _("bad register size"));
635 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
636 struct agent_expr
*ax
, int reg
)
638 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
639 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
640 && reg
< 2 * gdbarch_num_regs (gdbarch
));
642 ax_reg_mask (ax
, rawnum
);
648 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
649 struct agent_expr
*ax
, int reg
)
651 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
652 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
653 && reg
< 2 * gdbarch_num_regs (gdbarch
));
654 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
658 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
660 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
661 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
664 ax_simple (ax
, aop_lsh
);
667 ax_simple (ax
, aop_rsh_signed
);
671 internal_error (__FILE__
, __LINE__
, _("bad register size"));
676 /* Table to translate MIPS16 register field to actual register number. */
677 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
679 /* Heuristic_proc_start may hunt through the text section for a long
680 time across a 2400 baud serial line. Allows the user to limit this
683 static unsigned int heuristic_fence_post
= 0;
685 /* Number of bytes of storage in the actual machine representation for
686 register N. NOTE: This defines the pseudo register type so need to
687 rebuild the architecture vector. */
689 static int mips64_transfers_32bit_regs_p
= 0;
692 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
693 struct cmd_list_element
*c
)
695 struct gdbarch_info info
;
696 gdbarch_info_init (&info
);
697 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
698 instead of relying on globals. Doing that would let generic code
699 handle the search for this specific architecture. */
700 if (!gdbarch_update_p (info
))
702 mips64_transfers_32bit_regs_p
= 0;
703 error (_("32-bit compatibility mode not supported"));
707 /* Convert to/from a register and the corresponding memory value. */
709 /* This predicate tests for the case of an 8 byte floating point
710 value that is being transferred to or from a pair of floating point
711 registers each of which are (or are considered to be) only 4 bytes
714 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
717 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
718 && register_size (gdbarch
, regnum
) == 4
719 && (regnum
% gdbarch_num_regs (gdbarch
))
720 >= mips_regnum (gdbarch
)->fp0
721 && (regnum
% gdbarch_num_regs (gdbarch
))
722 < mips_regnum (gdbarch
)->fp0
+ 32
723 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
726 /* This predicate tests for the case of a value of less than 8
727 bytes in width that is being transfered to or from an 8 byte
728 general purpose register. */
730 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
733 int num_regs
= gdbarch_num_regs (gdbarch
);
735 return (register_size (gdbarch
, regnum
) == 8
736 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
737 && TYPE_LENGTH (type
) < 8);
741 mips_convert_register_p (struct gdbarch
*gdbarch
,
742 int regnum
, struct type
*type
)
744 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
745 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
749 mips_register_to_value (struct frame_info
*frame
, int regnum
,
750 struct type
*type
, gdb_byte
*to
,
751 int *optimizedp
, int *unavailablep
)
753 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
755 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
757 get_frame_register (frame
, regnum
+ 0, to
+ 4);
758 get_frame_register (frame
, regnum
+ 1, to
+ 0);
760 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
761 optimizedp
, unavailablep
))
764 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
765 optimizedp
, unavailablep
))
767 *optimizedp
= *unavailablep
= 0;
770 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
772 int len
= TYPE_LENGTH (type
);
775 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
776 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
777 optimizedp
, unavailablep
))
780 *optimizedp
= *unavailablep
= 0;
785 internal_error (__FILE__
, __LINE__
,
786 _("mips_register_to_value: unrecognized case"));
791 mips_value_to_register (struct frame_info
*frame
, int regnum
,
792 struct type
*type
, const gdb_byte
*from
)
794 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
796 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
798 put_frame_register (frame
, regnum
+ 0, from
+ 4);
799 put_frame_register (frame
, regnum
+ 1, from
+ 0);
801 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
804 int len
= TYPE_LENGTH (type
);
806 /* Sign extend values, irrespective of type, that are stored to
807 a 64-bit general purpose register. (32-bit unsigned values
808 are stored as signed quantities within a 64-bit register.
809 When performing an operation, in compiled code, that combines
810 a 32-bit unsigned value with a signed 64-bit value, a type
811 conversion is first performed that zeroes out the high 32 bits.) */
812 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
815 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
817 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
818 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
819 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
823 if (from
[len
-1] & 0x80)
824 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
826 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
827 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
828 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
833 internal_error (__FILE__
, __LINE__
,
834 _("mips_value_to_register: unrecognized case"));
838 /* Return the GDB type object for the "standard" data type of data in
842 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
844 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
845 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
846 && (regnum
% gdbarch_num_regs (gdbarch
))
847 < mips_regnum (gdbarch
)->fp0
+ 32)
849 /* The floating-point registers raw, or cooked, always match
850 mips_isa_regsize(), and also map 1:1, byte for byte. */
851 if (mips_isa_regsize (gdbarch
) == 4)
852 return builtin_type (gdbarch
)->builtin_float
;
854 return builtin_type (gdbarch
)->builtin_double
;
856 else if (regnum
< gdbarch_num_regs (gdbarch
))
858 /* The raw or ISA registers. These are all sized according to
860 if (mips_isa_regsize (gdbarch
) == 4)
861 return builtin_type (gdbarch
)->builtin_int32
;
863 return builtin_type (gdbarch
)->builtin_int64
;
867 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
869 /* The cooked or ABI registers. These are sized according to
870 the ABI (with a few complications). */
871 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
872 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
873 return builtin_type (gdbarch
)->builtin_int32
;
874 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
875 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
876 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
877 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
878 /* The pseudo/cooked view of the embedded registers is always
879 32-bit. The raw view is handled below. */
880 return builtin_type (gdbarch
)->builtin_int32
;
881 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
882 /* The target, while possibly using a 64-bit register buffer,
883 is only transfering 32-bits of each integer register.
884 Reflect this in the cooked/pseudo (ABI) register value. */
885 return builtin_type (gdbarch
)->builtin_int32
;
886 else if (mips_abi_regsize (gdbarch
) == 4)
887 /* The ABI is restricted to 32-bit registers (the ISA could be
889 return builtin_type (gdbarch
)->builtin_int32
;
892 return builtin_type (gdbarch
)->builtin_int64
;
896 /* Return the GDB type for the pseudo register REGNUM, which is the
897 ABI-level view. This function is only called if there is a target
898 description which includes registers, so we know precisely the
899 types of hardware registers. */
902 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
904 const int num_regs
= gdbarch_num_regs (gdbarch
);
905 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
906 int rawnum
= regnum
% num_regs
;
907 struct type
*rawtype
;
909 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
911 /* Absent registers are still absent. */
912 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
913 if (TYPE_LENGTH (rawtype
) == 0)
916 if (rawnum
>= mips_regnum (gdbarch
)->fp0
917 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32)
918 /* Present the floating point registers however the hardware did;
919 do not try to convert between FPU layouts. */
922 /* Use pointer types for registers if we can. For n32 we can not,
923 since we do not have a 64-bit pointer type. */
924 if (mips_abi_regsize (gdbarch
)
925 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
927 if (rawnum
== MIPS_SP_REGNUM
928 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
929 return builtin_type (gdbarch
)->builtin_data_ptr
;
930 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
931 return builtin_type (gdbarch
)->builtin_func_ptr
;
934 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
935 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
936 || rawnum
== mips_regnum (gdbarch
)->lo
937 || rawnum
== mips_regnum (gdbarch
)->hi
938 || rawnum
== mips_regnum (gdbarch
)->badvaddr
939 || rawnum
== mips_regnum (gdbarch
)->cause
940 || rawnum
== mips_regnum (gdbarch
)->pc
941 || (mips_regnum (gdbarch
)->dspacc
!= -1
942 && rawnum
>= mips_regnum (gdbarch
)->dspacc
943 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
944 return builtin_type (gdbarch
)->builtin_int32
;
946 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
947 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
948 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
949 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
951 /* The pseudo/cooked view of embedded registers is always
952 32-bit, even if the target transfers 64-bit values for them.
953 New targets relying on XML descriptions should only transfer
954 the necessary 32 bits, but older versions of GDB expected 64,
955 so allow the target to provide 64 bits without interfering
956 with the displayed type. */
957 return builtin_type (gdbarch
)->builtin_int32
;
960 /* For all other registers, pass through the hardware type. */
964 /* Should the upper word of 64-bit addresses be zeroed? */
965 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
968 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
970 switch (mask_address_var
)
972 case AUTO_BOOLEAN_TRUE
:
974 case AUTO_BOOLEAN_FALSE
:
977 case AUTO_BOOLEAN_AUTO
:
978 return tdep
->default_mask_address_p
;
980 internal_error (__FILE__
, __LINE__
,
981 _("mips_mask_address_p: bad switch"));
987 show_mask_address (struct ui_file
*file
, int from_tty
,
988 struct cmd_list_element
*c
, const char *value
)
990 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
992 deprecated_show_value_hack (file
, from_tty
, c
, value
);
993 switch (mask_address_var
)
995 case AUTO_BOOLEAN_TRUE
:
996 printf_filtered ("The 32 bit mips address mask is enabled\n");
998 case AUTO_BOOLEAN_FALSE
:
999 printf_filtered ("The 32 bit mips address mask is disabled\n");
1001 case AUTO_BOOLEAN_AUTO
:
1003 ("The 32 bit address mask is set automatically. Currently %s\n",
1004 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1007 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1012 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1015 mips_pc_is_mips16 (CORE_ADDR memaddr
)
1017 struct minimal_symbol
*sym
;
1019 /* A flag indicating that this is a MIPS16 function is stored by
1020 elfread.c in the high bit of the info field. Use this to decide
1021 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of
1022 the address is set, assume this is a MIPS16 address. */
1023 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1025 return msymbol_is_special (sym
);
1027 return is_mips16_addr (memaddr
);
1030 /* MIPS believes that the PC has a sign extended value. Perhaps the
1031 all registers should be sign extended for simplicity? */
1034 mips_read_pc (struct regcache
*regcache
)
1037 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1038 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1039 if (is_mips16_addr (pc
))
1040 pc
= unmake_mips16_addr (pc
);
1045 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1049 pc
= frame_unwind_register_signed
1050 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
1051 if (is_mips16_addr (pc
))
1052 pc
= unmake_mips16_addr (pc
);
1057 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1059 return frame_unwind_register_signed
1060 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1063 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1064 dummy frame. The frame ID's base needs to match the TOS value
1065 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1068 static struct frame_id
1069 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1071 return frame_id_build
1072 (get_frame_register_signed (this_frame
,
1073 gdbarch_num_regs (gdbarch
)
1075 get_frame_pc (this_frame
));
1079 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1081 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
1082 if (mips_pc_is_mips16 (pc
))
1083 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1085 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1088 /* Fetch and return instruction from the specified location. If the PC
1089 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1092 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1094 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1095 gdb_byte buf
[MIPS_INSN32_SIZE
];
1099 if (mips_pc_is_mips16 (addr
))
1101 instlen
= MIPS_INSN16_SIZE
;
1102 addr
= unmake_mips16_addr (addr
);
1105 instlen
= MIPS_INSN32_SIZE
;
1106 status
= target_read_memory (addr
, buf
, instlen
);
1108 memory_error (status
, addr
);
1109 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1112 /* These are the fields of 32 bit mips instructions. */
1113 #define mips32_op(x) (x >> 26)
1114 #define itype_op(x) (x >> 26)
1115 #define itype_rs(x) ((x >> 21) & 0x1f)
1116 #define itype_rt(x) ((x >> 16) & 0x1f)
1117 #define itype_immediate(x) (x & 0xffff)
1119 #define jtype_op(x) (x >> 26)
1120 #define jtype_target(x) (x & 0x03ffffff)
1122 #define rtype_op(x) (x >> 26)
1123 #define rtype_rs(x) ((x >> 21) & 0x1f)
1124 #define rtype_rt(x) ((x >> 16) & 0x1f)
1125 #define rtype_rd(x) ((x >> 11) & 0x1f)
1126 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1127 #define rtype_funct(x) (x & 0x3f)
1130 mips32_relative_offset (ULONGEST inst
)
1132 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1135 /* Determine where to set a single step breakpoint while considering
1136 branch prediction. */
1138 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1140 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1143 inst
= mips_fetch_instruction (gdbarch
, pc
);
1144 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1147 if (itype_op (inst
) >> 2 == 5)
1148 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1150 op
= (itype_op (inst
) & 0x03);
1160 goto greater_branch
;
1165 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1166 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1168 int tf
= itype_rt (inst
) & 0x01;
1169 int cnum
= itype_rt (inst
) >> 2;
1171 get_frame_register_signed (frame
,
1172 mips_regnum (get_frame_arch (frame
))->
1174 int cond
= ((fcrcs
>> 24) & 0xfe) | ((fcrcs
>> 23) & 0x01);
1176 if (((cond
>> cnum
) & 0x01) == tf
)
1177 pc
+= mips32_relative_offset (inst
) + 4;
1182 pc
+= 4; /* Not a branch, next instruction is easy. */
1185 { /* This gets way messy. */
1187 /* Further subdivide into SPECIAL, REGIMM and other. */
1188 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1190 case 0: /* SPECIAL */
1191 op
= rtype_funct (inst
);
1196 /* Set PC to that address. */
1197 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1199 case 12: /* SYSCALL */
1201 struct gdbarch_tdep
*tdep
;
1203 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1204 if (tdep
->syscall_next_pc
!= NULL
)
1205 pc
= tdep
->syscall_next_pc (frame
);
1214 break; /* end SPECIAL */
1215 case 1: /* REGIMM */
1217 op
= itype_rt (inst
); /* branch condition */
1222 case 16: /* BLTZAL */
1223 case 18: /* BLTZALL */
1225 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1226 pc
+= mips32_relative_offset (inst
) + 4;
1228 pc
+= 8; /* after the delay slot */
1232 case 17: /* BGEZAL */
1233 case 19: /* BGEZALL */
1234 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1235 pc
+= mips32_relative_offset (inst
) + 4;
1237 pc
+= 8; /* after the delay slot */
1239 /* All of the other instructions in the REGIMM category */
1244 break; /* end REGIMM */
1249 reg
= jtype_target (inst
) << 2;
1250 /* Upper four bits get never changed... */
1251 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1254 /* FIXME case JALX : */
1257 reg
= jtype_target (inst
) << 2;
1258 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1259 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1261 break; /* The new PC will be alternate mode */
1262 case 4: /* BEQ, BEQL */
1264 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1265 get_frame_register_signed (frame
, itype_rt (inst
)))
1266 pc
+= mips32_relative_offset (inst
) + 4;
1270 case 5: /* BNE, BNEL */
1272 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1273 get_frame_register_signed (frame
, itype_rt (inst
)))
1274 pc
+= mips32_relative_offset (inst
) + 4;
1278 case 6: /* BLEZ, BLEZL */
1279 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1280 pc
+= mips32_relative_offset (inst
) + 4;
1286 greater_branch
: /* BGTZ, BGTZL */
1287 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1288 pc
+= mips32_relative_offset (inst
) + 4;
1295 } /* mips32_next_pc */
1297 /* Decoding the next place to set a breakpoint is irregular for the
1298 mips 16 variant, but fortunately, there fewer instructions. We have
1299 to cope ith extensions for 16 bit instructions and a pair of actual
1300 32 bit instructions. We dont want to set a single step instruction
1301 on the extend instruction either. */
1303 /* Lots of mips16 instruction formats */
1304 /* Predicting jumps requires itype,ritype,i8type
1305 and their extensions extItype,extritype,extI8type. */
1306 enum mips16_inst_fmts
1308 itype
, /* 0 immediate 5,10 */
1309 ritype
, /* 1 5,3,8 */
1310 rrtype
, /* 2 5,3,3,5 */
1311 rritype
, /* 3 5,3,3,5 */
1312 rrrtype
, /* 4 5,3,3,3,2 */
1313 rriatype
, /* 5 5,3,3,1,4 */
1314 shifttype
, /* 6 5,3,3,3,2 */
1315 i8type
, /* 7 5,3,8 */
1316 i8movtype
, /* 8 5,3,3,5 */
1317 i8mov32rtype
, /* 9 5,3,5,3 */
1318 i64type
, /* 10 5,3,8 */
1319 ri64type
, /* 11 5,3,3,5 */
1320 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1321 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1322 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1323 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1324 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1325 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1326 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1327 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1328 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1329 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1331 /* I am heaping all the fields of the formats into one structure and
1332 then, only the fields which are involved in instruction extension. */
1336 unsigned int regx
; /* Function in i8 type. */
1341 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1342 for the bits which make up the immediate extension. */
1345 extended_offset (unsigned int extension
)
1349 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1351 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1353 value
|= extension
& 0x1f; /* Extract 4:0. */
1358 /* Only call this function if you know that this is an extendable
1359 instruction. It won't malfunction, but why make excess remote memory
1360 references? If the immediate operands get sign extended or something,
1361 do it after the extension is performed. */
1362 /* FIXME: Every one of these cases needs to worry about sign extension
1363 when the offset is to be used in relative addressing. */
1366 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1368 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1370 pc
&= 0xfffffffe; /* Clear the low order bit. */
1371 target_read_memory (pc
, buf
, 2);
1372 return extract_unsigned_integer (buf
, 2, byte_order
);
1376 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1377 unsigned int extension
,
1379 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1384 switch (insn_format
)
1391 value
= extended_offset ((extension
<< 16) | inst
);
1392 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1396 value
= inst
& 0x7ff;
1397 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
1406 { /* A register identifier and an offset. */
1407 /* Most of the fields are the same as I type but the
1408 immediate value is of a different length. */
1412 value
= extended_offset ((extension
<< 16) | inst
);
1413 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1417 value
= inst
& 0xff; /* 8 bits */
1418 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
1421 regx
= (inst
>> 8) & 0x07; /* i8 funct */
1427 unsigned long value
;
1428 unsigned int nexthalf
;
1429 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1430 value
= value
<< 16;
1431 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1440 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1442 upk
->offset
= offset
;
1449 add_offset_16 (CORE_ADDR pc
, int offset
)
1451 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1455 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1456 unsigned int extension
, unsigned int insn
)
1458 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1459 int op
= (insn
>> 11);
1462 case 2: /* Branch */
1465 struct upk_mips16 upk
;
1466 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1467 pc
+= (upk
.offset
<< 1) + 2;
1470 case 3: /* JAL , JALX - Watch out, these are 32 bit
1473 struct upk_mips16 upk
;
1474 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1475 pc
= add_offset_16 (pc
, upk
.offset
);
1476 if ((insn
>> 10) & 0x01) /* Exchange mode */
1477 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1484 struct upk_mips16 upk
;
1486 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1487 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1489 pc
+= (upk
.offset
<< 1) + 2;
1496 struct upk_mips16 upk
;
1498 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1499 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1501 pc
+= (upk
.offset
<< 1) + 2;
1506 case 12: /* I8 Formats btez btnez */
1508 struct upk_mips16 upk
;
1510 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1511 /* upk.regx contains the opcode */
1512 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1513 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1514 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1515 /* pc = add_offset_16(pc,upk.offset) ; */
1516 pc
+= (upk
.offset
<< 1) + 2;
1521 case 29: /* RR Formats JR, JALR, JALR-RA */
1523 struct upk_mips16 upk
;
1524 /* upk.fmt = rrtype; */
1529 upk
.regx
= (insn
>> 8) & 0x07;
1530 upk
.regy
= (insn
>> 5) & 0x07;
1531 if ((upk
.regy
& 1) == 0)
1532 reg
= mips16_to_32_reg
[upk
.regx
];
1534 reg
= 31; /* Function return instruction. */
1535 pc
= get_frame_register_signed (frame
, reg
);
1542 /* This is an instruction extension. Fetch the real instruction
1543 (which follows the extension) and decode things based on
1547 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1548 fetch_mips_16 (gdbarch
, pc
));
1561 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1563 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1564 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1565 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1568 /* The mips_next_pc function supports single_step when the remote
1569 target monitor or stub is not developed enough to do a single_step.
1570 It works by decoding the current instruction and predicting where a
1571 branch will go. This isnt hard because all the data is available.
1572 The MIPS32 and MIPS16 variants are quite different. */
1574 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1576 if (mips_pc_is_mips16 (pc
))
1577 return mips16_next_pc (frame
, pc
);
1579 return mips32_next_pc (frame
, pc
);
1582 struct mips_frame_cache
1585 struct trad_frame_saved_reg
*saved_regs
;
1588 /* Set a register's saved stack address in temp_saved_regs. If an
1589 address has already been set for this register, do nothing; this
1590 way we will only recognize the first save of a given register in a
1593 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1594 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1595 Strictly speaking, only the second range is used as it is only second
1596 range (the ABI instead of ISA registers) that comes into play when finding
1597 saved registers in a frame. */
1600 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1601 int regnum
, CORE_ADDR offset
)
1603 if (this_cache
!= NULL
1604 && this_cache
->saved_regs
[regnum
].addr
== -1)
1606 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1608 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1614 /* Fetch the immediate value from a MIPS16 instruction.
1615 If the previous instruction was an EXTEND, use it to extend
1616 the upper bits of the immediate value. This is a helper function
1617 for mips16_scan_prologue. */
1620 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1621 unsigned short inst
, /* current instruction */
1622 int nbits
, /* number of bits in imm field */
1623 int scale
, /* scale factor to be applied to imm */
1624 int is_signed
) /* is the imm field signed? */
1628 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1630 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1631 if (offset
& 0x8000) /* check for negative extend */
1632 offset
= 0 - (0x10000 - (offset
& 0xffff));
1633 return offset
| (inst
& 0x1f);
1637 int max_imm
= 1 << nbits
;
1638 int mask
= max_imm
- 1;
1639 int sign_bit
= max_imm
>> 1;
1641 offset
= inst
& mask
;
1642 if (is_signed
&& (offset
& sign_bit
))
1643 offset
= 0 - (max_imm
- offset
);
1644 return offset
* scale
;
1649 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1650 the associated FRAME_CACHE if not null.
1651 Return the address of the first instruction past the prologue. */
1654 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1655 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1656 struct frame_info
*this_frame
,
1657 struct mips_frame_cache
*this_cache
)
1660 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1662 long frame_offset
= 0; /* Size of stack frame. */
1663 long frame_adjust
= 0; /* Offset of FP from SP. */
1664 int frame_reg
= MIPS_SP_REGNUM
;
1665 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1666 unsigned inst
= 0; /* current instruction */
1667 unsigned entry_inst
= 0; /* the entry instruction */
1668 unsigned save_inst
= 0; /* the save instruction */
1671 int extend_bytes
= 0;
1672 int prev_extend_bytes
;
1673 CORE_ADDR end_prologue_addr
= 0;
1675 /* Can be called when there's no process, and hence when there's no
1677 if (this_frame
!= NULL
)
1678 sp
= get_frame_register_signed (this_frame
,
1679 gdbarch_num_regs (gdbarch
)
1684 if (limit_pc
> start_pc
+ 200)
1685 limit_pc
= start_pc
+ 200;
1687 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1689 /* Save the previous instruction. If it's an EXTEND, we'll extract
1690 the immediate offset extension from it in mips16_get_imm. */
1693 /* Fetch and decode the instruction. */
1694 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1696 /* Normally we ignore extend instructions. However, if it is
1697 not followed by a valid prologue instruction, then this
1698 instruction is not part of the prologue either. We must
1699 remember in this case to adjust the end_prologue_addr back
1701 if ((inst
& 0xf800) == 0xf000) /* extend */
1703 extend_bytes
= MIPS_INSN16_SIZE
;
1707 prev_extend_bytes
= extend_bytes
;
1710 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1711 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1713 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1714 if (offset
< 0) /* Negative stack adjustment? */
1715 frame_offset
-= offset
;
1717 /* Exit loop if a positive stack adjustment is found, which
1718 usually means that the stack cleanup code in the function
1719 epilogue is reached. */
1722 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1724 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1725 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1726 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1728 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1730 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1731 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1732 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1734 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1736 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1737 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1739 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1741 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1742 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1744 else if (inst
== 0x673d) /* move $s1, $sp */
1749 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1751 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1752 frame_addr
= sp
+ offset
;
1754 frame_adjust
= offset
;
1756 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1758 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1759 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1760 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1762 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1764 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1765 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1766 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1768 else if ((inst
& 0xf81f) == 0xe809
1769 && (inst
& 0x700) != 0x700) /* entry */
1770 entry_inst
= inst
; /* Save for later processing. */
1771 else if ((inst
& 0xff80) == 0x6480) /* save */
1773 save_inst
= inst
; /* Save for later processing. */
1774 if (prev_extend_bytes
) /* extend */
1775 save_inst
|= prev_inst
<< 16;
1777 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1778 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1779 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1781 /* This instruction is part of the prologue, but we don't
1782 need to do anything special to handle it. */
1786 /* This instruction is not an instruction typically found
1787 in a prologue, so we must have reached the end of the
1789 if (end_prologue_addr
== 0)
1790 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1794 /* The entry instruction is typically the first instruction in a function,
1795 and it stores registers at offsets relative to the value of the old SP
1796 (before the prologue). But the value of the sp parameter to this
1797 function is the new SP (after the prologue has been executed). So we
1798 can't calculate those offsets until we've seen the entire prologue,
1799 and can calculate what the old SP must have been. */
1800 if (entry_inst
!= 0)
1802 int areg_count
= (entry_inst
>> 8) & 7;
1803 int sreg_count
= (entry_inst
>> 6) & 3;
1805 /* The entry instruction always subtracts 32 from the SP. */
1808 /* Now we can calculate what the SP must have been at the
1809 start of the function prologue. */
1812 /* Check if a0-a3 were saved in the caller's argument save area. */
1813 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1815 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1816 offset
+= mips_abi_regsize (gdbarch
);
1819 /* Check if the ra register was pushed on the stack. */
1821 if (entry_inst
& 0x20)
1823 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1824 offset
-= mips_abi_regsize (gdbarch
);
1827 /* Check if the s0 and s1 registers were pushed on the stack. */
1828 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1830 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1831 offset
-= mips_abi_regsize (gdbarch
);
1835 /* The SAVE instruction is similar to ENTRY, except that defined by the
1836 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1837 size of the frame is specified as an immediate field of instruction
1838 and an extended variation exists which lets additional registers and
1839 frame space to be specified. The instruction always treats registers
1840 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1841 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1843 static int args_table
[16] = {
1844 0, 0, 0, 0, 1, 1, 1, 1,
1845 2, 2, 2, 0, 3, 3, 4, -1,
1847 static int astatic_table
[16] = {
1848 0, 1, 2, 3, 0, 1, 2, 3,
1849 0, 1, 2, 4, 0, 1, 0, -1,
1851 int aregs
= (save_inst
>> 16) & 0xf;
1852 int xsregs
= (save_inst
>> 24) & 0x7;
1853 int args
= args_table
[aregs
];
1854 int astatic
= astatic_table
[aregs
];
1859 warning (_("Invalid number of argument registers encoded in SAVE."));
1864 warning (_("Invalid number of static registers encoded in SAVE."));
1868 /* For standard SAVE the frame size of 0 means 128. */
1869 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1870 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1873 frame_offset
+= frame_size
;
1875 /* Now we can calculate what the SP must have been at the
1876 start of the function prologue. */
1879 /* Check if A0-A3 were saved in the caller's argument save area. */
1880 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1882 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1883 offset
+= mips_abi_regsize (gdbarch
);
1888 /* Check if the RA register was pushed on the stack. */
1889 if (save_inst
& 0x40)
1891 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1892 offset
-= mips_abi_regsize (gdbarch
);
1895 /* Check if the S8 register was pushed on the stack. */
1898 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1899 offset
-= mips_abi_regsize (gdbarch
);
1902 /* Check if S2-S7 were pushed on the stack. */
1903 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1905 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1906 offset
-= mips_abi_regsize (gdbarch
);
1909 /* Check if the S1 register was pushed on the stack. */
1910 if (save_inst
& 0x10)
1912 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1913 offset
-= mips_abi_regsize (gdbarch
);
1915 /* Check if the S0 register was pushed on the stack. */
1916 if (save_inst
& 0x20)
1918 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1919 offset
-= mips_abi_regsize (gdbarch
);
1922 /* Check if A0-A3 were pushed on the stack. */
1923 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1925 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1926 offset
-= mips_abi_regsize (gdbarch
);
1930 if (this_cache
!= NULL
)
1933 (get_frame_register_signed (this_frame
,
1934 gdbarch_num_regs (gdbarch
) + frame_reg
)
1935 + frame_offset
- frame_adjust
);
1936 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1937 be able to get rid of the assignment below, evetually. But it's
1938 still needed for now. */
1939 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1940 + mips_regnum (gdbarch
)->pc
]
1941 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1944 /* If we didn't reach the end of the prologue when scanning the function
1945 instructions, then set end_prologue_addr to the address of the
1946 instruction immediately after the last one we scanned. */
1947 if (end_prologue_addr
== 0)
1948 end_prologue_addr
= cur_pc
;
1950 return end_prologue_addr
;
1953 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1954 Procedures that use the 32-bit instruction set are handled by the
1955 mips_insn32 unwinder. */
1957 static struct mips_frame_cache
*
1958 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1960 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1961 struct mips_frame_cache
*cache
;
1963 if ((*this_cache
) != NULL
)
1964 return (*this_cache
);
1965 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1966 (*this_cache
) = cache
;
1967 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1969 /* Analyze the function prologue. */
1971 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1972 CORE_ADDR start_addr
;
1974 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1975 if (start_addr
== 0)
1976 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1977 /* We can't analyze the prologue if we couldn't find the begining
1979 if (start_addr
== 0)
1982 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1985 /* gdbarch_sp_regnum contains the value and not the address. */
1986 trad_frame_set_value (cache
->saved_regs
,
1987 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1990 return (*this_cache
);
1994 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1995 struct frame_id
*this_id
)
1997 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1999 /* This marks the outermost frame. */
2000 if (info
->base
== 0)
2002 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2005 static struct value
*
2006 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2007 void **this_cache
, int regnum
)
2009 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2011 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2015 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2016 struct frame_info
*this_frame
, void **this_cache
)
2018 CORE_ADDR pc
= get_frame_pc (this_frame
);
2019 if (mips_pc_is_mips16 (pc
))
2024 static const struct frame_unwind mips_insn16_frame_unwind
=
2027 default_frame_unwind_stop_reason
,
2028 mips_insn16_frame_this_id
,
2029 mips_insn16_frame_prev_register
,
2031 mips_insn16_frame_sniffer
2035 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2038 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2043 static const struct frame_base mips_insn16_frame_base
=
2045 &mips_insn16_frame_unwind
,
2046 mips_insn16_frame_base_address
,
2047 mips_insn16_frame_base_address
,
2048 mips_insn16_frame_base_address
2051 static const struct frame_base
*
2052 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2054 CORE_ADDR pc
= get_frame_pc (this_frame
);
2055 if (mips_pc_is_mips16 (pc
))
2056 return &mips_insn16_frame_base
;
2061 /* Mark all the registers as unset in the saved_regs array
2062 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2065 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2067 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2071 const int num_regs
= gdbarch_num_regs (gdbarch
);
2074 for (i
= 0; i
< num_regs
; i
++)
2076 this_cache
->saved_regs
[i
].addr
= -1;
2081 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2082 the associated FRAME_CACHE if not null.
2083 Return the address of the first instruction past the prologue. */
2086 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2087 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2088 struct frame_info
*this_frame
,
2089 struct mips_frame_cache
*this_cache
)
2092 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2096 int frame_reg
= MIPS_SP_REGNUM
;
2098 CORE_ADDR end_prologue_addr
= 0;
2099 int seen_sp_adjust
= 0;
2100 int load_immediate_bytes
= 0;
2101 int in_delay_slot
= 0;
2102 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2104 /* Can be called when there's no process, and hence when there's no
2106 if (this_frame
!= NULL
)
2107 sp
= get_frame_register_signed (this_frame
,
2108 gdbarch_num_regs (gdbarch
)
2113 if (limit_pc
> start_pc
+ 200)
2114 limit_pc
= start_pc
+ 200;
2119 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2121 unsigned long inst
, high_word
, low_word
;
2124 /* Fetch the instruction. */
2125 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2127 /* Save some code by pre-extracting some useful fields. */
2128 high_word
= (inst
>> 16) & 0xffff;
2129 low_word
= inst
& 0xffff;
2130 reg
= high_word
& 0x1f;
2132 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2133 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2134 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2136 if (low_word
& 0x8000) /* Negative stack adjustment? */
2137 frame_offset
+= 0x10000 - low_word
;
2139 /* Exit loop if a positive stack adjustment is found, which
2140 usually means that the stack cleanup code in the function
2141 epilogue is reached. */
2145 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2146 && !regsize_is_64_bits
)
2148 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2150 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2151 && regsize_is_64_bits
)
2153 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2154 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2156 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2158 /* Old gcc frame, r30 is virtual frame pointer. */
2159 if ((long) low_word
!= frame_offset
)
2160 frame_addr
= sp
+ low_word
;
2161 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2163 unsigned alloca_adjust
;
2166 frame_addr
= get_frame_register_signed
2167 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2169 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2170 if (alloca_adjust
> 0)
2172 /* FP > SP + frame_size. This may be because of
2173 an alloca or somethings similar. Fix sp to
2174 "pre-alloca" value, and try again. */
2175 sp
+= alloca_adjust
;
2176 /* Need to reset the status of all registers. Otherwise,
2177 we will hit a guard that prevents the new address
2178 for each register to be recomputed during the second
2180 reset_saved_regs (gdbarch
, this_cache
);
2185 /* move $30,$sp. With different versions of gas this will be either
2186 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2187 Accept any one of these. */
2188 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2190 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2191 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2193 unsigned alloca_adjust
;
2196 frame_addr
= get_frame_register_signed
2197 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2199 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2200 if (alloca_adjust
> 0)
2202 /* FP > SP + frame_size. This may be because of
2203 an alloca or somethings similar. Fix sp to
2204 "pre-alloca" value, and try again. */
2206 /* Need to reset the status of all registers. Otherwise,
2207 we will hit a guard that prevents the new address
2208 for each register to be recomputed during the second
2210 reset_saved_regs (gdbarch
, this_cache
);
2215 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2216 && !regsize_is_64_bits
)
2218 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2220 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2221 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2222 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2223 || high_word
== 0x3c1c /* lui $gp,n */
2224 || high_word
== 0x279c /* addiu $gp,$gp,n */
2225 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2226 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2229 /* These instructions are part of the prologue, but we don't
2230 need to do anything special to handle them. */
2232 /* The instructions below load $at or $t0 with an immediate
2233 value in preparation for a stack adjustment via
2234 subu $sp,$sp,[$at,$t0]. These instructions could also
2235 initialize a local variable, so we accept them only before
2236 a stack adjustment instruction was seen. */
2237 else if (!seen_sp_adjust
2238 && (high_word
== 0x3c01 /* lui $at,n */
2239 || high_word
== 0x3c08 /* lui $t0,n */
2240 || high_word
== 0x3421 /* ori $at,$at,n */
2241 || high_word
== 0x3508 /* ori $t0,$t0,n */
2242 || high_word
== 0x3401 /* ori $at,$zero,n */
2243 || high_word
== 0x3408 /* ori $t0,$zero,n */
2246 if (end_prologue_addr
== 0)
2247 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2251 /* This instruction is not an instruction typically found
2252 in a prologue, so we must have reached the end of the
2254 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2255 loop now? Why would we need to continue scanning the function
2257 if (end_prologue_addr
== 0)
2258 end_prologue_addr
= cur_pc
;
2260 /* Check for branches and jumps. For now, only jump to
2261 register are caught (i.e. returns). */
2262 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2266 /* If the previous instruction was a jump, we must have reached
2267 the end of the prologue by now. Stop scanning so that we do
2268 not go past the function return. */
2273 if (this_cache
!= NULL
)
2276 (get_frame_register_signed (this_frame
,
2277 gdbarch_num_regs (gdbarch
) + frame_reg
)
2279 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2280 this assignment below, eventually. But it's still needed
2282 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2283 + mips_regnum (gdbarch
)->pc
]
2284 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2288 /* If we didn't reach the end of the prologue when scanning the function
2289 instructions, then set end_prologue_addr to the address of the
2290 instruction immediately after the last one we scanned. */
2291 /* brobecker/2004-10-10: I don't think this would ever happen, but
2292 we may as well be careful and do our best if we have a null
2293 end_prologue_addr. */
2294 if (end_prologue_addr
== 0)
2295 end_prologue_addr
= cur_pc
;
2297 /* In a frameless function, we might have incorrectly
2298 skipped some load immediate instructions. Undo the skipping
2299 if the load immediate was not followed by a stack adjustment. */
2300 if (load_immediate_bytes
&& !seen_sp_adjust
)
2301 end_prologue_addr
-= load_immediate_bytes
;
2303 return end_prologue_addr
;
2306 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2307 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2308 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2311 static struct mips_frame_cache
*
2312 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2314 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2315 struct mips_frame_cache
*cache
;
2317 if ((*this_cache
) != NULL
)
2318 return (*this_cache
);
2320 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2321 (*this_cache
) = cache
;
2322 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2324 /* Analyze the function prologue. */
2326 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2327 CORE_ADDR start_addr
;
2329 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2330 if (start_addr
== 0)
2331 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2332 /* We can't analyze the prologue if we couldn't find the begining
2334 if (start_addr
== 0)
2337 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2340 /* gdbarch_sp_regnum contains the value and not the address. */
2341 trad_frame_set_value (cache
->saved_regs
,
2342 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2345 return (*this_cache
);
2349 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2350 struct frame_id
*this_id
)
2352 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2354 /* This marks the outermost frame. */
2355 if (info
->base
== 0)
2357 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2360 static struct value
*
2361 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2362 void **this_cache
, int regnum
)
2364 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2366 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2370 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2371 struct frame_info
*this_frame
, void **this_cache
)
2373 CORE_ADDR pc
= get_frame_pc (this_frame
);
2374 if (! mips_pc_is_mips16 (pc
))
2379 static const struct frame_unwind mips_insn32_frame_unwind
=
2382 default_frame_unwind_stop_reason
,
2383 mips_insn32_frame_this_id
,
2384 mips_insn32_frame_prev_register
,
2386 mips_insn32_frame_sniffer
2390 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2393 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2398 static const struct frame_base mips_insn32_frame_base
=
2400 &mips_insn32_frame_unwind
,
2401 mips_insn32_frame_base_address
,
2402 mips_insn32_frame_base_address
,
2403 mips_insn32_frame_base_address
2406 static const struct frame_base
*
2407 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2409 CORE_ADDR pc
= get_frame_pc (this_frame
);
2410 if (! mips_pc_is_mips16 (pc
))
2411 return &mips_insn32_frame_base
;
2416 static struct trad_frame_cache
*
2417 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2420 CORE_ADDR start_addr
;
2421 CORE_ADDR stack_addr
;
2422 struct trad_frame_cache
*this_trad_cache
;
2423 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2424 int num_regs
= gdbarch_num_regs (gdbarch
);
2426 if ((*this_cache
) != NULL
)
2427 return (*this_cache
);
2428 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2429 (*this_cache
) = this_trad_cache
;
2431 /* The return address is in the link register. */
2432 trad_frame_set_reg_realreg (this_trad_cache
,
2433 gdbarch_pc_regnum (gdbarch
),
2434 num_regs
+ MIPS_RA_REGNUM
);
2436 /* Frame ID, since it's a frameless / stackless function, no stack
2437 space is allocated and SP on entry is the current SP. */
2438 pc
= get_frame_pc (this_frame
);
2439 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2440 stack_addr
= get_frame_register_signed (this_frame
,
2441 num_regs
+ MIPS_SP_REGNUM
);
2442 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2444 /* Assume that the frame's base is the same as the
2446 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2448 return this_trad_cache
;
2452 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2453 struct frame_id
*this_id
)
2455 struct trad_frame_cache
*this_trad_cache
2456 = mips_stub_frame_cache (this_frame
, this_cache
);
2457 trad_frame_get_id (this_trad_cache
, this_id
);
2460 static struct value
*
2461 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2462 void **this_cache
, int regnum
)
2464 struct trad_frame_cache
*this_trad_cache
2465 = mips_stub_frame_cache (this_frame
, this_cache
);
2466 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2470 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2471 struct frame_info
*this_frame
, void **this_cache
)
2474 struct obj_section
*s
;
2475 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2476 struct minimal_symbol
*msym
;
2478 /* Use the stub unwinder for unreadable code. */
2479 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2482 if (in_plt_section (pc
, NULL
))
2485 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2486 s
= find_pc_section (pc
);
2489 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2490 ".MIPS.stubs") == 0)
2493 /* Calling a PIC function from a non-PIC function passes through a
2494 stub. The stub for foo is named ".pic.foo". */
2495 msym
= lookup_minimal_symbol_by_pc (pc
);
2497 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2498 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2504 static const struct frame_unwind mips_stub_frame_unwind
=
2507 default_frame_unwind_stop_reason
,
2508 mips_stub_frame_this_id
,
2509 mips_stub_frame_prev_register
,
2511 mips_stub_frame_sniffer
2515 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2518 struct trad_frame_cache
*this_trad_cache
2519 = mips_stub_frame_cache (this_frame
, this_cache
);
2520 return trad_frame_get_this_base (this_trad_cache
);
2523 static const struct frame_base mips_stub_frame_base
=
2525 &mips_stub_frame_unwind
,
2526 mips_stub_frame_base_address
,
2527 mips_stub_frame_base_address
,
2528 mips_stub_frame_base_address
2531 static const struct frame_base
*
2532 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2534 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2535 return &mips_stub_frame_base
;
2540 /* mips_addr_bits_remove - remove useless address bits */
2543 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2545 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2547 if (is_mips16_addr (addr
))
2548 addr
= unmake_mips16_addr (addr
);
2550 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2551 /* This hack is a work-around for existing boards using PMON, the
2552 simulator, and any other 64-bit targets that doesn't have true
2553 64-bit addressing. On these targets, the upper 32 bits of
2554 addresses are ignored by the hardware. Thus, the PC or SP are
2555 likely to have been sign extended to all 1s by instruction
2556 sequences that load 32-bit addresses. For example, a typical
2557 piece of code that loads an address is this:
2559 lui $r2, <upper 16 bits>
2560 ori $r2, <lower 16 bits>
2562 But the lui sign-extends the value such that the upper 32 bits
2563 may be all 1s. The workaround is simply to mask off these
2564 bits. In the future, gcc may be changed to support true 64-bit
2565 addressing, and this masking will have to be disabled. */
2566 return addr
&= 0xffffffffUL
;
2571 /* Instructions used during single-stepping of atomic sequences. */
2572 #define LL_OPCODE 0x30
2573 #define LLD_OPCODE 0x34
2574 #define SC_OPCODE 0x38
2575 #define SCD_OPCODE 0x3c
2577 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2578 instruction and ending with a SC/SCD instruction. If such a sequence
2579 is found, attempt to step through it. A breakpoint is placed at the end of
2583 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2584 struct address_space
*aspace
, CORE_ADDR pc
)
2586 CORE_ADDR breaks
[2] = {-1, -1};
2588 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2592 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2593 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2598 insn
= mips_fetch_instruction (gdbarch
, loc
);
2599 /* Assume all atomic sequences start with a ll/lld instruction. */
2600 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2603 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2605 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2608 loc
+= MIPS_INSN32_SIZE
;
2609 insn
= mips_fetch_instruction (gdbarch
, loc
);
2611 /* Assume that there is at most one branch in the atomic
2612 sequence. If a branch is found, put a breakpoint in its
2613 destination address. */
2614 switch (itype_op (insn
))
2616 case 0: /* SPECIAL */
2617 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2618 return 0; /* fallback to the standard single-step code. */
2620 case 1: /* REGIMM */
2621 is_branch
= ((itype_rt (insn
) & 0xc) == 0); /* B{LT,GE}Z* */
2625 return 0; /* fallback to the standard single-step code. */
2632 case 22: /* BLEZL */
2633 case 23: /* BGTTL */
2639 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2644 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2645 if (last_breakpoint
>= 1)
2646 return 0; /* More than one branch found, fallback to the
2647 standard single-step code. */
2648 breaks
[1] = branch_bp
;
2652 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2656 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2657 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2660 loc
+= MIPS_INSN32_SIZE
;
2662 /* Insert a breakpoint right after the end of the atomic sequence. */
2665 /* Check for duplicated breakpoints. Check also for a breakpoint
2666 placed (branch instruction's destination) in the atomic sequence. */
2667 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2668 last_breakpoint
= 0;
2670 /* Effectively inserts the breakpoints. */
2671 for (index
= 0; index
<= last_breakpoint
; index
++)
2672 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2677 /* mips_software_single_step() is called just before we want to resume
2678 the inferior, if we want to single-step it but there is no hardware
2679 or kernel single-step support (MIPS on GNU/Linux for example). We find
2680 the target of the coming instruction and breakpoint it. */
2683 mips_software_single_step (struct frame_info
*frame
)
2685 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2686 struct address_space
*aspace
= get_frame_address_space (frame
);
2687 CORE_ADDR pc
, next_pc
;
2689 pc
= get_frame_pc (frame
);
2690 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2693 next_pc
= mips_next_pc (frame
, pc
);
2695 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2699 /* Test whether the PC points to the return instruction at the
2700 end of a function. */
2703 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2705 if (mips_pc_is_mips16 (pc
))
2706 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2707 generates a "jr $ra"; other times it generates code to load
2708 the return address from the stack to an accessible register (such
2709 as $a3), then a "jr" using that register. This second case
2710 is almost impossible to distinguish from an indirect jump
2711 used for switch statements, so we don't even try. */
2712 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2714 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2718 /* This fencepost looks highly suspicious to me. Removing it also
2719 seems suspicious as it could affect remote debugging across serial
2723 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2729 struct inferior
*inf
;
2731 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2733 fence
= start_pc
- heuristic_fence_post
;
2737 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2738 fence
= VM_MIN_ADDRESS
;
2740 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2742 inf
= current_inferior ();
2744 /* Search back for previous return. */
2745 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2746 if (start_pc
< fence
)
2748 /* It's not clear to me why we reach this point when
2749 stop_soon, but with this test, at least we
2750 don't print out warnings for every child forked (eg, on
2751 decstation). 22apr93 rich@cygnus.com. */
2752 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2754 static int blurb_printed
= 0;
2756 warning (_("GDB can't find the start of the function at %s."),
2757 paddress (gdbarch
, pc
));
2761 /* This actually happens frequently in embedded
2762 development, when you first connect to a board
2763 and your stack pointer and pc are nowhere in
2764 particular. This message needs to give people
2765 in that situation enough information to
2766 determine that it's no big deal. */
2767 printf_filtered ("\n\
2768 GDB is unable to find the start of the function at %s\n\
2769 and thus can't determine the size of that function's stack frame.\n\
2770 This means that GDB may be unable to access that stack frame, or\n\
2771 the frames below it.\n\
2772 This problem is most likely caused by an invalid program counter or\n\
2774 However, if you think GDB should simply search farther back\n\
2775 from %s for code which looks like the beginning of a\n\
2776 function, you can increase the range of the search using the `set\n\
2777 heuristic-fence-post' command.\n",
2778 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2785 else if (mips_pc_is_mips16 (start_pc
))
2787 unsigned short inst
;
2789 /* On MIPS16, any one of the following is likely to be the
2790 start of a function:
2796 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2797 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2798 if ((inst
& 0xff80) == 0x6480) /* save */
2800 if (start_pc
- instlen
>= fence
)
2802 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2803 if ((inst
& 0xf800) == 0xf000) /* extend */
2804 start_pc
-= instlen
;
2808 else if (((inst
& 0xf81f) == 0xe809
2809 && (inst
& 0x700) != 0x700) /* entry */
2810 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2811 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2812 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2814 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2815 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2820 else if (mips_about_to_return (gdbarch
, start_pc
))
2822 /* Skip return and its delay slot. */
2823 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2830 struct mips_objfile_private
2836 /* According to the current ABI, should the type be passed in a
2837 floating-point register (assuming that there is space)? When there
2838 is no FPU, FP are not even considered as possible candidates for
2839 FP registers and, consequently this returns false - forces FP
2840 arguments into integer registers. */
2843 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2844 struct type
*arg_type
)
2846 return ((typecode
== TYPE_CODE_FLT
2847 || (MIPS_EABI (gdbarch
)
2848 && (typecode
== TYPE_CODE_STRUCT
2849 || typecode
== TYPE_CODE_UNION
)
2850 && TYPE_NFIELDS (arg_type
) == 1
2851 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2853 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2856 /* On o32, argument passing in GPRs depends on the alignment of the type being
2857 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2860 mips_type_needs_double_align (struct type
*type
)
2862 enum type_code typecode
= TYPE_CODE (type
);
2864 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2866 else if (typecode
== TYPE_CODE_STRUCT
)
2868 if (TYPE_NFIELDS (type
) < 1)
2870 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2872 else if (typecode
== TYPE_CODE_UNION
)
2876 n
= TYPE_NFIELDS (type
);
2877 for (i
= 0; i
< n
; i
++)
2878 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2885 /* Adjust the address downward (direction of stack growth) so that it
2886 is correctly aligned for a new stack frame. */
2888 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2890 return align_down (addr
, 16);
2894 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2895 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2896 int nargs
, struct value
**args
, CORE_ADDR sp
,
2897 int struct_return
, CORE_ADDR struct_addr
)
2903 int stack_offset
= 0;
2904 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2905 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2906 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2907 int regsize
= mips_abi_regsize (gdbarch
);
2909 /* For shared libraries, "t9" needs to point at the function
2911 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2913 /* Set the return address register to point to the entry point of
2914 the program, where a breakpoint lies in wait. */
2915 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2917 /* First ensure that the stack and structure return address (if any)
2918 are properly aligned. The stack has to be at least 64-bit
2919 aligned even on 32-bit machines, because doubles must be 64-bit
2920 aligned. For n32 and n64, stack frames need to be 128-bit
2921 aligned, so we round to this widest known alignment. */
2923 sp
= align_down (sp
, 16);
2924 struct_addr
= align_down (struct_addr
, 16);
2926 /* Now make space on the stack for the args. We allocate more
2927 than necessary for EABI, because the first few arguments are
2928 passed in registers, but that's OK. */
2929 for (argnum
= 0; argnum
< nargs
; argnum
++)
2930 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2931 sp
-= align_up (len
, 16);
2934 fprintf_unfiltered (gdb_stdlog
,
2935 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2936 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2938 /* Initialize the integer and float register pointers. */
2939 argreg
= MIPS_A0_REGNUM
;
2940 float_argreg
= mips_fpa0_regnum (gdbarch
);
2942 /* The struct_return pointer occupies the first parameter-passing reg. */
2946 fprintf_unfiltered (gdb_stdlog
,
2947 "mips_eabi_push_dummy_call: "
2948 "struct_return reg=%d %s\n",
2949 argreg
, paddress (gdbarch
, struct_addr
));
2950 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2953 /* Now load as many as possible of the first arguments into
2954 registers, and push the rest onto the stack. Loop thru args
2955 from first to last. */
2956 for (argnum
= 0; argnum
< nargs
; argnum
++)
2958 const gdb_byte
*val
;
2959 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2960 struct value
*arg
= args
[argnum
];
2961 struct type
*arg_type
= check_typedef (value_type (arg
));
2962 int len
= TYPE_LENGTH (arg_type
);
2963 enum type_code typecode
= TYPE_CODE (arg_type
);
2966 fprintf_unfiltered (gdb_stdlog
,
2967 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2968 argnum
+ 1, len
, (int) typecode
);
2970 /* Function pointer arguments to mips16 code need to be made into
2972 if (typecode
== TYPE_CODE_PTR
2973 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
2975 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
2977 if (mips_pc_is_mips16 (addr
))
2979 store_signed_integer (valbuf
, len
, byte_order
,
2980 make_mips16_addr (addr
));
2984 val
= value_contents (arg
);
2986 /* The EABI passes structures that do not fit in a register by
2988 else if (len
> regsize
2989 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2991 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2992 value_address (arg
));
2993 typecode
= TYPE_CODE_PTR
;
2997 fprintf_unfiltered (gdb_stdlog
, " push");
3000 val
= value_contents (arg
);
3002 /* 32-bit ABIs always start floating point arguments in an
3003 even-numbered floating point register. Round the FP register
3004 up before the check to see if there are any FP registers
3005 left. Non MIPS_EABI targets also pass the FP in the integer
3006 registers so also round up normal registers. */
3007 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3009 if ((float_argreg
& 1))
3013 /* Floating point arguments passed in registers have to be
3014 treated specially. On 32-bit architectures, doubles
3015 are passed in register pairs; the even register gets
3016 the low word, and the odd register gets the high word.
3017 On non-EABI processors, the first two floating point arguments are
3018 also copied to general registers, because MIPS16 functions
3019 don't use float registers for arguments. This duplication of
3020 arguments in general registers can't hurt non-MIPS16 functions
3021 because those registers are normally skipped. */
3022 /* MIPS_EABI squeezes a struct that contains a single floating
3023 point value into an FP register instead of pushing it onto the
3025 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3026 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3028 /* EABI32 will pass doubles in consecutive registers, even on
3029 64-bit cores. At one time, we used to check the size of
3030 `float_argreg' to determine whether or not to pass doubles
3031 in consecutive registers, but this is not sufficient for
3032 making the ABI determination. */
3033 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3035 int low_offset
= gdbarch_byte_order (gdbarch
)
3036 == BFD_ENDIAN_BIG
? 4 : 0;
3039 /* Write the low word of the double to the even register(s). */
3040 regval
= extract_signed_integer (val
+ low_offset
,
3043 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3044 float_argreg
, phex (regval
, 4));
3045 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3047 /* Write the high word of the double to the odd register(s). */
3048 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3051 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3052 float_argreg
, phex (regval
, 4));
3053 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3057 /* This is a floating point value that fits entirely
3058 in a single register. */
3059 /* On 32 bit ABI's the float_argreg is further adjusted
3060 above to ensure that it is even register aligned. */
3061 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3063 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3064 float_argreg
, phex (regval
, len
));
3065 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3070 /* Copy the argument to general registers or the stack in
3071 register-sized pieces. Large arguments are split between
3072 registers and stack. */
3073 /* Note: structs whose size is not a multiple of regsize
3074 are treated specially: Irix cc passes
3075 them in registers where gcc sometimes puts them on the
3076 stack. For maximum compatibility, we will put them in
3078 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3080 /* Note: Floating-point values that didn't fit into an FP
3081 register are only written to memory. */
3084 /* Remember if the argument was written to the stack. */
3085 int stack_used_p
= 0;
3086 int partial_len
= (len
< regsize
? len
: regsize
);
3089 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3092 /* Write this portion of the argument to the stack. */
3093 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3095 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3097 /* Should shorter than int integer values be
3098 promoted to int before being stored? */
3099 int longword_offset
= 0;
3102 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3105 && (typecode
== TYPE_CODE_INT
3106 || typecode
== TYPE_CODE_PTR
3107 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3108 longword_offset
= regsize
- len
;
3109 else if ((typecode
== TYPE_CODE_STRUCT
3110 || typecode
== TYPE_CODE_UNION
)
3111 && TYPE_LENGTH (arg_type
) < regsize
)
3112 longword_offset
= regsize
- len
;
3117 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3118 paddress (gdbarch
, stack_offset
));
3119 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3120 paddress (gdbarch
, longword_offset
));
3123 addr
= sp
+ stack_offset
+ longword_offset
;
3128 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3129 paddress (gdbarch
, addr
));
3130 for (i
= 0; i
< partial_len
; i
++)
3132 fprintf_unfiltered (gdb_stdlog
, "%02x",
3136 write_memory (addr
, val
, partial_len
);
3139 /* Note!!! This is NOT an else clause. Odd sized
3140 structs may go thru BOTH paths. Floating point
3141 arguments will not. */
3142 /* Write this portion of the argument to a general
3143 purpose register. */
3144 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3145 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3148 extract_signed_integer (val
, partial_len
, byte_order
);
3151 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3153 phex (regval
, regsize
));
3154 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3161 /* Compute the offset into the stack at which we will
3162 copy the next parameter.
3164 In the new EABI (and the NABI32), the stack_offset
3165 only needs to be adjusted when it has been used. */
3168 stack_offset
+= align_up (partial_len
, regsize
);
3172 fprintf_unfiltered (gdb_stdlog
, "\n");
3175 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3177 /* Return adjusted stack pointer. */
3181 /* Determine the return value convention being used. */
3183 static enum return_value_convention
3184 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3185 struct type
*type
, struct regcache
*regcache
,
3186 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3189 int fp_return_type
= 0;
3190 int offset
, regnum
, xfer
;
3192 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3193 return RETURN_VALUE_STRUCT_CONVENTION
;
3195 /* Floating point type? */
3196 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3198 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3200 /* Structs with a single field of float type
3201 are returned in a floating point register. */
3202 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3203 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3204 && TYPE_NFIELDS (type
) == 1)
3206 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3208 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3215 /* A floating-point value belongs in the least significant part
3218 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3219 regnum
= mips_regnum (gdbarch
)->fp0
;
3223 /* An integer value goes in V0/V1. */
3225 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3226 regnum
= MIPS_V0_REGNUM
;
3229 offset
< TYPE_LENGTH (type
);
3230 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3232 xfer
= mips_abi_regsize (gdbarch
);
3233 if (offset
+ xfer
> TYPE_LENGTH (type
))
3234 xfer
= TYPE_LENGTH (type
) - offset
;
3235 mips_xfer_register (gdbarch
, regcache
,
3236 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3237 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3241 return RETURN_VALUE_REGISTER_CONVENTION
;
3245 /* N32/N64 ABI stuff. */
3247 /* Search for a naturally aligned double at OFFSET inside a struct
3248 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3252 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3257 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3260 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3263 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3266 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3269 struct type
*field_type
;
3271 /* We're only looking at normal fields. */
3272 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3273 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3276 /* If we have gone past the offset, there is no double to pass. */
3277 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3281 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3283 /* If this field is entirely before the requested offset, go
3284 on to the next one. */
3285 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3288 /* If this is our special aligned double, we can stop. */
3289 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3290 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3293 /* This field starts at or before the requested offset, and
3294 overlaps it. If it is a structure, recurse inwards. */
3295 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3302 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3303 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3304 int nargs
, struct value
**args
, CORE_ADDR sp
,
3305 int struct_return
, CORE_ADDR struct_addr
)
3311 int stack_offset
= 0;
3312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3313 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3314 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3316 /* For shared libraries, "t9" needs to point at the function
3318 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3320 /* Set the return address register to point to the entry point of
3321 the program, where a breakpoint lies in wait. */
3322 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3324 /* First ensure that the stack and structure return address (if any)
3325 are properly aligned. The stack has to be at least 64-bit
3326 aligned even on 32-bit machines, because doubles must be 64-bit
3327 aligned. For n32 and n64, stack frames need to be 128-bit
3328 aligned, so we round to this widest known alignment. */
3330 sp
= align_down (sp
, 16);
3331 struct_addr
= align_down (struct_addr
, 16);
3333 /* Now make space on the stack for the args. */
3334 for (argnum
= 0; argnum
< nargs
; argnum
++)
3335 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3336 sp
-= align_up (len
, 16);
3339 fprintf_unfiltered (gdb_stdlog
,
3340 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3341 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3343 /* Initialize the integer and float register pointers. */
3344 argreg
= MIPS_A0_REGNUM
;
3345 float_argreg
= mips_fpa0_regnum (gdbarch
);
3347 /* The struct_return pointer occupies the first parameter-passing reg. */
3351 fprintf_unfiltered (gdb_stdlog
,
3352 "mips_n32n64_push_dummy_call: "
3353 "struct_return reg=%d %s\n",
3354 argreg
, paddress (gdbarch
, struct_addr
));
3355 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3358 /* Now load as many as possible of the first arguments into
3359 registers, and push the rest onto the stack. Loop thru args
3360 from first to last. */
3361 for (argnum
= 0; argnum
< nargs
; argnum
++)
3363 const gdb_byte
*val
;
3364 struct value
*arg
= args
[argnum
];
3365 struct type
*arg_type
= check_typedef (value_type (arg
));
3366 int len
= TYPE_LENGTH (arg_type
);
3367 enum type_code typecode
= TYPE_CODE (arg_type
);
3370 fprintf_unfiltered (gdb_stdlog
,
3371 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3372 argnum
+ 1, len
, (int) typecode
);
3374 val
= value_contents (arg
);
3376 /* A 128-bit long double value requires an even-odd pair of
3377 floating-point registers. */
3379 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3380 && (float_argreg
& 1))
3386 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3387 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3389 /* This is a floating point value that fits entirely
3390 in a single register or a pair of registers. */
3391 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3392 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3394 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3395 float_argreg
, phex (regval
, reglen
));
3396 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3399 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3400 argreg
, phex (regval
, reglen
));
3401 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3406 regval
= extract_unsigned_integer (val
+ reglen
,
3407 reglen
, byte_order
);
3409 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3410 float_argreg
, phex (regval
, reglen
));
3411 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3414 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3415 argreg
, phex (regval
, reglen
));
3416 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3423 /* Copy the argument to general registers or the stack in
3424 register-sized pieces. Large arguments are split between
3425 registers and stack. */
3426 /* For N32/N64, structs, unions, or other composite types are
3427 treated as a sequence of doublewords, and are passed in integer
3428 or floating point registers as though they were simple scalar
3429 parameters to the extent that they fit, with any excess on the
3430 stack packed according to the normal memory layout of the
3432 The caller does not reserve space for the register arguments;
3433 the callee is responsible for reserving it if required. */
3434 /* Note: Floating-point values that didn't fit into an FP
3435 register are only written to memory. */
3438 /* Remember if the argument was written to the stack. */
3439 int stack_used_p
= 0;
3440 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3443 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3446 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3447 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3449 /* Write this portion of the argument to the stack. */
3450 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3452 /* Should shorter than int integer values be
3453 promoted to int before being stored? */
3454 int longword_offset
= 0;
3457 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3459 if ((typecode
== TYPE_CODE_INT
3460 || typecode
== TYPE_CODE_PTR
)
3462 longword_offset
= MIPS64_REGSIZE
- len
;
3467 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3468 paddress (gdbarch
, stack_offset
));
3469 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3470 paddress (gdbarch
, longword_offset
));
3473 addr
= sp
+ stack_offset
+ longword_offset
;
3478 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3479 paddress (gdbarch
, addr
));
3480 for (i
= 0; i
< partial_len
; i
++)
3482 fprintf_unfiltered (gdb_stdlog
, "%02x",
3486 write_memory (addr
, val
, partial_len
);
3489 /* Note!!! This is NOT an else clause. Odd sized
3490 structs may go thru BOTH paths. */
3491 /* Write this portion of the argument to a general
3492 purpose register. */
3493 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3497 /* Sign extend pointers, 32-bit integers and signed
3498 16-bit and 8-bit integers; everything else is taken
3501 if ((partial_len
== 4
3502 && (typecode
== TYPE_CODE_PTR
3503 || typecode
== TYPE_CODE_INT
))
3505 && typecode
== TYPE_CODE_INT
3506 && !TYPE_UNSIGNED (arg_type
)))
3507 regval
= extract_signed_integer (val
, partial_len
,
3510 regval
= extract_unsigned_integer (val
, partial_len
,
3513 /* A non-floating-point argument being passed in a
3514 general register. If a struct or union, and if
3515 the remaining length is smaller than the register
3516 size, we have to adjust the register value on
3519 It does not seem to be necessary to do the
3520 same for integral types. */
3522 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3523 && partial_len
< MIPS64_REGSIZE
3524 && (typecode
== TYPE_CODE_STRUCT
3525 || typecode
== TYPE_CODE_UNION
))
3526 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3530 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3532 phex (regval
, MIPS64_REGSIZE
));
3533 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3535 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3536 TYPE_LENGTH (arg_type
) - len
))
3539 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3541 phex (regval
, MIPS64_REGSIZE
));
3542 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3553 /* Compute the offset into the stack at which we will
3554 copy the next parameter.
3556 In N32 (N64?), the stack_offset only needs to be
3557 adjusted when it has been used. */
3560 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3564 fprintf_unfiltered (gdb_stdlog
, "\n");
3567 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3569 /* Return adjusted stack pointer. */
3573 static enum return_value_convention
3574 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3575 struct type
*type
, struct regcache
*regcache
,
3576 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3578 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3580 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3582 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3583 if needed), as appropriate for the type. Composite results (struct,
3584 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3587 * A struct with only one or two floating point fields is returned in $f0
3588 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3591 * Any other composite results of at most 128 bits are returned in
3592 $2 (first 64 bits) and $3 (remainder, if necessary).
3594 * Larger composite results are handled by converting the function to a
3595 procedure with an implicit first parameter, which is a pointer to an area
3596 reserved by the caller to receive the result. [The o32-bit ABI requires
3597 that all composite results be handled by conversion to implicit first
3598 parameters. The MIPS/SGI Fortran implementation has always made a
3599 specific exception to return COMPLEX results in the floating point
3602 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3603 return RETURN_VALUE_STRUCT_CONVENTION
;
3604 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3605 && TYPE_LENGTH (type
) == 16
3606 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3608 /* A 128-bit floating-point value fills both $f0 and $f2. The
3609 two registers are used in the same as memory order, so the
3610 eight bytes with the lower memory address are in $f0. */
3612 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3613 mips_xfer_register (gdbarch
, regcache
,
3614 gdbarch_num_regs (gdbarch
)
3615 + mips_regnum (gdbarch
)->fp0
,
3616 8, gdbarch_byte_order (gdbarch
),
3617 readbuf
, writebuf
, 0);
3618 mips_xfer_register (gdbarch
, regcache
,
3619 gdbarch_num_regs (gdbarch
)
3620 + mips_regnum (gdbarch
)->fp0
+ 2,
3621 8, gdbarch_byte_order (gdbarch
),
3622 readbuf
? readbuf
+ 8 : readbuf
,
3623 writebuf
? writebuf
+ 8 : writebuf
, 0);
3624 return RETURN_VALUE_REGISTER_CONVENTION
;
3626 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3627 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3629 /* A single or double floating-point value that fits in FP0. */
3631 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3632 mips_xfer_register (gdbarch
, regcache
,
3633 gdbarch_num_regs (gdbarch
)
3634 + mips_regnum (gdbarch
)->fp0
,
3636 gdbarch_byte_order (gdbarch
),
3637 readbuf
, writebuf
, 0);
3638 return RETURN_VALUE_REGISTER_CONVENTION
;
3640 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3641 && TYPE_NFIELDS (type
) <= 2
3642 && TYPE_NFIELDS (type
) >= 1
3643 && ((TYPE_NFIELDS (type
) == 1
3644 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3646 || (TYPE_NFIELDS (type
) == 2
3647 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3649 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3650 == TYPE_CODE_FLT
))))
3652 /* A struct that contains one or two floats. Each value is part
3653 in the least significant part of their floating point
3654 register (or GPR, for soft float). */
3657 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3658 ? mips_regnum (gdbarch
)->fp0
3660 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3662 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3665 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3667 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3669 /* A 16-byte long double field goes in two consecutive
3671 mips_xfer_register (gdbarch
, regcache
,
3672 gdbarch_num_regs (gdbarch
) + regnum
,
3674 gdbarch_byte_order (gdbarch
),
3675 readbuf
, writebuf
, offset
);
3676 mips_xfer_register (gdbarch
, regcache
,
3677 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3679 gdbarch_byte_order (gdbarch
),
3680 readbuf
, writebuf
, offset
+ 8);
3683 mips_xfer_register (gdbarch
, regcache
,
3684 gdbarch_num_regs (gdbarch
) + regnum
,
3685 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3686 gdbarch_byte_order (gdbarch
),
3687 readbuf
, writebuf
, offset
);
3689 return RETURN_VALUE_REGISTER_CONVENTION
;
3691 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3692 || TYPE_CODE (type
) == TYPE_CODE_UNION
3693 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3695 /* A composite type. Extract the left justified value,
3696 regardless of the byte order. I.e. DO NOT USE
3700 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3701 offset
< TYPE_LENGTH (type
);
3702 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3704 int xfer
= register_size (gdbarch
, regnum
);
3705 if (offset
+ xfer
> TYPE_LENGTH (type
))
3706 xfer
= TYPE_LENGTH (type
) - offset
;
3708 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3709 offset
, xfer
, regnum
);
3710 mips_xfer_register (gdbarch
, regcache
,
3711 gdbarch_num_regs (gdbarch
) + regnum
,
3712 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3715 return RETURN_VALUE_REGISTER_CONVENTION
;
3719 /* A scalar extract each part but least-significant-byte
3723 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3724 offset
< TYPE_LENGTH (type
);
3725 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3727 int xfer
= register_size (gdbarch
, regnum
);
3728 if (offset
+ xfer
> TYPE_LENGTH (type
))
3729 xfer
= TYPE_LENGTH (type
) - offset
;
3731 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3732 offset
, xfer
, regnum
);
3733 mips_xfer_register (gdbarch
, regcache
,
3734 gdbarch_num_regs (gdbarch
) + regnum
,
3735 xfer
, gdbarch_byte_order (gdbarch
),
3736 readbuf
, writebuf
, offset
);
3738 return RETURN_VALUE_REGISTER_CONVENTION
;
3742 /* O32 ABI stuff. */
3745 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3746 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3747 int nargs
, struct value
**args
, CORE_ADDR sp
,
3748 int struct_return
, CORE_ADDR struct_addr
)
3754 int stack_offset
= 0;
3755 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3756 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3757 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3759 /* For shared libraries, "t9" needs to point at the function
3761 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3763 /* Set the return address register to point to the entry point of
3764 the program, where a breakpoint lies in wait. */
3765 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3767 /* First ensure that the stack and structure return address (if any)
3768 are properly aligned. The stack has to be at least 64-bit
3769 aligned even on 32-bit machines, because doubles must be 64-bit
3770 aligned. For n32 and n64, stack frames need to be 128-bit
3771 aligned, so we round to this widest known alignment. */
3773 sp
= align_down (sp
, 16);
3774 struct_addr
= align_down (struct_addr
, 16);
3776 /* Now make space on the stack for the args. */
3777 for (argnum
= 0; argnum
< nargs
; argnum
++)
3779 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3780 int arglen
= TYPE_LENGTH (arg_type
);
3782 /* Align to double-word if necessary. */
3783 if (mips_type_needs_double_align (arg_type
))
3784 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3785 /* Allocate space on the stack. */
3786 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3788 sp
-= align_up (len
, 16);
3791 fprintf_unfiltered (gdb_stdlog
,
3792 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3793 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3795 /* Initialize the integer and float register pointers. */
3796 argreg
= MIPS_A0_REGNUM
;
3797 float_argreg
= mips_fpa0_regnum (gdbarch
);
3799 /* The struct_return pointer occupies the first parameter-passing reg. */
3803 fprintf_unfiltered (gdb_stdlog
,
3804 "mips_o32_push_dummy_call: "
3805 "struct_return reg=%d %s\n",
3806 argreg
, paddress (gdbarch
, struct_addr
));
3807 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3808 stack_offset
+= MIPS32_REGSIZE
;
3811 /* Now load as many as possible of the first arguments into
3812 registers, and push the rest onto the stack. Loop thru args
3813 from first to last. */
3814 for (argnum
= 0; argnum
< nargs
; argnum
++)
3816 const gdb_byte
*val
;
3817 struct value
*arg
= args
[argnum
];
3818 struct type
*arg_type
= check_typedef (value_type (arg
));
3819 int len
= TYPE_LENGTH (arg_type
);
3820 enum type_code typecode
= TYPE_CODE (arg_type
);
3823 fprintf_unfiltered (gdb_stdlog
,
3824 "mips_o32_push_dummy_call: %d len=%d type=%d",
3825 argnum
+ 1, len
, (int) typecode
);
3827 val
= value_contents (arg
);
3829 /* 32-bit ABIs always start floating point arguments in an
3830 even-numbered floating point register. Round the FP register
3831 up before the check to see if there are any FP registers
3832 left. O32/O64 targets also pass the FP in the integer
3833 registers so also round up normal registers. */
3834 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3836 if ((float_argreg
& 1))
3840 /* Floating point arguments passed in registers have to be
3841 treated specially. On 32-bit architectures, doubles
3842 are passed in register pairs; the even register gets
3843 the low word, and the odd register gets the high word.
3844 On O32/O64, the first two floating point arguments are
3845 also copied to general registers, because MIPS16 functions
3846 don't use float registers for arguments. This duplication of
3847 arguments in general registers can't hurt non-MIPS16 functions
3848 because those registers are normally skipped. */
3850 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3851 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3853 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3855 int low_offset
= gdbarch_byte_order (gdbarch
)
3856 == BFD_ENDIAN_BIG
? 4 : 0;
3857 unsigned long regval
;
3859 /* Write the low word of the double to the even register(s). */
3860 regval
= extract_unsigned_integer (val
+ low_offset
,
3863 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3864 float_argreg
, phex (regval
, 4));
3865 regcache_cooked_write_unsigned (regcache
,
3866 float_argreg
++, regval
);
3868 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3869 argreg
, phex (regval
, 4));
3870 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3872 /* Write the high word of the double to the odd register(s). */
3873 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3876 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3877 float_argreg
, phex (regval
, 4));
3878 regcache_cooked_write_unsigned (regcache
,
3879 float_argreg
++, regval
);
3882 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3883 argreg
, phex (regval
, 4));
3884 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3888 /* This is a floating point value that fits entirely
3889 in a single register. */
3890 /* On 32 bit ABI's the float_argreg is further adjusted
3891 above to ensure that it is even register aligned. */
3892 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3894 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3895 float_argreg
, phex (regval
, len
));
3896 regcache_cooked_write_unsigned (regcache
,
3897 float_argreg
++, regval
);
3898 /* Although two FP registers are reserved for each
3899 argument, only one corresponding integer register is
3902 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3903 argreg
, phex (regval
, len
));
3904 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3906 /* Reserve space for the FP register. */
3907 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3911 /* Copy the argument to general registers or the stack in
3912 register-sized pieces. Large arguments are split between
3913 registers and stack. */
3914 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3915 are treated specially: Irix cc passes
3916 them in registers where gcc sometimes puts them on the
3917 stack. For maximum compatibility, we will put them in
3919 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3920 && len
% MIPS32_REGSIZE
!= 0);
3921 /* Structures should be aligned to eight bytes (even arg registers)
3922 on MIPS_ABI_O32, if their first member has double precision. */
3923 if (mips_type_needs_double_align (arg_type
))
3928 stack_offset
+= MIPS32_REGSIZE
;
3933 /* Remember if the argument was written to the stack. */
3934 int stack_used_p
= 0;
3935 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3938 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3941 /* Write this portion of the argument to the stack. */
3942 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3943 || odd_sized_struct
)
3945 /* Should shorter than int integer values be
3946 promoted to int before being stored? */
3947 int longword_offset
= 0;
3953 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3954 paddress (gdbarch
, stack_offset
));
3955 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3956 paddress (gdbarch
, longword_offset
));
3959 addr
= sp
+ stack_offset
+ longword_offset
;
3964 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3965 paddress (gdbarch
, addr
));
3966 for (i
= 0; i
< partial_len
; i
++)
3968 fprintf_unfiltered (gdb_stdlog
, "%02x",
3972 write_memory (addr
, val
, partial_len
);
3975 /* Note!!! This is NOT an else clause. Odd sized
3976 structs may go thru BOTH paths. */
3977 /* Write this portion of the argument to a general
3978 purpose register. */
3979 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3981 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3983 /* Value may need to be sign extended, because
3984 mips_isa_regsize() != mips_abi_regsize(). */
3986 /* A non-floating-point argument being passed in a
3987 general register. If a struct or union, and if
3988 the remaining length is smaller than the register
3989 size, we have to adjust the register value on
3992 It does not seem to be necessary to do the
3993 same for integral types.
3995 Also don't do this adjustment on O64 binaries.
3997 cagney/2001-07-23: gdb/179: Also, GCC, when
3998 outputting LE O32 with sizeof (struct) <
3999 mips_abi_regsize(), generates a left shift
4000 as part of storing the argument in a register
4001 (the left shift isn't generated when
4002 sizeof (struct) >= mips_abi_regsize()). Since
4003 it is quite possible that this is GCC
4004 contradicting the LE/O32 ABI, GDB has not been
4005 adjusted to accommodate this. Either someone
4006 needs to demonstrate that the LE/O32 ABI
4007 specifies such a left shift OR this new ABI gets
4008 identified as such and GDB gets tweaked
4011 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4012 && partial_len
< MIPS32_REGSIZE
4013 && (typecode
== TYPE_CODE_STRUCT
4014 || typecode
== TYPE_CODE_UNION
))
4015 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4019 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4021 phex (regval
, MIPS32_REGSIZE
));
4022 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4025 /* Prevent subsequent floating point arguments from
4026 being passed in floating point registers. */
4027 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4033 /* Compute the offset into the stack at which we will
4034 copy the next parameter.
4036 In older ABIs, the caller reserved space for
4037 registers that contained arguments. This was loosely
4038 refered to as their "home". Consequently, space is
4039 always allocated. */
4041 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4045 fprintf_unfiltered (gdb_stdlog
, "\n");
4048 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4050 /* Return adjusted stack pointer. */
4054 static enum return_value_convention
4055 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4056 struct type
*type
, struct regcache
*regcache
,
4057 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4059 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4061 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4062 || TYPE_CODE (type
) == TYPE_CODE_UNION
4063 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4064 return RETURN_VALUE_STRUCT_CONVENTION
;
4065 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4066 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4068 /* A single-precision floating-point value. It fits in the
4069 least significant part of FP0. */
4071 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4072 mips_xfer_register (gdbarch
, regcache
,
4073 gdbarch_num_regs (gdbarch
)
4074 + mips_regnum (gdbarch
)->fp0
,
4076 gdbarch_byte_order (gdbarch
),
4077 readbuf
, writebuf
, 0);
4078 return RETURN_VALUE_REGISTER_CONVENTION
;
4080 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4081 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4083 /* A double-precision floating-point value. The most
4084 significant part goes in FP1, and the least significant in
4087 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4088 switch (gdbarch_byte_order (gdbarch
))
4090 case BFD_ENDIAN_LITTLE
:
4091 mips_xfer_register (gdbarch
, regcache
,
4092 gdbarch_num_regs (gdbarch
)
4093 + mips_regnum (gdbarch
)->fp0
+
4094 0, 4, gdbarch_byte_order (gdbarch
),
4095 readbuf
, writebuf
, 0);
4096 mips_xfer_register (gdbarch
, regcache
,
4097 gdbarch_num_regs (gdbarch
)
4098 + mips_regnum (gdbarch
)->fp0
+ 1,
4099 4, gdbarch_byte_order (gdbarch
),
4100 readbuf
, writebuf
, 4);
4102 case BFD_ENDIAN_BIG
:
4103 mips_xfer_register (gdbarch
, regcache
,
4104 gdbarch_num_regs (gdbarch
)
4105 + mips_regnum (gdbarch
)->fp0
+ 1,
4106 4, gdbarch_byte_order (gdbarch
),
4107 readbuf
, writebuf
, 0);
4108 mips_xfer_register (gdbarch
, regcache
,
4109 gdbarch_num_regs (gdbarch
)
4110 + mips_regnum (gdbarch
)->fp0
+ 0,
4111 4, gdbarch_byte_order (gdbarch
),
4112 readbuf
, writebuf
, 4);
4115 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4117 return RETURN_VALUE_REGISTER_CONVENTION
;
4120 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4121 && TYPE_NFIELDS (type
) <= 2
4122 && TYPE_NFIELDS (type
) >= 1
4123 && ((TYPE_NFIELDS (type
) == 1
4124 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4126 || (TYPE_NFIELDS (type
) == 2
4127 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4129 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4131 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4133 /* A struct that contains one or two floats. Each value is part
4134 in the least significant part of their floating point
4136 gdb_byte reg
[MAX_REGISTER_SIZE
];
4139 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4140 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4142 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4145 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4147 mips_xfer_register (gdbarch
, regcache
,
4148 gdbarch_num_regs (gdbarch
) + regnum
,
4149 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4150 gdbarch_byte_order (gdbarch
),
4151 readbuf
, writebuf
, offset
);
4153 return RETURN_VALUE_REGISTER_CONVENTION
;
4157 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4158 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4160 /* A structure or union. Extract the left justified value,
4161 regardless of the byte order. I.e. DO NOT USE
4165 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4166 offset
< TYPE_LENGTH (type
);
4167 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4169 int xfer
= register_size (gdbarch
, regnum
);
4170 if (offset
+ xfer
> TYPE_LENGTH (type
))
4171 xfer
= TYPE_LENGTH (type
) - offset
;
4173 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4174 offset
, xfer
, regnum
);
4175 mips_xfer_register (gdbarch
, regcache
,
4176 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4177 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4179 return RETURN_VALUE_REGISTER_CONVENTION
;
4184 /* A scalar extract each part but least-significant-byte
4185 justified. o32 thinks registers are 4 byte, regardless of
4189 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4190 offset
< TYPE_LENGTH (type
);
4191 offset
+= MIPS32_REGSIZE
, regnum
++)
4193 int xfer
= MIPS32_REGSIZE
;
4194 if (offset
+ xfer
> TYPE_LENGTH (type
))
4195 xfer
= TYPE_LENGTH (type
) - offset
;
4197 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4198 offset
, xfer
, regnum
);
4199 mips_xfer_register (gdbarch
, regcache
,
4200 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4201 gdbarch_byte_order (gdbarch
),
4202 readbuf
, writebuf
, offset
);
4204 return RETURN_VALUE_REGISTER_CONVENTION
;
4208 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4212 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4213 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4215 struct value
**args
, CORE_ADDR sp
,
4216 int struct_return
, CORE_ADDR struct_addr
)
4222 int stack_offset
= 0;
4223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4224 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4225 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4227 /* For shared libraries, "t9" needs to point at the function
4229 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4231 /* Set the return address register to point to the entry point of
4232 the program, where a breakpoint lies in wait. */
4233 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4235 /* First ensure that the stack and structure return address (if any)
4236 are properly aligned. The stack has to be at least 64-bit
4237 aligned even on 32-bit machines, because doubles must be 64-bit
4238 aligned. For n32 and n64, stack frames need to be 128-bit
4239 aligned, so we round to this widest known alignment. */
4241 sp
= align_down (sp
, 16);
4242 struct_addr
= align_down (struct_addr
, 16);
4244 /* Now make space on the stack for the args. */
4245 for (argnum
= 0; argnum
< nargs
; argnum
++)
4247 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4248 int arglen
= TYPE_LENGTH (arg_type
);
4250 /* Allocate space on the stack. */
4251 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4253 sp
-= align_up (len
, 16);
4256 fprintf_unfiltered (gdb_stdlog
,
4257 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4258 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4260 /* Initialize the integer and float register pointers. */
4261 argreg
= MIPS_A0_REGNUM
;
4262 float_argreg
= mips_fpa0_regnum (gdbarch
);
4264 /* The struct_return pointer occupies the first parameter-passing reg. */
4268 fprintf_unfiltered (gdb_stdlog
,
4269 "mips_o64_push_dummy_call: "
4270 "struct_return reg=%d %s\n",
4271 argreg
, paddress (gdbarch
, struct_addr
));
4272 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4273 stack_offset
+= MIPS64_REGSIZE
;
4276 /* Now load as many as possible of the first arguments into
4277 registers, and push the rest onto the stack. Loop thru args
4278 from first to last. */
4279 for (argnum
= 0; argnum
< nargs
; argnum
++)
4281 const gdb_byte
*val
;
4282 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4283 struct value
*arg
= args
[argnum
];
4284 struct type
*arg_type
= check_typedef (value_type (arg
));
4285 int len
= TYPE_LENGTH (arg_type
);
4286 enum type_code typecode
= TYPE_CODE (arg_type
);
4289 fprintf_unfiltered (gdb_stdlog
,
4290 "mips_o64_push_dummy_call: %d len=%d type=%d",
4291 argnum
+ 1, len
, (int) typecode
);
4293 val
= value_contents (arg
);
4295 /* Function pointer arguments to mips16 code need to be made into
4297 if (typecode
== TYPE_CODE_PTR
4298 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4300 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4302 if (mips_pc_is_mips16 (addr
))
4304 store_signed_integer (valbuf
, len
, byte_order
,
4305 make_mips16_addr (addr
));
4310 /* Floating point arguments passed in registers have to be
4311 treated specially. On 32-bit architectures, doubles
4312 are passed in register pairs; the even register gets
4313 the low word, and the odd register gets the high word.
4314 On O32/O64, the first two floating point arguments are
4315 also copied to general registers, because MIPS16 functions
4316 don't use float registers for arguments. This duplication of
4317 arguments in general registers can't hurt non-MIPS16 functions
4318 because those registers are normally skipped. */
4320 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4321 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4323 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4325 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4326 float_argreg
, phex (regval
, len
));
4327 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4329 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4330 argreg
, phex (regval
, len
));
4331 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4333 /* Reserve space for the FP register. */
4334 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4338 /* Copy the argument to general registers or the stack in
4339 register-sized pieces. Large arguments are split between
4340 registers and stack. */
4341 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4342 are treated specially: Irix cc passes them in registers
4343 where gcc sometimes puts them on the stack. For maximum
4344 compatibility, we will put them in both places. */
4345 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4346 && len
% MIPS64_REGSIZE
!= 0);
4349 /* Remember if the argument was written to the stack. */
4350 int stack_used_p
= 0;
4351 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4354 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4357 /* Write this portion of the argument to the stack. */
4358 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4359 || odd_sized_struct
)
4361 /* Should shorter than int integer values be
4362 promoted to int before being stored? */
4363 int longword_offset
= 0;
4366 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4368 if ((typecode
== TYPE_CODE_INT
4369 || typecode
== TYPE_CODE_PTR
4370 || typecode
== TYPE_CODE_FLT
)
4372 longword_offset
= MIPS64_REGSIZE
- len
;
4377 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4378 paddress (gdbarch
, stack_offset
));
4379 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4380 paddress (gdbarch
, longword_offset
));
4383 addr
= sp
+ stack_offset
+ longword_offset
;
4388 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4389 paddress (gdbarch
, addr
));
4390 for (i
= 0; i
< partial_len
; i
++)
4392 fprintf_unfiltered (gdb_stdlog
, "%02x",
4396 write_memory (addr
, val
, partial_len
);
4399 /* Note!!! This is NOT an else clause. Odd sized
4400 structs may go thru BOTH paths. */
4401 /* Write this portion of the argument to a general
4402 purpose register. */
4403 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4405 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4407 /* Value may need to be sign extended, because
4408 mips_isa_regsize() != mips_abi_regsize(). */
4410 /* A non-floating-point argument being passed in a
4411 general register. If a struct or union, and if
4412 the remaining length is smaller than the register
4413 size, we have to adjust the register value on
4416 It does not seem to be necessary to do the
4417 same for integral types. */
4419 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4420 && partial_len
< MIPS64_REGSIZE
4421 && (typecode
== TYPE_CODE_STRUCT
4422 || typecode
== TYPE_CODE_UNION
))
4423 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4427 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4429 phex (regval
, MIPS64_REGSIZE
));
4430 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4433 /* Prevent subsequent floating point arguments from
4434 being passed in floating point registers. */
4435 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4441 /* Compute the offset into the stack at which we will
4442 copy the next parameter.
4444 In older ABIs, the caller reserved space for
4445 registers that contained arguments. This was loosely
4446 refered to as their "home". Consequently, space is
4447 always allocated. */
4449 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4453 fprintf_unfiltered (gdb_stdlog
, "\n");
4456 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4458 /* Return adjusted stack pointer. */
4462 static enum return_value_convention
4463 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4464 struct type
*type
, struct regcache
*regcache
,
4465 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4469 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4470 || TYPE_CODE (type
) == TYPE_CODE_UNION
4471 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4472 return RETURN_VALUE_STRUCT_CONVENTION
;
4473 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4475 /* A floating-point value. It fits in the least significant
4478 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4479 mips_xfer_register (gdbarch
, regcache
,
4480 gdbarch_num_regs (gdbarch
)
4481 + mips_regnum (gdbarch
)->fp0
,
4483 gdbarch_byte_order (gdbarch
),
4484 readbuf
, writebuf
, 0);
4485 return RETURN_VALUE_REGISTER_CONVENTION
;
4489 /* A scalar extract each part but least-significant-byte
4493 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4494 offset
< TYPE_LENGTH (type
);
4495 offset
+= MIPS64_REGSIZE
, regnum
++)
4497 int xfer
= MIPS64_REGSIZE
;
4498 if (offset
+ xfer
> TYPE_LENGTH (type
))
4499 xfer
= TYPE_LENGTH (type
) - offset
;
4501 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4502 offset
, xfer
, regnum
);
4503 mips_xfer_register (gdbarch
, regcache
,
4504 gdbarch_num_regs (gdbarch
) + regnum
,
4505 xfer
, gdbarch_byte_order (gdbarch
),
4506 readbuf
, writebuf
, offset
);
4508 return RETURN_VALUE_REGISTER_CONVENTION
;
4512 /* Floating point register management.
4514 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4515 64bit operations, these early MIPS cpus treat fp register pairs
4516 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4517 registers and offer a compatibility mode that emulates the MIPS2 fp
4518 model. When operating in MIPS2 fp compat mode, later cpu's split
4519 double precision floats into two 32-bit chunks and store them in
4520 consecutive fp regs. To display 64-bit floats stored in this
4521 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4522 Throw in user-configurable endianness and you have a real mess.
4524 The way this works is:
4525 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4526 double-precision value will be split across two logical registers.
4527 The lower-numbered logical register will hold the low-order bits,
4528 regardless of the processor's endianness.
4529 - If we are on a 64-bit processor, and we are looking for a
4530 single-precision value, it will be in the low ordered bits
4531 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4532 save slot in memory.
4533 - If we are in 64-bit mode, everything is straightforward.
4535 Note that this code only deals with "live" registers at the top of the
4536 stack. We will attempt to deal with saved registers later, when
4537 the raw/cooked register interface is in place. (We need a general
4538 interface that can deal with dynamic saved register sizes -- fp
4539 regs could be 32 bits wide in one frame and 64 on the frame above
4542 /* Copy a 32-bit single-precision value from the current frame
4543 into rare_buffer. */
4546 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4547 gdb_byte
*rare_buffer
)
4549 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4550 int raw_size
= register_size (gdbarch
, regno
);
4551 gdb_byte
*raw_buffer
= alloca (raw_size
);
4553 if (!frame_register_read (frame
, regno
, raw_buffer
))
4554 error (_("can't read register %d (%s)"),
4555 regno
, gdbarch_register_name (gdbarch
, regno
));
4558 /* We have a 64-bit value for this register. Find the low-order
4562 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4567 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4571 memcpy (rare_buffer
, raw_buffer
, 4);
4575 /* Copy a 64-bit double-precision value from the current frame into
4576 rare_buffer. This may include getting half of it from the next
4580 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4581 gdb_byte
*rare_buffer
)
4583 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4584 int raw_size
= register_size (gdbarch
, regno
);
4586 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4588 /* We have a 64-bit value for this register, and we should use
4590 if (!frame_register_read (frame
, regno
, rare_buffer
))
4591 error (_("can't read register %d (%s)"),
4592 regno
, gdbarch_register_name (gdbarch
, regno
));
4596 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4598 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4599 internal_error (__FILE__
, __LINE__
,
4600 _("mips_read_fp_register_double: bad access to "
4601 "odd-numbered FP register"));
4603 /* mips_read_fp_register_single will find the correct 32 bits from
4605 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4607 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4608 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4612 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4613 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4619 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4621 { /* Do values for FP (float) regs. */
4622 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4623 gdb_byte
*raw_buffer
;
4624 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4627 raw_buffer
= alloca (2 * register_size (gdbarch
,
4628 mips_regnum (gdbarch
)->fp0
));
4630 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4631 fprintf_filtered (file
, "%*s",
4632 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4635 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4637 struct value_print_options opts
;
4639 /* 4-byte registers: Print hex and floating. Also print even
4640 numbered registers as doubles. */
4641 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4642 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4645 get_formatted_print_options (&opts
, 'x');
4646 print_scalar_formatted (raw_buffer
,
4647 builtin_type (gdbarch
)->builtin_uint32
,
4650 fprintf_filtered (file
, " flt: ");
4652 fprintf_filtered (file
, " <invalid float> ");
4654 fprintf_filtered (file
, "%-17.9g", flt1
);
4656 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4658 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4659 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4662 fprintf_filtered (file
, " dbl: ");
4664 fprintf_filtered (file
, "<invalid double>");
4666 fprintf_filtered (file
, "%-24.17g", doub
);
4671 struct value_print_options opts
;
4673 /* Eight byte registers: print each one as hex, float and double. */
4674 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4675 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4678 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4679 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4682 get_formatted_print_options (&opts
, 'x');
4683 print_scalar_formatted (raw_buffer
,
4684 builtin_type (gdbarch
)->builtin_uint64
,
4687 fprintf_filtered (file
, " flt: ");
4689 fprintf_filtered (file
, "<invalid float>");
4691 fprintf_filtered (file
, "%-17.9g", flt1
);
4693 fprintf_filtered (file
, " dbl: ");
4695 fprintf_filtered (file
, "<invalid double>");
4697 fprintf_filtered (file
, "%-24.17g", doub
);
4702 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4705 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4707 struct value_print_options opts
;
4710 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4712 mips_print_fp_register (file
, frame
, regnum
);
4716 val
= get_frame_register_value (frame
, regnum
);
4717 if (value_optimized_out (val
))
4719 fprintf_filtered (file
, "%s: [Invalid]",
4720 gdbarch_register_name (gdbarch
, regnum
));
4724 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4726 /* The problem with printing numeric register names (r26, etc.) is that
4727 the user can't use them on input. Probably the best solution is to
4728 fix it so that either the numeric or the funky (a2, etc.) names
4729 are accepted on input. */
4730 if (regnum
< MIPS_NUMREGS
)
4731 fprintf_filtered (file
, "(r%d): ", regnum
);
4733 fprintf_filtered (file
, ": ");
4735 get_formatted_print_options (&opts
, 'x');
4736 val_print_scalar_formatted (value_type (val
),
4737 value_contents_for_printing (val
),
4738 value_embedded_offset (val
),
4743 /* Replacement for generic do_registers_info.
4744 Print regs in pretty columns. */
4747 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4750 fprintf_filtered (file
, " ");
4751 mips_print_fp_register (file
, frame
, regnum
);
4752 fprintf_filtered (file
, "\n");
4757 /* Print a row's worth of GP (int) registers, with name labels above. */
4760 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4763 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4764 /* Do values for GP (int) regs. */
4765 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4766 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
4771 /* For GP registers, we print a separate row of names above the vals. */
4772 for (col
= 0, regnum
= start_regnum
;
4773 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4774 + gdbarch_num_pseudo_regs (gdbarch
);
4777 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4778 continue; /* unused register */
4779 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4781 break; /* End the row: reached FP register. */
4782 /* Large registers are handled separately. */
4783 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4786 break; /* End the row before this register. */
4788 /* Print this register on a row by itself. */
4789 mips_print_register (file
, frame
, regnum
);
4790 fprintf_filtered (file
, "\n");
4794 fprintf_filtered (file
, " ");
4795 fprintf_filtered (file
,
4796 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4797 gdbarch_register_name (gdbarch
, regnum
));
4804 /* Print the R0 to R31 names. */
4805 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4806 fprintf_filtered (file
, "\n R%-4d",
4807 start_regnum
% gdbarch_num_regs (gdbarch
));
4809 fprintf_filtered (file
, "\n ");
4811 /* Now print the values in hex, 4 or 8 to the row. */
4812 for (col
= 0, regnum
= start_regnum
;
4813 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4814 + gdbarch_num_pseudo_regs (gdbarch
);
4817 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4818 continue; /* unused register */
4819 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4821 break; /* End row: reached FP register. */
4822 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4823 break; /* End row: large register. */
4825 /* OK: get the data in raw format. */
4826 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4827 error (_("can't read register %d (%s)"),
4828 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4829 /* pad small registers */
4831 byte
< (mips_abi_regsize (gdbarch
)
4832 - register_size (gdbarch
, regnum
)); byte
++)
4833 printf_filtered (" ");
4834 /* Now print the register value in hex, endian order. */
4835 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4837 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4838 byte
< register_size (gdbarch
, regnum
); byte
++)
4839 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4841 for (byte
= register_size (gdbarch
, regnum
) - 1;
4843 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4844 fprintf_filtered (file
, " ");
4847 if (col
> 0) /* ie. if we actually printed anything... */
4848 fprintf_filtered (file
, "\n");
4853 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
4856 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4857 struct frame_info
*frame
, int regnum
, int all
)
4859 if (regnum
!= -1) /* Do one specified register. */
4861 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4862 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4863 error (_("Not a valid register for the current processor type"));
4865 mips_print_register (file
, frame
, regnum
);
4866 fprintf_filtered (file
, "\n");
4869 /* Do all (or most) registers. */
4871 regnum
= gdbarch_num_regs (gdbarch
);
4872 while (regnum
< gdbarch_num_regs (gdbarch
)
4873 + gdbarch_num_pseudo_regs (gdbarch
))
4875 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4878 if (all
) /* True for "INFO ALL-REGISTERS" command. */
4879 regnum
= print_fp_register_row (file
, frame
, regnum
);
4881 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
4884 regnum
= print_gp_register_row (file
, frame
, regnum
);
4889 /* Is this a branch with a delay slot? */
4892 is_delayed (unsigned long insn
)
4895 for (i
= 0; i
< NUMOPCODES
; ++i
)
4896 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4897 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4899 return (i
< NUMOPCODES
4900 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4901 | INSN_COND_BRANCH_DELAY
4902 | INSN_COND_BRANCH_LIKELY
)));
4906 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4907 struct frame_info
*frame
)
4909 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4910 CORE_ADDR pc
= get_frame_pc (frame
);
4911 gdb_byte buf
[MIPS_INSN32_SIZE
];
4913 /* There is no branch delay slot on MIPS16. */
4914 if (mips_pc_is_mips16 (pc
))
4917 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4920 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4921 /* If error reading memory, guess that it is not a delayed
4924 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4927 /* To skip prologues, I use this predicate. Returns either PC itself
4928 if the code at PC does not look like a function prologue; otherwise
4929 returns an address that (if we're lucky) follows the prologue. If
4930 LENIENT, then we must skip everything which is involved in setting
4931 up the frame (it's OK to skip more, just so long as we don't skip
4932 anything which might clobber the registers which are being saved.
4933 We must skip more in the case where part of the prologue is in the
4934 delay slot of a non-prologue instruction). */
4937 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4940 CORE_ADDR func_addr
;
4942 /* See if we can determine the end of the prologue via the symbol table.
4943 If so, then return either PC, or the PC after the prologue, whichever
4945 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4947 CORE_ADDR post_prologue_pc
4948 = skip_prologue_using_sal (gdbarch
, func_addr
);
4949 if (post_prologue_pc
!= 0)
4950 return max (pc
, post_prologue_pc
);
4953 /* Can't determine prologue from the symbol table, need to examine
4956 /* Find an upper limit on the function prologue using the debug
4957 information. If the debug information could not be used to provide
4958 that bound, then use an arbitrary large number as the upper bound. */
4959 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4961 limit_pc
= pc
+ 100; /* Magic. */
4963 if (mips_pc_is_mips16 (pc
))
4964 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4966 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4969 /* Check whether the PC is in a function epilogue (32-bit version).
4970 This is a helper function for mips_in_function_epilogue_p. */
4972 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4974 CORE_ADDR func_addr
= 0, func_end
= 0;
4976 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4978 /* The MIPS epilogue is max. 12 bytes long. */
4979 CORE_ADDR addr
= func_end
- 12;
4981 if (addr
< func_addr
+ 4)
4982 addr
= func_addr
+ 4;
4986 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4988 unsigned long high_word
;
4991 inst
= mips_fetch_instruction (gdbarch
, pc
);
4992 high_word
= (inst
>> 16) & 0xffff;
4994 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4995 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4996 && inst
!= 0x03e00008 /* jr $ra */
4997 && inst
!= 0x00000000) /* nop */
5007 /* Check whether the PC is in a function epilogue (16-bit version).
5008 This is a helper function for mips_in_function_epilogue_p. */
5010 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5012 CORE_ADDR func_addr
= 0, func_end
= 0;
5014 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5016 /* The MIPS epilogue is max. 12 bytes long. */
5017 CORE_ADDR addr
= func_end
- 12;
5019 if (addr
< func_addr
+ 4)
5020 addr
= func_addr
+ 4;
5024 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5026 unsigned short inst
;
5028 inst
= mips_fetch_instruction (gdbarch
, pc
);
5030 if ((inst
& 0xf800) == 0xf000) /* extend */
5033 if (inst
!= 0x6300 /* addiu $sp,offset */
5034 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5035 && inst
!= 0xe820 /* jr $ra */
5036 && inst
!= 0xe8a0 /* jrc $ra */
5037 && inst
!= 0x6500) /* nop */
5047 /* The epilogue is defined here as the area at the end of a function,
5048 after an instruction which destroys the function's stack frame. */
5050 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5052 if (mips_pc_is_mips16 (pc
))
5053 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5055 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5058 /* Root of all "set mips "/"show mips " commands. This will eventually be
5059 used for all MIPS-specific commands. */
5062 show_mips_command (char *args
, int from_tty
)
5064 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5068 set_mips_command (char *args
, int from_tty
)
5071 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5072 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5075 /* Commands to show/set the MIPS FPU type. */
5078 show_mipsfpu_command (char *args
, int from_tty
)
5082 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5085 ("The MIPS floating-point coprocessor is unknown "
5086 "because the current architecture is not MIPS.\n");
5090 switch (MIPS_FPU_TYPE (target_gdbarch
))
5092 case MIPS_FPU_SINGLE
:
5093 fpu
= "single-precision";
5095 case MIPS_FPU_DOUBLE
:
5096 fpu
= "double-precision";
5099 fpu
= "absent (none)";
5102 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5104 if (mips_fpu_type_auto
)
5105 printf_unfiltered ("The MIPS floating-point coprocessor "
5106 "is set automatically (currently %s)\n",
5110 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5115 set_mipsfpu_command (char *args
, int from_tty
)
5117 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5118 "\"single\",\"none\" or \"auto\".\n");
5119 show_mipsfpu_command (args
, from_tty
);
5123 set_mipsfpu_single_command (char *args
, int from_tty
)
5125 struct gdbarch_info info
;
5126 gdbarch_info_init (&info
);
5127 mips_fpu_type
= MIPS_FPU_SINGLE
;
5128 mips_fpu_type_auto
= 0;
5129 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5130 instead of relying on globals. Doing that would let generic code
5131 handle the search for this specific architecture. */
5132 if (!gdbarch_update_p (info
))
5133 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5137 set_mipsfpu_double_command (char *args
, int from_tty
)
5139 struct gdbarch_info info
;
5140 gdbarch_info_init (&info
);
5141 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5142 mips_fpu_type_auto
= 0;
5143 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5144 instead of relying on globals. Doing that would let generic code
5145 handle the search for this specific architecture. */
5146 if (!gdbarch_update_p (info
))
5147 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5151 set_mipsfpu_none_command (char *args
, int from_tty
)
5153 struct gdbarch_info info
;
5154 gdbarch_info_init (&info
);
5155 mips_fpu_type
= MIPS_FPU_NONE
;
5156 mips_fpu_type_auto
= 0;
5157 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5158 instead of relying on globals. Doing that would let generic code
5159 handle the search for this specific architecture. */
5160 if (!gdbarch_update_p (info
))
5161 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5165 set_mipsfpu_auto_command (char *args
, int from_tty
)
5167 mips_fpu_type_auto
= 1;
5170 /* Attempt to identify the particular processor model by reading the
5171 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5172 the relevant processor still exists (it dates back to '94) and
5173 secondly this is not the way to do this. The processor type should
5174 be set by forcing an architecture change. */
5177 deprecated_mips_set_processor_regs_hack (void)
5179 struct regcache
*regcache
= get_current_regcache ();
5180 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5181 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5184 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5185 if ((prid
& ~0xf) == 0x700)
5186 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5189 /* Just like reinit_frame_cache, but with the right arguments to be
5190 callable as an sfunc. */
5193 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5194 struct cmd_list_element
*c
)
5196 reinit_frame_cache ();
5200 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5202 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5203 disassembler needs to be able to locally determine the ISA, and
5204 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5206 if (mips_pc_is_mips16 (memaddr
))
5207 info
->mach
= bfd_mach_mips16
;
5209 /* Round down the instruction address to the appropriate boundary. */
5210 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5212 /* Set the disassembler options. */
5213 if (!info
->disassembler_options
)
5214 /* This string is not recognized explicitly by the disassembler,
5215 but it tells the disassembler to not try to guess the ABI from
5216 the bfd elf headers, such that, if the user overrides the ABI
5217 of a program linked as NewABI, the disassembly will follow the
5218 register naming conventions specified by the user. */
5219 info
->disassembler_options
= "gpr-names=32";
5221 /* Call the appropriate disassembler based on the target endian-ness. */
5222 if (info
->endian
== BFD_ENDIAN_BIG
)
5223 return print_insn_big_mips (memaddr
, info
);
5225 return print_insn_little_mips (memaddr
, info
);
5229 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5231 /* Set up the disassembler info, so that we get the right
5232 register names from libopcodes. */
5233 info
->disassembler_options
= "gpr-names=n32";
5234 info
->flavour
= bfd_target_elf_flavour
;
5236 return gdb_print_insn_mips (memaddr
, info
);
5240 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5242 /* Set up the disassembler info, so that we get the right
5243 register names from libopcodes. */
5244 info
->disassembler_options
= "gpr-names=64";
5245 info
->flavour
= bfd_target_elf_flavour
;
5247 return gdb_print_insn_mips (memaddr
, info
);
5250 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5251 program counter value to determine whether a 16- or 32-bit breakpoint
5252 should be used. It returns a pointer to a string of bytes that encode a
5253 breakpoint instruction, stores the length of the string to *lenptr, and
5254 adjusts pc (if necessary) to point to the actual memory location where
5255 the breakpoint should be inserted. */
5257 static const gdb_byte
*
5258 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5259 CORE_ADDR
*pcptr
, int *lenptr
)
5261 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5263 if (mips_pc_is_mips16 (*pcptr
))
5265 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5266 *pcptr
= unmake_mips16_addr (*pcptr
);
5267 *lenptr
= sizeof (mips16_big_breakpoint
);
5268 return mips16_big_breakpoint
;
5272 /* The IDT board uses an unusual breakpoint value, and
5273 sometimes gets confused when it sees the usual MIPS
5274 breakpoint instruction. */
5275 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5276 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5277 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5278 /* Likewise, IRIX appears to expect a different breakpoint,
5279 although this is not apparent until you try to use pthreads. */
5280 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5282 *lenptr
= sizeof (big_breakpoint
);
5284 if (strcmp (target_shortname
, "mips") == 0)
5285 return idt_big_breakpoint
;
5286 else if (strcmp (target_shortname
, "ddb") == 0
5287 || strcmp (target_shortname
, "pmon") == 0
5288 || strcmp (target_shortname
, "lsi") == 0)
5289 return pmon_big_breakpoint
;
5290 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5291 return irix_big_breakpoint
;
5293 return big_breakpoint
;
5298 if (mips_pc_is_mips16 (*pcptr
))
5300 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5301 *pcptr
= unmake_mips16_addr (*pcptr
);
5302 *lenptr
= sizeof (mips16_little_breakpoint
);
5303 return mips16_little_breakpoint
;
5307 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5308 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5309 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5311 *lenptr
= sizeof (little_breakpoint
);
5313 if (strcmp (target_shortname
, "mips") == 0)
5314 return idt_little_breakpoint
;
5315 else if (strcmp (target_shortname
, "ddb") == 0
5316 || strcmp (target_shortname
, "pmon") == 0
5317 || strcmp (target_shortname
, "lsi") == 0)
5318 return pmon_little_breakpoint
;
5320 return little_breakpoint
;
5325 /* Return non-zero if the ADDR instruction has a branch delay slot
5326 (i.e. it is a jump or branch instruction). This function is based
5327 on mips32_next_pc. */
5330 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
5332 gdb_byte buf
[MIPS_INSN32_SIZE
];
5337 status
= target_read_memory (addr
, buf
, MIPS_INSN32_SIZE
);
5341 inst
= mips_fetch_instruction (gdbarch
, addr
);
5342 op
= itype_op (inst
);
5343 if ((inst
& 0xe0000000) != 0)
5344 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
5345 || op
== 29 /* JALX: bits 011101 */
5346 || (op
== 17 && itype_rs (inst
) == 8));
5347 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
5349 switch (op
& 0x07) /* extract bits 28,27,26 */
5351 case 0: /* SPECIAL */
5352 op
= rtype_funct (inst
);
5353 return (op
== 8 /* JR */
5354 || op
== 9); /* JALR */
5355 break; /* end SPECIAL */
5356 case 1: /* REGIMM */
5357 op
= itype_rt (inst
); /* branch condition */
5358 return (op
& 0xc) == 0;
5359 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
5360 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
5361 break; /* end REGIMM */
5362 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
5368 /* Return non-zero if the ADDR instruction, which must be a 32-bit
5369 instruction if MUSTBE32 is set or can be any instruction otherwise,
5370 has a branch delay slot (i.e. it is a non-compact jump instruction). */
5373 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
5376 gdb_byte buf
[MIPS_INSN16_SIZE
];
5377 unsigned short inst
;
5380 status
= target_read_memory (addr
, buf
, MIPS_INSN16_SIZE
);
5384 inst
= mips_fetch_instruction (gdbarch
, addr
);
5386 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
5387 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
5390 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
5391 This assumes KSSEG exists. */
5394 mips_segment_boundary (CORE_ADDR bpaddr
)
5396 CORE_ADDR mask
= CORE_ADDR_MAX
;
5399 if (sizeof (CORE_ADDR
) == 8)
5400 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
5401 a compiler warning produced where CORE_ADDR is a 32-bit type even
5402 though in that case this is dead code). */
5403 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
5406 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
5407 segsize
= 29; /* 32-bit compatibility segment */
5409 segsize
= 62; /* xkseg */
5411 case 2: /* xkphys */
5414 default: /* xksseg (1), xkuseg/kuseg (0) */
5418 else if (bpaddr
& 0x80000000) /* kernel segment */
5421 segsize
= 31; /* user segment */
5423 return bpaddr
& mask
;
5426 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
5427 it backwards if necessary. Return the address of the new location. */
5430 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5432 CORE_ADDR prev_addr
, next_addr
;
5434 CORE_ADDR func_addr
;
5436 /* If a breakpoint is set on the instruction in a branch delay slot,
5437 GDB gets confused. When the breakpoint is hit, the PC isn't on
5438 the instruction in the branch delay slot, the PC will point to
5439 the branch instruction. Since the PC doesn't match any known
5440 breakpoints, GDB reports a trap exception.
5442 There are two possible fixes for this problem.
5444 1) When the breakpoint gets hit, see if the BD bit is set in the
5445 Cause register (which indicates the last exception occurred in a
5446 branch delay slot). If the BD bit is set, fix the PC to point to
5447 the instruction in the branch delay slot.
5449 2) When the user sets the breakpoint, don't allow him to set the
5450 breakpoint on the instruction in the branch delay slot. Instead
5451 move the breakpoint to the branch instruction (which will have
5454 The problem with the first solution is that if the user then
5455 single-steps the processor, the branch instruction will get
5456 skipped (since GDB thinks the PC is on the instruction in the
5459 So, we'll use the second solution. To do this we need to know if
5460 the instruction we're trying to set the breakpoint on is in the
5461 branch delay slot. */
5463 boundary
= mips_segment_boundary (bpaddr
);
5465 /* Make sure we don't scan back before the beginning of the current
5466 function, since we may fetch constant data or insns that look like
5467 a jump. Of course we might do that anyway if the compiler has
5468 moved constants inline. :-( */
5469 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
5470 && func_addr
> boundary
&& func_addr
<= bpaddr
)
5471 boundary
= func_addr
;
5473 if (!mips_pc_is_mips16 (bpaddr
))
5475 if (bpaddr
== boundary
)
5478 /* If the previous instruction has a branch delay slot, we have
5479 to move the breakpoint to the branch instruction. */
5480 prev_addr
= bpaddr
- 4;
5481 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
5486 struct minimal_symbol
*sym
;
5487 CORE_ADDR addr
, jmpaddr
;
5490 boundary
= unmake_mips16_addr (boundary
);
5492 /* The only MIPS16 instructions with delay slots are JAL, JALX,
5493 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
5494 so try for that first, then try the 2 byte JALR/JR.
5495 FIXME: We have to assume that bpaddr is not the second half
5496 of an extended instruction. */
5500 for (i
= 1; i
< 4; i
++)
5502 if (unmake_mips16_addr (addr
) == boundary
)
5505 if (i
== 1 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 0))
5506 /* Looks like a JR/JALR at [target-1], but it could be
5507 the second word of a previous JAL/JALX, so record it
5508 and check back one more. */
5511 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 1))
5514 /* Looks like a JAL/JALX at [target-2], but it could also
5515 be the second word of a previous JAL/JALX, record it,
5516 and check back one more. */
5519 /* Looks like a JAL/JALX at [target-3], so any previously
5520 recorded JAL/JALX or JR/JALR must be wrong, because:
5523 -2: JAL-ext (can't be JAL/JALX)
5524 -1: bdslot (can't be JR/JALR)
5527 Of course it could be another JAL-ext which looks
5528 like a JAL, but in that case we'd have broken out
5529 of this loop at [target-2]:
5533 -2: bdslot (can't be jmp)
5540 /* Not a jump instruction: if we're at [target-1] this
5541 could be the second word of a JAL/JALX, so continue;
5542 otherwise we're done. */
5555 /* If PC is in a mips16 call or return stub, return the address of the target
5556 PC, which is either the callee or the caller. There are several
5557 cases which must be handled:
5559 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5560 target PC is in $31 ($ra).
5561 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5562 and the target PC is in $2.
5563 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5564 before the jal instruction, this is effectively a call stub
5565 and the target PC is in $2. Otherwise this is effectively
5566 a return stub and the target PC is in $18.
5568 See the source code for the stubs in gcc/config/mips/mips16.S for
5572 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5574 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5576 CORE_ADDR start_addr
;
5578 /* Find the starting address and name of the function containing the PC. */
5579 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5582 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5583 target PC is in $31 ($ra). */
5584 if (strcmp (name
, "__mips16_ret_sf") == 0
5585 || strcmp (name
, "__mips16_ret_df") == 0)
5586 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5588 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5590 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5591 and the target PC is in $2. */
5592 if (name
[19] >= '0' && name
[19] <= '9')
5593 return get_frame_register_signed (frame
, 2);
5595 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5596 before the jal instruction, this is effectively a call stub
5597 and the target PC is in $2. Otherwise this is effectively
5598 a return stub and the target PC is in $18. */
5599 else if (name
[19] == 's' || name
[19] == 'd')
5601 if (pc
== start_addr
)
5603 /* Check if the target of the stub is a compiler-generated
5604 stub. Such a stub for a function bar might have a name
5605 like __fn_stub_bar, and might look like this:
5610 la $1,bar (becomes a lui/addiu pair)
5612 So scan down to the lui/addi and extract the target
5613 address from those two instructions. */
5615 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5618 /* See if the name of the target function is __fn_stub_*. */
5619 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5622 if (strncmp (name
, "__fn_stub_", 10) != 0
5623 && strcmp (name
, "etext") != 0
5624 && strcmp (name
, "_etext") != 0)
5627 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5628 The limit on the search is arbitrarily set to 20
5629 instructions. FIXME. */
5630 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5632 ULONGEST inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5633 CORE_ADDR addr
= inst
;
5635 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5636 pc
= (((addr
& 0xffff) ^ 0x8000) - 0x8000) << 16;
5638 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5639 return pc
+ ((addr
& 0xffff) ^ 0x8000) - 0x8000;
5643 /* Couldn't find the lui/addui pair, so return stub address. */
5647 /* This is the 'return' part of a call stub. The return
5648 address is in $r18. */
5649 return get_frame_register_signed (frame
, 18);
5652 return 0; /* not a stub */
5655 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5656 PC of the stub target. The stub just loads $t9 and jumps to it,
5657 so that $t9 has the correct value at function entry. */
5660 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5662 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5663 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5664 struct minimal_symbol
*msym
;
5666 gdb_byte stub_code
[16];
5667 int32_t stub_words
[4];
5669 /* The stub for foo is named ".pic.foo", and is either two
5670 instructions inserted before foo or a three instruction sequence
5671 which jumps to foo. */
5672 msym
= lookup_minimal_symbol_by_pc (pc
);
5674 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5675 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5676 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5679 /* A two-instruction header. */
5680 if (MSYMBOL_SIZE (msym
) == 8)
5683 /* A three-instruction (plus delay slot) trampoline. */
5684 if (MSYMBOL_SIZE (msym
) == 16)
5686 if (target_read_memory (pc
, stub_code
, 16) != 0)
5688 for (i
= 0; i
< 4; i
++)
5689 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5692 /* A stub contains these instructions:
5695 addiu t9, t9, %lo(target)
5698 This works even for N64, since stubs are only generated with
5700 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5701 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5702 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5703 && stub_words
[3] == 0x00000000)
5704 return (((stub_words
[0] & 0x0000ffff) << 16)
5705 + (stub_words
[2] & 0x0000ffff));
5708 /* Not a recognized stub. */
5713 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5715 CORE_ADDR target_pc
;
5717 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5721 target_pc
= find_solib_trampoline_target (frame
, pc
);
5725 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5732 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5733 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5736 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5739 if (num
>= 0 && num
< 32)
5741 else if (num
>= 38 && num
< 70)
5742 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5744 regnum
= mips_regnum (gdbarch
)->hi
;
5746 regnum
= mips_regnum (gdbarch
)->lo
;
5747 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
5748 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
5750 /* This will hopefully (eventually) provoke a warning. Should
5751 we be calling complaint() here? */
5752 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5753 return gdbarch_num_regs (gdbarch
) + regnum
;
5757 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5758 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5761 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5764 if (num
>= 0 && num
< 32)
5766 else if (num
>= 32 && num
< 64)
5767 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5769 regnum
= mips_regnum (gdbarch
)->hi
;
5771 regnum
= mips_regnum (gdbarch
)->lo
;
5772 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
5773 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
5775 /* This will hopefully (eventually) provoke a warning. Should we
5776 be calling complaint() here? */
5777 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5778 return gdbarch_num_regs (gdbarch
) + regnum
;
5782 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5784 /* Only makes sense to supply raw registers. */
5785 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5786 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5787 decide if it is valid. Should instead define a standard sim/gdb
5788 register numbering scheme. */
5789 if (gdbarch_register_name (gdbarch
,
5790 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5791 && gdbarch_register_name (gdbarch
,
5792 gdbarch_num_regs (gdbarch
)
5793 + regnum
)[0] != '\0')
5796 return LEGACY_SIM_REGNO_IGNORE
;
5800 /* Convert an integer into an address. Extracting the value signed
5801 guarantees a correctly sign extended address. */
5804 mips_integer_to_address (struct gdbarch
*gdbarch
,
5805 struct type
*type
, const gdb_byte
*buf
)
5807 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5808 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5811 /* Dummy virtual frame pointer method. This is no more or less accurate
5812 than most other architectures; we just need to be explicit about it,
5813 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5814 an assertion failure. */
5817 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5818 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5820 *reg
= MIPS_SP_REGNUM
;
5825 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5827 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5828 const char *name
= bfd_get_section_name (abfd
, sect
);
5830 if (*abip
!= MIPS_ABI_UNKNOWN
)
5833 if (strncmp (name
, ".mdebug.", 8) != 0)
5836 if (strcmp (name
, ".mdebug.abi32") == 0)
5837 *abip
= MIPS_ABI_O32
;
5838 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5839 *abip
= MIPS_ABI_N32
;
5840 else if (strcmp (name
, ".mdebug.abi64") == 0)
5841 *abip
= MIPS_ABI_N64
;
5842 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5843 *abip
= MIPS_ABI_O64
;
5844 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5845 *abip
= MIPS_ABI_EABI32
;
5846 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5847 *abip
= MIPS_ABI_EABI64
;
5849 warning (_("unsupported ABI %s."), name
+ 8);
5853 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5855 int *lbp
= (int *) obj
;
5856 const char *name
= bfd_get_section_name (abfd
, sect
);
5858 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5860 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5862 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5863 warning (_("unrecognized .gcc_compiled_longXX"));
5866 static enum mips_abi
5867 global_mips_abi (void)
5871 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5872 if (mips_abi_strings
[i
] == mips_abi_string
)
5873 return (enum mips_abi
) i
;
5875 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5879 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5881 /* If the size matches the set of 32-bit or 64-bit integer registers,
5882 assume that's what we've got. */
5883 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5884 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5886 /* If the size matches the full set of registers GDB traditionally
5887 knows about, including floating point, for either 32-bit or
5888 64-bit, assume that's what we've got. */
5889 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5890 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5892 /* Otherwise we don't have a useful guess. */
5895 static struct value
*
5896 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5898 const int *reg_p
= baton
;
5899 return value_of_register (*reg_p
, frame
);
5902 static struct gdbarch
*
5903 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5905 struct gdbarch
*gdbarch
;
5906 struct gdbarch_tdep
*tdep
;
5908 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5910 enum mips_fpu_type fpu_type
;
5911 struct tdesc_arch_data
*tdesc_data
= NULL
;
5912 int elf_fpu_type
= 0;
5913 const char **reg_names
;
5914 struct mips_regnum mips_regnum
, *regnum
;
5918 /* Fill in the OS dependent register numbers and names. */
5919 if (info
.osabi
== GDB_OSABI_IRIX
)
5921 mips_regnum
.fp0
= 32;
5922 mips_regnum
.pc
= 64;
5923 mips_regnum
.cause
= 65;
5924 mips_regnum
.badvaddr
= 66;
5925 mips_regnum
.hi
= 67;
5926 mips_regnum
.lo
= 68;
5927 mips_regnum
.fp_control_status
= 69;
5928 mips_regnum
.fp_implementation_revision
= 70;
5929 mips_regnum
.dspacc
= dspacc
= -1;
5930 mips_regnum
.dspctl
= dspctl
= -1;
5932 reg_names
= mips_irix_reg_names
;
5934 else if (info
.osabi
== GDB_OSABI_LINUX
)
5936 mips_regnum
.fp0
= 38;
5937 mips_regnum
.pc
= 37;
5938 mips_regnum
.cause
= 36;
5939 mips_regnum
.badvaddr
= 35;
5940 mips_regnum
.hi
= 34;
5941 mips_regnum
.lo
= 33;
5942 mips_regnum
.fp_control_status
= 70;
5943 mips_regnum
.fp_implementation_revision
= 71;
5944 mips_regnum
.dspacc
= -1;
5945 mips_regnum
.dspctl
= -1;
5949 reg_names
= mips_linux_reg_names
;
5953 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
5954 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
5955 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5956 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
5957 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
5958 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
5959 mips_regnum
.fp_control_status
= 70;
5960 mips_regnum
.fp_implementation_revision
= 71;
5961 mips_regnum
.dspacc
= dspacc
= -1;
5962 mips_regnum
.dspctl
= dspctl
= -1;
5963 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5964 if (info
.bfd_arch_info
!= NULL
5965 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5966 reg_names
= mips_tx39_reg_names
;
5968 reg_names
= mips_generic_reg_names
;
5971 /* Check any target description for validity. */
5972 if (tdesc_has_registers (info
.target_desc
))
5974 static const char *const mips_gprs
[] = {
5975 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5976 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5977 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5978 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5980 static const char *const mips_fprs
[] = {
5981 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5982 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5983 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5984 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5987 const struct tdesc_feature
*feature
;
5990 feature
= tdesc_find_feature (info
.target_desc
,
5991 "org.gnu.gdb.mips.cpu");
5992 if (feature
== NULL
)
5995 tdesc_data
= tdesc_data_alloc ();
5998 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5999 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6003 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6004 mips_regnum
.lo
, "lo");
6005 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6006 mips_regnum
.hi
, "hi");
6007 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6008 mips_regnum
.pc
, "pc");
6012 tdesc_data_cleanup (tdesc_data
);
6016 feature
= tdesc_find_feature (info
.target_desc
,
6017 "org.gnu.gdb.mips.cp0");
6018 if (feature
== NULL
)
6020 tdesc_data_cleanup (tdesc_data
);
6025 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6026 mips_regnum
.badvaddr
, "badvaddr");
6027 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6028 MIPS_PS_REGNUM
, "status");
6029 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6030 mips_regnum
.cause
, "cause");
6034 tdesc_data_cleanup (tdesc_data
);
6038 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
6039 backend is not prepared for that, though. */
6040 feature
= tdesc_find_feature (info
.target_desc
,
6041 "org.gnu.gdb.mips.fpu");
6042 if (feature
== NULL
)
6044 tdesc_data_cleanup (tdesc_data
);
6049 for (i
= 0; i
< 32; i
++)
6050 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6051 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
6053 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6054 mips_regnum
.fp_control_status
,
6057 &= tdesc_numbered_register (feature
, tdesc_data
,
6058 mips_regnum
.fp_implementation_revision
,
6063 tdesc_data_cleanup (tdesc_data
);
6069 feature
= tdesc_find_feature (info
.target_desc
,
6070 "org.gnu.gdb.mips.dsp");
6071 /* The DSP registers are optional; it's OK if they are absent. */
6072 if (feature
!= NULL
)
6076 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6077 dspacc
+ i
++, "hi1");
6078 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6079 dspacc
+ i
++, "lo1");
6080 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6081 dspacc
+ i
++, "hi2");
6082 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6083 dspacc
+ i
++, "lo2");
6084 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6085 dspacc
+ i
++, "hi3");
6086 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6087 dspacc
+ i
++, "lo3");
6089 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6094 tdesc_data_cleanup (tdesc_data
);
6098 mips_regnum
.dspacc
= dspacc
;
6099 mips_regnum
.dspctl
= dspctl
;
6103 /* It would be nice to detect an attempt to use a 64-bit ABI
6104 when only 32-bit registers are provided. */
6108 /* First of all, extract the elf_flags, if available. */
6109 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6110 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6111 else if (arches
!= NULL
)
6112 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6116 fprintf_unfiltered (gdb_stdlog
,
6117 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6119 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6120 switch ((elf_flags
& EF_MIPS_ABI
))
6122 case E_MIPS_ABI_O32
:
6123 found_abi
= MIPS_ABI_O32
;
6125 case E_MIPS_ABI_O64
:
6126 found_abi
= MIPS_ABI_O64
;
6128 case E_MIPS_ABI_EABI32
:
6129 found_abi
= MIPS_ABI_EABI32
;
6131 case E_MIPS_ABI_EABI64
:
6132 found_abi
= MIPS_ABI_EABI64
;
6135 if ((elf_flags
& EF_MIPS_ABI2
))
6136 found_abi
= MIPS_ABI_N32
;
6138 found_abi
= MIPS_ABI_UNKNOWN
;
6142 /* GCC creates a pseudo-section whose name describes the ABI. */
6143 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6144 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6146 /* If we have no useful BFD information, use the ABI from the last
6147 MIPS architecture (if there is one). */
6148 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6149 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6151 /* Try the architecture for any hint of the correct ABI. */
6152 if (found_abi
== MIPS_ABI_UNKNOWN
6153 && info
.bfd_arch_info
!= NULL
6154 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6156 switch (info
.bfd_arch_info
->mach
)
6158 case bfd_mach_mips3900
:
6159 found_abi
= MIPS_ABI_EABI32
;
6161 case bfd_mach_mips4100
:
6162 case bfd_mach_mips5000
:
6163 found_abi
= MIPS_ABI_EABI64
;
6165 case bfd_mach_mips8000
:
6166 case bfd_mach_mips10000
:
6167 /* On Irix, ELF64 executables use the N64 ABI. The
6168 pseudo-sections which describe the ABI aren't present
6169 on IRIX. (Even for executables created by gcc.) */
6170 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6171 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6172 found_abi
= MIPS_ABI_N64
;
6174 found_abi
= MIPS_ABI_N32
;
6179 /* Default 64-bit objects to N64 instead of O32. */
6180 if (found_abi
== MIPS_ABI_UNKNOWN
6181 && info
.abfd
!= NULL
6182 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6183 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6184 found_abi
= MIPS_ABI_N64
;
6187 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6190 /* What has the user specified from the command line? */
6191 wanted_abi
= global_mips_abi ();
6193 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6196 /* Now that we have found what the ABI for this binary would be,
6197 check whether the user is overriding it. */
6198 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6199 mips_abi
= wanted_abi
;
6200 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6201 mips_abi
= found_abi
;
6203 mips_abi
= MIPS_ABI_O32
;
6205 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6208 /* Also used when doing an architecture lookup. */
6210 fprintf_unfiltered (gdb_stdlog
,
6211 "mips_gdbarch_init: "
6212 "mips64_transfers_32bit_regs_p = %d\n",
6213 mips64_transfers_32bit_regs_p
);
6215 /* Determine the MIPS FPU type. */
6218 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6219 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6220 Tag_GNU_MIPS_ABI_FP
);
6221 #endif /* HAVE_ELF */
6223 if (!mips_fpu_type_auto
)
6224 fpu_type
= mips_fpu_type
;
6225 else if (elf_fpu_type
!= 0)
6227 switch (elf_fpu_type
)
6230 fpu_type
= MIPS_FPU_DOUBLE
;
6233 fpu_type
= MIPS_FPU_SINGLE
;
6237 /* Soft float or unknown. */
6238 fpu_type
= MIPS_FPU_NONE
;
6242 else if (info
.bfd_arch_info
!= NULL
6243 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6244 switch (info
.bfd_arch_info
->mach
)
6246 case bfd_mach_mips3900
:
6247 case bfd_mach_mips4100
:
6248 case bfd_mach_mips4111
:
6249 case bfd_mach_mips4120
:
6250 fpu_type
= MIPS_FPU_NONE
;
6252 case bfd_mach_mips4650
:
6253 fpu_type
= MIPS_FPU_SINGLE
;
6256 fpu_type
= MIPS_FPU_DOUBLE
;
6259 else if (arches
!= NULL
)
6260 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6262 fpu_type
= MIPS_FPU_DOUBLE
;
6264 fprintf_unfiltered (gdb_stdlog
,
6265 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6267 /* Check for blatant incompatibilities. */
6269 /* If we have only 32-bit registers, then we can't debug a 64-bit
6271 if (info
.target_desc
6272 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
6273 && mips_abi
!= MIPS_ABI_EABI32
6274 && mips_abi
!= MIPS_ABI_O32
)
6276 if (tdesc_data
!= NULL
)
6277 tdesc_data_cleanup (tdesc_data
);
6281 /* Try to find a pre-existing architecture. */
6282 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6284 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6286 /* MIPS needs to be pedantic about which ABI the object is
6288 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6290 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6292 /* Need to be pedantic about which register virtual size is
6294 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6295 != mips64_transfers_32bit_regs_p
)
6297 /* Be pedantic about which FPU is selected. */
6298 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6301 if (tdesc_data
!= NULL
)
6302 tdesc_data_cleanup (tdesc_data
);
6303 return arches
->gdbarch
;
6306 /* Need a new architecture. Fill in a target specific vector. */
6307 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6308 gdbarch
= gdbarch_alloc (&info
, tdep
);
6309 tdep
->elf_flags
= elf_flags
;
6310 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6311 tdep
->found_abi
= found_abi
;
6312 tdep
->mips_abi
= mips_abi
;
6313 tdep
->mips_fpu_type
= fpu_type
;
6314 tdep
->register_size_valid_p
= 0;
6315 tdep
->register_size
= 0;
6316 tdep
->gregset
= NULL
;
6317 tdep
->gregset64
= NULL
;
6318 tdep
->fpregset
= NULL
;
6319 tdep
->fpregset64
= NULL
;
6321 if (info
.target_desc
)
6323 /* Some useful properties can be inferred from the target. */
6324 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
6326 tdep
->register_size_valid_p
= 1;
6327 tdep
->register_size
= 4;
6329 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
6331 tdep
->register_size_valid_p
= 1;
6332 tdep
->register_size
= 8;
6336 /* Initially set everything according to the default ABI/ISA. */
6337 set_gdbarch_short_bit (gdbarch
, 16);
6338 set_gdbarch_int_bit (gdbarch
, 32);
6339 set_gdbarch_float_bit (gdbarch
, 32);
6340 set_gdbarch_double_bit (gdbarch
, 64);
6341 set_gdbarch_long_double_bit (gdbarch
, 64);
6342 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6343 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6344 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6346 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6347 mips_ax_pseudo_register_collect
);
6348 set_gdbarch_ax_pseudo_register_push_stack
6349 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6351 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6352 mips_elf_make_msymbol_special
);
6354 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
6355 *regnum
= mips_regnum
;
6356 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
6357 replaced by gdbarch_read_pc? */
6358 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6359 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6360 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6361 set_gdbarch_num_regs (gdbarch
, num_regs
);
6362 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6363 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6364 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6365 tdep
->mips_processor_reg_names
= reg_names
;
6366 tdep
->regnum
= regnum
;
6371 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6372 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6373 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6374 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6375 tdep
->default_mask_address_p
= 0;
6376 set_gdbarch_long_bit (gdbarch
, 32);
6377 set_gdbarch_ptr_bit (gdbarch
, 32);
6378 set_gdbarch_long_long_bit (gdbarch
, 64);
6381 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6382 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6383 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6384 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6385 tdep
->default_mask_address_p
= 0;
6386 set_gdbarch_long_bit (gdbarch
, 32);
6387 set_gdbarch_ptr_bit (gdbarch
, 32);
6388 set_gdbarch_long_long_bit (gdbarch
, 64);
6390 case MIPS_ABI_EABI32
:
6391 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6392 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6393 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6394 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6395 tdep
->default_mask_address_p
= 0;
6396 set_gdbarch_long_bit (gdbarch
, 32);
6397 set_gdbarch_ptr_bit (gdbarch
, 32);
6398 set_gdbarch_long_long_bit (gdbarch
, 64);
6400 case MIPS_ABI_EABI64
:
6401 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6402 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6403 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6404 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6405 tdep
->default_mask_address_p
= 0;
6406 set_gdbarch_long_bit (gdbarch
, 64);
6407 set_gdbarch_ptr_bit (gdbarch
, 64);
6408 set_gdbarch_long_long_bit (gdbarch
, 64);
6411 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6412 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6413 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6414 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6415 tdep
->default_mask_address_p
= 0;
6416 set_gdbarch_long_bit (gdbarch
, 32);
6417 set_gdbarch_ptr_bit (gdbarch
, 32);
6418 set_gdbarch_long_long_bit (gdbarch
, 64);
6419 set_gdbarch_long_double_bit (gdbarch
, 128);
6420 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6423 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6424 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6425 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6426 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6427 tdep
->default_mask_address_p
= 0;
6428 set_gdbarch_long_bit (gdbarch
, 64);
6429 set_gdbarch_ptr_bit (gdbarch
, 64);
6430 set_gdbarch_long_long_bit (gdbarch
, 64);
6431 set_gdbarch_long_double_bit (gdbarch
, 128);
6432 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6435 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6438 /* GCC creates a pseudo-section whose name specifies the size of
6439 longs, since -mlong32 or -mlong64 may be used independent of
6440 other options. How those options affect pointer sizes is ABI and
6441 architecture dependent, so use them to override the default sizes
6442 set by the ABI. This table shows the relationship between ABI,
6443 -mlongXX, and size of pointers:
6445 ABI -mlongXX ptr bits
6446 --- -------- --------
6460 Note that for o32 and eabi32, pointers are always 32 bits
6461 regardless of any -mlongXX option. For all others, pointers and
6462 longs are the same, as set by -mlongXX or set by defaults. */
6464 if (info
.abfd
!= NULL
)
6468 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6471 set_gdbarch_long_bit (gdbarch
, long_bit
);
6475 case MIPS_ABI_EABI32
:
6480 case MIPS_ABI_EABI64
:
6481 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6484 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6489 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6490 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6493 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6494 flag in object files because to do so would make it impossible to
6495 link with libraries compiled without "-gp32". This is
6496 unnecessarily restrictive.
6498 We could solve this problem by adding "-gp32" multilibs to gcc,
6499 but to set this flag before gcc is built with such multilibs will
6500 break too many systems.''
6502 But even more unhelpfully, the default linker output target for
6503 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6504 for 64-bit programs - you need to change the ABI to change this,
6505 and not all gcc targets support that currently. Therefore using
6506 this flag to detect 32-bit mode would do the wrong thing given
6507 the current gcc - it would make GDB treat these 64-bit programs
6508 as 32-bit programs by default. */
6510 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6511 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6513 /* Add/remove bits from an address. The MIPS needs be careful to
6514 ensure that all 32 bit addresses are sign extended to 64 bits. */
6515 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6517 /* Unwind the frame. */
6518 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6519 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6520 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6522 /* Map debug register numbers onto internal register numbers. */
6523 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6524 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6525 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6526 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6527 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6528 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6530 /* MIPS version of CALL_DUMMY. */
6532 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6533 replaced by a command, and all targets will default to on stack
6534 (regardless of the stack's execute status). */
6535 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6536 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6538 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6539 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6540 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6542 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6543 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6544 set_gdbarch_adjust_breakpoint_address (gdbarch
,
6545 mips_adjust_breakpoint_address
);
6547 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6549 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6551 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6552 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6553 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6555 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6557 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6559 if (mips_abi
== MIPS_ABI_N32
)
6560 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6561 else if (mips_abi
== MIPS_ABI_N64
)
6562 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6564 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6566 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6567 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6568 need to all be folded into the target vector. Since they are
6569 being used as guards for target_stopped_by_watchpoint, why not have
6570 target_stopped_by_watchpoint return the type of watchpoint that the code
6572 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6574 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6576 set_gdbarch_single_step_through_delay (gdbarch
,
6577 mips_single_step_through_delay
);
6579 /* Virtual tables. */
6580 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6582 mips_register_g_packet_guesses (gdbarch
);
6584 /* Hook in OS ABI-specific overrides, if they have been registered. */
6585 info
.tdep_info
= (void *) tdesc_data
;
6586 gdbarch_init_osabi (info
, gdbarch
);
6588 /* Unwind the frame. */
6589 dwarf2_append_unwinders (gdbarch
);
6590 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6591 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6592 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6593 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6594 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6595 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6596 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6600 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6601 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6603 /* Override the normal target description methods to handle our
6604 dual real and pseudo registers. */
6605 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6606 set_gdbarch_register_reggroup_p (gdbarch
,
6607 mips_tdesc_register_reggroup_p
);
6609 num_regs
= gdbarch_num_regs (gdbarch
);
6610 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6611 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6612 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6615 /* Add ABI-specific aliases for the registers. */
6616 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6617 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6618 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6619 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6621 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6622 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6623 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6625 /* Add some other standard aliases. */
6626 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6627 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6628 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6630 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6631 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6632 value_of_mips_user_reg
,
6633 &mips_numeric_register_aliases
[i
].regnum
);
6639 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6641 struct gdbarch_info info
;
6643 /* Force the architecture to update, and (if it's a MIPS architecture)
6644 mips_gdbarch_init will take care of the rest. */
6645 gdbarch_info_init (&info
);
6646 gdbarch_update_p (info
);
6649 /* Print out which MIPS ABI is in use. */
6652 show_mips_abi (struct ui_file
*file
,
6654 struct cmd_list_element
*ignored_cmd
,
6655 const char *ignored_value
)
6657 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6660 "The MIPS ABI is unknown because the current architecture "
6664 enum mips_abi global_abi
= global_mips_abi ();
6665 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6666 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6668 if (global_abi
== MIPS_ABI_UNKNOWN
)
6671 "The MIPS ABI is set automatically (currently \"%s\").\n",
6673 else if (global_abi
== actual_abi
)
6676 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6680 /* Probably shouldn't happen... */
6681 fprintf_filtered (file
,
6682 "The (auto detected) MIPS ABI \"%s\" is in use "
6683 "even though the user setting was \"%s\".\n",
6684 actual_abi_str
, mips_abi_strings
[global_abi
]);
6690 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6692 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6696 int ef_mips_32bitmode
;
6697 /* Determine the ISA. */
6698 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6716 /* Determine the size of a pointer. */
6717 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6718 fprintf_unfiltered (file
,
6719 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6721 fprintf_unfiltered (file
,
6722 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6724 fprintf_unfiltered (file
,
6725 "mips_dump_tdep: ef_mips_arch = %d\n",
6727 fprintf_unfiltered (file
,
6728 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6729 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6730 fprintf_unfiltered (file
,
6732 "mips_mask_address_p() %d (default %d)\n",
6733 mips_mask_address_p (tdep
),
6734 tdep
->default_mask_address_p
);
6736 fprintf_unfiltered (file
,
6737 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6738 MIPS_DEFAULT_FPU_TYPE
,
6739 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6740 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6741 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6743 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6744 MIPS_EABI (gdbarch
));
6745 fprintf_unfiltered (file
,
6746 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6747 MIPS_FPU_TYPE (gdbarch
),
6748 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6749 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6750 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6754 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6757 _initialize_mips_tdep (void)
6759 static struct cmd_list_element
*mipsfpulist
= NULL
;
6760 struct cmd_list_element
*c
;
6762 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6763 if (MIPS_ABI_LAST
+ 1
6764 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6765 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6767 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6769 mips_pdr_data
= register_objfile_data ();
6771 /* Create feature sets with the appropriate properties. The values
6772 are not important. */
6773 mips_tdesc_gp32
= allocate_target_description ();
6774 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6776 mips_tdesc_gp64
= allocate_target_description ();
6777 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6779 /* Add root prefix command for all "set mips"/"show mips" commands. */
6780 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6781 _("Various MIPS specific commands."),
6782 &setmipscmdlist
, "set mips ", 0, &setlist
);
6784 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6785 _("Various MIPS specific commands."),
6786 &showmipscmdlist
, "show mips ", 0, &showlist
);
6788 /* Allow the user to override the ABI. */
6789 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6790 &mips_abi_string
, _("\
6791 Set the MIPS ABI used by this program."), _("\
6792 Show the MIPS ABI used by this program."), _("\
6793 This option can be set to one of:\n\
6794 auto - the default ABI associated with the current binary\n\
6803 &setmipscmdlist
, &showmipscmdlist
);
6805 /* Let the user turn off floating point and set the fence post for
6806 heuristic_proc_start. */
6808 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6809 _("Set use of MIPS floating-point coprocessor."),
6810 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6811 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6812 _("Select single-precision MIPS floating-point coprocessor."),
6814 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6815 _("Select double-precision MIPS floating-point coprocessor."),
6817 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6818 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6819 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6820 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6821 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6822 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6823 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6824 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6825 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6826 _("Select MIPS floating-point coprocessor automatically."),
6828 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6829 _("Show current use of MIPS floating-point coprocessor target."),
6832 /* We really would like to have both "0" and "unlimited" work, but
6833 command.c doesn't deal with that. So make it a var_zinteger
6834 because the user can always use "999999" or some such for unlimited. */
6835 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6836 &heuristic_fence_post
, _("\
6837 Set the distance searched for the start of a function."), _("\
6838 Show the distance searched for the start of a function."), _("\
6839 If you are debugging a stripped executable, GDB needs to search through the\n\
6840 program for the start of a function. This command sets the distance of the\n\
6841 search. The only need to set it is when debugging a stripped executable."),
6842 reinit_frame_cache_sfunc
,
6843 NULL
, /* FIXME: i18n: The distance searched for
6844 the start of a function is %s. */
6845 &setlist
, &showlist
);
6847 /* Allow the user to control whether the upper bits of 64-bit
6848 addresses should be zeroed. */
6849 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6850 &mask_address_var
, _("\
6851 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6852 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6853 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6854 allow GDB to determine the correct value."),
6855 NULL
, show_mask_address
,
6856 &setmipscmdlist
, &showmipscmdlist
);
6858 /* Allow the user to control the size of 32 bit registers within the
6859 raw remote packet. */
6860 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6861 &mips64_transfers_32bit_regs_p
, _("\
6862 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6864 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6866 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6867 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6868 64 bits for others. Use \"off\" to disable compatibility mode"),
6869 set_mips64_transfers_32bit_regs
,
6870 NULL
, /* FIXME: i18n: Compatibility with 64-bit
6871 MIPS target that transfers 32-bit
6872 quantities is %s. */
6873 &setlist
, &showlist
);
6875 /* Debug this files internals. */
6876 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6878 Set mips debugging."), _("\
6879 Show mips debugging."), _("\
6880 When non-zero, mips specific debugging is enabled."),
6882 NULL
, /* FIXME: i18n: Mips debugging is
6884 &setdebuglist
, &showdebuglist
);