1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static void set_reg_offset (CORE_ADDR
*saved_regs
, int regnum
, CORE_ADDR off
);
62 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
64 /* A useful bit in the CP0 status register (PS_REGNUM). */
65 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
66 #define ST0_FR (1 << 26)
68 /* The sizes of floating point registers. */
72 MIPS_FPU_SINGLE_REGSIZE
= 4,
73 MIPS_FPU_DOUBLE_REGSIZE
= 8
77 static const char *mips_abi_string
;
79 static const char *mips_abi_strings
[] = {
90 struct frame_extra_info
92 mips_extra_func_info_t proc_desc
;
96 /* Various MIPS ISA options (related to stack analysis) can be
97 overridden dynamically. Establish an enum/array for managing
100 static const char size_auto
[] = "auto";
101 static const char size_32
[] = "32";
102 static const char size_64
[] = "64";
104 static const char *size_enums
[] = {
111 /* Some MIPS boards don't support floating point while others only
112 support single-precision floating-point operations. */
116 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
117 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
118 MIPS_FPU_NONE
/* No floating point. */
121 #ifndef MIPS_DEFAULT_FPU_TYPE
122 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
124 static int mips_fpu_type_auto
= 1;
125 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
127 static int mips_debug
= 0;
129 /* MIPS specific per-architecture information */
132 /* from the elf header */
136 enum mips_abi mips_abi
;
137 enum mips_abi found_abi
;
138 enum mips_fpu_type mips_fpu_type
;
139 int mips_last_arg_regnum
;
140 int mips_last_fp_arg_regnum
;
141 int default_mask_address_p
;
142 /* Is the target using 64-bit raw integer registers but only
143 storing a left-aligned 32-bit value in each? */
144 int mips64_transfers_32bit_regs_p
;
145 /* Indexes for various registers. IRIX and embedded have
146 different values. This contains the "public" fields. Don't
147 add any that do not need to be public. */
148 const struct mips_regnum
*regnum
;
149 /* Register names table for the current register set. */
150 const char **mips_processor_reg_names
;
154 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
160 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
161 They are implemented as a pair of 64bit doubles where the high
162 part holds the result of the operation rounded to double, and
163 the low double holds the difference between the exact result and
164 the rounded result. So "high" + "low" contains the result with
165 added precision. Unfortunately, the floatformat structure used
166 by GDB is not powerful enough to describe this format. As a temporary
167 measure, we define a 128bit floatformat that only uses the high part.
168 We lose a bit of precision but that's probably the best we can do
169 for now with the current infrastructure. */
171 static const struct floatformat floatformat_n32n64_long_double_big
=
173 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
174 floatformat_intbit_no
,
175 "floatformat_ieee_double_big",
176 n32n64_floatformat_always_valid
179 const struct mips_regnum
*
180 mips_regnum (struct gdbarch
*gdbarch
)
182 return gdbarch_tdep (gdbarch
)->regnum
;
186 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
188 return mips_regnum (gdbarch
)->fp0
+ 12;
191 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
192 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
194 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
196 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
198 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
200 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
201 functions to test, set, or clear bit 0 of addresses. */
204 is_mips16_addr (CORE_ADDR addr
)
210 make_mips16_addr (CORE_ADDR addr
)
216 unmake_mips16_addr (CORE_ADDR addr
)
218 return ((addr
) & ~1);
221 /* Return the contents of register REGNUM as a signed integer. */
224 read_signed_register (int regnum
)
226 void *buf
= alloca (register_size (current_gdbarch
, regnum
));
227 deprecated_read_register_gen (regnum
, buf
);
228 return (extract_signed_integer
229 (buf
, register_size (current_gdbarch
, regnum
)));
233 read_signed_register_pid (int regnum
, ptid_t ptid
)
238 if (ptid_equal (ptid
, inferior_ptid
))
239 return read_signed_register (regnum
);
241 save_ptid
= inferior_ptid
;
243 inferior_ptid
= ptid
;
245 retval
= read_signed_register (regnum
);
247 inferior_ptid
= save_ptid
;
252 /* Return the MIPS ABI associated with GDBARCH. */
254 mips_abi (struct gdbarch
*gdbarch
)
256 return gdbarch_tdep (gdbarch
)->mips_abi
;
260 mips_isa_regsize (struct gdbarch
*gdbarch
)
262 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
263 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
266 /* Return the currently configured (or set) saved register size. */
268 static const char *mips_abi_regsize_string
= size_auto
;
271 mips_abi_regsize (struct gdbarch
*gdbarch
)
273 if (mips_abi_regsize_string
== size_auto
)
274 switch (mips_abi (gdbarch
))
276 case MIPS_ABI_EABI32
:
282 case MIPS_ABI_EABI64
:
284 case MIPS_ABI_UNKNOWN
:
287 internal_error (__FILE__
, __LINE__
, "bad switch");
289 else if (mips_abi_regsize_string
== size_64
)
291 else /* if (mips_abi_regsize_string == size_32) */
295 /* Functions for setting and testing a bit in a minimal symbol that
296 marks it as 16-bit function. The MSB of the minimal symbol's
297 "info" field is used for this purpose.
299 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
300 i.e. refers to a 16-bit function, and sets a "special" bit in a
301 minimal symbol to mark it as a 16-bit function
303 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
306 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
308 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
310 MSYMBOL_INFO (msym
) = (char *)
311 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
312 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
317 msymbol_is_special (struct minimal_symbol
*msym
)
319 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
322 /* XFER a value from the big/little/left end of the register.
323 Depending on the size of the value it might occupy the entire
324 register or just part of it. Make an allowance for this, aligning
325 things accordingly. */
328 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
329 enum bfd_endian endian
, bfd_byte
* in
,
330 const bfd_byte
* out
, int buf_offset
)
333 gdb_assert (reg_num
>= NUM_REGS
);
334 /* Need to transfer the left or right part of the register, based on
335 the targets byte order. */
339 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
341 case BFD_ENDIAN_LITTLE
:
344 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
348 internal_error (__FILE__
, __LINE__
, "bad switch");
351 fprintf_unfiltered (gdb_stderr
,
352 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
353 reg_num
, reg_offset
, buf_offset
, length
);
354 if (mips_debug
&& out
!= NULL
)
357 fprintf_unfiltered (gdb_stdlog
, "out ");
358 for (i
= 0; i
< length
; i
++)
359 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
362 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
365 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
367 if (mips_debug
&& in
!= NULL
)
370 fprintf_unfiltered (gdb_stdlog
, "in ");
371 for (i
= 0; i
< length
; i
++)
372 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
375 fprintf_unfiltered (gdb_stdlog
, "\n");
378 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
379 compatiblity mode. A return value of 1 means that we have
380 physical 64-bit registers, but should treat them as 32-bit registers. */
383 mips2_fp_compat (void)
385 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
387 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
392 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
393 in all the places we deal with FP registers. PR gdb/413. */
394 /* Otherwise check the FR bit in the status register - it controls
395 the FP compatiblity mode. If it is clear we are in compatibility
397 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
404 /* The amount of space reserved on the stack for registers. This is
405 different to MIPS_ABI_REGSIZE as it determines the alignment of
406 data allocated after the registers have run out. */
408 static const char *mips_stack_argsize_string
= size_auto
;
411 mips_stack_argsize (struct gdbarch
*gdbarch
)
413 if (mips_stack_argsize_string
== size_auto
)
414 return mips_abi_regsize (gdbarch
);
415 else if (mips_stack_argsize_string
== size_64
)
417 else /* if (mips_stack_argsize_string == size_32) */
421 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
423 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
424 struct frame_info
*);
425 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
428 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
430 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
432 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
434 static mips_extra_func_info_t
find_proc_desc (CORE_ADDR pc
,
435 struct frame_info
*next_frame
);
437 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
439 static struct type
*mips_float_register_type (void);
440 static struct type
*mips_double_register_type (void);
442 /* The list of available "set mips " and "show mips " commands */
444 static struct cmd_list_element
*setmipscmdlist
= NULL
;
445 static struct cmd_list_element
*showmipscmdlist
= NULL
;
447 /* Integer registers 0 thru 31 are handled explicitly by
448 mips_register_name(). Processor specific registers 32 and above
449 are listed in the followign tables. */
452 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
456 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
457 "sr", "lo", "hi", "bad", "cause", "pc",
458 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
459 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
460 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
461 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
462 "fsr", "fir", "" /*"fp" */ , "",
463 "", "", "", "", "", "", "", "",
464 "", "", "", "", "", "", "", "",
467 /* Names of IDT R3041 registers. */
469 static const char *mips_r3041_reg_names
[] = {
470 "sr", "lo", "hi", "bad", "cause", "pc",
471 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
472 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
473 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
474 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
475 "fsr", "fir", "", /*"fp" */ "",
476 "", "", "bus", "ccfg", "", "", "", "",
477 "", "", "port", "cmp", "", "", "epc", "prid",
480 /* Names of tx39 registers. */
482 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
483 "sr", "lo", "hi", "bad", "cause", "pc",
484 "", "", "", "", "", "", "", "",
485 "", "", "", "", "", "", "", "",
486 "", "", "", "", "", "", "", "",
487 "", "", "", "", "", "", "", "",
489 "", "", "", "", "", "", "", "",
490 "", "", "config", "cache", "debug", "depc", "epc", ""
493 /* Names of IRIX registers. */
494 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
495 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
496 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
497 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
498 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
499 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
503 /* Return the name of the register corresponding to REGNO. */
505 mips_register_name (int regno
)
507 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
508 /* GPR names for all ABIs other than n32/n64. */
509 static char *mips_gpr_names
[] = {
510 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
511 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
512 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
513 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
516 /* GPR names for n32 and n64 ABIs. */
517 static char *mips_n32_n64_gpr_names
[] = {
518 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
519 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
520 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
521 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
524 enum mips_abi abi
= mips_abi (current_gdbarch
);
526 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
527 don't make the raw register names visible. */
528 int rawnum
= regno
% NUM_REGS
;
529 if (regno
< NUM_REGS
)
532 /* The MIPS integer registers are always mapped from 0 to 31. The
533 names of the registers (which reflects the conventions regarding
534 register use) vary depending on the ABI. */
535 if (0 <= rawnum
&& rawnum
< 32)
537 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
538 return mips_n32_n64_gpr_names
[rawnum
];
540 return mips_gpr_names
[rawnum
];
542 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
544 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
545 return tdep
->mips_processor_reg_names
[rawnum
- 32];
548 internal_error (__FILE__
, __LINE__
,
549 "mips_register_name: bad register number %d", rawnum
);
552 /* Return the groups that a MIPS register can be categorised into. */
555 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
556 struct reggroup
*reggroup
)
561 int rawnum
= regnum
% NUM_REGS
;
562 int pseudo
= regnum
/ NUM_REGS
;
563 if (reggroup
== all_reggroup
)
565 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
566 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
567 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
568 (gdbarch), as not all architectures are multi-arch. */
569 raw_p
= rawnum
< NUM_REGS
;
570 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
572 if (reggroup
== float_reggroup
)
573 return float_p
&& pseudo
;
574 if (reggroup
== vector_reggroup
)
575 return vector_p
&& pseudo
;
576 if (reggroup
== general_reggroup
)
577 return (!vector_p
&& !float_p
) && pseudo
;
578 /* Save the pseudo registers. Need to make certain that any code
579 extracting register values from a saved register cache also uses
581 if (reggroup
== save_reggroup
)
582 return raw_p
&& pseudo
;
583 /* Restore the same pseudo register. */
584 if (reggroup
== restore_reggroup
)
585 return raw_p
&& pseudo
;
589 /* Map the symbol table registers which live in the range [1 *
590 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
591 registers. Take care of alignment and size problems. */
594 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
595 int cookednum
, void *buf
)
597 int rawnum
= cookednum
% NUM_REGS
;
598 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
599 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
600 regcache_raw_read (regcache
, rawnum
, buf
);
601 else if (register_size (gdbarch
, rawnum
) >
602 register_size (gdbarch
, cookednum
))
604 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
605 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
606 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
608 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
611 internal_error (__FILE__
, __LINE__
, "bad register size");
615 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
616 struct regcache
*regcache
, int cookednum
,
619 int rawnum
= cookednum
% NUM_REGS
;
620 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
621 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
622 regcache_raw_write (regcache
, rawnum
, buf
);
623 else if (register_size (gdbarch
, rawnum
) >
624 register_size (gdbarch
, cookednum
))
626 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
627 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
628 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
630 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
633 internal_error (__FILE__
, __LINE__
, "bad register size");
636 /* Table to translate MIPS16 register field to actual register number. */
637 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
639 /* Heuristic_proc_start may hunt through the text section for a long
640 time across a 2400 baud serial line. Allows the user to limit this
643 static unsigned int heuristic_fence_post
= 0;
645 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
646 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
647 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
648 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
649 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
650 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
651 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
652 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
653 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
654 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
655 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
656 this will corrupt pdr.iline. Fortunately we don't use it. */
657 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
658 #define _PROC_MAGIC_ 0x0F0F0F0F
659 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
660 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
662 /* Number of bytes of storage in the actual machine representation for
663 register N. NOTE: This defines the pseudo register type so need to
664 rebuild the architecture vector. */
666 static int mips64_transfers_32bit_regs_p
= 0;
669 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
670 struct cmd_list_element
*c
)
672 struct gdbarch_info info
;
673 gdbarch_info_init (&info
);
674 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
675 instead of relying on globals. Doing that would let generic code
676 handle the search for this specific architecture. */
677 if (!gdbarch_update_p (info
))
679 mips64_transfers_32bit_regs_p
= 0;
680 error ("32-bit compatibility mode not supported");
684 /* Convert to/from a register and the corresponding memory value. */
687 mips_convert_register_p (int regnum
, struct type
*type
)
689 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
690 && register_size (current_gdbarch
, regnum
) == 4
691 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
692 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
693 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
697 mips_register_to_value (struct frame_info
*frame
, int regnum
,
698 struct type
*type
, void *to
)
700 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
701 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
705 mips_value_to_register (struct frame_info
*frame
, int regnum
,
706 struct type
*type
, const void *from
)
708 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
709 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
712 /* Return the GDB type object for the "standard" data type of data in
716 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
718 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
719 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
720 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
722 /* The floating-point registers raw, or cooked, always match
723 mips_isa_regsize(), and also map 1:1, byte for byte. */
724 switch (gdbarch_byte_order (gdbarch
))
727 if (mips_isa_regsize (gdbarch
) == 4)
728 return builtin_type_ieee_single_big
;
730 return builtin_type_ieee_double_big
;
731 case BFD_ENDIAN_LITTLE
:
732 if (mips_isa_regsize (gdbarch
) == 4)
733 return builtin_type_ieee_single_little
;
735 return builtin_type_ieee_double_little
;
736 case BFD_ENDIAN_UNKNOWN
:
738 internal_error (__FILE__
, __LINE__
, "bad switch");
741 else if (regnum
< NUM_REGS
)
743 /* The raw or ISA registers. These are all sized according to
745 if (mips_isa_regsize (gdbarch
) == 4)
746 return builtin_type_int32
;
748 return builtin_type_int64
;
752 /* The cooked or ABI registers. These are sized according to
753 the ABI (with a few complications). */
754 if (regnum
>= (NUM_REGS
755 + mips_regnum (current_gdbarch
)->fp_control_status
)
756 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
757 /* The pseudo/cooked view of the embedded registers is always
758 32-bit. The raw view is handled below. */
759 return builtin_type_int32
;
760 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
761 /* The target, while possibly using a 64-bit register buffer,
762 is only transfering 32-bits of each integer register.
763 Reflect this in the cooked/pseudo (ABI) register value. */
764 return builtin_type_int32
;
765 else if (mips_abi_regsize (gdbarch
) == 4)
766 /* The ABI is restricted to 32-bit registers (the ISA could be
768 return builtin_type_int32
;
771 return builtin_type_int64
;
775 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
780 return read_signed_register (MIPS_SP_REGNUM
);
783 /* Should the upper word of 64-bit addresses be zeroed? */
784 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
787 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
789 switch (mask_address_var
)
791 case AUTO_BOOLEAN_TRUE
:
793 case AUTO_BOOLEAN_FALSE
:
796 case AUTO_BOOLEAN_AUTO
:
797 return tdep
->default_mask_address_p
;
799 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
805 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
807 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
808 switch (mask_address_var
)
810 case AUTO_BOOLEAN_TRUE
:
811 printf_filtered ("The 32 bit mips address mask is enabled\n");
813 case AUTO_BOOLEAN_FALSE
:
814 printf_filtered ("The 32 bit mips address mask is disabled\n");
816 case AUTO_BOOLEAN_AUTO
:
818 ("The 32 bit address mask is set automatically. Currently %s\n",
819 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
822 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
827 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
830 pc_is_mips16 (bfd_vma memaddr
)
832 struct minimal_symbol
*sym
;
834 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
835 if (is_mips16_addr (memaddr
))
838 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
839 the high bit of the info field. Use this to decide if the function is
840 MIPS16 or normal MIPS. */
841 sym
= lookup_minimal_symbol_by_pc (memaddr
);
843 return msymbol_is_special (sym
);
848 /* MIPS believes that the PC has a sign extended value. Perhaps the
849 all registers should be sign extended for simplicity? */
852 mips_read_pc (ptid_t ptid
)
854 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
858 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
860 return frame_unwind_register_signed (next_frame
,
861 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
864 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
865 dummy frame. The frame ID's base needs to match the TOS value
866 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
869 static struct frame_id
870 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
872 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
873 frame_pc_unwind (next_frame
));
877 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
879 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
882 /* This returns the PC of the first inst after the prologue. If we can't
883 find the prologue, then return 0. */
886 after_prologue (CORE_ADDR pc
)
888 mips_extra_func_info_t proc_desc
;
889 struct symtab_and_line sal
;
890 CORE_ADDR func_addr
, func_end
;
891 CORE_ADDR startaddr
= 0;
893 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
894 attempt to read the stack pointer from the current machine state,
895 because the current machine state has nothing to do with the
896 information we need from the proc_desc; and the process may or
897 may not exist right now. */
898 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
901 /* IF this is the topmost frame AND (this proc does not have
902 debugging information OR the PC is in the procedure prologue)
903 THEN create a "heuristic" proc_desc (by analyzing the actual
904 code) to replace the "official" proc_desc. */
905 struct symtab_and_line val
;
906 struct symbol
*proc_symbol
=
907 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
911 val
= find_pc_line (BLOCK_START
912 (SYMBOL_BLOCK_VALUE (proc_symbol
)), 0);
913 val
.pc
= val
.end
? val
.end
: pc
;
915 if (!proc_symbol
|| pc
< val
.pc
)
917 mips_extra_func_info_t found_heuristic
=
918 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
);
920 proc_desc
= found_heuristic
;
926 startaddr
= heuristic_proc_start (pc
);
928 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
);
933 /* If function is frameless, then we need to do it the hard way. I
934 strongly suspect that frameless always means prologueless... */
935 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
936 && PROC_FRAME_OFFSET (proc_desc
) == 0)
940 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
941 return 0; /* Unknown */
943 sal
= find_pc_line (func_addr
, 0);
945 if (sal
.end
< func_end
)
948 /* The line after the prologue is after the end of the function. In this
949 case, tell the caller to find the prologue the hard way. */
954 /* Decode a MIPS32 instruction that saves a register in the stack, and
955 set the appropriate bit in the general register mask or float register mask
956 to indicate which register is saved. This is a helper function
957 for mips_find_saved_regs. */
960 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
961 unsigned long *float_mask
)
965 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
966 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
967 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
969 /* It might be possible to use the instruction to
970 find the offset, rather than the code below which
971 is based on things being in a certain order in the
972 frame, but figuring out what the instruction's offset
973 is relative to might be a little tricky. */
974 reg
= (inst
& 0x001f0000) >> 16;
975 *gen_mask
|= (1 << reg
);
977 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
978 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
979 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
982 reg
= ((inst
& 0x001f0000) >> 16);
983 *float_mask
|= (1 << reg
);
987 /* Decode a MIPS16 instruction that saves a register in the stack, and
988 set the appropriate bit in the general register or float register mask
989 to indicate which register is saved. This is a helper function
990 for mips_find_saved_regs. */
993 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
995 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
997 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
998 *gen_mask
|= (1 << reg
);
1000 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1002 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1003 *gen_mask
|= (1 << reg
);
1005 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
1006 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1007 *gen_mask
|= (1 << RA_REGNUM
);
1011 /* Fetch and return instruction from the specified location. If the PC
1012 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1015 mips_fetch_instruction (CORE_ADDR addr
)
1017 char buf
[MIPS_INSTLEN
];
1021 if (pc_is_mips16 (addr
))
1023 instlen
= MIPS16_INSTLEN
;
1024 addr
= unmake_mips16_addr (addr
);
1027 instlen
= MIPS_INSTLEN
;
1028 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1030 memory_error (status
, addr
);
1031 return extract_unsigned_integer (buf
, instlen
);
1035 mips16_fetch_instruction (CORE_ADDR addr
)
1037 char buf
[MIPS_INSTLEN
];
1041 instlen
= MIPS16_INSTLEN
;
1042 addr
= unmake_mips16_addr (addr
);
1043 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1045 memory_error (status
, addr
);
1046 return extract_unsigned_integer (buf
, instlen
);
1050 mips32_fetch_instruction (CORE_ADDR addr
)
1052 char buf
[MIPS_INSTLEN
];
1055 instlen
= MIPS_INSTLEN
;
1056 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
1058 memory_error (status
, addr
);
1059 return extract_unsigned_integer (buf
, instlen
);
1063 /* These the fields of 32 bit mips instructions */
1064 #define mips32_op(x) (x >> 26)
1065 #define itype_op(x) (x >> 26)
1066 #define itype_rs(x) ((x >> 21) & 0x1f)
1067 #define itype_rt(x) ((x >> 16) & 0x1f)
1068 #define itype_immediate(x) (x & 0xffff)
1070 #define jtype_op(x) (x >> 26)
1071 #define jtype_target(x) (x & 0x03ffffff)
1073 #define rtype_op(x) (x >> 26)
1074 #define rtype_rs(x) ((x >> 21) & 0x1f)
1075 #define rtype_rt(x) ((x >> 16) & 0x1f)
1076 #define rtype_rd(x) ((x >> 11) & 0x1f)
1077 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1078 #define rtype_funct(x) (x & 0x3f)
1081 mips32_relative_offset (unsigned long inst
)
1084 x
= itype_immediate (inst
);
1085 if (x
& 0x8000) /* sign bit set */
1087 x
|= 0xffff0000; /* sign extension */
1093 /* Determine whate to set a single step breakpoint while considering
1094 branch prediction */
1096 mips32_next_pc (CORE_ADDR pc
)
1100 inst
= mips_fetch_instruction (pc
);
1101 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1103 if (itype_op (inst
) >> 2 == 5)
1104 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1106 op
= (itype_op (inst
) & 0x03);
1116 goto greater_branch
;
1121 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1122 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1124 int tf
= itype_rt (inst
) & 0x01;
1125 int cnum
= itype_rt (inst
) >> 2;
1127 read_signed_register (mips_regnum (current_gdbarch
)->
1129 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1131 if (((cond
>> cnum
) & 0x01) == tf
)
1132 pc
+= mips32_relative_offset (inst
) + 4;
1137 pc
+= 4; /* Not a branch, next instruction is easy */
1140 { /* This gets way messy */
1142 /* Further subdivide into SPECIAL, REGIMM and other */
1143 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1145 case 0: /* SPECIAL */
1146 op
= rtype_funct (inst
);
1151 /* Set PC to that address */
1152 pc
= read_signed_register (rtype_rs (inst
));
1158 break; /* end SPECIAL */
1159 case 1: /* REGIMM */
1161 op
= itype_rt (inst
); /* branch condition */
1166 case 16: /* BLTZAL */
1167 case 18: /* BLTZALL */
1169 if (read_signed_register (itype_rs (inst
)) < 0)
1170 pc
+= mips32_relative_offset (inst
) + 4;
1172 pc
+= 8; /* after the delay slot */
1176 case 17: /* BGEZAL */
1177 case 19: /* BGEZALL */
1178 if (read_signed_register (itype_rs (inst
)) >= 0)
1179 pc
+= mips32_relative_offset (inst
) + 4;
1181 pc
+= 8; /* after the delay slot */
1183 /* All of the other instructions in the REGIMM category */
1188 break; /* end REGIMM */
1193 reg
= jtype_target (inst
) << 2;
1194 /* Upper four bits get never changed... */
1195 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1198 /* FIXME case JALX : */
1201 reg
= jtype_target (inst
) << 2;
1202 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1203 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1205 break; /* The new PC will be alternate mode */
1206 case 4: /* BEQ, BEQL */
1208 if (read_signed_register (itype_rs (inst
)) ==
1209 read_signed_register (itype_rt (inst
)))
1210 pc
+= mips32_relative_offset (inst
) + 4;
1214 case 5: /* BNE, BNEL */
1216 if (read_signed_register (itype_rs (inst
)) !=
1217 read_signed_register (itype_rt (inst
)))
1218 pc
+= mips32_relative_offset (inst
) + 4;
1222 case 6: /* BLEZ, BLEZL */
1223 if (read_signed_register (itype_rs (inst
) <= 0))
1224 pc
+= mips32_relative_offset (inst
) + 4;
1230 greater_branch
: /* BGTZ, BGTZL */
1231 if (read_signed_register (itype_rs (inst
) > 0))
1232 pc
+= mips32_relative_offset (inst
) + 4;
1239 } /* mips32_next_pc */
1241 /* Decoding the next place to set a breakpoint is irregular for the
1242 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1243 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1244 We dont want to set a single step instruction on the extend instruction
1248 /* Lots of mips16 instruction formats */
1249 /* Predicting jumps requires itype,ritype,i8type
1250 and their extensions extItype,extritype,extI8type
1252 enum mips16_inst_fmts
1254 itype
, /* 0 immediate 5,10 */
1255 ritype
, /* 1 5,3,8 */
1256 rrtype
, /* 2 5,3,3,5 */
1257 rritype
, /* 3 5,3,3,5 */
1258 rrrtype
, /* 4 5,3,3,3,2 */
1259 rriatype
, /* 5 5,3,3,1,4 */
1260 shifttype
, /* 6 5,3,3,3,2 */
1261 i8type
, /* 7 5,3,8 */
1262 i8movtype
, /* 8 5,3,3,5 */
1263 i8mov32rtype
, /* 9 5,3,5,3 */
1264 i64type
, /* 10 5,3,8 */
1265 ri64type
, /* 11 5,3,3,5 */
1266 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1267 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1268 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1269 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1270 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1271 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1272 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1273 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1274 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1275 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1277 /* I am heaping all the fields of the formats into one structure and
1278 then, only the fields which are involved in instruction extension */
1282 unsigned int regx
; /* Function in i8 type */
1287 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1288 for the bits which make up the immediatate extension. */
1291 extended_offset (unsigned int extension
)
1294 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1296 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1298 value
|= extension
& 0x01f; /* extract 4:0 */
1302 /* Only call this function if you know that this is an extendable
1303 instruction, It wont malfunction, but why make excess remote memory references?
1304 If the immediate operands get sign extended or somthing, do it after
1305 the extension is performed.
1307 /* FIXME: Every one of these cases needs to worry about sign extension
1308 when the offset is to be used in relative addressing */
1312 fetch_mips_16 (CORE_ADDR pc
)
1315 pc
&= 0xfffffffe; /* clear the low order bit */
1316 target_read_memory (pc
, buf
, 2);
1317 return extract_unsigned_integer (buf
, 2);
1321 unpack_mips16 (CORE_ADDR pc
,
1322 unsigned int extension
,
1324 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1329 switch (insn_format
)
1336 value
= extended_offset (extension
);
1337 value
= value
<< 11; /* rom for the original value */
1338 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1342 value
= inst
& 0x7ff;
1343 /* FIXME : Consider sign extension */
1352 { /* A register identifier and an offset */
1353 /* Most of the fields are the same as I type but the
1354 immediate value is of a different length */
1358 value
= extended_offset (extension
);
1359 value
= value
<< 8; /* from the original instruction */
1360 value
|= inst
& 0xff; /* eleven bits from instruction */
1361 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1362 if (value
& 0x4000) /* test the sign bit , bit 26 */
1364 value
&= ~0x3fff; /* remove the sign bit */
1370 value
= inst
& 0xff; /* 8 bits */
1371 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1372 /* FIXME: Do sign extension , this format needs it */
1373 if (value
& 0x80) /* THIS CONFUSES ME */
1375 value
&= 0xef; /* remove the sign bit */
1385 unsigned long value
;
1386 unsigned int nexthalf
;
1387 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1388 value
= value
<< 16;
1389 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1397 internal_error (__FILE__
, __LINE__
, "bad switch");
1399 upk
->offset
= offset
;
1406 add_offset_16 (CORE_ADDR pc
, int offset
)
1408 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1412 extended_mips16_next_pc (CORE_ADDR pc
,
1413 unsigned int extension
, unsigned int insn
)
1415 int op
= (insn
>> 11);
1418 case 2: /* Branch */
1421 struct upk_mips16 upk
;
1422 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1423 offset
= upk
.offset
;
1429 pc
+= (offset
<< 1) + 2;
1432 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1434 struct upk_mips16 upk
;
1435 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1436 pc
= add_offset_16 (pc
, upk
.offset
);
1437 if ((insn
>> 10) & 0x01) /* Exchange mode */
1438 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1445 struct upk_mips16 upk
;
1447 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1448 reg
= read_signed_register (upk
.regx
);
1450 pc
+= (upk
.offset
<< 1) + 2;
1457 struct upk_mips16 upk
;
1459 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1460 reg
= read_signed_register (upk
.regx
);
1462 pc
+= (upk
.offset
<< 1) + 2;
1467 case 12: /* I8 Formats btez btnez */
1469 struct upk_mips16 upk
;
1471 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1472 /* upk.regx contains the opcode */
1473 reg
= read_signed_register (24); /* Test register is 24 */
1474 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1475 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1476 /* pc = add_offset_16(pc,upk.offset) ; */
1477 pc
+= (upk
.offset
<< 1) + 2;
1482 case 29: /* RR Formats JR, JALR, JALR-RA */
1484 struct upk_mips16 upk
;
1485 /* upk.fmt = rrtype; */
1490 upk
.regx
= (insn
>> 8) & 0x07;
1491 upk
.regy
= (insn
>> 5) & 0x07;
1499 break; /* Function return instruction */
1505 break; /* BOGUS Guess */
1507 pc
= read_signed_register (reg
);
1514 /* This is an instruction extension. Fetch the real instruction
1515 (which follows the extension) and decode things based on
1519 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1532 mips16_next_pc (CORE_ADDR pc
)
1534 unsigned int insn
= fetch_mips_16 (pc
);
1535 return extended_mips16_next_pc (pc
, 0, insn
);
1538 /* The mips_next_pc function supports single_step when the remote
1539 target monitor or stub is not developed enough to do a single_step.
1540 It works by decoding the current instruction and predicting where a
1541 branch will go. This isnt hard because all the data is available.
1542 The MIPS32 and MIPS16 variants are quite different */
1544 mips_next_pc (CORE_ADDR pc
)
1547 return mips16_next_pc (pc
);
1549 return mips32_next_pc (pc
);
1552 struct mips_frame_cache
1555 struct trad_frame_saved_reg
*saved_regs
;
1559 static struct mips_frame_cache
*
1560 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1562 mips_extra_func_info_t proc_desc
;
1563 struct mips_frame_cache
*cache
;
1564 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1565 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1566 /* r0 bit means kernel trap */
1568 /* What registers have been saved? Bitmasks. */
1569 unsigned long gen_mask
, float_mask
;
1571 if ((*this_cache
) != NULL
)
1572 return (*this_cache
);
1573 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1574 (*this_cache
) = cache
;
1575 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1577 /* Get the mdebug proc descriptor. */
1578 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
);
1579 if (proc_desc
== NULL
)
1580 /* I'm not sure how/whether this can happen. Normally when we
1581 can't find a proc_desc, we "synthesize" one using
1582 heuristic_proc_desc and set the saved_regs right away. */
1585 /* Extract the frame's base. */
1586 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1587 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1589 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1590 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1591 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1593 /* In any frame other than the innermost or a frame interrupted by a
1594 signal, we assume that all registers have been saved. This
1595 assumes that all register saves in a function happen before the
1596 first function call. */
1597 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1598 /* Not sure exactly what kernel_trap means, but if it means the
1599 kernel saves the registers without a prologue doing it, we
1600 better not examine the prologue to see whether registers
1601 have been saved yet. */
1604 /* We need to figure out whether the registers that the
1605 proc_desc claims are saved have been saved yet. */
1609 /* Bitmasks; set if we have found a save for the register. */
1610 unsigned long gen_save_found
= 0;
1611 unsigned long float_save_found
= 0;
1614 /* If the address is odd, assume this is MIPS16 code. */
1615 addr
= PROC_LOW_ADDR (proc_desc
);
1616 mips16
= pc_is_mips16 (addr
);
1618 /* Scan through this function's instructions preceding the
1619 current PC, and look for those that save registers. */
1620 while (addr
< frame_pc_unwind (next_frame
))
1624 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1626 addr
+= MIPS16_INSTLEN
;
1630 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1631 &gen_save_found
, &float_save_found
);
1632 addr
+= MIPS_INSTLEN
;
1635 gen_mask
= gen_save_found
;
1636 float_mask
= float_save_found
;
1639 /* Fill in the offsets for the registers which gen_mask says were
1642 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1645 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1646 if (gen_mask
& 0x80000000)
1648 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1649 reg_position
-= mips_abi_regsize (gdbarch
);
1653 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1654 order of that normally used by gcc. Therefore, we have to fetch
1655 the first instruction of the function, and if it's an entry
1656 instruction that saves $s0 or $s1, correct their saved addresses. */
1657 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1659 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1660 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1664 int sreg_count
= (inst
>> 6) & 3;
1666 /* Check if the ra register was pushed on the stack. */
1667 CORE_ADDR reg_position
= (cache
->base
1668 + PROC_REG_OFFSET (proc_desc
));
1670 reg_position
-= mips_abi_regsize (gdbarch
);
1672 /* Check if the s0 and s1 registers were pushed on the
1674 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1676 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1678 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1679 reg_position
-= mips_abi_regsize (gdbarch
);
1684 /* Fill in the offsets for the registers which float_mask says were
1687 CORE_ADDR reg_position
= (cache
->base
1688 + PROC_FREG_OFFSET (proc_desc
));
1690 /* Fill in the offsets for the float registers which float_mask
1692 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1693 if (float_mask
& 0x80000000)
1695 if (mips_abi_regsize (gdbarch
) == 4
1696 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1698 /* On a big endian 32 bit ABI, floating point registers
1699 are paired to form doubles such that the most
1700 significant part is in $f[N+1] and the least
1701 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1702 registers are also spilled as a pair and stored as a
1705 When little-endian the least significant part is
1706 stored first leading to the memory order $f[N] and
1709 Unfortunately, when big-endian the most significant
1710 part of the double is stored first, and the least
1711 significant is stored second. This leads to the
1712 registers being ordered in memory as firt $f[N+1] and
1715 For the big-endian case make certain that the
1716 addresses point at the correct (swapped) locations
1717 $f[N] and $f[N+1] pair (keep in mind that
1718 reg_position is decremented each time through the
1721 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1722 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1724 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1725 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1728 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1729 .addr
= reg_position
;
1730 reg_position
-= mips_abi_regsize (gdbarch
);
1733 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1734 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
1737 /* SP_REGNUM, contains the value and not the address. */
1738 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1740 return (*this_cache
);
1744 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1745 struct frame_id
*this_id
)
1747 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1749 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1753 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1755 int regnum
, int *optimizedp
,
1756 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1757 int *realnump
, void *valuep
)
1759 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1761 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1762 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1765 static const struct frame_unwind mips_mdebug_frame_unwind
=
1768 mips_mdebug_frame_this_id
,
1769 mips_mdebug_frame_prev_register
1772 static const struct frame_unwind
*
1773 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1775 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1776 CORE_ADDR startaddr
= 0;
1777 mips_extra_func_info_t proc_desc
;
1780 /* Only use the mdebug frame unwinder on mdebug frames where all the
1781 registers have been saved. Leave hard cases such as no mdebug or
1782 in prologue for the heuristic unwinders. */
1784 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1785 if (proc_desc
== NULL
)
1788 /* Not sure exactly what kernel_trap means, but if it means the
1789 kernel saves the registers without a prologue doing it, we better
1790 not examine the prologue to see whether registers have been saved
1792 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1794 return &mips_mdebug_frame_unwind
;
1796 /* In any frame other than the innermost or a frame interrupted by a
1797 signal, we assume that all registers have been saved. This
1798 assumes that all register saves in a function happen before the
1799 first function call. */
1800 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1801 return &mips_mdebug_frame_unwind
;
1807 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1810 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1815 static const struct frame_base mips_mdebug_frame_base
= {
1816 &mips_mdebug_frame_unwind
,
1817 mips_mdebug_frame_base_address
,
1818 mips_mdebug_frame_base_address
,
1819 mips_mdebug_frame_base_address
1822 static const struct frame_base
*
1823 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1825 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1826 return &mips_mdebug_frame_base
;
1831 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1832 Procedures that use the 32-bit instruction set are handled by the
1833 mips_insn32 unwinder. */
1835 static struct mips_frame_cache
*
1836 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1838 mips_extra_func_info_t proc_desc
;
1839 struct mips_frame_cache
*cache
;
1840 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1841 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1842 /* r0 bit means kernel trap */
1844 /* What registers have been saved? Bitmasks. */
1845 unsigned long gen_mask
, float_mask
;
1847 if ((*this_cache
) != NULL
)
1848 return (*this_cache
);
1849 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1850 (*this_cache
) = cache
;
1851 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1853 /* Get the mdebug proc descriptor. */
1854 proc_desc
= find_proc_desc (frame_pc_unwind (next_frame
), next_frame
);
1855 if (proc_desc
== NULL
)
1856 /* I'm not sure how/whether this can happen. Normally when we
1857 can't find a proc_desc, we "synthesize" one using
1858 heuristic_proc_desc and set the saved_regs right away. */
1861 /* Extract the frame's base. */
1862 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1863 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1865 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1866 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1867 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1869 /* In any frame other than the innermost or a frame interrupted by a
1870 signal, we assume that all registers have been saved. This
1871 assumes that all register saves in a function happen before the
1872 first function call. */
1873 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1874 /* Not sure exactly what kernel_trap means, but if it means the
1875 kernel saves the registers without a prologue doing it, we
1876 better not examine the prologue to see whether registers
1877 have been saved yet. */
1880 /* We need to figure out whether the registers that the
1881 proc_desc claims are saved have been saved yet. */
1885 /* Bitmasks; set if we have found a save for the register. */
1886 unsigned long gen_save_found
= 0;
1887 unsigned long float_save_found
= 0;
1890 /* If the address is odd, assume this is MIPS16 code. */
1891 addr
= PROC_LOW_ADDR (proc_desc
);
1892 mips16
= pc_is_mips16 (addr
);
1894 /* Scan through this function's instructions preceding the
1895 current PC, and look for those that save registers. */
1896 while (addr
< frame_pc_unwind (next_frame
))
1900 mips16_decode_reg_save (mips16_fetch_instruction (addr
),
1902 addr
+= MIPS16_INSTLEN
;
1906 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
1907 &gen_save_found
, &float_save_found
);
1908 addr
+= MIPS_INSTLEN
;
1911 gen_mask
= gen_save_found
;
1912 float_mask
= float_save_found
;
1915 /* Fill in the offsets for the registers which gen_mask says were
1918 CORE_ADDR reg_position
= (cache
->base
1919 + PROC_REG_OFFSET (proc_desc
));
1921 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1922 if (gen_mask
& 0x80000000)
1924 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1925 reg_position
-= mips_abi_regsize (gdbarch
);
1929 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1930 order of that normally used by gcc. Therefore, we have to fetch
1931 the first instruction of the function, and if it's an entry
1932 instruction that saves $s0 or $s1, correct their saved addresses. */
1933 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1935 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1936 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1940 int sreg_count
= (inst
>> 6) & 3;
1942 /* Check if the ra register was pushed on the stack. */
1943 CORE_ADDR reg_position
= (cache
->base
1944 + PROC_REG_OFFSET (proc_desc
));
1946 reg_position
-= mips_abi_regsize (gdbarch
);
1948 /* Check if the s0 and s1 registers were pushed on the
1950 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1952 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1954 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1955 reg_position
-= mips_abi_regsize (gdbarch
);
1960 /* Fill in the offsets for the registers which float_mask says were
1963 CORE_ADDR reg_position
= (cache
->base
1964 + PROC_FREG_OFFSET (proc_desc
));
1966 /* Fill in the offsets for the float registers which float_mask
1968 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1969 if (float_mask
& 0x80000000)
1971 if (mips_abi_regsize (gdbarch
) == 4
1972 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1974 /* On a big endian 32 bit ABI, floating point registers
1975 are paired to form doubles such that the most
1976 significant part is in $f[N+1] and the least
1977 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1978 registers are also spilled as a pair and stored as a
1981 When little-endian the least significant part is
1982 stored first leading to the memory order $f[N] and
1985 Unfortunately, when big-endian the most significant
1986 part of the double is stored first, and the least
1987 significant is stored second. This leads to the
1988 registers being ordered in memory as firt $f[N+1] and
1991 For the big-endian case make certain that the
1992 addresses point at the correct (swapped) locations
1993 $f[N] and $f[N+1] pair (keep in mind that
1994 reg_position is decremented each time through the
1997 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1998 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
2000 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2001 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
2004 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
2005 .addr
= reg_position
;
2006 reg_position
-= mips_abi_regsize (gdbarch
);
2009 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2010 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2013 /* SP_REGNUM, contains the value and not the address. */
2014 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2016 return (*this_cache
);
2020 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2021 struct frame_id
*this_id
)
2023 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2025 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2029 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
2031 int regnum
, int *optimizedp
,
2032 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2033 int *realnump
, void *valuep
)
2035 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2037 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2038 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2041 static const struct frame_unwind mips_insn16_frame_unwind
=
2044 mips_insn16_frame_this_id
,
2045 mips_insn16_frame_prev_register
2048 static const struct frame_unwind
*
2049 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
2051 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2052 if (pc_is_mips16 (pc
))
2053 return &mips_insn16_frame_unwind
;
2058 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
2061 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2066 static const struct frame_base mips_insn16_frame_base
=
2068 &mips_insn16_frame_unwind
,
2069 mips_insn16_frame_base_address
,
2070 mips_insn16_frame_base_address
,
2071 mips_insn16_frame_base_address
2074 static const struct frame_base
*
2075 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
2077 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
2078 return &mips_insn16_frame_base
;
2083 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2084 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2085 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2088 static struct mips_frame_cache
*
2089 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2091 mips_extra_func_info_t proc_desc
;
2092 struct mips_frame_cache
*cache
;
2093 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2094 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2095 /* r0 bit means kernel trap */
2097 /* What registers have been saved? Bitmasks. */
2098 unsigned long gen_mask
, float_mask
;
2100 if ((*this_cache
) != NULL
)
2101 return (*this_cache
);
2102 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2103 (*this_cache
) = cache
;
2104 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2106 /* Synthesize a proc descriptor. */
2108 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2109 CORE_ADDR start_addr
;
2111 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2112 if (start_addr
== 0)
2113 start_addr
= heuristic_proc_start (pc
);
2115 proc_desc
= heuristic_proc_desc (start_addr
, pc
, next_frame
);
2118 if (proc_desc
== NULL
)
2119 /* I'm not sure how/whether this can happen. Normally when we
2120 can't find a proc_desc, we "synthesize" one using
2121 heuristic_proc_desc and set the saved_regs right away. */
2124 /* Extract the frame's base. */
2125 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
2126 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
2128 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
2129 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
2130 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
2132 /* In any frame other than the innermost or a frame interrupted by a
2133 signal, we assume that all registers have been saved. This
2134 assumes that all register saves in a function happen before the
2135 first function call. */
2136 if (in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
2137 /* Not sure exactly what kernel_trap means, but if it means the
2138 kernel saves the registers without a prologue doing it, we
2139 better not examine the prologue to see whether registers
2140 have been saved yet. */
2143 /* We need to figure out whether the registers that the
2144 proc_desc claims are saved have been saved yet. */
2148 /* Bitmasks; set if we have found a save for the register. */
2149 unsigned long gen_save_found
= 0;
2150 unsigned long float_save_found
= 0;
2152 addr
= PROC_LOW_ADDR (proc_desc
);
2154 /* Scan through this function's instructions preceding the
2155 current PC, and look for those that save registers. */
2156 while (addr
< frame_pc_unwind (next_frame
))
2158 mips32_decode_reg_save (mips32_fetch_instruction (addr
),
2159 &gen_save_found
, &float_save_found
);
2160 addr
+= MIPS_INSTLEN
;
2162 gen_mask
= gen_save_found
;
2163 float_mask
= float_save_found
;
2166 /* Fill in the offsets for the registers which gen_mask says were
2169 CORE_ADDR reg_position
= (cache
->base
2170 + PROC_REG_OFFSET (proc_desc
));
2172 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
2173 if (gen_mask
& 0x80000000)
2175 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
2176 reg_position
-= mips_abi_regsize (gdbarch
);
2180 /* Fill in the offsets for the registers which float_mask says were
2183 CORE_ADDR reg_position
= (cache
->base
+ PROC_FREG_OFFSET (proc_desc
));
2186 /* Fill in the offsets for the float registers which float_mask
2188 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
2189 if (float_mask
& 0x80000000)
2192 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
;
2194 if (mips_abi_regsize (gdbarch
) == 4
2195 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2197 /* On a big endian 32 bit ABI, floating point registers
2198 are paired to form doubles such that the most
2199 significant part is in $f[N+1] and the least
2200 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
2201 registers are also spilled as a pair and stored as a
2204 When little-endian the least significant part is
2205 stored first leading to the memory order $f[N] and
2208 Unfortunately, when big-endian the most significant
2209 part of the double is stored first, and the least
2210 significant is stored second. This leads to the
2211 registers being ordered in memory as firt $f[N+1] and
2214 For the big-endian case make certain that the
2215 addresses point at the correct (swapped) locations
2216 $f[N] and $f[N+1] pair (keep in mind that
2217 reg_position is decremented each time through the
2220 cache
->saved_regs
[regno
].addr
=
2221 reg_position
- mips_abi_regsize (gdbarch
);
2223 cache
->saved_regs
[regno
].addr
=
2224 reg_position
+ mips_abi_regsize (gdbarch
);
2227 cache
->saved_regs
[regno
].addr
= reg_position
;
2228 reg_position
-= mips_abi_regsize (gdbarch
);
2231 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2232 = cache
->saved_regs
[NUM_REGS
+ RA_REGNUM
];
2235 /* SP_REGNUM, contains the value and not the address. */
2236 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2238 return (*this_cache
);
2242 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2243 struct frame_id
*this_id
)
2245 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2247 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2251 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2253 int regnum
, int *optimizedp
,
2254 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2255 int *realnump
, void *valuep
)
2257 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2259 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2260 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2263 static const struct frame_unwind mips_insn32_frame_unwind
=
2266 mips_insn32_frame_this_id
,
2267 mips_insn32_frame_prev_register
2270 static const struct frame_unwind
*
2271 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2273 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2274 if (! pc_is_mips16 (pc
))
2275 return &mips_insn32_frame_unwind
;
2280 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2283 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2288 static const struct frame_base mips_insn32_frame_base
=
2290 &mips_insn32_frame_unwind
,
2291 mips_insn32_frame_base_address
,
2292 mips_insn32_frame_base_address
,
2293 mips_insn32_frame_base_address
2296 static const struct frame_base
*
2297 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2299 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2300 return &mips_insn32_frame_base
;
2305 static struct trad_frame_cache
*
2306 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2309 CORE_ADDR start_addr
;
2310 CORE_ADDR stack_addr
;
2311 struct trad_frame_cache
*this_trad_cache
;
2313 if ((*this_cache
) != NULL
)
2314 return (*this_cache
);
2315 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2316 (*this_cache
) = this_trad_cache
;
2318 /* The return address is in the link register. */
2319 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, RA_REGNUM
);
2321 /* Frame ID, since it's a frameless / stackless function, no stack
2322 space is allocated and SP on entry is the current SP. */
2323 pc
= frame_pc_unwind (next_frame
);
2324 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2325 stack_addr
= frame_unwind_register_signed (next_frame
, SP_REGNUM
);
2326 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2328 /* Assume that the frame's base is the same as the
2330 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2332 return this_trad_cache
;
2336 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2337 struct frame_id
*this_id
)
2339 struct trad_frame_cache
*this_trad_cache
2340 = mips_stub_frame_cache (next_frame
, this_cache
);
2341 trad_frame_get_id (this_trad_cache
, this_id
);
2345 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2347 int regnum
, int *optimizedp
,
2348 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2349 int *realnump
, void *valuep
)
2351 struct trad_frame_cache
*this_trad_cache
2352 = mips_stub_frame_cache (next_frame
, this_cache
);
2353 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2354 lvalp
, addrp
, realnump
, valuep
);
2357 static const struct frame_unwind mips_stub_frame_unwind
=
2360 mips_stub_frame_this_id
,
2361 mips_stub_frame_prev_register
2364 static const struct frame_unwind
*
2365 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2367 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2368 if (in_plt_section (pc
, NULL
))
2369 return &mips_stub_frame_unwind
;
2375 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2378 struct trad_frame_cache
*this_trad_cache
2379 = mips_stub_frame_cache (next_frame
, this_cache
);
2380 return trad_frame_get_this_base (this_trad_cache
);
2383 static const struct frame_base mips_stub_frame_base
=
2385 &mips_stub_frame_unwind
,
2386 mips_stub_frame_base_address
,
2387 mips_stub_frame_base_address
,
2388 mips_stub_frame_base_address
2391 static const struct frame_base
*
2392 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2394 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2395 return &mips_stub_frame_base
;
2401 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2403 /* Always a pseudo. */
2404 gdb_assert (regno
>= NUM_REGS
);
2408 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2411 else if ((regno
% NUM_REGS
) == MIPS_SP_REGNUM
)
2412 /* MIPS_SP_REGNUM is special, its value is stored in saved_regs.
2413 In fact, it is so special that it can even only be fetched
2414 using a raw register number! Once this code as been converted
2415 to frame-unwind the problem goes away. */
2416 return frame_unwind_register_signed (fi
, regno
% NUM_REGS
);
2418 return frame_unwind_register_signed (fi
, regno
);
2422 /* mips_addr_bits_remove - remove useless address bits */
2425 mips_addr_bits_remove (CORE_ADDR addr
)
2427 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2428 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2429 /* This hack is a work-around for existing boards using PMON, the
2430 simulator, and any other 64-bit targets that doesn't have true
2431 64-bit addressing. On these targets, the upper 32 bits of
2432 addresses are ignored by the hardware. Thus, the PC or SP are
2433 likely to have been sign extended to all 1s by instruction
2434 sequences that load 32-bit addresses. For example, a typical
2435 piece of code that loads an address is this:
2437 lui $r2, <upper 16 bits>
2438 ori $r2, <lower 16 bits>
2440 But the lui sign-extends the value such that the upper 32 bits
2441 may be all 1s. The workaround is simply to mask off these
2442 bits. In the future, gcc may be changed to support true 64-bit
2443 addressing, and this masking will have to be disabled. */
2444 return addr
&= 0xffffffffUL
;
2449 /* mips_software_single_step() is called just before we want to resume
2450 the inferior, if we want to single-step it but there is no hardware
2451 or kernel single-step support (MIPS on GNU/Linux for example). We find
2452 the target of the coming instruction and breakpoint it.
2454 single_step is also called just after the inferior stops. If we had
2455 set up a simulated single-step, we undo our damage. */
2458 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2460 static CORE_ADDR next_pc
;
2461 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2462 static binsn_quantum break_mem
;
2465 if (insert_breakpoints_p
)
2467 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2468 next_pc
= mips_next_pc (pc
);
2470 target_insert_breakpoint (next_pc
, break_mem
);
2473 target_remove_breakpoint (next_pc
, break_mem
);
2476 static struct mips_extra_func_info temp_proc_desc
;
2478 /* This hack will go away once the get_prev_frame() code has been
2479 modified to set the frame's type first. That is BEFORE init extra
2480 frame info et.al. is called. This is because it will become
2481 possible to skip the init extra info call for sigtramp and dummy
2483 static CORE_ADDR
*temp_saved_regs
;
2485 /* Set a register's saved stack address in temp_saved_regs. If an
2486 address has already been set for this register, do nothing; this
2487 way we will only recognize the first save of a given register in a
2490 For simplicity, save the address in both [0 .. NUM_REGS) and
2491 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
2492 is used as it is only second range (the ABI instead of ISA
2493 registers) that comes into play when finding saved registers in a
2497 set_reg_offset (CORE_ADDR
*saved_regs
, int regno
, CORE_ADDR offset
)
2499 if (saved_regs
[regno
] == 0)
2501 saved_regs
[regno
+ 0 * NUM_REGS
] = offset
;
2502 saved_regs
[regno
+ 1 * NUM_REGS
] = offset
;
2507 /* Test whether the PC points to the return instruction at the
2508 end of a function. */
2511 mips_about_to_return (CORE_ADDR pc
)
2513 if (pc_is_mips16 (pc
))
2514 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2515 generates a "jr $ra"; other times it generates code to load
2516 the return address from the stack to an accessible register (such
2517 as $a3), then a "jr" using that register. This second case
2518 is almost impossible to distinguish from an indirect jump
2519 used for switch statements, so we don't even try. */
2520 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2522 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2526 /* This fencepost looks highly suspicious to me. Removing it also
2527 seems suspicious as it could affect remote debugging across serial
2531 heuristic_proc_start (CORE_ADDR pc
)
2538 pc
= ADDR_BITS_REMOVE (pc
);
2540 fence
= start_pc
- heuristic_fence_post
;
2544 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2545 fence
= VM_MIN_ADDRESS
;
2547 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
2549 /* search back for previous return */
2550 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2551 if (start_pc
< fence
)
2553 /* It's not clear to me why we reach this point when
2554 stop_soon, but with this test, at least we
2555 don't print out warnings for every child forked (eg, on
2556 decstation). 22apr93 rich@cygnus.com. */
2557 if (stop_soon
== NO_STOP_QUIETLY
)
2559 static int blurb_printed
= 0;
2561 warning ("GDB can't find the start of the function at 0x%s.",
2566 /* This actually happens frequently in embedded
2567 development, when you first connect to a board
2568 and your stack pointer and pc are nowhere in
2569 particular. This message needs to give people
2570 in that situation enough information to
2571 determine that it's no big deal. */
2572 printf_filtered ("\n\
2573 GDB is unable to find the start of the function at 0x%s\n\
2574 and thus can't determine the size of that function's stack frame.\n\
2575 This means that GDB may be unable to access that stack frame, or\n\
2576 the frames below it.\n\
2577 This problem is most likely caused by an invalid program counter or\n\
2579 However, if you think GDB should simply search farther back\n\
2580 from 0x%s for code which looks like the beginning of a\n\
2581 function, you can increase the range of the search using the `set\n\
2582 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2589 else if (pc_is_mips16 (start_pc
))
2591 unsigned short inst
;
2593 /* On MIPS16, any one of the following is likely to be the
2594 start of a function:
2598 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2599 inst
= mips_fetch_instruction (start_pc
);
2600 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2601 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2602 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2603 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2605 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2606 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2611 else if (mips_about_to_return (start_pc
))
2613 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
2620 /* Fetch the immediate value from a MIPS16 instruction.
2621 If the previous instruction was an EXTEND, use it to extend
2622 the upper bits of the immediate value. This is a helper function
2623 for mips16_heuristic_proc_desc. */
2626 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2627 unsigned short inst
, /* current instruction */
2628 int nbits
, /* number of bits in imm field */
2629 int scale
, /* scale factor to be applied to imm */
2630 int is_signed
) /* is the imm field signed? */
2634 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2636 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2637 if (offset
& 0x8000) /* check for negative extend */
2638 offset
= 0 - (0x10000 - (offset
& 0xffff));
2639 return offset
| (inst
& 0x1f);
2643 int max_imm
= 1 << nbits
;
2644 int mask
= max_imm
- 1;
2645 int sign_bit
= max_imm
>> 1;
2647 offset
= inst
& mask
;
2648 if (is_signed
&& (offset
& sign_bit
))
2649 offset
= 0 - (max_imm
- offset
);
2650 return offset
* scale
;
2655 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
2656 stream from start_pc to limit_pc. */
2659 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2660 struct frame_info
*next_frame
, CORE_ADDR sp
)
2663 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
2664 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
2665 unsigned inst
= 0; /* current instruction */
2666 unsigned entry_inst
= 0; /* the entry instruction */
2668 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2670 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
2671 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2673 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
2675 /* Save the previous instruction. If it's an EXTEND, we'll extract
2676 the immediate offset extension from it in mips16_get_imm. */
2679 /* Fetch and decode the instruction. */
2680 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
2681 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2682 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2684 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2685 if (offset
< 0) /* negative stack adjustment? */
2686 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
2688 /* Exit loop if a positive stack adjustment is found, which
2689 usually means that the stack cleanup code in the function
2690 epilogue is reached. */
2693 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2695 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2696 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
2697 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2698 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2700 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2702 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2703 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2704 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
2705 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2707 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2709 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2710 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2711 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2713 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2715 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2716 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
2717 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2719 else if (inst
== 0x673d) /* move $s1, $sp */
2722 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2724 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2726 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2727 frame_addr
= sp
+ offset
;
2728 PROC_FRAME_REG (&temp_proc_desc
) = 17;
2729 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
2731 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2733 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2734 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2735 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2736 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2738 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2740 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2741 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
2742 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2743 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ offset
);
2745 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2746 entry_inst
= inst
; /* save for later processing */
2747 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2748 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
2751 /* The entry instruction is typically the first instruction in a function,
2752 and it stores registers at offsets relative to the value of the old SP
2753 (before the prologue). But the value of the sp parameter to this
2754 function is the new SP (after the prologue has been executed). So we
2755 can't calculate those offsets until we've seen the entire prologue,
2756 and can calculate what the old SP must have been. */
2757 if (entry_inst
!= 0)
2759 int areg_count
= (entry_inst
>> 8) & 7;
2760 int sreg_count
= (entry_inst
>> 6) & 3;
2762 /* The entry instruction always subtracts 32 from the SP. */
2763 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
2765 /* Now we can calculate what the SP must have been at the
2766 start of the function prologue. */
2767 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
2769 /* Check if a0-a3 were saved in the caller's argument save area. */
2770 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2772 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2773 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2774 offset
+= mips_abi_regsize (current_gdbarch
);
2777 /* Check if the ra register was pushed on the stack. */
2779 if (entry_inst
& 0x20)
2781 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
2782 set_reg_offset (temp_saved_regs
, RA_REGNUM
, sp
+ offset
);
2783 offset
-= mips_abi_regsize (current_gdbarch
);
2786 /* Check if the s0 and s1 registers were pushed on the stack. */
2787 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2789 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2790 set_reg_offset (temp_saved_regs
, reg
, sp
+ offset
);
2791 offset
-= mips_abi_regsize (current_gdbarch
);
2797 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2798 struct frame_info
*next_frame
, CORE_ADDR sp
)
2801 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2803 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2804 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2805 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
2806 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
2807 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
2809 unsigned long inst
, high_word
, low_word
;
2812 /* Fetch the instruction. */
2813 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2815 /* Save some code by pre-extracting some useful fields. */
2816 high_word
= (inst
>> 16) & 0xffff;
2817 low_word
= inst
& 0xffff;
2818 reg
= high_word
& 0x1f;
2820 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2821 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2822 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2824 if (low_word
& 0x8000) /* negative stack adjustment? */
2825 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2827 /* Exit loop if a positive stack adjustment is found, which
2828 usually means that the stack cleanup code in the function
2829 epilogue is reached. */
2832 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2834 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2835 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2837 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2839 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and
2841 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2842 set_reg_offset (temp_saved_regs
, reg
, sp
+ low_word
);
2844 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2846 /* Old gcc frame, r30 is virtual frame pointer. */
2847 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2848 frame_addr
= sp
+ low_word
;
2849 else if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2851 unsigned alloca_adjust
;
2852 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2853 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2854 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2855 if (alloca_adjust
> 0)
2857 /* FP > SP + frame_size. This may be because
2858 * of an alloca or somethings similar.
2859 * Fix sp to "pre-alloca" value, and try again.
2861 sp
+= alloca_adjust
;
2866 /* move $30,$sp. With different versions of gas this will be either
2867 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2868 Accept any one of these. */
2869 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2871 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2872 if (PROC_FRAME_REG (&temp_proc_desc
) == MIPS_SP_REGNUM
)
2874 unsigned alloca_adjust
;
2875 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2876 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2877 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2878 if (alloca_adjust
> 0)
2880 /* FP > SP + frame_size. This may be because
2881 * of an alloca or somethings similar.
2882 * Fix sp to "pre-alloca" value, and try again.
2884 sp
+= alloca_adjust
;
2889 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2891 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2892 set_reg_offset (temp_saved_regs
, reg
, frame_addr
+ low_word
);
2897 static mips_extra_func_info_t
2898 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2899 struct frame_info
*next_frame
)
2903 /* Can be called when there's no process, and hence when there's no
2905 if (next_frame
!= NULL
)
2906 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2912 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2913 temp_saved_regs
= xrealloc (temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2914 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2915 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2916 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2917 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2919 if (start_pc
+ 200 < limit_pc
)
2920 limit_pc
= start_pc
+ 200;
2921 if (pc_is_mips16 (start_pc
))
2922 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2924 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2925 return &temp_proc_desc
;
2928 struct mips_objfile_private
2934 /* Global used to communicate between non_heuristic_proc_desc and
2935 compare_pdr_entries within qsort (). */
2936 static bfd
*the_bfd
;
2939 compare_pdr_entries (const void *a
, const void *b
)
2941 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2942 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2946 else if (lhs
== rhs
)
2952 static mips_extra_func_info_t
2953 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2955 CORE_ADDR startaddr
;
2956 mips_extra_func_info_t proc_desc
;
2957 struct block
*b
= block_for_pc (pc
);
2959 struct obj_section
*sec
;
2960 struct mips_objfile_private
*priv
;
2962 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2964 *addrptr
= startaddr
;
2968 sec
= find_pc_section (pc
);
2971 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2973 /* Search the ".pdr" section generated by GAS. This includes most of
2974 the information normally found in ECOFF PDRs. */
2976 the_bfd
= sec
->objfile
->obfd
;
2978 && (the_bfd
->format
== bfd_object
2979 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2980 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2982 /* Right now GAS only outputs the address as a four-byte sequence.
2983 This means that we should not bother with this method on 64-bit
2984 targets (until that is fixed). */
2986 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2987 sizeof (struct mips_objfile_private
));
2989 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2991 else if (priv
== NULL
)
2995 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2996 sizeof (struct mips_objfile_private
));
2998 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
3001 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
3002 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
3004 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
3005 priv
->contents
, 0, priv
->size
);
3007 /* In general, the .pdr section is sorted. However, in the
3008 presence of multiple code sections (and other corner cases)
3009 it can become unsorted. Sort it so that we can use a faster
3011 qsort (priv
->contents
, priv
->size
/ 32, 32,
3012 compare_pdr_entries
);
3017 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
3021 if (priv
->size
!= 0)
3028 high
= priv
->size
/ 32;
3030 /* We've found a .pdr section describing this objfile. We want to
3031 find the entry which describes this code address. The .pdr
3032 information is not very descriptive; we have only a function
3033 start address. We have to look for the closest entry, because
3034 the local symbol at the beginning of this function may have
3035 been stripped - so if we ask the symbol table for the start
3036 address we may get a preceding global function. */
3038 /* First, find the last .pdr entry starting at or before PC. */
3041 mid
= (low
+ high
) / 2;
3043 ptr
= priv
->contents
+ mid
* 32;
3044 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3045 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3046 SECT_OFF_TEXT (sec
->objfile
));
3053 while (low
!= high
);
3055 /* Both low and high point one past the PDR of interest. If
3056 both are zero, that means this PC is before any region
3057 covered by a PDR, i.e. pdr_pc for the first PDR entry is
3061 ptr
= priv
->contents
+ (low
- 1) * 32;
3062 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
3063 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
3064 SECT_OFF_TEXT (sec
->objfile
));
3067 /* We don't have a range, so we have no way to know for sure
3068 whether we're in the correct PDR or a PDR for a preceding
3069 function and the current function was a stripped local
3070 symbol. But if the PDR's PC is at least as great as the
3071 best guess from the symbol table, assume that it does cover
3072 the right area; if a .pdr section is present at all then
3073 nearly every function will have an entry. The biggest exception
3074 will be the dynamic linker stubs; conveniently these are
3075 placed before .text instead of after. */
3077 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
3079 struct symbol
*sym
= find_pc_function (pc
);
3084 /* Fill in what we need of the proc_desc. */
3085 proc_desc
= (mips_extra_func_info_t
)
3086 obstack_alloc (&sec
->objfile
->objfile_obstack
,
3087 sizeof (struct mips_extra_func_info
));
3088 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
3090 /* Only used for dummy frames. */
3091 PROC_HIGH_ADDR (proc_desc
) = 0;
3093 PROC_FRAME_OFFSET (proc_desc
)
3094 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
3095 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3097 PROC_FRAME_ADJUST (proc_desc
) = 0;
3098 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3100 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3102 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3104 PROC_FREG_OFFSET (proc_desc
)
3105 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
3106 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
3108 proc_desc
->pdr
.isym
= (long) sym
;
3118 if (startaddr
> BLOCK_START (b
))
3120 /* This is the "pathological" case referred to in a comment in
3121 print_frame_info. It might be better to move this check into
3126 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
3128 /* If we never found a PDR for this function in symbol reading, then
3129 examine prologues to find the information. */
3132 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
3133 if (PROC_FRAME_REG (proc_desc
) == -1)
3143 static mips_extra_func_info_t
3144 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
)
3146 mips_extra_func_info_t proc_desc
;
3147 CORE_ADDR startaddr
= 0;
3149 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
3150 if (proc_desc
== NULL
)
3153 startaddr
= heuristic_proc_start (pc
);
3155 proc_desc
= heuristic_proc_desc (startaddr
, pc
, next_frame
);
3160 /* MIPS stack frames are almost impenetrable. When execution stops,
3161 we basically have to look at symbol information for the function
3162 that we stopped in, which tells us *which* register (if any) is
3163 the base of the frame pointer, and what offset from that register
3164 the frame itself is at.
3166 This presents a problem when trying to examine a stack in memory
3167 (that isn't executing at the moment), using the "frame" command. We
3168 don't have a PC, nor do we have any registers except SP.
3170 This routine takes two arguments, SP and PC, and tries to make the
3171 cached frames look as if these two arguments defined a frame on the
3172 cache. This allows the rest of info frame to extract the important
3173 arguments without difficulty. */
3176 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
3179 error ("MIPS frame specifications require two arguments: sp and pc");
3181 return create_new_frame (argv
[0], argv
[1]);
3184 /* According to the current ABI, should the type be passed in a
3185 floating-point register (assuming that there is space)? When there
3186 is no FPU, FP are not even considered as possibile candidates for
3187 FP registers and, consequently this returns false - forces FP
3188 arguments into integer registers. */
3191 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
3193 return ((typecode
== TYPE_CODE_FLT
3195 && (typecode
== TYPE_CODE_STRUCT
3196 || typecode
== TYPE_CODE_UNION
)
3197 && TYPE_NFIELDS (arg_type
) == 1
3198 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
3199 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
3202 /* On o32, argument passing in GPRs depends on the alignment of the type being
3203 passed. Return 1 if this type must be aligned to a doubleword boundary. */
3206 mips_type_needs_double_align (struct type
*type
)
3208 enum type_code typecode
= TYPE_CODE (type
);
3210 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
3212 else if (typecode
== TYPE_CODE_STRUCT
)
3214 if (TYPE_NFIELDS (type
) < 1)
3216 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
3218 else if (typecode
== TYPE_CODE_UNION
)
3222 n
= TYPE_NFIELDS (type
);
3223 for (i
= 0; i
< n
; i
++)
3224 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3231 /* Adjust the address downward (direction of stack growth) so that it
3232 is correctly aligned for a new stack frame. */
3234 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3236 return align_down (addr
, 16);
3239 /* Determine how a return value is stored within the MIPS register
3240 file, given the return type `valtype'. */
3242 struct return_value_word
3251 return_value_location (struct type
*valtype
,
3252 struct return_value_word
*hi
,
3253 struct return_value_word
*lo
)
3255 int len
= TYPE_LENGTH (valtype
);
3256 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3258 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3259 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3260 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3262 if (mips_abi_regsize (current_gdbarch
) < 8 && len
== 8)
3264 /* We need to break a 64bit float in two 32 bit halves and
3265 spread them across a floating-point register pair. */
3266 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3267 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
3268 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3269 && register_size (current_gdbarch
,
3270 mips_regnum (current_gdbarch
)->
3271 fp0
) == 8) ? 4 : 0);
3272 hi
->reg_offset
= lo
->reg_offset
;
3273 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 0;
3274 hi
->reg
= mips_regnum (current_gdbarch
)->fp0
+ 1;
3280 /* The floating point value fits in a single floating-point
3282 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3283 && register_size (current_gdbarch
,
3284 mips_regnum (current_gdbarch
)->
3286 && len
== 4) ? 4 : 0);
3287 lo
->reg
= mips_regnum (current_gdbarch
)->fp0
;
3298 /* Locate a result possibly spread across two registers. */
3300 lo
->reg
= regnum
+ 0;
3301 hi
->reg
= regnum
+ 1;
3302 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3303 && len
< mips_abi_regsize (current_gdbarch
))
3305 /* "un-left-justify" the value in the low register */
3306 lo
->reg_offset
= mips_abi_regsize (current_gdbarch
) - len
;
3311 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
&& len
> mips_abi_regsize (current_gdbarch
) /* odd-size structs */
3312 && len
< mips_abi_regsize (current_gdbarch
) * 2
3313 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3314 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3316 /* "un-left-justify" the value spread across two registers. */
3317 lo
->reg_offset
= 2 * mips_abi_regsize (current_gdbarch
) - len
;
3318 lo
->len
= mips_abi_regsize (current_gdbarch
) - lo
->reg_offset
;
3320 hi
->len
= len
- lo
->len
;
3324 /* Only perform a partial copy of the second register. */
3327 if (len
> mips_abi_regsize (current_gdbarch
))
3329 lo
->len
= mips_abi_regsize (current_gdbarch
);
3330 hi
->len
= len
- mips_abi_regsize (current_gdbarch
);
3338 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3339 && register_size (current_gdbarch
, regnum
) == 8
3340 && mips_abi_regsize (current_gdbarch
) == 4)
3342 /* Account for the fact that only the least-signficant part
3343 of the register is being used */
3344 lo
->reg_offset
+= 4;
3345 hi
->reg_offset
+= 4;
3348 hi
->buf_offset
= lo
->len
;
3352 /* Should call_function allocate stack space for a struct return? */
3355 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
3357 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3358 return (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (current_gdbarch
));
3361 /* Should call_function pass struct by reference?
3362 For each architecture, structs are passed either by
3363 value or by reference, depending on their size. */
3366 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
3368 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
3369 int len
= TYPE_LENGTH (check_typedef (type
));
3370 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3372 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
3373 return (len
> mips_abi_regsize (current_gdbarch
));
3379 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3380 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3381 int nargs
, struct value
**args
, CORE_ADDR sp
,
3382 int struct_return
, CORE_ADDR struct_addr
)
3388 int stack_offset
= 0;
3389 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3390 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3392 /* For shared libraries, "t9" needs to point at the function
3394 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3396 /* Set the return address register to point to the entry point of
3397 the program, where a breakpoint lies in wait. */
3398 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3400 /* First ensure that the stack and structure return address (if any)
3401 are properly aligned. The stack has to be at least 64-bit
3402 aligned even on 32-bit machines, because doubles must be 64-bit
3403 aligned. For n32 and n64, stack frames need to be 128-bit
3404 aligned, so we round to this widest known alignment. */
3406 sp
= align_down (sp
, 16);
3407 struct_addr
= align_down (struct_addr
, 16);
3409 /* Now make space on the stack for the args. We allocate more
3410 than necessary for EABI, because the first few arguments are
3411 passed in registers, but that's OK. */
3412 for (argnum
= 0; argnum
< nargs
; argnum
++)
3413 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3414 mips_stack_argsize (gdbarch
));
3415 sp
-= align_up (len
, 16);
3418 fprintf_unfiltered (gdb_stdlog
,
3419 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3420 paddr_nz (sp
), (long) align_up (len
, 16));
3422 /* Initialize the integer and float register pointers. */
3424 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3426 /* The struct_return pointer occupies the first parameter-passing reg. */
3430 fprintf_unfiltered (gdb_stdlog
,
3431 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3432 argreg
, paddr_nz (struct_addr
));
3433 write_register (argreg
++, struct_addr
);
3436 /* Now load as many as possible of the first arguments into
3437 registers, and push the rest onto the stack. Loop thru args
3438 from first to last. */
3439 for (argnum
= 0; argnum
< nargs
; argnum
++)
3442 char valbuf
[MAX_REGISTER_SIZE
];
3443 struct value
*arg
= args
[argnum
];
3444 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3445 int len
= TYPE_LENGTH (arg_type
);
3446 enum type_code typecode
= TYPE_CODE (arg_type
);
3449 fprintf_unfiltered (gdb_stdlog
,
3450 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3451 argnum
+ 1, len
, (int) typecode
);
3453 /* The EABI passes structures that do not fit in a register by
3455 if (len
> mips_abi_regsize (gdbarch
)
3456 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3458 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3459 VALUE_ADDRESS (arg
));
3460 typecode
= TYPE_CODE_PTR
;
3461 len
= mips_abi_regsize (gdbarch
);
3464 fprintf_unfiltered (gdb_stdlog
, " push");
3467 val
= (char *) VALUE_CONTENTS (arg
);
3469 /* 32-bit ABIs always start floating point arguments in an
3470 even-numbered floating point register. Round the FP register
3471 up before the check to see if there are any FP registers
3472 left. Non MIPS_EABI targets also pass the FP in the integer
3473 registers so also round up normal registers. */
3474 if (mips_abi_regsize (gdbarch
) < 8
3475 && fp_register_arg_p (typecode
, arg_type
))
3477 if ((float_argreg
& 1))
3481 /* Floating point arguments passed in registers have to be
3482 treated specially. On 32-bit architectures, doubles
3483 are passed in register pairs; the even register gets
3484 the low word, and the odd register gets the high word.
3485 On non-EABI processors, the first two floating point arguments are
3486 also copied to general registers, because MIPS16 functions
3487 don't use float registers for arguments. This duplication of
3488 arguments in general registers can't hurt non-MIPS16 functions
3489 because those registers are normally skipped. */
3490 /* MIPS_EABI squeezes a struct that contains a single floating
3491 point value into an FP register instead of pushing it onto the
3493 if (fp_register_arg_p (typecode
, arg_type
)
3494 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3496 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3498 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3499 unsigned long regval
;
3501 /* Write the low word of the double to the even register(s). */
3502 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3504 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3505 float_argreg
, phex (regval
, 4));
3506 write_register (float_argreg
++, regval
);
3508 /* Write the high word of the double to the odd register(s). */
3509 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3511 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3512 float_argreg
, phex (regval
, 4));
3513 write_register (float_argreg
++, regval
);
3517 /* This is a floating point value that fits entirely
3518 in a single register. */
3519 /* On 32 bit ABI's the float_argreg is further adjusted
3520 above to ensure that it is even register aligned. */
3521 LONGEST regval
= extract_unsigned_integer (val
, len
);
3523 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3524 float_argreg
, phex (regval
, len
));
3525 write_register (float_argreg
++, regval
);
3530 /* Copy the argument to general registers or the stack in
3531 register-sized pieces. Large arguments are split between
3532 registers and stack. */
3533 /* Note: structs whose size is not a multiple of
3534 mips_abi_regsize() are treated specially: Irix cc passes
3535 them in registers where gcc sometimes puts them on the
3536 stack. For maximum compatibility, we will put them in
3538 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3539 && (len
% mips_abi_regsize (gdbarch
) != 0));
3541 /* Note: Floating-point values that didn't fit into an FP
3542 register are only written to memory. */
3545 /* Remember if the argument was written to the stack. */
3546 int stack_used_p
= 0;
3547 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3548 ? len
: mips_abi_regsize (gdbarch
));
3551 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3554 /* Write this portion of the argument to the stack. */
3555 if (argreg
> MIPS_LAST_ARG_REGNUM
3557 || fp_register_arg_p (typecode
, arg_type
))
3559 /* Should shorter than int integer values be
3560 promoted to int before being stored? */
3561 int longword_offset
= 0;
3564 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3566 if (mips_stack_argsize (gdbarch
) == 8
3567 && (typecode
== TYPE_CODE_INT
3568 || typecode
== TYPE_CODE_PTR
3569 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3570 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3571 else if ((typecode
== TYPE_CODE_STRUCT
3572 || typecode
== TYPE_CODE_UNION
)
3573 && (TYPE_LENGTH (arg_type
)
3574 < mips_stack_argsize (gdbarch
)))
3575 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3580 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3581 paddr_nz (stack_offset
));
3582 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3583 paddr_nz (longword_offset
));
3586 addr
= sp
+ stack_offset
+ longword_offset
;
3591 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3593 for (i
= 0; i
< partial_len
; i
++)
3595 fprintf_unfiltered (gdb_stdlog
, "%02x",
3599 write_memory (addr
, val
, partial_len
);
3602 /* Note!!! This is NOT an else clause. Odd sized
3603 structs may go thru BOTH paths. Floating point
3604 arguments will not. */
3605 /* Write this portion of the argument to a general
3606 purpose register. */
3607 if (argreg
<= MIPS_LAST_ARG_REGNUM
3608 && !fp_register_arg_p (typecode
, arg_type
))
3611 extract_unsigned_integer (val
, partial_len
);
3614 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3617 mips_abi_regsize (gdbarch
)));
3618 write_register (argreg
, regval
);
3625 /* Compute the the offset into the stack at which we
3626 will copy the next parameter.
3628 In the new EABI (and the NABI32), the stack_offset
3629 only needs to be adjusted when it has been used. */
3632 stack_offset
+= align_up (partial_len
,
3633 mips_stack_argsize (gdbarch
));
3637 fprintf_unfiltered (gdb_stdlog
, "\n");
3640 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3642 /* Return adjusted stack pointer. */
3646 /* Given a return value in `regbuf' with a type `valtype', extract and
3647 copy its value into `valbuf'. */
3650 mips_eabi_extract_return_value (struct type
*valtype
,
3651 char regbuf
[], char *valbuf
)
3653 struct return_value_word lo
;
3654 struct return_value_word hi
;
3655 return_value_location (valtype
, &hi
, &lo
);
3657 memcpy (valbuf
+ lo
.buf_offset
,
3658 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
3659 lo
.reg_offset
, lo
.len
);
3662 memcpy (valbuf
+ hi
.buf_offset
,
3663 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
3664 hi
.reg_offset
, hi
.len
);
3667 /* Given a return value in `valbuf' with a type `valtype', write it's
3668 value into the appropriate register. */
3671 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
3673 char raw_buffer
[MAX_REGISTER_SIZE
];
3674 struct return_value_word lo
;
3675 struct return_value_word hi
;
3676 return_value_location (valtype
, &hi
, &lo
);
3678 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3679 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3680 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
3681 raw_buffer
, register_size (current_gdbarch
,
3686 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3687 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3688 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
3690 register_size (current_gdbarch
,
3695 /* N32/N64 ABI stuff. */
3698 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3699 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3700 int nargs
, struct value
**args
, CORE_ADDR sp
,
3701 int struct_return
, CORE_ADDR struct_addr
)
3707 int stack_offset
= 0;
3708 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3709 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3711 /* For shared libraries, "t9" needs to point at the function
3713 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
3715 /* Set the return address register to point to the entry point of
3716 the program, where a breakpoint lies in wait. */
3717 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
3719 /* First ensure that the stack and structure return address (if any)
3720 are properly aligned. The stack has to be at least 64-bit
3721 aligned even on 32-bit machines, because doubles must be 64-bit
3722 aligned. For n32 and n64, stack frames need to be 128-bit
3723 aligned, so we round to this widest known alignment. */
3725 sp
= align_down (sp
, 16);
3726 struct_addr
= align_down (struct_addr
, 16);
3728 /* Now make space on the stack for the args. */
3729 for (argnum
= 0; argnum
< nargs
; argnum
++)
3730 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3731 mips_stack_argsize (gdbarch
));
3732 sp
-= align_up (len
, 16);
3735 fprintf_unfiltered (gdb_stdlog
,
3736 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3737 paddr_nz (sp
), (long) align_up (len
, 16));
3739 /* Initialize the integer and float register pointers. */
3741 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3743 /* The struct_return pointer occupies the first parameter-passing reg. */
3747 fprintf_unfiltered (gdb_stdlog
,
3748 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3749 argreg
, paddr_nz (struct_addr
));
3750 write_register (argreg
++, struct_addr
);
3753 /* Now load as many as possible of the first arguments into
3754 registers, and push the rest onto the stack. Loop thru args
3755 from first to last. */
3756 for (argnum
= 0; argnum
< nargs
; argnum
++)
3759 struct value
*arg
= args
[argnum
];
3760 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3761 int len
= TYPE_LENGTH (arg_type
);
3762 enum type_code typecode
= TYPE_CODE (arg_type
);
3765 fprintf_unfiltered (gdb_stdlog
,
3766 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3767 argnum
+ 1, len
, (int) typecode
);
3769 val
= (char *) VALUE_CONTENTS (arg
);
3771 if (fp_register_arg_p (typecode
, arg_type
)
3772 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3774 /* This is a floating point value that fits entirely
3775 in a single register. */
3776 /* On 32 bit ABI's the float_argreg is further adjusted
3777 above to ensure that it is even register aligned. */
3778 LONGEST regval
= extract_unsigned_integer (val
, len
);
3780 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3781 float_argreg
, phex (regval
, len
));
3782 write_register (float_argreg
++, regval
);
3785 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3786 argreg
, phex (regval
, len
));
3787 write_register (argreg
, regval
);
3792 /* Copy the argument to general registers or the stack in
3793 register-sized pieces. Large arguments are split between
3794 registers and stack. */
3795 /* Note: structs whose size is not a multiple of
3796 mips_abi_regsize() are treated specially: Irix cc passes
3797 them in registers where gcc sometimes puts them on the
3798 stack. For maximum compatibility, we will put them in
3800 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3801 && (len
% mips_abi_regsize (gdbarch
) != 0));
3802 /* Note: Floating-point values that didn't fit into an FP
3803 register are only written to memory. */
3806 /* Rememer if the argument was written to the stack. */
3807 int stack_used_p
= 0;
3808 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3809 ? len
: mips_abi_regsize (gdbarch
));
3812 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3815 /* Write this portion of the argument to the stack. */
3816 if (argreg
> MIPS_LAST_ARG_REGNUM
3818 || fp_register_arg_p (typecode
, arg_type
))
3820 /* Should shorter than int integer values be
3821 promoted to int before being stored? */
3822 int longword_offset
= 0;
3825 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3827 if (mips_stack_argsize (gdbarch
) == 8
3828 && (typecode
== TYPE_CODE_INT
3829 || typecode
== TYPE_CODE_PTR
3830 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3831 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3836 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3837 paddr_nz (stack_offset
));
3838 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3839 paddr_nz (longword_offset
));
3842 addr
= sp
+ stack_offset
+ longword_offset
;
3847 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3849 for (i
= 0; i
< partial_len
; i
++)
3851 fprintf_unfiltered (gdb_stdlog
, "%02x",
3855 write_memory (addr
, val
, partial_len
);
3858 /* Note!!! This is NOT an else clause. Odd sized
3859 structs may go thru BOTH paths. Floating point
3860 arguments will not. */
3861 /* Write this portion of the argument to a general
3862 purpose register. */
3863 if (argreg
<= MIPS_LAST_ARG_REGNUM
3864 && !fp_register_arg_p (typecode
, arg_type
))
3867 extract_unsigned_integer (val
, partial_len
);
3869 /* A non-floating-point argument being passed in a
3870 general register. If a struct or union, and if
3871 the remaining length is smaller than the register
3872 size, we have to adjust the register value on
3875 It does not seem to be necessary to do the
3876 same for integral types.
3878 cagney/2001-07-23: gdb/179: Also, GCC, when
3879 outputting LE O32 with sizeof (struct) <
3880 mips_abi_regsize(), generates a left shift as
3881 part of storing the argument in a register a
3882 register (the left shift isn't generated when
3883 sizeof (struct) >= mips_abi_regsize()). Since
3884 it is quite possible that this is GCC
3885 contradicting the LE/O32 ABI, GDB has not been
3886 adjusted to accommodate this. Either someone
3887 needs to demonstrate that the LE/O32 ABI
3888 specifies such a left shift OR this new ABI gets
3889 identified as such and GDB gets tweaked
3892 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3893 && partial_len
< mips_abi_regsize (gdbarch
)
3894 && (typecode
== TYPE_CODE_STRUCT
||
3895 typecode
== TYPE_CODE_UNION
))
3896 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3900 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3903 mips_abi_regsize (gdbarch
)));
3904 write_register (argreg
, regval
);
3911 /* Compute the the offset into the stack at which we
3912 will copy the next parameter.
3914 In N32 (N64?), the stack_offset only needs to be
3915 adjusted when it has been used. */
3918 stack_offset
+= align_up (partial_len
,
3919 mips_stack_argsize (gdbarch
));
3923 fprintf_unfiltered (gdb_stdlog
, "\n");
3926 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3928 /* Return adjusted stack pointer. */
3932 static enum return_value_convention
3933 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3934 struct type
*type
, struct regcache
*regcache
,
3935 void *readbuf
, const void *writebuf
)
3937 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3938 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3939 || TYPE_CODE (type
) == TYPE_CODE_UNION
3940 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3941 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3942 return RETURN_VALUE_STRUCT_CONVENTION
;
3943 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3944 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3946 /* A floating-point value belongs in the least significant part
3949 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3950 mips_xfer_register (regcache
,
3951 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3953 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3954 return RETURN_VALUE_REGISTER_CONVENTION
;
3956 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3957 && TYPE_NFIELDS (type
) <= 2
3958 && TYPE_NFIELDS (type
) >= 1
3959 && ((TYPE_NFIELDS (type
) == 1
3960 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3962 || (TYPE_NFIELDS (type
) == 2
3963 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3965 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3967 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3969 /* A struct that contains one or two floats. Each value is part
3970 in the least significant part of their floating point
3974 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3975 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3977 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3980 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3982 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3983 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3984 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3986 return RETURN_VALUE_REGISTER_CONVENTION
;
3988 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3989 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3991 /* A structure or union. Extract the left justified value,
3992 regardless of the byte order. I.e. DO NOT USE
3996 for (offset
= 0, regnum
= V0_REGNUM
;
3997 offset
< TYPE_LENGTH (type
);
3998 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4000 int xfer
= register_size (current_gdbarch
, regnum
);
4001 if (offset
+ xfer
> TYPE_LENGTH (type
))
4002 xfer
= TYPE_LENGTH (type
) - offset
;
4004 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4005 offset
, xfer
, regnum
);
4006 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4007 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4009 return RETURN_VALUE_REGISTER_CONVENTION
;
4013 /* A scalar extract each part but least-significant-byte
4017 for (offset
= 0, regnum
= V0_REGNUM
;
4018 offset
< TYPE_LENGTH (type
);
4019 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4021 int xfer
= register_size (current_gdbarch
, regnum
);
4022 if (offset
+ xfer
> TYPE_LENGTH (type
))
4023 xfer
= TYPE_LENGTH (type
) - offset
;
4025 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4026 offset
, xfer
, regnum
);
4027 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4028 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4030 return RETURN_VALUE_REGISTER_CONVENTION
;
4034 /* O32 ABI stuff. */
4037 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4038 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4039 int nargs
, struct value
**args
, CORE_ADDR sp
,
4040 int struct_return
, CORE_ADDR struct_addr
)
4046 int stack_offset
= 0;
4047 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4048 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4050 /* For shared libraries, "t9" needs to point at the function
4052 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4054 /* Set the return address register to point to the entry point of
4055 the program, where a breakpoint lies in wait. */
4056 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4058 /* First ensure that the stack and structure return address (if any)
4059 are properly aligned. The stack has to be at least 64-bit
4060 aligned even on 32-bit machines, because doubles must be 64-bit
4061 aligned. For n32 and n64, stack frames need to be 128-bit
4062 aligned, so we round to this widest known alignment. */
4064 sp
= align_down (sp
, 16);
4065 struct_addr
= align_down (struct_addr
, 16);
4067 /* Now make space on the stack for the args. */
4068 for (argnum
= 0; argnum
< nargs
; argnum
++)
4069 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4070 mips_stack_argsize (gdbarch
));
4071 sp
-= align_up (len
, 16);
4074 fprintf_unfiltered (gdb_stdlog
,
4075 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
4076 paddr_nz (sp
), (long) align_up (len
, 16));
4078 /* Initialize the integer and float register pointers. */
4080 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4082 /* The struct_return pointer occupies the first parameter-passing reg. */
4086 fprintf_unfiltered (gdb_stdlog
,
4087 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
4088 argreg
, paddr_nz (struct_addr
));
4089 write_register (argreg
++, struct_addr
);
4090 stack_offset
+= mips_stack_argsize (gdbarch
);
4093 /* Now load as many as possible of the first arguments into
4094 registers, and push the rest onto the stack. Loop thru args
4095 from first to last. */
4096 for (argnum
= 0; argnum
< nargs
; argnum
++)
4099 struct value
*arg
= args
[argnum
];
4100 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4101 int len
= TYPE_LENGTH (arg_type
);
4102 enum type_code typecode
= TYPE_CODE (arg_type
);
4105 fprintf_unfiltered (gdb_stdlog
,
4106 "mips_o32_push_dummy_call: %d len=%d type=%d",
4107 argnum
+ 1, len
, (int) typecode
);
4109 val
= (char *) VALUE_CONTENTS (arg
);
4111 /* 32-bit ABIs always start floating point arguments in an
4112 even-numbered floating point register. Round the FP register
4113 up before the check to see if there are any FP registers
4114 left. O32/O64 targets also pass the FP in the integer
4115 registers so also round up normal registers. */
4116 if (mips_abi_regsize (gdbarch
) < 8
4117 && fp_register_arg_p (typecode
, arg_type
))
4119 if ((float_argreg
& 1))
4123 /* Floating point arguments passed in registers have to be
4124 treated specially. On 32-bit architectures, doubles
4125 are passed in register pairs; the even register gets
4126 the low word, and the odd register gets the high word.
4127 On O32/O64, the first two floating point arguments are
4128 also copied to general registers, because MIPS16 functions
4129 don't use float registers for arguments. This duplication of
4130 arguments in general registers can't hurt non-MIPS16 functions
4131 because those registers are normally skipped. */
4133 if (fp_register_arg_p (typecode
, arg_type
)
4134 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4136 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4138 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4139 unsigned long regval
;
4141 /* Write the low word of the double to the even register(s). */
4142 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4144 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4145 float_argreg
, phex (regval
, 4));
4146 write_register (float_argreg
++, regval
);
4148 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4149 argreg
, phex (regval
, 4));
4150 write_register (argreg
++, regval
);
4152 /* Write the high word of the double to the odd register(s). */
4153 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4155 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4156 float_argreg
, phex (regval
, 4));
4157 write_register (float_argreg
++, regval
);
4160 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4161 argreg
, phex (regval
, 4));
4162 write_register (argreg
++, regval
);
4166 /* This is a floating point value that fits entirely
4167 in a single register. */
4168 /* On 32 bit ABI's the float_argreg is further adjusted
4169 above to ensure that it is even register aligned. */
4170 LONGEST regval
= extract_unsigned_integer (val
, len
);
4172 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4173 float_argreg
, phex (regval
, len
));
4174 write_register (float_argreg
++, regval
);
4175 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4176 registers for each argument. The below is (my
4177 guess) to ensure that the corresponding integer
4178 register has reserved the same space. */
4180 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4181 argreg
, phex (regval
, len
));
4182 write_register (argreg
, regval
);
4183 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4185 /* Reserve space for the FP register. */
4186 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4190 /* Copy the argument to general registers or the stack in
4191 register-sized pieces. Large arguments are split between
4192 registers and stack. */
4193 /* Note: structs whose size is not a multiple of
4194 mips_abi_regsize() are treated specially: Irix cc passes
4195 them in registers where gcc sometimes puts them on the
4196 stack. For maximum compatibility, we will put them in
4198 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4199 && (len
% mips_abi_regsize (gdbarch
) != 0));
4200 /* Structures should be aligned to eight bytes (even arg registers)
4201 on MIPS_ABI_O32, if their first member has double precision. */
4202 if (mips_abi_regsize (gdbarch
) < 8
4203 && mips_type_needs_double_align (arg_type
))
4208 /* Note: Floating-point values that didn't fit into an FP
4209 register are only written to memory. */
4212 /* Remember if the argument was written to the stack. */
4213 int stack_used_p
= 0;
4214 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4215 ? len
: mips_abi_regsize (gdbarch
));
4218 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4221 /* Write this portion of the argument to the stack. */
4222 if (argreg
> MIPS_LAST_ARG_REGNUM
4224 || fp_register_arg_p (typecode
, arg_type
))
4226 /* Should shorter than int integer values be
4227 promoted to int before being stored? */
4228 int longword_offset
= 0;
4231 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4233 if (mips_stack_argsize (gdbarch
) == 8
4234 && (typecode
== TYPE_CODE_INT
4235 || typecode
== TYPE_CODE_PTR
4236 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4237 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4242 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4243 paddr_nz (stack_offset
));
4244 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4245 paddr_nz (longword_offset
));
4248 addr
= sp
+ stack_offset
+ longword_offset
;
4253 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4255 for (i
= 0; i
< partial_len
; i
++)
4257 fprintf_unfiltered (gdb_stdlog
, "%02x",
4261 write_memory (addr
, val
, partial_len
);
4264 /* Note!!! This is NOT an else clause. Odd sized
4265 structs may go thru BOTH paths. Floating point
4266 arguments will not. */
4267 /* Write this portion of the argument to a general
4268 purpose register. */
4269 if (argreg
<= MIPS_LAST_ARG_REGNUM
4270 && !fp_register_arg_p (typecode
, arg_type
))
4272 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4273 /* Value may need to be sign extended, because
4274 mips_isa_regsize() != mips_abi_regsize(). */
4276 /* A non-floating-point argument being passed in a
4277 general register. If a struct or union, and if
4278 the remaining length is smaller than the register
4279 size, we have to adjust the register value on
4282 It does not seem to be necessary to do the
4283 same for integral types.
4285 Also don't do this adjustment on O64 binaries.
4287 cagney/2001-07-23: gdb/179: Also, GCC, when
4288 outputting LE O32 with sizeof (struct) <
4289 mips_abi_regsize(), generates a left shift as
4290 part of storing the argument in a register a
4291 register (the left shift isn't generated when
4292 sizeof (struct) >= mips_abi_regsize()). Since
4293 it is quite possible that this is GCC
4294 contradicting the LE/O32 ABI, GDB has not been
4295 adjusted to accommodate this. Either someone
4296 needs to demonstrate that the LE/O32 ABI
4297 specifies such a left shift OR this new ABI gets
4298 identified as such and GDB gets tweaked
4301 if (mips_abi_regsize (gdbarch
) < 8
4302 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4303 && partial_len
< mips_abi_regsize (gdbarch
)
4304 && (typecode
== TYPE_CODE_STRUCT
||
4305 typecode
== TYPE_CODE_UNION
))
4306 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4310 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4313 mips_abi_regsize (gdbarch
)));
4314 write_register (argreg
, regval
);
4317 /* Prevent subsequent floating point arguments from
4318 being passed in floating point registers. */
4319 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4325 /* Compute the the offset into the stack at which we
4326 will copy the next parameter.
4328 In older ABIs, the caller reserved space for
4329 registers that contained arguments. This was loosely
4330 refered to as their "home". Consequently, space is
4331 always allocated. */
4333 stack_offset
+= align_up (partial_len
,
4334 mips_stack_argsize (gdbarch
));
4338 fprintf_unfiltered (gdb_stdlog
, "\n");
4341 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4343 /* Return adjusted stack pointer. */
4347 static enum return_value_convention
4348 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
4349 struct regcache
*regcache
,
4350 void *readbuf
, const void *writebuf
)
4352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4354 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4355 || TYPE_CODE (type
) == TYPE_CODE_UNION
4356 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4357 return RETURN_VALUE_STRUCT_CONVENTION
;
4358 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4359 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4361 /* A single-precision floating-point value. It fits in the
4362 least significant part of FP0. */
4364 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4365 mips_xfer_register (regcache
,
4366 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
4368 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4369 return RETURN_VALUE_REGISTER_CONVENTION
;
4371 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4372 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4374 /* A double-precision floating-point value. The most
4375 significant part goes in FP1, and the least significant in
4378 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4379 switch (TARGET_BYTE_ORDER
)
4381 case BFD_ENDIAN_LITTLE
:
4382 mips_xfer_register (regcache
,
4383 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4384 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4385 mips_xfer_register (regcache
,
4386 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4387 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4389 case BFD_ENDIAN_BIG
:
4390 mips_xfer_register (regcache
,
4391 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4392 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
4393 mips_xfer_register (regcache
,
4394 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
4395 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
4398 internal_error (__FILE__
, __LINE__
, "bad switch");
4400 return RETURN_VALUE_REGISTER_CONVENTION
;
4403 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4404 && TYPE_NFIELDS (type
) <= 2
4405 && TYPE_NFIELDS (type
) >= 1
4406 && ((TYPE_NFIELDS (type
) == 1
4407 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4409 || (TYPE_NFIELDS (type
) == 2
4410 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4412 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4414 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4416 /* A struct that contains one or two floats. Each value is part
4417 in the least significant part of their floating point
4419 bfd_byte reg
[MAX_REGISTER_SIZE
];
4422 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
4423 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4425 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4428 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4430 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4431 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4432 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4434 return RETURN_VALUE_REGISTER_CONVENTION
;
4438 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4439 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4441 /* A structure or union. Extract the left justified value,
4442 regardless of the byte order. I.e. DO NOT USE
4446 for (offset
= 0, regnum
= V0_REGNUM
;
4447 offset
< TYPE_LENGTH (type
);
4448 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4450 int xfer
= register_size (current_gdbarch
, regnum
);
4451 if (offset
+ xfer
> TYPE_LENGTH (type
))
4452 xfer
= TYPE_LENGTH (type
) - offset
;
4454 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4455 offset
, xfer
, regnum
);
4456 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4457 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4459 return RETURN_VALUE_REGISTER_CONVENTION
;
4464 /* A scalar extract each part but least-significant-byte
4465 justified. o32 thinks registers are 4 byte, regardless of
4466 the ISA. mips_stack_argsize controls this. */
4469 for (offset
= 0, regnum
= V0_REGNUM
;
4470 offset
< TYPE_LENGTH (type
);
4471 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4473 int xfer
= mips_stack_argsize (gdbarch
);
4474 if (offset
+ xfer
> TYPE_LENGTH (type
))
4475 xfer
= TYPE_LENGTH (type
) - offset
;
4477 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4478 offset
, xfer
, regnum
);
4479 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4480 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4482 return RETURN_VALUE_REGISTER_CONVENTION
;
4486 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4490 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4491 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4493 struct value
**args
, CORE_ADDR sp
,
4494 int struct_return
, CORE_ADDR struct_addr
)
4500 int stack_offset
= 0;
4501 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4502 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4504 /* For shared libraries, "t9" needs to point at the function
4506 regcache_cooked_write_signed (regcache
, T9_REGNUM
, func_addr
);
4508 /* Set the return address register to point to the entry point of
4509 the program, where a breakpoint lies in wait. */
4510 regcache_cooked_write_signed (regcache
, RA_REGNUM
, bp_addr
);
4512 /* First ensure that the stack and structure return address (if any)
4513 are properly aligned. The stack has to be at least 64-bit
4514 aligned even on 32-bit machines, because doubles must be 64-bit
4515 aligned. For n32 and n64, stack frames need to be 128-bit
4516 aligned, so we round to this widest known alignment. */
4518 sp
= align_down (sp
, 16);
4519 struct_addr
= align_down (struct_addr
, 16);
4521 /* Now make space on the stack for the args. */
4522 for (argnum
= 0; argnum
< nargs
; argnum
++)
4523 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4524 mips_stack_argsize (gdbarch
));
4525 sp
-= align_up (len
, 16);
4528 fprintf_unfiltered (gdb_stdlog
,
4529 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4530 paddr_nz (sp
), (long) align_up (len
, 16));
4532 /* Initialize the integer and float register pointers. */
4534 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4536 /* The struct_return pointer occupies the first parameter-passing reg. */
4540 fprintf_unfiltered (gdb_stdlog
,
4541 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4542 argreg
, paddr_nz (struct_addr
));
4543 write_register (argreg
++, struct_addr
);
4544 stack_offset
+= mips_stack_argsize (gdbarch
);
4547 /* Now load as many as possible of the first arguments into
4548 registers, and push the rest onto the stack. Loop thru args
4549 from first to last. */
4550 for (argnum
= 0; argnum
< nargs
; argnum
++)
4553 struct value
*arg
= args
[argnum
];
4554 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4555 int len
= TYPE_LENGTH (arg_type
);
4556 enum type_code typecode
= TYPE_CODE (arg_type
);
4559 fprintf_unfiltered (gdb_stdlog
,
4560 "mips_o64_push_dummy_call: %d len=%d type=%d",
4561 argnum
+ 1, len
, (int) typecode
);
4563 val
= (char *) VALUE_CONTENTS (arg
);
4565 /* 32-bit ABIs always start floating point arguments in an
4566 even-numbered floating point register. Round the FP register
4567 up before the check to see if there are any FP registers
4568 left. O32/O64 targets also pass the FP in the integer
4569 registers so also round up normal registers. */
4570 if (mips_abi_regsize (gdbarch
) < 8
4571 && fp_register_arg_p (typecode
, arg_type
))
4573 if ((float_argreg
& 1))
4577 /* Floating point arguments passed in registers have to be
4578 treated specially. On 32-bit architectures, doubles
4579 are passed in register pairs; the even register gets
4580 the low word, and the odd register gets the high word.
4581 On O32/O64, the first two floating point arguments are
4582 also copied to general registers, because MIPS16 functions
4583 don't use float registers for arguments. This duplication of
4584 arguments in general registers can't hurt non-MIPS16 functions
4585 because those registers are normally skipped. */
4587 if (fp_register_arg_p (typecode
, arg_type
)
4588 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4590 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4592 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4593 unsigned long regval
;
4595 /* Write the low word of the double to the even register(s). */
4596 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4598 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4599 float_argreg
, phex (regval
, 4));
4600 write_register (float_argreg
++, regval
);
4602 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4603 argreg
, phex (regval
, 4));
4604 write_register (argreg
++, regval
);
4606 /* Write the high word of the double to the odd register(s). */
4607 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4609 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4610 float_argreg
, phex (regval
, 4));
4611 write_register (float_argreg
++, regval
);
4614 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4615 argreg
, phex (regval
, 4));
4616 write_register (argreg
++, regval
);
4620 /* This is a floating point value that fits entirely
4621 in a single register. */
4622 /* On 32 bit ABI's the float_argreg is further adjusted
4623 above to ensure that it is even register aligned. */
4624 LONGEST regval
= extract_unsigned_integer (val
, len
);
4626 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4627 float_argreg
, phex (regval
, len
));
4628 write_register (float_argreg
++, regval
);
4629 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4630 registers for each argument. The below is (my
4631 guess) to ensure that the corresponding integer
4632 register has reserved the same space. */
4634 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4635 argreg
, phex (regval
, len
));
4636 write_register (argreg
, regval
);
4637 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4639 /* Reserve space for the FP register. */
4640 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4644 /* Copy the argument to general registers or the stack in
4645 register-sized pieces. Large arguments are split between
4646 registers and stack. */
4647 /* Note: structs whose size is not a multiple of
4648 mips_abi_regsize() are treated specially: Irix cc passes
4649 them in registers where gcc sometimes puts them on the
4650 stack. For maximum compatibility, we will put them in
4652 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4653 && (len
% mips_abi_regsize (gdbarch
) != 0));
4654 /* Structures should be aligned to eight bytes (even arg registers)
4655 on MIPS_ABI_O32, if their first member has double precision. */
4656 if (mips_abi_regsize (gdbarch
) < 8
4657 && mips_type_needs_double_align (arg_type
))
4662 /* Note: Floating-point values that didn't fit into an FP
4663 register are only written to memory. */
4666 /* Remember if the argument was written to the stack. */
4667 int stack_used_p
= 0;
4668 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4669 ? len
: mips_abi_regsize (gdbarch
));
4672 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4675 /* Write this portion of the argument to the stack. */
4676 if (argreg
> MIPS_LAST_ARG_REGNUM
4678 || fp_register_arg_p (typecode
, arg_type
))
4680 /* Should shorter than int integer values be
4681 promoted to int before being stored? */
4682 int longword_offset
= 0;
4685 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4687 if (mips_stack_argsize (gdbarch
) == 8
4688 && (typecode
== TYPE_CODE_INT
4689 || typecode
== TYPE_CODE_PTR
4690 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4691 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4696 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4697 paddr_nz (stack_offset
));
4698 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4699 paddr_nz (longword_offset
));
4702 addr
= sp
+ stack_offset
+ longword_offset
;
4707 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4709 for (i
= 0; i
< partial_len
; i
++)
4711 fprintf_unfiltered (gdb_stdlog
, "%02x",
4715 write_memory (addr
, val
, partial_len
);
4718 /* Note!!! This is NOT an else clause. Odd sized
4719 structs may go thru BOTH paths. Floating point
4720 arguments will not. */
4721 /* Write this portion of the argument to a general
4722 purpose register. */
4723 if (argreg
<= MIPS_LAST_ARG_REGNUM
4724 && !fp_register_arg_p (typecode
, arg_type
))
4726 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4727 /* Value may need to be sign extended, because
4728 mips_isa_regsize() != mips_abi_regsize(). */
4730 /* A non-floating-point argument being passed in a
4731 general register. If a struct or union, and if
4732 the remaining length is smaller than the register
4733 size, we have to adjust the register value on
4736 It does not seem to be necessary to do the
4737 same for integral types.
4739 Also don't do this adjustment on O64 binaries.
4741 cagney/2001-07-23: gdb/179: Also, GCC, when
4742 outputting LE O32 with sizeof (struct) <
4743 mips_abi_regsize(), generates a left shift as
4744 part of storing the argument in a register a
4745 register (the left shift isn't generated when
4746 sizeof (struct) >= mips_abi_regsize()). Since
4747 it is quite possible that this is GCC
4748 contradicting the LE/O32 ABI, GDB has not been
4749 adjusted to accommodate this. Either someone
4750 needs to demonstrate that the LE/O32 ABI
4751 specifies such a left shift OR this new ABI gets
4752 identified as such and GDB gets tweaked
4755 if (mips_abi_regsize (gdbarch
) < 8
4756 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4757 && partial_len
< mips_abi_regsize (gdbarch
)
4758 && (typecode
== TYPE_CODE_STRUCT
||
4759 typecode
== TYPE_CODE_UNION
))
4760 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4764 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4767 mips_abi_regsize (gdbarch
)));
4768 write_register (argreg
, regval
);
4771 /* Prevent subsequent floating point arguments from
4772 being passed in floating point registers. */
4773 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4779 /* Compute the the offset into the stack at which we
4780 will copy the next parameter.
4782 In older ABIs, the caller reserved space for
4783 registers that contained arguments. This was loosely
4784 refered to as their "home". Consequently, space is
4785 always allocated. */
4787 stack_offset
+= align_up (partial_len
,
4788 mips_stack_argsize (gdbarch
));
4792 fprintf_unfiltered (gdb_stdlog
, "\n");
4795 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4797 /* Return adjusted stack pointer. */
4802 mips_o64_extract_return_value (struct type
*valtype
,
4803 char regbuf
[], char *valbuf
)
4805 struct return_value_word lo
;
4806 struct return_value_word hi
;
4807 return_value_location (valtype
, &hi
, &lo
);
4809 memcpy (valbuf
+ lo
.buf_offset
,
4810 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ lo
.reg
) +
4811 lo
.reg_offset
, lo
.len
);
4814 memcpy (valbuf
+ hi
.buf_offset
,
4815 regbuf
+ DEPRECATED_REGISTER_BYTE (NUM_REGS
+ hi
.reg
) +
4816 hi
.reg_offset
, hi
.len
);
4820 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4822 char raw_buffer
[MAX_REGISTER_SIZE
];
4823 struct return_value_word lo
;
4824 struct return_value_word hi
;
4825 return_value_location (valtype
, &hi
, &lo
);
4827 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4828 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4829 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (lo
.reg
),
4830 raw_buffer
, register_size (current_gdbarch
,
4835 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4836 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4837 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (hi
.reg
),
4839 register_size (current_gdbarch
,
4844 /* Floating point register management.
4846 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4847 64bit operations, these early MIPS cpus treat fp register pairs
4848 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4849 registers and offer a compatibility mode that emulates the MIPS2 fp
4850 model. When operating in MIPS2 fp compat mode, later cpu's split
4851 double precision floats into two 32-bit chunks and store them in
4852 consecutive fp regs. To display 64-bit floats stored in this
4853 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4854 Throw in user-configurable endianness and you have a real mess.
4856 The way this works is:
4857 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4858 double-precision value will be split across two logical registers.
4859 The lower-numbered logical register will hold the low-order bits,
4860 regardless of the processor's endianness.
4861 - If we are on a 64-bit processor, and we are looking for a
4862 single-precision value, it will be in the low ordered bits
4863 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4864 save slot in memory.
4865 - If we are in 64-bit mode, everything is straightforward.
4867 Note that this code only deals with "live" registers at the top of the
4868 stack. We will attempt to deal with saved registers later, when
4869 the raw/cooked register interface is in place. (We need a general
4870 interface that can deal with dynamic saved register sizes -- fp
4871 regs could be 32 bits wide in one frame and 64 on the frame above
4874 static struct type
*
4875 mips_float_register_type (void)
4877 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4878 return builtin_type_ieee_single_big
;
4880 return builtin_type_ieee_single_little
;
4883 static struct type
*
4884 mips_double_register_type (void)
4886 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4887 return builtin_type_ieee_double_big
;
4889 return builtin_type_ieee_double_little
;
4892 /* Copy a 32-bit single-precision value from the current frame
4893 into rare_buffer. */
4896 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4899 int raw_size
= register_size (current_gdbarch
, regno
);
4900 char *raw_buffer
= alloca (raw_size
);
4902 if (!frame_register_read (frame
, regno
, raw_buffer
))
4903 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4906 /* We have a 64-bit value for this register. Find the low-order
4910 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4915 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4919 memcpy (rare_buffer
, raw_buffer
, 4);
4923 /* Copy a 64-bit double-precision value from the current frame into
4924 rare_buffer. This may include getting half of it from the next
4928 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4931 int raw_size
= register_size (current_gdbarch
, regno
);
4933 if (raw_size
== 8 && !mips2_fp_compat ())
4935 /* We have a 64-bit value for this register, and we should use
4937 if (!frame_register_read (frame
, regno
, rare_buffer
))
4938 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4942 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4943 internal_error (__FILE__
, __LINE__
,
4944 "mips_read_fp_register_double: bad access to "
4945 "odd-numbered FP register");
4947 /* mips_read_fp_register_single will find the correct 32 bits from
4949 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4951 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4952 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4956 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4957 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4963 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4965 { /* do values for FP (float) regs */
4967 double doub
, flt1
; /* doubles extracted from raw hex data */
4971 (char *) alloca (2 *
4972 register_size (current_gdbarch
,
4973 mips_regnum (current_gdbarch
)->fp0
));
4975 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4976 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4979 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4981 /* 4-byte registers: Print hex and floating. Also print even
4982 numbered registers as doubles. */
4983 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4984 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4986 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4989 fprintf_filtered (file
, " flt: ");
4991 fprintf_filtered (file
, " <invalid float> ");
4993 fprintf_filtered (file
, "%-17.9g", flt1
);
4995 if (regnum
% 2 == 0)
4997 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4998 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
5001 fprintf_filtered (file
, " dbl: ");
5003 fprintf_filtered (file
, "<invalid double>");
5005 fprintf_filtered (file
, "%-24.17g", doub
);
5010 /* Eight byte registers: print each one as hex, float and double. */
5011 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
5012 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
5014 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
5015 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
5018 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
5021 fprintf_filtered (file
, " flt: ");
5023 fprintf_filtered (file
, "<invalid float>");
5025 fprintf_filtered (file
, "%-17.9g", flt1
);
5027 fprintf_filtered (file
, " dbl: ");
5029 fprintf_filtered (file
, "<invalid double>");
5031 fprintf_filtered (file
, "%-24.17g", doub
);
5036 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
5037 int regnum
, int all
)
5039 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5040 char raw_buffer
[MAX_REGISTER_SIZE
];
5043 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
5045 mips_print_fp_register (file
, frame
, regnum
);
5049 /* Get the data in raw format. */
5050 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5052 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
5056 fputs_filtered (REGISTER_NAME (regnum
), file
);
5058 /* The problem with printing numeric register names (r26, etc.) is that
5059 the user can't use them on input. Probably the best solution is to
5060 fix it so that either the numeric or the funky (a2, etc.) names
5061 are accepted on input. */
5062 if (regnum
< MIPS_NUMREGS
)
5063 fprintf_filtered (file
, "(r%d): ", regnum
);
5065 fprintf_filtered (file
, ": ");
5067 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5069 register_size (current_gdbarch
,
5070 regnum
) - register_size (current_gdbarch
, regnum
);
5074 print_scalar_formatted (raw_buffer
+ offset
,
5075 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
5079 /* Replacement for generic do_registers_info.
5080 Print regs in pretty columns. */
5083 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5086 fprintf_filtered (file
, " ");
5087 mips_print_fp_register (file
, frame
, regnum
);
5088 fprintf_filtered (file
, "\n");
5093 /* Print a row's worth of GP (int) registers, with name labels above */
5096 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5099 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5100 /* do values for GP (int) regs */
5101 char raw_buffer
[MAX_REGISTER_SIZE
];
5102 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
5106 /* For GP registers, we print a separate row of names above the vals */
5107 fprintf_filtered (file
, " ");
5108 for (col
= 0, regnum
= start_regnum
;
5109 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5111 if (*REGISTER_NAME (regnum
) == '\0')
5112 continue; /* unused register */
5113 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5115 break; /* end the row: reached FP register */
5116 fprintf_filtered (file
,
5117 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
5118 REGISTER_NAME (regnum
));
5121 /* print the R0 to R31 names */
5122 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
5123 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
5125 fprintf_filtered (file
, "\n ");
5127 /* now print the values in hex, 4 or 8 to the row */
5128 for (col
= 0, regnum
= start_regnum
;
5129 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
5131 if (*REGISTER_NAME (regnum
) == '\0')
5132 continue; /* unused register */
5133 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5135 break; /* end row: reached FP register */
5136 /* OK: get the data in raw format. */
5137 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5138 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
5139 /* pad small registers */
5141 byte
< (mips_abi_regsize (current_gdbarch
)
5142 - register_size (current_gdbarch
, regnum
)); byte
++)
5143 printf_filtered (" ");
5144 /* Now print the register value in hex, endian order. */
5145 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5147 register_size (current_gdbarch
,
5148 regnum
) - register_size (current_gdbarch
, regnum
);
5149 byte
< register_size (current_gdbarch
, regnum
); byte
++)
5150 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5152 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
5154 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
5155 fprintf_filtered (file
, " ");
5158 if (col
> 0) /* ie. if we actually printed anything... */
5159 fprintf_filtered (file
, "\n");
5164 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
5167 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5168 struct frame_info
*frame
, int regnum
, int all
)
5170 if (regnum
!= -1) /* do one specified register */
5172 gdb_assert (regnum
>= NUM_REGS
);
5173 if (*(REGISTER_NAME (regnum
)) == '\0')
5174 error ("Not a valid register for the current processor type");
5176 mips_print_register (file
, frame
, regnum
, 0);
5177 fprintf_filtered (file
, "\n");
5180 /* do all (or most) registers */
5183 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
5185 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
5188 if (all
) /* true for "INFO ALL-REGISTERS" command */
5189 regnum
= print_fp_register_row (file
, frame
, regnum
);
5191 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
5194 regnum
= print_gp_register_row (file
, frame
, regnum
);
5199 /* Is this a branch with a delay slot? */
5201 static int is_delayed (unsigned long);
5204 is_delayed (unsigned long insn
)
5207 for (i
= 0; i
< NUMOPCODES
; ++i
)
5208 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5209 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5211 return (i
< NUMOPCODES
5212 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5213 | INSN_COND_BRANCH_DELAY
5214 | INSN_COND_BRANCH_LIKELY
)));
5218 mips_step_skips_delay (CORE_ADDR pc
)
5220 char buf
[MIPS_INSTLEN
];
5222 /* There is no branch delay slot on MIPS16. */
5223 if (pc_is_mips16 (pc
))
5226 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
5227 /* If error reading memory, guess that it is not a delayed branch. */
5229 return is_delayed ((unsigned long)
5230 extract_unsigned_integer (buf
, MIPS_INSTLEN
));
5233 /* Skip the PC past function prologue instructions (32-bit version).
5234 This is a helper function for mips_skip_prologue. */
5237 mips32_skip_prologue (CORE_ADDR pc
)
5241 int seen_sp_adjust
= 0;
5242 int load_immediate_bytes
= 0;
5244 /* Find an upper bound on the prologue. */
5245 end_pc
= skip_prologue_using_sal (pc
);
5247 end_pc
= pc
+ 100; /* Magic. */
5249 /* Skip the typical prologue instructions. These are the stack adjustment
5250 instruction and the instructions that save registers on the stack
5251 or in the gcc frame. */
5252 for (; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
5254 unsigned long high_word
;
5256 inst
= mips_fetch_instruction (pc
);
5257 high_word
= (inst
>> 16) & 0xffff;
5259 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
5260 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
5262 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
5263 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
5265 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
5266 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
5267 && (inst
& 0x001F0000)) /* reg != $zero */
5270 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
5272 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
5274 continue; /* reg != $zero */
5276 /* move $s8,$sp. With different versions of gas this will be either
5277 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
5278 Accept any one of these. */
5279 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
5282 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
5284 else if (high_word
== 0x3c1c) /* lui $gp,n */
5286 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
5288 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
5289 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
5291 /* The following instructions load $at or $t0 with an immediate
5292 value in preparation for a stack adjustment via
5293 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
5294 a local variable, so we accept them only before a stack adjustment
5295 instruction was seen. */
5296 else if (!seen_sp_adjust
)
5298 if (high_word
== 0x3c01 || /* lui $at,n */
5299 high_word
== 0x3c08) /* lui $t0,n */
5301 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5304 else if (high_word
== 0x3421 || /* ori $at,$at,n */
5305 high_word
== 0x3508 || /* ori $t0,$t0,n */
5306 high_word
== 0x3401 || /* ori $at,$zero,n */
5307 high_word
== 0x3408) /* ori $t0,$zero,n */
5309 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
5319 /* In a frameless function, we might have incorrectly
5320 skipped some load immediate instructions. Undo the skipping
5321 if the load immediate was not followed by a stack adjustment. */
5322 if (load_immediate_bytes
&& !seen_sp_adjust
)
5323 pc
-= load_immediate_bytes
;
5327 /* Skip the PC past function prologue instructions (16-bit version).
5328 This is a helper function for mips_skip_prologue. */
5331 mips16_skip_prologue (CORE_ADDR pc
)
5334 int extend_bytes
= 0;
5335 int prev_extend_bytes
;
5337 /* Table of instructions likely to be found in a function prologue. */
5340 unsigned short inst
;
5341 unsigned short mask
;
5347 , /* addiu $sp,offset */
5350 , /* daddiu $sp,offset */
5353 , /* sw reg,n($sp) */
5356 , /* sd reg,n($sp) */
5359 , /* sw $ra,n($sp) */
5362 , /* sd $ra,n($sp) */
5368 , /* sw $a0-$a3,n($s1) */
5371 , /* move reg,$a0-$a3 */
5374 , /* entry pseudo-op */
5377 , /* addiu $s1,$sp,n */
5379 0, 0} /* end of table marker */
5382 /* Find an upper bound on the prologue. */
5383 end_pc
= skip_prologue_using_sal (pc
);
5385 end_pc
= pc
+ 100; /* Magic. */
5387 /* Skip the typical prologue instructions. These are the stack adjustment
5388 instruction and the instructions that save registers on the stack
5389 or in the gcc frame. */
5390 for (; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
5392 unsigned short inst
;
5395 inst
= mips_fetch_instruction (pc
);
5397 /* Normally we ignore an extend instruction. However, if it is
5398 not followed by a valid prologue instruction, we must adjust
5399 the pc back over the extend so that it won't be considered
5400 part of the prologue. */
5401 if ((inst
& 0xf800) == 0xf000) /* extend */
5403 extend_bytes
= MIPS16_INSTLEN
;
5406 prev_extend_bytes
= extend_bytes
;
5409 /* Check for other valid prologue instructions besides extend. */
5410 for (i
= 0; table
[i
].mask
!= 0; i
++)
5411 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
5413 if (table
[i
].mask
!= 0) /* it was in table? */
5414 continue; /* ignore it */
5418 /* Return the current pc, adjusted backwards by 2 if
5419 the previous instruction was an extend. */
5420 return pc
- prev_extend_bytes
;
5426 /* To skip prologues, I use this predicate. Returns either PC itself
5427 if the code at PC does not look like a function prologue; otherwise
5428 returns an address that (if we're lucky) follows the prologue. If
5429 LENIENT, then we must skip everything which is involved in setting
5430 up the frame (it's OK to skip more, just so long as we don't skip
5431 anything which might clobber the registers which are being saved.
5432 We must skip more in the case where part of the prologue is in the
5433 delay slot of a non-prologue instruction). */
5436 mips_skip_prologue (CORE_ADDR pc
)
5438 /* See if we can determine the end of the prologue via the symbol table.
5439 If so, then return either PC, or the PC after the prologue, whichever
5442 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
5444 if (post_prologue_pc
!= 0)
5445 return max (pc
, post_prologue_pc
);
5447 /* Can't determine prologue from the symbol table, need to examine
5450 if (pc_is_mips16 (pc
))
5451 return mips16_skip_prologue (pc
);
5453 return mips32_skip_prologue (pc
);
5456 /* Root of all "set mips "/"show mips " commands. This will eventually be
5457 used for all MIPS-specific commands. */
5460 show_mips_command (char *args
, int from_tty
)
5462 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5466 set_mips_command (char *args
, int from_tty
)
5469 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5470 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5473 /* Commands to show/set the MIPS FPU type. */
5476 show_mipsfpu_command (char *args
, int from_tty
)
5479 switch (MIPS_FPU_TYPE
)
5481 case MIPS_FPU_SINGLE
:
5482 fpu
= "single-precision";
5484 case MIPS_FPU_DOUBLE
:
5485 fpu
= "double-precision";
5488 fpu
= "absent (none)";
5491 internal_error (__FILE__
, __LINE__
, "bad switch");
5493 if (mips_fpu_type_auto
)
5495 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5499 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5504 set_mipsfpu_command (char *args
, int from_tty
)
5507 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5508 show_mipsfpu_command (args
, from_tty
);
5512 set_mipsfpu_single_command (char *args
, int from_tty
)
5514 struct gdbarch_info info
;
5515 gdbarch_info_init (&info
);
5516 mips_fpu_type
= MIPS_FPU_SINGLE
;
5517 mips_fpu_type_auto
= 0;
5518 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5519 instead of relying on globals. Doing that would let generic code
5520 handle the search for this specific architecture. */
5521 if (!gdbarch_update_p (info
))
5522 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5526 set_mipsfpu_double_command (char *args
, int from_tty
)
5528 struct gdbarch_info info
;
5529 gdbarch_info_init (&info
);
5530 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5531 mips_fpu_type_auto
= 0;
5532 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5533 instead of relying on globals. Doing that would let generic code
5534 handle the search for this specific architecture. */
5535 if (!gdbarch_update_p (info
))
5536 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5540 set_mipsfpu_none_command (char *args
, int from_tty
)
5542 struct gdbarch_info info
;
5543 gdbarch_info_init (&info
);
5544 mips_fpu_type
= MIPS_FPU_NONE
;
5545 mips_fpu_type_auto
= 0;
5546 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5547 instead of relying on globals. Doing that would let generic code
5548 handle the search for this specific architecture. */
5549 if (!gdbarch_update_p (info
))
5550 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
5554 set_mipsfpu_auto_command (char *args
, int from_tty
)
5556 mips_fpu_type_auto
= 1;
5559 /* Attempt to identify the particular processor model by reading the
5560 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5561 the relevant processor still exists (it dates back to '94) and
5562 secondly this is not the way to do this. The processor type should
5563 be set by forcing an architecture change. */
5566 deprecated_mips_set_processor_regs_hack (void)
5568 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5571 prid
= read_register (PRID_REGNUM
);
5573 if ((prid
& ~0xf) == 0x700)
5574 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5577 /* Just like reinit_frame_cache, but with the right arguments to be
5578 callable as an sfunc. */
5581 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5582 struct cmd_list_element
*c
)
5584 reinit_frame_cache ();
5588 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5590 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5591 mips_extra_func_info_t proc_desc
;
5593 /* Search for the function containing this address. Set the low bit
5594 of the address when searching, in case we were given an even address
5595 that is the start of a 16-bit function. If we didn't do this,
5596 the search would fail because the symbol table says the function
5597 starts at an odd address, i.e. 1 byte past the given address. */
5598 memaddr
= ADDR_BITS_REMOVE (memaddr
);
5599 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
5601 /* Make an attempt to determine if this is a 16-bit function. If
5602 the procedure descriptor exists and the address therein is odd,
5603 it's definitely a 16-bit function. Otherwise, we have to just
5604 guess that if the address passed in is odd, it's 16-bits. */
5605 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5606 disassembler needs to be able to locally determine the ISA, and
5607 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5611 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
5612 info
->mach
= bfd_mach_mips16
;
5616 if (pc_is_mips16 (memaddr
))
5617 info
->mach
= bfd_mach_mips16
;
5620 /* Round down the instruction address to the appropriate boundary. */
5621 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5623 /* Set the disassembler options. */
5624 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
5626 /* Set up the disassembler info, so that we get the right
5627 register names from libopcodes. */
5628 if (tdep
->mips_abi
== MIPS_ABI_N32
)
5629 info
->disassembler_options
= "gpr-names=n32";
5631 info
->disassembler_options
= "gpr-names=64";
5632 info
->flavour
= bfd_target_elf_flavour
;
5635 /* This string is not recognized explicitly by the disassembler,
5636 but it tells the disassembler to not try to guess the ABI from
5637 the bfd elf headers, such that, if the user overrides the ABI
5638 of a program linked as NewABI, the disassembly will follow the
5639 register naming conventions specified by the user. */
5640 info
->disassembler_options
= "gpr-names=32";
5642 /* Call the appropriate disassembler based on the target endian-ness. */
5643 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5644 return print_insn_big_mips (memaddr
, info
);
5646 return print_insn_little_mips (memaddr
, info
);
5649 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
5650 counter value to determine whether a 16- or 32-bit breakpoint should be
5651 used. It returns a pointer to a string of bytes that encode a breakpoint
5652 instruction, stores the length of the string to *lenptr, and adjusts pc
5653 (if necessary) to point to the actual memory location where the
5654 breakpoint should be inserted. */
5656 static const unsigned char *
5657 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5659 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5661 if (pc_is_mips16 (*pcptr
))
5663 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5664 *pcptr
= unmake_mips16_addr (*pcptr
);
5665 *lenptr
= sizeof (mips16_big_breakpoint
);
5666 return mips16_big_breakpoint
;
5670 /* The IDT board uses an unusual breakpoint value, and
5671 sometimes gets confused when it sees the usual MIPS
5672 breakpoint instruction. */
5673 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5674 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5675 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5677 *lenptr
= sizeof (big_breakpoint
);
5679 if (strcmp (target_shortname
, "mips") == 0)
5680 return idt_big_breakpoint
;
5681 else if (strcmp (target_shortname
, "ddb") == 0
5682 || strcmp (target_shortname
, "pmon") == 0
5683 || strcmp (target_shortname
, "lsi") == 0)
5684 return pmon_big_breakpoint
;
5686 return big_breakpoint
;
5691 if (pc_is_mips16 (*pcptr
))
5693 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5694 *pcptr
= unmake_mips16_addr (*pcptr
);
5695 *lenptr
= sizeof (mips16_little_breakpoint
);
5696 return mips16_little_breakpoint
;
5700 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5701 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5702 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5704 *lenptr
= sizeof (little_breakpoint
);
5706 if (strcmp (target_shortname
, "mips") == 0)
5707 return idt_little_breakpoint
;
5708 else if (strcmp (target_shortname
, "ddb") == 0
5709 || strcmp (target_shortname
, "pmon") == 0
5710 || strcmp (target_shortname
, "lsi") == 0)
5711 return pmon_little_breakpoint
;
5713 return little_breakpoint
;
5718 /* If PC is in a mips16 call or return stub, return the address of the target
5719 PC, which is either the callee or the caller. There are several
5720 cases which must be handled:
5722 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5723 target PC is in $31 ($ra).
5724 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5725 and the target PC is in $2.
5726 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5727 before the jal instruction, this is effectively a call stub
5728 and the the target PC is in $2. Otherwise this is effectively
5729 a return stub and the target PC is in $18.
5731 See the source code for the stubs in gcc/config/mips/mips16.S for
5734 This function implements the SKIP_TRAMPOLINE_CODE macro.
5738 mips_skip_stub (CORE_ADDR pc
)
5741 CORE_ADDR start_addr
;
5743 /* Find the starting address and name of the function containing the PC. */
5744 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5747 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5748 target PC is in $31 ($ra). */
5749 if (strcmp (name
, "__mips16_ret_sf") == 0
5750 || strcmp (name
, "__mips16_ret_df") == 0)
5751 return read_signed_register (RA_REGNUM
);
5753 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5755 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5756 and the target PC is in $2. */
5757 if (name
[19] >= '0' && name
[19] <= '9')
5758 return read_signed_register (2);
5760 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5761 before the jal instruction, this is effectively a call stub
5762 and the the target PC is in $2. Otherwise this is effectively
5763 a return stub and the target PC is in $18. */
5764 else if (name
[19] == 's' || name
[19] == 'd')
5766 if (pc
== start_addr
)
5768 /* Check if the target of the stub is a compiler-generated
5769 stub. Such a stub for a function bar might have a name
5770 like __fn_stub_bar, and might look like this:
5775 la $1,bar (becomes a lui/addiu pair)
5777 So scan down to the lui/addi and extract the target
5778 address from those two instructions. */
5780 CORE_ADDR target_pc
= read_signed_register (2);
5784 /* See if the name of the target function is __fn_stub_*. */
5785 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5788 if (strncmp (name
, "__fn_stub_", 10) != 0
5789 && strcmp (name
, "etext") != 0
5790 && strcmp (name
, "_etext") != 0)
5793 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5794 The limit on the search is arbitrarily set to 20
5795 instructions. FIXME. */
5796 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5798 inst
= mips_fetch_instruction (target_pc
);
5799 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5800 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5801 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5802 return pc
| (inst
& 0xffff); /* low word */
5805 /* Couldn't find the lui/addui pair, so return stub address. */
5809 /* This is the 'return' part of a call stub. The return
5810 address is in $r18. */
5811 return read_signed_register (18);
5814 return 0; /* not a stub */
5818 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5819 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5822 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5824 CORE_ADDR start_addr
;
5826 /* Find the starting address of the function containing the PC. If the
5827 caller didn't give us a name, look it up at the same time. */
5828 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5832 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5834 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5835 if (name
[19] >= '0' && name
[19] <= '9')
5837 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5838 before the jal instruction, this is effectively a call stub. */
5839 else if (name
[19] == 's' || name
[19] == 'd')
5840 return pc
== start_addr
;
5843 return 0; /* not a stub */
5847 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5848 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5851 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5853 CORE_ADDR start_addr
;
5855 /* Find the starting address of the function containing the PC. */
5856 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5859 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5860 if (strcmp (name
, "__mips16_ret_sf") == 0
5861 || strcmp (name
, "__mips16_ret_df") == 0)
5864 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5865 i.e. after the jal instruction, this is effectively a return stub. */
5866 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5867 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5870 return 0; /* not a stub */
5874 /* Return non-zero if the PC is in a library helper function that
5875 should be ignored. This implements the
5876 DEPRECATED_IGNORE_HELPER_CALL macro. */
5879 mips_ignore_helper (CORE_ADDR pc
)
5883 /* Find the starting address and name of the function containing the PC. */
5884 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5887 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5888 that we want to ignore. */
5889 return (strcmp (name
, "__mips16_ret_sf") == 0
5890 || strcmp (name
, "__mips16_ret_df") == 0);
5894 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5895 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5898 mips_stab_reg_to_regnum (int num
)
5901 if (num
>= 0 && num
< 32)
5903 else if (num
>= 38 && num
< 70)
5904 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5906 regnum
= mips_regnum (current_gdbarch
)->hi
;
5908 regnum
= mips_regnum (current_gdbarch
)->lo
;
5910 /* This will hopefully (eventually) provoke a warning. Should
5911 we be calling complaint() here? */
5912 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5913 return NUM_REGS
+ regnum
;
5917 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5918 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5921 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5924 if (num
>= 0 && num
< 32)
5926 else if (num
>= 32 && num
< 64)
5927 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5929 regnum
= mips_regnum (current_gdbarch
)->hi
;
5931 regnum
= mips_regnum (current_gdbarch
)->lo
;
5933 /* This will hopefully (eventually) provoke a warning. Should we
5934 be calling complaint() here? */
5935 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5936 return NUM_REGS
+ regnum
;
5940 mips_register_sim_regno (int regnum
)
5942 /* Only makes sense to supply raw registers. */
5943 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5944 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5945 decide if it is valid. Should instead define a standard sim/gdb
5946 register numbering scheme. */
5947 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5948 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5951 return LEGACY_SIM_REGNO_IGNORE
;
5955 /* Convert an integer into an address. By first converting the value
5956 into a pointer and then extracting it signed, the address is
5957 guarenteed to be correctly sign extended. */
5960 mips_integer_to_address (struct type
*type
, void *buf
)
5962 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5963 LONGEST val
= unpack_long (type
, buf
);
5964 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5965 return extract_signed_integer (tmp
,
5966 TYPE_LENGTH (builtin_type_void_data_ptr
));
5970 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5972 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5973 const char *name
= bfd_get_section_name (abfd
, sect
);
5975 if (*abip
!= MIPS_ABI_UNKNOWN
)
5978 if (strncmp (name
, ".mdebug.", 8) != 0)
5981 if (strcmp (name
, ".mdebug.abi32") == 0)
5982 *abip
= MIPS_ABI_O32
;
5983 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5984 *abip
= MIPS_ABI_N32
;
5985 else if (strcmp (name
, ".mdebug.abi64") == 0)
5986 *abip
= MIPS_ABI_N64
;
5987 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5988 *abip
= MIPS_ABI_O64
;
5989 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5990 *abip
= MIPS_ABI_EABI32
;
5991 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5992 *abip
= MIPS_ABI_EABI64
;
5994 warning ("unsupported ABI %s.", name
+ 8);
5997 static enum mips_abi
5998 global_mips_abi (void)
6002 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
6003 if (mips_abi_strings
[i
] == mips_abi_string
)
6004 return (enum mips_abi
) i
;
6006 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
6009 static struct gdbarch
*
6010 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6012 struct gdbarch
*gdbarch
;
6013 struct gdbarch_tdep
*tdep
;
6015 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
6017 enum mips_fpu_type fpu_type
;
6019 /* First of all, extract the elf_flags, if available. */
6020 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6021 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6022 else if (arches
!= NULL
)
6023 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6027 fprintf_unfiltered (gdb_stdlog
,
6028 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6030 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6031 switch ((elf_flags
& EF_MIPS_ABI
))
6033 case E_MIPS_ABI_O32
:
6034 found_abi
= MIPS_ABI_O32
;
6036 case E_MIPS_ABI_O64
:
6037 found_abi
= MIPS_ABI_O64
;
6039 case E_MIPS_ABI_EABI32
:
6040 found_abi
= MIPS_ABI_EABI32
;
6042 case E_MIPS_ABI_EABI64
:
6043 found_abi
= MIPS_ABI_EABI64
;
6046 if ((elf_flags
& EF_MIPS_ABI2
))
6047 found_abi
= MIPS_ABI_N32
;
6049 found_abi
= MIPS_ABI_UNKNOWN
;
6053 /* GCC creates a pseudo-section whose name describes the ABI. */
6054 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6055 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6057 /* If we have no useful BFD information, use the ABI from the last
6058 MIPS architecture (if there is one). */
6059 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6060 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6062 /* Try the architecture for any hint of the correct ABI. */
6063 if (found_abi
== MIPS_ABI_UNKNOWN
6064 && info
.bfd_arch_info
!= NULL
6065 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6067 switch (info
.bfd_arch_info
->mach
)
6069 case bfd_mach_mips3900
:
6070 found_abi
= MIPS_ABI_EABI32
;
6072 case bfd_mach_mips4100
:
6073 case bfd_mach_mips5000
:
6074 found_abi
= MIPS_ABI_EABI64
;
6076 case bfd_mach_mips8000
:
6077 case bfd_mach_mips10000
:
6078 /* On Irix, ELF64 executables use the N64 ABI. The
6079 pseudo-sections which describe the ABI aren't present
6080 on IRIX. (Even for executables created by gcc.) */
6081 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6082 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6083 found_abi
= MIPS_ABI_N64
;
6085 found_abi
= MIPS_ABI_N32
;
6091 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6094 /* What has the user specified from the command line? */
6095 wanted_abi
= global_mips_abi ();
6097 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6100 /* Now that we have found what the ABI for this binary would be,
6101 check whether the user is overriding it. */
6102 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6103 mips_abi
= wanted_abi
;
6104 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6105 mips_abi
= found_abi
;
6107 mips_abi
= MIPS_ABI_O32
;
6109 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6112 /* Also used when doing an architecture lookup. */
6114 fprintf_unfiltered (gdb_stdlog
,
6115 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
6116 mips64_transfers_32bit_regs_p
);
6118 /* Determine the MIPS FPU type. */
6119 if (!mips_fpu_type_auto
)
6120 fpu_type
= mips_fpu_type
;
6121 else if (info
.bfd_arch_info
!= NULL
6122 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6123 switch (info
.bfd_arch_info
->mach
)
6125 case bfd_mach_mips3900
:
6126 case bfd_mach_mips4100
:
6127 case bfd_mach_mips4111
:
6128 case bfd_mach_mips4120
:
6129 fpu_type
= MIPS_FPU_NONE
;
6131 case bfd_mach_mips4650
:
6132 fpu_type
= MIPS_FPU_SINGLE
;
6135 fpu_type
= MIPS_FPU_DOUBLE
;
6138 else if (arches
!= NULL
)
6139 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6141 fpu_type
= MIPS_FPU_DOUBLE
;
6143 fprintf_unfiltered (gdb_stdlog
,
6144 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6146 /* try to find a pre-existing architecture */
6147 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6149 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6151 /* MIPS needs to be pedantic about which ABI the object is
6153 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6155 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6157 /* Need to be pedantic about which register virtual size is
6159 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6160 != mips64_transfers_32bit_regs_p
)
6162 /* Be pedantic about which FPU is selected. */
6163 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6165 return arches
->gdbarch
;
6168 /* Need a new architecture. Fill in a target specific vector. */
6169 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6170 gdbarch
= gdbarch_alloc (&info
, tdep
);
6171 tdep
->elf_flags
= elf_flags
;
6172 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6173 tdep
->found_abi
= found_abi
;
6174 tdep
->mips_abi
= mips_abi
;
6175 tdep
->mips_fpu_type
= fpu_type
;
6177 /* Initially set everything according to the default ABI/ISA. */
6178 set_gdbarch_short_bit (gdbarch
, 16);
6179 set_gdbarch_int_bit (gdbarch
, 32);
6180 set_gdbarch_float_bit (gdbarch
, 32);
6181 set_gdbarch_double_bit (gdbarch
, 64);
6182 set_gdbarch_long_double_bit (gdbarch
, 64);
6183 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6184 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6185 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6187 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6188 mips_elf_make_msymbol_special
);
6190 /* Fill in the OS dependant register numbers and names. */
6192 const char **reg_names
;
6193 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
6194 struct mips_regnum
);
6195 if (info
.osabi
== GDB_OSABI_IRIX
)
6200 regnum
->badvaddr
= 66;
6203 regnum
->fp_control_status
= 69;
6204 regnum
->fp_implementation_revision
= 70;
6206 reg_names
= mips_irix_reg_names
;
6210 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
6211 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
6212 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6213 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
6214 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
6215 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
6216 regnum
->fp_control_status
= 70;
6217 regnum
->fp_implementation_revision
= 71;
6219 if (info
.bfd_arch_info
!= NULL
6220 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6221 reg_names
= mips_tx39_reg_names
;
6223 reg_names
= mips_generic_reg_names
;
6225 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
6226 replaced by read_pc? */
6227 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
6228 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6229 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6230 set_gdbarch_num_regs (gdbarch
, num_regs
);
6231 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6232 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6233 tdep
->mips_processor_reg_names
= reg_names
;
6234 tdep
->regnum
= regnum
;
6240 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6241 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6242 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6243 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6244 tdep
->default_mask_address_p
= 0;
6245 set_gdbarch_long_bit (gdbarch
, 32);
6246 set_gdbarch_ptr_bit (gdbarch
, 32);
6247 set_gdbarch_long_long_bit (gdbarch
, 64);
6250 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6251 set_gdbarch_deprecated_store_return_value (gdbarch
,
6252 mips_o64_store_return_value
);
6253 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6254 mips_o64_extract_return_value
);
6255 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
6256 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6257 tdep
->default_mask_address_p
= 0;
6258 set_gdbarch_long_bit (gdbarch
, 32);
6259 set_gdbarch_ptr_bit (gdbarch
, 32);
6260 set_gdbarch_long_long_bit (gdbarch
, 64);
6261 set_gdbarch_deprecated_use_struct_convention (gdbarch
, always_use_struct_convention
);
6263 case MIPS_ABI_EABI32
:
6264 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6265 set_gdbarch_deprecated_store_return_value (gdbarch
,
6266 mips_eabi_store_return_value
);
6267 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6268 mips_eabi_extract_return_value
);
6269 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6270 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6271 tdep
->default_mask_address_p
= 0;
6272 set_gdbarch_long_bit (gdbarch
, 32);
6273 set_gdbarch_ptr_bit (gdbarch
, 32);
6274 set_gdbarch_long_long_bit (gdbarch
, 64);
6275 set_gdbarch_deprecated_reg_struct_has_addr
6276 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6277 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6279 case MIPS_ABI_EABI64
:
6280 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6281 set_gdbarch_deprecated_store_return_value (gdbarch
,
6282 mips_eabi_store_return_value
);
6283 set_gdbarch_deprecated_extract_return_value (gdbarch
,
6284 mips_eabi_extract_return_value
);
6285 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6286 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6287 tdep
->default_mask_address_p
= 0;
6288 set_gdbarch_long_bit (gdbarch
, 64);
6289 set_gdbarch_ptr_bit (gdbarch
, 64);
6290 set_gdbarch_long_long_bit (gdbarch
, 64);
6291 set_gdbarch_deprecated_reg_struct_has_addr
6292 (gdbarch
, mips_eabi_reg_struct_has_addr
);
6293 set_gdbarch_deprecated_use_struct_convention (gdbarch
, mips_eabi_use_struct_convention
);
6296 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6297 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6298 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6299 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6300 tdep
->default_mask_address_p
= 0;
6301 set_gdbarch_long_bit (gdbarch
, 32);
6302 set_gdbarch_ptr_bit (gdbarch
, 32);
6303 set_gdbarch_long_long_bit (gdbarch
, 64);
6304 set_gdbarch_long_double_bit (gdbarch
, 128);
6305 set_gdbarch_long_double_format (gdbarch
,
6306 &floatformat_n32n64_long_double_big
);
6309 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6310 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6311 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
6312 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6313 tdep
->default_mask_address_p
= 0;
6314 set_gdbarch_long_bit (gdbarch
, 64);
6315 set_gdbarch_ptr_bit (gdbarch
, 64);
6316 set_gdbarch_long_long_bit (gdbarch
, 64);
6317 set_gdbarch_long_double_bit (gdbarch
, 128);
6318 set_gdbarch_long_double_format (gdbarch
,
6319 &floatformat_n32n64_long_double_big
);
6322 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
6325 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6326 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6329 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6330 flag in object files because to do so would make it impossible to
6331 link with libraries compiled without "-gp32". This is
6332 unnecessarily restrictive.
6334 We could solve this problem by adding "-gp32" multilibs to gcc,
6335 but to set this flag before gcc is built with such multilibs will
6336 break too many systems.''
6338 But even more unhelpfully, the default linker output target for
6339 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6340 for 64-bit programs - you need to change the ABI to change this,
6341 and not all gcc targets support that currently. Therefore using
6342 this flag to detect 32-bit mode would do the wrong thing given
6343 the current gcc - it would make GDB treat these 64-bit programs
6344 as 32-bit programs by default. */
6346 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6347 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6348 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
6350 /* Add/remove bits from an address. The MIPS needs be careful to
6351 ensure that all 32 bit addresses are sign extended to 64 bits. */
6352 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6354 /* Unwind the frame. */
6355 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6356 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
6358 /* Map debug register numbers onto internal register numbers. */
6359 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6360 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6361 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6362 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
6363 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6364 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6365 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6366 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6368 /* MIPS version of CALL_DUMMY */
6370 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6371 replaced by a command, and all targets will default to on stack
6372 (regardless of the stack's execute status). */
6373 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6374 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6376 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6377 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6378 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6380 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6381 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6383 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6385 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6386 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6387 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6389 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6391 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6393 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6395 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
6396 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
6397 need to all be folded into the target vector. Since they are
6398 being used as guards for STOPPED_BY_WATCHPOINT, why not have
6399 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
6401 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6403 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_stub
);
6405 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
6406 to support MIPS16. This is a bad thing. Make sure not to do it
6407 if we have an OS ABI that actually supports shared libraries, since
6408 shared library support is more important. If we have an OS someday
6409 that supports both shared libraries and MIPS16, we'll have to find
6410 a better place for these. */
6411 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
6413 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
6414 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
6417 /* Hook in OS ABI-specific overrides, if they have been registered. */
6418 gdbarch_init_osabi (info
, gdbarch
);
6420 /* Unwind the frame. */
6421 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
6422 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
6423 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
6424 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
6425 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6426 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
6427 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6428 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6434 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6436 struct gdbarch_info info
;
6438 /* Force the architecture to update, and (if it's a MIPS architecture)
6439 mips_gdbarch_init will take care of the rest. */
6440 gdbarch_info_init (&info
);
6441 gdbarch_update_p (info
);
6444 /* Print out which MIPS ABI is in use. */
6447 show_mips_abi (char *ignore_args
, int from_tty
)
6449 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
6451 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
6454 enum mips_abi global_abi
= global_mips_abi ();
6455 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
6456 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6458 if (global_abi
== MIPS_ABI_UNKNOWN
)
6460 ("The MIPS ABI is set automatically (currently \"%s\").\n",
6462 else if (global_abi
== actual_abi
)
6464 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6468 /* Probably shouldn't happen... */
6470 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6471 actual_abi_str
, mips_abi_strings
[global_abi
]);
6477 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
6479 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
6483 int ef_mips_32bitmode
;
6484 /* determine the ISA */
6485 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6503 /* determine the size of a pointer */
6504 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6505 fprintf_unfiltered (file
,
6506 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6508 fprintf_unfiltered (file
,
6509 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6511 fprintf_unfiltered (file
,
6512 "mips_dump_tdep: ef_mips_arch = %d\n",
6514 fprintf_unfiltered (file
,
6515 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6516 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6517 fprintf_unfiltered (file
,
6518 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6519 mips_mask_address_p (tdep
),
6520 tdep
->default_mask_address_p
);
6522 fprintf_unfiltered (file
,
6523 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6524 MIPS_DEFAULT_FPU_TYPE
,
6525 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6526 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6527 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6529 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
6530 fprintf_unfiltered (file
,
6531 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6533 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6534 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6535 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6537 fprintf_unfiltered (file
,
6538 "mips_dump_tdep: mips_stack_argsize() = %d\n",
6539 mips_stack_argsize (current_gdbarch
));
6540 fprintf_unfiltered (file
, "mips_dump_tdep: A0_REGNUM = %d\n", A0_REGNUM
);
6541 fprintf_unfiltered (file
,
6542 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
6543 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
6544 fprintf_unfiltered (file
,
6545 "mips_dump_tdep: ATTACH_DETACH # %s\n",
6546 XSTRING (ATTACH_DETACH
));
6547 fprintf_unfiltered (file
,
6548 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
6549 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
6550 fprintf_unfiltered (file
,
6551 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
6552 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
6553 fprintf_unfiltered (file
,
6554 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
6555 FIRST_EMBED_REGNUM
);
6556 fprintf_unfiltered (file
,
6557 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
6558 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
6559 fprintf_unfiltered (file
,
6560 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6561 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6562 fprintf_unfiltered (file
,
6563 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6564 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6565 fprintf_unfiltered (file
,
6566 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6568 #ifdef MACHINE_CPROC_FP_OFFSET
6569 fprintf_unfiltered (file
,
6570 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6571 MACHINE_CPROC_FP_OFFSET
);
6573 #ifdef MACHINE_CPROC_PC_OFFSET
6574 fprintf_unfiltered (file
,
6575 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6576 MACHINE_CPROC_PC_OFFSET
);
6578 #ifdef MACHINE_CPROC_SP_OFFSET
6579 fprintf_unfiltered (file
,
6580 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6581 MACHINE_CPROC_SP_OFFSET
);
6583 fprintf_unfiltered (file
,
6584 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6586 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6587 fprintf_unfiltered (file
,
6588 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6589 fprintf_unfiltered (file
,
6590 "mips_dump_tdep: MIPS_INSTLEN = %d\n", MIPS_INSTLEN
);
6591 fprintf_unfiltered (file
,
6592 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6593 MIPS_LAST_ARG_REGNUM
,
6594 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6595 fprintf_unfiltered (file
,
6596 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
6597 fprintf_unfiltered (file
,
6598 "mips_dump_tdep: mips_abi_regsize() = %d\n",
6599 mips_abi_regsize (current_gdbarch
));
6600 fprintf_unfiltered (file
,
6601 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
6602 fprintf_unfiltered (file
,
6603 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6604 fprintf_unfiltered (file
,
6605 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6606 fprintf_unfiltered (file
,
6607 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6608 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6609 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6610 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6611 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6612 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6613 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
6614 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
6615 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6616 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
6617 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
6618 fprintf_unfiltered (file
, "mips_dump_tdep: RA_REGNUM = %d\n", RA_REGNUM
);
6620 fprintf_unfiltered (file
,
6621 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
6624 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
6627 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
6629 fprintf_unfiltered (file
,
6630 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6631 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6632 fprintf_unfiltered (file
,
6633 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6634 fprintf_unfiltered (file
,
6635 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6636 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6637 fprintf_unfiltered (file
,
6638 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6639 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6640 fprintf_unfiltered (file
,
6641 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6642 SOFTWARE_SINGLE_STEP_P ());
6643 fprintf_unfiltered (file
,
6644 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6645 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6646 #ifdef STACK_END_ADDR
6647 fprintf_unfiltered (file
,
6648 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6651 fprintf_unfiltered (file
,
6652 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6653 XSTRING (STEP_SKIPS_DELAY (PC
)));
6654 fprintf_unfiltered (file
,
6655 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6656 STEP_SKIPS_DELAY_P
);
6657 fprintf_unfiltered (file
,
6658 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6659 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6660 fprintf_unfiltered (file
, "mips_dump_tdep: T9_REGNUM = %d\n", T9_REGNUM
);
6661 fprintf_unfiltered (file
,
6662 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6663 fprintf_unfiltered (file
,
6664 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6665 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
6666 (TYPE
, CNT
, OTHERTYPE
)));
6667 fprintf_unfiltered (file
,
6668 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6669 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6671 fprintf_unfiltered (file
,
6672 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6673 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6676 fprintf_unfiltered (file
,
6677 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
6679 #ifdef TRACE_FLAVOR_SIZE
6680 fprintf_unfiltered (file
,
6681 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6685 fprintf_unfiltered (file
,
6686 "mips_dump_tdep: TRACE_SET # %s\n",
6687 XSTRING (TRACE_SET (X
, STATE
)));
6689 #ifdef UNUSED_REGNUM
6690 fprintf_unfiltered (file
,
6691 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6693 fprintf_unfiltered (file
, "mips_dump_tdep: V0_REGNUM = %d\n", V0_REGNUM
);
6694 fprintf_unfiltered (file
,
6695 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6696 (long) VM_MIN_ADDRESS
);
6697 fprintf_unfiltered (file
,
6698 "mips_dump_tdep: ZERO_REGNUM = %d\n", ZERO_REGNUM
);
6699 fprintf_unfiltered (file
,
6700 "mips_dump_tdep: _PROC_MAGIC_ = %d\n", _PROC_MAGIC_
);
6703 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6706 _initialize_mips_tdep (void)
6708 static struct cmd_list_element
*mipsfpulist
= NULL
;
6709 struct cmd_list_element
*c
;
6711 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6712 if (MIPS_ABI_LAST
+ 1
6713 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6714 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6716 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6718 mips_pdr_data
= register_objfile_data ();
6720 /* Add root prefix command for all "set mips"/"show mips" commands */
6721 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6722 "Various MIPS specific commands.",
6723 &setmipscmdlist
, "set mips ", 0, &setlist
);
6725 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6726 "Various MIPS specific commands.",
6727 &showmipscmdlist
, "show mips ", 0, &showlist
);
6729 /* Allow the user to override the saved register size. */
6730 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6733 &mips_abi_regsize_string
, "\
6734 Set size of general purpose registers saved on the stack.\n\
6735 This option can be set to one of:\n\
6736 32 - Force GDB to treat saved GP registers as 32-bit\n\
6737 64 - Force GDB to treat saved GP registers as 64-bit\n\
6738 auto - Allow GDB to use the target's default setting or autodetect the\n\
6739 saved GP register size from information contained in the executable.\n\
6740 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6742 /* Allow the user to override the argument stack size. */
6743 deprecated_add_show_from_set
6744 (add_set_enum_cmd ("stack-arg-size",
6747 &mips_stack_argsize_string
, "\
6748 Set the amount of stack space reserved for each argument.\n\
6749 This option can be set to one of:\n\
6750 32 - Force GDB to allocate 32-bit chunks per argument\n\
6751 64 - Force GDB to allocate 64-bit chunks per argument\n\
6752 auto - Allow GDB to determine the correct setting from the current\n\
6753 target and executable (default)", &setmipscmdlist
),
6756 /* Allow the user to override the ABI. */
6757 c
= add_set_enum_cmd
6758 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6759 "Set the ABI used by this program.\n"
6760 "This option can be set to one of:\n"
6761 " auto - the default ABI associated with the current binary\n"
6763 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6764 set_cmd_sfunc (c
, mips_abi_update
);
6765 add_cmd ("abi", class_obscure
, show_mips_abi
,
6766 "Show ABI in use by MIPS target", &showmipscmdlist
);
6768 /* Let the user turn off floating point and set the fence post for
6769 heuristic_proc_start. */
6771 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6772 "Set use of MIPS floating-point coprocessor.",
6773 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6774 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6775 "Select single-precision MIPS floating-point coprocessor.",
6777 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6778 "Select double-precision MIPS floating-point coprocessor.",
6780 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6781 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6782 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6783 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6784 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6785 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6786 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6787 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6788 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6789 "Select MIPS floating-point coprocessor automatically.",
6791 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6792 "Show current use of MIPS floating-point coprocessor target.",
6795 /* We really would like to have both "0" and "unlimited" work, but
6796 command.c doesn't deal with that. So make it a var_zinteger
6797 because the user can always use "999999" or some such for unlimited. */
6798 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6799 (char *) &heuristic_fence_post
, "\
6800 Set the distance searched for the start of a function.\n\
6801 If you are debugging a stripped executable, GDB needs to search through the\n\
6802 program for the start of a function. This command sets the distance of the\n\
6803 search. The only need to set it is when debugging a stripped executable.", &setlist
);
6804 /* We need to throw away the frame cache when we set this, since it
6805 might change our ability to get backtraces. */
6806 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6807 deprecated_add_show_from_set (c
, &showlist
);
6809 /* Allow the user to control whether the upper bits of 64-bit
6810 addresses should be zeroed. */
6811 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6812 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6813 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6814 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6815 allow GDB to determine the correct value.\n", "\
6816 Zerroing of upper 32 bits of 64-bit address is %s.",
6817 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6819 /* Allow the user to control the size of 32 bit registers within the
6820 raw remote packet. */
6821 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6822 &mips64_transfers_32bit_regs_p
, "\
6823 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6824 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6825 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6826 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6827 64 bits for others. Use \"off\" to disable compatibility mode", "\
6828 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6829 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6831 /* Debug this files internals. */
6832 deprecated_add_show_from_set
6833 (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6834 &mips_debug
, "Set mips debugging.\n\
6835 When non-zero, mips specific debugging is enabled.", &setdebuglist
),