1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
41 #include "opcode/mips.h"
46 /* The sizes of floating point registers. */
50 MIPS_FPU_SINGLE_REGSIZE
= 4,
51 MIPS_FPU_DOUBLE_REGSIZE
= 8
54 /* All the possible MIPS ABIs. */
66 struct frame_extra_info
68 mips_extra_func_info_t proc_desc
;
72 /* Various MIPS ISA options (related to stack analysis) can be
73 overridden dynamically. Establish an enum/array for managing
76 static const char size_auto
[] = "auto";
77 static const char size_32
[] = "32";
78 static const char size_64
[] = "64";
80 static const char *size_enums
[] = {
87 /* Some MIPS boards don't support floating point while others only
88 support single-precision floating-point operations. See also
89 FP_REGISTER_DOUBLE. */
93 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
94 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
95 MIPS_FPU_NONE
/* No floating point. */
98 #ifndef MIPS_DEFAULT_FPU_TYPE
99 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
101 static int mips_fpu_type_auto
= 1;
102 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
103 #define MIPS_FPU_TYPE mips_fpu_type
105 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
106 #ifndef FP_REGISTER_DOUBLE
107 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
111 /* MIPS specific per-architecture information */
114 /* from the elf header */
117 enum mips_abi mips_abi
;
118 enum mips_fpu_type mips_fpu_type
;
119 int mips_last_arg_regnum
;
120 int mips_last_fp_arg_regnum
;
121 int mips_default_saved_regsize
;
122 int mips_fp_register_double
;
123 int mips_regs_have_home_p
;
124 int mips_default_stack_argsize
;
129 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
130 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
134 #undef MIPS_LAST_FP_ARG_REGNUM
135 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
139 #undef MIPS_LAST_ARG_REGNUM
140 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
145 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
148 /* Return the currently configured (or set) saved register size. */
151 #undef MIPS_DEFAULT_SAVED_REGSIZE
152 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
153 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
154 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
157 static const char *mips_saved_regsize_string
= size_auto
;
159 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
162 mips_saved_regsize ()
164 if (mips_saved_regsize_string
== size_auto
)
165 return MIPS_DEFAULT_SAVED_REGSIZE
;
166 else if (mips_saved_regsize_string
== size_64
)
168 else /* if (mips_saved_regsize_string == size_32) */
172 /* Indicate that the ABI makes use of double-precision registers
173 provided by the FPU (rather than combining pairs of registers to
174 form double-precision values). Do not use "TARGET_IS_MIPS64" to
175 determine if the ABI is using double-precision registers. See also
178 #undef FP_REGISTER_DOUBLE
179 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
182 /* Does the caller allocate a ``home'' for each register used in the
183 function call? The N32 ABI and MIPS_EABI do not, the others do. */
186 #undef MIPS_REGS_HAVE_HOME_P
187 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
188 #elif !defined (MIPS_REGS_HAVE_HOME_P)
189 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
192 /* The amount of space reserved on the stack for registers. This is
193 different to MIPS_SAVED_REGSIZE as it determines the alignment of
194 data allocated after the registers have run out. */
197 #undef MIPS_DEFAULT_STACK_ARGSIZE
198 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
199 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
200 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
203 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
205 static const char *mips_stack_argsize_string
= size_auto
;
208 mips_stack_argsize (void)
210 if (mips_stack_argsize_string
== size_auto
)
211 return MIPS_DEFAULT_STACK_ARGSIZE
;
212 else if (mips_stack_argsize_string
== size_64
)
214 else /* if (mips_stack_argsize_string == size_32) */
220 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
223 static int mips_in_lenient_prologue (CORE_ADDR
, CORE_ADDR
);
226 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
228 static void mips_print_register (int, int);
230 static mips_extra_func_info_t
231 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*);
233 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
235 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
237 int mips_set_processor_type (char *);
239 static void mips_show_processor_type_command (char *, int);
241 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
243 static mips_extra_func_info_t
244 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
);
246 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
247 mips_extra_func_info_t proc_desc
);
249 /* This value is the model of MIPS in use. It is derived from the value
250 of the PrID register. */
252 char *mips_processor_type
;
254 char *tmp_mips_processor_type
;
256 /* A set of original names, to be used when restoring back to generic
257 registers from a specific set. */
259 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
260 char **mips_processor_reg_names
= mips_generic_reg_names
;
262 /* The list of available "set mips " and "show mips " commands */
263 static struct cmd_list_element
*setmipscmdlist
= NULL
;
264 static struct cmd_list_element
*showmipscmdlist
= NULL
;
267 mips_register_name (i
)
270 return mips_processor_reg_names
[i
];
273 /* Names of IDT R3041 registers. */
275 char *mips_r3041_reg_names
[] = {
276 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
277 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
278 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
279 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
280 "sr", "lo", "hi", "bad", "cause","pc",
281 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
282 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
283 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
284 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
285 "fsr", "fir", "fp", "",
286 "", "", "bus", "ccfg", "", "", "", "",
287 "", "", "port", "cmp", "", "", "epc", "prid",
290 /* Names of IDT R3051 registers. */
292 char *mips_r3051_reg_names
[] = {
293 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
294 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
295 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
296 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
297 "sr", "lo", "hi", "bad", "cause","pc",
298 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
299 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
300 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
301 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
302 "fsr", "fir", "fp", "",
303 "inx", "rand", "elo", "", "ctxt", "", "", "",
304 "", "", "ehi", "", "", "", "epc", "prid",
307 /* Names of IDT R3081 registers. */
309 char *mips_r3081_reg_names
[] = {
310 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
311 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
312 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
313 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
314 "sr", "lo", "hi", "bad", "cause","pc",
315 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
316 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
317 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
318 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
319 "fsr", "fir", "fp", "",
320 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
321 "", "", "ehi", "", "", "", "epc", "prid",
324 /* Names of LSI 33k registers. */
326 char *mips_lsi33k_reg_names
[] = {
327 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
328 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
329 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
330 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
331 "epc", "hi", "lo", "sr", "cause","badvaddr",
332 "dcic", "bpc", "bda", "", "", "", "", "",
333 "", "", "", "", "", "", "", "",
334 "", "", "", "", "", "", "", "",
335 "", "", "", "", "", "", "", "",
337 "", "", "", "", "", "", "", "",
338 "", "", "", "", "", "", "", "",
344 } mips_processor_type_table
[] = {
345 { "generic", mips_generic_reg_names
},
346 { "r3041", mips_r3041_reg_names
},
347 { "r3051", mips_r3051_reg_names
},
348 { "r3071", mips_r3081_reg_names
},
349 { "r3081", mips_r3081_reg_names
},
350 { "lsi33k", mips_lsi33k_reg_names
},
358 /* Table to translate MIPS16 register field to actual register number. */
359 static int mips16_to_32_reg
[8] =
360 {16, 17, 2, 3, 4, 5, 6, 7};
362 /* Heuristic_proc_start may hunt through the text section for a long
363 time across a 2400 baud serial line. Allows the user to limit this
366 static unsigned int heuristic_fence_post
= 0;
368 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
369 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
370 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
371 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
372 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
373 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
374 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
375 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
376 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
377 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
378 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
379 #define _PROC_MAGIC_ 0x0F0F0F0F
380 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
381 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
383 struct linked_proc_info
385 struct mips_extra_func_info info
;
386 struct linked_proc_info
*next
;
388 *linked_proc_desc_table
= NULL
;
391 mips_print_extra_frame_info (fi
)
392 struct frame_info
*fi
;
396 && fi
->extra_info
->proc_desc
397 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
398 printf_filtered (" frame pointer is at %s+%s\n",
399 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
400 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
403 /* Convert between RAW and VIRTUAL registers. The RAW register size
404 defines the remote-gdb packet. */
406 static int mips64_transfers_32bit_regs_p
= 0;
409 mips_register_raw_size (reg_nr
)
412 if (mips64_transfers_32bit_regs_p
)
413 return REGISTER_VIRTUAL_SIZE (reg_nr
);
419 mips_register_convertible (reg_nr
)
422 if (mips64_transfers_32bit_regs_p
)
425 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
429 mips_register_convert_to_virtual (n
, virtual_type
, raw_buf
, virt_buf
)
431 struct type
*virtual_type
;
435 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
437 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
438 TYPE_LENGTH (virtual_type
));
442 TYPE_LENGTH (virtual_type
));
446 mips_register_convert_to_raw (virtual_type
, n
, virt_buf
, raw_buf
)
447 struct type
*virtual_type
;
452 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
453 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
454 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
456 TYPE_LENGTH (virtual_type
));
460 TYPE_LENGTH (virtual_type
));
463 /* Should the upper word of 64-bit addresses be zeroed? */
464 static int mask_address_p
= 1;
466 /* Should call_function allocate stack space for a struct return? */
468 mips_use_struct_convention (gcc_p
, type
)
473 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
475 return 1; /* Structures are returned by ref in extra arg0 */
478 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
481 pc_is_mips16 (bfd_vma memaddr
)
483 struct minimal_symbol
*sym
;
485 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
486 if (IS_MIPS16_ADDR (memaddr
))
489 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
490 the high bit of the info field. Use this to decide if the function is
491 MIPS16 or normal MIPS. */
492 sym
= lookup_minimal_symbol_by_pc (memaddr
);
494 return MSYMBOL_IS_SPECIAL (sym
);
500 /* This returns the PC of the first inst after the prologue. If we can't
501 find the prologue, then return 0. */
504 after_prologue (pc
, proc_desc
)
506 mips_extra_func_info_t proc_desc
;
508 struct symtab_and_line sal
;
509 CORE_ADDR func_addr
, func_end
;
512 proc_desc
= find_proc_desc (pc
, NULL
);
516 /* If function is frameless, then we need to do it the hard way. I
517 strongly suspect that frameless always means prologueless... */
518 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
519 && PROC_FRAME_OFFSET (proc_desc
) == 0)
523 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
524 return 0; /* Unknown */
526 sal
= find_pc_line (func_addr
, 0);
528 if (sal
.end
< func_end
)
531 /* The line after the prologue is after the end of the function. In this
532 case, tell the caller to find the prologue the hard way. */
537 /* Decode a MIPS32 instruction that saves a register in the stack, and
538 set the appropriate bit in the general register mask or float register mask
539 to indicate which register is saved. This is a helper function
540 for mips_find_saved_regs. */
543 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
545 unsigned long *gen_mask
;
546 unsigned long *float_mask
;
550 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
551 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
552 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
554 /* It might be possible to use the instruction to
555 find the offset, rather than the code below which
556 is based on things being in a certain order in the
557 frame, but figuring out what the instruction's offset
558 is relative to might be a little tricky. */
559 reg
= (inst
& 0x001f0000) >> 16;
560 *gen_mask
|= (1 << reg
);
562 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
563 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
564 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
567 reg
= ((inst
& 0x001f0000) >> 16);
568 *float_mask
|= (1 << reg
);
572 /* Decode a MIPS16 instruction that saves a register in the stack, and
573 set the appropriate bit in the general register or float register mask
574 to indicate which register is saved. This is a helper function
575 for mips_find_saved_regs. */
578 mips16_decode_reg_save (inst
, gen_mask
)
580 unsigned long *gen_mask
;
582 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
584 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
585 *gen_mask
|= (1 << reg
);
587 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
589 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
590 *gen_mask
|= (1 << reg
);
592 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
593 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
594 *gen_mask
|= (1 << RA_REGNUM
);
598 /* Fetch and return instruction from the specified location. If the PC
599 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
602 mips_fetch_instruction (addr
)
605 char buf
[MIPS_INSTLEN
];
609 if (pc_is_mips16 (addr
))
611 instlen
= MIPS16_INSTLEN
;
612 addr
= UNMAKE_MIPS16_ADDR (addr
);
615 instlen
= MIPS_INSTLEN
;
616 status
= read_memory_nobpt (addr
, buf
, instlen
);
618 memory_error (status
, addr
);
619 return extract_unsigned_integer (buf
, instlen
);
623 /* These the fields of 32 bit mips instructions */
624 #define mips32_op(x) (x >> 25)
625 #define itype_op(x) (x >> 25)
626 #define itype_rs(x) ((x >> 21)& 0x1f)
627 #define itype_rt(x) ((x >> 16) & 0x1f)
628 #define itype_immediate(x) ( x & 0xffff)
630 #define jtype_op(x) (x >> 25)
631 #define jtype_target(x) ( x & 0x03fffff)
633 #define rtype_op(x) (x >>25)
634 #define rtype_rs(x) ((x>>21) & 0x1f)
635 #define rtype_rt(x) ((x>>16) & 0x1f)
636 #define rtype_rd(x) ((x>>11) & 0x1f)
637 #define rtype_shamt(x) ((x>>6) & 0x1f)
638 #define rtype_funct(x) (x & 0x3f )
641 mips32_relative_offset (unsigned long inst
)
644 x
= itype_immediate (inst
);
645 if (x
& 0x8000) /* sign bit set */
647 x
|= 0xffff0000; /* sign extension */
653 /* Determine whate to set a single step breakpoint while considering
656 mips32_next_pc (CORE_ADDR pc
)
660 inst
= mips_fetch_instruction (pc
);
661 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
663 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
665 op
= ((inst
>> 25) & 0x03);
669 goto equal_branch
; /* BEQL */
671 goto neq_branch
; /* BNEZ */
673 goto less_branch
; /* BLEZ */
675 goto greater_branch
; /* BGTZ */
681 pc
+= 4; /* Not a branch, next instruction is easy */
684 { /* This gets way messy */
686 /* Further subdivide into SPECIAL, REGIMM and other */
687 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
689 case 0: /* SPECIAL */
690 op
= rtype_funct (inst
);
695 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
701 break; /* end special */
704 op
= jtype_op (inst
); /* branch condition */
705 switch (jtype_op (inst
))
709 case 16: /* BLTZALL */
710 case 18: /* BLTZALL */
712 if (read_register (itype_rs (inst
)) < 0)
713 pc
+= mips32_relative_offset (inst
) + 4;
715 pc
+= 8; /* after the delay slot */
719 case 17: /* BGEZAL */
720 case 19: /* BGEZALL */
721 greater_equal_branch
:
722 if (read_register (itype_rs (inst
)) >= 0)
723 pc
+= mips32_relative_offset (inst
) + 4;
725 pc
+= 8; /* after the delay slot */
727 /* All of the other intructions in the REGIMM catagory */
732 break; /* end REGIMM */
737 reg
= jtype_target (inst
) << 2;
738 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
739 /* Whats this mysterious 0xf000000 adjustment ??? */
742 /* FIXME case JALX : */
745 reg
= jtype_target (inst
) << 2;
746 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
747 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
749 break; /* The new PC will be alternate mode */
750 case 4: /* BEQ , BEQL */
752 if (read_register (itype_rs (inst
)) ==
753 read_register (itype_rt (inst
)))
754 pc
+= mips32_relative_offset (inst
) + 4;
758 case 5: /* BNE , BNEL */
760 if (read_register (itype_rs (inst
)) !=
761 read_register (itype_rs (inst
)))
762 pc
+= mips32_relative_offset (inst
) + 4;
766 case 6: /* BLEZ , BLEZL */
768 if (read_register (itype_rs (inst
) <= 0))
769 pc
+= mips32_relative_offset (inst
) + 4;
774 greater_branch
: /* BGTZ BGTZL */
775 if (read_register (itype_rs (inst
) > 0))
776 pc
+= mips32_relative_offset (inst
) + 4;
785 } /* mips32_next_pc */
787 /* Decoding the next place to set a breakpoint is irregular for the
788 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
789 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
790 We dont want to set a single step instruction on the extend instruction
794 /* Lots of mips16 instruction formats */
795 /* Predicting jumps requires itype,ritype,i8type
796 and their extensions extItype,extritype,extI8type
798 enum mips16_inst_fmts
800 itype
, /* 0 immediate 5,10 */
801 ritype
, /* 1 5,3,8 */
802 rrtype
, /* 2 5,3,3,5 */
803 rritype
, /* 3 5,3,3,5 */
804 rrrtype
, /* 4 5,3,3,3,2 */
805 rriatype
, /* 5 5,3,3,1,4 */
806 shifttype
, /* 6 5,3,3,3,2 */
807 i8type
, /* 7 5,3,8 */
808 i8movtype
, /* 8 5,3,3,5 */
809 i8mov32rtype
, /* 9 5,3,5,3 */
810 i64type
, /* 10 5,3,8 */
811 ri64type
, /* 11 5,3,3,5 */
812 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
813 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
814 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
815 extRRItype
, /* 15 5,5,5,5,3,3,5 */
816 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
817 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
818 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
819 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
820 extRi64type
, /* 20 5,6,5,5,3,3,5 */
821 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
823 /* I am heaping all the fields of the formats into one structure and then,
824 only the fields which are involved in instruction extension */
828 enum mips16_inst_fmts fmt
;
829 unsigned long offset
;
830 unsigned int regx
; /* Function in i8 type */
837 print_unpack (char *comment
,
838 struct upk_mips16
*u
)
840 printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
841 comment
, u
->inst
, u
->fmt
, paddr (u
->offset
), u
->regx
, u
->regy
);
844 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
845 format for the bits which make up the immediatate extension.
848 extended_offset (unsigned long extension
)
851 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
853 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
855 value
|= extension
& 0x01f; /* extract 4:0 */
859 /* Only call this function if you know that this is an extendable
860 instruction, It wont malfunction, but why make excess remote memory references?
861 If the immediate operands get sign extended or somthing, do it after
862 the extension is performed.
864 /* FIXME: Every one of these cases needs to worry about sign extension
865 when the offset is to be used in relative addressing */
868 static unsigned short
869 fetch_mips_16 (CORE_ADDR pc
)
872 pc
&= 0xfffffffe; /* clear the low order bit */
873 target_read_memory (pc
, buf
, 2);
874 return extract_unsigned_integer (buf
, 2);
878 unpack_mips16 (CORE_ADDR pc
,
879 struct upk_mips16
*upk
)
882 unsigned long extension
;
884 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
885 /* Decrement to previous address and loose the 16bit mode flag */
886 /* return if the instruction was extendable, but not actually extended */
887 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
890 extension
= mips_fetch_instruction (extpc
);
899 value
= extended_offset (extension
);
900 value
= value
<< 11; /* rom for the original value */
901 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
905 value
= upk
->inst
& 0x7ff;
906 /* FIXME : Consider sign extension */
913 { /* A register identifier and an offset */
914 /* Most of the fields are the same as I type but the
915 immediate value is of a different length */
919 value
= extended_offset (extension
);
920 value
= value
<< 8; /* from the original instruction */
921 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
922 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
923 if (value
& 0x4000) /* test the sign bit , bit 26 */
925 value
&= ~0x3fff; /* remove the sign bit */
931 value
= upk
->inst
& 0xff; /* 8 bits */
932 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
933 /* FIXME: Do sign extension , this format needs it */
934 if (value
& 0x80) /* THIS CONFUSES ME */
936 value
&= 0xef; /* remove the sign bit */
947 unsigned short nexthalf
;
948 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
950 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
956 printf_filtered ("Decoding unimplemented instruction format type\n");
959 /* print_unpack("UPK",upk) ; */
963 #define mips16_op(x) (x >> 11)
965 /* This is a map of the opcodes which ae known to perform branches */
966 static unsigned char map16
[32] =
967 {0, 0, 1, 1, 1, 1, 0, 0,
968 0, 0, 0, 0, 1, 0, 0, 0,
969 0, 0, 0, 0, 0, 0, 0, 0,
970 0, 0, 0, 0, 0, 1, 1, 0
974 add_offset_16 (CORE_ADDR pc
, int offset
)
976 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
982 static struct upk_mips16 upk
;
985 mips16_next_pc (CORE_ADDR pc
)
989 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
990 inst
= fetch_mips_16 (pc
);
992 op
= mips16_op (upk
.inst
);
1000 unpack_mips16 (pc
, &upk
);
1003 offset
= upk
.offset
;
1009 pc
+= (offset
<< 1) + 2;
1012 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1014 unpack_mips16 (pc
, &upk
);
1015 pc
= add_offset_16 (pc
, upk
.offset
);
1016 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
1017 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1023 unpack_mips16 (pc
, &upk
);
1024 reg
= read_register (upk
.regx
);
1026 pc
+= (upk
.offset
<< 1) + 2;
1032 unpack_mips16 (pc
, &upk
);
1033 reg
= read_register (upk
.regx
);
1035 pc
+= (upk
.offset
<< 1) + 2;
1039 case 12: /* I8 Formats btez btnez */
1041 unpack_mips16 (pc
, &upk
);
1042 /* upk.regx contains the opcode */
1043 reg
= read_register (24); /* Test register is 24 */
1044 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1045 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1046 /* pc = add_offset_16(pc,upk.offset) ; */
1047 pc
+= (upk
.offset
<< 1) + 2;
1051 case 29: /* RR Formats JR, JALR, JALR-RA */
1053 op
= upk
.inst
& 0x1f;
1056 upk
.regx
= (upk
.inst
>> 8) & 0x07;
1057 upk
.regy
= (upk
.inst
>> 5) & 0x07;
1065 break; /* Function return instruction */
1071 break; /* BOGUS Guess */
1073 pc
= read_register (reg
);
1078 case 30: /* This is an extend instruction */
1079 pc
+= 4; /* Dont be setting breakpints on the second half */
1082 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
1088 pc
+= 2; /* just a good old instruction */
1089 /* See if we CAN actually break on the next instruction */
1090 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
1092 } /* mips16_next_pc */
1094 /* The mips_next_pc function supports single_tep when the remote target monitor or
1095 stub is not developed enough to so a single_step.
1096 It works by decoding the current instruction and predicting where a branch
1097 will go. This isnt hard because all the data is available.
1098 The MIPS32 and MIPS16 variants are quite different
1101 mips_next_pc (CORE_ADDR pc
)
1104 /* inst = mips_fetch_instruction(pc) ; */
1105 /* if (pc_is_mips16) <----- This is failing */
1107 return mips16_next_pc (pc
);
1109 return mips32_next_pc (pc
);
1110 } /* mips_next_pc */
1112 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1116 mips_find_saved_regs (fci
)
1117 struct frame_info
*fci
;
1120 CORE_ADDR reg_position
;
1121 /* r0 bit means kernel trap */
1123 /* What registers have been saved? Bitmasks. */
1124 unsigned long gen_mask
, float_mask
;
1125 mips_extra_func_info_t proc_desc
;
1128 frame_saved_regs_zalloc (fci
);
1130 /* If it is the frame for sigtramp, the saved registers are located
1131 in a sigcontext structure somewhere on the stack.
1132 If the stack layout for sigtramp changes we might have to change these
1133 constants and the companion fixup_sigtramp in mdebugread.c */
1134 #ifndef SIGFRAME_BASE
1135 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1136 above the sigtramp frame. */
1137 #define SIGFRAME_BASE MIPS_REGSIZE
1138 /* FIXME! Are these correct?? */
1139 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1140 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1141 #define SIGFRAME_FPREGSAVE_OFF \
1142 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1144 #ifndef SIGFRAME_REG_SIZE
1145 /* FIXME! Is this correct?? */
1146 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1148 if (fci
->signal_handler_caller
)
1150 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1152 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1153 + ireg
* SIGFRAME_REG_SIZE
;
1154 fci
->saved_regs
[ireg
] = reg_position
;
1156 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1158 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1159 + ireg
* SIGFRAME_REG_SIZE
;
1160 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1162 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1166 proc_desc
= fci
->extra_info
->proc_desc
;
1167 if (proc_desc
== NULL
)
1168 /* I'm not sure how/whether this can happen. Normally when we can't
1169 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1170 and set the saved_regs right away. */
1173 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1174 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1175 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1177 if ( /* In any frame other than the innermost or a frame interrupted by
1178 a signal, we assume that all registers have been saved.
1179 This assumes that all register saves in a function happen before
1180 the first function call. */
1181 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1183 /* In a dummy frame we know exactly where things are saved. */
1184 && !PROC_DESC_IS_DUMMY (proc_desc
)
1186 /* Don't bother unless we are inside a function prologue. Outside the
1187 prologue, we know where everything is. */
1189 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1191 /* Not sure exactly what kernel_trap means, but if it means
1192 the kernel saves the registers without a prologue doing it,
1193 we better not examine the prologue to see whether registers
1194 have been saved yet. */
1197 /* We need to figure out whether the registers that the proc_desc
1198 claims are saved have been saved yet. */
1202 /* Bitmasks; set if we have found a save for the register. */
1203 unsigned long gen_save_found
= 0;
1204 unsigned long float_save_found
= 0;
1207 /* If the address is odd, assume this is MIPS16 code. */
1208 addr
= PROC_LOW_ADDR (proc_desc
);
1209 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1211 /* Scan through this function's instructions preceding the current
1212 PC, and look for those that save registers. */
1213 while (addr
< fci
->pc
)
1215 inst
= mips_fetch_instruction (addr
);
1216 if (pc_is_mips16 (addr
))
1217 mips16_decode_reg_save (inst
, &gen_save_found
);
1219 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1222 gen_mask
= gen_save_found
;
1223 float_mask
= float_save_found
;
1226 /* Fill in the offsets for the registers which gen_mask says
1228 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1229 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1230 if (gen_mask
& 0x80000000)
1232 fci
->saved_regs
[ireg
] = reg_position
;
1233 reg_position
-= MIPS_SAVED_REGSIZE
;
1236 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1237 of that normally used by gcc. Therefore, we have to fetch the first
1238 instruction of the function, and if it's an entry instruction that
1239 saves $s0 or $s1, correct their saved addresses. */
1240 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1242 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1243 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1246 int sreg_count
= (inst
>> 6) & 3;
1248 /* Check if the ra register was pushed on the stack. */
1249 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1251 reg_position
-= MIPS_SAVED_REGSIZE
;
1253 /* Check if the s0 and s1 registers were pushed on the stack. */
1254 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1256 fci
->saved_regs
[reg
] = reg_position
;
1257 reg_position
-= MIPS_SAVED_REGSIZE
;
1262 /* Fill in the offsets for the registers which float_mask says
1264 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1266 /* The freg_offset points to where the first *double* register
1267 is saved. So skip to the high-order word. */
1268 if (!GDB_TARGET_IS_MIPS64
)
1269 reg_position
+= MIPS_SAVED_REGSIZE
;
1271 /* Fill in the offsets for the float registers which float_mask says
1273 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1274 if (float_mask
& 0x80000000)
1276 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1277 reg_position
-= MIPS_SAVED_REGSIZE
;
1280 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1284 read_next_frame_reg (fi
, regno
)
1285 struct frame_info
*fi
;
1288 for (; fi
; fi
= fi
->next
)
1290 /* We have to get the saved sp from the sigcontext
1291 if it is a signal handler frame. */
1292 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1296 if (fi
->saved_regs
== NULL
)
1297 mips_find_saved_regs (fi
);
1298 if (fi
->saved_regs
[regno
])
1299 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1302 return read_register (regno
);
1305 /* mips_addr_bits_remove - remove useless address bits */
1308 mips_addr_bits_remove (addr
)
1311 #if GDB_TARGET_IS_MIPS64
1312 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1314 /* This hack is a work-around for existing boards using PMON,
1315 the simulator, and any other 64-bit targets that doesn't have
1316 true 64-bit addressing. On these targets, the upper 32 bits
1317 of addresses are ignored by the hardware. Thus, the PC or SP
1318 are likely to have been sign extended to all 1s by instruction
1319 sequences that load 32-bit addresses. For example, a typical
1320 piece of code that loads an address is this:
1321 lui $r2, <upper 16 bits>
1322 ori $r2, <lower 16 bits>
1323 But the lui sign-extends the value such that the upper 32 bits
1324 may be all 1s. The workaround is simply to mask off these bits.
1325 In the future, gcc may be changed to support true 64-bit
1326 addressing, and this masking will have to be disabled. */
1327 addr
&= (CORE_ADDR
) 0xffffffff;
1330 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1331 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1332 So we still have to mask off useless bits from addresses. */
1333 addr
&= (CORE_ADDR
) 0xffffffff;
1340 mips_init_frame_pc_first (fromleaf
, prev
)
1342 struct frame_info
*prev
;
1346 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1347 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1348 tmp
= mips_skip_stub (pc
);
1349 prev
->pc
= tmp
? tmp
: pc
;
1354 mips_frame_saved_pc (frame
)
1355 struct frame_info
*frame
;
1358 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1359 /* We have to get the saved pc from the sigcontext
1360 if it is a signal handler frame. */
1361 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1362 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1364 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1365 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1367 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1369 return ADDR_BITS_REMOVE (saved_pc
);
1372 static struct mips_extra_func_info temp_proc_desc
;
1373 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1375 /* Set a register's saved stack address in temp_saved_regs. If an address
1376 has already been set for this register, do nothing; this way we will
1377 only recognize the first save of a given register in a function prologue.
1378 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1381 set_reg_offset (regno
, offset
)
1385 if (temp_saved_regs
[regno
] == 0)
1386 temp_saved_regs
[regno
] = offset
;
1390 /* Test whether the PC points to the return instruction at the
1391 end of a function. */
1394 mips_about_to_return (pc
)
1397 if (pc_is_mips16 (pc
))
1398 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1399 generates a "jr $ra"; other times it generates code to load
1400 the return address from the stack to an accessible register (such
1401 as $a3), then a "jr" using that register. This second case
1402 is almost impossible to distinguish from an indirect jump
1403 used for switch statements, so we don't even try. */
1404 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1406 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1410 /* This fencepost looks highly suspicious to me. Removing it also
1411 seems suspicious as it could affect remote debugging across serial
1415 heuristic_proc_start (pc
)
1423 pc
= ADDR_BITS_REMOVE (pc
);
1425 fence
= start_pc
- heuristic_fence_post
;
1429 if (heuristic_fence_post
== UINT_MAX
1430 || fence
< VM_MIN_ADDRESS
)
1431 fence
= VM_MIN_ADDRESS
;
1433 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1435 /* search back for previous return */
1436 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1437 if (start_pc
< fence
)
1439 /* It's not clear to me why we reach this point when
1440 stop_soon_quietly, but with this test, at least we
1441 don't print out warnings for every child forked (eg, on
1442 decstation). 22apr93 rich@cygnus.com. */
1443 if (!stop_soon_quietly
)
1445 static int blurb_printed
= 0;
1447 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1452 /* This actually happens frequently in embedded
1453 development, when you first connect to a board
1454 and your stack pointer and pc are nowhere in
1455 particular. This message needs to give people
1456 in that situation enough information to
1457 determine that it's no big deal. */
1458 printf_filtered ("\n\
1459 GDB is unable to find the start of the function at 0x%s\n\
1460 and thus can't determine the size of that function's stack frame.\n\
1461 This means that GDB may be unable to access that stack frame, or\n\
1462 the frames below it.\n\
1463 This problem is most likely caused by an invalid program counter or\n\
1465 However, if you think GDB should simply search farther back\n\
1466 from 0x%s for code which looks like the beginning of a\n\
1467 function, you can increase the range of the search using the `set\n\
1468 heuristic-fence-post' command.\n",
1469 paddr_nz (pc
), paddr_nz (pc
));
1476 else if (pc_is_mips16 (start_pc
))
1478 unsigned short inst
;
1480 /* On MIPS16, any one of the following is likely to be the
1481 start of a function:
1485 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1486 inst
= mips_fetch_instruction (start_pc
);
1487 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1488 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1489 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1490 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1492 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1493 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1498 else if (mips_about_to_return (start_pc
))
1500 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1505 /* skip nops (usually 1) 0 - is this */
1506 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1507 start_pc
+= MIPS_INSTLEN
;
1512 /* Fetch the immediate value from a MIPS16 instruction.
1513 If the previous instruction was an EXTEND, use it to extend
1514 the upper bits of the immediate value. This is a helper function
1515 for mips16_heuristic_proc_desc. */
1518 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1519 unsigned short prev_inst
; /* previous instruction */
1520 unsigned short inst
; /* current instruction */
1521 int nbits
; /* number of bits in imm field */
1522 int scale
; /* scale factor to be applied to imm */
1523 int is_signed
; /* is the imm field signed? */
1527 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1529 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1530 if (offset
& 0x8000) /* check for negative extend */
1531 offset
= 0 - (0x10000 - (offset
& 0xffff));
1532 return offset
| (inst
& 0x1f);
1536 int max_imm
= 1 << nbits
;
1537 int mask
= max_imm
- 1;
1538 int sign_bit
= max_imm
>> 1;
1540 offset
= inst
& mask
;
1541 if (is_signed
&& (offset
& sign_bit
))
1542 offset
= 0 - (max_imm
- offset
);
1543 return offset
* scale
;
1548 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1549 stream from start_pc to limit_pc. */
1552 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1553 CORE_ADDR start_pc
, limit_pc
;
1554 struct frame_info
*next_frame
;
1558 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1559 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1560 unsigned inst
= 0; /* current instruction */
1561 unsigned entry_inst
= 0; /* the entry instruction */
1564 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1565 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1567 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1569 /* Save the previous instruction. If it's an EXTEND, we'll extract
1570 the immediate offset extension from it in mips16_get_imm. */
1573 /* Fetch and decode the instruction. */
1574 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1575 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1576 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1578 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1579 if (offset
< 0) /* negative stack adjustment? */
1580 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1582 /* Exit loop if a positive stack adjustment is found, which
1583 usually means that the stack cleanup code in the function
1584 epilogue is reached. */
1587 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1589 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1590 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1591 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1592 set_reg_offset (reg
, sp
+ offset
);
1594 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1596 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1597 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1598 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1599 set_reg_offset (reg
, sp
+ offset
);
1601 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1603 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1604 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1605 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1607 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1609 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1610 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1611 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1613 else if (inst
== 0x673d) /* move $s1, $sp */
1616 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1618 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1620 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1621 frame_addr
= sp
+ offset
;
1622 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1623 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1625 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1627 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1628 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1629 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1630 set_reg_offset (reg
, frame_addr
+ offset
);
1632 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1634 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1635 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1636 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1637 set_reg_offset (reg
, frame_addr
+ offset
);
1639 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1640 entry_inst
= inst
; /* save for later processing */
1641 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1642 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1645 /* The entry instruction is typically the first instruction in a function,
1646 and it stores registers at offsets relative to the value of the old SP
1647 (before the prologue). But the value of the sp parameter to this
1648 function is the new SP (after the prologue has been executed). So we
1649 can't calculate those offsets until we've seen the entire prologue,
1650 and can calculate what the old SP must have been. */
1651 if (entry_inst
!= 0)
1653 int areg_count
= (entry_inst
>> 8) & 7;
1654 int sreg_count
= (entry_inst
>> 6) & 3;
1656 /* The entry instruction always subtracts 32 from the SP. */
1657 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1659 /* Now we can calculate what the SP must have been at the
1660 start of the function prologue. */
1661 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1663 /* Check if a0-a3 were saved in the caller's argument save area. */
1664 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1666 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1667 set_reg_offset (reg
, sp
+ offset
);
1668 offset
+= MIPS_SAVED_REGSIZE
;
1671 /* Check if the ra register was pushed on the stack. */
1673 if (entry_inst
& 0x20)
1675 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1676 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1677 offset
-= MIPS_SAVED_REGSIZE
;
1680 /* Check if the s0 and s1 registers were pushed on the stack. */
1681 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1683 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1684 set_reg_offset (reg
, sp
+ offset
);
1685 offset
-= MIPS_SAVED_REGSIZE
;
1691 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1692 CORE_ADDR start_pc
, limit_pc
;
1693 struct frame_info
*next_frame
;
1697 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1699 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1700 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1701 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1702 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1704 unsigned long inst
, high_word
, low_word
;
1707 /* Fetch the instruction. */
1708 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1710 /* Save some code by pre-extracting some useful fields. */
1711 high_word
= (inst
>> 16) & 0xffff;
1712 low_word
= inst
& 0xffff;
1713 reg
= high_word
& 0x1f;
1715 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1716 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1717 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1719 if (low_word
& 0x8000) /* negative stack adjustment? */
1720 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1722 /* Exit loop if a positive stack adjustment is found, which
1723 usually means that the stack cleanup code in the function
1724 epilogue is reached. */
1727 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1729 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1730 set_reg_offset (reg
, sp
+ low_word
);
1732 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1734 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1735 but the register size used is only 32 bits. Make the address
1736 for the saved register point to the lower 32 bits. */
1737 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1738 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1740 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1742 /* Old gcc frame, r30 is virtual frame pointer. */
1743 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1744 frame_addr
= sp
+ low_word
;
1745 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1747 unsigned alloca_adjust
;
1748 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1749 frame_addr
= read_next_frame_reg (next_frame
, 30);
1750 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1751 if (alloca_adjust
> 0)
1753 /* FP > SP + frame_size. This may be because
1754 * of an alloca or somethings similar.
1755 * Fix sp to "pre-alloca" value, and try again.
1757 sp
+= alloca_adjust
;
1762 /* move $30,$sp. With different versions of gas this will be either
1763 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1764 Accept any one of these. */
1765 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1767 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1768 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1770 unsigned alloca_adjust
;
1771 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1772 frame_addr
= read_next_frame_reg (next_frame
, 30);
1773 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1774 if (alloca_adjust
> 0)
1776 /* FP > SP + frame_size. This may be because
1777 * of an alloca or somethings similar.
1778 * Fix sp to "pre-alloca" value, and try again.
1780 sp
+= alloca_adjust
;
1785 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1787 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1788 set_reg_offset (reg
, frame_addr
+ low_word
);
1793 static mips_extra_func_info_t
1794 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1795 CORE_ADDR start_pc
, limit_pc
;
1796 struct frame_info
*next_frame
;
1798 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1802 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1803 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1804 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1805 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1806 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1808 if (start_pc
+ 200 < limit_pc
)
1809 limit_pc
= start_pc
+ 200;
1810 if (pc_is_mips16 (start_pc
))
1811 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1813 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1814 return &temp_proc_desc
;
1817 static mips_extra_func_info_t
1818 non_heuristic_proc_desc (pc
, addrptr
)
1822 CORE_ADDR startaddr
;
1823 mips_extra_func_info_t proc_desc
;
1824 struct block
*b
= block_for_pc (pc
);
1827 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1829 *addrptr
= startaddr
;
1830 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1834 if (startaddr
> BLOCK_START (b
))
1835 /* This is the "pathological" case referred to in a comment in
1836 print_frame_info. It might be better to move this check into
1840 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1843 /* If we never found a PDR for this function in symbol reading, then
1844 examine prologues to find the information. */
1847 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1848 if (PROC_FRAME_REG (proc_desc
) == -1)
1858 static mips_extra_func_info_t
1859 find_proc_desc (pc
, next_frame
)
1861 struct frame_info
*next_frame
;
1863 mips_extra_func_info_t proc_desc
;
1864 CORE_ADDR startaddr
;
1866 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1870 /* IF this is the topmost frame AND
1871 * (this proc does not have debugging information OR
1872 * the PC is in the procedure prologue)
1873 * THEN create a "heuristic" proc_desc (by analyzing
1874 * the actual code) to replace the "official" proc_desc.
1876 if (next_frame
== NULL
)
1878 struct symtab_and_line val
;
1879 struct symbol
*proc_symbol
=
1880 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1884 val
= find_pc_line (BLOCK_START
1885 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1887 val
.pc
= val
.end
? val
.end
: pc
;
1889 if (!proc_symbol
|| pc
< val
.pc
)
1891 mips_extra_func_info_t found_heuristic
=
1892 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1894 if (found_heuristic
)
1895 proc_desc
= found_heuristic
;
1901 /* Is linked_proc_desc_table really necessary? It only seems to be used
1902 by procedure call dummys. However, the procedures being called ought
1903 to have their own proc_descs, and even if they don't,
1904 heuristic_proc_desc knows how to create them! */
1906 register struct linked_proc_info
*link
;
1908 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1909 if (PROC_LOW_ADDR (&link
->info
) <= pc
1910 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1914 startaddr
= heuristic_proc_start (pc
);
1917 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1923 get_frame_pointer (frame
, proc_desc
)
1924 struct frame_info
*frame
;
1925 mips_extra_func_info_t proc_desc
;
1927 return ADDR_BITS_REMOVE (
1928 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1929 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1932 mips_extra_func_info_t cached_proc_desc
;
1935 mips_frame_chain (frame
)
1936 struct frame_info
*frame
;
1938 mips_extra_func_info_t proc_desc
;
1940 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1942 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1945 /* Check if the PC is inside a call stub. If it is, fetch the
1946 PC of the caller of that stub. */
1947 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1950 /* Look up the procedure descriptor for this PC. */
1951 proc_desc
= find_proc_desc (saved_pc
, frame
);
1955 cached_proc_desc
= proc_desc
;
1957 /* If no frame pointer and frame size is zero, we must be at end
1958 of stack (or otherwise hosed). If we don't check frame size,
1959 we loop forever if we see a zero size frame. */
1960 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1961 && PROC_FRAME_OFFSET (proc_desc
) == 0
1962 /* The previous frame from a sigtramp frame might be frameless
1963 and have frame size zero. */
1964 && !frame
->signal_handler_caller
)
1967 return get_frame_pointer (frame
, proc_desc
);
1971 mips_init_extra_frame_info (fromleaf
, fci
)
1973 struct frame_info
*fci
;
1977 /* Use proc_desc calculated in frame_chain */
1978 mips_extra_func_info_t proc_desc
=
1979 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1981 fci
->extra_info
= (struct frame_extra_info
*)
1982 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1984 fci
->saved_regs
= NULL
;
1985 fci
->extra_info
->proc_desc
=
1986 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1989 /* Fixup frame-pointer - only needed for top frame */
1990 /* This may not be quite right, if proc has a real frame register.
1991 Get the value of the frame relative sp, procedure might have been
1992 interrupted by a signal at it's very start. */
1993 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1994 && !PROC_DESC_IS_DUMMY (proc_desc
))
1995 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1997 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1999 if (proc_desc
== &temp_proc_desc
)
2003 /* Do not set the saved registers for a sigtramp frame,
2004 mips_find_saved_registers will do that for us.
2005 We can't use fci->signal_handler_caller, it is not yet set. */
2006 find_pc_partial_function (fci
->pc
, &name
,
2007 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2008 if (!IN_SIGTRAMP (fci
->pc
, name
))
2010 frame_saved_regs_zalloc (fci
);
2011 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2012 fci
->saved_regs
[PC_REGNUM
]
2013 = fci
->saved_regs
[RA_REGNUM
];
2017 /* hack: if argument regs are saved, guess these contain args */
2018 /* assume we can't tell how many args for now */
2019 fci
->extra_info
->num_args
= -1;
2020 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2022 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2024 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2031 /* MIPS stack frames are almost impenetrable. When execution stops,
2032 we basically have to look at symbol information for the function
2033 that we stopped in, which tells us *which* register (if any) is
2034 the base of the frame pointer, and what offset from that register
2035 the frame itself is at.
2037 This presents a problem when trying to examine a stack in memory
2038 (that isn't executing at the moment), using the "frame" command. We
2039 don't have a PC, nor do we have any registers except SP.
2041 This routine takes two arguments, SP and PC, and tries to make the
2042 cached frames look as if these two arguments defined a frame on the
2043 cache. This allows the rest of info frame to extract the important
2044 arguments without difficulty. */
2047 setup_arbitrary_frame (argc
, argv
)
2052 error ("MIPS frame specifications require two arguments: sp and pc");
2054 return create_new_frame (argv
[0], argv
[1]);
2058 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
2063 CORE_ADDR struct_addr
;
2069 int stack_offset
= 0;
2071 /* Macros to round N up or down to the next A boundary; A must be
2073 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2074 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2076 /* First ensure that the stack and structure return address (if any)
2077 are properly aligned. The stack has to be at least 64-bit aligned
2078 even on 32-bit machines, because doubles must be 64-bit aligned.
2079 On at least one MIPS variant, stack frames need to be 128-bit
2080 aligned, so we round to this widest known alignment. */
2081 sp
= ROUND_DOWN (sp
, 16);
2082 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
2084 /* Now make space on the stack for the args. We allocate more
2085 than necessary for EABI, because the first few arguments are
2086 passed in registers, but that's OK. */
2087 for (argnum
= 0; argnum
< nargs
; argnum
++)
2088 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_SAVED_REGSIZE
);
2089 sp
-= ROUND_UP (len
, 16);
2091 /* Initialize the integer and float register pointers. */
2093 float_argreg
= FPA0_REGNUM
;
2095 /* the struct_return pointer occupies the first parameter-passing reg */
2097 write_register (argreg
++, struct_addr
);
2099 /* Now load as many as possible of the first arguments into
2100 registers, and push the rest onto the stack. Loop thru args
2101 from first to last. */
2102 for (argnum
= 0; argnum
< nargs
; argnum
++)
2105 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2106 value_ptr arg
= args
[argnum
];
2107 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2108 int len
= TYPE_LENGTH (arg_type
);
2109 enum type_code typecode
= TYPE_CODE (arg_type
);
2111 /* The EABI passes structures that do not fit in a register by
2112 reference. In all other cases, pass the structure by value. */
2113 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
2114 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2116 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2117 typecode
= TYPE_CODE_PTR
;
2118 len
= MIPS_SAVED_REGSIZE
;
2122 val
= (char *) VALUE_CONTENTS (arg
);
2124 /* 32-bit ABIs always start floating point arguments in an
2125 even-numbered floating point register. */
2126 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
2127 && (float_argreg
& 1))
2130 /* Floating point arguments passed in registers have to be
2131 treated specially. On 32-bit architectures, doubles
2132 are passed in register pairs; the even register gets
2133 the low word, and the odd register gets the high word.
2134 On non-EABI processors, the first two floating point arguments are
2135 also copied to general registers, because MIPS16 functions
2136 don't use float registers for arguments. This duplication of
2137 arguments in general registers can't hurt non-MIPS16 functions
2138 because those registers are normally skipped. */
2139 if (typecode
== TYPE_CODE_FLT
2140 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
2141 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2143 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2145 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2146 unsigned long regval
;
2148 /* Write the low word of the double to the even register(s). */
2149 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2150 write_register (float_argreg
++, regval
);
2152 write_register (argreg
+ 1, regval
);
2154 /* Write the high word of the double to the odd register(s). */
2155 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2156 write_register (float_argreg
++, regval
);
2159 write_register (argreg
, regval
);
2166 /* This is a floating point value that fits entirely
2167 in a single register. */
2168 /* On 32 bit ABI's the float_argreg is further adjusted
2169 above to ensure that it is even register aligned. */
2170 CORE_ADDR regval
= extract_address (val
, len
);
2171 write_register (float_argreg
++, regval
);
2174 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2175 registers for each argument. The below is (my
2176 guess) to ensure that the corresponding integer
2177 register has reserved the same space. */
2178 write_register (argreg
, regval
);
2179 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2185 /* Copy the argument to general registers or the stack in
2186 register-sized pieces. Large arguments are split between
2187 registers and stack. */
2188 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2189 are treated specially: Irix cc passes them in registers
2190 where gcc sometimes puts them on the stack. For maximum
2191 compatibility, we will put them in both places. */
2193 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2194 (len
% MIPS_SAVED_REGSIZE
!= 0));
2197 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2199 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
2201 /* Write this portion of the argument to the stack. */
2202 /* Should shorter than int integer values be
2203 promoted to int before being stored? */
2205 int longword_offset
= 0;
2206 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2208 if (MIPS_STACK_ARGSIZE
== 8 &&
2209 (typecode
== TYPE_CODE_INT
||
2210 typecode
== TYPE_CODE_PTR
||
2211 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2212 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2213 else if ((typecode
== TYPE_CODE_STRUCT
||
2214 typecode
== TYPE_CODE_UNION
) &&
2215 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2216 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2219 write_memory (sp
+ stack_offset
+ longword_offset
,
2223 /* Note!!! This is NOT an else clause.
2224 Odd sized structs may go thru BOTH paths. */
2225 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
2227 CORE_ADDR regval
= extract_address (val
, partial_len
);
2229 /* A non-floating-point argument being passed in a
2230 general register. If a struct or union, and if
2231 the remaining length is smaller than the register
2232 size, we have to adjust the register value on
2235 It does not seem to be necessary to do the
2236 same for integral types.
2238 Also don't do this adjustment on EABI and O64
2242 && MIPS_SAVED_REGSIZE
< 8
2243 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2244 && partial_len
< MIPS_SAVED_REGSIZE
2245 && (typecode
== TYPE_CODE_STRUCT
||
2246 typecode
== TYPE_CODE_UNION
))
2247 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2250 write_register (argreg
, regval
);
2253 /* If this is the old ABI, prevent subsequent floating
2254 point arguments from being passed in floating point
2257 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2263 /* The offset onto the stack at which we will start
2264 copying parameters (after the registers are used up)
2265 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2266 leaves room for the "home" area for register parameters.
2268 In the new EABI (and the NABI32), the 8 register parameters
2269 do not have "home" stack space reserved for them, so the
2270 stack offset does not get incremented until after
2271 we have used up the 8 parameter registers. */
2273 if (MIPS_REGS_HAVE_HOME_P
|| argnum
>= 8)
2274 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2279 /* Return adjusted stack pointer. */
2284 mips_push_return_address (pc
, sp
)
2288 /* Set the return address register to point to the entry
2289 point of the program, where a breakpoint lies in wait. */
2290 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2295 mips_push_register (CORE_ADDR
* sp
, int regno
)
2297 char buffer
[MAX_REGISTER_RAW_SIZE
];
2300 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2302 regsize
= MIPS_SAVED_REGSIZE
;
2303 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2304 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2309 regsize
= REGISTER_RAW_SIZE (regno
);
2313 read_register_gen (regno
, buffer
);
2314 write_memory (*sp
, buffer
+ offset
, regsize
);
2317 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2318 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2321 mips_push_dummy_frame ()
2324 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2325 xmalloc (sizeof (struct linked_proc_info
));
2326 mips_extra_func_info_t proc_desc
= &link
->info
;
2327 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2328 CORE_ADDR old_sp
= sp
;
2329 link
->next
= linked_proc_desc_table
;
2330 linked_proc_desc_table
= link
;
2332 /* FIXME! are these correct ? */
2333 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2334 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2335 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2336 #define FLOAT_SINGLE_REG_SAVE_MASK \
2337 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2339 * The registers we must save are all those not preserved across
2340 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2341 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2342 * and FP Control/Status registers.
2345 * Dummy frame layout:
2348 * Saved MMHI, MMLO, FPC_CSR
2353 * Saved D18 (i.e. F19, F18)
2355 * Saved D0 (i.e. F1, F0)
2356 * Argument build area and stack arguments written via mips_push_arguments
2360 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2361 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2362 PROC_FRAME_OFFSET (proc_desc
) = 0;
2363 PROC_FRAME_ADJUST (proc_desc
) = 0;
2364 mips_push_register (&sp
, PC_REGNUM
);
2365 mips_push_register (&sp
, HI_REGNUM
);
2366 mips_push_register (&sp
, LO_REGNUM
);
2367 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2369 /* Save general CPU registers */
2370 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2371 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2372 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2373 for (ireg
= 32; --ireg
>= 0;)
2374 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2375 mips_push_register (&sp
, ireg
);
2377 /* Save floating point registers starting with high order word */
2378 PROC_FREG_MASK (proc_desc
) =
2379 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2380 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2381 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2383 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2384 for (ireg
= 32; --ireg
>= 0;)
2385 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2386 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2388 /* Update the frame pointer for the call dummy and the stack pointer.
2389 Set the procedure's starting and ending addresses to point to the
2390 call dummy address at the entry point. */
2391 write_register (PUSH_FP_REGNUM
, old_sp
);
2392 write_register (SP_REGNUM
, sp
);
2393 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2394 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2395 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2396 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2402 register int regnum
;
2403 struct frame_info
*frame
= get_current_frame ();
2404 CORE_ADDR new_sp
= FRAME_FP (frame
);
2406 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2408 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2409 if (frame
->saved_regs
== NULL
)
2410 mips_find_saved_regs (frame
);
2411 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2413 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2414 && frame
->saved_regs
[regnum
])
2415 write_register (regnum
,
2416 read_memory_integer (frame
->saved_regs
[regnum
],
2417 MIPS_SAVED_REGSIZE
));
2419 write_register (SP_REGNUM
, new_sp
);
2420 flush_cached_frames ();
2422 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2424 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2426 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2428 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2430 if (&pi_ptr
->info
== proc_desc
)
2435 error ("Can't locate dummy extra frame info\n");
2437 if (prev_ptr
!= NULL
)
2438 prev_ptr
->next
= pi_ptr
->next
;
2440 linked_proc_desc_table
= pi_ptr
->next
;
2444 write_register (HI_REGNUM
,
2445 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2446 MIPS_SAVED_REGSIZE
));
2447 write_register (LO_REGNUM
,
2448 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2449 MIPS_SAVED_REGSIZE
));
2450 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2451 write_register (FCRCS_REGNUM
,
2452 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2453 MIPS_SAVED_REGSIZE
));
2458 mips_print_register (regnum
, all
)
2461 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2463 /* Get the data in raw format. */
2464 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2466 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2470 /* If an even floating point register, also print as double. */
2471 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2472 && !((regnum
- FP0_REGNUM
) & 1))
2473 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2475 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2477 read_relative_register_raw_bytes (regnum
, dbuffer
);
2478 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2479 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2481 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2482 val_print (builtin_type_double
, dbuffer
, 0, 0,
2483 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2484 printf_filtered ("); ");
2486 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2488 /* The problem with printing numeric register names (r26, etc.) is that
2489 the user can't use them on input. Probably the best solution is to
2490 fix it so that either the numeric or the funky (a2, etc.) names
2491 are accepted on input. */
2492 if (regnum
< MIPS_NUMREGS
)
2493 printf_filtered ("(r%d): ", regnum
);
2495 printf_filtered (": ");
2497 /* If virtual format is floating, print it that way. */
2498 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2499 if (FP_REGISTER_DOUBLE
)
2500 { /* show 8-byte floats as float AND double: */
2501 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2503 printf_filtered (" (float) ");
2504 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2505 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2506 printf_filtered (", (double) ");
2507 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2508 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2511 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2512 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2513 /* Else print as integer in hex. */
2518 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2519 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2523 print_scalar_formatted (raw_buffer
+ offset
,
2524 REGISTER_VIRTUAL_TYPE (regnum
),
2525 'x', 0, gdb_stdout
);
2529 /* Replacement for generic do_registers_info.
2530 Print regs in pretty columns. */
2533 do_fp_register_row (regnum
)
2535 { /* do values for FP (float) regs */
2536 char *raw_buffer
[2];
2538 /* use HI and LO to control the order of combining two flt regs */
2539 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2540 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2541 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2542 int inv1
, inv2
, inv3
;
2544 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2545 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2546 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2548 /* Get the data in raw format. */
2549 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2550 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2551 if (REGISTER_RAW_SIZE (regnum
) == 4)
2553 /* 4-byte registers: we can fit two registers per row. */
2554 /* Also print every pair of 4-byte regs as an 8-byte double. */
2555 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2556 error ("can't read register %d (%s)",
2557 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2559 /* copy the two floats into one double, and unpack both */
2560 memcpy (dbl_buffer
, raw_buffer
, 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2561 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2562 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2563 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2565 printf_filtered (inv1
? " %-5s: <invalid float>" :
2566 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2567 printf_filtered (inv2
? " %-5s: <invalid float>" :
2568 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2569 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2570 " dbl: %-24.17g\n", doub
);
2571 /* may want to do hex display here (future enhancement) */
2575 { /* eight byte registers: print each one as float AND as double. */
2576 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2578 memcpy (dbl_buffer
, raw_buffer
[HI
], 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2579 flt1
= unpack_double (builtin_type_float
,
2580 &raw_buffer
[HI
][offset
], &inv1
);
2581 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2583 printf_filtered (inv1
? " %-5s: <invalid float>" :
2584 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2585 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2586 " dbl: %-24.17g\n", doub
);
2587 /* may want to do hex display here (future enhancement) */
2593 /* Print a row's worth of GP (int) registers, with name labels above */
2596 do_gp_register_row (regnum
)
2599 /* do values for GP (int) regs */
2600 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2601 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2603 int start_regnum
= regnum
;
2604 int numregs
= NUM_REGS
;
2607 /* For GP registers, we print a separate row of names above the vals */
2608 printf_filtered (" ");
2609 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2611 if (*REGISTER_NAME (regnum
) == '\0')
2612 continue; /* unused register */
2613 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2614 break; /* end the row: reached FP register */
2615 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2616 REGISTER_NAME (regnum
));
2619 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2620 start_regnum
); /* print the R0 to R31 names */
2622 regnum
= start_regnum
; /* go back to start of row */
2623 /* now print the values in hex, 4 or 8 to the row */
2624 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2626 if (*REGISTER_NAME (regnum
) == '\0')
2627 continue; /* unused register */
2628 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2629 break; /* end row: reached FP register */
2630 /* OK: get the data in raw format. */
2631 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2632 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2633 /* pad small registers */
2634 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2635 printf_filtered (" ");
2636 /* Now print the register value in hex, endian order. */
2637 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2638 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2639 byte
< REGISTER_RAW_SIZE (regnum
);
2641 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2643 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2646 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2647 printf_filtered (" ");
2650 if (col
> 0) /* ie. if we actually printed anything... */
2651 printf_filtered ("\n");
2656 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2659 mips_do_registers_info (regnum
, fpregs
)
2663 if (regnum
!= -1) /* do one specified register */
2665 if (*(REGISTER_NAME (regnum
)) == '\0')
2666 error ("Not a valid register for the current processor type");
2668 mips_print_register (regnum
, 0);
2669 printf_filtered ("\n");
2672 /* do all (or most) registers */
2675 while (regnum
< NUM_REGS
)
2677 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2678 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2679 regnum
= do_fp_register_row (regnum
); /* FP regs */
2681 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2683 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2688 /* Return number of args passed to a frame. described by FIP.
2689 Can return -1, meaning no way to tell. */
2692 mips_frame_num_args (frame
)
2693 struct frame_info
*frame
;
2695 #if 0 /* FIXME Use or lose this! */
2696 struct chain_info_t
*p
;
2698 p
= mips_find_cached_frame (FRAME_FP (frame
));
2700 return p
->the_info
.numargs
;
2705 /* Is this a branch with a delay slot? */
2707 static int is_delayed (unsigned long);
2714 for (i
= 0; i
< NUMOPCODES
; ++i
)
2715 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2716 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2718 return (i
< NUMOPCODES
2719 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2720 | INSN_COND_BRANCH_DELAY
2721 | INSN_COND_BRANCH_LIKELY
)));
2725 mips_step_skips_delay (pc
)
2728 char buf
[MIPS_INSTLEN
];
2730 /* There is no branch delay slot on MIPS16. */
2731 if (pc_is_mips16 (pc
))
2734 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2735 /* If error reading memory, guess that it is not a delayed branch. */
2737 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2741 /* Skip the PC past function prologue instructions (32-bit version).
2742 This is a helper function for mips_skip_prologue. */
2745 mips32_skip_prologue (pc
, lenient
)
2746 CORE_ADDR pc
; /* starting PC to search from */
2751 int seen_sp_adjust
= 0;
2752 int load_immediate_bytes
= 0;
2754 /* Skip the typical prologue instructions. These are the stack adjustment
2755 instruction and the instructions that save registers on the stack
2756 or in the gcc frame. */
2757 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2759 unsigned long high_word
;
2761 inst
= mips_fetch_instruction (pc
);
2762 high_word
= (inst
>> 16) & 0xffff;
2765 if (lenient
&& is_delayed (inst
))
2769 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2770 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2772 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2773 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2775 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2776 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2777 && (inst
& 0x001F0000)) /* reg != $zero */
2780 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2782 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2784 continue; /* reg != $zero */
2786 /* move $s8,$sp. With different versions of gas this will be either
2787 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2788 Accept any one of these. */
2789 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2792 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2794 else if (high_word
== 0x3c1c) /* lui $gp,n */
2796 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2798 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2799 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2801 /* The following instructions load $at or $t0 with an immediate
2802 value in preparation for a stack adjustment via
2803 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2804 a local variable, so we accept them only before a stack adjustment
2805 instruction was seen. */
2806 else if (!seen_sp_adjust
)
2808 if (high_word
== 0x3c01 || /* lui $at,n */
2809 high_word
== 0x3c08) /* lui $t0,n */
2811 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2814 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2815 high_word
== 0x3508 || /* ori $t0,$t0,n */
2816 high_word
== 0x3401 || /* ori $at,$zero,n */
2817 high_word
== 0x3408) /* ori $t0,$zero,n */
2819 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2829 /* In a frameless function, we might have incorrectly
2830 skipped some load immediate instructions. Undo the skipping
2831 if the load immediate was not followed by a stack adjustment. */
2832 if (load_immediate_bytes
&& !seen_sp_adjust
)
2833 pc
-= load_immediate_bytes
;
2837 /* Skip the PC past function prologue instructions (16-bit version).
2838 This is a helper function for mips_skip_prologue. */
2841 mips16_skip_prologue (pc
, lenient
)
2842 CORE_ADDR pc
; /* starting PC to search from */
2846 int extend_bytes
= 0;
2847 int prev_extend_bytes
;
2849 /* Table of instructions likely to be found in a function prologue. */
2852 unsigned short inst
;
2853 unsigned short mask
;
2860 , /* addiu $sp,offset */
2864 , /* daddiu $sp,offset */
2868 , /* sw reg,n($sp) */
2872 , /* sd reg,n($sp) */
2876 , /* sw $ra,n($sp) */
2880 , /* sd $ra,n($sp) */
2888 , /* sw $a0-$a3,n($s1) */
2892 , /* move reg,$a0-$a3 */
2896 , /* entry pseudo-op */
2900 , /* addiu $s1,$sp,n */
2903 } /* end of table marker */
2906 /* Skip the typical prologue instructions. These are the stack adjustment
2907 instruction and the instructions that save registers on the stack
2908 or in the gcc frame. */
2909 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2911 unsigned short inst
;
2914 inst
= mips_fetch_instruction (pc
);
2916 /* Normally we ignore an extend instruction. However, if it is
2917 not followed by a valid prologue instruction, we must adjust
2918 the pc back over the extend so that it won't be considered
2919 part of the prologue. */
2920 if ((inst
& 0xf800) == 0xf000) /* extend */
2922 extend_bytes
= MIPS16_INSTLEN
;
2925 prev_extend_bytes
= extend_bytes
;
2928 /* Check for other valid prologue instructions besides extend. */
2929 for (i
= 0; table
[i
].mask
!= 0; i
++)
2930 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2932 if (table
[i
].mask
!= 0) /* it was in table? */
2933 continue; /* ignore it */
2937 /* Return the current pc, adjusted backwards by 2 if
2938 the previous instruction was an extend. */
2939 return pc
- prev_extend_bytes
;
2945 /* To skip prologues, I use this predicate. Returns either PC itself
2946 if the code at PC does not look like a function prologue; otherwise
2947 returns an address that (if we're lucky) follows the prologue. If
2948 LENIENT, then we must skip everything which is involved in setting
2949 up the frame (it's OK to skip more, just so long as we don't skip
2950 anything which might clobber the registers which are being saved.
2951 We must skip more in the case where part of the prologue is in the
2952 delay slot of a non-prologue instruction). */
2955 mips_skip_prologue (pc
, lenient
)
2959 /* See if we can determine the end of the prologue via the symbol table.
2960 If so, then return either PC, or the PC after the prologue, whichever
2963 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2965 if (post_prologue_pc
!= 0)
2966 return max (pc
, post_prologue_pc
);
2968 /* Can't determine prologue from the symbol table, need to examine
2971 if (pc_is_mips16 (pc
))
2972 return mips16_skip_prologue (pc
, lenient
);
2974 return mips32_skip_prologue (pc
, lenient
);
2978 /* The lenient prologue stuff should be superseded by the code in
2979 init_extra_frame_info which looks to see whether the stores mentioned
2980 in the proc_desc have actually taken place. */
2982 /* Is address PC in the prologue (loosely defined) for function at
2986 mips_in_lenient_prologue (startaddr
, pc
)
2987 CORE_ADDR startaddr
;
2990 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2991 return pc
>= startaddr
&& pc
< end_prologue
;
2995 /* Determine how a return value is stored within the MIPS register
2996 file, given the return type `valtype'. */
2998 struct return_value_word
3006 static void return_value_location (struct type
*, struct return_value_word
*,
3007 struct return_value_word
*);
3010 return_value_location (valtype
, hi
, lo
)
3011 struct type
*valtype
;
3012 struct return_value_word
*hi
;
3013 struct return_value_word
*lo
;
3015 int len
= TYPE_LENGTH (valtype
);
3017 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3018 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3019 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3021 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3023 /* We need to break a 64bit float in two 32 bit halves and
3024 spread them across a floating-point register pair. */
3025 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
3026 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
3027 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3028 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3030 hi
->reg_offset
= lo
->reg_offset
;
3031 lo
->reg
= FP0_REGNUM
+ 0;
3032 hi
->reg
= FP0_REGNUM
+ 1;
3038 /* The floating point value fits in a single floating-point
3040 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3041 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3044 lo
->reg
= FP0_REGNUM
;
3055 /* Locate a result possibly spread across two registers. */
3057 lo
->reg
= regnum
+ 0;
3058 hi
->reg
= regnum
+ 1;
3059 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3060 && len
< MIPS_SAVED_REGSIZE
)
3062 /* "un-left-justify" the value in the low register */
3063 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3068 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3069 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3070 && len
< MIPS_SAVED_REGSIZE
* 2
3071 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3072 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3074 /* "un-left-justify" the value spread across two registers. */
3075 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3076 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3078 hi
->len
= len
- lo
->len
;
3082 /* Only perform a partial copy of the second register. */
3085 if (len
> MIPS_SAVED_REGSIZE
)
3087 lo
->len
= MIPS_SAVED_REGSIZE
;
3088 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3096 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3097 && REGISTER_RAW_SIZE (regnum
) == 8
3098 && MIPS_SAVED_REGSIZE
== 4)
3100 /* Account for the fact that only the least-signficant part
3101 of the register is being used */
3102 lo
->reg_offset
+= 4;
3103 hi
->reg_offset
+= 4;
3106 hi
->buf_offset
= lo
->len
;
3110 /* Given a return value in `regbuf' with a type `valtype', extract and
3111 copy its value into `valbuf'. */
3114 mips_extract_return_value (valtype
, regbuf
, valbuf
)
3115 struct type
*valtype
;
3116 char regbuf
[REGISTER_BYTES
];
3119 struct return_value_word lo
;
3120 struct return_value_word hi
;
3121 return_value_location (valtype
, &lo
, &hi
);
3123 memcpy (valbuf
+ lo
.buf_offset
,
3124 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3128 memcpy (valbuf
+ hi
.buf_offset
,
3129 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3135 int len
= TYPE_LENGTH (valtype
);
3138 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3139 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3140 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3141 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
3142 regnum
= FP0_REGNUM
;
3144 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3145 { /* "un-left-justify" the value from the register */
3146 if (len
< REGISTER_RAW_SIZE (regnum
))
3147 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3148 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3149 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3150 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3151 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3152 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3154 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
3155 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
3159 /* Given a return value in `valbuf' with a type `valtype', write it's
3160 value into the appropriate register. */
3163 mips_store_return_value (valtype
, valbuf
)
3164 struct type
*valtype
;
3167 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3168 struct return_value_word lo
;
3169 struct return_value_word hi
;
3170 return_value_location (valtype
, &lo
, &hi
);
3172 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3173 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3174 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3176 REGISTER_RAW_SIZE (lo
.reg
));
3180 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3181 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3182 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3184 REGISTER_RAW_SIZE (hi
.reg
));
3190 int len
= TYPE_LENGTH (valtype
);
3191 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3194 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3195 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3196 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3197 && len
<= MIPS_REGSIZE
)))
3198 regnum
= FP0_REGNUM
;
3200 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3201 { /* "left-justify" the value in the register */
3202 if (len
< REGISTER_RAW_SIZE (regnum
))
3203 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3204 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3205 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3206 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3207 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3208 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3210 memcpy (raw_buffer
+ offset
, valbuf
, len
);
3211 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
3212 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3213 len
> REGISTER_RAW_SIZE (regnum
) ?
3214 len
: REGISTER_RAW_SIZE (regnum
));
3218 /* Exported procedure: Is PC in the signal trampoline code */
3221 in_sigtramp (pc
, ignore
)
3223 char *ignore
; /* function name */
3225 if (sigtramp_address
== 0)
3227 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3230 /* Root of all "set mips "/"show mips " commands. This will eventually be
3231 used for all MIPS-specific commands. */
3233 static void show_mips_command (char *, int);
3235 show_mips_command (args
, from_tty
)
3239 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3242 static void set_mips_command (char *, int);
3244 set_mips_command (args
, from_tty
)
3248 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3249 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3252 /* Commands to show/set the MIPS FPU type. */
3254 static void show_mipsfpu_command (char *, int);
3256 show_mipsfpu_command (args
, from_tty
)
3262 switch (MIPS_FPU_TYPE
)
3264 case MIPS_FPU_SINGLE
:
3265 fpu
= "single-precision";
3267 case MIPS_FPU_DOUBLE
:
3268 fpu
= "double-precision";
3271 fpu
= "absent (none)";
3274 if (mips_fpu_type_auto
)
3275 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3278 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3283 static void set_mipsfpu_command (char *, int);
3285 set_mipsfpu_command (args
, from_tty
)
3289 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3290 show_mipsfpu_command (args
, from_tty
);
3293 static void set_mipsfpu_single_command (char *, int);
3295 set_mipsfpu_single_command (args
, from_tty
)
3299 mips_fpu_type
= MIPS_FPU_SINGLE
;
3300 mips_fpu_type_auto
= 0;
3303 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3307 static void set_mipsfpu_double_command (char *, int);
3309 set_mipsfpu_double_command (args
, from_tty
)
3313 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3314 mips_fpu_type_auto
= 0;
3317 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3321 static void set_mipsfpu_none_command (char *, int);
3323 set_mipsfpu_none_command (args
, from_tty
)
3327 mips_fpu_type
= MIPS_FPU_NONE
;
3328 mips_fpu_type_auto
= 0;
3331 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3335 static void set_mipsfpu_auto_command (char *, int);
3337 set_mipsfpu_auto_command (args
, from_tty
)
3341 mips_fpu_type_auto
= 1;
3344 /* Command to set the processor type. */
3347 mips_set_processor_type_command (args
, from_tty
)
3353 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3355 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3356 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3357 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3359 /* Restore the value. */
3360 tmp_mips_processor_type
= strsave (mips_processor_type
);
3365 if (!mips_set_processor_type (tmp_mips_processor_type
))
3367 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3368 /* Restore its value. */
3369 tmp_mips_processor_type
= strsave (mips_processor_type
);
3374 mips_show_processor_type_command (args
, from_tty
)
3380 /* Modify the actual processor type. */
3383 mips_set_processor_type (str
)
3391 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3393 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3395 mips_processor_type
= str
;
3396 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3398 /* FIXME tweak fpu flag too */
3405 /* Attempt to identify the particular processor model by reading the
3409 mips_read_processor_type ()
3413 prid
= read_register (PRID_REGNUM
);
3415 if ((prid
& ~0xf) == 0x700)
3416 return savestring ("r3041", strlen ("r3041"));
3421 /* Just like reinit_frame_cache, but with the right arguments to be
3422 callable as an sfunc. */
3425 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3428 struct cmd_list_element
*c
;
3430 reinit_frame_cache ();
3434 gdb_print_insn_mips (memaddr
, info
)
3436 disassemble_info
*info
;
3438 mips_extra_func_info_t proc_desc
;
3440 /* Search for the function containing this address. Set the low bit
3441 of the address when searching, in case we were given an even address
3442 that is the start of a 16-bit function. If we didn't do this,
3443 the search would fail because the symbol table says the function
3444 starts at an odd address, i.e. 1 byte past the given address. */
3445 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3446 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3448 /* Make an attempt to determine if this is a 16-bit function. If
3449 the procedure descriptor exists and the address therein is odd,
3450 it's definitely a 16-bit function. Otherwise, we have to just
3451 guess that if the address passed in is odd, it's 16-bits. */
3453 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3455 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3457 /* Round down the instruction address to the appropriate boundary. */
3458 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3460 /* Call the appropriate disassembler based on the target endian-ness. */
3461 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3462 return print_insn_big_mips (memaddr
, info
);
3464 return print_insn_little_mips (memaddr
, info
);
3467 /* Old-style breakpoint macros.
3468 The IDT board uses an unusual breakpoint value, and sometimes gets
3469 confused when it sees the usual MIPS breakpoint instruction. */
3471 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3472 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3473 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3474 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3475 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3476 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3477 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3478 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3480 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3481 counter value to determine whether a 16- or 32-bit breakpoint should be
3482 used. It returns a pointer to a string of bytes that encode a breakpoint
3483 instruction, stores the length of the string to *lenptr, and adjusts pc
3484 (if necessary) to point to the actual memory location where the
3485 breakpoint should be inserted. */
3488 mips_breakpoint_from_pc (pcptr
, lenptr
)
3492 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3494 if (pc_is_mips16 (*pcptr
))
3496 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3497 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3498 *lenptr
= sizeof (mips16_big_breakpoint
);
3499 return mips16_big_breakpoint
;
3503 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3504 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3505 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3507 *lenptr
= sizeof (big_breakpoint
);
3509 if (strcmp (target_shortname
, "mips") == 0)
3510 return idt_big_breakpoint
;
3511 else if (strcmp (target_shortname
, "ddb") == 0
3512 || strcmp (target_shortname
, "pmon") == 0
3513 || strcmp (target_shortname
, "lsi") == 0)
3514 return pmon_big_breakpoint
;
3516 return big_breakpoint
;
3521 if (pc_is_mips16 (*pcptr
))
3523 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3524 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3525 *lenptr
= sizeof (mips16_little_breakpoint
);
3526 return mips16_little_breakpoint
;
3530 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3531 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3532 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3534 *lenptr
= sizeof (little_breakpoint
);
3536 if (strcmp (target_shortname
, "mips") == 0)
3537 return idt_little_breakpoint
;
3538 else if (strcmp (target_shortname
, "ddb") == 0
3539 || strcmp (target_shortname
, "pmon") == 0
3540 || strcmp (target_shortname
, "lsi") == 0)
3541 return pmon_little_breakpoint
;
3543 return little_breakpoint
;
3548 /* If PC is in a mips16 call or return stub, return the address of the target
3549 PC, which is either the callee or the caller. There are several
3550 cases which must be handled:
3552 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3553 target PC is in $31 ($ra).
3554 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3555 and the target PC is in $2.
3556 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3557 before the jal instruction, this is effectively a call stub
3558 and the the target PC is in $2. Otherwise this is effectively
3559 a return stub and the target PC is in $18.
3561 See the source code for the stubs in gcc/config/mips/mips16.S for
3564 This function implements the SKIP_TRAMPOLINE_CODE macro.
3572 CORE_ADDR start_addr
;
3574 /* Find the starting address and name of the function containing the PC. */
3575 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3578 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3579 target PC is in $31 ($ra). */
3580 if (strcmp (name
, "__mips16_ret_sf") == 0
3581 || strcmp (name
, "__mips16_ret_df") == 0)
3582 return read_register (RA_REGNUM
);
3584 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3586 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3587 and the target PC is in $2. */
3588 if (name
[19] >= '0' && name
[19] <= '9')
3589 return read_register (2);
3591 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3592 before the jal instruction, this is effectively a call stub
3593 and the the target PC is in $2. Otherwise this is effectively
3594 a return stub and the target PC is in $18. */
3595 else if (name
[19] == 's' || name
[19] == 'd')
3597 if (pc
== start_addr
)
3599 /* Check if the target of the stub is a compiler-generated
3600 stub. Such a stub for a function bar might have a name
3601 like __fn_stub_bar, and might look like this:
3606 la $1,bar (becomes a lui/addiu pair)
3608 So scan down to the lui/addi and extract the target
3609 address from those two instructions. */
3611 CORE_ADDR target_pc
= read_register (2);
3615 /* See if the name of the target function is __fn_stub_*. */
3616 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3618 if (strncmp (name
, "__fn_stub_", 10) != 0
3619 && strcmp (name
, "etext") != 0
3620 && strcmp (name
, "_etext") != 0)
3623 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3624 The limit on the search is arbitrarily set to 20
3625 instructions. FIXME. */
3626 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3628 inst
= mips_fetch_instruction (target_pc
);
3629 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3630 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3631 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3632 return pc
| (inst
& 0xffff); /* low word */
3635 /* Couldn't find the lui/addui pair, so return stub address. */
3639 /* This is the 'return' part of a call stub. The return
3640 address is in $r18. */
3641 return read_register (18);
3644 return 0; /* not a stub */
3648 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3649 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3652 mips_in_call_stub (pc
, name
)
3656 CORE_ADDR start_addr
;
3658 /* Find the starting address of the function containing the PC. If the
3659 caller didn't give us a name, look it up at the same time. */
3660 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3663 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3665 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3666 if (name
[19] >= '0' && name
[19] <= '9')
3668 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3669 before the jal instruction, this is effectively a call stub. */
3670 else if (name
[19] == 's' || name
[19] == 'd')
3671 return pc
== start_addr
;
3674 return 0; /* not a stub */
3678 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3679 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3682 mips_in_return_stub (pc
, name
)
3686 CORE_ADDR start_addr
;
3688 /* Find the starting address of the function containing the PC. */
3689 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3692 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3693 if (strcmp (name
, "__mips16_ret_sf") == 0
3694 || strcmp (name
, "__mips16_ret_df") == 0)
3697 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3698 i.e. after the jal instruction, this is effectively a return stub. */
3699 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3700 && (name
[19] == 's' || name
[19] == 'd')
3701 && pc
!= start_addr
)
3704 return 0; /* not a stub */
3708 /* Return non-zero if the PC is in a library helper function that should
3709 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3712 mips_ignore_helper (pc
)
3717 /* Find the starting address and name of the function containing the PC. */
3718 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3721 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3722 that we want to ignore. */
3723 return (strcmp (name
, "__mips16_ret_sf") == 0
3724 || strcmp (name
, "__mips16_ret_df") == 0);
3728 /* Return a location where we can set a breakpoint that will be hit
3729 when an inferior function call returns. This is normally the
3730 program's entry point. Executables that don't have an entry
3731 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3732 whose address is the location where the breakpoint should be placed. */
3735 mips_call_dummy_address ()
3737 struct minimal_symbol
*sym
;
3739 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3741 return SYMBOL_VALUE_ADDRESS (sym
);
3743 return entry_point_address ();
3747 /* If the current gcc for for this target does not produce correct debugging
3748 information for float parameters, both prototyped and unprototyped, then
3749 define this macro. This forces gdb to always assume that floats are
3750 passed as doubles and then converted in the callee.
3752 For the mips chip, it appears that the debug info marks the parameters as
3753 floats regardless of whether the function is prototyped, but the actual
3754 values are passed as doubles for the non-prototyped case and floats for
3755 the prototyped case. Thus we choose to make the non-prototyped case work
3756 for C and break the prototyped case, since the non-prototyped case is
3757 probably much more common. (FIXME). */
3760 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3762 return current_language
->la_language
== language_c
;
3765 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
3766 the register stored on the stack (32) is different to its real raw
3767 size (64). The below ensures that registers are fetched from the
3768 stack using their ABI size and then stored into the RAW_BUFFER
3769 using their raw size.
3771 The alternative to adding this function would be to add an ABI
3772 macro - REGISTER_STACK_SIZE(). */
3775 mips_get_saved_register (raw_buffer
, optimized
, addrp
, frame
, regnum
, lval
)
3779 struct frame_info
*frame
;
3781 enum lval_type
*lval
;
3785 if (!target_has_registers
)
3786 error ("No registers.");
3788 /* Normal systems don't optimize out things with register numbers. */
3789 if (optimized
!= NULL
)
3791 addr
= find_saved_register (frame
, regnum
);
3795 *lval
= lval_memory
;
3796 if (regnum
== SP_REGNUM
)
3798 if (raw_buffer
!= NULL
)
3800 /* Put it back in target format. */
3801 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
3808 if (raw_buffer
!= NULL
)
3812 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
3814 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
3816 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
3817 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
3823 *lval
= lval_register
;
3824 addr
= REGISTER_BYTE (regnum
);
3825 if (raw_buffer
!= NULL
)
3826 read_register_gen (regnum
, raw_buffer
);
3832 static gdbarch_init_ftype mips_gdbarch_init
;
3833 static struct gdbarch
*
3834 mips_gdbarch_init (info
, arches
)
3835 struct gdbarch_info info
;
3836 struct gdbarch_list
*arches
;
3838 static LONGEST mips_call_dummy_words
[] =
3840 struct gdbarch
*gdbarch
;
3841 struct gdbarch_tdep
*tdep
;
3843 int ef_mips_bitptrs
;
3845 enum mips_abi mips_abi
;
3847 /* Extract the elf_flags if available */
3848 if (info
.abfd
!= NULL
3849 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3850 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3854 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
3855 switch ((elf_flags
& EF_MIPS_ABI
))
3857 case E_MIPS_ABI_O32
:
3858 mips_abi
= MIPS_ABI_O32
;
3860 case E_MIPS_ABI_O64
:
3861 mips_abi
= MIPS_ABI_O64
;
3863 case E_MIPS_ABI_EABI32
:
3864 mips_abi
= MIPS_ABI_EABI32
;
3866 case E_MIPS_ABI_EABI64
:
3867 mips_abi
= MIPS_ABI_EABI32
;
3870 mips_abi
= MIPS_ABI_UNKNOWN
;
3873 /* Try the architecture for any hint of the corect ABI */
3874 if (mips_abi
== MIPS_ABI_UNKNOWN
3875 && info
.bfd_arch_info
!= NULL
3876 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3878 switch (info
.bfd_arch_info
->mach
)
3880 case bfd_mach_mips3900
:
3881 mips_abi
= MIPS_ABI_EABI32
;
3883 case bfd_mach_mips4100
:
3884 case bfd_mach_mips5000
:
3885 mips_abi
= MIPS_ABI_EABI64
;
3889 #ifdef MIPS_DEFAULT_ABI
3890 if (mips_abi
== MIPS_ABI_UNKNOWN
)
3891 mips_abi
= MIPS_DEFAULT_ABI
;
3896 fprintf_unfiltered (gdb_stdlog
,
3897 "mips_gdbarch_init: elf_flags = %08x\n",
3899 fprintf_unfiltered (gdb_stdlog
,
3900 "mips_gdbarch_init: ef_mips_arch = %d\n",
3902 fprintf_unfiltered (gdb_stdlog
,
3903 "mips_gdbarch_init: ef_mips_bitptrs = %d\n",
3905 fprintf_unfiltered (gdb_stdlog
,
3906 "mips_gdbarch_init: mips_abi = %d\n",
3910 /* try to find a pre-existing architecture */
3911 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3913 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3915 /* MIPS needs to be pedantic about which ABI the object is
3917 if (gdbarch_tdep (current_gdbarch
)->elf_flags
!= elf_flags
)
3919 if (gdbarch_tdep (current_gdbarch
)->mips_abi
!= mips_abi
)
3921 return arches
->gdbarch
;
3924 /* Need a new architecture. Fill in a target specific vector. */
3925 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3926 gdbarch
= gdbarch_alloc (&info
, tdep
);
3927 tdep
->elf_flags
= elf_flags
;
3929 /* Initially set everything according to the ABI. */
3930 set_gdbarch_short_bit (gdbarch
, 16);
3931 set_gdbarch_int_bit (gdbarch
, 32);
3932 set_gdbarch_float_bit (gdbarch
, 32);
3933 set_gdbarch_double_bit (gdbarch
, 64);
3934 set_gdbarch_long_double_bit (gdbarch
, 64);
3935 tdep
->mips_abi
= mips_abi
;
3939 tdep
->mips_default_saved_regsize
= 4;
3940 tdep
->mips_default_stack_argsize
= 4;
3941 tdep
->mips_fp_register_double
= 0;
3942 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 7;
3943 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
3944 tdep
->mips_regs_have_home_p
= 1;
3945 set_gdbarch_long_bit (gdbarch
, 32);
3946 set_gdbarch_ptr_bit (gdbarch
, 32);
3947 set_gdbarch_long_long_bit (gdbarch
, 64);
3950 tdep
->mips_default_saved_regsize
= 8;
3951 tdep
->mips_default_stack_argsize
= 8;
3952 tdep
->mips_fp_register_double
= 1;
3953 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 7;
3954 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 15;
3955 tdep
->mips_regs_have_home_p
= 1;
3956 set_gdbarch_long_bit (gdbarch
, 32);
3957 set_gdbarch_ptr_bit (gdbarch
, 32);
3958 set_gdbarch_long_long_bit (gdbarch
, 64);
3960 case MIPS_ABI_EABI32
:
3961 tdep
->mips_default_saved_regsize
= 4;
3962 tdep
->mips_default_stack_argsize
= 4;
3963 tdep
->mips_fp_register_double
= 0;
3964 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
3965 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3966 tdep
->mips_regs_have_home_p
= 0;
3967 set_gdbarch_long_bit (gdbarch
, 32);
3968 set_gdbarch_ptr_bit (gdbarch
, 32);
3969 set_gdbarch_long_long_bit (gdbarch
, 64);
3971 case MIPS_ABI_EABI64
:
3972 tdep
->mips_default_saved_regsize
= 8;
3973 tdep
->mips_default_stack_argsize
= 8;
3974 tdep
->mips_fp_register_double
= 1;
3975 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
3976 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3977 tdep
->mips_regs_have_home_p
= 0;
3978 set_gdbarch_long_bit (gdbarch
, 64);
3979 set_gdbarch_ptr_bit (gdbarch
, 64);
3980 set_gdbarch_long_long_bit (gdbarch
, 64);
3983 tdep
->mips_default_saved_regsize
= 4;
3984 tdep
->mips_default_stack_argsize
= 8;
3985 tdep
->mips_fp_register_double
= 1;
3986 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
3987 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3988 tdep
->mips_regs_have_home_p
= 0;
3989 set_gdbarch_long_bit (gdbarch
, 32);
3990 set_gdbarch_ptr_bit (gdbarch
, 32);
3991 set_gdbarch_long_long_bit (gdbarch
, 64);
3994 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
3995 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
3996 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
3997 tdep
->mips_last_arg_regnum
= ZERO_REGNUM
+ 11;
3998 tdep
->mips_last_fp_arg_regnum
= FP0_REGNUM
+ 19;
3999 tdep
->mips_regs_have_home_p
= 1;
4000 set_gdbarch_long_bit (gdbarch
, 32);
4001 set_gdbarch_ptr_bit (gdbarch
, 32);
4002 set_gdbarch_long_long_bit (gdbarch
, 64);
4006 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4007 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4010 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4011 flag in object files because to do so would make it impossible to
4012 link with libraries compiled without "-gp32". This is
4013 unnecessarily restrictive.
4015 We could solve this problem by adding "-gp32" multilibs to gcc,
4016 but to set this flag before gcc is built with such multilibs will
4017 break too many systems.''
4019 But even more unhelpfully, the default linker output target for
4020 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4021 for 64-bit programs - you need to change the ABI to change this,
4022 and not all gcc targets support that currently. Therefore using
4023 this flag to detect 32-bit mode would do the wrong thing given
4024 the current gcc - it would make GDB treat these 64-bit programs
4025 as 32-bit programs by default. */
4027 /* determine the ISA */
4028 switch (elf_flags
& EF_MIPS_ARCH
)
4047 /* determine the size of a pointer */
4048 if ((elf_flags
& EF_MIPS_32BITPTRS
))
4050 ef_mips_bitptrs
= 32;
4052 else if ((elf_flags
& EF_MIPS_64BITPTRS
))
4054 ef_mips_bitptrs
= 64;
4058 ef_mips_bitptrs
= 0;
4062 /* enable/disable the MIPS FPU */
4063 if (!mips_fpu_type_auto
)
4064 tdep
->mips_fpu_type
= mips_fpu_type
;
4065 else if (info
.bfd_arch_info
!= NULL
4066 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4067 switch (info
.bfd_arch_info
->mach
)
4069 case bfd_mach_mips3900
:
4070 case bfd_mach_mips4100
:
4071 case bfd_mach_mips4111
:
4072 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4074 case bfd_mach_mips4650
:
4075 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4078 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4082 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4084 /* MIPS version of register names. NOTE: At present the MIPS
4085 register name management is part way between the old -
4086 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4087 Further work on it is required. */
4088 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4089 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
4090 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4091 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4092 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
4093 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4094 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4096 /* Initialize a frame */
4097 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4099 /* MIPS version of CALL_DUMMY */
4101 set_gdbarch_call_dummy_p (gdbarch
, 1);
4102 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4103 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4104 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4105 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4106 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4107 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4108 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4109 set_gdbarch_call_dummy_length (gdbarch
, 0);
4110 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4111 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4112 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4113 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4114 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4115 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4116 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4118 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4119 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4125 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4127 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4130 fprintf_unfiltered (file
,
4131 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4133 fprintf_unfiltered (file
,
4134 "mips_dump_tdep: tdep->mips_abi = %d\n",
4137 fprintf_unfiltered (file
,
4138 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4139 FP_REGISTER_DOUBLE
);
4140 fprintf_unfiltered (file
,
4141 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4142 MIPS_DEFAULT_FPU_TYPE
,
4143 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4144 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4145 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4147 fprintf_unfiltered (file
,
4148 "mips_dump_tdep: MIPS_EABI = %d\n",
4150 fprintf_unfiltered (file
,
4151 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d\n",
4152 MIPS_LAST_FP_ARG_REGNUM
);
4153 fprintf_unfiltered (file
,
4154 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d\n",
4155 MIPS_LAST_ARG_REGNUM
);
4156 fprintf_unfiltered (file
,
4157 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4159 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4160 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4161 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4163 fprintf_unfiltered (file
,
4164 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4165 MIPS_DEFAULT_SAVED_REGSIZE
);
4166 fprintf_unfiltered (file
,
4167 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4168 MIPS_SAVED_REGSIZE
);
4169 fprintf_unfiltered (file
,
4170 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4171 FP_REGISTER_DOUBLE
);
4172 fprintf_unfiltered (file
,
4173 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4174 MIPS_REGS_HAVE_HOME_P
);
4175 fprintf_unfiltered (file
,
4176 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4177 MIPS_DEFAULT_STACK_ARGSIZE
);
4178 fprintf_unfiltered (file
,
4179 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4180 MIPS_STACK_ARGSIZE
);
4181 fprintf_unfiltered (file
,
4182 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4187 _initialize_mips_tdep ()
4189 static struct cmd_list_element
*mipsfpulist
= NULL
;
4190 struct cmd_list_element
*c
;
4192 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4193 if (!tm_print_insn
) /* Someone may have already set it */
4194 tm_print_insn
= gdb_print_insn_mips
;
4196 /* Add root prefix command for all "set mips"/"show mips" commands */
4197 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4198 "Various MIPS specific commands.",
4199 &setmipscmdlist
, "set mips ", 0, &setlist
);
4201 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4202 "Various MIPS specific commands.",
4203 &showmipscmdlist
, "show mips ", 0, &showlist
);
4205 /* Allow the user to override the saved register size. */
4206 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4209 &mips_saved_regsize_string
, "\
4210 Set size of general purpose registers saved on the stack.\n\
4211 This option can be set to one of:\n\
4212 32 - Force GDB to treat saved GP registers as 32-bit\n\
4213 64 - Force GDB to treat saved GP registers as 64-bit\n\
4214 auto - Allow GDB to use the target's default setting or autodetect the\n\
4215 saved GP register size from information contained in the executable.\n\
4220 /* Allow the user to override the argument stack size. */
4221 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4224 &mips_stack_argsize_string
, "\
4225 Set the amount of stack space reserved for each argument.\n\
4226 This option can be set to one of:\n\
4227 32 - Force GDB to allocate 32-bit chunks per argument\n\
4228 64 - Force GDB to allocate 64-bit chunks per argument\n\
4229 auto - Allow GDB to determine the correct setting from the current\n\
4230 target and executable (default)",
4234 /* Let the user turn off floating point and set the fence post for
4235 heuristic_proc_start. */
4237 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4238 "Set use of MIPS floating-point coprocessor.",
4239 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4240 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4241 "Select single-precision MIPS floating-point coprocessor.",
4243 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4244 "Select double-precision MIPS floating-point coprocessor .",
4246 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4247 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4248 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4249 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4250 "Select no MIPS floating-point coprocessor.",
4252 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4253 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4254 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4255 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4256 "Select MIPS floating-point coprocessor automatically.",
4258 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4259 "Show current use of MIPS floating-point coprocessor target.",
4263 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4264 (char *) &tmp_mips_processor_type
,
4265 "Set the type of MIPS processor in use.\n\
4266 Set this to be able to access processor-type-specific registers.\n\
4269 c
->function
.cfunc
= mips_set_processor_type_command
;
4270 c
= add_show_from_set (c
, &showlist
);
4271 c
->function
.cfunc
= mips_show_processor_type_command
;
4273 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
4274 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
4277 /* We really would like to have both "0" and "unlimited" work, but
4278 command.c doesn't deal with that. So make it a var_zinteger
4279 because the user can always use "999999" or some such for unlimited. */
4280 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4281 (char *) &heuristic_fence_post
,
4283 Set the distance searched for the start of a function.\n\
4284 If you are debugging a stripped executable, GDB needs to search through the\n\
4285 program for the start of a function. This command sets the distance of the\n\
4286 search. The only need to set it is when debugging a stripped executable.",
4288 /* We need to throw away the frame cache when we set this, since it
4289 might change our ability to get backtraces. */
4290 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4291 add_show_from_set (c
, &showlist
);
4293 /* Allow the user to control whether the upper bits of 64-bit
4294 addresses should be zeroed. */
4296 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *) &mask_address_p
,
4297 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4298 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
4299 Without an argument, zeroing of upper address bits is enabled.", &setlist
),
4302 /* Allow the user to control the size of 32 bit registers within the
4303 raw remote packet. */
4304 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4307 (char *)&mips64_transfers_32bit_regs_p
, "\
4308 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4309 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4310 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4311 64 bits for others. Use \"off\" to disable compatibility mode",