1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
5 2010 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
62 static const struct objfile_data
*mips_pdr_data
;
64 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
66 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
67 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
68 #define ST0_FR (1 << 26)
70 /* The sizes of floating point registers. */
74 MIPS_FPU_SINGLE_REGSIZE
= 4,
75 MIPS_FPU_DOUBLE_REGSIZE
= 8
84 static const char *mips_abi_string
;
86 static const char *mips_abi_strings
[] = {
97 /* The standard register names, and all the valid aliases for them. */
104 /* Aliases for o32 and most other ABIs. */
105 const struct register_alias mips_o32_aliases
[] = {
112 /* Aliases for n32 and n64. */
113 const struct register_alias mips_n32_n64_aliases
[] = {
120 /* Aliases for ABI-independent registers. */
121 const struct register_alias mips_register_aliases
[] = {
122 /* The architecture manuals specify these ABI-independent names for
124 #define R(n) { "r" #n, n }
125 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
126 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
127 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
128 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
131 /* k0 and k1 are sometimes called these instead (for "kernel
136 /* This is the traditional GDB name for the CP0 status register. */
137 { "sr", MIPS_PS_REGNUM
},
139 /* This is the traditional GDB name for the CP0 BadVAddr register. */
140 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
142 /* This is the traditional GDB name for the FCSR. */
143 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
146 const struct register_alias mips_numeric_register_aliases
[] = {
147 #define R(n) { #n, n }
148 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
149 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
150 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
151 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 const struct mips_regnum
*
172 mips_regnum (struct gdbarch
*gdbarch
)
174 return gdbarch_tdep (gdbarch
)->regnum
;
178 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
180 return mips_regnum (gdbarch
)->fp0
+ 12;
183 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
185 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
187 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
191 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
193 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
194 functions to test, set, or clear bit 0 of addresses. */
197 is_mips16_addr (CORE_ADDR addr
)
203 unmake_mips16_addr (CORE_ADDR addr
)
205 return ((addr
) & ~(CORE_ADDR
) 1);
209 make_mips16_addr (CORE_ADDR addr
)
211 return ((addr
) | (CORE_ADDR
) 1);
214 /* Return the MIPS ABI associated with GDBARCH. */
216 mips_abi (struct gdbarch
*gdbarch
)
218 return gdbarch_tdep (gdbarch
)->mips_abi
;
222 mips_isa_regsize (struct gdbarch
*gdbarch
)
224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
226 /* If we know how big the registers are, use that size. */
227 if (tdep
->register_size_valid_p
)
228 return tdep
->register_size
;
230 /* Fall back to the previous behavior. */
231 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
232 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
235 /* Return the currently configured (or set) saved register size. */
238 mips_abi_regsize (struct gdbarch
*gdbarch
)
240 switch (mips_abi (gdbarch
))
242 case MIPS_ABI_EABI32
:
248 case MIPS_ABI_EABI64
:
250 case MIPS_ABI_UNKNOWN
:
253 internal_error (__FILE__
, __LINE__
, _("bad switch"));
257 /* Functions for setting and testing a bit in a minimal symbol that
258 marks it as 16-bit function. The MSB of the minimal symbol's
259 "info" field is used for this purpose.
261 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
262 i.e. refers to a 16-bit function, and sets a "special" bit in a
263 minimal symbol to mark it as a 16-bit function
265 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
268 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
270 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
272 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
277 msymbol_is_special (struct minimal_symbol
*msym
)
279 return MSYMBOL_TARGET_FLAG_1 (msym
);
282 /* XFER a value from the big/little/left end of the register.
283 Depending on the size of the value it might occupy the entire
284 register or just part of it. Make an allowance for this, aligning
285 things accordingly. */
288 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
289 int reg_num
, int length
,
290 enum bfd_endian endian
, gdb_byte
*in
,
291 const gdb_byte
*out
, int buf_offset
)
295 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
296 /* Need to transfer the left or right part of the register, based on
297 the targets byte order. */
301 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
303 case BFD_ENDIAN_LITTLE
:
306 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
310 internal_error (__FILE__
, __LINE__
, _("bad switch"));
313 fprintf_unfiltered (gdb_stderr
,
314 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
315 reg_num
, reg_offset
, buf_offset
, length
);
316 if (mips_debug
&& out
!= NULL
)
319 fprintf_unfiltered (gdb_stdlog
, "out ");
320 for (i
= 0; i
< length
; i
++)
321 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
324 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
327 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
329 if (mips_debug
&& in
!= NULL
)
332 fprintf_unfiltered (gdb_stdlog
, "in ");
333 for (i
= 0; i
< length
; i
++)
334 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
337 fprintf_unfiltered (gdb_stdlog
, "\n");
340 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
341 compatiblity mode. A return value of 1 means that we have
342 physical 64-bit registers, but should treat them as 32-bit registers. */
345 mips2_fp_compat (struct frame_info
*frame
)
347 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
348 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
350 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
354 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
355 in all the places we deal with FP registers. PR gdb/413. */
356 /* Otherwise check the FR bit in the status register - it controls
357 the FP compatiblity mode. If it is clear we are in compatibility
359 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
366 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
368 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
370 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
372 /* The list of available "set mips " and "show mips " commands */
374 static struct cmd_list_element
*setmipscmdlist
= NULL
;
375 static struct cmd_list_element
*showmipscmdlist
= NULL
;
377 /* Integer registers 0 thru 31 are handled explicitly by
378 mips_register_name(). Processor specific registers 32 and above
379 are listed in the following tables. */
382 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
386 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
387 "sr", "lo", "hi", "bad", "cause", "pc",
388 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
389 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
390 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
391 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
392 "fsr", "fir", "" /*"fp" */ , "",
393 "", "", "", "", "", "", "", "",
394 "", "", "", "", "", "", "", "",
397 /* Names of IDT R3041 registers. */
399 static const char *mips_r3041_reg_names
[] = {
400 "sr", "lo", "hi", "bad", "cause", "pc",
401 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
402 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
403 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
404 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
405 "fsr", "fir", "", /*"fp" */ "",
406 "", "", "bus", "ccfg", "", "", "", "",
407 "", "", "port", "cmp", "", "", "epc", "prid",
410 /* Names of tx39 registers. */
412 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
413 "sr", "lo", "hi", "bad", "cause", "pc",
414 "", "", "", "", "", "", "", "",
415 "", "", "", "", "", "", "", "",
416 "", "", "", "", "", "", "", "",
417 "", "", "", "", "", "", "", "",
419 "", "", "", "", "", "", "", "",
420 "", "", "config", "cache", "debug", "depc", "epc", ""
423 /* Names of IRIX registers. */
424 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
425 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
426 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
427 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
428 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
429 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
433 /* Return the name of the register corresponding to REGNO. */
435 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
437 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
438 /* GPR names for all ABIs other than n32/n64. */
439 static char *mips_gpr_names
[] = {
440 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
441 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
442 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
443 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
446 /* GPR names for n32 and n64 ABIs. */
447 static char *mips_n32_n64_gpr_names
[] = {
448 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
449 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
450 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
451 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
454 enum mips_abi abi
= mips_abi (gdbarch
);
456 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
457 but then don't make the raw register names visible. This (upper)
458 range of user visible register numbers are the pseudo-registers.
460 This approach was adopted accommodate the following scenario:
461 It is possible to debug a 64-bit device using a 32-bit
462 programming model. In such instances, the raw registers are
463 configured to be 64-bits wide, while the pseudo registers are
464 configured to be 32-bits wide. The registers that the user
465 sees - the pseudo registers - match the users expectations
466 given the programming model being used. */
467 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
468 if (regno
< gdbarch_num_regs (gdbarch
))
471 /* The MIPS integer registers are always mapped from 0 to 31. The
472 names of the registers (which reflects the conventions regarding
473 register use) vary depending on the ABI. */
474 if (0 <= rawnum
&& rawnum
< 32)
476 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
477 return mips_n32_n64_gpr_names
[rawnum
];
479 return mips_gpr_names
[rawnum
];
481 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
482 return tdesc_register_name (gdbarch
, rawnum
);
483 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
485 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
486 return tdep
->mips_processor_reg_names
[rawnum
- 32];
489 internal_error (__FILE__
, __LINE__
,
490 _("mips_register_name: bad register number %d"), rawnum
);
493 /* Return the groups that a MIPS register can be categorised into. */
496 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
497 struct reggroup
*reggroup
)
502 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
503 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
504 if (reggroup
== all_reggroup
)
506 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
507 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
508 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
509 (gdbarch), as not all architectures are multi-arch. */
510 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
511 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
512 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
514 if (reggroup
== float_reggroup
)
515 return float_p
&& pseudo
;
516 if (reggroup
== vector_reggroup
)
517 return vector_p
&& pseudo
;
518 if (reggroup
== general_reggroup
)
519 return (!vector_p
&& !float_p
) && pseudo
;
520 /* Save the pseudo registers. Need to make certain that any code
521 extracting register values from a saved register cache also uses
523 if (reggroup
== save_reggroup
)
524 return raw_p
&& pseudo
;
525 /* Restore the same pseudo register. */
526 if (reggroup
== restore_reggroup
)
527 return raw_p
&& pseudo
;
531 /* Return the groups that a MIPS register can be categorised into.
532 This version is only used if we have a target description which
533 describes real registers (and their groups). */
536 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
537 struct reggroup
*reggroup
)
539 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
540 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
543 /* Only save, restore, and display the pseudo registers. Need to
544 make certain that any code extracting register values from a
545 saved register cache also uses pseudo registers.
547 Note: saving and restoring the pseudo registers is slightly
548 strange; if we have 64 bits, we should save and restore all
549 64 bits. But this is hard and has little benefit. */
553 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
557 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
560 /* Map the symbol table registers which live in the range [1 *
561 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
562 registers. Take care of alignment and size problems. */
565 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
566 int cookednum
, gdb_byte
*buf
)
568 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
569 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
570 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
571 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
572 regcache_raw_read (regcache
, rawnum
, buf
);
573 else if (register_size (gdbarch
, rawnum
) >
574 register_size (gdbarch
, cookednum
))
576 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
577 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
580 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
582 regcache_raw_read_signed (regcache
, rawnum
, ®val
);
583 store_signed_integer (buf
, 4, byte_order
, regval
);
587 internal_error (__FILE__
, __LINE__
, _("bad register size"));
591 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
592 struct regcache
*regcache
, int cookednum
,
595 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
596 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
597 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
598 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
599 regcache_raw_write (regcache
, rawnum
, buf
);
600 else if (register_size (gdbarch
, rawnum
) >
601 register_size (gdbarch
, cookednum
))
603 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
604 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
607 /* Sign extend the shortened version of the register prior
608 to placing it in the raw register. This is required for
609 some mips64 parts in order to avoid unpredictable behavior. */
610 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
611 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
612 regcache_raw_write_signed (regcache
, rawnum
, regval
);
616 internal_error (__FILE__
, __LINE__
, _("bad register size"));
619 /* Table to translate MIPS16 register field to actual register number. */
620 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
622 /* Heuristic_proc_start may hunt through the text section for a long
623 time across a 2400 baud serial line. Allows the user to limit this
626 static unsigned int heuristic_fence_post
= 0;
628 /* Number of bytes of storage in the actual machine representation for
629 register N. NOTE: This defines the pseudo register type so need to
630 rebuild the architecture vector. */
632 static int mips64_transfers_32bit_regs_p
= 0;
635 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
636 struct cmd_list_element
*c
)
638 struct gdbarch_info info
;
639 gdbarch_info_init (&info
);
640 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
641 instead of relying on globals. Doing that would let generic code
642 handle the search for this specific architecture. */
643 if (!gdbarch_update_p (info
))
645 mips64_transfers_32bit_regs_p
= 0;
646 error (_("32-bit compatibility mode not supported"));
650 /* Convert to/from a register and the corresponding memory value. */
652 /* This predicate tests for the case of an 8 byte floating point
653 value that is being transferred to or from a pair of floating point
654 registers each of which are (or are considered to be) only 4 bytes
657 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
660 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
661 && register_size (gdbarch
, regnum
) == 4
662 && (regnum
% gdbarch_num_regs (gdbarch
))
663 >= mips_regnum (gdbarch
)->fp0
664 && (regnum
% gdbarch_num_regs (gdbarch
))
665 < mips_regnum (gdbarch
)->fp0
+ 32
666 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
669 /* This predicate tests for the case of a value of less than 8
670 bytes in width that is being transfered to or from an 8 byte
671 general purpose register. */
673 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
676 int num_regs
= gdbarch_num_regs (gdbarch
);
678 return (register_size (gdbarch
, regnum
) == 8
679 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
680 && TYPE_LENGTH (type
) < 8);
684 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
686 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
687 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
691 mips_register_to_value (struct frame_info
*frame
, int regnum
,
692 struct type
*type
, gdb_byte
*to
)
694 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
696 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
698 get_frame_register (frame
, regnum
+ 0, to
+ 4);
699 get_frame_register (frame
, regnum
+ 1, to
+ 0);
701 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
703 int len
= TYPE_LENGTH (type
);
704 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
705 get_frame_register_bytes (frame
, regnum
, 8 - len
, len
, to
);
707 get_frame_register_bytes (frame
, regnum
, 0, len
, to
);
711 internal_error (__FILE__
, __LINE__
,
712 _("mips_register_to_value: unrecognized case"));
717 mips_value_to_register (struct frame_info
*frame
, int regnum
,
718 struct type
*type
, const gdb_byte
*from
)
720 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
722 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
724 put_frame_register (frame
, regnum
+ 0, from
+ 4);
725 put_frame_register (frame
, regnum
+ 1, from
+ 0);
727 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
730 int len
= TYPE_LENGTH (type
);
732 /* Sign extend values, irrespective of type, that are stored to
733 a 64-bit general purpose register. (32-bit unsigned values
734 are stored as signed quantities within a 64-bit register.
735 When performing an operation, in compiled code, that combines
736 a 32-bit unsigned value with a signed 64-bit value, a type
737 conversion is first performed that zeroes out the high 32 bits.) */
738 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
741 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
743 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
744 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
745 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
749 if (from
[len
-1] & 0x80)
750 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
752 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
753 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
754 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
759 internal_error (__FILE__
, __LINE__
,
760 _("mips_value_to_register: unrecognized case"));
764 /* Return the GDB type object for the "standard" data type of data in
768 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
770 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
771 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
772 && (regnum
% gdbarch_num_regs (gdbarch
))
773 < mips_regnum (gdbarch
)->fp0
+ 32)
775 /* The floating-point registers raw, or cooked, always match
776 mips_isa_regsize(), and also map 1:1, byte for byte. */
777 if (mips_isa_regsize (gdbarch
) == 4)
778 return builtin_type (gdbarch
)->builtin_float
;
780 return builtin_type (gdbarch
)->builtin_double
;
782 else if (regnum
< gdbarch_num_regs (gdbarch
))
784 /* The raw or ISA registers. These are all sized according to
786 if (mips_isa_regsize (gdbarch
) == 4)
787 return builtin_type (gdbarch
)->builtin_int32
;
789 return builtin_type (gdbarch
)->builtin_int64
;
793 /* The cooked or ABI registers. These are sized according to
794 the ABI (with a few complications). */
795 if (regnum
>= (gdbarch_num_regs (gdbarch
)
796 + mips_regnum (gdbarch
)->fp_control_status
)
797 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
798 /* The pseudo/cooked view of the embedded registers is always
799 32-bit. The raw view is handled below. */
800 return builtin_type (gdbarch
)->builtin_int32
;
801 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
802 /* The target, while possibly using a 64-bit register buffer,
803 is only transfering 32-bits of each integer register.
804 Reflect this in the cooked/pseudo (ABI) register value. */
805 return builtin_type (gdbarch
)->builtin_int32
;
806 else if (mips_abi_regsize (gdbarch
) == 4)
807 /* The ABI is restricted to 32-bit registers (the ISA could be
809 return builtin_type (gdbarch
)->builtin_int32
;
812 return builtin_type (gdbarch
)->builtin_int64
;
816 /* Return the GDB type for the pseudo register REGNUM, which is the
817 ABI-level view. This function is only called if there is a target
818 description which includes registers, so we know precisely the
819 types of hardware registers. */
822 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
824 const int num_regs
= gdbarch_num_regs (gdbarch
);
825 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
826 int rawnum
= regnum
% num_regs
;
827 struct type
*rawtype
;
829 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
831 /* Absent registers are still absent. */
832 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
833 if (TYPE_LENGTH (rawtype
) == 0)
836 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
837 /* Present the floating point registers however the hardware did;
838 do not try to convert between FPU layouts. */
841 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
843 /* The pseudo/cooked view of embedded registers is always
844 32-bit, even if the target transfers 64-bit values for them.
845 New targets relying on XML descriptions should only transfer
846 the necessary 32 bits, but older versions of GDB expected 64,
847 so allow the target to provide 64 bits without interfering
848 with the displayed type. */
849 return builtin_type (gdbarch
)->builtin_int32
;
852 /* Use pointer types for registers if we can. For n32 we can not,
853 since we do not have a 64-bit pointer type. */
854 if (mips_abi_regsize (gdbarch
)
855 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
857 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
858 return builtin_type (gdbarch
)->builtin_data_ptr
;
859 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
860 return builtin_type (gdbarch
)->builtin_func_ptr
;
863 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
864 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
865 return builtin_type (gdbarch
)->builtin_int32
;
867 /* For all other registers, pass through the hardware type. */
871 /* Should the upper word of 64-bit addresses be zeroed? */
872 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
875 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
877 switch (mask_address_var
)
879 case AUTO_BOOLEAN_TRUE
:
881 case AUTO_BOOLEAN_FALSE
:
884 case AUTO_BOOLEAN_AUTO
:
885 return tdep
->default_mask_address_p
;
887 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
893 show_mask_address (struct ui_file
*file
, int from_tty
,
894 struct cmd_list_element
*c
, const char *value
)
896 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
898 deprecated_show_value_hack (file
, from_tty
, c
, value
);
899 switch (mask_address_var
)
901 case AUTO_BOOLEAN_TRUE
:
902 printf_filtered ("The 32 bit mips address mask is enabled\n");
904 case AUTO_BOOLEAN_FALSE
:
905 printf_filtered ("The 32 bit mips address mask is disabled\n");
907 case AUTO_BOOLEAN_AUTO
:
909 ("The 32 bit address mask is set automatically. Currently %s\n",
910 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
913 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
918 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
921 mips_pc_is_mips16 (CORE_ADDR memaddr
)
923 struct minimal_symbol
*sym
;
925 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
926 if (is_mips16_addr (memaddr
))
929 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
930 the high bit of the info field. Use this to decide if the function is
931 MIPS16 or normal MIPS. */
932 sym
= lookup_minimal_symbol_by_pc (memaddr
);
934 return msymbol_is_special (sym
);
939 /* MIPS believes that the PC has a sign extended value. Perhaps the
940 all registers should be sign extended for simplicity? */
943 mips_read_pc (struct regcache
*regcache
)
946 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
947 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
948 if (is_mips16_addr (pc
))
949 pc
= unmake_mips16_addr (pc
);
954 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
958 pc
= frame_unwind_register_signed
959 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
960 if (is_mips16_addr (pc
))
961 pc
= unmake_mips16_addr (pc
);
966 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
968 return frame_unwind_register_signed
969 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
972 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
973 dummy frame. The frame ID's base needs to match the TOS value
974 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
977 static struct frame_id
978 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
980 return frame_id_build
981 (get_frame_register_signed (this_frame
,
982 gdbarch_num_regs (gdbarch
)
984 get_frame_pc (this_frame
));
988 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
990 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
991 if (mips_pc_is_mips16 (pc
))
992 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
994 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
997 /* Fetch and return instruction from the specified location. If the PC
998 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1001 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1003 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1004 gdb_byte buf
[MIPS_INSN32_SIZE
];
1008 if (mips_pc_is_mips16 (addr
))
1010 instlen
= MIPS_INSN16_SIZE
;
1011 addr
= unmake_mips16_addr (addr
);
1014 instlen
= MIPS_INSN32_SIZE
;
1015 status
= target_read_memory (addr
, buf
, instlen
);
1017 memory_error (status
, addr
);
1018 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1021 /* These the fields of 32 bit mips instructions */
1022 #define mips32_op(x) (x >> 26)
1023 #define itype_op(x) (x >> 26)
1024 #define itype_rs(x) ((x >> 21) & 0x1f)
1025 #define itype_rt(x) ((x >> 16) & 0x1f)
1026 #define itype_immediate(x) (x & 0xffff)
1028 #define jtype_op(x) (x >> 26)
1029 #define jtype_target(x) (x & 0x03ffffff)
1031 #define rtype_op(x) (x >> 26)
1032 #define rtype_rs(x) ((x >> 21) & 0x1f)
1033 #define rtype_rt(x) ((x >> 16) & 0x1f)
1034 #define rtype_rd(x) ((x >> 11) & 0x1f)
1035 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1036 #define rtype_funct(x) (x & 0x3f)
1039 mips32_relative_offset (ULONGEST inst
)
1041 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1044 /* Determine where to set a single step breakpoint while considering
1045 branch prediction. */
1047 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1049 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1052 inst
= mips_fetch_instruction (gdbarch
, pc
);
1053 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1055 if (itype_op (inst
) >> 2 == 5)
1056 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1058 op
= (itype_op (inst
) & 0x03);
1068 goto greater_branch
;
1073 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1074 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1076 int tf
= itype_rt (inst
) & 0x01;
1077 int cnum
= itype_rt (inst
) >> 2;
1079 get_frame_register_signed (frame
,
1080 mips_regnum (get_frame_arch (frame
))->
1082 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1084 if (((cond
>> cnum
) & 0x01) == tf
)
1085 pc
+= mips32_relative_offset (inst
) + 4;
1090 pc
+= 4; /* Not a branch, next instruction is easy */
1093 { /* This gets way messy */
1095 /* Further subdivide into SPECIAL, REGIMM and other */
1096 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1098 case 0: /* SPECIAL */
1099 op
= rtype_funct (inst
);
1104 /* Set PC to that address */
1105 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1107 case 12: /* SYSCALL */
1109 struct gdbarch_tdep
*tdep
;
1111 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1112 if (tdep
->syscall_next_pc
!= NULL
)
1113 pc
= tdep
->syscall_next_pc (frame
);
1122 break; /* end SPECIAL */
1123 case 1: /* REGIMM */
1125 op
= itype_rt (inst
); /* branch condition */
1130 case 16: /* BLTZAL */
1131 case 18: /* BLTZALL */
1133 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1134 pc
+= mips32_relative_offset (inst
) + 4;
1136 pc
+= 8; /* after the delay slot */
1140 case 17: /* BGEZAL */
1141 case 19: /* BGEZALL */
1142 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1143 pc
+= mips32_relative_offset (inst
) + 4;
1145 pc
+= 8; /* after the delay slot */
1147 /* All of the other instructions in the REGIMM category */
1152 break; /* end REGIMM */
1157 reg
= jtype_target (inst
) << 2;
1158 /* Upper four bits get never changed... */
1159 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1162 /* FIXME case JALX : */
1165 reg
= jtype_target (inst
) << 2;
1166 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1167 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1169 break; /* The new PC will be alternate mode */
1170 case 4: /* BEQ, BEQL */
1172 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1173 get_frame_register_signed (frame
, itype_rt (inst
)))
1174 pc
+= mips32_relative_offset (inst
) + 4;
1178 case 5: /* BNE, BNEL */
1180 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1181 get_frame_register_signed (frame
, itype_rt (inst
)))
1182 pc
+= mips32_relative_offset (inst
) + 4;
1186 case 6: /* BLEZ, BLEZL */
1187 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1188 pc
+= mips32_relative_offset (inst
) + 4;
1194 greater_branch
: /* BGTZ, BGTZL */
1195 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1196 pc
+= mips32_relative_offset (inst
) + 4;
1203 } /* mips32_next_pc */
1205 /* Decoding the next place to set a breakpoint is irregular for the
1206 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1207 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1208 We dont want to set a single step instruction on the extend instruction
1212 /* Lots of mips16 instruction formats */
1213 /* Predicting jumps requires itype,ritype,i8type
1214 and their extensions extItype,extritype,extI8type
1216 enum mips16_inst_fmts
1218 itype
, /* 0 immediate 5,10 */
1219 ritype
, /* 1 5,3,8 */
1220 rrtype
, /* 2 5,3,3,5 */
1221 rritype
, /* 3 5,3,3,5 */
1222 rrrtype
, /* 4 5,3,3,3,2 */
1223 rriatype
, /* 5 5,3,3,1,4 */
1224 shifttype
, /* 6 5,3,3,3,2 */
1225 i8type
, /* 7 5,3,8 */
1226 i8movtype
, /* 8 5,3,3,5 */
1227 i8mov32rtype
, /* 9 5,3,5,3 */
1228 i64type
, /* 10 5,3,8 */
1229 ri64type
, /* 11 5,3,3,5 */
1230 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1231 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1232 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1233 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1234 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1235 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1236 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1237 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1238 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1239 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1241 /* I am heaping all the fields of the formats into one structure and
1242 then, only the fields which are involved in instruction extension */
1246 unsigned int regx
; /* Function in i8 type */
1251 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1252 for the bits which make up the immediate extension. */
1255 extended_offset (unsigned int extension
)
1258 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1260 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1262 value
|= extension
& 0x01f; /* extract 4:0 */
1266 /* Only call this function if you know that this is an extendable
1267 instruction. It won't malfunction, but why make excess remote memory
1268 references? If the immediate operands get sign extended or something,
1269 do it after the extension is performed. */
1270 /* FIXME: Every one of these cases needs to worry about sign extension
1271 when the offset is to be used in relative addressing. */
1274 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1276 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1278 pc
&= 0xfffffffe; /* clear the low order bit */
1279 target_read_memory (pc
, buf
, 2);
1280 return extract_unsigned_integer (buf
, 2, byte_order
);
1284 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1285 unsigned int extension
,
1287 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1292 switch (insn_format
)
1299 value
= extended_offset (extension
);
1300 value
= value
<< 11; /* rom for the original value */
1301 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1305 value
= inst
& 0x7ff;
1306 /* FIXME : Consider sign extension */
1315 { /* A register identifier and an offset */
1316 /* Most of the fields are the same as I type but the
1317 immediate value is of a different length */
1321 value
= extended_offset (extension
);
1322 value
= value
<< 8; /* from the original instruction */
1323 value
|= inst
& 0xff; /* eleven bits from instruction */
1324 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1325 if (value
& 0x4000) /* test the sign bit , bit 26 */
1327 value
&= ~0x3fff; /* remove the sign bit */
1333 value
= inst
& 0xff; /* 8 bits */
1334 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1335 /* FIXME: Do sign extension , this format needs it */
1336 if (value
& 0x80) /* THIS CONFUSES ME */
1338 value
&= 0xef; /* remove the sign bit */
1348 unsigned long value
;
1349 unsigned int nexthalf
;
1350 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1351 value
= value
<< 16;
1352 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit still set */
1360 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1362 upk
->offset
= offset
;
1369 add_offset_16 (CORE_ADDR pc
, int offset
)
1371 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1375 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1376 unsigned int extension
, unsigned int insn
)
1378 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1379 int op
= (insn
>> 11);
1382 case 2: /* Branch */
1385 struct upk_mips16 upk
;
1386 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1387 offset
= upk
.offset
;
1393 pc
+= (offset
<< 1) + 2;
1396 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1398 struct upk_mips16 upk
;
1399 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1400 pc
= add_offset_16 (pc
, upk
.offset
);
1401 if ((insn
>> 10) & 0x01) /* Exchange mode */
1402 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1409 struct upk_mips16 upk
;
1411 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1412 reg
= get_frame_register_signed (frame
, upk
.regx
);
1414 pc
+= (upk
.offset
<< 1) + 2;
1421 struct upk_mips16 upk
;
1423 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1424 reg
= get_frame_register_signed (frame
, upk
.regx
);
1426 pc
+= (upk
.offset
<< 1) + 2;
1431 case 12: /* I8 Formats btez btnez */
1433 struct upk_mips16 upk
;
1435 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1436 /* upk.regx contains the opcode */
1437 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1438 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1439 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1440 /* pc = add_offset_16(pc,upk.offset) ; */
1441 pc
+= (upk
.offset
<< 1) + 2;
1446 case 29: /* RR Formats JR, JALR, JALR-RA */
1448 struct upk_mips16 upk
;
1449 /* upk.fmt = rrtype; */
1454 upk
.regx
= (insn
>> 8) & 0x07;
1455 upk
.regy
= (insn
>> 5) & 0x07;
1463 break; /* Function return instruction */
1469 break; /* BOGUS Guess */
1471 pc
= get_frame_register_signed (frame
, reg
);
1478 /* This is an instruction extension. Fetch the real instruction
1479 (which follows the extension) and decode things based on
1483 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1484 fetch_mips_16 (gdbarch
, pc
));
1497 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1499 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1500 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1501 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1504 /* The mips_next_pc function supports single_step when the remote
1505 target monitor or stub is not developed enough to do a single_step.
1506 It works by decoding the current instruction and predicting where a
1507 branch will go. This isnt hard because all the data is available.
1508 The MIPS32 and MIPS16 variants are quite different. */
1510 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1512 if (is_mips16_addr (pc
))
1513 return mips16_next_pc (frame
, pc
);
1515 return mips32_next_pc (frame
, pc
);
1518 struct mips_frame_cache
1521 struct trad_frame_saved_reg
*saved_regs
;
1524 /* Set a register's saved stack address in temp_saved_regs. If an
1525 address has already been set for this register, do nothing; this
1526 way we will only recognize the first save of a given register in a
1529 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1530 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1531 Strictly speaking, only the second range is used as it is only second
1532 range (the ABI instead of ISA registers) that comes into play when finding
1533 saved registers in a frame. */
1536 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1537 int regnum
, CORE_ADDR offset
)
1539 if (this_cache
!= NULL
1540 && this_cache
->saved_regs
[regnum
].addr
== -1)
1542 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1544 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1550 /* Fetch the immediate value from a MIPS16 instruction.
1551 If the previous instruction was an EXTEND, use it to extend
1552 the upper bits of the immediate value. This is a helper function
1553 for mips16_scan_prologue. */
1556 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1557 unsigned short inst
, /* current instruction */
1558 int nbits
, /* number of bits in imm field */
1559 int scale
, /* scale factor to be applied to imm */
1560 int is_signed
) /* is the imm field signed? */
1564 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1566 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1567 if (offset
& 0x8000) /* check for negative extend */
1568 offset
= 0 - (0x10000 - (offset
& 0xffff));
1569 return offset
| (inst
& 0x1f);
1573 int max_imm
= 1 << nbits
;
1574 int mask
= max_imm
- 1;
1575 int sign_bit
= max_imm
>> 1;
1577 offset
= inst
& mask
;
1578 if (is_signed
&& (offset
& sign_bit
))
1579 offset
= 0 - (max_imm
- offset
);
1580 return offset
* scale
;
1585 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1586 the associated FRAME_CACHE if not null.
1587 Return the address of the first instruction past the prologue. */
1590 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1591 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1592 struct frame_info
*this_frame
,
1593 struct mips_frame_cache
*this_cache
)
1596 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1598 long frame_offset
= 0; /* Size of stack frame. */
1599 long frame_adjust
= 0; /* Offset of FP from SP. */
1600 int frame_reg
= MIPS_SP_REGNUM
;
1601 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1602 unsigned inst
= 0; /* current instruction */
1603 unsigned entry_inst
= 0; /* the entry instruction */
1604 unsigned save_inst
= 0; /* the save instruction */
1607 int extend_bytes
= 0;
1608 int prev_extend_bytes
;
1609 CORE_ADDR end_prologue_addr
= 0;
1611 /* Can be called when there's no process, and hence when there's no
1613 if (this_frame
!= NULL
)
1614 sp
= get_frame_register_signed (this_frame
,
1615 gdbarch_num_regs (gdbarch
)
1620 if (limit_pc
> start_pc
+ 200)
1621 limit_pc
= start_pc
+ 200;
1623 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1625 /* Save the previous instruction. If it's an EXTEND, we'll extract
1626 the immediate offset extension from it in mips16_get_imm. */
1629 /* Fetch and decode the instruction. */
1630 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1632 /* Normally we ignore extend instructions. However, if it is
1633 not followed by a valid prologue instruction, then this
1634 instruction is not part of the prologue either. We must
1635 remember in this case to adjust the end_prologue_addr back
1637 if ((inst
& 0xf800) == 0xf000) /* extend */
1639 extend_bytes
= MIPS_INSN16_SIZE
;
1643 prev_extend_bytes
= extend_bytes
;
1646 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1647 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1649 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1650 if (offset
< 0) /* negative stack adjustment? */
1651 frame_offset
-= offset
;
1653 /* Exit loop if a positive stack adjustment is found, which
1654 usually means that the stack cleanup code in the function
1655 epilogue is reached. */
1658 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1660 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1661 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1662 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1664 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1666 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1667 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1668 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1670 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1672 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1673 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1675 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1677 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1678 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1680 else if (inst
== 0x673d) /* move $s1, $sp */
1685 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1687 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1688 frame_addr
= sp
+ offset
;
1690 frame_adjust
= offset
;
1692 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1694 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1695 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1696 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1698 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1700 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1701 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1702 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1704 else if ((inst
& 0xf81f) == 0xe809
1705 && (inst
& 0x700) != 0x700) /* entry */
1706 entry_inst
= inst
; /* save for later processing */
1707 else if ((inst
& 0xff80) == 0x6480) /* save */
1709 save_inst
= inst
; /* save for later processing */
1710 if (prev_extend_bytes
) /* extend */
1711 save_inst
|= prev_inst
<< 16;
1713 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1714 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1715 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1717 /* This instruction is part of the prologue, but we don't
1718 need to do anything special to handle it. */
1722 /* This instruction is not an instruction typically found
1723 in a prologue, so we must have reached the end of the
1725 if (end_prologue_addr
== 0)
1726 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1730 /* The entry instruction is typically the first instruction in a function,
1731 and it stores registers at offsets relative to the value of the old SP
1732 (before the prologue). But the value of the sp parameter to this
1733 function is the new SP (after the prologue has been executed). So we
1734 can't calculate those offsets until we've seen the entire prologue,
1735 and can calculate what the old SP must have been. */
1736 if (entry_inst
!= 0)
1738 int areg_count
= (entry_inst
>> 8) & 7;
1739 int sreg_count
= (entry_inst
>> 6) & 3;
1741 /* The entry instruction always subtracts 32 from the SP. */
1744 /* Now we can calculate what the SP must have been at the
1745 start of the function prologue. */
1748 /* Check if a0-a3 were saved in the caller's argument save area. */
1749 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1751 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1752 offset
+= mips_abi_regsize (gdbarch
);
1755 /* Check if the ra register was pushed on the stack. */
1757 if (entry_inst
& 0x20)
1759 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1760 offset
-= mips_abi_regsize (gdbarch
);
1763 /* Check if the s0 and s1 registers were pushed on the stack. */
1764 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1766 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1767 offset
-= mips_abi_regsize (gdbarch
);
1771 /* The SAVE instruction is similar to ENTRY, except that defined by the
1772 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1773 size of the frame is specified as an immediate field of instruction
1774 and an extended variation exists which lets additional registers and
1775 frame space to be specified. The instruction always treats registers
1776 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1777 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1779 static int args_table
[16] = {
1780 0, 0, 0, 0, 1, 1, 1, 1,
1781 2, 2, 2, 0, 3, 3, 4, -1,
1783 static int astatic_table
[16] = {
1784 0, 1, 2, 3, 0, 1, 2, 3,
1785 0, 1, 2, 4, 0, 1, 0, -1,
1787 int aregs
= (save_inst
>> 16) & 0xf;
1788 int xsregs
= (save_inst
>> 24) & 0x7;
1789 int args
= args_table
[aregs
];
1790 int astatic
= astatic_table
[aregs
];
1795 warning (_("Invalid number of argument registers encoded in SAVE."));
1800 warning (_("Invalid number of static registers encoded in SAVE."));
1804 /* For standard SAVE the frame size of 0 means 128. */
1805 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1806 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1809 frame_offset
+= frame_size
;
1811 /* Now we can calculate what the SP must have been at the
1812 start of the function prologue. */
1815 /* Check if A0-A3 were saved in the caller's argument save area. */
1816 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1818 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1819 offset
+= mips_abi_regsize (gdbarch
);
1824 /* Check if the RA register was pushed on the stack. */
1825 if (save_inst
& 0x40)
1827 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1828 offset
-= mips_abi_regsize (gdbarch
);
1831 /* Check if the S8 register was pushed on the stack. */
1834 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1835 offset
-= mips_abi_regsize (gdbarch
);
1838 /* Check if S2-S7 were pushed on the stack. */
1839 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1841 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1842 offset
-= mips_abi_regsize (gdbarch
);
1845 /* Check if the S1 register was pushed on the stack. */
1846 if (save_inst
& 0x10)
1848 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1849 offset
-= mips_abi_regsize (gdbarch
);
1851 /* Check if the S0 register was pushed on the stack. */
1852 if (save_inst
& 0x20)
1854 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1855 offset
-= mips_abi_regsize (gdbarch
);
1858 /* Check if A0-A3 were pushed on the stack. */
1859 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1861 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1862 offset
-= mips_abi_regsize (gdbarch
);
1866 if (this_cache
!= NULL
)
1869 (get_frame_register_signed (this_frame
,
1870 gdbarch_num_regs (gdbarch
) + frame_reg
)
1871 + frame_offset
- frame_adjust
);
1872 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1873 be able to get rid of the assignment below, evetually. But it's
1874 still needed for now. */
1875 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1876 + mips_regnum (gdbarch
)->pc
]
1877 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1880 /* If we didn't reach the end of the prologue when scanning the function
1881 instructions, then set end_prologue_addr to the address of the
1882 instruction immediately after the last one we scanned. */
1883 if (end_prologue_addr
== 0)
1884 end_prologue_addr
= cur_pc
;
1886 return end_prologue_addr
;
1889 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1890 Procedures that use the 32-bit instruction set are handled by the
1891 mips_insn32 unwinder. */
1893 static struct mips_frame_cache
*
1894 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1896 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1897 struct mips_frame_cache
*cache
;
1899 if ((*this_cache
) != NULL
)
1900 return (*this_cache
);
1901 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1902 (*this_cache
) = cache
;
1903 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1905 /* Analyze the function prologue. */
1907 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1908 CORE_ADDR start_addr
;
1910 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1911 if (start_addr
== 0)
1912 start_addr
= heuristic_proc_start (gdbarch
, pc
);
1913 /* We can't analyze the prologue if we couldn't find the begining
1915 if (start_addr
== 0)
1918 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
1921 /* gdbarch_sp_regnum contains the value and not the address. */
1922 trad_frame_set_value (cache
->saved_regs
,
1923 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
1926 return (*this_cache
);
1930 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1931 struct frame_id
*this_id
)
1933 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1935 /* This marks the outermost frame. */
1936 if (info
->base
== 0)
1938 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1941 static struct value
*
1942 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1943 void **this_cache
, int regnum
)
1945 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1947 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1951 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1952 struct frame_info
*this_frame
, void **this_cache
)
1954 CORE_ADDR pc
= get_frame_pc (this_frame
);
1955 if (mips_pc_is_mips16 (pc
))
1960 static const struct frame_unwind mips_insn16_frame_unwind
=
1963 mips_insn16_frame_this_id
,
1964 mips_insn16_frame_prev_register
,
1966 mips_insn16_frame_sniffer
1970 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
1973 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1978 static const struct frame_base mips_insn16_frame_base
=
1980 &mips_insn16_frame_unwind
,
1981 mips_insn16_frame_base_address
,
1982 mips_insn16_frame_base_address
,
1983 mips_insn16_frame_base_address
1986 static const struct frame_base
*
1987 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
1989 CORE_ADDR pc
= get_frame_pc (this_frame
);
1990 if (mips_pc_is_mips16 (pc
))
1991 return &mips_insn16_frame_base
;
1996 /* Mark all the registers as unset in the saved_regs array
1997 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2000 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2002 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2006 const int num_regs
= gdbarch_num_regs (gdbarch
);
2009 for (i
= 0; i
< num_regs
; i
++)
2011 this_cache
->saved_regs
[i
].addr
= -1;
2016 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2017 the associated FRAME_CACHE if not null.
2018 Return the address of the first instruction past the prologue. */
2021 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2022 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2023 struct frame_info
*this_frame
,
2024 struct mips_frame_cache
*this_cache
)
2027 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2030 int frame_reg
= MIPS_SP_REGNUM
;
2032 CORE_ADDR end_prologue_addr
= 0;
2033 int seen_sp_adjust
= 0;
2034 int load_immediate_bytes
= 0;
2035 int in_delay_slot
= 0;
2036 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2038 /* Can be called when there's no process, and hence when there's no
2040 if (this_frame
!= NULL
)
2041 sp
= get_frame_register_signed (this_frame
,
2042 gdbarch_num_regs (gdbarch
)
2047 if (limit_pc
> start_pc
+ 200)
2048 limit_pc
= start_pc
+ 200;
2053 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2055 unsigned long inst
, high_word
, low_word
;
2058 /* Fetch the instruction. */
2059 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2061 /* Save some code by pre-extracting some useful fields. */
2062 high_word
= (inst
>> 16) & 0xffff;
2063 low_word
= inst
& 0xffff;
2064 reg
= high_word
& 0x1f;
2066 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2067 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2068 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2070 if (low_word
& 0x8000) /* negative stack adjustment? */
2071 frame_offset
+= 0x10000 - low_word
;
2073 /* Exit loop if a positive stack adjustment is found, which
2074 usually means that the stack cleanup code in the function
2075 epilogue is reached. */
2079 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2080 && !regsize_is_64_bits
)
2082 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2084 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2085 && regsize_is_64_bits
)
2087 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2088 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2090 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2092 /* Old gcc frame, r30 is virtual frame pointer. */
2093 if ((long) low_word
!= frame_offset
)
2094 frame_addr
= sp
+ low_word
;
2095 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2097 unsigned alloca_adjust
;
2100 frame_addr
= get_frame_register_signed
2101 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2103 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2104 if (alloca_adjust
> 0)
2106 /* FP > SP + frame_size. This may be because of
2107 an alloca or somethings similar. Fix sp to
2108 "pre-alloca" value, and try again. */
2109 sp
+= alloca_adjust
;
2110 /* Need to reset the status of all registers. Otherwise,
2111 we will hit a guard that prevents the new address
2112 for each register to be recomputed during the second
2114 reset_saved_regs (gdbarch
, this_cache
);
2119 /* move $30,$sp. With different versions of gas this will be either
2120 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2121 Accept any one of these. */
2122 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2124 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2125 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2127 unsigned alloca_adjust
;
2130 frame_addr
= get_frame_register_signed
2131 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2133 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2134 if (alloca_adjust
> 0)
2136 /* FP > SP + frame_size. This may be because of
2137 an alloca or somethings similar. Fix sp to
2138 "pre-alloca" value, and try again. */
2140 /* Need to reset the status of all registers. Otherwise,
2141 we will hit a guard that prevents the new address
2142 for each register to be recomputed during the second
2144 reset_saved_regs (gdbarch
, this_cache
);
2149 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2150 && !regsize_is_64_bits
)
2152 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2154 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2155 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2156 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2157 || high_word
== 0x3c1c /* lui $gp,n */
2158 || high_word
== 0x279c /* addiu $gp,$gp,n */
2159 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2160 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2163 /* These instructions are part of the prologue, but we don't
2164 need to do anything special to handle them. */
2166 /* The instructions below load $at or $t0 with an immediate
2167 value in preparation for a stack adjustment via
2168 subu $sp,$sp,[$at,$t0]. These instructions could also
2169 initialize a local variable, so we accept them only before
2170 a stack adjustment instruction was seen. */
2171 else if (!seen_sp_adjust
2172 && (high_word
== 0x3c01 /* lui $at,n */
2173 || high_word
== 0x3c08 /* lui $t0,n */
2174 || high_word
== 0x3421 /* ori $at,$at,n */
2175 || high_word
== 0x3508 /* ori $t0,$t0,n */
2176 || high_word
== 0x3401 /* ori $at,$zero,n */
2177 || high_word
== 0x3408 /* ori $t0,$zero,n */
2180 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2184 /* This instruction is not an instruction typically found
2185 in a prologue, so we must have reached the end of the
2187 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2188 loop now? Why would we need to continue scanning the function
2190 if (end_prologue_addr
== 0)
2191 end_prologue_addr
= cur_pc
;
2193 /* Check for branches and jumps. For now, only jump to
2194 register are caught (i.e. returns). */
2195 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2199 /* If the previous instruction was a jump, we must have reached
2200 the end of the prologue by now. Stop scanning so that we do
2201 not go past the function return. */
2206 if (this_cache
!= NULL
)
2209 (get_frame_register_signed (this_frame
,
2210 gdbarch_num_regs (gdbarch
) + frame_reg
)
2212 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2213 this assignment below, eventually. But it's still needed
2215 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2216 + mips_regnum (gdbarch
)->pc
]
2217 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2221 /* If we didn't reach the end of the prologue when scanning the function
2222 instructions, then set end_prologue_addr to the address of the
2223 instruction immediately after the last one we scanned. */
2224 /* brobecker/2004-10-10: I don't think this would ever happen, but
2225 we may as well be careful and do our best if we have a null
2226 end_prologue_addr. */
2227 if (end_prologue_addr
== 0)
2228 end_prologue_addr
= cur_pc
;
2230 /* In a frameless function, we might have incorrectly
2231 skipped some load immediate instructions. Undo the skipping
2232 if the load immediate was not followed by a stack adjustment. */
2233 if (load_immediate_bytes
&& !seen_sp_adjust
)
2234 end_prologue_addr
-= load_immediate_bytes
;
2236 return end_prologue_addr
;
2239 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2240 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2241 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2244 static struct mips_frame_cache
*
2245 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2247 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2248 struct mips_frame_cache
*cache
;
2250 if ((*this_cache
) != NULL
)
2251 return (*this_cache
);
2253 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2254 (*this_cache
) = cache
;
2255 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2257 /* Analyze the function prologue. */
2259 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2260 CORE_ADDR start_addr
;
2262 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2263 if (start_addr
== 0)
2264 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2265 /* We can't analyze the prologue if we couldn't find the begining
2267 if (start_addr
== 0)
2270 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2273 /* gdbarch_sp_regnum contains the value and not the address. */
2274 trad_frame_set_value (cache
->saved_regs
,
2275 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2278 return (*this_cache
);
2282 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2283 struct frame_id
*this_id
)
2285 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2287 /* This marks the outermost frame. */
2288 if (info
->base
== 0)
2290 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2293 static struct value
*
2294 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2295 void **this_cache
, int regnum
)
2297 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2299 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2303 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2304 struct frame_info
*this_frame
, void **this_cache
)
2306 CORE_ADDR pc
= get_frame_pc (this_frame
);
2307 if (! mips_pc_is_mips16 (pc
))
2312 static const struct frame_unwind mips_insn32_frame_unwind
=
2315 mips_insn32_frame_this_id
,
2316 mips_insn32_frame_prev_register
,
2318 mips_insn32_frame_sniffer
2322 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2325 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2330 static const struct frame_base mips_insn32_frame_base
=
2332 &mips_insn32_frame_unwind
,
2333 mips_insn32_frame_base_address
,
2334 mips_insn32_frame_base_address
,
2335 mips_insn32_frame_base_address
2338 static const struct frame_base
*
2339 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2341 CORE_ADDR pc
= get_frame_pc (this_frame
);
2342 if (! mips_pc_is_mips16 (pc
))
2343 return &mips_insn32_frame_base
;
2348 static struct trad_frame_cache
*
2349 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2352 CORE_ADDR start_addr
;
2353 CORE_ADDR stack_addr
;
2354 struct trad_frame_cache
*this_trad_cache
;
2355 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2356 int num_regs
= gdbarch_num_regs (gdbarch
);
2358 if ((*this_cache
) != NULL
)
2359 return (*this_cache
);
2360 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2361 (*this_cache
) = this_trad_cache
;
2363 /* The return address is in the link register. */
2364 trad_frame_set_reg_realreg (this_trad_cache
,
2365 gdbarch_pc_regnum (gdbarch
),
2366 num_regs
+ MIPS_RA_REGNUM
);
2368 /* Frame ID, since it's a frameless / stackless function, no stack
2369 space is allocated and SP on entry is the current SP. */
2370 pc
= get_frame_pc (this_frame
);
2371 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2372 stack_addr
= get_frame_register_signed (this_frame
,
2373 num_regs
+ MIPS_SP_REGNUM
);
2374 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2376 /* Assume that the frame's base is the same as the
2378 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2380 return this_trad_cache
;
2384 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2385 struct frame_id
*this_id
)
2387 struct trad_frame_cache
*this_trad_cache
2388 = mips_stub_frame_cache (this_frame
, this_cache
);
2389 trad_frame_get_id (this_trad_cache
, this_id
);
2392 static struct value
*
2393 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2394 void **this_cache
, int regnum
)
2396 struct trad_frame_cache
*this_trad_cache
2397 = mips_stub_frame_cache (this_frame
, this_cache
);
2398 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2402 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2403 struct frame_info
*this_frame
, void **this_cache
)
2406 struct obj_section
*s
;
2407 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2408 struct minimal_symbol
*msym
;
2410 /* Use the stub unwinder for unreadable code. */
2411 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2414 if (in_plt_section (pc
, NULL
))
2417 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2418 s
= find_pc_section (pc
);
2421 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2422 ".MIPS.stubs") == 0)
2425 /* Calling a PIC function from a non-PIC function passes through a
2426 stub. The stub for foo is named ".pic.foo". */
2427 msym
= lookup_minimal_symbol_by_pc (pc
);
2429 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2430 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2436 static const struct frame_unwind mips_stub_frame_unwind
=
2439 mips_stub_frame_this_id
,
2440 mips_stub_frame_prev_register
,
2442 mips_stub_frame_sniffer
2446 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2449 struct trad_frame_cache
*this_trad_cache
2450 = mips_stub_frame_cache (this_frame
, this_cache
);
2451 return trad_frame_get_this_base (this_trad_cache
);
2454 static const struct frame_base mips_stub_frame_base
=
2456 &mips_stub_frame_unwind
,
2457 mips_stub_frame_base_address
,
2458 mips_stub_frame_base_address
,
2459 mips_stub_frame_base_address
2462 static const struct frame_base
*
2463 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2465 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2466 return &mips_stub_frame_base
;
2471 /* mips_addr_bits_remove - remove useless address bits */
2474 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2476 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2478 if (is_mips16_addr (addr
))
2479 addr
= unmake_mips16_addr (addr
);
2481 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2482 /* This hack is a work-around for existing boards using PMON, the
2483 simulator, and any other 64-bit targets that doesn't have true
2484 64-bit addressing. On these targets, the upper 32 bits of
2485 addresses are ignored by the hardware. Thus, the PC or SP are
2486 likely to have been sign extended to all 1s by instruction
2487 sequences that load 32-bit addresses. For example, a typical
2488 piece of code that loads an address is this:
2490 lui $r2, <upper 16 bits>
2491 ori $r2, <lower 16 bits>
2493 But the lui sign-extends the value such that the upper 32 bits
2494 may be all 1s. The workaround is simply to mask off these
2495 bits. In the future, gcc may be changed to support true 64-bit
2496 addressing, and this masking will have to be disabled. */
2497 return addr
&= 0xffffffffUL
;
2502 /* Instructions used during single-stepping of atomic sequences. */
2503 #define LL_OPCODE 0x30
2504 #define LLD_OPCODE 0x34
2505 #define SC_OPCODE 0x38
2506 #define SCD_OPCODE 0x3c
2508 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2509 instruction and ending with a SC/SCD instruction. If such a sequence
2510 is found, attempt to step through it. A breakpoint is placed at the end of
2514 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2515 struct address_space
*aspace
, CORE_ADDR pc
)
2517 CORE_ADDR breaks
[2] = {-1, -1};
2519 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2523 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2524 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2529 insn
= mips_fetch_instruction (gdbarch
, loc
);
2530 /* Assume all atomic sequences start with a ll/lld instruction. */
2531 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2534 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2536 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2539 loc
+= MIPS_INSN32_SIZE
;
2540 insn
= mips_fetch_instruction (gdbarch
, loc
);
2542 /* Assume that there is at most one branch in the atomic
2543 sequence. If a branch is found, put a breakpoint in its
2544 destination address. */
2545 switch (itype_op (insn
))
2547 case 0: /* SPECIAL */
2548 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2549 return 0; /* fallback to the standard single-step code. */
2551 case 1: /* REGIMM */
2552 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2556 return 0; /* fallback to the standard single-step code. */
2563 case 22: /* BLEZL */
2564 case 23: /* BGTTL */
2570 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2575 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2576 if (last_breakpoint
>= 1)
2577 return 0; /* More than one branch found, fallback to the
2578 standard single-step code. */
2579 breaks
[1] = branch_bp
;
2583 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2587 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2588 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2591 loc
+= MIPS_INSN32_SIZE
;
2593 /* Insert a breakpoint right after the end of the atomic sequence. */
2596 /* Check for duplicated breakpoints. Check also for a breakpoint
2597 placed (branch instruction's destination) in the atomic sequence */
2598 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2599 last_breakpoint
= 0;
2601 /* Effectively inserts the breakpoints. */
2602 for (index
= 0; index
<= last_breakpoint
; index
++)
2603 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2608 /* mips_software_single_step() is called just before we want to resume
2609 the inferior, if we want to single-step it but there is no hardware
2610 or kernel single-step support (MIPS on GNU/Linux for example). We find
2611 the target of the coming instruction and breakpoint it. */
2614 mips_software_single_step (struct frame_info
*frame
)
2616 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2617 struct address_space
*aspace
= get_frame_address_space (frame
);
2618 CORE_ADDR pc
, next_pc
;
2620 pc
= get_frame_pc (frame
);
2621 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2624 next_pc
= mips_next_pc (frame
, pc
);
2626 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2630 /* Test whether the PC points to the return instruction at the
2631 end of a function. */
2634 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2636 if (mips_pc_is_mips16 (pc
))
2637 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2638 generates a "jr $ra"; other times it generates code to load
2639 the return address from the stack to an accessible register (such
2640 as $a3), then a "jr" using that register. This second case
2641 is almost impossible to distinguish from an indirect jump
2642 used for switch statements, so we don't even try. */
2643 return mips_fetch_instruction (gdbarch
, pc
) == 0xe820; /* jr $ra */
2645 return mips_fetch_instruction (gdbarch
, pc
) == 0x3e00008; /* jr $ra */
2649 /* This fencepost looks highly suspicious to me. Removing it also
2650 seems suspicious as it could affect remote debugging across serial
2654 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2660 struct inferior
*inf
;
2662 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2664 fence
= start_pc
- heuristic_fence_post
;
2668 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2669 fence
= VM_MIN_ADDRESS
;
2671 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2673 inf
= current_inferior ();
2675 /* search back for previous return */
2676 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2677 if (start_pc
< fence
)
2679 /* It's not clear to me why we reach this point when
2680 stop_soon, but with this test, at least we
2681 don't print out warnings for every child forked (eg, on
2682 decstation). 22apr93 rich@cygnus.com. */
2683 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2685 static int blurb_printed
= 0;
2687 warning (_("GDB can't find the start of the function at %s."),
2688 paddress (gdbarch
, pc
));
2692 /* This actually happens frequently in embedded
2693 development, when you first connect to a board
2694 and your stack pointer and pc are nowhere in
2695 particular. This message needs to give people
2696 in that situation enough information to
2697 determine that it's no big deal. */
2698 printf_filtered ("\n\
2699 GDB is unable to find the start of the function at %s\n\
2700 and thus can't determine the size of that function's stack frame.\n\
2701 This means that GDB may be unable to access that stack frame, or\n\
2702 the frames below it.\n\
2703 This problem is most likely caused by an invalid program counter or\n\
2705 However, if you think GDB should simply search farther back\n\
2706 from %s for code which looks like the beginning of a\n\
2707 function, you can increase the range of the search using the `set\n\
2708 heuristic-fence-post' command.\n",
2709 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2716 else if (mips_pc_is_mips16 (start_pc
))
2718 unsigned short inst
;
2720 /* On MIPS16, any one of the following is likely to be the
2721 start of a function:
2727 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2728 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2729 if ((inst
& 0xff80) == 0x6480) /* save */
2731 if (start_pc
- instlen
>= fence
)
2733 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2734 if ((inst
& 0xf800) == 0xf000) /* extend */
2735 start_pc
-= instlen
;
2739 else if (((inst
& 0xf81f) == 0xe809
2740 && (inst
& 0x700) != 0x700) /* entry */
2741 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2742 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2743 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2745 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2746 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2751 else if (mips_about_to_return (gdbarch
, start_pc
))
2753 /* Skip return and its delay slot. */
2754 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2761 struct mips_objfile_private
2767 /* According to the current ABI, should the type be passed in a
2768 floating-point register (assuming that there is space)? When there
2769 is no FPU, FP are not even considered as possible candidates for
2770 FP registers and, consequently this returns false - forces FP
2771 arguments into integer registers. */
2774 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2775 struct type
*arg_type
)
2777 return ((typecode
== TYPE_CODE_FLT
2778 || (MIPS_EABI (gdbarch
)
2779 && (typecode
== TYPE_CODE_STRUCT
2780 || typecode
== TYPE_CODE_UNION
)
2781 && TYPE_NFIELDS (arg_type
) == 1
2782 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2784 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2787 /* On o32, argument passing in GPRs depends on the alignment of the type being
2788 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2791 mips_type_needs_double_align (struct type
*type
)
2793 enum type_code typecode
= TYPE_CODE (type
);
2795 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2797 else if (typecode
== TYPE_CODE_STRUCT
)
2799 if (TYPE_NFIELDS (type
) < 1)
2801 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2803 else if (typecode
== TYPE_CODE_UNION
)
2807 n
= TYPE_NFIELDS (type
);
2808 for (i
= 0; i
< n
; i
++)
2809 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2816 /* Adjust the address downward (direction of stack growth) so that it
2817 is correctly aligned for a new stack frame. */
2819 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2821 return align_down (addr
, 16);
2825 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2826 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2827 int nargs
, struct value
**args
, CORE_ADDR sp
,
2828 int struct_return
, CORE_ADDR struct_addr
)
2834 int stack_offset
= 0;
2835 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2836 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2837 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2838 int regsize
= mips_abi_regsize (gdbarch
);
2840 /* For shared libraries, "t9" needs to point at the function
2842 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2844 /* Set the return address register to point to the entry point of
2845 the program, where a breakpoint lies in wait. */
2846 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2848 /* First ensure that the stack and structure return address (if any)
2849 are properly aligned. The stack has to be at least 64-bit
2850 aligned even on 32-bit machines, because doubles must be 64-bit
2851 aligned. For n32 and n64, stack frames need to be 128-bit
2852 aligned, so we round to this widest known alignment. */
2854 sp
= align_down (sp
, 16);
2855 struct_addr
= align_down (struct_addr
, 16);
2857 /* Now make space on the stack for the args. We allocate more
2858 than necessary for EABI, because the first few arguments are
2859 passed in registers, but that's OK. */
2860 for (argnum
= 0; argnum
< nargs
; argnum
++)
2861 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2862 sp
-= align_up (len
, 16);
2865 fprintf_unfiltered (gdb_stdlog
,
2866 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
2867 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
2869 /* Initialize the integer and float register pointers. */
2870 argreg
= MIPS_A0_REGNUM
;
2871 float_argreg
= mips_fpa0_regnum (gdbarch
);
2873 /* The struct_return pointer occupies the first parameter-passing reg. */
2877 fprintf_unfiltered (gdb_stdlog
,
2878 "mips_eabi_push_dummy_call: struct_return reg=%d %s\n",
2879 argreg
, paddress (gdbarch
, struct_addr
));
2880 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2883 /* Now load as many as possible of the first arguments into
2884 registers, and push the rest onto the stack. Loop thru args
2885 from first to last. */
2886 for (argnum
= 0; argnum
< nargs
; argnum
++)
2888 const gdb_byte
*val
;
2889 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2890 struct value
*arg
= args
[argnum
];
2891 struct type
*arg_type
= check_typedef (value_type (arg
));
2892 int len
= TYPE_LENGTH (arg_type
);
2893 enum type_code typecode
= TYPE_CODE (arg_type
);
2896 fprintf_unfiltered (gdb_stdlog
,
2897 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2898 argnum
+ 1, len
, (int) typecode
);
2900 /* Function pointer arguments to mips16 code need to be made into
2902 if (typecode
== TYPE_CODE_PTR
2903 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
2905 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
2907 if (mips_pc_is_mips16 (addr
))
2909 store_signed_integer (valbuf
, len
, byte_order
,
2910 make_mips16_addr (addr
));
2914 val
= value_contents (arg
);
2916 /* The EABI passes structures that do not fit in a register by
2918 else if (len
> regsize
2919 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2921 store_unsigned_integer (valbuf
, regsize
, byte_order
,
2922 value_address (arg
));
2923 typecode
= TYPE_CODE_PTR
;
2927 fprintf_unfiltered (gdb_stdlog
, " push");
2930 val
= value_contents (arg
);
2932 /* 32-bit ABIs always start floating point arguments in an
2933 even-numbered floating point register. Round the FP register
2934 up before the check to see if there are any FP registers
2935 left. Non MIPS_EABI targets also pass the FP in the integer
2936 registers so also round up normal registers. */
2937 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2939 if ((float_argreg
& 1))
2943 /* Floating point arguments passed in registers have to be
2944 treated specially. On 32-bit architectures, doubles
2945 are passed in register pairs; the even register gets
2946 the low word, and the odd register gets the high word.
2947 On non-EABI processors, the first two floating point arguments are
2948 also copied to general registers, because MIPS16 functions
2949 don't use float registers for arguments. This duplication of
2950 arguments in general registers can't hurt non-MIPS16 functions
2951 because those registers are normally skipped. */
2952 /* MIPS_EABI squeezes a struct that contains a single floating
2953 point value into an FP register instead of pushing it onto the
2955 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
2956 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
2958 /* EABI32 will pass doubles in consecutive registers, even on
2959 64-bit cores. At one time, we used to check the size of
2960 `float_argreg' to determine whether or not to pass doubles
2961 in consecutive registers, but this is not sufficient for
2962 making the ABI determination. */
2963 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2965 int low_offset
= gdbarch_byte_order (gdbarch
)
2966 == BFD_ENDIAN_BIG
? 4 : 0;
2969 /* Write the low word of the double to the even register(s). */
2970 regval
= extract_signed_integer (val
+ low_offset
,
2973 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2974 float_argreg
, phex (regval
, 4));
2975 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
2977 /* Write the high word of the double to the odd register(s). */
2978 regval
= extract_signed_integer (val
+ 4 - low_offset
,
2981 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2982 float_argreg
, phex (regval
, 4));
2983 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
2987 /* This is a floating point value that fits entirely
2988 in a single register. */
2989 /* On 32 bit ABI's the float_argreg is further adjusted
2990 above to ensure that it is even register aligned. */
2991 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
2993 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2994 float_argreg
, phex (regval
, len
));
2995 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3000 /* Copy the argument to general registers or the stack in
3001 register-sized pieces. Large arguments are split between
3002 registers and stack. */
3003 /* Note: structs whose size is not a multiple of regsize
3004 are treated specially: Irix cc passes
3005 them in registers where gcc sometimes puts them on the
3006 stack. For maximum compatibility, we will put them in
3008 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3010 /* Note: Floating-point values that didn't fit into an FP
3011 register are only written to memory. */
3014 /* Remember if the argument was written to the stack. */
3015 int stack_used_p
= 0;
3016 int partial_len
= (len
< regsize
? len
: regsize
);
3019 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3022 /* Write this portion of the argument to the stack. */
3023 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3025 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3027 /* Should shorter than int integer values be
3028 promoted to int before being stored? */
3029 int longword_offset
= 0;
3032 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3035 && (typecode
== TYPE_CODE_INT
3036 || typecode
== TYPE_CODE_PTR
3037 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3038 longword_offset
= regsize
- len
;
3039 else if ((typecode
== TYPE_CODE_STRUCT
3040 || typecode
== TYPE_CODE_UNION
)
3041 && TYPE_LENGTH (arg_type
) < regsize
)
3042 longword_offset
= regsize
- len
;
3047 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3048 paddress (gdbarch
, stack_offset
));
3049 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3050 paddress (gdbarch
, longword_offset
));
3053 addr
= sp
+ stack_offset
+ longword_offset
;
3058 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3059 paddress (gdbarch
, addr
));
3060 for (i
= 0; i
< partial_len
; i
++)
3062 fprintf_unfiltered (gdb_stdlog
, "%02x",
3066 write_memory (addr
, val
, partial_len
);
3069 /* Note!!! This is NOT an else clause. Odd sized
3070 structs may go thru BOTH paths. Floating point
3071 arguments will not. */
3072 /* Write this portion of the argument to a general
3073 purpose register. */
3074 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3075 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3078 extract_signed_integer (val
, partial_len
, byte_order
);
3081 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3083 phex (regval
, regsize
));
3084 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3091 /* Compute the the offset into the stack at which we
3092 will copy the next parameter.
3094 In the new EABI (and the NABI32), the stack_offset
3095 only needs to be adjusted when it has been used. */
3098 stack_offset
+= align_up (partial_len
, regsize
);
3102 fprintf_unfiltered (gdb_stdlog
, "\n");
3105 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3107 /* Return adjusted stack pointer. */
3111 /* Determine the return value convention being used. */
3113 static enum return_value_convention
3114 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3115 struct type
*type
, struct regcache
*regcache
,
3116 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3118 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3119 int fp_return_type
= 0;
3120 int offset
, regnum
, xfer
;
3122 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3123 return RETURN_VALUE_STRUCT_CONVENTION
;
3125 /* Floating point type? */
3126 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3128 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3130 /* Structs with a single field of float type
3131 are returned in a floating point register. */
3132 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3133 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3134 && TYPE_NFIELDS (type
) == 1)
3136 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3138 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3145 /* A floating-point value belongs in the least significant part
3148 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3149 regnum
= mips_regnum (gdbarch
)->fp0
;
3153 /* An integer value goes in V0/V1. */
3155 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3156 regnum
= MIPS_V0_REGNUM
;
3159 offset
< TYPE_LENGTH (type
);
3160 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3162 xfer
= mips_abi_regsize (gdbarch
);
3163 if (offset
+ xfer
> TYPE_LENGTH (type
))
3164 xfer
= TYPE_LENGTH (type
) - offset
;
3165 mips_xfer_register (gdbarch
, regcache
,
3166 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3167 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3171 return RETURN_VALUE_REGISTER_CONVENTION
;
3175 /* N32/N64 ABI stuff. */
3177 /* Search for a naturally aligned double at OFFSET inside a struct
3178 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3182 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3187 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3190 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3193 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3196 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3199 struct type
*field_type
;
3201 /* We're only looking at normal fields. */
3202 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3203 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3206 /* If we have gone past the offset, there is no double to pass. */
3207 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3211 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3213 /* If this field is entirely before the requested offset, go
3214 on to the next one. */
3215 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3218 /* If this is our special aligned double, we can stop. */
3219 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3220 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3223 /* This field starts at or before the requested offset, and
3224 overlaps it. If it is a structure, recurse inwards. */
3225 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3232 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3233 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3234 int nargs
, struct value
**args
, CORE_ADDR sp
,
3235 int struct_return
, CORE_ADDR struct_addr
)
3241 int stack_offset
= 0;
3242 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3243 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3244 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3246 /* For shared libraries, "t9" needs to point at the function
3248 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3250 /* Set the return address register to point to the entry point of
3251 the program, where a breakpoint lies in wait. */
3252 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3254 /* First ensure that the stack and structure return address (if any)
3255 are properly aligned. The stack has to be at least 64-bit
3256 aligned even on 32-bit machines, because doubles must be 64-bit
3257 aligned. For n32 and n64, stack frames need to be 128-bit
3258 aligned, so we round to this widest known alignment. */
3260 sp
= align_down (sp
, 16);
3261 struct_addr
= align_down (struct_addr
, 16);
3263 /* Now make space on the stack for the args. */
3264 for (argnum
= 0; argnum
< nargs
; argnum
++)
3265 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3266 sp
-= align_up (len
, 16);
3269 fprintf_unfiltered (gdb_stdlog
,
3270 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3271 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3273 /* Initialize the integer and float register pointers. */
3274 argreg
= MIPS_A0_REGNUM
;
3275 float_argreg
= mips_fpa0_regnum (gdbarch
);
3277 /* The struct_return pointer occupies the first parameter-passing reg. */
3281 fprintf_unfiltered (gdb_stdlog
,
3282 "mips_n32n64_push_dummy_call: struct_return reg=%d %s\n",
3283 argreg
, paddress (gdbarch
, struct_addr
));
3284 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3287 /* Now load as many as possible of the first arguments into
3288 registers, and push the rest onto the stack. Loop thru args
3289 from first to last. */
3290 for (argnum
= 0; argnum
< nargs
; argnum
++)
3292 const gdb_byte
*val
;
3293 struct value
*arg
= args
[argnum
];
3294 struct type
*arg_type
= check_typedef (value_type (arg
));
3295 int len
= TYPE_LENGTH (arg_type
);
3296 enum type_code typecode
= TYPE_CODE (arg_type
);
3299 fprintf_unfiltered (gdb_stdlog
,
3300 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3301 argnum
+ 1, len
, (int) typecode
);
3303 val
= value_contents (arg
);
3305 /* A 128-bit long double value requires an even-odd pair of
3306 floating-point registers. */
3308 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3309 && (float_argreg
& 1))
3315 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3316 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3318 /* This is a floating point value that fits entirely
3319 in a single register or a pair of registers. */
3320 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3321 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3323 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3324 float_argreg
, phex (regval
, reglen
));
3325 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3328 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3329 argreg
, phex (regval
, reglen
));
3330 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3335 regval
= extract_unsigned_integer (val
+ reglen
,
3336 reglen
, byte_order
);
3338 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3339 float_argreg
, phex (regval
, reglen
));
3340 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3343 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3344 argreg
, phex (regval
, reglen
));
3345 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3352 /* Copy the argument to general registers or the stack in
3353 register-sized pieces. Large arguments are split between
3354 registers and stack. */
3355 /* For N32/N64, structs, unions, or other composite types are
3356 treated as a sequence of doublewords, and are passed in integer
3357 or floating point registers as though they were simple scalar
3358 parameters to the extent that they fit, with any excess on the
3359 stack packed according to the normal memory layout of the
3361 The caller does not reserve space for the register arguments;
3362 the callee is responsible for reserving it if required. */
3363 /* Note: Floating-point values that didn't fit into an FP
3364 register are only written to memory. */
3367 /* Remember if the argument was written to the stack. */
3368 int stack_used_p
= 0;
3369 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3372 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3375 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3376 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3378 /* Write this portion of the argument to the stack. */
3379 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3381 /* Should shorter than int integer values be
3382 promoted to int before being stored? */
3383 int longword_offset
= 0;
3386 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3388 if ((typecode
== TYPE_CODE_INT
3389 || typecode
== TYPE_CODE_PTR
)
3391 longword_offset
= MIPS64_REGSIZE
- len
;
3396 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3397 paddress (gdbarch
, stack_offset
));
3398 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3399 paddress (gdbarch
, longword_offset
));
3402 addr
= sp
+ stack_offset
+ longword_offset
;
3407 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3408 paddress (gdbarch
, addr
));
3409 for (i
= 0; i
< partial_len
; i
++)
3411 fprintf_unfiltered (gdb_stdlog
, "%02x",
3415 write_memory (addr
, val
, partial_len
);
3418 /* Note!!! This is NOT an else clause. Odd sized
3419 structs may go thru BOTH paths. */
3420 /* Write this portion of the argument to a general
3421 purpose register. */
3422 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3426 /* Sign extend pointers, 32-bit integers and signed
3427 16-bit and 8-bit integers; everything else is taken
3430 if ((partial_len
== 4
3431 && (typecode
== TYPE_CODE_PTR
3432 || typecode
== TYPE_CODE_INT
))
3434 && typecode
== TYPE_CODE_INT
3435 && !TYPE_UNSIGNED (arg_type
)))
3436 regval
= extract_signed_integer (val
, partial_len
,
3439 regval
= extract_unsigned_integer (val
, partial_len
,
3442 /* A non-floating-point argument being passed in a
3443 general register. If a struct or union, and if
3444 the remaining length is smaller than the register
3445 size, we have to adjust the register value on
3448 It does not seem to be necessary to do the
3449 same for integral types. */
3451 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3452 && partial_len
< MIPS64_REGSIZE
3453 && (typecode
== TYPE_CODE_STRUCT
3454 || typecode
== TYPE_CODE_UNION
))
3455 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3459 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3461 phex (regval
, MIPS64_REGSIZE
));
3462 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3464 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3465 TYPE_LENGTH (arg_type
) - len
))
3468 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3470 phex (regval
, MIPS64_REGSIZE
));
3471 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3482 /* Compute the the offset into the stack at which we
3483 will copy the next parameter.
3485 In N32 (N64?), the stack_offset only needs to be
3486 adjusted when it has been used. */
3489 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3493 fprintf_unfiltered (gdb_stdlog
, "\n");
3496 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3498 /* Return adjusted stack pointer. */
3502 static enum return_value_convention
3503 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3504 struct type
*type
, struct regcache
*regcache
,
3505 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3507 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3509 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3511 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3512 if needed), as appropriate for the type. Composite results (struct,
3513 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3516 * A struct with only one or two floating point fields is returned in $f0
3517 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3520 * Any other composite results of at most 128 bits are returned in
3521 $2 (first 64 bits) and $3 (remainder, if necessary).
3523 * Larger composite results are handled by converting the function to a
3524 procedure with an implicit first parameter, which is a pointer to an area
3525 reserved by the caller to receive the result. [The o32-bit ABI requires
3526 that all composite results be handled by conversion to implicit first
3527 parameters. The MIPS/SGI Fortran implementation has always made a
3528 specific exception to return COMPLEX results in the floating point
3531 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3532 return RETURN_VALUE_STRUCT_CONVENTION
;
3533 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3534 && TYPE_LENGTH (type
) == 16
3535 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3537 /* A 128-bit floating-point value fills both $f0 and $f2. The
3538 two registers are used in the same as memory order, so the
3539 eight bytes with the lower memory address are in $f0. */
3541 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3542 mips_xfer_register (gdbarch
, regcache
,
3543 gdbarch_num_regs (gdbarch
)
3544 + mips_regnum (gdbarch
)->fp0
,
3545 8, gdbarch_byte_order (gdbarch
),
3546 readbuf
, writebuf
, 0);
3547 mips_xfer_register (gdbarch
, regcache
,
3548 gdbarch_num_regs (gdbarch
)
3549 + mips_regnum (gdbarch
)->fp0
+ 2,
3550 8, gdbarch_byte_order (gdbarch
),
3551 readbuf
? readbuf
+ 8 : readbuf
,
3552 writebuf
? writebuf
+ 8 : writebuf
, 0);
3553 return RETURN_VALUE_REGISTER_CONVENTION
;
3555 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3556 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3558 /* A single or double floating-point value that fits in FP0. */
3560 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3561 mips_xfer_register (gdbarch
, regcache
,
3562 gdbarch_num_regs (gdbarch
)
3563 + mips_regnum (gdbarch
)->fp0
,
3565 gdbarch_byte_order (gdbarch
),
3566 readbuf
, writebuf
, 0);
3567 return RETURN_VALUE_REGISTER_CONVENTION
;
3569 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3570 && TYPE_NFIELDS (type
) <= 2
3571 && TYPE_NFIELDS (type
) >= 1
3572 && ((TYPE_NFIELDS (type
) == 1
3573 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3575 || (TYPE_NFIELDS (type
) == 2
3576 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3578 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3579 == TYPE_CODE_FLT
))))
3581 /* A struct that contains one or two floats. Each value is part
3582 in the least significant part of their floating point
3583 register (or GPR, for soft float). */
3586 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3587 ? mips_regnum (gdbarch
)->fp0
3589 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3591 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3594 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3596 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3598 /* A 16-byte long double field goes in two consecutive
3600 mips_xfer_register (gdbarch
, regcache
,
3601 gdbarch_num_regs (gdbarch
) + regnum
,
3603 gdbarch_byte_order (gdbarch
),
3604 readbuf
, writebuf
, offset
);
3605 mips_xfer_register (gdbarch
, regcache
,
3606 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3608 gdbarch_byte_order (gdbarch
),
3609 readbuf
, writebuf
, offset
+ 8);
3612 mips_xfer_register (gdbarch
, regcache
,
3613 gdbarch_num_regs (gdbarch
) + regnum
,
3614 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3615 gdbarch_byte_order (gdbarch
),
3616 readbuf
, writebuf
, offset
);
3618 return RETURN_VALUE_REGISTER_CONVENTION
;
3620 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3621 || TYPE_CODE (type
) == TYPE_CODE_UNION
3622 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3624 /* A composite type. Extract the left justified value,
3625 regardless of the byte order. I.e. DO NOT USE
3629 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3630 offset
< TYPE_LENGTH (type
);
3631 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3633 int xfer
= register_size (gdbarch
, regnum
);
3634 if (offset
+ xfer
> TYPE_LENGTH (type
))
3635 xfer
= TYPE_LENGTH (type
) - offset
;
3637 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3638 offset
, xfer
, regnum
);
3639 mips_xfer_register (gdbarch
, regcache
,
3640 gdbarch_num_regs (gdbarch
) + regnum
,
3641 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3644 return RETURN_VALUE_REGISTER_CONVENTION
;
3648 /* A scalar extract each part but least-significant-byte
3652 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3653 offset
< TYPE_LENGTH (type
);
3654 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3656 int xfer
= register_size (gdbarch
, regnum
);
3657 if (offset
+ xfer
> TYPE_LENGTH (type
))
3658 xfer
= TYPE_LENGTH (type
) - offset
;
3660 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3661 offset
, xfer
, regnum
);
3662 mips_xfer_register (gdbarch
, regcache
,
3663 gdbarch_num_regs (gdbarch
) + regnum
,
3664 xfer
, gdbarch_byte_order (gdbarch
),
3665 readbuf
, writebuf
, offset
);
3667 return RETURN_VALUE_REGISTER_CONVENTION
;
3671 /* O32 ABI stuff. */
3674 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3675 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3676 int nargs
, struct value
**args
, CORE_ADDR sp
,
3677 int struct_return
, CORE_ADDR struct_addr
)
3683 int stack_offset
= 0;
3684 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3685 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3686 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3688 /* For shared libraries, "t9" needs to point at the function
3690 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3692 /* Set the return address register to point to the entry point of
3693 the program, where a breakpoint lies in wait. */
3694 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3696 /* First ensure that the stack and structure return address (if any)
3697 are properly aligned. The stack has to be at least 64-bit
3698 aligned even on 32-bit machines, because doubles must be 64-bit
3699 aligned. For n32 and n64, stack frames need to be 128-bit
3700 aligned, so we round to this widest known alignment. */
3702 sp
= align_down (sp
, 16);
3703 struct_addr
= align_down (struct_addr
, 16);
3705 /* Now make space on the stack for the args. */
3706 for (argnum
= 0; argnum
< nargs
; argnum
++)
3708 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3709 int arglen
= TYPE_LENGTH (arg_type
);
3711 /* Align to double-word if necessary. */
3712 if (mips_type_needs_double_align (arg_type
))
3713 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3714 /* Allocate space on the stack. */
3715 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3717 sp
-= align_up (len
, 16);
3720 fprintf_unfiltered (gdb_stdlog
,
3721 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3722 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3724 /* Initialize the integer and float register pointers. */
3725 argreg
= MIPS_A0_REGNUM
;
3726 float_argreg
= mips_fpa0_regnum (gdbarch
);
3728 /* The struct_return pointer occupies the first parameter-passing reg. */
3732 fprintf_unfiltered (gdb_stdlog
,
3733 "mips_o32_push_dummy_call: struct_return reg=%d %s\n",
3734 argreg
, paddress (gdbarch
, struct_addr
));
3735 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3736 stack_offset
+= MIPS32_REGSIZE
;
3739 /* Now load as many as possible of the first arguments into
3740 registers, and push the rest onto the stack. Loop thru args
3741 from first to last. */
3742 for (argnum
= 0; argnum
< nargs
; argnum
++)
3744 const gdb_byte
*val
;
3745 struct value
*arg
= args
[argnum
];
3746 struct type
*arg_type
= check_typedef (value_type (arg
));
3747 int len
= TYPE_LENGTH (arg_type
);
3748 enum type_code typecode
= TYPE_CODE (arg_type
);
3751 fprintf_unfiltered (gdb_stdlog
,
3752 "mips_o32_push_dummy_call: %d len=%d type=%d",
3753 argnum
+ 1, len
, (int) typecode
);
3755 val
= value_contents (arg
);
3757 /* 32-bit ABIs always start floating point arguments in an
3758 even-numbered floating point register. Round the FP register
3759 up before the check to see if there are any FP registers
3760 left. O32/O64 targets also pass the FP in the integer
3761 registers so also round up normal registers. */
3762 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3764 if ((float_argreg
& 1))
3768 /* Floating point arguments passed in registers have to be
3769 treated specially. On 32-bit architectures, doubles
3770 are passed in register pairs; the even register gets
3771 the low word, and the odd register gets the high word.
3772 On O32/O64, the first two floating point arguments are
3773 also copied to general registers, because MIPS16 functions
3774 don't use float registers for arguments. This duplication of
3775 arguments in general registers can't hurt non-MIPS16 functions
3776 because those registers are normally skipped. */
3778 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3779 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3781 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3783 int low_offset
= gdbarch_byte_order (gdbarch
)
3784 == BFD_ENDIAN_BIG
? 4 : 0;
3785 unsigned long regval
;
3787 /* Write the low word of the double to the even register(s). */
3788 regval
= extract_unsigned_integer (val
+ low_offset
,
3791 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3792 float_argreg
, phex (regval
, 4));
3793 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3795 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3796 argreg
, phex (regval
, 4));
3797 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3799 /* Write the high word of the double to the odd register(s). */
3800 regval
= extract_unsigned_integer (val
+ 4 - low_offset
,
3803 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3804 float_argreg
, phex (regval
, 4));
3805 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3808 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3809 argreg
, phex (regval
, 4));
3810 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3814 /* This is a floating point value that fits entirely
3815 in a single register. */
3816 /* On 32 bit ABI's the float_argreg is further adjusted
3817 above to ensure that it is even register aligned. */
3818 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
3820 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3821 float_argreg
, phex (regval
, len
));
3822 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3823 /* Although two FP registers are reserved for each
3824 argument, only one corresponding integer register is
3827 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3828 argreg
, phex (regval
, len
));
3829 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3831 /* Reserve space for the FP register. */
3832 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3836 /* Copy the argument to general registers or the stack in
3837 register-sized pieces. Large arguments are split between
3838 registers and stack. */
3839 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3840 are treated specially: Irix cc passes
3841 them in registers where gcc sometimes puts them on the
3842 stack. For maximum compatibility, we will put them in
3844 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3845 && len
% MIPS32_REGSIZE
!= 0);
3846 /* Structures should be aligned to eight bytes (even arg registers)
3847 on MIPS_ABI_O32, if their first member has double precision. */
3848 if (mips_type_needs_double_align (arg_type
))
3853 stack_offset
+= MIPS32_REGSIZE
;
3858 /* Remember if the argument was written to the stack. */
3859 int stack_used_p
= 0;
3860 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3863 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3866 /* Write this portion of the argument to the stack. */
3867 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3868 || odd_sized_struct
)
3870 /* Should shorter than int integer values be
3871 promoted to int before being stored? */
3872 int longword_offset
= 0;
3878 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3879 paddress (gdbarch
, stack_offset
));
3880 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3881 paddress (gdbarch
, longword_offset
));
3884 addr
= sp
+ stack_offset
+ longword_offset
;
3889 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3890 paddress (gdbarch
, addr
));
3891 for (i
= 0; i
< partial_len
; i
++)
3893 fprintf_unfiltered (gdb_stdlog
, "%02x",
3897 write_memory (addr
, val
, partial_len
);
3900 /* Note!!! This is NOT an else clause. Odd sized
3901 structs may go thru BOTH paths. */
3902 /* Write this portion of the argument to a general
3903 purpose register. */
3904 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3906 LONGEST regval
= extract_signed_integer (val
, partial_len
,
3908 /* Value may need to be sign extended, because
3909 mips_isa_regsize() != mips_abi_regsize(). */
3911 /* A non-floating-point argument being passed in a
3912 general register. If a struct or union, and if
3913 the remaining length is smaller than the register
3914 size, we have to adjust the register value on
3917 It does not seem to be necessary to do the
3918 same for integral types.
3920 Also don't do this adjustment on O64 binaries.
3922 cagney/2001-07-23: gdb/179: Also, GCC, when
3923 outputting LE O32 with sizeof (struct) <
3924 mips_abi_regsize(), generates a left shift
3925 as part of storing the argument in a register
3926 (the left shift isn't generated when
3927 sizeof (struct) >= mips_abi_regsize()). Since
3928 it is quite possible that this is GCC
3929 contradicting the LE/O32 ABI, GDB has not been
3930 adjusted to accommodate this. Either someone
3931 needs to demonstrate that the LE/O32 ABI
3932 specifies such a left shift OR this new ABI gets
3933 identified as such and GDB gets tweaked
3936 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3937 && partial_len
< MIPS32_REGSIZE
3938 && (typecode
== TYPE_CODE_STRUCT
3939 || typecode
== TYPE_CODE_UNION
))
3940 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3944 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3946 phex (regval
, MIPS32_REGSIZE
));
3947 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3950 /* Prevent subsequent floating point arguments from
3951 being passed in floating point registers. */
3952 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
3958 /* Compute the the offset into the stack at which we
3959 will copy the next parameter.
3961 In older ABIs, the caller reserved space for
3962 registers that contained arguments. This was loosely
3963 refered to as their "home". Consequently, space is
3964 always allocated. */
3966 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3970 fprintf_unfiltered (gdb_stdlog
, "\n");
3973 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3975 /* Return adjusted stack pointer. */
3979 static enum return_value_convention
3980 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3981 struct type
*type
, struct regcache
*regcache
,
3982 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3984 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3986 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3987 || TYPE_CODE (type
) == TYPE_CODE_UNION
3988 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3989 return RETURN_VALUE_STRUCT_CONVENTION
;
3990 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3991 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3993 /* A single-precision floating-point value. It fits in the
3994 least significant part of FP0. */
3996 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3997 mips_xfer_register (gdbarch
, regcache
,
3998 gdbarch_num_regs (gdbarch
)
3999 + mips_regnum (gdbarch
)->fp0
,
4001 gdbarch_byte_order (gdbarch
),
4002 readbuf
, writebuf
, 0);
4003 return RETURN_VALUE_REGISTER_CONVENTION
;
4005 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4006 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4008 /* A double-precision floating-point value. The most
4009 significant part goes in FP1, and the least significant in
4012 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4013 switch (gdbarch_byte_order (gdbarch
))
4015 case BFD_ENDIAN_LITTLE
:
4016 mips_xfer_register (gdbarch
, regcache
,
4017 gdbarch_num_regs (gdbarch
)
4018 + mips_regnum (gdbarch
)->fp0
+
4019 0, 4, gdbarch_byte_order (gdbarch
),
4020 readbuf
, writebuf
, 0);
4021 mips_xfer_register (gdbarch
, regcache
,
4022 gdbarch_num_regs (gdbarch
)
4023 + mips_regnum (gdbarch
)->fp0
+ 1,
4024 4, gdbarch_byte_order (gdbarch
),
4025 readbuf
, writebuf
, 4);
4027 case BFD_ENDIAN_BIG
:
4028 mips_xfer_register (gdbarch
, regcache
,
4029 gdbarch_num_regs (gdbarch
)
4030 + mips_regnum (gdbarch
)->fp0
+ 1,
4031 4, gdbarch_byte_order (gdbarch
),
4032 readbuf
, writebuf
, 0);
4033 mips_xfer_register (gdbarch
, regcache
,
4034 gdbarch_num_regs (gdbarch
)
4035 + mips_regnum (gdbarch
)->fp0
+ 0,
4036 4, gdbarch_byte_order (gdbarch
),
4037 readbuf
, writebuf
, 4);
4040 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4042 return RETURN_VALUE_REGISTER_CONVENTION
;
4045 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4046 && TYPE_NFIELDS (type
) <= 2
4047 && TYPE_NFIELDS (type
) >= 1
4048 && ((TYPE_NFIELDS (type
) == 1
4049 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4051 || (TYPE_NFIELDS (type
) == 2
4052 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4054 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4056 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4058 /* A struct that contains one or two floats. Each value is part
4059 in the least significant part of their floating point
4061 gdb_byte reg
[MAX_REGISTER_SIZE
];
4064 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4065 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4067 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4070 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4072 mips_xfer_register (gdbarch
, regcache
,
4073 gdbarch_num_regs (gdbarch
) + regnum
,
4074 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4075 gdbarch_byte_order (gdbarch
),
4076 readbuf
, writebuf
, offset
);
4078 return RETURN_VALUE_REGISTER_CONVENTION
;
4082 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4083 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4085 /* A structure or union. Extract the left justified value,
4086 regardless of the byte order. I.e. DO NOT USE
4090 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4091 offset
< TYPE_LENGTH (type
);
4092 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4094 int xfer
= register_size (gdbarch
, regnum
);
4095 if (offset
+ xfer
> TYPE_LENGTH (type
))
4096 xfer
= TYPE_LENGTH (type
) - offset
;
4098 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4099 offset
, xfer
, regnum
);
4100 mips_xfer_register (gdbarch
, regcache
,
4101 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4102 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4104 return RETURN_VALUE_REGISTER_CONVENTION
;
4109 /* A scalar extract each part but least-significant-byte
4110 justified. o32 thinks registers are 4 byte, regardless of
4114 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4115 offset
< TYPE_LENGTH (type
);
4116 offset
+= MIPS32_REGSIZE
, regnum
++)
4118 int xfer
= MIPS32_REGSIZE
;
4119 if (offset
+ xfer
> TYPE_LENGTH (type
))
4120 xfer
= TYPE_LENGTH (type
) - offset
;
4122 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4123 offset
, xfer
, regnum
);
4124 mips_xfer_register (gdbarch
, regcache
,
4125 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4126 gdbarch_byte_order (gdbarch
),
4127 readbuf
, writebuf
, offset
);
4129 return RETURN_VALUE_REGISTER_CONVENTION
;
4133 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4137 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4138 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4140 struct value
**args
, CORE_ADDR sp
,
4141 int struct_return
, CORE_ADDR struct_addr
)
4147 int stack_offset
= 0;
4148 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4149 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4150 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4152 /* For shared libraries, "t9" needs to point at the function
4154 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4156 /* Set the return address register to point to the entry point of
4157 the program, where a breakpoint lies in wait. */
4158 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4160 /* First ensure that the stack and structure return address (if any)
4161 are properly aligned. The stack has to be at least 64-bit
4162 aligned even on 32-bit machines, because doubles must be 64-bit
4163 aligned. For n32 and n64, stack frames need to be 128-bit
4164 aligned, so we round to this widest known alignment. */
4166 sp
= align_down (sp
, 16);
4167 struct_addr
= align_down (struct_addr
, 16);
4169 /* Now make space on the stack for the args. */
4170 for (argnum
= 0; argnum
< nargs
; argnum
++)
4172 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4173 int arglen
= TYPE_LENGTH (arg_type
);
4175 /* Allocate space on the stack. */
4176 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4178 sp
-= align_up (len
, 16);
4181 fprintf_unfiltered (gdb_stdlog
,
4182 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4183 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4185 /* Initialize the integer and float register pointers. */
4186 argreg
= MIPS_A0_REGNUM
;
4187 float_argreg
= mips_fpa0_regnum (gdbarch
);
4189 /* The struct_return pointer occupies the first parameter-passing reg. */
4193 fprintf_unfiltered (gdb_stdlog
,
4194 "mips_o64_push_dummy_call: struct_return reg=%d %s\n",
4195 argreg
, paddress (gdbarch
, struct_addr
));
4196 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4197 stack_offset
+= MIPS64_REGSIZE
;
4200 /* Now load as many as possible of the first arguments into
4201 registers, and push the rest onto the stack. Loop thru args
4202 from first to last. */
4203 for (argnum
= 0; argnum
< nargs
; argnum
++)
4205 const gdb_byte
*val
;
4206 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4207 struct value
*arg
= args
[argnum
];
4208 struct type
*arg_type
= check_typedef (value_type (arg
));
4209 int len
= TYPE_LENGTH (arg_type
);
4210 enum type_code typecode
= TYPE_CODE (arg_type
);
4213 fprintf_unfiltered (gdb_stdlog
,
4214 "mips_o64_push_dummy_call: %d len=%d type=%d",
4215 argnum
+ 1, len
, (int) typecode
);
4217 val
= value_contents (arg
);
4219 /* Function pointer arguments to mips16 code need to be made into
4221 if (typecode
== TYPE_CODE_PTR
4222 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4224 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4226 if (mips_pc_is_mips16 (addr
))
4228 store_signed_integer (valbuf
, len
, byte_order
,
4229 make_mips16_addr (addr
));
4234 /* Floating point arguments passed in registers have to be
4235 treated specially. On 32-bit architectures, doubles
4236 are passed in register pairs; the even register gets
4237 the low word, and the odd register gets the high word.
4238 On O32/O64, the first two floating point arguments are
4239 also copied to general registers, because MIPS16 functions
4240 don't use float registers for arguments. This duplication of
4241 arguments in general registers can't hurt non-MIPS16 functions
4242 because those registers are normally skipped. */
4244 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4245 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4247 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4249 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4250 float_argreg
, phex (regval
, len
));
4251 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4253 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4254 argreg
, phex (regval
, len
));
4255 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4257 /* Reserve space for the FP register. */
4258 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4262 /* Copy the argument to general registers or the stack in
4263 register-sized pieces. Large arguments are split between
4264 registers and stack. */
4265 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4266 are treated specially: Irix cc passes them in registers
4267 where gcc sometimes puts them on the stack. For maximum
4268 compatibility, we will put them in both places. */
4269 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4270 && len
% MIPS64_REGSIZE
!= 0);
4273 /* Remember if the argument was written to the stack. */
4274 int stack_used_p
= 0;
4275 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4278 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4281 /* Write this portion of the argument to the stack. */
4282 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4283 || odd_sized_struct
)
4285 /* Should shorter than int integer values be
4286 promoted to int before being stored? */
4287 int longword_offset
= 0;
4290 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4292 if ((typecode
== TYPE_CODE_INT
4293 || typecode
== TYPE_CODE_PTR
4294 || typecode
== TYPE_CODE_FLT
)
4296 longword_offset
= MIPS64_REGSIZE
- len
;
4301 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4302 paddress (gdbarch
, stack_offset
));
4303 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4304 paddress (gdbarch
, longword_offset
));
4307 addr
= sp
+ stack_offset
+ longword_offset
;
4312 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4313 paddress (gdbarch
, addr
));
4314 for (i
= 0; i
< partial_len
; i
++)
4316 fprintf_unfiltered (gdb_stdlog
, "%02x",
4320 write_memory (addr
, val
, partial_len
);
4323 /* Note!!! This is NOT an else clause. Odd sized
4324 structs may go thru BOTH paths. */
4325 /* Write this portion of the argument to a general
4326 purpose register. */
4327 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4329 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4331 /* Value may need to be sign extended, because
4332 mips_isa_regsize() != mips_abi_regsize(). */
4334 /* A non-floating-point argument being passed in a
4335 general register. If a struct or union, and if
4336 the remaining length is smaller than the register
4337 size, we have to adjust the register value on
4340 It does not seem to be necessary to do the
4341 same for integral types. */
4343 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4344 && partial_len
< MIPS64_REGSIZE
4345 && (typecode
== TYPE_CODE_STRUCT
4346 || typecode
== TYPE_CODE_UNION
))
4347 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4351 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4353 phex (regval
, MIPS64_REGSIZE
));
4354 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4357 /* Prevent subsequent floating point arguments from
4358 being passed in floating point registers. */
4359 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4365 /* Compute the the offset into the stack at which we
4366 will copy the next parameter.
4368 In older ABIs, the caller reserved space for
4369 registers that contained arguments. This was loosely
4370 refered to as their "home". Consequently, space is
4371 always allocated. */
4373 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4377 fprintf_unfiltered (gdb_stdlog
, "\n");
4380 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4382 /* Return adjusted stack pointer. */
4386 static enum return_value_convention
4387 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4388 struct type
*type
, struct regcache
*regcache
,
4389 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4391 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4393 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4394 || TYPE_CODE (type
) == TYPE_CODE_UNION
4395 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4396 return RETURN_VALUE_STRUCT_CONVENTION
;
4397 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4399 /* A floating-point value. It fits in the least significant
4402 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4403 mips_xfer_register (gdbarch
, regcache
,
4404 gdbarch_num_regs (gdbarch
)
4405 + mips_regnum (gdbarch
)->fp0
,
4407 gdbarch_byte_order (gdbarch
),
4408 readbuf
, writebuf
, 0);
4409 return RETURN_VALUE_REGISTER_CONVENTION
;
4413 /* A scalar extract each part but least-significant-byte
4417 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4418 offset
< TYPE_LENGTH (type
);
4419 offset
+= MIPS64_REGSIZE
, regnum
++)
4421 int xfer
= MIPS64_REGSIZE
;
4422 if (offset
+ xfer
> TYPE_LENGTH (type
))
4423 xfer
= TYPE_LENGTH (type
) - offset
;
4425 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4426 offset
, xfer
, regnum
);
4427 mips_xfer_register (gdbarch
, regcache
,
4428 gdbarch_num_regs (gdbarch
) + regnum
,
4429 xfer
, gdbarch_byte_order (gdbarch
),
4430 readbuf
, writebuf
, offset
);
4432 return RETURN_VALUE_REGISTER_CONVENTION
;
4436 /* Floating point register management.
4438 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4439 64bit operations, these early MIPS cpus treat fp register pairs
4440 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4441 registers and offer a compatibility mode that emulates the MIPS2 fp
4442 model. When operating in MIPS2 fp compat mode, later cpu's split
4443 double precision floats into two 32-bit chunks and store them in
4444 consecutive fp regs. To display 64-bit floats stored in this
4445 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4446 Throw in user-configurable endianness and you have a real mess.
4448 The way this works is:
4449 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4450 double-precision value will be split across two logical registers.
4451 The lower-numbered logical register will hold the low-order bits,
4452 regardless of the processor's endianness.
4453 - If we are on a 64-bit processor, and we are looking for a
4454 single-precision value, it will be in the low ordered bits
4455 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4456 save slot in memory.
4457 - If we are in 64-bit mode, everything is straightforward.
4459 Note that this code only deals with "live" registers at the top of the
4460 stack. We will attempt to deal with saved registers later, when
4461 the raw/cooked register interface is in place. (We need a general
4462 interface that can deal with dynamic saved register sizes -- fp
4463 regs could be 32 bits wide in one frame and 64 on the frame above
4466 /* Copy a 32-bit single-precision value from the current frame
4467 into rare_buffer. */
4470 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4471 gdb_byte
*rare_buffer
)
4473 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4474 int raw_size
= register_size (gdbarch
, regno
);
4475 gdb_byte
*raw_buffer
= alloca (raw_size
);
4477 if (!frame_register_read (frame
, regno
, raw_buffer
))
4478 error (_("can't read register %d (%s)"),
4479 regno
, gdbarch_register_name (gdbarch
, regno
));
4482 /* We have a 64-bit value for this register. Find the low-order
4486 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4491 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4495 memcpy (rare_buffer
, raw_buffer
, 4);
4499 /* Copy a 64-bit double-precision value from the current frame into
4500 rare_buffer. This may include getting half of it from the next
4504 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4505 gdb_byte
*rare_buffer
)
4507 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4508 int raw_size
= register_size (gdbarch
, regno
);
4510 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4512 /* We have a 64-bit value for this register, and we should use
4514 if (!frame_register_read (frame
, regno
, rare_buffer
))
4515 error (_("can't read register %d (%s)"),
4516 regno
, gdbarch_register_name (gdbarch
, regno
));
4520 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4522 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4523 internal_error (__FILE__
, __LINE__
,
4524 _("mips_read_fp_register_double: bad access to "
4525 "odd-numbered FP register"));
4527 /* mips_read_fp_register_single will find the correct 32 bits from
4529 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4531 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4532 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4536 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4537 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4543 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4545 { /* do values for FP (float) regs */
4546 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4547 gdb_byte
*raw_buffer
;
4548 double doub
, flt1
; /* doubles extracted from raw hex data */
4551 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4553 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4554 fprintf_filtered (file
, "%*s",
4555 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4558 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4560 struct value_print_options opts
;
4562 /* 4-byte registers: Print hex and floating. Also print even
4563 numbered registers as doubles. */
4564 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4565 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
, raw_buffer
, &inv1
);
4567 get_formatted_print_options (&opts
, 'x');
4568 print_scalar_formatted (raw_buffer
,
4569 builtin_type (gdbarch
)->builtin_uint32
,
4572 fprintf_filtered (file
, " flt: ");
4574 fprintf_filtered (file
, " <invalid float> ");
4576 fprintf_filtered (file
, "%-17.9g", flt1
);
4578 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4580 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4581 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4584 fprintf_filtered (file
, " dbl: ");
4586 fprintf_filtered (file
, "<invalid double>");
4588 fprintf_filtered (file
, "%-24.17g", doub
);
4593 struct value_print_options opts
;
4595 /* Eight byte registers: print each one as hex, float and double. */
4596 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4597 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4600 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4601 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4604 get_formatted_print_options (&opts
, 'x');
4605 print_scalar_formatted (raw_buffer
,
4606 builtin_type (gdbarch
)->builtin_uint64
,
4609 fprintf_filtered (file
, " flt: ");
4611 fprintf_filtered (file
, "<invalid float>");
4613 fprintf_filtered (file
, "%-17.9g", flt1
);
4615 fprintf_filtered (file
, " dbl: ");
4617 fprintf_filtered (file
, "<invalid double>");
4619 fprintf_filtered (file
, "%-24.17g", doub
);
4624 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4627 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4628 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4630 struct value_print_options opts
;
4632 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4634 mips_print_fp_register (file
, frame
, regnum
);
4638 /* Get the data in raw format. */
4639 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4641 fprintf_filtered (file
, "%s: [Invalid]",
4642 gdbarch_register_name (gdbarch
, regnum
));
4646 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4648 /* The problem with printing numeric register names (r26, etc.) is that
4649 the user can't use them on input. Probably the best solution is to
4650 fix it so that either the numeric or the funky (a2, etc.) names
4651 are accepted on input. */
4652 if (regnum
< MIPS_NUMREGS
)
4653 fprintf_filtered (file
, "(r%d): ", regnum
);
4655 fprintf_filtered (file
, ": ");
4657 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4659 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4663 get_formatted_print_options (&opts
, 'x');
4664 print_scalar_formatted (raw_buffer
+ offset
,
4665 register_type (gdbarch
, regnum
), &opts
, 0,
4669 /* Replacement for generic do_registers_info.
4670 Print regs in pretty columns. */
4673 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4676 fprintf_filtered (file
, " ");
4677 mips_print_fp_register (file
, frame
, regnum
);
4678 fprintf_filtered (file
, "\n");
4683 /* Print a row's worth of GP (int) registers, with name labels above */
4686 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4689 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4690 /* do values for GP (int) regs */
4691 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4692 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4696 /* For GP registers, we print a separate row of names above the vals */
4697 for (col
= 0, regnum
= start_regnum
;
4698 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4699 + gdbarch_num_pseudo_regs (gdbarch
);
4702 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4703 continue; /* unused register */
4704 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4706 break; /* end the row: reached FP register */
4707 /* Large registers are handled separately. */
4708 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4711 break; /* End the row before this register. */
4713 /* Print this register on a row by itself. */
4714 mips_print_register (file
, frame
, regnum
);
4715 fprintf_filtered (file
, "\n");
4719 fprintf_filtered (file
, " ");
4720 fprintf_filtered (file
,
4721 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4722 gdbarch_register_name (gdbarch
, regnum
));
4729 /* print the R0 to R31 names */
4730 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4731 fprintf_filtered (file
, "\n R%-4d",
4732 start_regnum
% gdbarch_num_regs (gdbarch
));
4734 fprintf_filtered (file
, "\n ");
4736 /* now print the values in hex, 4 or 8 to the row */
4737 for (col
= 0, regnum
= start_regnum
;
4738 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4739 + gdbarch_num_pseudo_regs (gdbarch
);
4742 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4743 continue; /* unused register */
4744 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4746 break; /* end row: reached FP register */
4747 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4748 break; /* End row: large register. */
4750 /* OK: get the data in raw format. */
4751 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4752 error (_("can't read register %d (%s)"),
4753 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4754 /* pad small registers */
4756 byte
< (mips_abi_regsize (gdbarch
)
4757 - register_size (gdbarch
, regnum
)); byte
++)
4758 printf_filtered (" ");
4759 /* Now print the register value in hex, endian order. */
4760 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4762 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4763 byte
< register_size (gdbarch
, regnum
); byte
++)
4764 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4766 for (byte
= register_size (gdbarch
, regnum
) - 1;
4768 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4769 fprintf_filtered (file
, " ");
4772 if (col
> 0) /* ie. if we actually printed anything... */
4773 fprintf_filtered (file
, "\n");
4778 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4781 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4782 struct frame_info
*frame
, int regnum
, int all
)
4784 if (regnum
!= -1) /* do one specified register */
4786 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4787 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4788 error (_("Not a valid register for the current processor type"));
4790 mips_print_register (file
, frame
, regnum
);
4791 fprintf_filtered (file
, "\n");
4794 /* do all (or most) registers */
4796 regnum
= gdbarch_num_regs (gdbarch
);
4797 while (regnum
< gdbarch_num_regs (gdbarch
)
4798 + gdbarch_num_pseudo_regs (gdbarch
))
4800 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4803 if (all
) /* true for "INFO ALL-REGISTERS" command */
4804 regnum
= print_fp_register_row (file
, frame
, regnum
);
4806 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4809 regnum
= print_gp_register_row (file
, frame
, regnum
);
4814 /* Is this a branch with a delay slot? */
4817 is_delayed (unsigned long insn
)
4820 for (i
= 0; i
< NUMOPCODES
; ++i
)
4821 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4822 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4824 return (i
< NUMOPCODES
4825 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4826 | INSN_COND_BRANCH_DELAY
4827 | INSN_COND_BRANCH_LIKELY
)));
4831 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4832 struct frame_info
*frame
)
4834 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4835 CORE_ADDR pc
= get_frame_pc (frame
);
4836 gdb_byte buf
[MIPS_INSN32_SIZE
];
4838 /* There is no branch delay slot on MIPS16. */
4839 if (mips_pc_is_mips16 (pc
))
4842 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
4845 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4846 /* If error reading memory, guess that it is not a delayed
4849 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
4852 /* To skip prologues, I use this predicate. Returns either PC itself
4853 if the code at PC does not look like a function prologue; otherwise
4854 returns an address that (if we're lucky) follows the prologue. If
4855 LENIENT, then we must skip everything which is involved in setting
4856 up the frame (it's OK to skip more, just so long as we don't skip
4857 anything which might clobber the registers which are being saved.
4858 We must skip more in the case where part of the prologue is in the
4859 delay slot of a non-prologue instruction). */
4862 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4865 CORE_ADDR func_addr
;
4867 /* See if we can determine the end of the prologue via the symbol table.
4868 If so, then return either PC, or the PC after the prologue, whichever
4870 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4872 CORE_ADDR post_prologue_pc
4873 = skip_prologue_using_sal (gdbarch
, func_addr
);
4874 if (post_prologue_pc
!= 0)
4875 return max (pc
, post_prologue_pc
);
4878 /* Can't determine prologue from the symbol table, need to examine
4881 /* Find an upper limit on the function prologue using the debug
4882 information. If the debug information could not be used to provide
4883 that bound, then use an arbitrary large number as the upper bound. */
4884 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
4886 limit_pc
= pc
+ 100; /* Magic. */
4888 if (mips_pc_is_mips16 (pc
))
4889 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4891 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
4894 /* Check whether the PC is in a function epilogue (32-bit version).
4895 This is a helper function for mips_in_function_epilogue_p. */
4897 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4899 CORE_ADDR func_addr
= 0, func_end
= 0;
4901 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4903 /* The MIPS epilogue is max. 12 bytes long. */
4904 CORE_ADDR addr
= func_end
- 12;
4906 if (addr
< func_addr
+ 4)
4907 addr
= func_addr
+ 4;
4911 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4913 unsigned long high_word
;
4916 inst
= mips_fetch_instruction (gdbarch
, pc
);
4917 high_word
= (inst
>> 16) & 0xffff;
4919 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4920 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4921 && inst
!= 0x03e00008 /* jr $ra */
4922 && inst
!= 0x00000000) /* nop */
4932 /* Check whether the PC is in a function epilogue (16-bit version).
4933 This is a helper function for mips_in_function_epilogue_p. */
4935 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4937 CORE_ADDR func_addr
= 0, func_end
= 0;
4939 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4941 /* The MIPS epilogue is max. 12 bytes long. */
4942 CORE_ADDR addr
= func_end
- 12;
4944 if (addr
< func_addr
+ 4)
4945 addr
= func_addr
+ 4;
4949 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4951 unsigned short inst
;
4953 inst
= mips_fetch_instruction (gdbarch
, pc
);
4955 if ((inst
& 0xf800) == 0xf000) /* extend */
4958 if (inst
!= 0x6300 /* addiu $sp,offset */
4959 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4960 && inst
!= 0xe820 /* jr $ra */
4961 && inst
!= 0xe8a0 /* jrc $ra */
4962 && inst
!= 0x6500) /* nop */
4972 /* The epilogue is defined here as the area at the end of a function,
4973 after an instruction which destroys the function's stack frame. */
4975 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4977 if (mips_pc_is_mips16 (pc
))
4978 return mips16_in_function_epilogue_p (gdbarch
, pc
);
4980 return mips32_in_function_epilogue_p (gdbarch
, pc
);
4983 /* Root of all "set mips "/"show mips " commands. This will eventually be
4984 used for all MIPS-specific commands. */
4987 show_mips_command (char *args
, int from_tty
)
4989 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4993 set_mips_command (char *args
, int from_tty
)
4996 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4997 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5000 /* Commands to show/set the MIPS FPU type. */
5003 show_mipsfpu_command (char *args
, int from_tty
)
5007 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5010 ("The MIPS floating-point coprocessor is unknown "
5011 "because the current architecture is not MIPS.\n");
5015 switch (MIPS_FPU_TYPE (target_gdbarch
))
5017 case MIPS_FPU_SINGLE
:
5018 fpu
= "single-precision";
5020 case MIPS_FPU_DOUBLE
:
5021 fpu
= "double-precision";
5024 fpu
= "absent (none)";
5027 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5029 if (mips_fpu_type_auto
)
5031 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
5035 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5040 set_mipsfpu_command (char *args
, int from_tty
)
5043 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
5044 show_mipsfpu_command (args
, from_tty
);
5048 set_mipsfpu_single_command (char *args
, int from_tty
)
5050 struct gdbarch_info info
;
5051 gdbarch_info_init (&info
);
5052 mips_fpu_type
= MIPS_FPU_SINGLE
;
5053 mips_fpu_type_auto
= 0;
5054 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5055 instead of relying on globals. Doing that would let generic code
5056 handle the search for this specific architecture. */
5057 if (!gdbarch_update_p (info
))
5058 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5062 set_mipsfpu_double_command (char *args
, int from_tty
)
5064 struct gdbarch_info info
;
5065 gdbarch_info_init (&info
);
5066 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5067 mips_fpu_type_auto
= 0;
5068 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5069 instead of relying on globals. Doing that would let generic code
5070 handle the search for this specific architecture. */
5071 if (!gdbarch_update_p (info
))
5072 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5076 set_mipsfpu_none_command (char *args
, int from_tty
)
5078 struct gdbarch_info info
;
5079 gdbarch_info_init (&info
);
5080 mips_fpu_type
= MIPS_FPU_NONE
;
5081 mips_fpu_type_auto
= 0;
5082 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5083 instead of relying on globals. Doing that would let generic code
5084 handle the search for this specific architecture. */
5085 if (!gdbarch_update_p (info
))
5086 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5090 set_mipsfpu_auto_command (char *args
, int from_tty
)
5092 mips_fpu_type_auto
= 1;
5095 /* Attempt to identify the particular processor model by reading the
5096 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5097 the relevant processor still exists (it dates back to '94) and
5098 secondly this is not the way to do this. The processor type should
5099 be set by forcing an architecture change. */
5102 deprecated_mips_set_processor_regs_hack (void)
5104 struct regcache
*regcache
= get_current_regcache ();
5105 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5106 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5109 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5110 if ((prid
& ~0xf) == 0x700)
5111 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5114 /* Just like reinit_frame_cache, but with the right arguments to be
5115 callable as an sfunc. */
5118 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5119 struct cmd_list_element
*c
)
5121 reinit_frame_cache ();
5125 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5127 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5128 disassembler needs to be able to locally determine the ISA, and
5129 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5131 if (mips_pc_is_mips16 (memaddr
))
5132 info
->mach
= bfd_mach_mips16
;
5134 /* Round down the instruction address to the appropriate boundary. */
5135 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5137 /* Set the disassembler options. */
5138 if (!info
->disassembler_options
)
5139 /* This string is not recognized explicitly by the disassembler,
5140 but it tells the disassembler to not try to guess the ABI from
5141 the bfd elf headers, such that, if the user overrides the ABI
5142 of a program linked as NewABI, the disassembly will follow the
5143 register naming conventions specified by the user. */
5144 info
->disassembler_options
= "gpr-names=32";
5146 /* Call the appropriate disassembler based on the target endian-ness. */
5147 if (info
->endian
== BFD_ENDIAN_BIG
)
5148 return print_insn_big_mips (memaddr
, info
);
5150 return print_insn_little_mips (memaddr
, info
);
5154 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5156 /* Set up the disassembler info, so that we get the right
5157 register names from libopcodes. */
5158 info
->disassembler_options
= "gpr-names=n32";
5159 info
->flavour
= bfd_target_elf_flavour
;
5161 return gdb_print_insn_mips (memaddr
, info
);
5165 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5167 /* Set up the disassembler info, so that we get the right
5168 register names from libopcodes. */
5169 info
->disassembler_options
= "gpr-names=64";
5170 info
->flavour
= bfd_target_elf_flavour
;
5172 return gdb_print_insn_mips (memaddr
, info
);
5175 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
5176 counter value to determine whether a 16- or 32-bit breakpoint should be used.
5177 It returns a pointer to a string of bytes that encode a breakpoint
5178 instruction, stores the length of the string to *lenptr, and adjusts pc (if
5179 necessary) to point to the actual memory location where the breakpoint
5180 should be inserted. */
5182 static const gdb_byte
*
5183 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
5185 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5187 if (mips_pc_is_mips16 (*pcptr
))
5189 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5190 *pcptr
= unmake_mips16_addr (*pcptr
);
5191 *lenptr
= sizeof (mips16_big_breakpoint
);
5192 return mips16_big_breakpoint
;
5196 /* The IDT board uses an unusual breakpoint value, and
5197 sometimes gets confused when it sees the usual MIPS
5198 breakpoint instruction. */
5199 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5200 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5201 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5202 /* Likewise, IRIX appears to expect a different breakpoint,
5203 although this is not apparent until you try to use pthreads. */
5204 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5206 *lenptr
= sizeof (big_breakpoint
);
5208 if (strcmp (target_shortname
, "mips") == 0)
5209 return idt_big_breakpoint
;
5210 else if (strcmp (target_shortname
, "ddb") == 0
5211 || strcmp (target_shortname
, "pmon") == 0
5212 || strcmp (target_shortname
, "lsi") == 0)
5213 return pmon_big_breakpoint
;
5214 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5215 return irix_big_breakpoint
;
5217 return big_breakpoint
;
5222 if (mips_pc_is_mips16 (*pcptr
))
5224 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5225 *pcptr
= unmake_mips16_addr (*pcptr
);
5226 *lenptr
= sizeof (mips16_little_breakpoint
);
5227 return mips16_little_breakpoint
;
5231 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5232 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5233 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5235 *lenptr
= sizeof (little_breakpoint
);
5237 if (strcmp (target_shortname
, "mips") == 0)
5238 return idt_little_breakpoint
;
5239 else if (strcmp (target_shortname
, "ddb") == 0
5240 || strcmp (target_shortname
, "pmon") == 0
5241 || strcmp (target_shortname
, "lsi") == 0)
5242 return pmon_little_breakpoint
;
5244 return little_breakpoint
;
5249 /* If PC is in a mips16 call or return stub, return the address of the target
5250 PC, which is either the callee or the caller. There are several
5251 cases which must be handled:
5253 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5254 target PC is in $31 ($ra).
5255 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5256 and the target PC is in $2.
5257 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5258 before the jal instruction, this is effectively a call stub
5259 and the the target PC is in $2. Otherwise this is effectively
5260 a return stub and the target PC is in $18.
5262 See the source code for the stubs in gcc/config/mips/mips16.S for
5266 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5268 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5270 CORE_ADDR start_addr
;
5272 /* Find the starting address and name of the function containing the PC. */
5273 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5276 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5277 target PC is in $31 ($ra). */
5278 if (strcmp (name
, "__mips16_ret_sf") == 0
5279 || strcmp (name
, "__mips16_ret_df") == 0)
5280 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5282 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5284 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5285 and the target PC is in $2. */
5286 if (name
[19] >= '0' && name
[19] <= '9')
5287 return get_frame_register_signed (frame
, 2);
5289 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5290 before the jal instruction, this is effectively a call stub
5291 and the the target PC is in $2. Otherwise this is effectively
5292 a return stub and the target PC is in $18. */
5293 else if (name
[19] == 's' || name
[19] == 'd')
5295 if (pc
== start_addr
)
5297 /* Check if the target of the stub is a compiler-generated
5298 stub. Such a stub for a function bar might have a name
5299 like __fn_stub_bar, and might look like this:
5304 la $1,bar (becomes a lui/addiu pair)
5306 So scan down to the lui/addi and extract the target
5307 address from those two instructions. */
5309 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5313 /* See if the name of the target function is __fn_stub_*. */
5314 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5317 if (strncmp (name
, "__fn_stub_", 10) != 0
5318 && strcmp (name
, "etext") != 0
5319 && strcmp (name
, "_etext") != 0)
5322 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5323 The limit on the search is arbitrarily set to 20
5324 instructions. FIXME. */
5325 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5327 inst
= mips_fetch_instruction (gdbarch
, target_pc
);
5328 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5329 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5330 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5331 return pc
| (inst
& 0xffff); /* low word */
5334 /* Couldn't find the lui/addui pair, so return stub address. */
5338 /* This is the 'return' part of a call stub. The return
5339 address is in $r18. */
5340 return get_frame_register_signed (frame
, 18);
5343 return 0; /* not a stub */
5346 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
5347 PC of the stub target. The stub just loads $t9 and jumps to it,
5348 so that $t9 has the correct value at function entry. */
5351 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5353 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5354 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5355 struct minimal_symbol
*msym
;
5357 gdb_byte stub_code
[16];
5358 int32_t stub_words
[4];
5360 /* The stub for foo is named ".pic.foo", and is either two
5361 instructions inserted before foo or a three instruction sequence
5362 which jumps to foo. */
5363 msym
= lookup_minimal_symbol_by_pc (pc
);
5365 || SYMBOL_VALUE_ADDRESS (msym
) != pc
5366 || SYMBOL_LINKAGE_NAME (msym
) == NULL
5367 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
5370 /* A two-instruction header. */
5371 if (MSYMBOL_SIZE (msym
) == 8)
5374 /* A three-instruction (plus delay slot) trampoline. */
5375 if (MSYMBOL_SIZE (msym
) == 16)
5377 if (target_read_memory (pc
, stub_code
, 16) != 0)
5379 for (i
= 0; i
< 4; i
++)
5380 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
5383 /* A stub contains these instructions:
5386 addiu t9, t9, %lo(target)
5389 This works even for N64, since stubs are only generated with
5391 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
5392 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
5393 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
5394 && stub_words
[3] == 0x00000000)
5395 return (((stub_words
[0] & 0x0000ffff) << 16)
5396 + (stub_words
[2] & 0x0000ffff));
5399 /* Not a recognized stub. */
5404 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5406 CORE_ADDR target_pc
;
5408 target_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
5412 target_pc
= find_solib_trampoline_target (frame
, pc
);
5416 target_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
5423 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5424 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5427 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5430 if (num
>= 0 && num
< 32)
5432 else if (num
>= 38 && num
< 70)
5433 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5435 regnum
= mips_regnum (gdbarch
)->hi
;
5437 regnum
= mips_regnum (gdbarch
)->lo
;
5439 /* This will hopefully (eventually) provoke a warning. Should
5440 we be calling complaint() here? */
5441 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5442 return gdbarch_num_regs (gdbarch
) + regnum
;
5446 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5447 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5450 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5453 if (num
>= 0 && num
< 32)
5455 else if (num
>= 32 && num
< 64)
5456 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5458 regnum
= mips_regnum (gdbarch
)->hi
;
5460 regnum
= mips_regnum (gdbarch
)->lo
;
5462 /* This will hopefully (eventually) provoke a warning. Should we
5463 be calling complaint() here? */
5464 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5465 return gdbarch_num_regs (gdbarch
) + regnum
;
5469 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5471 /* Only makes sense to supply raw registers. */
5472 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5473 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5474 decide if it is valid. Should instead define a standard sim/gdb
5475 register numbering scheme. */
5476 if (gdbarch_register_name (gdbarch
,
5477 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5478 && gdbarch_register_name (gdbarch
,
5479 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5482 return LEGACY_SIM_REGNO_IGNORE
;
5486 /* Convert an integer into an address. Extracting the value signed
5487 guarantees a correctly sign extended address. */
5490 mips_integer_to_address (struct gdbarch
*gdbarch
,
5491 struct type
*type
, const gdb_byte
*buf
)
5493 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5494 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
5497 /* Dummy virtual frame pointer method. This is no more or less accurate
5498 than most other architectures; we just need to be explicit about it,
5499 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5500 an assertion failure. */
5503 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5504 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5506 *reg
= MIPS_SP_REGNUM
;
5511 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5513 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5514 const char *name
= bfd_get_section_name (abfd
, sect
);
5516 if (*abip
!= MIPS_ABI_UNKNOWN
)
5519 if (strncmp (name
, ".mdebug.", 8) != 0)
5522 if (strcmp (name
, ".mdebug.abi32") == 0)
5523 *abip
= MIPS_ABI_O32
;
5524 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5525 *abip
= MIPS_ABI_N32
;
5526 else if (strcmp (name
, ".mdebug.abi64") == 0)
5527 *abip
= MIPS_ABI_N64
;
5528 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5529 *abip
= MIPS_ABI_O64
;
5530 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5531 *abip
= MIPS_ABI_EABI32
;
5532 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5533 *abip
= MIPS_ABI_EABI64
;
5535 warning (_("unsupported ABI %s."), name
+ 8);
5539 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5541 int *lbp
= (int *) obj
;
5542 const char *name
= bfd_get_section_name (abfd
, sect
);
5544 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5546 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5548 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5549 warning (_("unrecognized .gcc_compiled_longXX"));
5552 static enum mips_abi
5553 global_mips_abi (void)
5557 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5558 if (mips_abi_strings
[i
] == mips_abi_string
)
5559 return (enum mips_abi
) i
;
5561 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5565 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5567 /* If the size matches the set of 32-bit or 64-bit integer registers,
5568 assume that's what we've got. */
5569 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5570 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5572 /* If the size matches the full set of registers GDB traditionally
5573 knows about, including floating point, for either 32-bit or
5574 64-bit, assume that's what we've got. */
5575 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5576 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5578 /* Otherwise we don't have a useful guess. */
5581 static struct value
*
5582 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5584 const int *reg_p
= baton
;
5585 return value_of_register (*reg_p
, frame
);
5588 static struct gdbarch
*
5589 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5591 struct gdbarch
*gdbarch
;
5592 struct gdbarch_tdep
*tdep
;
5594 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5596 enum mips_fpu_type fpu_type
;
5597 struct tdesc_arch_data
*tdesc_data
= NULL
;
5598 int elf_fpu_type
= 0;
5600 /* Check any target description for validity. */
5601 if (tdesc_has_registers (info
.target_desc
))
5603 static const char *const mips_gprs
[] = {
5604 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5605 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5606 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5607 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5609 static const char *const mips_fprs
[] = {
5610 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5611 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5612 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5613 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5616 const struct tdesc_feature
*feature
;
5619 feature
= tdesc_find_feature (info
.target_desc
,
5620 "org.gnu.gdb.mips.cpu");
5621 if (feature
== NULL
)
5624 tdesc_data
= tdesc_data_alloc ();
5627 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5628 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5632 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5633 MIPS_EMBED_LO_REGNUM
, "lo");
5634 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5635 MIPS_EMBED_HI_REGNUM
, "hi");
5636 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5637 MIPS_EMBED_PC_REGNUM
, "pc");
5641 tdesc_data_cleanup (tdesc_data
);
5645 feature
= tdesc_find_feature (info
.target_desc
,
5646 "org.gnu.gdb.mips.cp0");
5647 if (feature
== NULL
)
5649 tdesc_data_cleanup (tdesc_data
);
5654 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5655 MIPS_EMBED_BADVADDR_REGNUM
,
5657 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5658 MIPS_PS_REGNUM
, "status");
5659 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5660 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5664 tdesc_data_cleanup (tdesc_data
);
5668 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5669 backend is not prepared for that, though. */
5670 feature
= tdesc_find_feature (info
.target_desc
,
5671 "org.gnu.gdb.mips.fpu");
5672 if (feature
== NULL
)
5674 tdesc_data_cleanup (tdesc_data
);
5679 for (i
= 0; i
< 32; i
++)
5680 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5681 i
+ MIPS_EMBED_FP0_REGNUM
,
5684 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5685 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5686 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5687 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5691 tdesc_data_cleanup (tdesc_data
);
5695 /* It would be nice to detect an attempt to use a 64-bit ABI
5696 when only 32-bit registers are provided. */
5699 /* First of all, extract the elf_flags, if available. */
5700 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5701 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5702 else if (arches
!= NULL
)
5703 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5707 fprintf_unfiltered (gdb_stdlog
,
5708 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5710 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5711 switch ((elf_flags
& EF_MIPS_ABI
))
5713 case E_MIPS_ABI_O32
:
5714 found_abi
= MIPS_ABI_O32
;
5716 case E_MIPS_ABI_O64
:
5717 found_abi
= MIPS_ABI_O64
;
5719 case E_MIPS_ABI_EABI32
:
5720 found_abi
= MIPS_ABI_EABI32
;
5722 case E_MIPS_ABI_EABI64
:
5723 found_abi
= MIPS_ABI_EABI64
;
5726 if ((elf_flags
& EF_MIPS_ABI2
))
5727 found_abi
= MIPS_ABI_N32
;
5729 found_abi
= MIPS_ABI_UNKNOWN
;
5733 /* GCC creates a pseudo-section whose name describes the ABI. */
5734 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5735 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5737 /* If we have no useful BFD information, use the ABI from the last
5738 MIPS architecture (if there is one). */
5739 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5740 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5742 /* Try the architecture for any hint of the correct ABI. */
5743 if (found_abi
== MIPS_ABI_UNKNOWN
5744 && info
.bfd_arch_info
!= NULL
5745 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5747 switch (info
.bfd_arch_info
->mach
)
5749 case bfd_mach_mips3900
:
5750 found_abi
= MIPS_ABI_EABI32
;
5752 case bfd_mach_mips4100
:
5753 case bfd_mach_mips5000
:
5754 found_abi
= MIPS_ABI_EABI64
;
5756 case bfd_mach_mips8000
:
5757 case bfd_mach_mips10000
:
5758 /* On Irix, ELF64 executables use the N64 ABI. The
5759 pseudo-sections which describe the ABI aren't present
5760 on IRIX. (Even for executables created by gcc.) */
5761 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5762 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5763 found_abi
= MIPS_ABI_N64
;
5765 found_abi
= MIPS_ABI_N32
;
5770 /* Default 64-bit objects to N64 instead of O32. */
5771 if (found_abi
== MIPS_ABI_UNKNOWN
5772 && info
.abfd
!= NULL
5773 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5774 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5775 found_abi
= MIPS_ABI_N64
;
5778 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5781 /* What has the user specified from the command line? */
5782 wanted_abi
= global_mips_abi ();
5784 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5787 /* Now that we have found what the ABI for this binary would be,
5788 check whether the user is overriding it. */
5789 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5790 mips_abi
= wanted_abi
;
5791 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5792 mips_abi
= found_abi
;
5794 mips_abi
= MIPS_ABI_O32
;
5796 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5799 /* Also used when doing an architecture lookup. */
5801 fprintf_unfiltered (gdb_stdlog
,
5802 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5803 mips64_transfers_32bit_regs_p
);
5805 /* Determine the MIPS FPU type. */
5808 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5809 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5810 Tag_GNU_MIPS_ABI_FP
);
5811 #endif /* HAVE_ELF */
5813 if (!mips_fpu_type_auto
)
5814 fpu_type
= mips_fpu_type
;
5815 else if (elf_fpu_type
!= 0)
5817 switch (elf_fpu_type
)
5820 fpu_type
= MIPS_FPU_DOUBLE
;
5823 fpu_type
= MIPS_FPU_SINGLE
;
5827 /* Soft float or unknown. */
5828 fpu_type
= MIPS_FPU_NONE
;
5832 else if (info
.bfd_arch_info
!= NULL
5833 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5834 switch (info
.bfd_arch_info
->mach
)
5836 case bfd_mach_mips3900
:
5837 case bfd_mach_mips4100
:
5838 case bfd_mach_mips4111
:
5839 case bfd_mach_mips4120
:
5840 fpu_type
= MIPS_FPU_NONE
;
5842 case bfd_mach_mips4650
:
5843 fpu_type
= MIPS_FPU_SINGLE
;
5846 fpu_type
= MIPS_FPU_DOUBLE
;
5849 else if (arches
!= NULL
)
5850 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5852 fpu_type
= MIPS_FPU_DOUBLE
;
5854 fprintf_unfiltered (gdb_stdlog
,
5855 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5857 /* Check for blatant incompatibilities. */
5859 /* If we have only 32-bit registers, then we can't debug a 64-bit
5861 if (info
.target_desc
5862 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5863 && mips_abi
!= MIPS_ABI_EABI32
5864 && mips_abi
!= MIPS_ABI_O32
)
5866 if (tdesc_data
!= NULL
)
5867 tdesc_data_cleanup (tdesc_data
);
5871 /* try to find a pre-existing architecture */
5872 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5874 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5876 /* MIPS needs to be pedantic about which ABI the object is
5878 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5880 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5882 /* Need to be pedantic about which register virtual size is
5884 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5885 != mips64_transfers_32bit_regs_p
)
5887 /* Be pedantic about which FPU is selected. */
5888 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5891 if (tdesc_data
!= NULL
)
5892 tdesc_data_cleanup (tdesc_data
);
5893 return arches
->gdbarch
;
5896 /* Need a new architecture. Fill in a target specific vector. */
5897 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5898 gdbarch
= gdbarch_alloc (&info
, tdep
);
5899 tdep
->elf_flags
= elf_flags
;
5900 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5901 tdep
->found_abi
= found_abi
;
5902 tdep
->mips_abi
= mips_abi
;
5903 tdep
->mips_fpu_type
= fpu_type
;
5904 tdep
->register_size_valid_p
= 0;
5905 tdep
->register_size
= 0;
5906 tdep
->gregset
= NULL
;
5907 tdep
->gregset64
= NULL
;
5908 tdep
->fpregset
= NULL
;
5909 tdep
->fpregset64
= NULL
;
5911 if (info
.target_desc
)
5913 /* Some useful properties can be inferred from the target. */
5914 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5916 tdep
->register_size_valid_p
= 1;
5917 tdep
->register_size
= 4;
5919 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5921 tdep
->register_size_valid_p
= 1;
5922 tdep
->register_size
= 8;
5926 /* Initially set everything according to the default ABI/ISA. */
5927 set_gdbarch_short_bit (gdbarch
, 16);
5928 set_gdbarch_int_bit (gdbarch
, 32);
5929 set_gdbarch_float_bit (gdbarch
, 32);
5930 set_gdbarch_double_bit (gdbarch
, 64);
5931 set_gdbarch_long_double_bit (gdbarch
, 64);
5932 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5933 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5934 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5936 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5937 mips_elf_make_msymbol_special
);
5939 /* Fill in the OS dependant register numbers and names. */
5941 const char **reg_names
;
5942 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5943 struct mips_regnum
);
5944 if (tdesc_has_registers (info
.target_desc
))
5946 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5947 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5948 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5949 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5950 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5951 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5952 regnum
->fp_control_status
= 70;
5953 regnum
->fp_implementation_revision
= 71;
5954 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5957 else if (info
.osabi
== GDB_OSABI_IRIX
)
5962 regnum
->badvaddr
= 66;
5965 regnum
->fp_control_status
= 69;
5966 regnum
->fp_implementation_revision
= 70;
5968 reg_names
= mips_irix_reg_names
;
5972 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5973 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5974 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5975 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5976 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5977 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5978 regnum
->fp_control_status
= 70;
5979 regnum
->fp_implementation_revision
= 71;
5981 if (info
.bfd_arch_info
!= NULL
5982 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5983 reg_names
= mips_tx39_reg_names
;
5985 reg_names
= mips_generic_reg_names
;
5987 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5988 replaced by gdbarch_read_pc? */
5989 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5990 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5991 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5992 set_gdbarch_num_regs (gdbarch
, num_regs
);
5993 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5994 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5995 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5996 tdep
->mips_processor_reg_names
= reg_names
;
5997 tdep
->regnum
= regnum
;
6003 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6004 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6005 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6006 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6007 tdep
->default_mask_address_p
= 0;
6008 set_gdbarch_long_bit (gdbarch
, 32);
6009 set_gdbarch_ptr_bit (gdbarch
, 32);
6010 set_gdbarch_long_long_bit (gdbarch
, 64);
6013 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6014 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6015 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6016 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6017 tdep
->default_mask_address_p
= 0;
6018 set_gdbarch_long_bit (gdbarch
, 32);
6019 set_gdbarch_ptr_bit (gdbarch
, 32);
6020 set_gdbarch_long_long_bit (gdbarch
, 64);
6022 case MIPS_ABI_EABI32
:
6023 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6024 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6025 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6026 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6027 tdep
->default_mask_address_p
= 0;
6028 set_gdbarch_long_bit (gdbarch
, 32);
6029 set_gdbarch_ptr_bit (gdbarch
, 32);
6030 set_gdbarch_long_long_bit (gdbarch
, 64);
6032 case MIPS_ABI_EABI64
:
6033 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6034 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6035 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6036 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6037 tdep
->default_mask_address_p
= 0;
6038 set_gdbarch_long_bit (gdbarch
, 64);
6039 set_gdbarch_ptr_bit (gdbarch
, 64);
6040 set_gdbarch_long_long_bit (gdbarch
, 64);
6043 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6044 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6045 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6046 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6047 tdep
->default_mask_address_p
= 0;
6048 set_gdbarch_long_bit (gdbarch
, 32);
6049 set_gdbarch_ptr_bit (gdbarch
, 32);
6050 set_gdbarch_long_long_bit (gdbarch
, 64);
6051 set_gdbarch_long_double_bit (gdbarch
, 128);
6052 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6055 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6056 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6057 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6058 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6059 tdep
->default_mask_address_p
= 0;
6060 set_gdbarch_long_bit (gdbarch
, 64);
6061 set_gdbarch_ptr_bit (gdbarch
, 64);
6062 set_gdbarch_long_long_bit (gdbarch
, 64);
6063 set_gdbarch_long_double_bit (gdbarch
, 128);
6064 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6067 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6070 /* GCC creates a pseudo-section whose name specifies the size of
6071 longs, since -mlong32 or -mlong64 may be used independent of
6072 other options. How those options affect pointer sizes is ABI and
6073 architecture dependent, so use them to override the default sizes
6074 set by the ABI. This table shows the relationship between ABI,
6075 -mlongXX, and size of pointers:
6077 ABI -mlongXX ptr bits
6078 --- -------- --------
6092 Note that for o32 and eabi32, pointers are always 32 bits
6093 regardless of any -mlongXX option. For all others, pointers and
6094 longs are the same, as set by -mlongXX or set by defaults.
6097 if (info
.abfd
!= NULL
)
6101 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6104 set_gdbarch_long_bit (gdbarch
, long_bit
);
6108 case MIPS_ABI_EABI32
:
6113 case MIPS_ABI_EABI64
:
6114 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6117 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6122 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
6123 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
6126 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
6127 flag in object files because to do so would make it impossible to
6128 link with libraries compiled without "-gp32". This is
6129 unnecessarily restrictive.
6131 We could solve this problem by adding "-gp32" multilibs to gcc,
6132 but to set this flag before gcc is built with such multilibs will
6133 break too many systems.''
6135 But even more unhelpfully, the default linker output target for
6136 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
6137 for 64-bit programs - you need to change the ABI to change this,
6138 and not all gcc targets support that currently. Therefore using
6139 this flag to detect 32-bit mode would do the wrong thing given
6140 the current gcc - it would make GDB treat these 64-bit programs
6141 as 32-bit programs by default. */
6143 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
6144 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
6146 /* Add/remove bits from an address. The MIPS needs be careful to
6147 ensure that all 32 bit addresses are sign extended to 64 bits. */
6148 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
6150 /* Unwind the frame. */
6151 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
6152 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
6153 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
6155 /* Map debug register numbers onto internal register numbers. */
6156 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
6157 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
6158 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6159 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
6160 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
6161 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
6163 /* MIPS version of CALL_DUMMY */
6165 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
6166 replaced by a command, and all targets will default to on stack
6167 (regardless of the stack's execute status). */
6168 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
6169 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
6171 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
6172 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
6173 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
6175 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6176 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
6178 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
6180 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
6182 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
6183 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
6184 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
6186 set_gdbarch_register_type (gdbarch
, mips_register_type
);
6188 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
6190 if (mips_abi
== MIPS_ABI_N32
)
6191 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
6192 else if (mips_abi
== MIPS_ABI_N64
)
6193 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
6195 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
6197 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
6198 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
6199 need to all be folded into the target vector. Since they are
6200 being used as guards for target_stopped_by_watchpoint, why not have
6201 target_stopped_by_watchpoint return the type of watchpoint that the code
6203 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6205 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
6207 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
6209 /* Virtual tables. */
6210 set_gdbarch_vbit_in_delta (gdbarch
, 1);
6212 mips_register_g_packet_guesses (gdbarch
);
6214 /* Hook in OS ABI-specific overrides, if they have been registered. */
6215 info
.tdep_info
= (void *) tdesc_data
;
6216 gdbarch_init_osabi (info
, gdbarch
);
6218 /* Unwind the frame. */
6219 dwarf2_append_unwinders (gdbarch
);
6220 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
6221 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
6222 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
6223 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
6224 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
6225 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
6226 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
6230 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
6231 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
6233 /* Override the normal target description methods to handle our
6234 dual real and pseudo registers. */
6235 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6236 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
6238 num_regs
= gdbarch_num_regs (gdbarch
);
6239 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6240 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
6241 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
6244 /* Add ABI-specific aliases for the registers. */
6245 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
6246 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
6247 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
6248 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
6250 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
6251 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
6252 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
6254 /* Add some other standard aliases. */
6255 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
6256 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
6257 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
6259 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
6260 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
6261 value_of_mips_user_reg
,
6262 &mips_numeric_register_aliases
[i
].regnum
);
6268 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
6270 struct gdbarch_info info
;
6272 /* Force the architecture to update, and (if it's a MIPS architecture)
6273 mips_gdbarch_init will take care of the rest. */
6274 gdbarch_info_init (&info
);
6275 gdbarch_update_p (info
);
6278 /* Print out which MIPS ABI is in use. */
6281 show_mips_abi (struct ui_file
*file
,
6283 struct cmd_list_element
*ignored_cmd
,
6284 const char *ignored_value
)
6286 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6289 "The MIPS ABI is unknown because the current architecture "
6293 enum mips_abi global_abi
= global_mips_abi ();
6294 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
6295 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
6297 if (global_abi
== MIPS_ABI_UNKNOWN
)
6300 "The MIPS ABI is set automatically (currently \"%s\").\n",
6302 else if (global_abi
== actual_abi
)
6305 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
6309 /* Probably shouldn't happen... */
6312 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
6313 actual_abi_str
, mips_abi_strings
[global_abi
]);
6319 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6321 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6325 int ef_mips_32bitmode
;
6326 /* Determine the ISA. */
6327 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6345 /* Determine the size of a pointer. */
6346 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6347 fprintf_unfiltered (file
,
6348 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6350 fprintf_unfiltered (file
,
6351 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6353 fprintf_unfiltered (file
,
6354 "mips_dump_tdep: ef_mips_arch = %d\n",
6356 fprintf_unfiltered (file
,
6357 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6358 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6359 fprintf_unfiltered (file
,
6360 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6361 mips_mask_address_p (tdep
),
6362 tdep
->default_mask_address_p
);
6364 fprintf_unfiltered (file
,
6365 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6366 MIPS_DEFAULT_FPU_TYPE
,
6367 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6368 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6369 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6371 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6372 MIPS_EABI (gdbarch
));
6373 fprintf_unfiltered (file
,
6374 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6375 MIPS_FPU_TYPE (gdbarch
),
6376 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6377 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6378 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6382 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6385 _initialize_mips_tdep (void)
6387 static struct cmd_list_element
*mipsfpulist
= NULL
;
6388 struct cmd_list_element
*c
;
6390 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6391 if (MIPS_ABI_LAST
+ 1
6392 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6393 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6395 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6397 mips_pdr_data
= register_objfile_data ();
6399 /* Create feature sets with the appropriate properties. The values
6400 are not important. */
6401 mips_tdesc_gp32
= allocate_target_description ();
6402 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6404 mips_tdesc_gp64
= allocate_target_description ();
6405 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6407 /* Add root prefix command for all "set mips"/"show mips" commands */
6408 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6409 _("Various MIPS specific commands."),
6410 &setmipscmdlist
, "set mips ", 0, &setlist
);
6412 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6413 _("Various MIPS specific commands."),
6414 &showmipscmdlist
, "show mips ", 0, &showlist
);
6416 /* Allow the user to override the ABI. */
6417 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6418 &mips_abi_string
, _("\
6419 Set the MIPS ABI used by this program."), _("\
6420 Show the MIPS ABI used by this program."), _("\
6421 This option can be set to one of:\n\
6422 auto - the default ABI associated with the current binary\n\
6431 &setmipscmdlist
, &showmipscmdlist
);
6433 /* Let the user turn off floating point and set the fence post for
6434 heuristic_proc_start. */
6436 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6437 _("Set use of MIPS floating-point coprocessor."),
6438 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6439 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6440 _("Select single-precision MIPS floating-point coprocessor."),
6442 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6443 _("Select double-precision MIPS floating-point coprocessor."),
6445 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6446 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6447 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6448 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6449 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6450 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6451 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6452 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6453 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6454 _("Select MIPS floating-point coprocessor automatically."),
6456 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6457 _("Show current use of MIPS floating-point coprocessor target."),
6460 /* We really would like to have both "0" and "unlimited" work, but
6461 command.c doesn't deal with that. So make it a var_zinteger
6462 because the user can always use "999999" or some such for unlimited. */
6463 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6464 &heuristic_fence_post
, _("\
6465 Set the distance searched for the start of a function."), _("\
6466 Show the distance searched for the start of a function."), _("\
6467 If you are debugging a stripped executable, GDB needs to search through the\n\
6468 program for the start of a function. This command sets the distance of the\n\
6469 search. The only need to set it is when debugging a stripped executable."),
6470 reinit_frame_cache_sfunc
,
6471 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6472 &setlist
, &showlist
);
6474 /* Allow the user to control whether the upper bits of 64-bit
6475 addresses should be zeroed. */
6476 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6477 &mask_address_var
, _("\
6478 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6479 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6480 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
6481 allow GDB to determine the correct value."),
6482 NULL
, show_mask_address
,
6483 &setmipscmdlist
, &showmipscmdlist
);
6485 /* Allow the user to control the size of 32 bit registers within the
6486 raw remote packet. */
6487 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6488 &mips64_transfers_32bit_regs_p
, _("\
6489 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6491 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6493 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6494 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6495 64 bits for others. Use \"off\" to disable compatibility mode"),
6496 set_mips64_transfers_32bit_regs
,
6497 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6498 &setlist
, &showlist
);
6500 /* Debug this files internals. */
6501 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6503 Set mips debugging."), _("\
6504 Show mips debugging."), _("\
6505 When non-zero, mips specific debugging is enabled."),
6507 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6508 &setdebuglist
, &showdebuglist
);