1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place - Suite 330,
25 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "gdb_assert.h"
41 #include "arch-utils.h"
44 #include "mips-tdep.h"
46 #include "reggroups.h"
47 #include "opcode/mips.h"
51 #include "sim-regno.h"
53 #include "frame-unwind.h"
54 #include "frame-base.h"
55 #include "trad-frame.h"
57 #include "floatformat.h"
59 static const struct objfile_data
*mips_pdr_data
;
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 /* A useful bit in the CP0 status register (PS_REGNUM). */
64 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
65 #define ST0_FR (1 << 26)
67 /* The sizes of floating point registers. */
71 MIPS_FPU_SINGLE_REGSIZE
= 4,
72 MIPS_FPU_DOUBLE_REGSIZE
= 8
76 static const char *mips_abi_string
;
78 static const char *mips_abi_strings
[] = {
89 struct frame_extra_info
91 mips_extra_func_info_t proc_desc
;
95 /* Various MIPS ISA options (related to stack analysis) can be
96 overridden dynamically. Establish an enum/array for managing
99 static const char size_auto
[] = "auto";
100 static const char size_32
[] = "32";
101 static const char size_64
[] = "64";
103 static const char *size_enums
[] = {
110 /* Some MIPS boards don't support floating point while others only
111 support single-precision floating-point operations. */
115 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
116 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
117 MIPS_FPU_NONE
/* No floating point. */
120 #ifndef MIPS_DEFAULT_FPU_TYPE
121 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
123 static int mips_fpu_type_auto
= 1;
124 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
126 static int mips_debug
= 0;
128 /* MIPS specific per-architecture information */
131 /* from the elf header */
135 enum mips_abi mips_abi
;
136 enum mips_abi found_abi
;
137 enum mips_fpu_type mips_fpu_type
;
138 int mips_last_arg_regnum
;
139 int mips_last_fp_arg_regnum
;
140 int default_mask_address_p
;
141 /* Is the target using 64-bit raw integer registers but only
142 storing a left-aligned 32-bit value in each? */
143 int mips64_transfers_32bit_regs_p
;
144 /* Indexes for various registers. IRIX and embedded have
145 different values. This contains the "public" fields. Don't
146 add any that do not need to be public. */
147 const struct mips_regnum
*regnum
;
148 /* Register names table for the current register set. */
149 const char **mips_processor_reg_names
;
153 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
159 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
160 They are implemented as a pair of 64bit doubles where the high
161 part holds the result of the operation rounded to double, and
162 the low double holds the difference between the exact result and
163 the rounded result. So "high" + "low" contains the result with
164 added precision. Unfortunately, the floatformat structure used
165 by GDB is not powerful enough to describe this format. As a temporary
166 measure, we define a 128bit floatformat that only uses the high part.
167 We lose a bit of precision but that's probably the best we can do
168 for now with the current infrastructure. */
170 static const struct floatformat floatformat_n32n64_long_double_big
=
172 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
173 floatformat_intbit_no
,
174 "floatformat_ieee_double_big",
175 n32n64_floatformat_always_valid
178 const struct mips_regnum
*
179 mips_regnum (struct gdbarch
*gdbarch
)
181 return gdbarch_tdep (gdbarch
)->regnum
;
185 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
187 return mips_regnum (gdbarch
)->fp0
+ 12;
190 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
191 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
193 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
195 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
197 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
199 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
200 functions to test, set, or clear bit 0 of addresses. */
203 is_mips16_addr (CORE_ADDR addr
)
209 make_mips16_addr (CORE_ADDR addr
)
215 unmake_mips16_addr (CORE_ADDR addr
)
217 return ((addr
) & ~1);
220 /* Return the contents of register REGNUM as a signed integer. */
223 read_signed_register (int regnum
)
226 regcache_cooked_read_signed (current_regcache
, regnum
, &val
);
231 read_signed_register_pid (int regnum
, ptid_t ptid
)
236 if (ptid_equal (ptid
, inferior_ptid
))
237 return read_signed_register (regnum
);
239 save_ptid
= inferior_ptid
;
241 inferior_ptid
= ptid
;
243 retval
= read_signed_register (regnum
);
245 inferior_ptid
= save_ptid
;
250 /* Return the MIPS ABI associated with GDBARCH. */
252 mips_abi (struct gdbarch
*gdbarch
)
254 return gdbarch_tdep (gdbarch
)->mips_abi
;
258 mips_isa_regsize (struct gdbarch
*gdbarch
)
260 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
261 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
264 /* Return the currently configured (or set) saved register size. */
266 static const char *mips_abi_regsize_string
= size_auto
;
269 mips_abi_regsize (struct gdbarch
*gdbarch
)
271 if (mips_abi_regsize_string
== size_auto
)
272 switch (mips_abi (gdbarch
))
274 case MIPS_ABI_EABI32
:
280 case MIPS_ABI_EABI64
:
282 case MIPS_ABI_UNKNOWN
:
285 internal_error (__FILE__
, __LINE__
, "bad switch");
287 else if (mips_abi_regsize_string
== size_64
)
289 else /* if (mips_abi_regsize_string == size_32) */
293 /* Functions for setting and testing a bit in a minimal symbol that
294 marks it as 16-bit function. The MSB of the minimal symbol's
295 "info" field is used for this purpose.
297 ELF_MAKE_MSYMBOL_SPECIAL tests whether an ELF symbol is "special",
298 i.e. refers to a 16-bit function, and sets a "special" bit in a
299 minimal symbol to mark it as a 16-bit function
301 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
304 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
306 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
308 MSYMBOL_INFO (msym
) = (char *)
309 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
310 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
315 msymbol_is_special (struct minimal_symbol
*msym
)
317 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
320 /* XFER a value from the big/little/left end of the register.
321 Depending on the size of the value it might occupy the entire
322 register or just part of it. Make an allowance for this, aligning
323 things accordingly. */
326 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
327 enum bfd_endian endian
, bfd_byte
* in
,
328 const bfd_byte
* out
, int buf_offset
)
331 gdb_assert (reg_num
>= NUM_REGS
);
332 /* Need to transfer the left or right part of the register, based on
333 the targets byte order. */
337 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
339 case BFD_ENDIAN_LITTLE
:
342 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
346 internal_error (__FILE__
, __LINE__
, "bad switch");
349 fprintf_unfiltered (gdb_stderr
,
350 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
351 reg_num
, reg_offset
, buf_offset
, length
);
352 if (mips_debug
&& out
!= NULL
)
355 fprintf_unfiltered (gdb_stdlog
, "out ");
356 for (i
= 0; i
< length
; i
++)
357 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
360 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
363 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
365 if (mips_debug
&& in
!= NULL
)
368 fprintf_unfiltered (gdb_stdlog
, "in ");
369 for (i
= 0; i
< length
; i
++)
370 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
373 fprintf_unfiltered (gdb_stdlog
, "\n");
376 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
377 compatiblity mode. A return value of 1 means that we have
378 physical 64-bit registers, but should treat them as 32-bit registers. */
381 mips2_fp_compat (void)
383 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
385 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
390 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
391 in all the places we deal with FP registers. PR gdb/413. */
392 /* Otherwise check the FR bit in the status register - it controls
393 the FP compatiblity mode. If it is clear we are in compatibility
395 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
402 /* The amount of space reserved on the stack for registers. This is
403 different to MIPS_ABI_REGSIZE as it determines the alignment of
404 data allocated after the registers have run out. */
406 static const char *mips_stack_argsize_string
= size_auto
;
409 mips_stack_argsize (struct gdbarch
*gdbarch
)
411 if (mips_stack_argsize_string
== size_auto
)
412 return mips_abi_regsize (gdbarch
);
413 else if (mips_stack_argsize_string
== size_64
)
415 else /* if (mips_stack_argsize_string == size_32) */
419 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
421 struct mips_frame_cache
;
422 static mips_extra_func_info_t
heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
,
424 struct mips_frame_cache
*);
425 static mips_extra_func_info_t
non_heuristic_proc_desc (CORE_ADDR pc
,
428 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
430 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
432 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
434 static CORE_ADDR
after_prologue (CORE_ADDR pc
);
436 static struct type
*mips_float_register_type (void);
437 static struct type
*mips_double_register_type (void);
439 /* The list of available "set mips " and "show mips " commands */
441 static struct cmd_list_element
*setmipscmdlist
= NULL
;
442 static struct cmd_list_element
*showmipscmdlist
= NULL
;
444 /* Integer registers 0 thru 31 are handled explicitly by
445 mips_register_name(). Processor specific registers 32 and above
446 are listed in the followign tables. */
449 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
453 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
454 "sr", "lo", "hi", "bad", "cause", "pc",
455 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
456 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
457 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
458 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
459 "fsr", "fir", "" /*"fp" */ , "",
460 "", "", "", "", "", "", "", "",
461 "", "", "", "", "", "", "", "",
464 /* Names of IDT R3041 registers. */
466 static const char *mips_r3041_reg_names
[] = {
467 "sr", "lo", "hi", "bad", "cause", "pc",
468 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
469 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
470 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
471 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
472 "fsr", "fir", "", /*"fp" */ "",
473 "", "", "bus", "ccfg", "", "", "", "",
474 "", "", "port", "cmp", "", "", "epc", "prid",
477 /* Names of tx39 registers. */
479 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
480 "sr", "lo", "hi", "bad", "cause", "pc",
481 "", "", "", "", "", "", "", "",
482 "", "", "", "", "", "", "", "",
483 "", "", "", "", "", "", "", "",
484 "", "", "", "", "", "", "", "",
486 "", "", "", "", "", "", "", "",
487 "", "", "config", "cache", "debug", "depc", "epc", ""
490 /* Names of IRIX registers. */
491 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
492 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
493 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
494 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
495 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
496 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
500 /* Return the name of the register corresponding to REGNO. */
502 mips_register_name (int regno
)
504 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
505 /* GPR names for all ABIs other than n32/n64. */
506 static char *mips_gpr_names
[] = {
507 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
508 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
509 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
510 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
513 /* GPR names for n32 and n64 ABIs. */
514 static char *mips_n32_n64_gpr_names
[] = {
515 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
516 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
517 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
518 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
521 enum mips_abi abi
= mips_abi (current_gdbarch
);
523 /* Map [NUM_REGS .. 2*NUM_REGS) onto the raw registers, but then
524 don't make the raw register names visible. */
525 int rawnum
= regno
% NUM_REGS
;
526 if (regno
< NUM_REGS
)
529 /* The MIPS integer registers are always mapped from 0 to 31. The
530 names of the registers (which reflects the conventions regarding
531 register use) vary depending on the ABI. */
532 if (0 <= rawnum
&& rawnum
< 32)
534 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
535 return mips_n32_n64_gpr_names
[rawnum
];
537 return mips_gpr_names
[rawnum
];
539 else if (32 <= rawnum
&& rawnum
< NUM_REGS
)
541 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
542 return tdep
->mips_processor_reg_names
[rawnum
- 32];
545 internal_error (__FILE__
, __LINE__
,
546 "mips_register_name: bad register number %d", rawnum
);
549 /* Return the groups that a MIPS register can be categorised into. */
552 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
553 struct reggroup
*reggroup
)
558 int rawnum
= regnum
% NUM_REGS
;
559 int pseudo
= regnum
/ NUM_REGS
;
560 if (reggroup
== all_reggroup
)
562 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
563 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
564 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
565 (gdbarch), as not all architectures are multi-arch. */
566 raw_p
= rawnum
< NUM_REGS
;
567 if (REGISTER_NAME (regnum
) == NULL
|| REGISTER_NAME (regnum
)[0] == '\0')
569 if (reggroup
== float_reggroup
)
570 return float_p
&& pseudo
;
571 if (reggroup
== vector_reggroup
)
572 return vector_p
&& pseudo
;
573 if (reggroup
== general_reggroup
)
574 return (!vector_p
&& !float_p
) && pseudo
;
575 /* Save the pseudo registers. Need to make certain that any code
576 extracting register values from a saved register cache also uses
578 if (reggroup
== save_reggroup
)
579 return raw_p
&& pseudo
;
580 /* Restore the same pseudo register. */
581 if (reggroup
== restore_reggroup
)
582 return raw_p
&& pseudo
;
586 /* Map the symbol table registers which live in the range [1 *
587 NUM_REGS .. 2 * NUM_REGS) back onto the corresponding raw
588 registers. Take care of alignment and size problems. */
591 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
592 int cookednum
, void *buf
)
594 int rawnum
= cookednum
% NUM_REGS
;
595 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
596 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
597 regcache_raw_read (regcache
, rawnum
, buf
);
598 else if (register_size (gdbarch
, rawnum
) >
599 register_size (gdbarch
, cookednum
))
601 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
602 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
603 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
605 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
608 internal_error (__FILE__
, __LINE__
, "bad register size");
612 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
613 struct regcache
*regcache
, int cookednum
,
616 int rawnum
= cookednum
% NUM_REGS
;
617 gdb_assert (cookednum
>= NUM_REGS
&& cookednum
< 2 * NUM_REGS
);
618 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
619 regcache_raw_write (regcache
, rawnum
, buf
);
620 else if (register_size (gdbarch
, rawnum
) >
621 register_size (gdbarch
, cookednum
))
623 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
624 || TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
625 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
627 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
630 internal_error (__FILE__
, __LINE__
, "bad register size");
633 /* Table to translate MIPS16 register field to actual register number. */
634 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
636 /* Heuristic_proc_start may hunt through the text section for a long
637 time across a 2400 baud serial line. Allows the user to limit this
640 static unsigned int heuristic_fence_post
= 0;
642 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
643 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
644 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
645 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
646 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
647 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
648 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
649 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
650 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
651 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
652 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
653 this will corrupt pdr.iline. Fortunately we don't use it. */
654 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
655 #define _PROC_MAGIC_ 0x0F0F0F0F
657 /* Number of bytes of storage in the actual machine representation for
658 register N. NOTE: This defines the pseudo register type so need to
659 rebuild the architecture vector. */
661 static int mips64_transfers_32bit_regs_p
= 0;
664 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
665 struct cmd_list_element
*c
)
667 struct gdbarch_info info
;
668 gdbarch_info_init (&info
);
669 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
670 instead of relying on globals. Doing that would let generic code
671 handle the search for this specific architecture. */
672 if (!gdbarch_update_p (info
))
674 mips64_transfers_32bit_regs_p
= 0;
675 error ("32-bit compatibility mode not supported");
679 /* Convert to/from a register and the corresponding memory value. */
682 mips_convert_register_p (int regnum
, struct type
*type
)
684 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
685 && register_size (current_gdbarch
, regnum
) == 4
686 && (regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
687 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32
688 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
692 mips_register_to_value (struct frame_info
*frame
, int regnum
,
693 struct type
*type
, void *to
)
695 get_frame_register (frame
, regnum
+ 0, (char *) to
+ 4);
696 get_frame_register (frame
, regnum
+ 1, (char *) to
+ 0);
700 mips_value_to_register (struct frame_info
*frame
, int regnum
,
701 struct type
*type
, const void *from
)
703 put_frame_register (frame
, regnum
+ 0, (const char *) from
+ 4);
704 put_frame_register (frame
, regnum
+ 1, (const char *) from
+ 0);
707 /* Return the GDB type object for the "standard" data type of data in
711 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
713 gdb_assert (regnum
>= 0 && regnum
< 2 * NUM_REGS
);
714 if ((regnum
% NUM_REGS
) >= mips_regnum (current_gdbarch
)->fp0
715 && (regnum
% NUM_REGS
) < mips_regnum (current_gdbarch
)->fp0
+ 32)
717 /* The floating-point registers raw, or cooked, always match
718 mips_isa_regsize(), and also map 1:1, byte for byte. */
719 switch (gdbarch_byte_order (gdbarch
))
722 if (mips_isa_regsize (gdbarch
) == 4)
723 return builtin_type_ieee_single_big
;
725 return builtin_type_ieee_double_big
;
726 case BFD_ENDIAN_LITTLE
:
727 if (mips_isa_regsize (gdbarch
) == 4)
728 return builtin_type_ieee_single_little
;
730 return builtin_type_ieee_double_little
;
731 case BFD_ENDIAN_UNKNOWN
:
733 internal_error (__FILE__
, __LINE__
, "bad switch");
736 else if (regnum
< NUM_REGS
)
738 /* The raw or ISA registers. These are all sized according to
740 if (mips_isa_regsize (gdbarch
) == 4)
741 return builtin_type_int32
;
743 return builtin_type_int64
;
747 /* The cooked or ABI registers. These are sized according to
748 the ABI (with a few complications). */
749 if (regnum
>= (NUM_REGS
750 + mips_regnum (current_gdbarch
)->fp_control_status
)
751 && regnum
<= NUM_REGS
+ LAST_EMBED_REGNUM
)
752 /* The pseudo/cooked view of the embedded registers is always
753 32-bit. The raw view is handled below. */
754 return builtin_type_int32
;
755 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
756 /* The target, while possibly using a 64-bit register buffer,
757 is only transfering 32-bits of each integer register.
758 Reflect this in the cooked/pseudo (ABI) register value. */
759 return builtin_type_int32
;
760 else if (mips_abi_regsize (gdbarch
) == 4)
761 /* The ABI is restricted to 32-bit registers (the ISA could be
763 return builtin_type_int32
;
766 return builtin_type_int64
;
770 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
775 return read_signed_register (MIPS_SP_REGNUM
);
778 /* Should the upper word of 64-bit addresses be zeroed? */
779 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
782 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
784 switch (mask_address_var
)
786 case AUTO_BOOLEAN_TRUE
:
788 case AUTO_BOOLEAN_FALSE
:
791 case AUTO_BOOLEAN_AUTO
:
792 return tdep
->default_mask_address_p
;
794 internal_error (__FILE__
, __LINE__
, "mips_mask_address_p: bad switch");
800 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
802 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
803 switch (mask_address_var
)
805 case AUTO_BOOLEAN_TRUE
:
806 printf_filtered ("The 32 bit mips address mask is enabled\n");
808 case AUTO_BOOLEAN_FALSE
:
809 printf_filtered ("The 32 bit mips address mask is disabled\n");
811 case AUTO_BOOLEAN_AUTO
:
813 ("The 32 bit address mask is set automatically. Currently %s\n",
814 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
817 internal_error (__FILE__
, __LINE__
, "show_mask_address: bad switch");
822 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
825 pc_is_mips16 (bfd_vma memaddr
)
827 struct minimal_symbol
*sym
;
829 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
830 if (is_mips16_addr (memaddr
))
833 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
834 the high bit of the info field. Use this to decide if the function is
835 MIPS16 or normal MIPS. */
836 sym
= lookup_minimal_symbol_by_pc (memaddr
);
838 return msymbol_is_special (sym
);
843 /* MIPS believes that the PC has a sign extended value. Perhaps the
844 all registers should be sign extended for simplicity? */
847 mips_read_pc (ptid_t ptid
)
849 return read_signed_register_pid (mips_regnum (current_gdbarch
)->pc
, ptid
);
853 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
855 return frame_unwind_register_signed (next_frame
,
856 NUM_REGS
+ mips_regnum (gdbarch
)->pc
);
859 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
860 dummy frame. The frame ID's base needs to match the TOS value
861 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
864 static struct frame_id
865 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
867 return frame_id_build (frame_unwind_register_signed (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
),
868 frame_pc_unwind (next_frame
));
872 mips_write_pc (CORE_ADDR pc
, ptid_t ptid
)
874 write_register_pid (mips_regnum (current_gdbarch
)->pc
, pc
, ptid
);
877 /* This returns the PC of the first inst after the prologue. If we can't
878 find the prologue, then return 0. */
881 after_prologue (CORE_ADDR pc
)
883 mips_extra_func_info_t proc_desc
;
884 struct symtab_and_line sal
;
885 CORE_ADDR func_addr
, func_end
;
886 CORE_ADDR startaddr
= 0;
888 /* Pass a NULL next_frame to heuristic_proc_desc. We should not
889 attempt to read the stack pointer from the current machine state,
890 because the current machine state has nothing to do with the
891 information we need from the proc_desc; and the process may or
892 may not exist right now. */
893 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
896 /* IF this is the topmost frame AND (this proc does not have
897 debugging information OR the PC is in the procedure prologue)
898 THEN create a "heuristic" proc_desc (by analyzing the actual
899 code) to replace the "official" proc_desc. */
900 struct symtab_and_line val
;
901 if (PROC_SYMBOL (proc_desc
))
903 val
= find_pc_line (BLOCK_START
904 (SYMBOL_BLOCK_VALUE (PROC_SYMBOL (proc_desc
))),
906 val
.pc
= val
.end
? val
.end
: pc
;
908 if (!PROC_SYMBOL (proc_desc
) || pc
< val
.pc
)
910 mips_extra_func_info_t found_heuristic
=
911 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
), pc
, NULL
, NULL
);
913 proc_desc
= found_heuristic
;
919 startaddr
= heuristic_proc_start (pc
);
921 proc_desc
= heuristic_proc_desc (startaddr
, pc
, NULL
, NULL
);
926 /* If function is frameless, then we need to do it the hard way. I
927 strongly suspect that frameless always means prologueless... */
928 if (PROC_FRAME_REG (proc_desc
) == MIPS_SP_REGNUM
929 && PROC_FRAME_OFFSET (proc_desc
) == 0)
933 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
934 return 0; /* Unknown */
936 sal
= find_pc_line (func_addr
, 0);
938 if (sal
.end
< func_end
)
941 /* The line after the prologue is after the end of the function. In this
942 case, tell the caller to find the prologue the hard way. */
947 /* Fetch and return instruction from the specified location. If the PC
948 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
951 mips_fetch_instruction (CORE_ADDR addr
)
953 char buf
[MIPS32_INSN_SIZE
];
957 if (pc_is_mips16 (addr
))
959 instlen
= MIPS16_INSN_SIZE
;
960 addr
= unmake_mips16_addr (addr
);
963 instlen
= MIPS32_INSN_SIZE
;
964 status
= deprecated_read_memory_nobpt (addr
, buf
, instlen
);
966 memory_error (status
, addr
);
967 return extract_unsigned_integer (buf
, instlen
);
971 mips16_fetch_instruction (CORE_ADDR addr
)
973 char buf
[MIPS16_INSN_SIZE
];
976 addr
= unmake_mips16_addr (addr
);
977 status
= deprecated_read_memory_nobpt (addr
, buf
, sizeof (buf
));
979 memory_error (status
, addr
);
980 return extract_unsigned_integer (buf
, sizeof (buf
));
983 /* These the fields of 32 bit mips instructions */
984 #define mips32_op(x) (x >> 26)
985 #define itype_op(x) (x >> 26)
986 #define itype_rs(x) ((x >> 21) & 0x1f)
987 #define itype_rt(x) ((x >> 16) & 0x1f)
988 #define itype_immediate(x) (x & 0xffff)
990 #define jtype_op(x) (x >> 26)
991 #define jtype_target(x) (x & 0x03ffffff)
993 #define rtype_op(x) (x >> 26)
994 #define rtype_rs(x) ((x >> 21) & 0x1f)
995 #define rtype_rt(x) ((x >> 16) & 0x1f)
996 #define rtype_rd(x) ((x >> 11) & 0x1f)
997 #define rtype_shamt(x) ((x >> 6) & 0x1f)
998 #define rtype_funct(x) (x & 0x3f)
1001 mips32_relative_offset (unsigned long inst
)
1004 x
= itype_immediate (inst
);
1005 if (x
& 0x8000) /* sign bit set */
1007 x
|= 0xffff0000; /* sign extension */
1013 /* Determine whate to set a single step breakpoint while considering
1014 branch prediction */
1016 mips32_next_pc (CORE_ADDR pc
)
1020 inst
= mips_fetch_instruction (pc
);
1021 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1023 if (itype_op (inst
) >> 2 == 5)
1024 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1026 op
= (itype_op (inst
) & 0x03);
1036 goto greater_branch
;
1041 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1042 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1044 int tf
= itype_rt (inst
) & 0x01;
1045 int cnum
= itype_rt (inst
) >> 2;
1047 read_signed_register (mips_regnum (current_gdbarch
)->
1049 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1051 if (((cond
>> cnum
) & 0x01) == tf
)
1052 pc
+= mips32_relative_offset (inst
) + 4;
1057 pc
+= 4; /* Not a branch, next instruction is easy */
1060 { /* This gets way messy */
1062 /* Further subdivide into SPECIAL, REGIMM and other */
1063 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1065 case 0: /* SPECIAL */
1066 op
= rtype_funct (inst
);
1071 /* Set PC to that address */
1072 pc
= read_signed_register (rtype_rs (inst
));
1078 break; /* end SPECIAL */
1079 case 1: /* REGIMM */
1081 op
= itype_rt (inst
); /* branch condition */
1086 case 16: /* BLTZAL */
1087 case 18: /* BLTZALL */
1089 if (read_signed_register (itype_rs (inst
)) < 0)
1090 pc
+= mips32_relative_offset (inst
) + 4;
1092 pc
+= 8; /* after the delay slot */
1096 case 17: /* BGEZAL */
1097 case 19: /* BGEZALL */
1098 if (read_signed_register (itype_rs (inst
)) >= 0)
1099 pc
+= mips32_relative_offset (inst
) + 4;
1101 pc
+= 8; /* after the delay slot */
1103 /* All of the other instructions in the REGIMM category */
1108 break; /* end REGIMM */
1113 reg
= jtype_target (inst
) << 2;
1114 /* Upper four bits get never changed... */
1115 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
1118 /* FIXME case JALX : */
1121 reg
= jtype_target (inst
) << 2;
1122 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
1123 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1125 break; /* The new PC will be alternate mode */
1126 case 4: /* BEQ, BEQL */
1128 if (read_signed_register (itype_rs (inst
)) ==
1129 read_signed_register (itype_rt (inst
)))
1130 pc
+= mips32_relative_offset (inst
) + 4;
1134 case 5: /* BNE, BNEL */
1136 if (read_signed_register (itype_rs (inst
)) !=
1137 read_signed_register (itype_rt (inst
)))
1138 pc
+= mips32_relative_offset (inst
) + 4;
1142 case 6: /* BLEZ, BLEZL */
1143 if (read_signed_register (itype_rs (inst
)) <= 0)
1144 pc
+= mips32_relative_offset (inst
) + 4;
1150 greater_branch
: /* BGTZ, BGTZL */
1151 if (read_signed_register (itype_rs (inst
)) > 0)
1152 pc
+= mips32_relative_offset (inst
) + 4;
1159 } /* mips32_next_pc */
1161 /* Decoding the next place to set a breakpoint is irregular for the
1162 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1163 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1164 We dont want to set a single step instruction on the extend instruction
1168 /* Lots of mips16 instruction formats */
1169 /* Predicting jumps requires itype,ritype,i8type
1170 and their extensions extItype,extritype,extI8type
1172 enum mips16_inst_fmts
1174 itype
, /* 0 immediate 5,10 */
1175 ritype
, /* 1 5,3,8 */
1176 rrtype
, /* 2 5,3,3,5 */
1177 rritype
, /* 3 5,3,3,5 */
1178 rrrtype
, /* 4 5,3,3,3,2 */
1179 rriatype
, /* 5 5,3,3,1,4 */
1180 shifttype
, /* 6 5,3,3,3,2 */
1181 i8type
, /* 7 5,3,8 */
1182 i8movtype
, /* 8 5,3,3,5 */
1183 i8mov32rtype
, /* 9 5,3,5,3 */
1184 i64type
, /* 10 5,3,8 */
1185 ri64type
, /* 11 5,3,3,5 */
1186 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1187 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1188 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1189 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1190 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1191 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1192 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1193 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1194 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1195 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1197 /* I am heaping all the fields of the formats into one structure and
1198 then, only the fields which are involved in instruction extension */
1202 unsigned int regx
; /* Function in i8 type */
1207 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1208 for the bits which make up the immediatate extension. */
1211 extended_offset (unsigned int extension
)
1214 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1216 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1218 value
|= extension
& 0x01f; /* extract 4:0 */
1222 /* Only call this function if you know that this is an extendable
1223 instruction, It wont malfunction, but why make excess remote memory references?
1224 If the immediate operands get sign extended or somthing, do it after
1225 the extension is performed.
1227 /* FIXME: Every one of these cases needs to worry about sign extension
1228 when the offset is to be used in relative addressing */
1232 fetch_mips_16 (CORE_ADDR pc
)
1235 pc
&= 0xfffffffe; /* clear the low order bit */
1236 target_read_memory (pc
, buf
, 2);
1237 return extract_unsigned_integer (buf
, 2);
1241 unpack_mips16 (CORE_ADDR pc
,
1242 unsigned int extension
,
1244 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1249 switch (insn_format
)
1256 value
= extended_offset (extension
);
1257 value
= value
<< 11; /* rom for the original value */
1258 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1262 value
= inst
& 0x7ff;
1263 /* FIXME : Consider sign extension */
1272 { /* A register identifier and an offset */
1273 /* Most of the fields are the same as I type but the
1274 immediate value is of a different length */
1278 value
= extended_offset (extension
);
1279 value
= value
<< 8; /* from the original instruction */
1280 value
|= inst
& 0xff; /* eleven bits from instruction */
1281 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1282 if (value
& 0x4000) /* test the sign bit , bit 26 */
1284 value
&= ~0x3fff; /* remove the sign bit */
1290 value
= inst
& 0xff; /* 8 bits */
1291 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1292 /* FIXME: Do sign extension , this format needs it */
1293 if (value
& 0x80) /* THIS CONFUSES ME */
1295 value
&= 0xef; /* remove the sign bit */
1305 unsigned long value
;
1306 unsigned int nexthalf
;
1307 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1308 value
= value
<< 16;
1309 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1317 internal_error (__FILE__
, __LINE__
, "bad switch");
1319 upk
->offset
= offset
;
1326 add_offset_16 (CORE_ADDR pc
, int offset
)
1328 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1332 extended_mips16_next_pc (CORE_ADDR pc
,
1333 unsigned int extension
, unsigned int insn
)
1335 int op
= (insn
>> 11);
1338 case 2: /* Branch */
1341 struct upk_mips16 upk
;
1342 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1343 offset
= upk
.offset
;
1349 pc
+= (offset
<< 1) + 2;
1352 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1354 struct upk_mips16 upk
;
1355 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1356 pc
= add_offset_16 (pc
, upk
.offset
);
1357 if ((insn
>> 10) & 0x01) /* Exchange mode */
1358 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1365 struct upk_mips16 upk
;
1367 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1368 reg
= read_signed_register (upk
.regx
);
1370 pc
+= (upk
.offset
<< 1) + 2;
1377 struct upk_mips16 upk
;
1379 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1380 reg
= read_signed_register (upk
.regx
);
1382 pc
+= (upk
.offset
<< 1) + 2;
1387 case 12: /* I8 Formats btez btnez */
1389 struct upk_mips16 upk
;
1391 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1392 /* upk.regx contains the opcode */
1393 reg
= read_signed_register (24); /* Test register is 24 */
1394 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1395 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1396 /* pc = add_offset_16(pc,upk.offset) ; */
1397 pc
+= (upk
.offset
<< 1) + 2;
1402 case 29: /* RR Formats JR, JALR, JALR-RA */
1404 struct upk_mips16 upk
;
1405 /* upk.fmt = rrtype; */
1410 upk
.regx
= (insn
>> 8) & 0x07;
1411 upk
.regy
= (insn
>> 5) & 0x07;
1419 break; /* Function return instruction */
1425 break; /* BOGUS Guess */
1427 pc
= read_signed_register (reg
);
1434 /* This is an instruction extension. Fetch the real instruction
1435 (which follows the extension) and decode things based on
1439 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1452 mips16_next_pc (CORE_ADDR pc
)
1454 unsigned int insn
= fetch_mips_16 (pc
);
1455 return extended_mips16_next_pc (pc
, 0, insn
);
1458 /* The mips_next_pc function supports single_step when the remote
1459 target monitor or stub is not developed enough to do a single_step.
1460 It works by decoding the current instruction and predicting where a
1461 branch will go. This isnt hard because all the data is available.
1462 The MIPS32 and MIPS16 variants are quite different */
1464 mips_next_pc (CORE_ADDR pc
)
1467 return mips16_next_pc (pc
);
1469 return mips32_next_pc (pc
);
1472 struct mips_frame_cache
1475 struct trad_frame_saved_reg
*saved_regs
;
1479 static struct mips_frame_cache
*
1480 mips_mdebug_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1482 CORE_ADDR startaddr
= 0;
1483 mips_extra_func_info_t proc_desc
;
1484 struct mips_frame_cache
*cache
;
1485 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
1486 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1487 /* r0 bit means kernel trap */
1489 /* What registers have been saved? Bitmasks. */
1490 unsigned long gen_mask
, float_mask
;
1492 if ((*this_cache
) != NULL
)
1493 return (*this_cache
);
1494 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1495 (*this_cache
) = cache
;
1496 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1498 /* Get the mdebug proc descriptor. */
1499 proc_desc
= non_heuristic_proc_desc (frame_pc_unwind (next_frame
),
1501 /* Must be true. This is only called when the sniffer detected a
1503 gdb_assert (proc_desc
!= NULL
);
1505 /* Extract the frame's base. */
1506 cache
->base
= (frame_unwind_register_signed (next_frame
, NUM_REGS
+ PROC_FRAME_REG (proc_desc
))
1507 + PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1509 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1510 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1511 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1513 /* Must be true. The in_prologue case is left for the heuristic
1514 unwinder. This is always used on kernel traps. */
1515 gdb_assert (!in_prologue (frame_pc_unwind (next_frame
), PROC_LOW_ADDR (proc_desc
))
1518 /* Fill in the offsets for the registers which gen_mask says were
1521 CORE_ADDR reg_position
= (cache
->base
+ PROC_REG_OFFSET (proc_desc
));
1524 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1525 if (gen_mask
& 0x80000000)
1527 cache
->saved_regs
[NUM_REGS
+ ireg
].addr
= reg_position
;
1528 reg_position
-= mips_abi_regsize (gdbarch
);
1532 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse
1533 order of that normally used by gcc. Therefore, we have to fetch
1534 the first instruction of the function, and if it's an entry
1535 instruction that saves $s0 or $s1, correct their saved addresses. */
1536 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1538 ULONGEST inst
= mips16_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1539 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700)
1543 int sreg_count
= (inst
>> 6) & 3;
1545 /* Check if the ra register was pushed on the stack. */
1546 CORE_ADDR reg_position
= (cache
->base
1547 + PROC_REG_OFFSET (proc_desc
));
1549 reg_position
-= mips_abi_regsize (gdbarch
);
1551 /* Check if the s0 and s1 registers were pushed on the
1553 /* NOTE: cagney/2004-02-08: Huh? This is doing no such
1555 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1557 cache
->saved_regs
[NUM_REGS
+ reg
].addr
= reg_position
;
1558 reg_position
-= mips_abi_regsize (gdbarch
);
1563 /* Fill in the offsets for the registers which float_mask says were
1566 CORE_ADDR reg_position
= (cache
->base
1567 + PROC_FREG_OFFSET (proc_desc
));
1569 /* Fill in the offsets for the float registers which float_mask
1571 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1572 if (float_mask
& 0x80000000)
1574 if (mips_abi_regsize (gdbarch
) == 4
1575 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1577 /* On a big endian 32 bit ABI, floating point registers
1578 are paired to form doubles such that the most
1579 significant part is in $f[N+1] and the least
1580 significant in $f[N] vis: $f[N+1] ||| $f[N]. The
1581 registers are also spilled as a pair and stored as a
1584 When little-endian the least significant part is
1585 stored first leading to the memory order $f[N] and
1588 Unfortunately, when big-endian the most significant
1589 part of the double is stored first, and the least
1590 significant is stored second. This leads to the
1591 registers being ordered in memory as firt $f[N+1] and
1594 For the big-endian case make certain that the
1595 addresses point at the correct (swapped) locations
1596 $f[N] and $f[N+1] pair (keep in mind that
1597 reg_position is decremented each time through the
1600 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1601 .addr
= reg_position
- mips_abi_regsize (gdbarch
);
1603 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1604 .addr
= reg_position
+ mips_abi_regsize (gdbarch
);
1607 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+ ireg
]
1608 .addr
= reg_position
;
1609 reg_position
-= mips_abi_regsize (gdbarch
);
1612 cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1613 = cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1616 /* SP_REGNUM, contains the value and not the address. */
1617 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
1619 return (*this_cache
);
1623 mips_mdebug_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1624 struct frame_id
*this_id
)
1626 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1628 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
1632 mips_mdebug_frame_prev_register (struct frame_info
*next_frame
,
1634 int regnum
, int *optimizedp
,
1635 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1636 int *realnump
, void *valuep
)
1638 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1640 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1641 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1644 static const struct frame_unwind mips_mdebug_frame_unwind
=
1647 mips_mdebug_frame_this_id
,
1648 mips_mdebug_frame_prev_register
1651 static const struct frame_unwind
*
1652 mips_mdebug_frame_sniffer (struct frame_info
*next_frame
)
1654 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1655 CORE_ADDR startaddr
= 0;
1656 mips_extra_func_info_t proc_desc
;
1659 /* Only use the mdebug frame unwinder on mdebug frames where all the
1660 registers have been saved. Leave hard cases such as no mdebug or
1661 in prologue for the heuristic unwinders. */
1663 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1664 if (proc_desc
== NULL
)
1667 /* Not sure exactly what kernel_trap means, but if it means the
1668 kernel saves the registers without a prologue doing it, we better
1669 not examine the prologue to see whether registers have been saved
1671 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1673 return &mips_mdebug_frame_unwind
;
1675 /* In any frame other than the innermost or a frame interrupted by a
1676 signal, we assume that all registers have been saved. This
1677 assumes that all register saves in a function happen before the
1678 first function call. */
1679 if (!in_prologue (pc
, PROC_LOW_ADDR (proc_desc
)))
1680 return &mips_mdebug_frame_unwind
;
1686 mips_mdebug_frame_base_address (struct frame_info
*next_frame
,
1689 struct mips_frame_cache
*info
= mips_mdebug_frame_cache (next_frame
,
1694 static const struct frame_base mips_mdebug_frame_base
= {
1695 &mips_mdebug_frame_unwind
,
1696 mips_mdebug_frame_base_address
,
1697 mips_mdebug_frame_base_address
,
1698 mips_mdebug_frame_base_address
1701 static const struct frame_base
*
1702 mips_mdebug_frame_base_sniffer (struct frame_info
*next_frame
)
1704 if (mips_mdebug_frame_sniffer (next_frame
) != NULL
)
1705 return &mips_mdebug_frame_base
;
1710 /* Set a register's saved stack address in temp_saved_regs. If an
1711 address has already been set for this register, do nothing; this
1712 way we will only recognize the first save of a given register in a
1715 For simplicity, save the address in both [0 .. NUM_REGS) and
1716 [NUM_REGS .. 2*NUM_REGS). Strictly speaking, only the second range
1717 is used as it is only second range (the ABI instead of ISA
1718 registers) that comes into play when finding saved registers in a
1722 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1725 if (this_cache
!= NULL
1726 && this_cache
->saved_regs
[regnum
].addr
== -1)
1728 this_cache
->saved_regs
[regnum
+ 0 * NUM_REGS
].addr
= offset
;
1729 this_cache
->saved_regs
[regnum
+ 1 * NUM_REGS
].addr
= offset
;
1734 /* Fetch the immediate value from a MIPS16 instruction.
1735 If the previous instruction was an EXTEND, use it to extend
1736 the upper bits of the immediate value. This is a helper function
1737 for mips16_scan_prologue. */
1740 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1741 unsigned short inst
, /* current instruction */
1742 int nbits
, /* number of bits in imm field */
1743 int scale
, /* scale factor to be applied to imm */
1744 int is_signed
) /* is the imm field signed? */
1748 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1750 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1751 if (offset
& 0x8000) /* check for negative extend */
1752 offset
= 0 - (0x10000 - (offset
& 0xffff));
1753 return offset
| (inst
& 0x1f);
1757 int max_imm
= 1 << nbits
;
1758 int mask
= max_imm
- 1;
1759 int sign_bit
= max_imm
>> 1;
1761 offset
= inst
& mask
;
1762 if (is_signed
&& (offset
& sign_bit
))
1763 offset
= 0 - (max_imm
- offset
);
1764 return offset
* scale
;
1769 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1770 the associated FRAME_CACHE if not null.
1771 Return the address of the first instruction past the prologue. */
1774 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1775 struct frame_info
*next_frame
,
1776 struct mips_frame_cache
*this_cache
)
1779 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1781 long frame_offset
= 0; /* Size of stack frame. */
1782 long frame_adjust
= 0; /* Offset of FP from SP. */
1783 int frame_reg
= MIPS_SP_REGNUM
;
1784 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1785 unsigned inst
= 0; /* current instruction */
1786 unsigned entry_inst
= 0; /* the entry instruction */
1789 int extend_bytes
= 0;
1790 int prev_extend_bytes
;
1791 CORE_ADDR end_prologue_addr
= 0;
1793 /* Can be called when there's no process, and hence when there's no
1795 if (next_frame
!= NULL
)
1796 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
1800 if (limit_pc
> start_pc
+ 200)
1801 limit_pc
= start_pc
+ 200;
1803 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSN_SIZE
)
1805 /* Save the previous instruction. If it's an EXTEND, we'll extract
1806 the immediate offset extension from it in mips16_get_imm. */
1809 /* Fetch and decode the instruction. */
1810 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1812 /* Normally we ignore extend instructions. However, if it is
1813 not followed by a valid prologue instruction, then this
1814 instruction is not part of the prologue either. We must
1815 remember in this case to adjust the end_prologue_addr back
1817 if ((inst
& 0xf800) == 0xf000) /* extend */
1819 extend_bytes
= MIPS16_INSN_SIZE
;
1823 prev_extend_bytes
= extend_bytes
;
1826 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1827 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1829 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1830 if (offset
< 0) /* negative stack adjustment? */
1831 frame_offset
-= offset
;
1833 /* Exit loop if a positive stack adjustment is found, which
1834 usually means that the stack cleanup code in the function
1835 epilogue is reached. */
1838 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1840 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1841 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1842 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1844 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1846 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1847 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1848 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1850 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1852 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1853 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1855 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1857 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1858 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1860 else if (inst
== 0x673d) /* move $s1, $sp */
1865 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1867 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1868 frame_addr
= sp
+ offset
;
1870 frame_adjust
= offset
;
1872 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1874 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1875 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1876 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1878 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1880 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1881 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1882 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1884 else if ((inst
& 0xf81f) == 0xe809
1885 && (inst
& 0x700) != 0x700) /* entry */
1886 entry_inst
= inst
; /* save for later processing */
1887 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1888 cur_pc
+= MIPS16_INSN_SIZE
; /* 32-bit instruction */
1889 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1891 /* This instruction is part of the prologue, but we don't
1892 need to do anything special to handle it. */
1896 /* This instruction is not an instruction typically found
1897 in a prologue, so we must have reached the end of the
1899 if (end_prologue_addr
== 0)
1900 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1904 /* The entry instruction is typically the first instruction in a function,
1905 and it stores registers at offsets relative to the value of the old SP
1906 (before the prologue). But the value of the sp parameter to this
1907 function is the new SP (after the prologue has been executed). So we
1908 can't calculate those offsets until we've seen the entire prologue,
1909 and can calculate what the old SP must have been. */
1910 if (entry_inst
!= 0)
1912 int areg_count
= (entry_inst
>> 8) & 7;
1913 int sreg_count
= (entry_inst
>> 6) & 3;
1915 /* The entry instruction always subtracts 32 from the SP. */
1918 /* Now we can calculate what the SP must have been at the
1919 start of the function prologue. */
1922 /* Check if a0-a3 were saved in the caller's argument save area. */
1923 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1925 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1926 offset
+= mips_abi_regsize (current_gdbarch
);
1929 /* Check if the ra register was pushed on the stack. */
1931 if (entry_inst
& 0x20)
1933 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1934 offset
-= mips_abi_regsize (current_gdbarch
);
1937 /* Check if the s0 and s1 registers were pushed on the stack. */
1938 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1940 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1941 offset
-= mips_abi_regsize (current_gdbarch
);
1945 if (this_cache
!= NULL
)
1948 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
1949 + frame_offset
- frame_adjust
);
1950 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1951 be able to get rid of the assignment below, evetually. But it's
1952 still needed for now. */
1953 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
1954 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
1957 /* If we didn't reach the end of the prologue when scanning the function
1958 instructions, then set end_prologue_addr to the address of the
1959 instruction immediately after the last one we scanned. */
1960 if (end_prologue_addr
== 0)
1961 end_prologue_addr
= cur_pc
;
1963 return end_prologue_addr
;
1966 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1967 Procedures that use the 32-bit instruction set are handled by the
1968 mips_insn32 unwinder. */
1970 static struct mips_frame_cache
*
1971 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1973 struct mips_frame_cache
*cache
;
1975 if ((*this_cache
) != NULL
)
1976 return (*this_cache
);
1977 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1978 (*this_cache
) = cache
;
1979 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1981 /* Analyze the function prologue. */
1983 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1984 CORE_ADDR start_addr
;
1986 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1987 if (start_addr
== 0)
1988 start_addr
= heuristic_proc_start (pc
);
1989 /* We can't analyze the prologue if we couldn't find the begining
1991 if (start_addr
== 0)
1994 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1997 /* SP_REGNUM, contains the value and not the address. */
1998 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2000 return (*this_cache
);
2004 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2005 struct frame_id
*this_id
)
2007 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2009 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2013 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
2015 int regnum
, int *optimizedp
,
2016 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2017 int *realnump
, void *valuep
)
2019 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2021 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2022 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2025 static const struct frame_unwind mips_insn16_frame_unwind
=
2028 mips_insn16_frame_this_id
,
2029 mips_insn16_frame_prev_register
2032 static const struct frame_unwind
*
2033 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
2035 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2036 if (pc_is_mips16 (pc
))
2037 return &mips_insn16_frame_unwind
;
2042 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
2045 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
2050 static const struct frame_base mips_insn16_frame_base
=
2052 &mips_insn16_frame_unwind
,
2053 mips_insn16_frame_base_address
,
2054 mips_insn16_frame_base_address
,
2055 mips_insn16_frame_base_address
2058 static const struct frame_base
*
2059 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
2061 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
2062 return &mips_insn16_frame_base
;
2067 /* Mark all the registers as unset in the saved_regs array
2068 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2071 reset_saved_regs (struct mips_frame_cache
*this_cache
)
2073 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2077 const int num_regs
= NUM_REGS
;
2080 for (i
= 0; i
< num_regs
; i
++)
2082 this_cache
->saved_regs
[i
].addr
= -1;
2087 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2088 the associated FRAME_CACHE if not null.
2089 Return the address of the first instruction past the prologue. */
2092 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2093 struct frame_info
*next_frame
,
2094 struct mips_frame_cache
*this_cache
)
2097 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
2100 int frame_reg
= MIPS_SP_REGNUM
;
2102 CORE_ADDR end_prologue_addr
= 0;
2103 int seen_sp_adjust
= 0;
2104 int load_immediate_bytes
= 0;
2106 /* Can be called when there's no process, and hence when there's no
2108 if (next_frame
!= NULL
)
2109 sp
= read_next_frame_reg (next_frame
, NUM_REGS
+ MIPS_SP_REGNUM
);
2113 if (limit_pc
> start_pc
+ 200)
2114 limit_pc
= start_pc
+ 200;
2119 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS32_INSN_SIZE
)
2121 unsigned long inst
, high_word
, low_word
;
2124 /* Fetch the instruction. */
2125 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
2127 /* Save some code by pre-extracting some useful fields. */
2128 high_word
= (inst
>> 16) & 0xffff;
2129 low_word
= inst
& 0xffff;
2130 reg
= high_word
& 0x1f;
2132 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2133 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2134 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2136 if (low_word
& 0x8000) /* negative stack adjustment? */
2137 frame_offset
+= 0x10000 - low_word
;
2139 /* Exit loop if a positive stack adjustment is found, which
2140 usually means that the stack cleanup code in the function
2141 epilogue is reached. */
2145 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2147 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2149 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2151 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2152 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
2154 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2156 /* Old gcc frame, r30 is virtual frame pointer. */
2157 if ((long) low_word
!= frame_offset
)
2158 frame_addr
= sp
+ low_word
;
2159 else if (frame_reg
== MIPS_SP_REGNUM
)
2161 unsigned alloca_adjust
;
2164 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2165 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2166 if (alloca_adjust
> 0)
2168 /* FP > SP + frame_size. This may be because of
2169 an alloca or somethings similar. Fix sp to
2170 "pre-alloca" value, and try again. */
2171 sp
+= alloca_adjust
;
2172 /* Need to reset the status of all registers. Otherwise,
2173 we will hit a guard that prevents the new address
2174 for each register to be recomputed during the second
2176 reset_saved_regs (this_cache
);
2181 /* move $30,$sp. With different versions of gas this will be either
2182 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2183 Accept any one of these. */
2184 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2186 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2187 if (frame_reg
== MIPS_SP_REGNUM
)
2189 unsigned alloca_adjust
;
2192 frame_addr
= read_next_frame_reg (next_frame
, NUM_REGS
+ 30);
2193 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2194 if (alloca_adjust
> 0)
2196 /* FP > SP + frame_size. This may be because of
2197 an alloca or somethings similar. Fix sp to
2198 "pre-alloca" value, and try again. */
2200 /* Need to reset the status of all registers. Otherwise,
2201 we will hit a guard that prevents the new address
2202 for each register to be recomputed during the second
2204 reset_saved_regs (this_cache
);
2209 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2211 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
2213 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2214 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2215 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2216 || high_word
== 0x3c1c /* lui $gp,n */
2217 || high_word
== 0x279c /* addiu $gp,$gp,n */
2218 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2219 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2222 /* These instructions are part of the prologue, but we don't
2223 need to do anything special to handle them. */
2225 /* The instructions below load $at or $t0 with an immediate
2226 value in preparation for a stack adjustment via
2227 subu $sp,$sp,[$at,$t0]. These instructions could also
2228 initialize a local variable, so we accept them only before
2229 a stack adjustment instruction was seen. */
2230 else if (!seen_sp_adjust
2231 && (high_word
== 0x3c01 /* lui $at,n */
2232 || high_word
== 0x3c08 /* lui $t0,n */
2233 || high_word
== 0x3421 /* ori $at,$at,n */
2234 || high_word
== 0x3508 /* ori $t0,$t0,n */
2235 || high_word
== 0x3401 /* ori $at,$zero,n */
2236 || high_word
== 0x3408 /* ori $t0,$zero,n */
2239 load_immediate_bytes
+= MIPS32_INSN_SIZE
; /* FIXME! */
2243 /* This instruction is not an instruction typically found
2244 in a prologue, so we must have reached the end of the
2246 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2247 loop now? Why would we need to continue scanning the function
2249 if (end_prologue_addr
== 0)
2250 end_prologue_addr
= cur_pc
;
2254 if (this_cache
!= NULL
)
2257 (frame_unwind_register_signed (next_frame
, NUM_REGS
+ frame_reg
)
2259 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2260 this assignment below, eventually. But it's still needed
2262 this_cache
->saved_regs
[NUM_REGS
+ mips_regnum (current_gdbarch
)->pc
]
2263 = this_cache
->saved_regs
[NUM_REGS
+ MIPS_RA_REGNUM
];
2266 /* If we didn't reach the end of the prologue when scanning the function
2267 instructions, then set end_prologue_addr to the address of the
2268 instruction immediately after the last one we scanned. */
2269 /* brobecker/2004-10-10: I don't think this would ever happen, but
2270 we may as well be careful and do our best if we have a null
2271 end_prologue_addr. */
2272 if (end_prologue_addr
== 0)
2273 end_prologue_addr
= cur_pc
;
2275 /* In a frameless function, we might have incorrectly
2276 skipped some load immediate instructions. Undo the skipping
2277 if the load immediate was not followed by a stack adjustment. */
2278 if (load_immediate_bytes
&& !seen_sp_adjust
)
2279 end_prologue_addr
-= load_immediate_bytes
;
2281 return end_prologue_addr
;
2284 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2285 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2286 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2289 static struct mips_frame_cache
*
2290 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2292 struct mips_frame_cache
*cache
;
2294 if ((*this_cache
) != NULL
)
2295 return (*this_cache
);
2297 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2298 (*this_cache
) = cache
;
2299 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2301 /* Analyze the function prologue. */
2303 const CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2304 CORE_ADDR start_addr
;
2306 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2307 if (start_addr
== 0)
2308 start_addr
= heuristic_proc_start (pc
);
2309 /* We can't analyze the prologue if we couldn't find the begining
2311 if (start_addr
== 0)
2314 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2317 /* SP_REGNUM, contains the value and not the address. */
2318 trad_frame_set_value (cache
->saved_regs
, NUM_REGS
+ MIPS_SP_REGNUM
, cache
->base
);
2320 return (*this_cache
);
2324 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2325 struct frame_id
*this_id
)
2327 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2329 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2333 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2335 int regnum
, int *optimizedp
,
2336 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2337 int *realnump
, void *valuep
)
2339 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2341 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2342 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2345 static const struct frame_unwind mips_insn32_frame_unwind
=
2348 mips_insn32_frame_this_id
,
2349 mips_insn32_frame_prev_register
2352 static const struct frame_unwind
*
2353 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2355 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2356 if (! pc_is_mips16 (pc
))
2357 return &mips_insn32_frame_unwind
;
2362 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2365 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2370 static const struct frame_base mips_insn32_frame_base
=
2372 &mips_insn32_frame_unwind
,
2373 mips_insn32_frame_base_address
,
2374 mips_insn32_frame_base_address
,
2375 mips_insn32_frame_base_address
2378 static const struct frame_base
*
2379 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2381 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2382 return &mips_insn32_frame_base
;
2387 static struct trad_frame_cache
*
2388 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2391 CORE_ADDR start_addr
;
2392 CORE_ADDR stack_addr
;
2393 struct trad_frame_cache
*this_trad_cache
;
2395 if ((*this_cache
) != NULL
)
2396 return (*this_cache
);
2397 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2398 (*this_cache
) = this_trad_cache
;
2400 /* The return address is in the link register. */
2401 trad_frame_set_reg_realreg (this_trad_cache
, PC_REGNUM
, MIPS_RA_REGNUM
);
2403 /* Frame ID, since it's a frameless / stackless function, no stack
2404 space is allocated and SP on entry is the current SP. */
2405 pc
= frame_pc_unwind (next_frame
);
2406 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2407 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2408 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2410 /* Assume that the frame's base is the same as the
2412 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2414 return this_trad_cache
;
2418 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2419 struct frame_id
*this_id
)
2421 struct trad_frame_cache
*this_trad_cache
2422 = mips_stub_frame_cache (next_frame
, this_cache
);
2423 trad_frame_get_id (this_trad_cache
, this_id
);
2427 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2429 int regnum
, int *optimizedp
,
2430 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2431 int *realnump
, void *valuep
)
2433 struct trad_frame_cache
*this_trad_cache
2434 = mips_stub_frame_cache (next_frame
, this_cache
);
2435 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2436 lvalp
, addrp
, realnump
, valuep
);
2439 static const struct frame_unwind mips_stub_frame_unwind
=
2442 mips_stub_frame_this_id
,
2443 mips_stub_frame_prev_register
2446 static const struct frame_unwind
*
2447 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2449 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2450 if (in_plt_section (pc
, NULL
))
2451 return &mips_stub_frame_unwind
;
2457 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2460 struct trad_frame_cache
*this_trad_cache
2461 = mips_stub_frame_cache (next_frame
, this_cache
);
2462 return trad_frame_get_this_base (this_trad_cache
);
2465 static const struct frame_base mips_stub_frame_base
=
2467 &mips_stub_frame_unwind
,
2468 mips_stub_frame_base_address
,
2469 mips_stub_frame_base_address
,
2470 mips_stub_frame_base_address
2473 static const struct frame_base
*
2474 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2476 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2477 return &mips_stub_frame_base
;
2483 read_next_frame_reg (struct frame_info
*fi
, int regno
)
2485 /* Always a pseudo. */
2486 gdb_assert (regno
>= NUM_REGS
);
2490 regcache_cooked_read_signed (current_regcache
, regno
, &val
);
2494 return frame_unwind_register_signed (fi
, regno
);
2498 /* mips_addr_bits_remove - remove useless address bits */
2501 mips_addr_bits_remove (CORE_ADDR addr
)
2503 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2504 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2505 /* This hack is a work-around for existing boards using PMON, the
2506 simulator, and any other 64-bit targets that doesn't have true
2507 64-bit addressing. On these targets, the upper 32 bits of
2508 addresses are ignored by the hardware. Thus, the PC or SP are
2509 likely to have been sign extended to all 1s by instruction
2510 sequences that load 32-bit addresses. For example, a typical
2511 piece of code that loads an address is this:
2513 lui $r2, <upper 16 bits>
2514 ori $r2, <lower 16 bits>
2516 But the lui sign-extends the value such that the upper 32 bits
2517 may be all 1s. The workaround is simply to mask off these
2518 bits. In the future, gcc may be changed to support true 64-bit
2519 addressing, and this masking will have to be disabled. */
2520 return addr
&= 0xffffffffUL
;
2525 /* mips_software_single_step() is called just before we want to resume
2526 the inferior, if we want to single-step it but there is no hardware
2527 or kernel single-step support (MIPS on GNU/Linux for example). We find
2528 the target of the coming instruction and breakpoint it.
2530 single_step is also called just after the inferior stops. If we had
2531 set up a simulated single-step, we undo our damage. */
2534 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
2536 static CORE_ADDR next_pc
;
2537 typedef char binsn_quantum
[BREAKPOINT_MAX
];
2538 static binsn_quantum break_mem
;
2541 if (insert_breakpoints_p
)
2543 pc
= read_register (mips_regnum (current_gdbarch
)->pc
);
2544 next_pc
= mips_next_pc (pc
);
2546 target_insert_breakpoint (next_pc
, break_mem
);
2549 target_remove_breakpoint (next_pc
, break_mem
);
2552 static struct mips_extra_func_info temp_proc_desc
;
2554 /* Test whether the PC points to the return instruction at the
2555 end of a function. */
2558 mips_about_to_return (CORE_ADDR pc
)
2560 if (pc_is_mips16 (pc
))
2561 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2562 generates a "jr $ra"; other times it generates code to load
2563 the return address from the stack to an accessible register (such
2564 as $a3), then a "jr" using that register. This second case
2565 is almost impossible to distinguish from an indirect jump
2566 used for switch statements, so we don't even try. */
2567 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2569 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2573 /* This fencepost looks highly suspicious to me. Removing it also
2574 seems suspicious as it could affect remote debugging across serial
2578 heuristic_proc_start (CORE_ADDR pc
)
2585 pc
= ADDR_BITS_REMOVE (pc
);
2587 fence
= start_pc
- heuristic_fence_post
;
2591 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2592 fence
= VM_MIN_ADDRESS
;
2594 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSN_SIZE
: MIPS32_INSN_SIZE
;
2596 /* search back for previous return */
2597 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2598 if (start_pc
< fence
)
2600 /* It's not clear to me why we reach this point when
2601 stop_soon, but with this test, at least we
2602 don't print out warnings for every child forked (eg, on
2603 decstation). 22apr93 rich@cygnus.com. */
2604 if (stop_soon
== NO_STOP_QUIETLY
)
2606 static int blurb_printed
= 0;
2608 warning ("GDB can't find the start of the function at 0x%s.",
2613 /* This actually happens frequently in embedded
2614 development, when you first connect to a board
2615 and your stack pointer and pc are nowhere in
2616 particular. This message needs to give people
2617 in that situation enough information to
2618 determine that it's no big deal. */
2619 printf_filtered ("\n\
2620 GDB is unable to find the start of the function at 0x%s\n\
2621 and thus can't determine the size of that function's stack frame.\n\
2622 This means that GDB may be unable to access that stack frame, or\n\
2623 the frames below it.\n\
2624 This problem is most likely caused by an invalid program counter or\n\
2626 However, if you think GDB should simply search farther back\n\
2627 from 0x%s for code which looks like the beginning of a\n\
2628 function, you can increase the range of the search using the `set\n\
2629 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2636 else if (pc_is_mips16 (start_pc
))
2638 unsigned short inst
;
2640 /* On MIPS16, any one of the following is likely to be the
2641 start of a function:
2645 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2646 inst
= mips_fetch_instruction (start_pc
);
2647 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
2648 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2649 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2650 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2652 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2653 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2658 else if (mips_about_to_return (start_pc
))
2660 /* Skip return and its delay slot. */
2661 start_pc
+= 2 * MIPS32_INSN_SIZE
;
2668 static mips_extra_func_info_t
2669 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2670 struct frame_info
*next_frame
,
2671 struct mips_frame_cache
*this_cache
)
2676 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2677 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2678 PROC_FRAME_REG (&temp_proc_desc
) = MIPS_SP_REGNUM
;
2679 PROC_PC_REG (&temp_proc_desc
) = MIPS_RA_REGNUM
;
2681 if (pc_is_mips16 (start_pc
))
2682 mips16_scan_prologue (start_pc
, limit_pc
, next_frame
, this_cache
);
2684 mips32_scan_prologue (start_pc
, limit_pc
, next_frame
, this_cache
);
2686 return &temp_proc_desc
;
2689 struct mips_objfile_private
2695 /* Global used to communicate between non_heuristic_proc_desc and
2696 compare_pdr_entries within qsort (). */
2697 static bfd
*the_bfd
;
2700 compare_pdr_entries (const void *a
, const void *b
)
2702 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2703 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2707 else if (lhs
== rhs
)
2713 static mips_extra_func_info_t
2714 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2716 CORE_ADDR startaddr
;
2717 mips_extra_func_info_t proc_desc
;
2718 struct block
*b
= block_for_pc (pc
);
2720 struct obj_section
*sec
;
2721 struct mips_objfile_private
*priv
;
2723 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2725 *addrptr
= startaddr
;
2729 sec
= find_pc_section (pc
);
2732 priv
= (struct mips_objfile_private
*) objfile_data (sec
->objfile
, mips_pdr_data
);
2734 /* Search the ".pdr" section generated by GAS. This includes most of
2735 the information normally found in ECOFF PDRs. */
2737 the_bfd
= sec
->objfile
->obfd
;
2739 && (the_bfd
->format
== bfd_object
2740 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2741 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2743 /* Right now GAS only outputs the address as a four-byte sequence.
2744 This means that we should not bother with this method on 64-bit
2745 targets (until that is fixed). */
2747 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2748 sizeof (struct mips_objfile_private
));
2750 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2752 else if (priv
== NULL
)
2756 priv
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2757 sizeof (struct mips_objfile_private
));
2759 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2762 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2763 priv
->contents
= obstack_alloc (&sec
->objfile
->objfile_obstack
,
2765 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2766 priv
->contents
, 0, priv
->size
);
2768 /* In general, the .pdr section is sorted. However, in the
2769 presence of multiple code sections (and other corner cases)
2770 it can become unsorted. Sort it so that we can use a faster
2772 qsort (priv
->contents
, priv
->size
/ 32, 32,
2773 compare_pdr_entries
);
2778 set_objfile_data (sec
->objfile
, mips_pdr_data
, priv
);
2782 if (priv
->size
!= 0)
2789 high
= priv
->size
/ 32;
2791 /* We've found a .pdr section describing this objfile. We want to
2792 find the entry which describes this code address. The .pdr
2793 information is not very descriptive; we have only a function
2794 start address. We have to look for the closest entry, because
2795 the local symbol at the beginning of this function may have
2796 been stripped - so if we ask the symbol table for the start
2797 address we may get a preceding global function. */
2799 /* First, find the last .pdr entry starting at or before PC. */
2802 mid
= (low
+ high
) / 2;
2804 ptr
= priv
->contents
+ mid
* 32;
2805 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2806 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2807 SECT_OFF_TEXT (sec
->objfile
));
2814 while (low
!= high
);
2816 /* Both low and high point one past the PDR of interest. If
2817 both are zero, that means this PC is before any region
2818 covered by a PDR, i.e. pdr_pc for the first PDR entry is
2822 ptr
= priv
->contents
+ (low
- 1) * 32;
2823 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2824 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2825 SECT_OFF_TEXT (sec
->objfile
));
2828 /* We don't have a range, so we have no way to know for sure
2829 whether we're in the correct PDR or a PDR for a preceding
2830 function and the current function was a stripped local
2831 symbol. But if the PDR's PC is at least as great as the
2832 best guess from the symbol table, assume that it does cover
2833 the right area; if a .pdr section is present at all then
2834 nearly every function will have an entry. The biggest exception
2835 will be the dynamic linker stubs; conveniently these are
2836 placed before .text instead of after. */
2838 if (pc
>= pdr_pc
&& pdr_pc
>= startaddr
)
2840 struct symbol
*sym
= find_pc_function (pc
);
2845 /* Fill in what we need of the proc_desc. */
2846 proc_desc
= (mips_extra_func_info_t
)
2847 obstack_alloc (&sec
->objfile
->objfile_obstack
,
2848 sizeof (struct mips_extra_func_info
));
2849 PROC_LOW_ADDR (proc_desc
) = pdr_pc
;
2851 /* Only used for dummy frames. */
2852 PROC_HIGH_ADDR (proc_desc
) = 0;
2854 PROC_FRAME_OFFSET (proc_desc
)
2855 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2856 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2858 PROC_FRAME_ADJUST (proc_desc
) = 0;
2859 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2861 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2863 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2865 PROC_FREG_OFFSET (proc_desc
)
2866 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2867 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2869 proc_desc
->pdr
.isym
= (long) sym
;
2879 if (startaddr
> BLOCK_START (b
))
2881 /* This is the "pathological" case referred to in a comment in
2882 print_frame_info. It might be better to move this check into
2887 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_DOMAIN
, 0, NULL
);
2889 /* If we never found a PDR for this function in symbol reading, then
2890 examine prologues to find the information. */
2893 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2894 if (PROC_FRAME_REG (proc_desc
) == -1)
2903 /* MIPS stack frames are almost impenetrable. When execution stops,
2904 we basically have to look at symbol information for the function
2905 that we stopped in, which tells us *which* register (if any) is
2906 the base of the frame pointer, and what offset from that register
2907 the frame itself is at.
2909 This presents a problem when trying to examine a stack in memory
2910 (that isn't executing at the moment), using the "frame" command. We
2911 don't have a PC, nor do we have any registers except SP.
2913 This routine takes two arguments, SP and PC, and tries to make the
2914 cached frames look as if these two arguments defined a frame on the
2915 cache. This allows the rest of info frame to extract the important
2916 arguments without difficulty. */
2919 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2922 error ("MIPS frame specifications require two arguments: sp and pc");
2924 return create_new_frame (argv
[0], argv
[1]);
2927 /* According to the current ABI, should the type be passed in a
2928 floating-point register (assuming that there is space)? When there
2929 is no FPU, FP are not even considered as possibile candidates for
2930 FP registers and, consequently this returns false - forces FP
2931 arguments into integer registers. */
2934 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2936 return ((typecode
== TYPE_CODE_FLT
2938 && (typecode
== TYPE_CODE_STRUCT
2939 || typecode
== TYPE_CODE_UNION
)
2940 && TYPE_NFIELDS (arg_type
) == 1
2941 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2942 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2945 /* On o32, argument passing in GPRs depends on the alignment of the type being
2946 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2949 mips_type_needs_double_align (struct type
*type
)
2951 enum type_code typecode
= TYPE_CODE (type
);
2953 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2955 else if (typecode
== TYPE_CODE_STRUCT
)
2957 if (TYPE_NFIELDS (type
) < 1)
2959 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2961 else if (typecode
== TYPE_CODE_UNION
)
2965 n
= TYPE_NFIELDS (type
);
2966 for (i
= 0; i
< n
; i
++)
2967 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2974 /* Adjust the address downward (direction of stack growth) so that it
2975 is correctly aligned for a new stack frame. */
2977 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2979 return align_down (addr
, 16);
2983 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2984 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2985 int nargs
, struct value
**args
, CORE_ADDR sp
,
2986 int struct_return
, CORE_ADDR struct_addr
)
2992 int stack_offset
= 0;
2993 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2994 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2996 /* For shared libraries, "t9" needs to point at the function
2998 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3000 /* Set the return address register to point to the entry point of
3001 the program, where a breakpoint lies in wait. */
3002 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3004 /* First ensure that the stack and structure return address (if any)
3005 are properly aligned. The stack has to be at least 64-bit
3006 aligned even on 32-bit machines, because doubles must be 64-bit
3007 aligned. For n32 and n64, stack frames need to be 128-bit
3008 aligned, so we round to this widest known alignment. */
3010 sp
= align_down (sp
, 16);
3011 struct_addr
= align_down (struct_addr
, 16);
3013 /* Now make space on the stack for the args. We allocate more
3014 than necessary for EABI, because the first few arguments are
3015 passed in registers, but that's OK. */
3016 for (argnum
= 0; argnum
< nargs
; argnum
++)
3017 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3018 mips_stack_argsize (gdbarch
));
3019 sp
-= align_up (len
, 16);
3022 fprintf_unfiltered (gdb_stdlog
,
3023 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
3024 paddr_nz (sp
), (long) align_up (len
, 16));
3026 /* Initialize the integer and float register pointers. */
3027 argreg
= MIPS_A0_REGNUM
;
3028 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3030 /* The struct_return pointer occupies the first parameter-passing reg. */
3034 fprintf_unfiltered (gdb_stdlog
,
3035 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
3036 argreg
, paddr_nz (struct_addr
));
3037 write_register (argreg
++, struct_addr
);
3040 /* Now load as many as possible of the first arguments into
3041 registers, and push the rest onto the stack. Loop thru args
3042 from first to last. */
3043 for (argnum
= 0; argnum
< nargs
; argnum
++)
3046 char valbuf
[MAX_REGISTER_SIZE
];
3047 struct value
*arg
= args
[argnum
];
3048 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3049 int len
= TYPE_LENGTH (arg_type
);
3050 enum type_code typecode
= TYPE_CODE (arg_type
);
3053 fprintf_unfiltered (gdb_stdlog
,
3054 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3055 argnum
+ 1, len
, (int) typecode
);
3057 /* The EABI passes structures that do not fit in a register by
3059 if (len
> mips_abi_regsize (gdbarch
)
3060 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3062 store_unsigned_integer (valbuf
, mips_abi_regsize (gdbarch
),
3063 VALUE_ADDRESS (arg
));
3064 typecode
= TYPE_CODE_PTR
;
3065 len
= mips_abi_regsize (gdbarch
);
3068 fprintf_unfiltered (gdb_stdlog
, " push");
3071 val
= (char *) VALUE_CONTENTS (arg
);
3073 /* 32-bit ABIs always start floating point arguments in an
3074 even-numbered floating point register. Round the FP register
3075 up before the check to see if there are any FP registers
3076 left. Non MIPS_EABI targets also pass the FP in the integer
3077 registers so also round up normal registers. */
3078 if (mips_abi_regsize (gdbarch
) < 8
3079 && fp_register_arg_p (typecode
, arg_type
))
3081 if ((float_argreg
& 1))
3085 /* Floating point arguments passed in registers have to be
3086 treated specially. On 32-bit architectures, doubles
3087 are passed in register pairs; the even register gets
3088 the low word, and the odd register gets the high word.
3089 On non-EABI processors, the first two floating point arguments are
3090 also copied to general registers, because MIPS16 functions
3091 don't use float registers for arguments. This duplication of
3092 arguments in general registers can't hurt non-MIPS16 functions
3093 because those registers are normally skipped. */
3094 /* MIPS_EABI squeezes a struct that contains a single floating
3095 point value into an FP register instead of pushing it onto the
3097 if (fp_register_arg_p (typecode
, arg_type
)
3098 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3100 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3102 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3103 unsigned long regval
;
3105 /* Write the low word of the double to the even register(s). */
3106 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3108 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3109 float_argreg
, phex (regval
, 4));
3110 write_register (float_argreg
++, regval
);
3112 /* Write the high word of the double to the odd register(s). */
3113 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3115 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3116 float_argreg
, phex (regval
, 4));
3117 write_register (float_argreg
++, regval
);
3121 /* This is a floating point value that fits entirely
3122 in a single register. */
3123 /* On 32 bit ABI's the float_argreg is further adjusted
3124 above to ensure that it is even register aligned. */
3125 LONGEST regval
= extract_unsigned_integer (val
, len
);
3127 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3128 float_argreg
, phex (regval
, len
));
3129 write_register (float_argreg
++, regval
);
3134 /* Copy the argument to general registers or the stack in
3135 register-sized pieces. Large arguments are split between
3136 registers and stack. */
3137 /* Note: structs whose size is not a multiple of
3138 mips_abi_regsize() are treated specially: Irix cc passes
3139 them in registers where gcc sometimes puts them on the
3140 stack. For maximum compatibility, we will put them in
3142 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3143 && (len
% mips_abi_regsize (gdbarch
) != 0));
3145 /* Note: Floating-point values that didn't fit into an FP
3146 register are only written to memory. */
3149 /* Remember if the argument was written to the stack. */
3150 int stack_used_p
= 0;
3151 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3152 ? len
: mips_abi_regsize (gdbarch
));
3155 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3158 /* Write this portion of the argument to the stack. */
3159 if (argreg
> MIPS_LAST_ARG_REGNUM
3161 || fp_register_arg_p (typecode
, arg_type
))
3163 /* Should shorter than int integer values be
3164 promoted to int before being stored? */
3165 int longword_offset
= 0;
3168 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3170 if (mips_stack_argsize (gdbarch
) == 8
3171 && (typecode
== TYPE_CODE_INT
3172 || typecode
== TYPE_CODE_PTR
3173 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3174 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3175 else if ((typecode
== TYPE_CODE_STRUCT
3176 || typecode
== TYPE_CODE_UNION
)
3177 && (TYPE_LENGTH (arg_type
)
3178 < mips_stack_argsize (gdbarch
)))
3179 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3184 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3185 paddr_nz (stack_offset
));
3186 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3187 paddr_nz (longword_offset
));
3190 addr
= sp
+ stack_offset
+ longword_offset
;
3195 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3197 for (i
= 0; i
< partial_len
; i
++)
3199 fprintf_unfiltered (gdb_stdlog
, "%02x",
3203 write_memory (addr
, val
, partial_len
);
3206 /* Note!!! This is NOT an else clause. Odd sized
3207 structs may go thru BOTH paths. Floating point
3208 arguments will not. */
3209 /* Write this portion of the argument to a general
3210 purpose register. */
3211 if (argreg
<= MIPS_LAST_ARG_REGNUM
3212 && !fp_register_arg_p (typecode
, arg_type
))
3215 extract_unsigned_integer (val
, partial_len
);
3218 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3221 mips_abi_regsize (gdbarch
)));
3222 write_register (argreg
, regval
);
3229 /* Compute the the offset into the stack at which we
3230 will copy the next parameter.
3232 In the new EABI (and the NABI32), the stack_offset
3233 only needs to be adjusted when it has been used. */
3236 stack_offset
+= align_up (partial_len
,
3237 mips_stack_argsize (gdbarch
));
3241 fprintf_unfiltered (gdb_stdlog
, "\n");
3244 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3246 /* Return adjusted stack pointer. */
3250 /* Determin the return value convention being used. */
3252 static enum return_value_convention
3253 mips_eabi_return_value (struct gdbarch
*gdbarch
,
3254 struct type
*type
, struct regcache
*regcache
,
3255 void *readbuf
, const void *writebuf
)
3257 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3258 return RETURN_VALUE_STRUCT_CONVENTION
;
3260 memset (readbuf
, 0, TYPE_LENGTH (type
));
3261 return RETURN_VALUE_REGISTER_CONVENTION
;
3265 /* N32/N64 ABI stuff. */
3268 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3269 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3270 int nargs
, struct value
**args
, CORE_ADDR sp
,
3271 int struct_return
, CORE_ADDR struct_addr
)
3277 int stack_offset
= 0;
3278 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3279 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3281 /* For shared libraries, "t9" needs to point at the function
3283 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3285 /* Set the return address register to point to the entry point of
3286 the program, where a breakpoint lies in wait. */
3287 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3289 /* First ensure that the stack and structure return address (if any)
3290 are properly aligned. The stack has to be at least 64-bit
3291 aligned even on 32-bit machines, because doubles must be 64-bit
3292 aligned. For n32 and n64, stack frames need to be 128-bit
3293 aligned, so we round to this widest known alignment. */
3295 sp
= align_down (sp
, 16);
3296 struct_addr
= align_down (struct_addr
, 16);
3298 /* Now make space on the stack for the args. */
3299 for (argnum
= 0; argnum
< nargs
; argnum
++)
3300 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3301 mips_stack_argsize (gdbarch
));
3302 sp
-= align_up (len
, 16);
3305 fprintf_unfiltered (gdb_stdlog
,
3306 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3307 paddr_nz (sp
), (long) align_up (len
, 16));
3309 /* Initialize the integer and float register pointers. */
3310 argreg
= MIPS_A0_REGNUM
;
3311 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3313 /* The struct_return pointer occupies the first parameter-passing reg. */
3317 fprintf_unfiltered (gdb_stdlog
,
3318 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3319 argreg
, paddr_nz (struct_addr
));
3320 write_register (argreg
++, struct_addr
);
3323 /* Now load as many as possible of the first arguments into
3324 registers, and push the rest onto the stack. Loop thru args
3325 from first to last. */
3326 for (argnum
= 0; argnum
< nargs
; argnum
++)
3329 struct value
*arg
= args
[argnum
];
3330 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3331 int len
= TYPE_LENGTH (arg_type
);
3332 enum type_code typecode
= TYPE_CODE (arg_type
);
3335 fprintf_unfiltered (gdb_stdlog
,
3336 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3337 argnum
+ 1, len
, (int) typecode
);
3339 val
= (char *) VALUE_CONTENTS (arg
);
3341 if (fp_register_arg_p (typecode
, arg_type
)
3342 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3344 /* This is a floating point value that fits entirely
3345 in a single register. */
3346 /* On 32 bit ABI's the float_argreg is further adjusted
3347 above to ensure that it is even register aligned. */
3348 LONGEST regval
= extract_unsigned_integer (val
, len
);
3350 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3351 float_argreg
, phex (regval
, len
));
3352 write_register (float_argreg
++, regval
);
3355 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3356 argreg
, phex (regval
, len
));
3357 write_register (argreg
, regval
);
3362 /* Copy the argument to general registers or the stack in
3363 register-sized pieces. Large arguments are split between
3364 registers and stack. */
3365 /* Note: structs whose size is not a multiple of
3366 mips_abi_regsize() are treated specially: Irix cc passes
3367 them in registers where gcc sometimes puts them on the
3368 stack. For maximum compatibility, we will put them in
3370 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3371 && (len
% mips_abi_regsize (gdbarch
) != 0));
3372 /* Note: Floating-point values that didn't fit into an FP
3373 register are only written to memory. */
3376 /* Rememer if the argument was written to the stack. */
3377 int stack_used_p
= 0;
3378 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3379 ? len
: mips_abi_regsize (gdbarch
));
3382 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3385 /* Write this portion of the argument to the stack. */
3386 if (argreg
> MIPS_LAST_ARG_REGNUM
3388 || fp_register_arg_p (typecode
, arg_type
))
3390 /* Should shorter than int integer values be
3391 promoted to int before being stored? */
3392 int longword_offset
= 0;
3395 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3397 if (mips_stack_argsize (gdbarch
) == 8
3398 && (typecode
== TYPE_CODE_INT
3399 || typecode
== TYPE_CODE_PTR
3400 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3401 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3406 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3407 paddr_nz (stack_offset
));
3408 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3409 paddr_nz (longword_offset
));
3412 addr
= sp
+ stack_offset
+ longword_offset
;
3417 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3419 for (i
= 0; i
< partial_len
; i
++)
3421 fprintf_unfiltered (gdb_stdlog
, "%02x",
3425 write_memory (addr
, val
, partial_len
);
3428 /* Note!!! This is NOT an else clause. Odd sized
3429 structs may go thru BOTH paths. Floating point
3430 arguments will not. */
3431 /* Write this portion of the argument to a general
3432 purpose register. */
3433 if (argreg
<= MIPS_LAST_ARG_REGNUM
3434 && !fp_register_arg_p (typecode
, arg_type
))
3437 extract_unsigned_integer (val
, partial_len
);
3439 /* A non-floating-point argument being passed in a
3440 general register. If a struct or union, and if
3441 the remaining length is smaller than the register
3442 size, we have to adjust the register value on
3445 It does not seem to be necessary to do the
3446 same for integral types.
3448 cagney/2001-07-23: gdb/179: Also, GCC, when
3449 outputting LE O32 with sizeof (struct) <
3450 mips_abi_regsize(), generates a left shift as
3451 part of storing the argument in a register a
3452 register (the left shift isn't generated when
3453 sizeof (struct) >= mips_abi_regsize()). Since
3454 it is quite possible that this is GCC
3455 contradicting the LE/O32 ABI, GDB has not been
3456 adjusted to accommodate this. Either someone
3457 needs to demonstrate that the LE/O32 ABI
3458 specifies such a left shift OR this new ABI gets
3459 identified as such and GDB gets tweaked
3462 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3463 && partial_len
< mips_abi_regsize (gdbarch
)
3464 && (typecode
== TYPE_CODE_STRUCT
||
3465 typecode
== TYPE_CODE_UNION
))
3466 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3470 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3473 mips_abi_regsize (gdbarch
)));
3474 write_register (argreg
, regval
);
3481 /* Compute the the offset into the stack at which we
3482 will copy the next parameter.
3484 In N32 (N64?), the stack_offset only needs to be
3485 adjusted when it has been used. */
3488 stack_offset
+= align_up (partial_len
,
3489 mips_stack_argsize (gdbarch
));
3493 fprintf_unfiltered (gdb_stdlog
, "\n");
3496 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3498 /* Return adjusted stack pointer. */
3502 static enum return_value_convention
3503 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3504 struct type
*type
, struct regcache
*regcache
,
3505 void *readbuf
, const void *writebuf
)
3507 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3508 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3509 || TYPE_CODE (type
) == TYPE_CODE_UNION
3510 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
3511 || TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3512 return RETURN_VALUE_STRUCT_CONVENTION
;
3513 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3514 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3516 /* A floating-point value belongs in the least significant part
3519 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3520 mips_xfer_register (regcache
,
3521 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3523 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3524 return RETURN_VALUE_REGISTER_CONVENTION
;
3526 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3527 && TYPE_NFIELDS (type
) <= 2
3528 && TYPE_NFIELDS (type
) >= 1
3529 && ((TYPE_NFIELDS (type
) == 1
3530 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3532 || (TYPE_NFIELDS (type
) == 2
3533 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3535 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3537 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3539 /* A struct that contains one or two floats. Each value is part
3540 in the least significant part of their floating point
3544 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3545 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3547 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3550 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3552 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
3553 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3554 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3556 return RETURN_VALUE_REGISTER_CONVENTION
;
3558 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3559 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3561 /* A structure or union. Extract the left justified value,
3562 regardless of the byte order. I.e. DO NOT USE
3566 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3567 offset
< TYPE_LENGTH (type
);
3568 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3570 int xfer
= register_size (current_gdbarch
, regnum
);
3571 if (offset
+ xfer
> TYPE_LENGTH (type
))
3572 xfer
= TYPE_LENGTH (type
) - offset
;
3574 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3575 offset
, xfer
, regnum
);
3576 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3577 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3579 return RETURN_VALUE_REGISTER_CONVENTION
;
3583 /* A scalar extract each part but least-significant-byte
3587 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3588 offset
< TYPE_LENGTH (type
);
3589 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3591 int xfer
= register_size (current_gdbarch
, regnum
);
3592 if (offset
+ xfer
> TYPE_LENGTH (type
))
3593 xfer
= TYPE_LENGTH (type
) - offset
;
3595 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3596 offset
, xfer
, regnum
);
3597 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
3598 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
3600 return RETURN_VALUE_REGISTER_CONVENTION
;
3604 /* O32 ABI stuff. */
3607 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3608 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3609 int nargs
, struct value
**args
, CORE_ADDR sp
,
3610 int struct_return
, CORE_ADDR struct_addr
)
3616 int stack_offset
= 0;
3617 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3618 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3620 /* For shared libraries, "t9" needs to point at the function
3622 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3624 /* Set the return address register to point to the entry point of
3625 the program, where a breakpoint lies in wait. */
3626 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3628 /* First ensure that the stack and structure return address (if any)
3629 are properly aligned. The stack has to be at least 64-bit
3630 aligned even on 32-bit machines, because doubles must be 64-bit
3631 aligned. For n32 and n64, stack frames need to be 128-bit
3632 aligned, so we round to this widest known alignment. */
3634 sp
= align_down (sp
, 16);
3635 struct_addr
= align_down (struct_addr
, 16);
3637 /* Now make space on the stack for the args. */
3638 for (argnum
= 0; argnum
< nargs
; argnum
++)
3639 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3640 mips_stack_argsize (gdbarch
));
3641 sp
-= align_up (len
, 16);
3644 fprintf_unfiltered (gdb_stdlog
,
3645 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3646 paddr_nz (sp
), (long) align_up (len
, 16));
3648 /* Initialize the integer and float register pointers. */
3649 argreg
= MIPS_A0_REGNUM
;
3650 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3652 /* The struct_return pointer occupies the first parameter-passing reg. */
3656 fprintf_unfiltered (gdb_stdlog
,
3657 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3658 argreg
, paddr_nz (struct_addr
));
3659 write_register (argreg
++, struct_addr
);
3660 stack_offset
+= mips_stack_argsize (gdbarch
);
3663 /* Now load as many as possible of the first arguments into
3664 registers, and push the rest onto the stack. Loop thru args
3665 from first to last. */
3666 for (argnum
= 0; argnum
< nargs
; argnum
++)
3669 struct value
*arg
= args
[argnum
];
3670 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3671 int len
= TYPE_LENGTH (arg_type
);
3672 enum type_code typecode
= TYPE_CODE (arg_type
);
3675 fprintf_unfiltered (gdb_stdlog
,
3676 "mips_o32_push_dummy_call: %d len=%d type=%d",
3677 argnum
+ 1, len
, (int) typecode
);
3679 val
= (char *) VALUE_CONTENTS (arg
);
3681 /* 32-bit ABIs always start floating point arguments in an
3682 even-numbered floating point register. Round the FP register
3683 up before the check to see if there are any FP registers
3684 left. O32/O64 targets also pass the FP in the integer
3685 registers so also round up normal registers. */
3686 if (mips_abi_regsize (gdbarch
) < 8
3687 && fp_register_arg_p (typecode
, arg_type
))
3689 if ((float_argreg
& 1))
3693 /* Floating point arguments passed in registers have to be
3694 treated specially. On 32-bit architectures, doubles
3695 are passed in register pairs; the even register gets
3696 the low word, and the odd register gets the high word.
3697 On O32/O64, the first two floating point arguments are
3698 also copied to general registers, because MIPS16 functions
3699 don't use float registers for arguments. This duplication of
3700 arguments in general registers can't hurt non-MIPS16 functions
3701 because those registers are normally skipped. */
3703 if (fp_register_arg_p (typecode
, arg_type
)
3704 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3706 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
3708 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3709 unsigned long regval
;
3711 /* Write the low word of the double to the even register(s). */
3712 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3714 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3715 float_argreg
, phex (regval
, 4));
3716 write_register (float_argreg
++, regval
);
3718 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3719 argreg
, phex (regval
, 4));
3720 write_register (argreg
++, regval
);
3722 /* Write the high word of the double to the odd register(s). */
3723 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3725 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3726 float_argreg
, phex (regval
, 4));
3727 write_register (float_argreg
++, regval
);
3730 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3731 argreg
, phex (regval
, 4));
3732 write_register (argreg
++, regval
);
3736 /* This is a floating point value that fits entirely
3737 in a single register. */
3738 /* On 32 bit ABI's the float_argreg is further adjusted
3739 above to ensure that it is even register aligned. */
3740 LONGEST regval
= extract_unsigned_integer (val
, len
);
3742 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3743 float_argreg
, phex (regval
, len
));
3744 write_register (float_argreg
++, regval
);
3745 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3746 registers for each argument. The below is (my
3747 guess) to ensure that the corresponding integer
3748 register has reserved the same space. */
3750 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3751 argreg
, phex (regval
, len
));
3752 write_register (argreg
, regval
);
3753 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
3755 /* Reserve space for the FP register. */
3756 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
3760 /* Copy the argument to general registers or the stack in
3761 register-sized pieces. Large arguments are split between
3762 registers and stack. */
3763 /* Note: structs whose size is not a multiple of
3764 mips_abi_regsize() are treated specially: Irix cc passes
3765 them in registers where gcc sometimes puts them on the
3766 stack. For maximum compatibility, we will put them in
3768 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
3769 && (len
% mips_abi_regsize (gdbarch
) != 0));
3770 /* Structures should be aligned to eight bytes (even arg registers)
3771 on MIPS_ABI_O32, if their first member has double precision. */
3772 if (mips_abi_regsize (gdbarch
) < 8
3773 && mips_type_needs_double_align (arg_type
))
3778 /* Note: Floating-point values that didn't fit into an FP
3779 register are only written to memory. */
3782 /* Remember if the argument was written to the stack. */
3783 int stack_used_p
= 0;
3784 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
3785 ? len
: mips_abi_regsize (gdbarch
));
3788 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3791 /* Write this portion of the argument to the stack. */
3792 if (argreg
> MIPS_LAST_ARG_REGNUM
3794 || fp_register_arg_p (typecode
, arg_type
))
3796 /* Should shorter than int integer values be
3797 promoted to int before being stored? */
3798 int longword_offset
= 0;
3801 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3803 if (mips_stack_argsize (gdbarch
) == 8
3804 && (typecode
== TYPE_CODE_INT
3805 || typecode
== TYPE_CODE_PTR
3806 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3807 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
3812 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3813 paddr_nz (stack_offset
));
3814 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3815 paddr_nz (longword_offset
));
3818 addr
= sp
+ stack_offset
+ longword_offset
;
3823 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3825 for (i
= 0; i
< partial_len
; i
++)
3827 fprintf_unfiltered (gdb_stdlog
, "%02x",
3831 write_memory (addr
, val
, partial_len
);
3834 /* Note!!! This is NOT an else clause. Odd sized
3835 structs may go thru BOTH paths. Floating point
3836 arguments will not. */
3837 /* Write this portion of the argument to a general
3838 purpose register. */
3839 if (argreg
<= MIPS_LAST_ARG_REGNUM
3840 && !fp_register_arg_p (typecode
, arg_type
))
3842 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3843 /* Value may need to be sign extended, because
3844 mips_isa_regsize() != mips_abi_regsize(). */
3846 /* A non-floating-point argument being passed in a
3847 general register. If a struct or union, and if
3848 the remaining length is smaller than the register
3849 size, we have to adjust the register value on
3852 It does not seem to be necessary to do the
3853 same for integral types.
3855 Also don't do this adjustment on O64 binaries.
3857 cagney/2001-07-23: gdb/179: Also, GCC, when
3858 outputting LE O32 with sizeof (struct) <
3859 mips_abi_regsize(), generates a left shift as
3860 part of storing the argument in a register a
3861 register (the left shift isn't generated when
3862 sizeof (struct) >= mips_abi_regsize()). Since
3863 it is quite possible that this is GCC
3864 contradicting the LE/O32 ABI, GDB has not been
3865 adjusted to accommodate this. Either someone
3866 needs to demonstrate that the LE/O32 ABI
3867 specifies such a left shift OR this new ABI gets
3868 identified as such and GDB gets tweaked
3871 if (mips_abi_regsize (gdbarch
) < 8
3872 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3873 && partial_len
< mips_abi_regsize (gdbarch
)
3874 && (typecode
== TYPE_CODE_STRUCT
||
3875 typecode
== TYPE_CODE_UNION
))
3876 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
3880 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3883 mips_abi_regsize (gdbarch
)));
3884 write_register (argreg
, regval
);
3887 /* Prevent subsequent floating point arguments from
3888 being passed in floating point registers. */
3889 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3895 /* Compute the the offset into the stack at which we
3896 will copy the next parameter.
3898 In older ABIs, the caller reserved space for
3899 registers that contained arguments. This was loosely
3900 refered to as their "home". Consequently, space is
3901 always allocated. */
3903 stack_offset
+= align_up (partial_len
,
3904 mips_stack_argsize (gdbarch
));
3908 fprintf_unfiltered (gdb_stdlog
, "\n");
3911 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3913 /* Return adjusted stack pointer. */
3917 static enum return_value_convention
3918 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3919 struct regcache
*regcache
,
3920 void *readbuf
, const void *writebuf
)
3922 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3924 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3925 || TYPE_CODE (type
) == TYPE_CODE_UNION
3926 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3927 return RETURN_VALUE_STRUCT_CONVENTION
;
3928 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3929 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3931 /* A single-precision floating-point value. It fits in the
3932 least significant part of FP0. */
3934 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3935 mips_xfer_register (regcache
,
3936 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
,
3938 TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3939 return RETURN_VALUE_REGISTER_CONVENTION
;
3941 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3942 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3944 /* A double-precision floating-point value. The most
3945 significant part goes in FP1, and the least significant in
3948 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3949 switch (TARGET_BYTE_ORDER
)
3951 case BFD_ENDIAN_LITTLE
:
3952 mips_xfer_register (regcache
,
3953 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3954 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3955 mips_xfer_register (regcache
,
3956 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3957 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3959 case BFD_ENDIAN_BIG
:
3960 mips_xfer_register (regcache
,
3961 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3962 1, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 0);
3963 mips_xfer_register (regcache
,
3964 NUM_REGS
+ mips_regnum (current_gdbarch
)->fp0
+
3965 0, 4, TARGET_BYTE_ORDER
, readbuf
, writebuf
, 4);
3968 internal_error (__FILE__
, __LINE__
, "bad switch");
3970 return RETURN_VALUE_REGISTER_CONVENTION
;
3973 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3974 && TYPE_NFIELDS (type
) <= 2
3975 && TYPE_NFIELDS (type
) >= 1
3976 && ((TYPE_NFIELDS (type
) == 1
3977 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3979 || (TYPE_NFIELDS (type
) == 2
3980 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3982 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3984 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3986 /* A struct that contains one or two floats. Each value is part
3987 in the least significant part of their floating point
3989 bfd_byte reg
[MAX_REGISTER_SIZE
];
3992 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3993 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3995 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3998 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4000 mips_xfer_register (regcache
, NUM_REGS
+ regnum
,
4001 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4002 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4004 return RETURN_VALUE_REGISTER_CONVENTION
;
4008 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4009 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4011 /* A structure or union. Extract the left justified value,
4012 regardless of the byte order. I.e. DO NOT USE
4016 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4017 offset
< TYPE_LENGTH (type
);
4018 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
4020 int xfer
= register_size (current_gdbarch
, regnum
);
4021 if (offset
+ xfer
> TYPE_LENGTH (type
))
4022 xfer
= TYPE_LENGTH (type
) - offset
;
4024 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4025 offset
, xfer
, regnum
);
4026 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4027 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4029 return RETURN_VALUE_REGISTER_CONVENTION
;
4034 /* A scalar extract each part but least-significant-byte
4035 justified. o32 thinks registers are 4 byte, regardless of
4036 the ISA. mips_stack_argsize controls this. */
4039 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4040 offset
< TYPE_LENGTH (type
);
4041 offset
+= mips_stack_argsize (gdbarch
), regnum
++)
4043 int xfer
= mips_stack_argsize (gdbarch
);
4044 if (offset
+ xfer
> TYPE_LENGTH (type
))
4045 xfer
= TYPE_LENGTH (type
) - offset
;
4047 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4048 offset
, xfer
, regnum
);
4049 mips_xfer_register (regcache
, NUM_REGS
+ regnum
, xfer
,
4050 TARGET_BYTE_ORDER
, readbuf
, writebuf
, offset
);
4052 return RETURN_VALUE_REGISTER_CONVENTION
;
4056 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4060 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4061 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4063 struct value
**args
, CORE_ADDR sp
,
4064 int struct_return
, CORE_ADDR struct_addr
)
4070 int stack_offset
= 0;
4071 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4072 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4074 /* For shared libraries, "t9" needs to point at the function
4076 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4078 /* Set the return address register to point to the entry point of
4079 the program, where a breakpoint lies in wait. */
4080 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4082 /* First ensure that the stack and structure return address (if any)
4083 are properly aligned. The stack has to be at least 64-bit
4084 aligned even on 32-bit machines, because doubles must be 64-bit
4085 aligned. For n32 and n64, stack frames need to be 128-bit
4086 aligned, so we round to this widest known alignment. */
4088 sp
= align_down (sp
, 16);
4089 struct_addr
= align_down (struct_addr
, 16);
4091 /* Now make space on the stack for the args. */
4092 for (argnum
= 0; argnum
< nargs
; argnum
++)
4093 len
+= align_up (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
4094 mips_stack_argsize (gdbarch
));
4095 sp
-= align_up (len
, 16);
4098 fprintf_unfiltered (gdb_stdlog
,
4099 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
4100 paddr_nz (sp
), (long) align_up (len
, 16));
4102 /* Initialize the integer and float register pointers. */
4103 argreg
= MIPS_A0_REGNUM
;
4104 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
4106 /* The struct_return pointer occupies the first parameter-passing reg. */
4110 fprintf_unfiltered (gdb_stdlog
,
4111 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
4112 argreg
, paddr_nz (struct_addr
));
4113 write_register (argreg
++, struct_addr
);
4114 stack_offset
+= mips_stack_argsize (gdbarch
);
4117 /* Now load as many as possible of the first arguments into
4118 registers, and push the rest onto the stack. Loop thru args
4119 from first to last. */
4120 for (argnum
= 0; argnum
< nargs
; argnum
++)
4123 struct value
*arg
= args
[argnum
];
4124 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
4125 int len
= TYPE_LENGTH (arg_type
);
4126 enum type_code typecode
= TYPE_CODE (arg_type
);
4129 fprintf_unfiltered (gdb_stdlog
,
4130 "mips_o64_push_dummy_call: %d len=%d type=%d",
4131 argnum
+ 1, len
, (int) typecode
);
4133 val
= (char *) VALUE_CONTENTS (arg
);
4135 /* 32-bit ABIs always start floating point arguments in an
4136 even-numbered floating point register. Round the FP register
4137 up before the check to see if there are any FP registers
4138 left. O32/O64 targets also pass the FP in the integer
4139 registers so also round up normal registers. */
4140 if (mips_abi_regsize (gdbarch
) < 8
4141 && fp_register_arg_p (typecode
, arg_type
))
4143 if ((float_argreg
& 1))
4147 /* Floating point arguments passed in registers have to be
4148 treated specially. On 32-bit architectures, doubles
4149 are passed in register pairs; the even register gets
4150 the low word, and the odd register gets the high word.
4151 On O32/O64, the first two floating point arguments are
4152 also copied to general registers, because MIPS16 functions
4153 don't use float registers for arguments. This duplication of
4154 arguments in general registers can't hurt non-MIPS16 functions
4155 because those registers are normally skipped. */
4157 if (fp_register_arg_p (typecode
, arg_type
)
4158 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
4160 if (mips_abi_regsize (gdbarch
) < 8 && len
== 8)
4162 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4163 unsigned long regval
;
4165 /* Write the low word of the double to the even register(s). */
4166 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
4168 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4169 float_argreg
, phex (regval
, 4));
4170 write_register (float_argreg
++, regval
);
4172 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4173 argreg
, phex (regval
, 4));
4174 write_register (argreg
++, regval
);
4176 /* Write the high word of the double to the odd register(s). */
4177 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
4179 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4180 float_argreg
, phex (regval
, 4));
4181 write_register (float_argreg
++, regval
);
4184 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4185 argreg
, phex (regval
, 4));
4186 write_register (argreg
++, regval
);
4190 /* This is a floating point value that fits entirely
4191 in a single register. */
4192 /* On 32 bit ABI's the float_argreg is further adjusted
4193 above to ensure that it is even register aligned. */
4194 LONGEST regval
= extract_unsigned_integer (val
, len
);
4196 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4197 float_argreg
, phex (regval
, len
));
4198 write_register (float_argreg
++, regval
);
4199 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
4200 registers for each argument. The below is (my
4201 guess) to ensure that the corresponding integer
4202 register has reserved the same space. */
4204 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4205 argreg
, phex (regval
, len
));
4206 write_register (argreg
, regval
);
4207 argreg
+= (mips_abi_regsize (gdbarch
) == 8) ? 1 : 2;
4209 /* Reserve space for the FP register. */
4210 stack_offset
+= align_up (len
, mips_stack_argsize (gdbarch
));
4214 /* Copy the argument to general registers or the stack in
4215 register-sized pieces. Large arguments are split between
4216 registers and stack. */
4217 /* Note: structs whose size is not a multiple of
4218 mips_abi_regsize() are treated specially: Irix cc passes
4219 them in registers where gcc sometimes puts them on the
4220 stack. For maximum compatibility, we will put them in
4222 int odd_sized_struct
= ((len
> mips_abi_regsize (gdbarch
))
4223 && (len
% mips_abi_regsize (gdbarch
) != 0));
4224 /* Structures should be aligned to eight bytes (even arg registers)
4225 on MIPS_ABI_O32, if their first member has double precision. */
4226 if (mips_abi_regsize (gdbarch
) < 8
4227 && mips_type_needs_double_align (arg_type
))
4232 /* Note: Floating-point values that didn't fit into an FP
4233 register are only written to memory. */
4236 /* Remember if the argument was written to the stack. */
4237 int stack_used_p
= 0;
4238 int partial_len
= (len
< mips_abi_regsize (gdbarch
)
4239 ? len
: mips_abi_regsize (gdbarch
));
4242 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4245 /* Write this portion of the argument to the stack. */
4246 if (argreg
> MIPS_LAST_ARG_REGNUM
4248 || fp_register_arg_p (typecode
, arg_type
))
4250 /* Should shorter than int integer values be
4251 promoted to int before being stored? */
4252 int longword_offset
= 0;
4255 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4257 if (mips_stack_argsize (gdbarch
) == 8
4258 && (typecode
== TYPE_CODE_INT
4259 || typecode
== TYPE_CODE_PTR
4260 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4261 longword_offset
= mips_stack_argsize (gdbarch
) - len
;
4266 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4267 paddr_nz (stack_offset
));
4268 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4269 paddr_nz (longword_offset
));
4272 addr
= sp
+ stack_offset
+ longword_offset
;
4277 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4279 for (i
= 0; i
< partial_len
; i
++)
4281 fprintf_unfiltered (gdb_stdlog
, "%02x",
4285 write_memory (addr
, val
, partial_len
);
4288 /* Note!!! This is NOT an else clause. Odd sized
4289 structs may go thru BOTH paths. Floating point
4290 arguments will not. */
4291 /* Write this portion of the argument to a general
4292 purpose register. */
4293 if (argreg
<= MIPS_LAST_ARG_REGNUM
4294 && !fp_register_arg_p (typecode
, arg_type
))
4296 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4297 /* Value may need to be sign extended, because
4298 mips_isa_regsize() != mips_abi_regsize(). */
4300 /* A non-floating-point argument being passed in a
4301 general register. If a struct or union, and if
4302 the remaining length is smaller than the register
4303 size, we have to adjust the register value on
4306 It does not seem to be necessary to do the
4307 same for integral types.
4309 Also don't do this adjustment on O64 binaries.
4311 cagney/2001-07-23: gdb/179: Also, GCC, when
4312 outputting LE O32 with sizeof (struct) <
4313 mips_abi_regsize(), generates a left shift as
4314 part of storing the argument in a register a
4315 register (the left shift isn't generated when
4316 sizeof (struct) >= mips_abi_regsize()). Since
4317 it is quite possible that this is GCC
4318 contradicting the LE/O32 ABI, GDB has not been
4319 adjusted to accommodate this. Either someone
4320 needs to demonstrate that the LE/O32 ABI
4321 specifies such a left shift OR this new ABI gets
4322 identified as such and GDB gets tweaked
4325 if (mips_abi_regsize (gdbarch
) < 8
4326 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4327 && partial_len
< mips_abi_regsize (gdbarch
)
4328 && (typecode
== TYPE_CODE_STRUCT
||
4329 typecode
== TYPE_CODE_UNION
))
4330 regval
<<= ((mips_abi_regsize (gdbarch
) - partial_len
) *
4334 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4337 mips_abi_regsize (gdbarch
)));
4338 write_register (argreg
, regval
);
4341 /* Prevent subsequent floating point arguments from
4342 being passed in floating point registers. */
4343 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
4349 /* Compute the the offset into the stack at which we
4350 will copy the next parameter.
4352 In older ABIs, the caller reserved space for
4353 registers that contained arguments. This was loosely
4354 refered to as their "home". Consequently, space is
4355 always allocated. */
4357 stack_offset
+= align_up (partial_len
,
4358 mips_stack_argsize (gdbarch
));
4362 fprintf_unfiltered (gdb_stdlog
, "\n");
4365 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4367 /* Return adjusted stack pointer. */
4371 static enum return_value_convention
4372 mips_o64_return_value (struct gdbarch
*gdbarch
,
4373 struct type
*type
, struct regcache
*regcache
,
4374 void *readbuf
, const void *writebuf
)
4376 return RETURN_VALUE_STRUCT_CONVENTION
;
4379 /* Floating point register management.
4381 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4382 64bit operations, these early MIPS cpus treat fp register pairs
4383 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4384 registers and offer a compatibility mode that emulates the MIPS2 fp
4385 model. When operating in MIPS2 fp compat mode, later cpu's split
4386 double precision floats into two 32-bit chunks and store them in
4387 consecutive fp regs. To display 64-bit floats stored in this
4388 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4389 Throw in user-configurable endianness and you have a real mess.
4391 The way this works is:
4392 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4393 double-precision value will be split across two logical registers.
4394 The lower-numbered logical register will hold the low-order bits,
4395 regardless of the processor's endianness.
4396 - If we are on a 64-bit processor, and we are looking for a
4397 single-precision value, it will be in the low ordered bits
4398 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4399 save slot in memory.
4400 - If we are in 64-bit mode, everything is straightforward.
4402 Note that this code only deals with "live" registers at the top of the
4403 stack. We will attempt to deal with saved registers later, when
4404 the raw/cooked register interface is in place. (We need a general
4405 interface that can deal with dynamic saved register sizes -- fp
4406 regs could be 32 bits wide in one frame and 64 on the frame above
4409 static struct type
*
4410 mips_float_register_type (void)
4412 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4413 return builtin_type_ieee_single_big
;
4415 return builtin_type_ieee_single_little
;
4418 static struct type
*
4419 mips_double_register_type (void)
4421 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4422 return builtin_type_ieee_double_big
;
4424 return builtin_type_ieee_double_little
;
4427 /* Copy a 32-bit single-precision value from the current frame
4428 into rare_buffer. */
4431 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4434 int raw_size
= register_size (current_gdbarch
, regno
);
4435 char *raw_buffer
= alloca (raw_size
);
4437 if (!frame_register_read (frame
, regno
, raw_buffer
))
4438 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4441 /* We have a 64-bit value for this register. Find the low-order
4445 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4450 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4454 memcpy (rare_buffer
, raw_buffer
, 4);
4458 /* Copy a 64-bit double-precision value from the current frame into
4459 rare_buffer. This may include getting half of it from the next
4463 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4466 int raw_size
= register_size (current_gdbarch
, regno
);
4468 if (raw_size
== 8 && !mips2_fp_compat ())
4470 /* We have a 64-bit value for this register, and we should use
4472 if (!frame_register_read (frame
, regno
, rare_buffer
))
4473 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
4477 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4478 internal_error (__FILE__
, __LINE__
,
4479 "mips_read_fp_register_double: bad access to "
4480 "odd-numbered FP register");
4482 /* mips_read_fp_register_single will find the correct 32 bits from
4484 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4486 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4487 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4491 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4492 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4498 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4500 { /* do values for FP (float) regs */
4502 double doub
, flt1
; /* doubles extracted from raw hex data */
4506 (char *) alloca (2 *
4507 register_size (current_gdbarch
,
4508 mips_regnum (current_gdbarch
)->fp0
));
4510 fprintf_filtered (file
, "%s:", REGISTER_NAME (regnum
));
4511 fprintf_filtered (file
, "%*s", 4 - (int) strlen (REGISTER_NAME (regnum
)),
4514 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat ())
4516 /* 4-byte registers: Print hex and floating. Also print even
4517 numbered registers as doubles. */
4518 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4519 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4521 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4524 fprintf_filtered (file
, " flt: ");
4526 fprintf_filtered (file
, " <invalid float> ");
4528 fprintf_filtered (file
, "%-17.9g", flt1
);
4530 if (regnum
% 2 == 0)
4532 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4533 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4536 fprintf_filtered (file
, " dbl: ");
4538 fprintf_filtered (file
, "<invalid double>");
4540 fprintf_filtered (file
, "%-24.17g", doub
);
4545 /* Eight byte registers: print each one as hex, float and double. */
4546 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4547 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4549 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4550 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4553 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4556 fprintf_filtered (file
, " flt: ");
4558 fprintf_filtered (file
, "<invalid float>");
4560 fprintf_filtered (file
, "%-17.9g", flt1
);
4562 fprintf_filtered (file
, " dbl: ");
4564 fprintf_filtered (file
, "<invalid double>");
4566 fprintf_filtered (file
, "%-24.17g", doub
);
4571 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4572 int regnum
, int all
)
4574 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4575 char raw_buffer
[MAX_REGISTER_SIZE
];
4578 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4580 mips_print_fp_register (file
, frame
, regnum
);
4584 /* Get the data in raw format. */
4585 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4587 fprintf_filtered (file
, "%s: [Invalid]", REGISTER_NAME (regnum
));
4591 fputs_filtered (REGISTER_NAME (regnum
), file
);
4593 /* The problem with printing numeric register names (r26, etc.) is that
4594 the user can't use them on input. Probably the best solution is to
4595 fix it so that either the numeric or the funky (a2, etc.) names
4596 are accepted on input. */
4597 if (regnum
< MIPS_NUMREGS
)
4598 fprintf_filtered (file
, "(r%d): ", regnum
);
4600 fprintf_filtered (file
, ": ");
4602 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4604 register_size (current_gdbarch
,
4605 regnum
) - register_size (current_gdbarch
, regnum
);
4609 print_scalar_formatted (raw_buffer
+ offset
,
4610 gdbarch_register_type (gdbarch
, regnum
), 'x', 0,
4614 /* Replacement for generic do_registers_info.
4615 Print regs in pretty columns. */
4618 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4621 fprintf_filtered (file
, " ");
4622 mips_print_fp_register (file
, frame
, regnum
);
4623 fprintf_filtered (file
, "\n");
4628 /* Print a row's worth of GP (int) registers, with name labels above */
4631 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4634 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4635 /* do values for GP (int) regs */
4636 char raw_buffer
[MAX_REGISTER_SIZE
];
4637 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4641 /* For GP registers, we print a separate row of names above the vals */
4642 fprintf_filtered (file
, " ");
4643 for (col
= 0, regnum
= start_regnum
;
4644 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4646 if (*REGISTER_NAME (regnum
) == '\0')
4647 continue; /* unused register */
4648 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4650 break; /* end the row: reached FP register */
4651 fprintf_filtered (file
,
4652 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4653 REGISTER_NAME (regnum
));
4656 /* print the R0 to R31 names */
4657 if ((start_regnum
% NUM_REGS
) < MIPS_NUMREGS
)
4658 fprintf_filtered (file
, "\n R%-4d", start_regnum
% NUM_REGS
);
4660 fprintf_filtered (file
, "\n ");
4662 /* now print the values in hex, 4 or 8 to the row */
4663 for (col
= 0, regnum
= start_regnum
;
4664 col
< ncols
&& regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
4666 if (*REGISTER_NAME (regnum
) == '\0')
4667 continue; /* unused register */
4668 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4670 break; /* end row: reached FP register */
4671 /* OK: get the data in raw format. */
4672 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4673 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4674 /* pad small registers */
4676 byte
< (mips_abi_regsize (current_gdbarch
)
4677 - register_size (current_gdbarch
, regnum
)); byte
++)
4678 printf_filtered (" ");
4679 /* Now print the register value in hex, endian order. */
4680 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4682 register_size (current_gdbarch
,
4683 regnum
) - register_size (current_gdbarch
, regnum
);
4684 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4685 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4687 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4689 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[byte
]);
4690 fprintf_filtered (file
, " ");
4693 if (col
> 0) /* ie. if we actually printed anything... */
4694 fprintf_filtered (file
, "\n");
4699 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4702 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4703 struct frame_info
*frame
, int regnum
, int all
)
4705 if (regnum
!= -1) /* do one specified register */
4707 gdb_assert (regnum
>= NUM_REGS
);
4708 if (*(REGISTER_NAME (regnum
)) == '\0')
4709 error ("Not a valid register for the current processor type");
4711 mips_print_register (file
, frame
, regnum
, 0);
4712 fprintf_filtered (file
, "\n");
4715 /* do all (or most) registers */
4718 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4720 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
4723 if (all
) /* true for "INFO ALL-REGISTERS" command */
4724 regnum
= print_fp_register_row (file
, frame
, regnum
);
4726 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4729 regnum
= print_gp_register_row (file
, frame
, regnum
);
4734 /* Is this a branch with a delay slot? */
4737 is_delayed (unsigned long insn
)
4740 for (i
= 0; i
< NUMOPCODES
; ++i
)
4741 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4742 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4744 return (i
< NUMOPCODES
4745 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4746 | INSN_COND_BRANCH_DELAY
4747 | INSN_COND_BRANCH_LIKELY
)));
4751 mips_step_skips_delay (CORE_ADDR pc
)
4753 char buf
[MIPS32_INSN_SIZE
];
4755 /* There is no branch delay slot on MIPS16. */
4756 if (pc_is_mips16 (pc
))
4759 if (target_read_memory (pc
, buf
, sizeof buf
) != 0)
4760 /* If error reading memory, guess that it is not a delayed branch. */
4762 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4765 /* To skip prologues, I use this predicate. Returns either PC itself
4766 if the code at PC does not look like a function prologue; otherwise
4767 returns an address that (if we're lucky) follows the prologue. If
4768 LENIENT, then we must skip everything which is involved in setting
4769 up the frame (it's OK to skip more, just so long as we don't skip
4770 anything which might clobber the registers which are being saved.
4771 We must skip more in the case where part of the prologue is in the
4772 delay slot of a non-prologue instruction). */
4775 mips_skip_prologue (CORE_ADDR pc
)
4777 /* See if we can determine the end of the prologue via the symbol table.
4778 If so, then return either PC, or the PC after the prologue, whichever
4781 CORE_ADDR post_prologue_pc
= after_prologue (pc
);
4784 if (post_prologue_pc
!= 0)
4785 return max (pc
, post_prologue_pc
);
4787 /* Can't determine prologue from the symbol table, need to examine
4790 /* Find an upper limit on the function prologue using the debug
4791 information. If the debug information could not be used to provide
4792 that bound, then use an arbitrary large number as the upper bound. */
4793 limit_pc
= skip_prologue_using_sal (pc
);
4795 limit_pc
= pc
+ 100; /* Magic. */
4797 if (pc_is_mips16 (pc
))
4798 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4800 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4803 /* Root of all "set mips "/"show mips " commands. This will eventually be
4804 used for all MIPS-specific commands. */
4807 show_mips_command (char *args
, int from_tty
)
4809 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4813 set_mips_command (char *args
, int from_tty
)
4816 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4817 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4820 /* Commands to show/set the MIPS FPU type. */
4823 show_mipsfpu_command (char *args
, int from_tty
)
4826 switch (MIPS_FPU_TYPE
)
4828 case MIPS_FPU_SINGLE
:
4829 fpu
= "single-precision";
4831 case MIPS_FPU_DOUBLE
:
4832 fpu
= "double-precision";
4835 fpu
= "absent (none)";
4838 internal_error (__FILE__
, __LINE__
, "bad switch");
4840 if (mips_fpu_type_auto
)
4842 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4846 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4851 set_mipsfpu_command (char *args
, int from_tty
)
4854 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4855 show_mipsfpu_command (args
, from_tty
);
4859 set_mipsfpu_single_command (char *args
, int from_tty
)
4861 struct gdbarch_info info
;
4862 gdbarch_info_init (&info
);
4863 mips_fpu_type
= MIPS_FPU_SINGLE
;
4864 mips_fpu_type_auto
= 0;
4865 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4866 instead of relying on globals. Doing that would let generic code
4867 handle the search for this specific architecture. */
4868 if (!gdbarch_update_p (info
))
4869 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4873 set_mipsfpu_double_command (char *args
, int from_tty
)
4875 struct gdbarch_info info
;
4876 gdbarch_info_init (&info
);
4877 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4878 mips_fpu_type_auto
= 0;
4879 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4880 instead of relying on globals. Doing that would let generic code
4881 handle the search for this specific architecture. */
4882 if (!gdbarch_update_p (info
))
4883 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4887 set_mipsfpu_none_command (char *args
, int from_tty
)
4889 struct gdbarch_info info
;
4890 gdbarch_info_init (&info
);
4891 mips_fpu_type
= MIPS_FPU_NONE
;
4892 mips_fpu_type_auto
= 0;
4893 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4894 instead of relying on globals. Doing that would let generic code
4895 handle the search for this specific architecture. */
4896 if (!gdbarch_update_p (info
))
4897 internal_error (__FILE__
, __LINE__
, "set mipsfpu failed");
4901 set_mipsfpu_auto_command (char *args
, int from_tty
)
4903 mips_fpu_type_auto
= 1;
4906 /* Attempt to identify the particular processor model by reading the
4907 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4908 the relevant processor still exists (it dates back to '94) and
4909 secondly this is not the way to do this. The processor type should
4910 be set by forcing an architecture change. */
4913 deprecated_mips_set_processor_regs_hack (void)
4915 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4918 prid
= read_register (PRID_REGNUM
);
4920 if ((prid
& ~0xf) == 0x700)
4921 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4924 /* Just like reinit_frame_cache, but with the right arguments to be
4925 callable as an sfunc. */
4928 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4929 struct cmd_list_element
*c
)
4931 reinit_frame_cache ();
4935 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4937 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4938 mips_extra_func_info_t proc_desc
;
4940 /* Search for the function containing this address. Set the low bit
4941 of the address when searching, in case we were given an even address
4942 that is the start of a 16-bit function. If we didn't do this,
4943 the search would fail because the symbol table says the function
4944 starts at an odd address, i.e. 1 byte past the given address. */
4945 memaddr
= ADDR_BITS_REMOVE (memaddr
);
4946 proc_desc
= non_heuristic_proc_desc (make_mips16_addr (memaddr
), NULL
);
4948 /* Make an attempt to determine if this is a 16-bit function. If
4949 the procedure descriptor exists and the address therein is odd,
4950 it's definitely a 16-bit function. Otherwise, we have to just
4951 guess that if the address passed in is odd, it's 16-bits. */
4952 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4953 disassembler needs to be able to locally determine the ISA, and
4954 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4958 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
4959 info
->mach
= bfd_mach_mips16
;
4963 if (pc_is_mips16 (memaddr
))
4964 info
->mach
= bfd_mach_mips16
;
4967 /* Round down the instruction address to the appropriate boundary. */
4968 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4970 /* Set the disassembler options. */
4971 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4973 /* Set up the disassembler info, so that we get the right
4974 register names from libopcodes. */
4975 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4976 info
->disassembler_options
= "gpr-names=n32";
4978 info
->disassembler_options
= "gpr-names=64";
4979 info
->flavour
= bfd_target_elf_flavour
;
4982 /* This string is not recognized explicitly by the disassembler,
4983 but it tells the disassembler to not try to guess the ABI from
4984 the bfd elf headers, such that, if the user overrides the ABI
4985 of a program linked as NewABI, the disassembly will follow the
4986 register naming conventions specified by the user. */
4987 info
->disassembler_options
= "gpr-names=32";
4989 /* Call the appropriate disassembler based on the target endian-ness. */
4990 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4991 return print_insn_big_mips (memaddr
, info
);
4993 return print_insn_little_mips (memaddr
, info
);
4996 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4997 counter value to determine whether a 16- or 32-bit breakpoint should be
4998 used. It returns a pointer to a string of bytes that encode a breakpoint
4999 instruction, stores the length of the string to *lenptr, and adjusts pc
5000 (if necessary) to point to the actual memory location where the
5001 breakpoint should be inserted. */
5003 static const unsigned char *
5004 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
5006 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
5008 if (pc_is_mips16 (*pcptr
))
5010 static unsigned char mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5011 *pcptr
= unmake_mips16_addr (*pcptr
);
5012 *lenptr
= sizeof (mips16_big_breakpoint
);
5013 return mips16_big_breakpoint
;
5017 /* The IDT board uses an unusual breakpoint value, and
5018 sometimes gets confused when it sees the usual MIPS
5019 breakpoint instruction. */
5020 static unsigned char big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5021 static unsigned char pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5022 static unsigned char idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5024 *lenptr
= sizeof (big_breakpoint
);
5026 if (strcmp (target_shortname
, "mips") == 0)
5027 return idt_big_breakpoint
;
5028 else if (strcmp (target_shortname
, "ddb") == 0
5029 || strcmp (target_shortname
, "pmon") == 0
5030 || strcmp (target_shortname
, "lsi") == 0)
5031 return pmon_big_breakpoint
;
5033 return big_breakpoint
;
5038 if (pc_is_mips16 (*pcptr
))
5040 static unsigned char mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5041 *pcptr
= unmake_mips16_addr (*pcptr
);
5042 *lenptr
= sizeof (mips16_little_breakpoint
);
5043 return mips16_little_breakpoint
;
5047 static unsigned char little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5048 static unsigned char pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5049 static unsigned char idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5051 *lenptr
= sizeof (little_breakpoint
);
5053 if (strcmp (target_shortname
, "mips") == 0)
5054 return idt_little_breakpoint
;
5055 else if (strcmp (target_shortname
, "ddb") == 0
5056 || strcmp (target_shortname
, "pmon") == 0
5057 || strcmp (target_shortname
, "lsi") == 0)
5058 return pmon_little_breakpoint
;
5060 return little_breakpoint
;
5065 /* If PC is in a mips16 call or return stub, return the address of the target
5066 PC, which is either the callee or the caller. There are several
5067 cases which must be handled:
5069 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5070 target PC is in $31 ($ra).
5071 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5072 and the target PC is in $2.
5073 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5074 before the jal instruction, this is effectively a call stub
5075 and the the target PC is in $2. Otherwise this is effectively
5076 a return stub and the target PC is in $18.
5078 See the source code for the stubs in gcc/config/mips/mips16.S for
5082 mips_skip_trampoline_code (CORE_ADDR pc
)
5085 CORE_ADDR start_addr
;
5087 /* Find the starting address and name of the function containing the PC. */
5088 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5091 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5092 target PC is in $31 ($ra). */
5093 if (strcmp (name
, "__mips16_ret_sf") == 0
5094 || strcmp (name
, "__mips16_ret_df") == 0)
5095 return read_signed_register (MIPS_RA_REGNUM
);
5097 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5099 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5100 and the target PC is in $2. */
5101 if (name
[19] >= '0' && name
[19] <= '9')
5102 return read_signed_register (2);
5104 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5105 before the jal instruction, this is effectively a call stub
5106 and the the target PC is in $2. Otherwise this is effectively
5107 a return stub and the target PC is in $18. */
5108 else if (name
[19] == 's' || name
[19] == 'd')
5110 if (pc
== start_addr
)
5112 /* Check if the target of the stub is a compiler-generated
5113 stub. Such a stub for a function bar might have a name
5114 like __fn_stub_bar, and might look like this:
5119 la $1,bar (becomes a lui/addiu pair)
5121 So scan down to the lui/addi and extract the target
5122 address from those two instructions. */
5124 CORE_ADDR target_pc
= read_signed_register (2);
5128 /* See if the name of the target function is __fn_stub_*. */
5129 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5132 if (strncmp (name
, "__fn_stub_", 10) != 0
5133 && strcmp (name
, "etext") != 0
5134 && strcmp (name
, "_etext") != 0)
5137 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5138 The limit on the search is arbitrarily set to 20
5139 instructions. FIXME. */
5140 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS32_INSN_SIZE
)
5142 inst
= mips_fetch_instruction (target_pc
);
5143 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5144 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5145 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5146 return pc
| (inst
& 0xffff); /* low word */
5149 /* Couldn't find the lui/addui pair, so return stub address. */
5153 /* This is the 'return' part of a call stub. The return
5154 address is in $r18. */
5155 return read_signed_register (18);
5158 return 0; /* not a stub */
5162 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5163 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5166 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5168 CORE_ADDR start_addr
;
5170 /* Find the starting address of the function containing the PC. If the
5171 caller didn't give us a name, look it up at the same time. */
5172 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) ==
5176 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5178 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5179 if (name
[19] >= '0' && name
[19] <= '9')
5181 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5182 before the jal instruction, this is effectively a call stub. */
5183 else if (name
[19] == 's' || name
[19] == 'd')
5184 return pc
== start_addr
;
5187 return 0; /* not a stub */
5191 /* Return non-zero if the PC is inside a return thunk (aka stub or
5195 mips_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
5197 CORE_ADDR start_addr
;
5199 /* Find the starting address of the function containing the PC. */
5200 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5203 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5204 if (strcmp (name
, "__mips16_ret_sf") == 0
5205 || strcmp (name
, "__mips16_ret_df") == 0)
5208 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5209 i.e. after the jal instruction, this is effectively a return stub. */
5210 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5211 && (name
[19] == 's' || name
[19] == 'd') && pc
!= start_addr
)
5214 return 0; /* not a stub */
5218 /* Return non-zero if the PC is in a library helper function that
5219 should be ignored. This implements the
5220 DEPRECATED_IGNORE_HELPER_CALL macro. */
5223 mips_ignore_helper (CORE_ADDR pc
)
5227 /* Find the starting address and name of the function containing the PC. */
5228 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5231 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5232 that we want to ignore. */
5233 return (strcmp (name
, "__mips16_ret_sf") == 0
5234 || strcmp (name
, "__mips16_ret_df") == 0);
5238 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5239 [1 * NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5242 mips_stab_reg_to_regnum (int num
)
5245 if (num
>= 0 && num
< 32)
5247 else if (num
>= 38 && num
< 70)
5248 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
5250 regnum
= mips_regnum (current_gdbarch
)->hi
;
5252 regnum
= mips_regnum (current_gdbarch
)->lo
;
5254 /* This will hopefully (eventually) provoke a warning. Should
5255 we be calling complaint() here? */
5256 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5257 return NUM_REGS
+ regnum
;
5261 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5262 NUM_REGS .. 2 * NUM_REGS) REGNUM. */
5265 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
5268 if (num
>= 0 && num
< 32)
5270 else if (num
>= 32 && num
< 64)
5271 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
5273 regnum
= mips_regnum (current_gdbarch
)->hi
;
5275 regnum
= mips_regnum (current_gdbarch
)->lo
;
5277 /* This will hopefully (eventually) provoke a warning. Should we
5278 be calling complaint() here? */
5279 return NUM_REGS
+ NUM_PSEUDO_REGS
;
5280 return NUM_REGS
+ regnum
;
5284 mips_register_sim_regno (int regnum
)
5286 /* Only makes sense to supply raw registers. */
5287 gdb_assert (regnum
>= 0 && regnum
< NUM_REGS
);
5288 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5289 decide if it is valid. Should instead define a standard sim/gdb
5290 register numbering scheme. */
5291 if (REGISTER_NAME (NUM_REGS
+ regnum
) != NULL
5292 && REGISTER_NAME (NUM_REGS
+ regnum
)[0] != '\0')
5295 return LEGACY_SIM_REGNO_IGNORE
;
5299 /* Convert an integer into an address. By first converting the value
5300 into a pointer and then extracting it signed, the address is
5301 guarenteed to be correctly sign extended. */
5304 mips_integer_to_address (struct type
*type
, void *buf
)
5306 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5307 LONGEST val
= unpack_long (type
, buf
);
5308 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5309 return extract_signed_integer (tmp
,
5310 TYPE_LENGTH (builtin_type_void_data_ptr
));
5314 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5316 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5317 const char *name
= bfd_get_section_name (abfd
, sect
);
5319 if (*abip
!= MIPS_ABI_UNKNOWN
)
5322 if (strncmp (name
, ".mdebug.", 8) != 0)
5325 if (strcmp (name
, ".mdebug.abi32") == 0)
5326 *abip
= MIPS_ABI_O32
;
5327 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5328 *abip
= MIPS_ABI_N32
;
5329 else if (strcmp (name
, ".mdebug.abi64") == 0)
5330 *abip
= MIPS_ABI_N64
;
5331 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5332 *abip
= MIPS_ABI_O64
;
5333 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5334 *abip
= MIPS_ABI_EABI32
;
5335 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5336 *abip
= MIPS_ABI_EABI64
;
5338 warning ("unsupported ABI %s.", name
+ 8);
5341 static enum mips_abi
5342 global_mips_abi (void)
5346 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5347 if (mips_abi_strings
[i
] == mips_abi_string
)
5348 return (enum mips_abi
) i
;
5350 internal_error (__FILE__
, __LINE__
, "unknown ABI string");
5353 static struct gdbarch
*
5354 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5356 struct gdbarch
*gdbarch
;
5357 struct gdbarch_tdep
*tdep
;
5359 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5361 enum mips_fpu_type fpu_type
;
5363 /* First of all, extract the elf_flags, if available. */
5364 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5365 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5366 else if (arches
!= NULL
)
5367 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5371 fprintf_unfiltered (gdb_stdlog
,
5372 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5374 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5375 switch ((elf_flags
& EF_MIPS_ABI
))
5377 case E_MIPS_ABI_O32
:
5378 found_abi
= MIPS_ABI_O32
;
5380 case E_MIPS_ABI_O64
:
5381 found_abi
= MIPS_ABI_O64
;
5383 case E_MIPS_ABI_EABI32
:
5384 found_abi
= MIPS_ABI_EABI32
;
5386 case E_MIPS_ABI_EABI64
:
5387 found_abi
= MIPS_ABI_EABI64
;
5390 if ((elf_flags
& EF_MIPS_ABI2
))
5391 found_abi
= MIPS_ABI_N32
;
5393 found_abi
= MIPS_ABI_UNKNOWN
;
5397 /* GCC creates a pseudo-section whose name describes the ABI. */
5398 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5399 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5401 /* If we have no useful BFD information, use the ABI from the last
5402 MIPS architecture (if there is one). */
5403 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5404 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5406 /* Try the architecture for any hint of the correct ABI. */
5407 if (found_abi
== MIPS_ABI_UNKNOWN
5408 && info
.bfd_arch_info
!= NULL
5409 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5411 switch (info
.bfd_arch_info
->mach
)
5413 case bfd_mach_mips3900
:
5414 found_abi
= MIPS_ABI_EABI32
;
5416 case bfd_mach_mips4100
:
5417 case bfd_mach_mips5000
:
5418 found_abi
= MIPS_ABI_EABI64
;
5420 case bfd_mach_mips8000
:
5421 case bfd_mach_mips10000
:
5422 /* On Irix, ELF64 executables use the N64 ABI. The
5423 pseudo-sections which describe the ABI aren't present
5424 on IRIX. (Even for executables created by gcc.) */
5425 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5426 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5427 found_abi
= MIPS_ABI_N64
;
5429 found_abi
= MIPS_ABI_N32
;
5435 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5438 /* What has the user specified from the command line? */
5439 wanted_abi
= global_mips_abi ();
5441 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5444 /* Now that we have found what the ABI for this binary would be,
5445 check whether the user is overriding it. */
5446 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5447 mips_abi
= wanted_abi
;
5448 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5449 mips_abi
= found_abi
;
5451 mips_abi
= MIPS_ABI_O32
;
5453 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5456 /* Also used when doing an architecture lookup. */
5458 fprintf_unfiltered (gdb_stdlog
,
5459 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5460 mips64_transfers_32bit_regs_p
);
5462 /* Determine the MIPS FPU type. */
5463 if (!mips_fpu_type_auto
)
5464 fpu_type
= mips_fpu_type
;
5465 else if (info
.bfd_arch_info
!= NULL
5466 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5467 switch (info
.bfd_arch_info
->mach
)
5469 case bfd_mach_mips3900
:
5470 case bfd_mach_mips4100
:
5471 case bfd_mach_mips4111
:
5472 case bfd_mach_mips4120
:
5473 fpu_type
= MIPS_FPU_NONE
;
5475 case bfd_mach_mips4650
:
5476 fpu_type
= MIPS_FPU_SINGLE
;
5479 fpu_type
= MIPS_FPU_DOUBLE
;
5482 else if (arches
!= NULL
)
5483 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5485 fpu_type
= MIPS_FPU_DOUBLE
;
5487 fprintf_unfiltered (gdb_stdlog
,
5488 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5490 /* try to find a pre-existing architecture */
5491 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5493 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5495 /* MIPS needs to be pedantic about which ABI the object is
5497 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5499 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5501 /* Need to be pedantic about which register virtual size is
5503 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5504 != mips64_transfers_32bit_regs_p
)
5506 /* Be pedantic about which FPU is selected. */
5507 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5509 return arches
->gdbarch
;
5512 /* Need a new architecture. Fill in a target specific vector. */
5513 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5514 gdbarch
= gdbarch_alloc (&info
, tdep
);
5515 tdep
->elf_flags
= elf_flags
;
5516 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5517 tdep
->found_abi
= found_abi
;
5518 tdep
->mips_abi
= mips_abi
;
5519 tdep
->mips_fpu_type
= fpu_type
;
5521 /* Initially set everything according to the default ABI/ISA. */
5522 set_gdbarch_short_bit (gdbarch
, 16);
5523 set_gdbarch_int_bit (gdbarch
, 32);
5524 set_gdbarch_float_bit (gdbarch
, 32);
5525 set_gdbarch_double_bit (gdbarch
, 64);
5526 set_gdbarch_long_double_bit (gdbarch
, 64);
5527 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5528 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5529 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5531 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5532 mips_elf_make_msymbol_special
);
5534 /* Fill in the OS dependant register numbers and names. */
5536 const char **reg_names
;
5537 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5538 struct mips_regnum
);
5539 if (info
.osabi
== GDB_OSABI_IRIX
)
5544 regnum
->badvaddr
= 66;
5547 regnum
->fp_control_status
= 69;
5548 regnum
->fp_implementation_revision
= 70;
5550 reg_names
= mips_irix_reg_names
;
5554 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5555 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5556 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5557 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5558 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5559 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5560 regnum
->fp_control_status
= 70;
5561 regnum
->fp_implementation_revision
= 71;
5563 if (info
.bfd_arch_info
!= NULL
5564 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5565 reg_names
= mips_tx39_reg_names
;
5567 reg_names
= mips_generic_reg_names
;
5569 /* FIXME: cagney/2003-11-15: For MIPS, hasn't PC_REGNUM been
5570 replaced by read_pc? */
5571 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5572 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5573 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5574 set_gdbarch_num_regs (gdbarch
, num_regs
);
5575 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5576 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5577 tdep
->mips_processor_reg_names
= reg_names
;
5578 tdep
->regnum
= regnum
;
5584 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5585 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5586 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5587 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5588 tdep
->default_mask_address_p
= 0;
5589 set_gdbarch_long_bit (gdbarch
, 32);
5590 set_gdbarch_ptr_bit (gdbarch
, 32);
5591 set_gdbarch_long_long_bit (gdbarch
, 64);
5594 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5595 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5596 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5597 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5598 tdep
->default_mask_address_p
= 0;
5599 set_gdbarch_long_bit (gdbarch
, 32);
5600 set_gdbarch_ptr_bit (gdbarch
, 32);
5601 set_gdbarch_long_long_bit (gdbarch
, 64);
5603 case MIPS_ABI_EABI32
:
5604 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5605 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5606 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5607 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5608 tdep
->default_mask_address_p
= 0;
5609 set_gdbarch_long_bit (gdbarch
, 32);
5610 set_gdbarch_ptr_bit (gdbarch
, 32);
5611 set_gdbarch_long_long_bit (gdbarch
, 64);
5613 case MIPS_ABI_EABI64
:
5614 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5615 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5616 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5617 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5618 tdep
->default_mask_address_p
= 0;
5619 set_gdbarch_long_bit (gdbarch
, 64);
5620 set_gdbarch_ptr_bit (gdbarch
, 64);
5621 set_gdbarch_long_long_bit (gdbarch
, 64);
5624 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5625 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5626 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5627 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5628 tdep
->default_mask_address_p
= 0;
5629 set_gdbarch_long_bit (gdbarch
, 32);
5630 set_gdbarch_ptr_bit (gdbarch
, 32);
5631 set_gdbarch_long_long_bit (gdbarch
, 64);
5632 set_gdbarch_long_double_bit (gdbarch
, 128);
5633 set_gdbarch_long_double_format (gdbarch
,
5634 &floatformat_n32n64_long_double_big
);
5637 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5638 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5639 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5640 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5641 tdep
->default_mask_address_p
= 0;
5642 set_gdbarch_long_bit (gdbarch
, 64);
5643 set_gdbarch_ptr_bit (gdbarch
, 64);
5644 set_gdbarch_long_long_bit (gdbarch
, 64);
5645 set_gdbarch_long_double_bit (gdbarch
, 128);
5646 set_gdbarch_long_double_format (gdbarch
,
5647 &floatformat_n32n64_long_double_big
);
5650 internal_error (__FILE__
, __LINE__
, "unknown ABI in switch");
5653 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5654 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5657 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5658 flag in object files because to do so would make it impossible to
5659 link with libraries compiled without "-gp32". This is
5660 unnecessarily restrictive.
5662 We could solve this problem by adding "-gp32" multilibs to gcc,
5663 but to set this flag before gcc is built with such multilibs will
5664 break too many systems.''
5666 But even more unhelpfully, the default linker output target for
5667 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5668 for 64-bit programs - you need to change the ABI to change this,
5669 and not all gcc targets support that currently. Therefore using
5670 this flag to detect 32-bit mode would do the wrong thing given
5671 the current gcc - it would make GDB treat these 64-bit programs
5672 as 32-bit programs by default. */
5674 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5675 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5676 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5678 /* Add/remove bits from an address. The MIPS needs be careful to
5679 ensure that all 32 bit addresses are sign extended to 64 bits. */
5680 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5682 /* Unwind the frame. */
5683 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5684 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5686 /* Map debug register numbers onto internal register numbers. */
5687 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5688 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5689 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5690 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5691 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5692 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5693 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5694 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5696 /* MIPS version of CALL_DUMMY */
5698 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5699 replaced by a command, and all targets will default to on stack
5700 (regardless of the stack's execute status). */
5701 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5702 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5704 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5705 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5706 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5708 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5709 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5711 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5713 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5714 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5715 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5717 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5719 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5721 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5723 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5724 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5725 need to all be folded into the target vector. Since they are
5726 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5727 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5729 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5731 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5733 /* NOTE drow/2004-02-11: We overload the core solib trampoline code
5734 to support MIPS16. This is a bad thing. Make sure not to do it
5735 if we have an OS ABI that actually supports shared libraries, since
5736 shared library support is more important. If we have an OS someday
5737 that supports both shared libraries and MIPS16, we'll have to find
5738 a better place for these. */
5739 if (info
.osabi
== GDB_OSABI_UNKNOWN
)
5741 set_gdbarch_in_solib_call_trampoline (gdbarch
, mips_in_call_stub
);
5742 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_solib_return_trampoline
);
5745 /* Hook in OS ABI-specific overrides, if they have been registered. */
5746 gdbarch_init_osabi (info
, gdbarch
);
5748 /* Unwind the frame. */
5749 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5750 frame_unwind_append_sniffer (gdbarch
, mips_mdebug_frame_sniffer
);
5751 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5752 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5753 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5754 frame_base_append_sniffer (gdbarch
, mips_mdebug_frame_base_sniffer
);
5755 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5756 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5762 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5764 struct gdbarch_info info
;
5766 /* Force the architecture to update, and (if it's a MIPS architecture)
5767 mips_gdbarch_init will take care of the rest. */
5768 gdbarch_info_init (&info
);
5769 gdbarch_update_p (info
);
5772 /* Print out which MIPS ABI is in use. */
5775 show_mips_abi (char *ignore_args
, int from_tty
)
5777 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5779 ("The MIPS ABI is unknown because the current architecture is not MIPS.\n");
5782 enum mips_abi global_abi
= global_mips_abi ();
5783 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5784 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5786 if (global_abi
== MIPS_ABI_UNKNOWN
)
5788 ("The MIPS ABI is set automatically (currently \"%s\").\n",
5790 else if (global_abi
== actual_abi
)
5792 ("The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5796 /* Probably shouldn't happen... */
5798 ("The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5799 actual_abi_str
, mips_abi_strings
[global_abi
]);
5805 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5807 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5811 int ef_mips_32bitmode
;
5812 /* determine the ISA */
5813 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5831 /* determine the size of a pointer */
5832 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5833 fprintf_unfiltered (file
,
5834 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5836 fprintf_unfiltered (file
,
5837 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5839 fprintf_unfiltered (file
,
5840 "mips_dump_tdep: ef_mips_arch = %d\n",
5842 fprintf_unfiltered (file
,
5843 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5844 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5845 fprintf_unfiltered (file
,
5846 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5847 mips_mask_address_p (tdep
),
5848 tdep
->default_mask_address_p
);
5850 fprintf_unfiltered (file
,
5851 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5852 MIPS_DEFAULT_FPU_TYPE
,
5853 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5854 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5855 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5857 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5858 fprintf_unfiltered (file
,
5859 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5861 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5862 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5863 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5865 fprintf_unfiltered (file
,
5866 "mips_dump_tdep: mips_stack_argsize() = %d\n",
5867 mips_stack_argsize (current_gdbarch
));
5868 fprintf_unfiltered (file
,
5869 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5870 XSTRING (ADDR_BITS_REMOVE (ADDR
)));
5871 fprintf_unfiltered (file
,
5872 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5873 XSTRING (ATTACH_DETACH
));
5874 fprintf_unfiltered (file
,
5875 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5876 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
5877 fprintf_unfiltered (file
,
5878 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5879 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
5880 fprintf_unfiltered (file
,
5881 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5882 FIRST_EMBED_REGNUM
);
5883 fprintf_unfiltered (file
,
5884 "mips_dump_tdep: DEPRECATED_IGNORE_HELPER_CALL # %s\n",
5885 XSTRING (DEPRECATED_IGNORE_HELPER_CALL (PC
)));
5886 fprintf_unfiltered (file
,
5887 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
5888 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
5889 fprintf_unfiltered (file
,
5890 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
5892 #ifdef MACHINE_CPROC_FP_OFFSET
5893 fprintf_unfiltered (file
,
5894 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
5895 MACHINE_CPROC_FP_OFFSET
);
5897 #ifdef MACHINE_CPROC_PC_OFFSET
5898 fprintf_unfiltered (file
,
5899 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
5900 MACHINE_CPROC_PC_OFFSET
);
5902 #ifdef MACHINE_CPROC_SP_OFFSET
5903 fprintf_unfiltered (file
,
5904 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
5905 MACHINE_CPROC_SP_OFFSET
);
5907 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
5908 fprintf_unfiltered (file
,
5909 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
5910 fprintf_unfiltered (file
,
5911 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
5912 MIPS_LAST_ARG_REGNUM
,
5913 MIPS_LAST_ARG_REGNUM
- MIPS_A0_REGNUM
+ 1);
5914 fprintf_unfiltered (file
,
5915 "mips_dump_tdep: MIPS_NUMREGS = %d\n", MIPS_NUMREGS
);
5916 fprintf_unfiltered (file
,
5917 "mips_dump_tdep: mips_abi_regsize() = %d\n",
5918 mips_abi_regsize (current_gdbarch
));
5919 fprintf_unfiltered (file
,
5920 "mips_dump_tdep: PRID_REGNUM = %d\n", PRID_REGNUM
);
5921 fprintf_unfiltered (file
,
5922 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
5923 fprintf_unfiltered (file
,
5924 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
5925 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FRAME_REG = function?\n");
5926 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_MASK = function?\n");
5927 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
5928 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
5929 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
5930 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_PC_REG = function?\n");
5931 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_MASK = function?\n");
5932 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
5933 fprintf_unfiltered (file
, "mips_dump_tdep: PROC_SYMBOL = function?\n");
5934 fprintf_unfiltered (file
, "mips_dump_tdep: PS_REGNUM = %d\n", PS_REGNUM
);
5936 fprintf_unfiltered (file
,
5937 "mips_dump_tdep: SAVED_BYTES = %d\n", SAVED_BYTES
);
5940 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_FP = %d\n", SAVED_FP
);
5943 fprintf_unfiltered (file
, "mips_dump_tdep: SAVED_PC = %d\n", SAVED_PC
);
5945 fprintf_unfiltered (file
,
5946 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
5947 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
5948 fprintf_unfiltered (file
,
5949 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
5950 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
5951 fprintf_unfiltered (file
,
5952 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
5953 SOFTWARE_SINGLE_STEP_P ());
5954 fprintf_unfiltered (file
,
5955 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
5956 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
5957 #ifdef STACK_END_ADDR
5958 fprintf_unfiltered (file
,
5959 "mips_dump_tdep: STACK_END_ADDR = %d\n",
5962 fprintf_unfiltered (file
,
5963 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
5964 XSTRING (STEP_SKIPS_DELAY (PC
)));
5965 fprintf_unfiltered (file
,
5966 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
5967 STEP_SKIPS_DELAY_P
);
5968 fprintf_unfiltered (file
,
5969 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
5970 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
5971 fprintf_unfiltered (file
,
5972 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
5973 fprintf_unfiltered (file
,
5974 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
5975 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT
5976 (TYPE
, CNT
, OTHERTYPE
)));
5978 fprintf_unfiltered (file
,
5979 "mips_dump_tdep: TRACE_CLEAR # %s\n",
5980 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
5983 fprintf_unfiltered (file
,
5984 "mips_dump_tdep: TRACE_FLAVOR = %d\n", TRACE_FLAVOR
);
5986 #ifdef TRACE_FLAVOR_SIZE
5987 fprintf_unfiltered (file
,
5988 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
5992 fprintf_unfiltered (file
,
5993 "mips_dump_tdep: TRACE_SET # %s\n",
5994 XSTRING (TRACE_SET (X
, STATE
)));
5996 #ifdef UNUSED_REGNUM
5997 fprintf_unfiltered (file
,
5998 "mips_dump_tdep: UNUSED_REGNUM = %d\n", UNUSED_REGNUM
);
6000 fprintf_unfiltered (file
,
6001 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6002 (long) VM_MIN_ADDRESS
);
6005 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6008 _initialize_mips_tdep (void)
6010 static struct cmd_list_element
*mipsfpulist
= NULL
;
6011 struct cmd_list_element
*c
;
6013 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6014 if (MIPS_ABI_LAST
+ 1
6015 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6016 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6018 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6020 mips_pdr_data
= register_objfile_data ();
6022 /* Add root prefix command for all "set mips"/"show mips" commands */
6023 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6024 "Various MIPS specific commands.",
6025 &setmipscmdlist
, "set mips ", 0, &setlist
);
6027 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6028 "Various MIPS specific commands.",
6029 &showmipscmdlist
, "show mips ", 0, &showlist
);
6031 /* Allow the user to override the saved register size. */
6032 deprecated_add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6035 &mips_abi_regsize_string
, "\
6036 Set size of general purpose registers saved on the stack.\n\
6037 This option can be set to one of:\n\
6038 32 - Force GDB to treat saved GP registers as 32-bit\n\
6039 64 - Force GDB to treat saved GP registers as 64-bit\n\
6040 auto - Allow GDB to use the target's default setting or autodetect the\n\
6041 saved GP register size from information contained in the executable.\n\
6042 (default: auto)", &setmipscmdlist
), &showmipscmdlist
);
6044 /* Allow the user to override the argument stack size. */
6045 deprecated_add_show_from_set
6046 (add_set_enum_cmd ("stack-arg-size",
6049 &mips_stack_argsize_string
, "\
6050 Set the amount of stack space reserved for each argument.\n\
6051 This option can be set to one of:\n\
6052 32 - Force GDB to allocate 32-bit chunks per argument\n\
6053 64 - Force GDB to allocate 64-bit chunks per argument\n\
6054 auto - Allow GDB to determine the correct setting from the current\n\
6055 target and executable (default)", &setmipscmdlist
),
6058 /* Allow the user to override the ABI. */
6059 c
= add_set_enum_cmd
6060 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6061 "Set the ABI used by this program.\n"
6062 "This option can be set to one of:\n"
6063 " auto - the default ABI associated with the current binary\n"
6065 " o64\n" " n32\n" " n64\n" " eabi32\n" " eabi64", &setmipscmdlist
);
6066 set_cmd_sfunc (c
, mips_abi_update
);
6067 add_cmd ("abi", class_obscure
, show_mips_abi
,
6068 "Show ABI in use by MIPS target", &showmipscmdlist
);
6070 /* Let the user turn off floating point and set the fence post for
6071 heuristic_proc_start. */
6073 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6074 "Set use of MIPS floating-point coprocessor.",
6075 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6076 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6077 "Select single-precision MIPS floating-point coprocessor.",
6079 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6080 "Select double-precision MIPS floating-point coprocessor.",
6082 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6083 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6084 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6085 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6086 "Select no MIPS floating-point coprocessor.", &mipsfpulist
);
6087 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6088 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6089 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6090 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6091 "Select MIPS floating-point coprocessor automatically.",
6093 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6094 "Show current use of MIPS floating-point coprocessor target.",
6097 /* We really would like to have both "0" and "unlimited" work, but
6098 command.c doesn't deal with that. So make it a var_zinteger
6099 because the user can always use "999999" or some such for unlimited. */
6100 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6101 &heuristic_fence_post
, "\
6102 Set the distance searched for the start of a function.\n", "\
6103 Show the distance searched for the start of a function.\n", "\
6104 If you are debugging a stripped executable, GDB needs to search through the\n\
6105 program for the start of a function. This command sets the distance of the\n\
6106 search. The only need to set it is when debugging a stripped executable.", "\
6107 The distance searched for the start of a function is %s.\n",
6108 reinit_frame_cache_sfunc
, NULL
,
6109 &setlist
, &showlist
);
6111 /* Allow the user to control whether the upper bits of 64-bit
6112 addresses should be zeroed. */
6113 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6114 Set zeroing of upper 32 bits of 64-bit addresses.", "\
6115 Show zeroing of upper 32 bits of 64-bit addresses.", "\
6116 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6117 allow GDB to determine the correct value.\n", "\
6118 Zerroing of upper 32 bits of 64-bit address is %s.",
6119 NULL
, show_mask_address
, &setmipscmdlist
, &showmipscmdlist
);
6121 /* Allow the user to control the size of 32 bit registers within the
6122 raw remote packet. */
6123 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6124 &mips64_transfers_32bit_regs_p
, "\
6125 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6126 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities.", "\
6127 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6128 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6129 64 bits for others. Use \"off\" to disable compatibility mode", "\
6130 Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s.",
6131 set_mips64_transfers_32bit_regs
, NULL
, &setlist
, &showlist
);
6133 /* Debug this files internals. */
6134 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6136 Set mips debugging.\n", "\
6137 Show mips debugging.\n", "\
6138 When non-zero, mips specific debugging is enabled.\n", "\
6139 Mips debugging is currently %s.\n",
6141 &setdebuglist
, &showdebuglist
);