1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
43 #include "opcode/mips.h"
48 /* A useful bit in the CP0 status register (PS_REGNUM). */
49 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
50 #define ST0_FR (1 << 26)
52 /* The sizes of floating point registers. */
56 MIPS_FPU_SINGLE_REGSIZE
= 4,
57 MIPS_FPU_DOUBLE_REGSIZE
= 8
60 /* All the possible MIPS ABIs. */
74 static const char *mips_abi_string
;
76 static const char *mips_abi_strings
[] = {
87 struct frame_extra_info
89 mips_extra_func_info_t proc_desc
;
93 /* Various MIPS ISA options (related to stack analysis) can be
94 overridden dynamically. Establish an enum/array for managing
97 static const char size_auto
[] = "auto";
98 static const char size_32
[] = "32";
99 static const char size_64
[] = "64";
101 static const char *size_enums
[] = {
108 /* Some MIPS boards don't support floating point while others only
109 support single-precision floating-point operations. See also
110 FP_REGISTER_DOUBLE. */
114 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
115 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
116 MIPS_FPU_NONE
/* No floating point. */
119 #ifndef MIPS_DEFAULT_FPU_TYPE
120 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
122 static int mips_fpu_type_auto
= 1;
123 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
125 static int mips_debug
= 0;
127 /* MIPS specific per-architecture information */
130 /* from the elf header */
134 enum mips_abi mips_abi
;
135 enum mips_abi found_abi
;
136 enum mips_fpu_type mips_fpu_type
;
137 int mips_last_arg_regnum
;
138 int mips_last_fp_arg_regnum
;
139 int mips_default_saved_regsize
;
140 int mips_fp_register_double
;
141 int mips_default_stack_argsize
;
142 int gdb_target_is_mips64
;
143 int default_mask_address_p
;
145 enum gdb_osabi osabi
;
148 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
149 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
151 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
153 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
155 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
157 /* Return the currently configured (or set) saved register size. */
159 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
161 static const char *mips_saved_regsize_string
= size_auto
;
163 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
166 mips_saved_regsize (void)
168 if (mips_saved_regsize_string
== size_auto
)
169 return MIPS_DEFAULT_SAVED_REGSIZE
;
170 else if (mips_saved_regsize_string
== size_64
)
172 else /* if (mips_saved_regsize_string == size_32) */
176 /* XFER a value from the big/little/left end of the register.
177 Depending on the size of the value it might occupy the entire
178 register or just part of it. Make an allowance for this, aligning
179 things accordingly. */
182 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
183 enum bfd_endian endian
, bfd_byte
*in
, const bfd_byte
*out
,
186 bfd_byte
*reg
= alloca (MAX_REGISTER_RAW_SIZE
);
191 reg_offset
= REGISTER_RAW_SIZE (reg_num
) - length
;
193 case BFD_ENDIAN_LITTLE
:
196 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
200 internal_error (__FILE__
, __LINE__
, "bad switch");
203 fprintf_unfiltered (gdb_stderr
, "xfer $%d[%d..%d] ",
204 reg_num
, reg_offset
, reg_offset
+ length
);
205 if (mips_debug
&& out
!= NULL
)
208 fprintf_unfiltered (gdb_stdlog
, "out: ");
209 for (i
= 0; i
< length
; i
++)
210 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[i
]);
213 regcache_raw_read_part (regcache
, reg_num
, reg_offset
, length
, in
+ buf_offset
);
215 regcache_raw_write_part (regcache
, reg_num
, reg_offset
, length
, out
+ buf_offset
);
216 if (mips_debug
&& in
!= NULL
)
219 fprintf_unfiltered (gdb_stdlog
, "in: ");
220 for (i
= 0; i
< length
; i
++)
221 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[i
]);
224 fprintf_unfiltered (gdb_stdlog
, "\n");
227 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
228 compatiblity mode. A return value of 1 means that we have
229 physical 64-bit registers, but should treat them as 32-bit registers. */
232 mips2_fp_compat (void)
234 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
236 if (REGISTER_RAW_SIZE (FP0_REGNUM
) == 4)
240 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
241 in all the places we deal with FP registers. PR gdb/413. */
242 /* Otherwise check the FR bit in the status register - it controls
243 the FP compatiblity mode. If it is clear we are in compatibility
245 if ((read_register (PS_REGNUM
) & ST0_FR
) == 0)
252 /* Indicate that the ABI makes use of double-precision registers
253 provided by the FPU (rather than combining pairs of registers to
254 form double-precision values). Do not use "TARGET_IS_MIPS64" to
255 determine if the ABI is using double-precision registers. See also
257 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
259 /* The amount of space reserved on the stack for registers. This is
260 different to MIPS_SAVED_REGSIZE as it determines the alignment of
261 data allocated after the registers have run out. */
263 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
265 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
267 static const char *mips_stack_argsize_string
= size_auto
;
270 mips_stack_argsize (void)
272 if (mips_stack_argsize_string
== size_auto
)
273 return MIPS_DEFAULT_STACK_ARGSIZE
;
274 else if (mips_stack_argsize_string
== size_64
)
276 else /* if (mips_stack_argsize_string == size_32) */
280 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
282 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
284 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
286 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
288 static void mips_print_register (int, int);
290 static mips_extra_func_info_t
291 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*, int);
293 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
295 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
297 int mips_set_processor_type (char *);
299 static void mips_show_processor_type_command (char *, int);
301 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
303 static mips_extra_func_info_t
304 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
);
306 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
307 mips_extra_func_info_t proc_desc
);
309 static void mips_read_fp_register_single (int regno
, char *rare_buffer
);
310 static void mips_read_fp_register_double (int regno
, char *rare_buffer
);
312 static struct type
*mips_float_register_type (void);
313 static struct type
*mips_double_register_type (void);
315 /* This value is the model of MIPS in use. It is derived from the value
316 of the PrID register. */
318 char *mips_processor_type
;
320 char *tmp_mips_processor_type
;
322 /* The list of available "set mips " and "show mips " commands */
324 static struct cmd_list_element
*setmipscmdlist
= NULL
;
325 static struct cmd_list_element
*showmipscmdlist
= NULL
;
327 /* A set of original names, to be used when restoring back to generic
328 registers from a specific set. */
330 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
331 char **mips_processor_reg_names
= mips_generic_reg_names
;
334 mips_register_name (int i
)
336 return mips_processor_reg_names
[i
];
339 /* Names of IDT R3041 registers. */
341 char *mips_r3041_reg_names
[] = {
342 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
343 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
344 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
345 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
346 "sr", "lo", "hi", "bad", "cause","pc",
347 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
348 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
349 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
350 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
351 "fsr", "fir", "fp", "",
352 "", "", "bus", "ccfg", "", "", "", "",
353 "", "", "port", "cmp", "", "", "epc", "prid",
356 /* Names of IDT R3051 registers. */
358 char *mips_r3051_reg_names
[] = {
359 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
360 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
361 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
362 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
363 "sr", "lo", "hi", "bad", "cause","pc",
364 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
365 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
366 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
367 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
368 "fsr", "fir", "fp", "",
369 "inx", "rand", "elo", "", "ctxt", "", "", "",
370 "", "", "ehi", "", "", "", "epc", "prid",
373 /* Names of IDT R3081 registers. */
375 char *mips_r3081_reg_names
[] = {
376 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
377 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
378 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
379 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
380 "sr", "lo", "hi", "bad", "cause","pc",
381 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
382 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
383 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
384 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
385 "fsr", "fir", "fp", "",
386 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
387 "", "", "ehi", "", "", "", "epc", "prid",
390 /* Names of LSI 33k registers. */
392 char *mips_lsi33k_reg_names
[] = {
393 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
394 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
395 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
396 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
397 "epc", "hi", "lo", "sr", "cause","badvaddr",
398 "dcic", "bpc", "bda", "", "", "", "", "",
399 "", "", "", "", "", "", "", "",
400 "", "", "", "", "", "", "", "",
401 "", "", "", "", "", "", "", "",
403 "", "", "", "", "", "", "", "",
404 "", "", "", "", "", "", "", "",
410 } mips_processor_type_table
[] = {
411 { "generic", mips_generic_reg_names
},
412 { "r3041", mips_r3041_reg_names
},
413 { "r3051", mips_r3051_reg_names
},
414 { "r3071", mips_r3081_reg_names
},
415 { "r3081", mips_r3081_reg_names
},
416 { "lsi33k", mips_lsi33k_reg_names
},
424 /* Table to translate MIPS16 register field to actual register number. */
425 static int mips16_to_32_reg
[8] =
426 {16, 17, 2, 3, 4, 5, 6, 7};
428 /* Heuristic_proc_start may hunt through the text section for a long
429 time across a 2400 baud serial line. Allows the user to limit this
432 static unsigned int heuristic_fence_post
= 0;
434 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
435 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
436 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
437 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
438 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
439 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
440 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
441 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
442 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
443 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
444 /* FIXME drow/2002-06-10: If a pointer on the host is bigger than a long,
445 this will corrupt pdr.iline. Fortunately we don't use it. */
446 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
447 #define _PROC_MAGIC_ 0x0F0F0F0F
448 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
449 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
451 struct linked_proc_info
453 struct mips_extra_func_info info
;
454 struct linked_proc_info
*next
;
456 *linked_proc_desc_table
= NULL
;
459 mips_print_extra_frame_info (struct frame_info
*fi
)
463 && fi
->extra_info
->proc_desc
464 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
465 printf_filtered (" frame pointer is at %s+%s\n",
466 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
467 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
470 /* Number of bytes of storage in the actual machine representation for
471 register N. NOTE: This indirectly defines the register size
472 transfered by the GDB protocol. */
474 static int mips64_transfers_32bit_regs_p
= 0;
477 mips_register_raw_size (int reg_nr
)
479 if (mips64_transfers_32bit_regs_p
)
480 return REGISTER_VIRTUAL_SIZE (reg_nr
);
481 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
482 && FP_REGISTER_DOUBLE
)
483 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
490 /* Convert between RAW and VIRTUAL registers. The RAW register size
491 defines the remote-gdb packet. */
494 mips_register_convertible (int reg_nr
)
496 if (mips64_transfers_32bit_regs_p
)
499 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
503 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
504 char *raw_buf
, char *virt_buf
)
506 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
508 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
509 TYPE_LENGTH (virtual_type
));
513 TYPE_LENGTH (virtual_type
));
517 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
518 char *virt_buf
, char *raw_buf
)
520 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
521 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
522 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
524 TYPE_LENGTH (virtual_type
));
528 TYPE_LENGTH (virtual_type
));
532 mips_register_convert_to_type (int regnum
, struct type
*type
, char *buffer
)
534 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
535 && REGISTER_RAW_SIZE (regnum
) == 4
536 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
537 && TYPE_CODE(type
) == TYPE_CODE_FLT
538 && TYPE_LENGTH(type
) == 8)
541 memcpy (temp
, ((char *)(buffer
))+4, 4);
542 memcpy (((char *)(buffer
))+4, (buffer
), 4);
543 memcpy (((char *)(buffer
)), temp
, 4);
548 mips_register_convert_from_type (int regnum
, struct type
*type
, char *buffer
)
550 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
551 && REGISTER_RAW_SIZE (regnum
) == 4
552 && (regnum
) >= FP0_REGNUM
&& (regnum
) < FP0_REGNUM
+ 32
553 && TYPE_CODE(type
) == TYPE_CODE_FLT
554 && TYPE_LENGTH(type
) == 8)
557 memcpy (temp
, ((char *)(buffer
))+4, 4);
558 memcpy (((char *)(buffer
))+4, (buffer
), 4);
559 memcpy (((char *)(buffer
)), temp
, 4);
563 /* Return the GDB type object for the "standard" data type
564 of data in register REG.
566 Note: kevinb/2002-08-01: The definition below should faithfully
567 reproduce the behavior of each of the REGISTER_VIRTUAL_TYPE
568 definitions found in config/mips/tm-*.h. I'm concerned about
569 the ``FCRCS_REGNUM <= reg && reg <= LAST_EMBED_REGNUM'' clause
570 though. In some cases FP_REGNUM is in this range, and I doubt
571 that this code is correct for the 64-bit case. */
574 mips_register_virtual_type (int reg
)
576 if (FP0_REGNUM
<= reg
&& reg
< FP0_REGNUM
+ 32)
578 /* Floating point registers... */
579 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
580 return builtin_type_ieee_double_big
;
582 return builtin_type_ieee_double_little
;
584 else if (reg
== PS_REGNUM
/* CR */)
585 return builtin_type_uint32
;
586 else if (FCRCS_REGNUM
<= reg
&& reg
<= LAST_EMBED_REGNUM
)
587 return builtin_type_uint32
;
590 /* Everything else...
591 Return type appropriate for width of register. */
592 if (MIPS_REGSIZE
== TYPE_LENGTH (builtin_type_uint64
))
593 return builtin_type_uint64
;
595 return builtin_type_uint32
;
599 /* TARGET_READ_SP -- Remove useless bits from the stack pointer. */
604 return ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
607 /* Should the upper word of 64-bit addresses be zeroed? */
608 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
611 mips_mask_address_p (void)
613 switch (mask_address_var
)
615 case AUTO_BOOLEAN_TRUE
:
617 case AUTO_BOOLEAN_FALSE
:
620 case AUTO_BOOLEAN_AUTO
:
621 return MIPS_DEFAULT_MASK_ADDRESS_P
;
623 internal_error (__FILE__
, __LINE__
,
624 "mips_mask_address_p: bad switch");
630 show_mask_address (char *cmd
, int from_tty
, struct cmd_list_element
*c
)
632 switch (mask_address_var
)
634 case AUTO_BOOLEAN_TRUE
:
635 printf_filtered ("The 32 bit mips address mask is enabled\n");
637 case AUTO_BOOLEAN_FALSE
:
638 printf_filtered ("The 32 bit mips address mask is disabled\n");
640 case AUTO_BOOLEAN_AUTO
:
641 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
642 mips_mask_address_p () ? "enabled" : "disabled");
645 internal_error (__FILE__
, __LINE__
,
646 "show_mask_address: bad switch");
651 /* Should call_function allocate stack space for a struct return? */
654 mips_eabi_use_struct_convention (int gcc_p
, struct type
*type
)
656 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
660 mips_n32n64_use_struct_convention (int gcc_p
, struct type
*type
)
662 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
666 mips_o32_use_struct_convention (int gcc_p
, struct type
*type
)
668 return 1; /* Structures are returned by ref in extra arg0. */
671 /* Should call_function pass struct by reference?
672 For each architecture, structs are passed either by
673 value or by reference, depending on their size. */
676 mips_eabi_reg_struct_has_addr (int gcc_p
, struct type
*type
)
678 enum type_code typecode
= TYPE_CODE (check_typedef (type
));
679 int len
= TYPE_LENGTH (check_typedef (type
));
681 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
682 return (len
> MIPS_SAVED_REGSIZE
);
688 mips_n32n64_reg_struct_has_addr (int gcc_p
, struct type
*type
)
690 return 0; /* Assumption: N32/N64 never passes struct by ref. */
694 mips_o32_reg_struct_has_addr (int gcc_p
, struct type
*type
)
696 return 0; /* Assumption: O32/O64 never passes struct by ref. */
699 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
702 pc_is_mips16 (bfd_vma memaddr
)
704 struct minimal_symbol
*sym
;
706 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
707 if (IS_MIPS16_ADDR (memaddr
))
710 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
711 the high bit of the info field. Use this to decide if the function is
712 MIPS16 or normal MIPS. */
713 sym
= lookup_minimal_symbol_by_pc (memaddr
);
715 return MSYMBOL_IS_SPECIAL (sym
);
720 /* MIPS believes that the PC has a sign extended value. Perhaphs the
721 all registers should be sign extended for simplicity? */
724 mips_read_pc (ptid_t ptid
)
726 return read_signed_register_pid (PC_REGNUM
, ptid
);
729 /* This returns the PC of the first inst after the prologue. If we can't
730 find the prologue, then return 0. */
733 after_prologue (CORE_ADDR pc
,
734 mips_extra_func_info_t proc_desc
)
736 struct symtab_and_line sal
;
737 CORE_ADDR func_addr
, func_end
;
739 /* Pass cur_frame == 0 to find_proc_desc. We should not attempt
740 to read the stack pointer from the current machine state, because
741 the current machine state has nothing to do with the information
742 we need from the proc_desc; and the process may or may not exist
745 proc_desc
= find_proc_desc (pc
, NULL
, 0);
749 /* If function is frameless, then we need to do it the hard way. I
750 strongly suspect that frameless always means prologueless... */
751 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
752 && PROC_FRAME_OFFSET (proc_desc
) == 0)
756 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
757 return 0; /* Unknown */
759 sal
= find_pc_line (func_addr
, 0);
761 if (sal
.end
< func_end
)
764 /* The line after the prologue is after the end of the function. In this
765 case, tell the caller to find the prologue the hard way. */
770 /* Decode a MIPS32 instruction that saves a register in the stack, and
771 set the appropriate bit in the general register mask or float register mask
772 to indicate which register is saved. This is a helper function
773 for mips_find_saved_regs. */
776 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
777 unsigned long *float_mask
)
781 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
782 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
783 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
785 /* It might be possible to use the instruction to
786 find the offset, rather than the code below which
787 is based on things being in a certain order in the
788 frame, but figuring out what the instruction's offset
789 is relative to might be a little tricky. */
790 reg
= (inst
& 0x001f0000) >> 16;
791 *gen_mask
|= (1 << reg
);
793 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
794 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
795 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
798 reg
= ((inst
& 0x001f0000) >> 16);
799 *float_mask
|= (1 << reg
);
803 /* Decode a MIPS16 instruction that saves a register in the stack, and
804 set the appropriate bit in the general register or float register mask
805 to indicate which register is saved. This is a helper function
806 for mips_find_saved_regs. */
809 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
811 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
813 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
814 *gen_mask
|= (1 << reg
);
816 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
818 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
819 *gen_mask
|= (1 << reg
);
821 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
822 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
823 *gen_mask
|= (1 << RA_REGNUM
);
827 /* Fetch and return instruction from the specified location. If the PC
828 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
831 mips_fetch_instruction (CORE_ADDR addr
)
833 char buf
[MIPS_INSTLEN
];
837 if (pc_is_mips16 (addr
))
839 instlen
= MIPS16_INSTLEN
;
840 addr
= UNMAKE_MIPS16_ADDR (addr
);
843 instlen
= MIPS_INSTLEN
;
844 status
= read_memory_nobpt (addr
, buf
, instlen
);
846 memory_error (status
, addr
);
847 return extract_unsigned_integer (buf
, instlen
);
851 /* These the fields of 32 bit mips instructions */
852 #define mips32_op(x) (x >> 26)
853 #define itype_op(x) (x >> 26)
854 #define itype_rs(x) ((x >> 21) & 0x1f)
855 #define itype_rt(x) ((x >> 16) & 0x1f)
856 #define itype_immediate(x) (x & 0xffff)
858 #define jtype_op(x) (x >> 26)
859 #define jtype_target(x) (x & 0x03ffffff)
861 #define rtype_op(x) (x >> 26)
862 #define rtype_rs(x) ((x >> 21) & 0x1f)
863 #define rtype_rt(x) ((x >> 16) & 0x1f)
864 #define rtype_rd(x) ((x >> 11) & 0x1f)
865 #define rtype_shamt(x) ((x >> 6) & 0x1f)
866 #define rtype_funct(x) (x & 0x3f)
869 mips32_relative_offset (unsigned long inst
)
872 x
= itype_immediate (inst
);
873 if (x
& 0x8000) /* sign bit set */
875 x
|= 0xffff0000; /* sign extension */
881 /* Determine whate to set a single step breakpoint while considering
884 mips32_next_pc (CORE_ADDR pc
)
888 inst
= mips_fetch_instruction (pc
);
889 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
891 if (itype_op (inst
) >> 2 == 5)
892 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
894 op
= (itype_op (inst
) & 0x03);
909 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
910 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
912 int tf
= itype_rt (inst
) & 0x01;
913 int cnum
= itype_rt (inst
) >> 2;
914 int fcrcs
= read_signed_register (FCRCS_REGNUM
);
915 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
917 if (((cond
>> cnum
) & 0x01) == tf
)
918 pc
+= mips32_relative_offset (inst
) + 4;
923 pc
+= 4; /* Not a branch, next instruction is easy */
926 { /* This gets way messy */
928 /* Further subdivide into SPECIAL, REGIMM and other */
929 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
931 case 0: /* SPECIAL */
932 op
= rtype_funct (inst
);
937 /* Set PC to that address */
938 pc
= read_signed_register (rtype_rs (inst
));
944 break; /* end SPECIAL */
947 op
= itype_rt (inst
); /* branch condition */
952 case 16: /* BLTZAL */
953 case 18: /* BLTZALL */
955 if (read_signed_register (itype_rs (inst
)) < 0)
956 pc
+= mips32_relative_offset (inst
) + 4;
958 pc
+= 8; /* after the delay slot */
962 case 17: /* BGEZAL */
963 case 19: /* BGEZALL */
964 greater_equal_branch
:
965 if (read_signed_register (itype_rs (inst
)) >= 0)
966 pc
+= mips32_relative_offset (inst
) + 4;
968 pc
+= 8; /* after the delay slot */
970 /* All of the other instructions in the REGIMM category */
975 break; /* end REGIMM */
980 reg
= jtype_target (inst
) << 2;
981 /* Upper four bits get never changed... */
982 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
985 /* FIXME case JALX : */
988 reg
= jtype_target (inst
) << 2;
989 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
990 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
992 break; /* The new PC will be alternate mode */
993 case 4: /* BEQ, BEQL */
995 if (read_signed_register (itype_rs (inst
)) ==
996 read_signed_register (itype_rt (inst
)))
997 pc
+= mips32_relative_offset (inst
) + 4;
1001 case 5: /* BNE, BNEL */
1003 if (read_signed_register (itype_rs (inst
)) !=
1004 read_signed_register (itype_rt (inst
)))
1005 pc
+= mips32_relative_offset (inst
) + 4;
1009 case 6: /* BLEZ, BLEZL */
1011 if (read_signed_register (itype_rs (inst
) <= 0))
1012 pc
+= mips32_relative_offset (inst
) + 4;
1018 greater_branch
: /* BGTZ, BGTZL */
1019 if (read_signed_register (itype_rs (inst
) > 0))
1020 pc
+= mips32_relative_offset (inst
) + 4;
1027 } /* mips32_next_pc */
1029 /* Decoding the next place to set a breakpoint is irregular for the
1030 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1031 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1032 We dont want to set a single step instruction on the extend instruction
1036 /* Lots of mips16 instruction formats */
1037 /* Predicting jumps requires itype,ritype,i8type
1038 and their extensions extItype,extritype,extI8type
1040 enum mips16_inst_fmts
1042 itype
, /* 0 immediate 5,10 */
1043 ritype
, /* 1 5,3,8 */
1044 rrtype
, /* 2 5,3,3,5 */
1045 rritype
, /* 3 5,3,3,5 */
1046 rrrtype
, /* 4 5,3,3,3,2 */
1047 rriatype
, /* 5 5,3,3,1,4 */
1048 shifttype
, /* 6 5,3,3,3,2 */
1049 i8type
, /* 7 5,3,8 */
1050 i8movtype
, /* 8 5,3,3,5 */
1051 i8mov32rtype
, /* 9 5,3,5,3 */
1052 i64type
, /* 10 5,3,8 */
1053 ri64type
, /* 11 5,3,3,5 */
1054 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1055 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1056 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1057 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1058 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1059 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1060 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1061 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1062 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1063 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1065 /* I am heaping all the fields of the formats into one structure and
1066 then, only the fields which are involved in instruction extension */
1070 unsigned int regx
; /* Function in i8 type */
1075 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1076 for the bits which make up the immediatate extension. */
1079 extended_offset (unsigned int extension
)
1082 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1084 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1086 value
|= extension
& 0x01f; /* extract 4:0 */
1090 /* Only call this function if you know that this is an extendable
1091 instruction, It wont malfunction, but why make excess remote memory references?
1092 If the immediate operands get sign extended or somthing, do it after
1093 the extension is performed.
1095 /* FIXME: Every one of these cases needs to worry about sign extension
1096 when the offset is to be used in relative addressing */
1100 fetch_mips_16 (CORE_ADDR pc
)
1103 pc
&= 0xfffffffe; /* clear the low order bit */
1104 target_read_memory (pc
, buf
, 2);
1105 return extract_unsigned_integer (buf
, 2);
1109 unpack_mips16 (CORE_ADDR pc
,
1110 unsigned int extension
,
1112 enum mips16_inst_fmts insn_format
,
1113 struct upk_mips16
*upk
)
1118 switch (insn_format
)
1125 value
= extended_offset (extension
);
1126 value
= value
<< 11; /* rom for the original value */
1127 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1131 value
= inst
& 0x7ff;
1132 /* FIXME : Consider sign extension */
1141 { /* A register identifier and an offset */
1142 /* Most of the fields are the same as I type but the
1143 immediate value is of a different length */
1147 value
= extended_offset (extension
);
1148 value
= value
<< 8; /* from the original instruction */
1149 value
|= inst
& 0xff; /* eleven bits from instruction */
1150 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1151 if (value
& 0x4000) /* test the sign bit , bit 26 */
1153 value
&= ~0x3fff; /* remove the sign bit */
1159 value
= inst
& 0xff; /* 8 bits */
1160 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1161 /* FIXME: Do sign extension , this format needs it */
1162 if (value
& 0x80) /* THIS CONFUSES ME */
1164 value
&= 0xef; /* remove the sign bit */
1174 unsigned long value
;
1175 unsigned int nexthalf
;
1176 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1177 value
= value
<< 16;
1178 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1186 internal_error (__FILE__
, __LINE__
,
1189 upk
->offset
= offset
;
1196 add_offset_16 (CORE_ADDR pc
, int offset
)
1198 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1202 extended_mips16_next_pc (CORE_ADDR pc
,
1203 unsigned int extension
,
1206 int op
= (insn
>> 11);
1209 case 2: /* Branch */
1212 struct upk_mips16 upk
;
1213 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1214 offset
= upk
.offset
;
1220 pc
+= (offset
<< 1) + 2;
1223 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1225 struct upk_mips16 upk
;
1226 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1227 pc
= add_offset_16 (pc
, upk
.offset
);
1228 if ((insn
>> 10) & 0x01) /* Exchange mode */
1229 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1236 struct upk_mips16 upk
;
1238 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1239 reg
= read_signed_register (upk
.regx
);
1241 pc
+= (upk
.offset
<< 1) + 2;
1248 struct upk_mips16 upk
;
1250 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1251 reg
= read_signed_register (upk
.regx
);
1253 pc
+= (upk
.offset
<< 1) + 2;
1258 case 12: /* I8 Formats btez btnez */
1260 struct upk_mips16 upk
;
1262 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1263 /* upk.regx contains the opcode */
1264 reg
= read_signed_register (24); /* Test register is 24 */
1265 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1266 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1267 /* pc = add_offset_16(pc,upk.offset) ; */
1268 pc
+= (upk
.offset
<< 1) + 2;
1273 case 29: /* RR Formats JR, JALR, JALR-RA */
1275 struct upk_mips16 upk
;
1276 /* upk.fmt = rrtype; */
1281 upk
.regx
= (insn
>> 8) & 0x07;
1282 upk
.regy
= (insn
>> 5) & 0x07;
1290 break; /* Function return instruction */
1296 break; /* BOGUS Guess */
1298 pc
= read_signed_register (reg
);
1305 /* This is an instruction extension. Fetch the real instruction
1306 (which follows the extension) and decode things based on
1310 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1323 mips16_next_pc (CORE_ADDR pc
)
1325 unsigned int insn
= fetch_mips_16 (pc
);
1326 return extended_mips16_next_pc (pc
, 0, insn
);
1329 /* The mips_next_pc function supports single_step when the remote
1330 target monitor or stub is not developed enough to do a single_step.
1331 It works by decoding the current instruction and predicting where a
1332 branch will go. This isnt hard because all the data is available.
1333 The MIPS32 and MIPS16 variants are quite different */
1335 mips_next_pc (CORE_ADDR pc
)
1338 return mips16_next_pc (pc
);
1340 return mips32_next_pc (pc
);
1343 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1346 Note: kevinb/2002-08-09: The only caller of this function is (and
1347 should remain) mips_frame_init_saved_regs(). In fact,
1348 aside from calling mips_find_saved_regs(), mips_frame_init_saved_regs()
1349 does nothing more than set frame->saved_regs[SP_REGNUM]. These two
1350 functions should really be combined and now that there is only one
1351 caller, it should be straightforward. (Watch out for multiple returns
1355 mips_find_saved_regs (struct frame_info
*fci
)
1358 CORE_ADDR reg_position
;
1359 /* r0 bit means kernel trap */
1361 /* What registers have been saved? Bitmasks. */
1362 unsigned long gen_mask
, float_mask
;
1363 mips_extra_func_info_t proc_desc
;
1366 frame_saved_regs_zalloc (fci
);
1368 /* If it is the frame for sigtramp, the saved registers are located
1369 in a sigcontext structure somewhere on the stack.
1370 If the stack layout for sigtramp changes we might have to change these
1371 constants and the companion fixup_sigtramp in mdebugread.c */
1372 #ifndef SIGFRAME_BASE
1373 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1374 above the sigtramp frame. */
1375 #define SIGFRAME_BASE MIPS_REGSIZE
1376 /* FIXME! Are these correct?? */
1377 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1378 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1379 #define SIGFRAME_FPREGSAVE_OFF \
1380 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1382 #ifndef SIGFRAME_REG_SIZE
1383 /* FIXME! Is this correct?? */
1384 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1386 if (fci
->signal_handler_caller
)
1388 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1390 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1391 + ireg
* SIGFRAME_REG_SIZE
;
1392 fci
->saved_regs
[ireg
] = reg_position
;
1394 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1396 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1397 + ireg
* SIGFRAME_REG_SIZE
;
1398 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1400 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1404 proc_desc
= fci
->extra_info
->proc_desc
;
1405 if (proc_desc
== NULL
)
1406 /* I'm not sure how/whether this can happen. Normally when we can't
1407 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1408 and set the saved_regs right away. */
1411 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1412 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1413 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1415 if ( /* In any frame other than the innermost or a frame interrupted by
1416 a signal, we assume that all registers have been saved.
1417 This assumes that all register saves in a function happen before
1418 the first function call. */
1419 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1421 /* In a dummy frame we know exactly where things are saved. */
1422 && !PROC_DESC_IS_DUMMY (proc_desc
)
1424 /* Don't bother unless we are inside a function prologue. Outside the
1425 prologue, we know where everything is. */
1427 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1429 /* Not sure exactly what kernel_trap means, but if it means
1430 the kernel saves the registers without a prologue doing it,
1431 we better not examine the prologue to see whether registers
1432 have been saved yet. */
1435 /* We need to figure out whether the registers that the proc_desc
1436 claims are saved have been saved yet. */
1440 /* Bitmasks; set if we have found a save for the register. */
1441 unsigned long gen_save_found
= 0;
1442 unsigned long float_save_found
= 0;
1445 /* If the address is odd, assume this is MIPS16 code. */
1446 addr
= PROC_LOW_ADDR (proc_desc
);
1447 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1449 /* Scan through this function's instructions preceding the current
1450 PC, and look for those that save registers. */
1451 while (addr
< fci
->pc
)
1453 inst
= mips_fetch_instruction (addr
);
1454 if (pc_is_mips16 (addr
))
1455 mips16_decode_reg_save (inst
, &gen_save_found
);
1457 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1460 gen_mask
= gen_save_found
;
1461 float_mask
= float_save_found
;
1464 /* Fill in the offsets for the registers which gen_mask says
1466 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1467 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1468 if (gen_mask
& 0x80000000)
1470 fci
->saved_regs
[ireg
] = reg_position
;
1471 reg_position
-= MIPS_SAVED_REGSIZE
;
1474 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1475 of that normally used by gcc. Therefore, we have to fetch the first
1476 instruction of the function, and if it's an entry instruction that
1477 saves $s0 or $s1, correct their saved addresses. */
1478 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1480 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1481 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1484 int sreg_count
= (inst
>> 6) & 3;
1486 /* Check if the ra register was pushed on the stack. */
1487 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1489 reg_position
-= MIPS_SAVED_REGSIZE
;
1491 /* Check if the s0 and s1 registers were pushed on the stack. */
1492 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1494 fci
->saved_regs
[reg
] = reg_position
;
1495 reg_position
-= MIPS_SAVED_REGSIZE
;
1500 /* Fill in the offsets for the registers which float_mask says
1502 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1504 /* Apparently, the freg_offset gives the offset to the first 64 bit
1507 When the ABI specifies 64 bit saved registers, the FREG_OFFSET
1508 designates the first saved 64 bit register.
1510 When the ABI specifies 32 bit saved registers, the ``64 bit saved
1511 DOUBLE'' consists of two adjacent 32 bit registers, Hence
1512 FREG_OFFSET, designates the address of the lower register of the
1513 register pair. Adjust the offset so that it designates the upper
1514 register of the pair -- i.e., the address of the first saved 32
1517 if (MIPS_SAVED_REGSIZE
== 4)
1518 reg_position
+= MIPS_SAVED_REGSIZE
;
1520 /* Fill in the offsets for the float registers which float_mask says
1522 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1523 if (float_mask
& 0x80000000)
1525 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1526 reg_position
-= MIPS_SAVED_REGSIZE
;
1529 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1532 /* Set up the 'saved_regs' array. This is a data structure containing
1533 the addresses on the stack where each register has been saved, for
1534 each stack frame. Registers that have not been saved will have
1535 zero here. The stack pointer register is special: rather than the
1536 address where the stack register has been saved, saved_regs[SP_REGNUM]
1537 will have the actual value of the previous frame's stack register. */
1540 mips_frame_init_saved_regs (struct frame_info
*frame
)
1542 if (frame
->saved_regs
== NULL
)
1544 mips_find_saved_regs (frame
);
1546 frame
->saved_regs
[SP_REGNUM
] = frame
->frame
;
1550 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1552 for (; fi
; fi
= fi
->next
)
1554 /* We have to get the saved sp from the sigcontext
1555 if it is a signal handler frame. */
1556 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1560 if (fi
->saved_regs
== NULL
)
1561 FRAME_INIT_SAVED_REGS (fi
);
1562 if (fi
->saved_regs
[regno
])
1563 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1566 return read_signed_register (regno
);
1569 /* mips_addr_bits_remove - remove useless address bits */
1572 mips_addr_bits_remove (CORE_ADDR addr
)
1574 if (GDB_TARGET_IS_MIPS64
)
1576 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1578 /* This hack is a work-around for existing boards using
1579 PMON, the simulator, and any other 64-bit targets that
1580 doesn't have true 64-bit addressing. On these targets,
1581 the upper 32 bits of addresses are ignored by the
1582 hardware. Thus, the PC or SP are likely to have been
1583 sign extended to all 1s by instruction sequences that
1584 load 32-bit addresses. For example, a typical piece of
1585 code that loads an address is this:
1586 lui $r2, <upper 16 bits>
1587 ori $r2, <lower 16 bits>
1588 But the lui sign-extends the value such that the upper 32
1589 bits may be all 1s. The workaround is simply to mask off
1590 these bits. In the future, gcc may be changed to support
1591 true 64-bit addressing, and this masking will have to be
1593 addr
&= (CORE_ADDR
) 0xffffffff;
1596 else if (mips_mask_address_p ())
1598 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1599 masking off bits, instead, the actual target should be asking
1600 for the address to be converted to a valid pointer. */
1601 /* Even when GDB is configured for some 32-bit targets
1602 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1603 so CORE_ADDR is 64 bits. So we still have to mask off
1604 useless bits from addresses. */
1605 addr
&= (CORE_ADDR
) 0xffffffff;
1610 /* mips_software_single_step() is called just before we want to resume
1611 the inferior, if we want to single-step it but there is no hardware
1612 or kernel single-step support (MIPS on GNU/Linux for example). We find
1613 the target of the coming instruction and breakpoint it.
1615 single_step is also called just after the inferior stops. If we had
1616 set up a simulated single-step, we undo our damage. */
1619 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1621 static CORE_ADDR next_pc
;
1622 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1623 static binsn_quantum break_mem
;
1626 if (insert_breakpoints_p
)
1628 pc
= read_register (PC_REGNUM
);
1629 next_pc
= mips_next_pc (pc
);
1631 target_insert_breakpoint (next_pc
, break_mem
);
1634 target_remove_breakpoint (next_pc
, break_mem
);
1638 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1642 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1643 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1644 tmp
= mips_skip_stub (pc
);
1645 prev
->pc
= tmp
? tmp
: pc
;
1650 mips_frame_saved_pc (struct frame_info
*frame
)
1653 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1654 /* We have to get the saved pc from the sigcontext
1655 if it is a signal handler frame. */
1656 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1657 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1659 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1660 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1662 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1664 return ADDR_BITS_REMOVE (saved_pc
);
1667 static struct mips_extra_func_info temp_proc_desc
;
1668 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1670 /* Set a register's saved stack address in temp_saved_regs. If an address
1671 has already been set for this register, do nothing; this way we will
1672 only recognize the first save of a given register in a function prologue.
1673 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1676 set_reg_offset (int regno
, CORE_ADDR offset
)
1678 if (temp_saved_regs
[regno
] == 0)
1679 temp_saved_regs
[regno
] = offset
;
1683 /* Test whether the PC points to the return instruction at the
1684 end of a function. */
1687 mips_about_to_return (CORE_ADDR pc
)
1689 if (pc_is_mips16 (pc
))
1690 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1691 generates a "jr $ra"; other times it generates code to load
1692 the return address from the stack to an accessible register (such
1693 as $a3), then a "jr" using that register. This second case
1694 is almost impossible to distinguish from an indirect jump
1695 used for switch statements, so we don't even try. */
1696 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1698 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1702 /* This fencepost looks highly suspicious to me. Removing it also
1703 seems suspicious as it could affect remote debugging across serial
1707 heuristic_proc_start (CORE_ADDR pc
)
1714 pc
= ADDR_BITS_REMOVE (pc
);
1716 fence
= start_pc
- heuristic_fence_post
;
1720 if (heuristic_fence_post
== UINT_MAX
1721 || fence
< VM_MIN_ADDRESS
)
1722 fence
= VM_MIN_ADDRESS
;
1724 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1726 /* search back for previous return */
1727 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1728 if (start_pc
< fence
)
1730 /* It's not clear to me why we reach this point when
1731 stop_soon_quietly, but with this test, at least we
1732 don't print out warnings for every child forked (eg, on
1733 decstation). 22apr93 rich@cygnus.com. */
1734 if (!stop_soon_quietly
)
1736 static int blurb_printed
= 0;
1738 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1743 /* This actually happens frequently in embedded
1744 development, when you first connect to a board
1745 and your stack pointer and pc are nowhere in
1746 particular. This message needs to give people
1747 in that situation enough information to
1748 determine that it's no big deal. */
1749 printf_filtered ("\n\
1750 GDB is unable to find the start of the function at 0x%s\n\
1751 and thus can't determine the size of that function's stack frame.\n\
1752 This means that GDB may be unable to access that stack frame, or\n\
1753 the frames below it.\n\
1754 This problem is most likely caused by an invalid program counter or\n\
1756 However, if you think GDB should simply search farther back\n\
1757 from 0x%s for code which looks like the beginning of a\n\
1758 function, you can increase the range of the search using the `set\n\
1759 heuristic-fence-post' command.\n",
1760 paddr_nz (pc
), paddr_nz (pc
));
1767 else if (pc_is_mips16 (start_pc
))
1769 unsigned short inst
;
1771 /* On MIPS16, any one of the following is likely to be the
1772 start of a function:
1776 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1777 inst
= mips_fetch_instruction (start_pc
);
1778 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1779 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1780 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1781 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1783 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1784 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1789 else if (mips_about_to_return (start_pc
))
1791 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1798 /* Fetch the immediate value from a MIPS16 instruction.
1799 If the previous instruction was an EXTEND, use it to extend
1800 the upper bits of the immediate value. This is a helper function
1801 for mips16_heuristic_proc_desc. */
1804 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1805 unsigned short inst
, /* current instruction */
1806 int nbits
, /* number of bits in imm field */
1807 int scale
, /* scale factor to be applied to imm */
1808 int is_signed
) /* is the imm field signed? */
1812 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1814 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1815 if (offset
& 0x8000) /* check for negative extend */
1816 offset
= 0 - (0x10000 - (offset
& 0xffff));
1817 return offset
| (inst
& 0x1f);
1821 int max_imm
= 1 << nbits
;
1822 int mask
= max_imm
- 1;
1823 int sign_bit
= max_imm
>> 1;
1825 offset
= inst
& mask
;
1826 if (is_signed
&& (offset
& sign_bit
))
1827 offset
= 0 - (max_imm
- offset
);
1828 return offset
* scale
;
1833 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1834 stream from start_pc to limit_pc. */
1837 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1838 struct frame_info
*next_frame
, CORE_ADDR sp
)
1841 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1842 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1843 unsigned inst
= 0; /* current instruction */
1844 unsigned entry_inst
= 0; /* the entry instruction */
1847 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1848 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1850 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1852 /* Save the previous instruction. If it's an EXTEND, we'll extract
1853 the immediate offset extension from it in mips16_get_imm. */
1856 /* Fetch and decode the instruction. */
1857 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1858 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1859 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1861 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1862 if (offset
< 0) /* negative stack adjustment? */
1863 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1865 /* Exit loop if a positive stack adjustment is found, which
1866 usually means that the stack cleanup code in the function
1867 epilogue is reached. */
1870 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1872 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1873 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1874 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1875 set_reg_offset (reg
, sp
+ offset
);
1877 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1879 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1880 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1881 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1882 set_reg_offset (reg
, sp
+ offset
);
1884 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1886 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1887 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1888 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1890 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1892 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1893 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1894 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1896 else if (inst
== 0x673d) /* move $s1, $sp */
1899 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1901 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1903 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1904 frame_addr
= sp
+ offset
;
1905 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1906 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1908 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1910 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1911 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1912 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1913 set_reg_offset (reg
, frame_addr
+ offset
);
1915 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1917 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1918 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1919 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1920 set_reg_offset (reg
, frame_addr
+ offset
);
1922 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1923 entry_inst
= inst
; /* save for later processing */
1924 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1925 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1928 /* The entry instruction is typically the first instruction in a function,
1929 and it stores registers at offsets relative to the value of the old SP
1930 (before the prologue). But the value of the sp parameter to this
1931 function is the new SP (after the prologue has been executed). So we
1932 can't calculate those offsets until we've seen the entire prologue,
1933 and can calculate what the old SP must have been. */
1934 if (entry_inst
!= 0)
1936 int areg_count
= (entry_inst
>> 8) & 7;
1937 int sreg_count
= (entry_inst
>> 6) & 3;
1939 /* The entry instruction always subtracts 32 from the SP. */
1940 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1942 /* Now we can calculate what the SP must have been at the
1943 start of the function prologue. */
1944 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1946 /* Check if a0-a3 were saved in the caller's argument save area. */
1947 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1949 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1950 set_reg_offset (reg
, sp
+ offset
);
1951 offset
+= MIPS_SAVED_REGSIZE
;
1954 /* Check if the ra register was pushed on the stack. */
1956 if (entry_inst
& 0x20)
1958 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1959 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1960 offset
-= MIPS_SAVED_REGSIZE
;
1963 /* Check if the s0 and s1 registers were pushed on the stack. */
1964 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1966 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1967 set_reg_offset (reg
, sp
+ offset
);
1968 offset
-= MIPS_SAVED_REGSIZE
;
1974 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1975 struct frame_info
*next_frame
, CORE_ADDR sp
)
1978 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1980 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1981 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1982 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1983 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1985 unsigned long inst
, high_word
, low_word
;
1988 /* Fetch the instruction. */
1989 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1991 /* Save some code by pre-extracting some useful fields. */
1992 high_word
= (inst
>> 16) & 0xffff;
1993 low_word
= inst
& 0xffff;
1994 reg
= high_word
& 0x1f;
1996 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1997 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1998 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2000 if (low_word
& 0x8000) /* negative stack adjustment? */
2001 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
2003 /* Exit loop if a positive stack adjustment is found, which
2004 usually means that the stack cleanup code in the function
2005 epilogue is reached. */
2008 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2010 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2011 set_reg_offset (reg
, sp
+ low_word
);
2013 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2015 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
2016 but the register size used is only 32 bits. Make the address
2017 for the saved register point to the lower 32 bits. */
2018 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2019 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
2021 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2023 /* Old gcc frame, r30 is virtual frame pointer. */
2024 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
2025 frame_addr
= sp
+ low_word
;
2026 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2028 unsigned alloca_adjust
;
2029 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2030 frame_addr
= read_next_frame_reg (next_frame
, 30);
2031 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2032 if (alloca_adjust
> 0)
2034 /* FP > SP + frame_size. This may be because
2035 * of an alloca or somethings similar.
2036 * Fix sp to "pre-alloca" value, and try again.
2038 sp
+= alloca_adjust
;
2043 /* move $30,$sp. With different versions of gas this will be either
2044 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2045 Accept any one of these. */
2046 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2048 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2049 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
2051 unsigned alloca_adjust
;
2052 PROC_FRAME_REG (&temp_proc_desc
) = 30;
2053 frame_addr
= read_next_frame_reg (next_frame
, 30);
2054 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2055 if (alloca_adjust
> 0)
2057 /* FP > SP + frame_size. This may be because
2058 * of an alloca or somethings similar.
2059 * Fix sp to "pre-alloca" value, and try again.
2061 sp
+= alloca_adjust
;
2066 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
2068 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
2069 set_reg_offset (reg
, frame_addr
+ low_word
);
2074 static mips_extra_func_info_t
2075 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2076 struct frame_info
*next_frame
, int cur_frame
)
2081 sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
2087 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
2088 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
2089 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
2090 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
2091 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
2093 if (start_pc
+ 200 < limit_pc
)
2094 limit_pc
= start_pc
+ 200;
2095 if (pc_is_mips16 (start_pc
))
2096 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2098 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
2099 return &temp_proc_desc
;
2102 struct mips_objfile_private
2108 /* Global used to communicate between non_heuristic_proc_desc and
2109 compare_pdr_entries within qsort (). */
2110 static bfd
*the_bfd
;
2113 compare_pdr_entries (const void *a
, const void *b
)
2115 CORE_ADDR lhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) a
);
2116 CORE_ADDR rhs
= bfd_get_32 (the_bfd
, (bfd_byte
*) b
);
2120 else if (lhs
== rhs
)
2126 static mips_extra_func_info_t
2127 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
2129 CORE_ADDR startaddr
;
2130 mips_extra_func_info_t proc_desc
;
2131 struct block
*b
= block_for_pc (pc
);
2133 struct obj_section
*sec
;
2134 struct mips_objfile_private
*priv
;
2136 if (PC_IN_CALL_DUMMY (pc
, 0, 0))
2139 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
2141 *addrptr
= startaddr
;
2145 sec
= find_pc_section (pc
);
2148 priv
= (struct mips_objfile_private
*) sec
->objfile
->obj_private
;
2150 /* Search the ".pdr" section generated by GAS. This includes most of
2151 the information normally found in ECOFF PDRs. */
2153 the_bfd
= sec
->objfile
->obfd
;
2155 && (the_bfd
->format
== bfd_object
2156 && bfd_get_flavour (the_bfd
) == bfd_target_elf_flavour
2157 && elf_elfheader (the_bfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
))
2159 /* Right now GAS only outputs the address as a four-byte sequence.
2160 This means that we should not bother with this method on 64-bit
2161 targets (until that is fixed). */
2163 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2164 sizeof (struct mips_objfile_private
));
2166 sec
->objfile
->obj_private
= priv
;
2168 else if (priv
== NULL
)
2172 priv
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2173 sizeof (struct mips_objfile_private
));
2175 bfdsec
= bfd_get_section_by_name (sec
->objfile
->obfd
, ".pdr");
2178 priv
->size
= bfd_section_size (sec
->objfile
->obfd
, bfdsec
);
2179 priv
->contents
= obstack_alloc (& sec
->objfile
->psymbol_obstack
,
2181 bfd_get_section_contents (sec
->objfile
->obfd
, bfdsec
,
2182 priv
->contents
, 0, priv
->size
);
2184 /* In general, the .pdr section is sorted. However, in the
2185 presence of multiple code sections (and other corner cases)
2186 it can become unsorted. Sort it so that we can use a faster
2188 qsort (priv
->contents
, priv
->size
/ 32, 32, compare_pdr_entries
);
2193 sec
->objfile
->obj_private
= priv
;
2197 if (priv
->size
!= 0)
2203 high
= priv
->size
/ 32;
2209 mid
= (low
+ high
) / 2;
2211 ptr
= priv
->contents
+ mid
* 32;
2212 pdr_pc
= bfd_get_signed_32 (sec
->objfile
->obfd
, ptr
);
2213 pdr_pc
+= ANOFFSET (sec
->objfile
->section_offsets
,
2214 SECT_OFF_TEXT (sec
->objfile
));
2215 if (pdr_pc
== startaddr
)
2217 if (pdr_pc
> startaddr
)
2222 while (low
!= high
);
2226 struct symbol
*sym
= find_pc_function (pc
);
2228 /* Fill in what we need of the proc_desc. */
2229 proc_desc
= (mips_extra_func_info_t
)
2230 obstack_alloc (&sec
->objfile
->psymbol_obstack
,
2231 sizeof (struct mips_extra_func_info
));
2232 PROC_LOW_ADDR (proc_desc
) = startaddr
;
2234 /* Only used for dummy frames. */
2235 PROC_HIGH_ADDR (proc_desc
) = 0;
2237 PROC_FRAME_OFFSET (proc_desc
)
2238 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 20);
2239 PROC_FRAME_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2241 PROC_FRAME_ADJUST (proc_desc
) = 0;
2242 PROC_REG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2244 PROC_FREG_MASK (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2246 PROC_REG_OFFSET (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2248 PROC_FREG_OFFSET (proc_desc
)
2249 = bfd_get_32 (sec
->objfile
->obfd
, ptr
+ 16);
2250 PROC_PC_REG (proc_desc
) = bfd_get_32 (sec
->objfile
->obfd
,
2252 proc_desc
->pdr
.isym
= (long) sym
;
2262 if (startaddr
> BLOCK_START (b
))
2264 /* This is the "pathological" case referred to in a comment in
2265 print_frame_info. It might be better to move this check into
2270 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
2272 /* If we never found a PDR for this function in symbol reading, then
2273 examine prologues to find the information. */
2276 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
2277 if (PROC_FRAME_REG (proc_desc
) == -1)
2287 static mips_extra_func_info_t
2288 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
, int cur_frame
)
2290 mips_extra_func_info_t proc_desc
;
2291 CORE_ADDR startaddr
;
2293 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
2297 /* IF this is the topmost frame AND
2298 * (this proc does not have debugging information OR
2299 * the PC is in the procedure prologue)
2300 * THEN create a "heuristic" proc_desc (by analyzing
2301 * the actual code) to replace the "official" proc_desc.
2303 if (next_frame
== NULL
)
2305 struct symtab_and_line val
;
2306 struct symbol
*proc_symbol
=
2307 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
2311 val
= find_pc_line (BLOCK_START
2312 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
2314 val
.pc
= val
.end
? val
.end
: pc
;
2316 if (!proc_symbol
|| pc
< val
.pc
)
2318 mips_extra_func_info_t found_heuristic
=
2319 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
2320 pc
, next_frame
, cur_frame
);
2321 if (found_heuristic
)
2322 proc_desc
= found_heuristic
;
2328 /* Is linked_proc_desc_table really necessary? It only seems to be used
2329 by procedure call dummys. However, the procedures being called ought
2330 to have their own proc_descs, and even if they don't,
2331 heuristic_proc_desc knows how to create them! */
2333 register struct linked_proc_info
*link
;
2335 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
2336 if (PROC_LOW_ADDR (&link
->info
) <= pc
2337 && PROC_HIGH_ADDR (&link
->info
) > pc
)
2341 startaddr
= heuristic_proc_start (pc
);
2344 heuristic_proc_desc (startaddr
, pc
, next_frame
, cur_frame
);
2350 get_frame_pointer (struct frame_info
*frame
,
2351 mips_extra_func_info_t proc_desc
)
2353 return ADDR_BITS_REMOVE (read_next_frame_reg (frame
,
2354 PROC_FRAME_REG (proc_desc
)) +
2355 PROC_FRAME_OFFSET (proc_desc
) -
2356 PROC_FRAME_ADJUST (proc_desc
));
2359 mips_extra_func_info_t cached_proc_desc
;
2362 mips_frame_chain (struct frame_info
*frame
)
2364 mips_extra_func_info_t proc_desc
;
2366 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
2368 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
2371 /* Check if the PC is inside a call stub. If it is, fetch the
2372 PC of the caller of that stub. */
2373 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
2376 /* Look up the procedure descriptor for this PC. */
2377 proc_desc
= find_proc_desc (saved_pc
, frame
, 1);
2381 cached_proc_desc
= proc_desc
;
2383 /* If no frame pointer and frame size is zero, we must be at end
2384 of stack (or otherwise hosed). If we don't check frame size,
2385 we loop forever if we see a zero size frame. */
2386 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2387 && PROC_FRAME_OFFSET (proc_desc
) == 0
2388 /* The previous frame from a sigtramp frame might be frameless
2389 and have frame size zero. */
2390 && !frame
->signal_handler_caller
2391 /* Check if this is a call dummy frame. */
2392 && frame
->pc
!= mips_call_dummy_address ())
2395 return get_frame_pointer (frame
, proc_desc
);
2399 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2403 /* Use proc_desc calculated in frame_chain */
2404 mips_extra_func_info_t proc_desc
=
2405 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
, 1);
2407 fci
->extra_info
= (struct frame_extra_info
*)
2408 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2410 fci
->saved_regs
= NULL
;
2411 fci
->extra_info
->proc_desc
=
2412 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2415 /* Fixup frame-pointer - only needed for top frame */
2416 /* This may not be quite right, if proc has a real frame register.
2417 Get the value of the frame relative sp, procedure might have been
2418 interrupted by a signal at it's very start. */
2419 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2420 && !PROC_DESC_IS_DUMMY (proc_desc
))
2421 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2423 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2425 if (proc_desc
== &temp_proc_desc
)
2429 /* Do not set the saved registers for a sigtramp frame,
2430 mips_find_saved_registers will do that for us.
2431 We can't use fci->signal_handler_caller, it is not yet set. */
2432 find_pc_partial_function (fci
->pc
, &name
,
2433 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2434 if (!PC_IN_SIGTRAMP (fci
->pc
, name
))
2436 frame_saved_regs_zalloc (fci
);
2437 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2438 fci
->saved_regs
[PC_REGNUM
]
2439 = fci
->saved_regs
[RA_REGNUM
];
2440 /* Set value of previous frame's stack pointer. Remember that
2441 saved_regs[SP_REGNUM] is special in that it contains the
2442 value of the stack pointer register. The other saved_regs
2443 values are addresses (in the inferior) at which a given
2444 register's value may be found. */
2445 fci
->saved_regs
[SP_REGNUM
] = fci
->frame
;
2449 /* hack: if argument regs are saved, guess these contain args */
2450 /* assume we can't tell how many args for now */
2451 fci
->extra_info
->num_args
= -1;
2452 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2454 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2456 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2463 /* MIPS stack frames are almost impenetrable. When execution stops,
2464 we basically have to look at symbol information for the function
2465 that we stopped in, which tells us *which* register (if any) is
2466 the base of the frame pointer, and what offset from that register
2467 the frame itself is at.
2469 This presents a problem when trying to examine a stack in memory
2470 (that isn't executing at the moment), using the "frame" command. We
2471 don't have a PC, nor do we have any registers except SP.
2473 This routine takes two arguments, SP and PC, and tries to make the
2474 cached frames look as if these two arguments defined a frame on the
2475 cache. This allows the rest of info frame to extract the important
2476 arguments without difficulty. */
2479 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2482 error ("MIPS frame specifications require two arguments: sp and pc");
2484 return create_new_frame (argv
[0], argv
[1]);
2487 /* According to the current ABI, should the type be passed in a
2488 floating-point register (assuming that there is space)? When there
2489 is no FPU, FP are not even considered as possibile candidates for
2490 FP registers and, consequently this returns false - forces FP
2491 arguments into integer registers. */
2494 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2496 return ((typecode
== TYPE_CODE_FLT
2498 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2499 && TYPE_NFIELDS (arg_type
) == 1
2500 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2501 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2504 /* On o32, argument passing in GPRs depends on the alignment of the type being
2505 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2508 mips_type_needs_double_align (struct type
*type
)
2510 enum type_code typecode
= TYPE_CODE (type
);
2512 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2514 else if (typecode
== TYPE_CODE_STRUCT
)
2516 if (TYPE_NFIELDS (type
) < 1)
2518 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2520 else if (typecode
== TYPE_CODE_UNION
)
2524 n
= TYPE_NFIELDS (type
);
2525 for (i
= 0; i
< n
; i
++)
2526 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2533 /* Macros to round N up or down to the next A boundary;
2534 A must be a power of two. */
2536 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2537 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2540 mips_eabi_push_arguments (int nargs
,
2541 struct value
**args
,
2544 CORE_ADDR struct_addr
)
2550 int stack_offset
= 0;
2552 /* First ensure that the stack and structure return address (if any)
2553 are properly aligned. The stack has to be at least 64-bit
2554 aligned even on 32-bit machines, because doubles must be 64-bit
2555 aligned. For n32 and n64, stack frames need to be 128-bit
2556 aligned, so we round to this widest known alignment. */
2558 sp
= ROUND_DOWN (sp
, 16);
2559 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2561 /* Now make space on the stack for the args. We allocate more
2562 than necessary for EABI, because the first few arguments are
2563 passed in registers, but that's OK. */
2564 for (argnum
= 0; argnum
< nargs
; argnum
++)
2565 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2566 MIPS_STACK_ARGSIZE
);
2567 sp
-= ROUND_UP (len
, 16);
2570 fprintf_unfiltered (gdb_stdlog
,
2571 "mips_eabi_push_arguments: sp=0x%s allocated %d\n",
2572 paddr_nz (sp
), ROUND_UP (len
, 16));
2574 /* Initialize the integer and float register pointers. */
2576 float_argreg
= FPA0_REGNUM
;
2578 /* The struct_return pointer occupies the first parameter-passing reg. */
2582 fprintf_unfiltered (gdb_stdlog
,
2583 "mips_eabi_push_arguments: struct_return reg=%d 0x%s\n",
2584 argreg
, paddr_nz (struct_addr
));
2585 write_register (argreg
++, struct_addr
);
2588 /* Now load as many as possible of the first arguments into
2589 registers, and push the rest onto the stack. Loop thru args
2590 from first to last. */
2591 for (argnum
= 0; argnum
< nargs
; argnum
++)
2594 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
2595 struct value
*arg
= args
[argnum
];
2596 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2597 int len
= TYPE_LENGTH (arg_type
);
2598 enum type_code typecode
= TYPE_CODE (arg_type
);
2601 fprintf_unfiltered (gdb_stdlog
,
2602 "mips_eabi_push_arguments: %d len=%d type=%d",
2603 argnum
+ 1, len
, (int) typecode
);
2605 /* The EABI passes structures that do not fit in a register by
2607 if (len
> MIPS_SAVED_REGSIZE
2608 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2610 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2611 typecode
= TYPE_CODE_PTR
;
2612 len
= MIPS_SAVED_REGSIZE
;
2615 fprintf_unfiltered (gdb_stdlog
, " push");
2618 val
= (char *) VALUE_CONTENTS (arg
);
2620 /* 32-bit ABIs always start floating point arguments in an
2621 even-numbered floating point register. Round the FP register
2622 up before the check to see if there are any FP registers
2623 left. Non MIPS_EABI targets also pass the FP in the integer
2624 registers so also round up normal registers. */
2625 if (!FP_REGISTER_DOUBLE
2626 && fp_register_arg_p (typecode
, arg_type
))
2628 if ((float_argreg
& 1))
2632 /* Floating point arguments passed in registers have to be
2633 treated specially. On 32-bit architectures, doubles
2634 are passed in register pairs; the even register gets
2635 the low word, and the odd register gets the high word.
2636 On non-EABI processors, the first two floating point arguments are
2637 also copied to general registers, because MIPS16 functions
2638 don't use float registers for arguments. This duplication of
2639 arguments in general registers can't hurt non-MIPS16 functions
2640 because those registers are normally skipped. */
2641 /* MIPS_EABI squeezes a struct that contains a single floating
2642 point value into an FP register instead of pushing it onto the
2644 if (fp_register_arg_p (typecode
, arg_type
)
2645 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2647 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2649 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
2650 unsigned long regval
;
2652 /* Write the low word of the double to the even register(s). */
2653 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2655 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2656 float_argreg
, phex (regval
, 4));
2657 write_register (float_argreg
++, regval
);
2659 /* Write the high word of the double to the odd register(s). */
2660 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2662 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2663 float_argreg
, phex (regval
, 4));
2664 write_register (float_argreg
++, regval
);
2668 /* This is a floating point value that fits entirely
2669 in a single register. */
2670 /* On 32 bit ABI's the float_argreg is further adjusted
2671 above to ensure that it is even register aligned. */
2672 LONGEST regval
= extract_unsigned_integer (val
, len
);
2674 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2675 float_argreg
, phex (regval
, len
));
2676 write_register (float_argreg
++, regval
);
2681 /* Copy the argument to general registers or the stack in
2682 register-sized pieces. Large arguments are split between
2683 registers and stack. */
2684 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2685 are treated specially: Irix cc passes them in registers
2686 where gcc sometimes puts them on the stack. For maximum
2687 compatibility, we will put them in both places. */
2688 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2689 (len
% MIPS_SAVED_REGSIZE
!= 0));
2691 /* Note: Floating-point values that didn't fit into an FP
2692 register are only written to memory. */
2695 /* Remember if the argument was written to the stack. */
2696 int stack_used_p
= 0;
2698 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2701 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2704 /* Write this portion of the argument to the stack. */
2705 if (argreg
> MIPS_LAST_ARG_REGNUM
2707 || fp_register_arg_p (typecode
, arg_type
))
2709 /* Should shorter than int integer values be
2710 promoted to int before being stored? */
2711 int longword_offset
= 0;
2714 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2716 if (MIPS_STACK_ARGSIZE
== 8 &&
2717 (typecode
== TYPE_CODE_INT
||
2718 typecode
== TYPE_CODE_PTR
||
2719 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2720 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2721 else if ((typecode
== TYPE_CODE_STRUCT
||
2722 typecode
== TYPE_CODE_UNION
) &&
2723 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2724 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2729 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2730 paddr_nz (stack_offset
));
2731 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2732 paddr_nz (longword_offset
));
2735 addr
= sp
+ stack_offset
+ longword_offset
;
2740 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2742 for (i
= 0; i
< partial_len
; i
++)
2744 fprintf_unfiltered (gdb_stdlog
, "%02x",
2748 write_memory (addr
, val
, partial_len
);
2751 /* Note!!! This is NOT an else clause. Odd sized
2752 structs may go thru BOTH paths. Floating point
2753 arguments will not. */
2754 /* Write this portion of the argument to a general
2755 purpose register. */
2756 if (argreg
<= MIPS_LAST_ARG_REGNUM
2757 && !fp_register_arg_p (typecode
, arg_type
))
2759 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2762 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2764 phex (regval
, MIPS_SAVED_REGSIZE
));
2765 write_register (argreg
, regval
);
2772 /* Compute the the offset into the stack at which we
2773 will copy the next parameter.
2775 In the new EABI (and the NABI32), the stack_offset
2776 only needs to be adjusted when it has been used. */
2779 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2783 fprintf_unfiltered (gdb_stdlog
, "\n");
2786 /* Return adjusted stack pointer. */
2790 /* N32/N64 version of push_arguments. */
2793 mips_n32n64_push_arguments (int nargs
,
2794 struct value
**args
,
2797 CORE_ADDR struct_addr
)
2803 int stack_offset
= 0;
2805 /* First ensure that the stack and structure return address (if any)
2806 are properly aligned. The stack has to be at least 64-bit
2807 aligned even on 32-bit machines, because doubles must be 64-bit
2808 aligned. For n32 and n64, stack frames need to be 128-bit
2809 aligned, so we round to this widest known alignment. */
2811 sp
= ROUND_DOWN (sp
, 16);
2812 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2814 /* Now make space on the stack for the args. */
2815 for (argnum
= 0; argnum
< nargs
; argnum
++)
2816 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
2817 MIPS_STACK_ARGSIZE
);
2818 sp
-= ROUND_UP (len
, 16);
2821 fprintf_unfiltered (gdb_stdlog
,
2822 "mips_n32n64_push_arguments: sp=0x%s allocated %d\n",
2823 paddr_nz (sp
), ROUND_UP (len
, 16));
2825 /* Initialize the integer and float register pointers. */
2827 float_argreg
= FPA0_REGNUM
;
2829 /* The struct_return pointer occupies the first parameter-passing reg. */
2833 fprintf_unfiltered (gdb_stdlog
,
2834 "mips_n32n64_push_arguments: struct_return reg=%d 0x%s\n",
2835 argreg
, paddr_nz (struct_addr
));
2836 write_register (argreg
++, struct_addr
);
2839 /* Now load as many as possible of the first arguments into
2840 registers, and push the rest onto the stack. Loop thru args
2841 from first to last. */
2842 for (argnum
= 0; argnum
< nargs
; argnum
++)
2845 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
2846 struct value
*arg
= args
[argnum
];
2847 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2848 int len
= TYPE_LENGTH (arg_type
);
2849 enum type_code typecode
= TYPE_CODE (arg_type
);
2852 fprintf_unfiltered (gdb_stdlog
,
2853 "mips_n32n64_push_arguments: %d len=%d type=%d",
2854 argnum
+ 1, len
, (int) typecode
);
2856 val
= (char *) VALUE_CONTENTS (arg
);
2858 if (fp_register_arg_p (typecode
, arg_type
)
2859 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2861 /* This is a floating point value that fits entirely
2862 in a single register. */
2863 /* On 32 bit ABI's the float_argreg is further adjusted
2864 above to ensure that it is even register aligned. */
2865 LONGEST regval
= extract_unsigned_integer (val
, len
);
2867 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2868 float_argreg
, phex (regval
, len
));
2869 write_register (float_argreg
++, regval
);
2872 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2873 argreg
, phex (regval
, len
));
2874 write_register (argreg
, regval
);
2879 /* Copy the argument to general registers or the stack in
2880 register-sized pieces. Large arguments are split between
2881 registers and stack. */
2882 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2883 are treated specially: Irix cc passes them in registers
2884 where gcc sometimes puts them on the stack. For maximum
2885 compatibility, we will put them in both places. */
2886 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2887 (len
% MIPS_SAVED_REGSIZE
!= 0));
2888 /* Note: Floating-point values that didn't fit into an FP
2889 register are only written to memory. */
2892 /* Rememer if the argument was written to the stack. */
2893 int stack_used_p
= 0;
2894 int partial_len
= len
< MIPS_SAVED_REGSIZE
?
2895 len
: MIPS_SAVED_REGSIZE
;
2898 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2901 /* Write this portion of the argument to the stack. */
2902 if (argreg
> MIPS_LAST_ARG_REGNUM
2904 || fp_register_arg_p (typecode
, arg_type
))
2906 /* Should shorter than int integer values be
2907 promoted to int before being stored? */
2908 int longword_offset
= 0;
2911 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2913 if (MIPS_STACK_ARGSIZE
== 8 &&
2914 (typecode
== TYPE_CODE_INT
||
2915 typecode
== TYPE_CODE_PTR
||
2916 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2917 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2918 else if ((typecode
== TYPE_CODE_STRUCT
||
2919 typecode
== TYPE_CODE_UNION
) &&
2920 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2921 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2926 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2927 paddr_nz (stack_offset
));
2928 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2929 paddr_nz (longword_offset
));
2932 addr
= sp
+ stack_offset
+ longword_offset
;
2937 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2939 for (i
= 0; i
< partial_len
; i
++)
2941 fprintf_unfiltered (gdb_stdlog
, "%02x",
2945 write_memory (addr
, val
, partial_len
);
2948 /* Note!!! This is NOT an else clause. Odd sized
2949 structs may go thru BOTH paths. Floating point
2950 arguments will not. */
2951 /* Write this portion of the argument to a general
2952 purpose register. */
2953 if (argreg
<= MIPS_LAST_ARG_REGNUM
2954 && !fp_register_arg_p (typecode
, arg_type
))
2956 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2958 /* A non-floating-point argument being passed in a
2959 general register. If a struct or union, and if
2960 the remaining length is smaller than the register
2961 size, we have to adjust the register value on
2964 It does not seem to be necessary to do the
2965 same for integral types.
2967 cagney/2001-07-23: gdb/179: Also, GCC, when
2968 outputting LE O32 with sizeof (struct) <
2969 MIPS_SAVED_REGSIZE, generates a left shift as
2970 part of storing the argument in a register a
2971 register (the left shift isn't generated when
2972 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
2973 is quite possible that this is GCC contradicting
2974 the LE/O32 ABI, GDB has not been adjusted to
2975 accommodate this. Either someone needs to
2976 demonstrate that the LE/O32 ABI specifies such a
2977 left shift OR this new ABI gets identified as
2978 such and GDB gets tweaked accordingly. */
2980 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
2981 && partial_len
< MIPS_SAVED_REGSIZE
2982 && (typecode
== TYPE_CODE_STRUCT
||
2983 typecode
== TYPE_CODE_UNION
))
2984 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2988 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2990 phex (regval
, MIPS_SAVED_REGSIZE
));
2991 write_register (argreg
, regval
);
2998 /* Compute the the offset into the stack at which we
2999 will copy the next parameter.
3001 In N32 (N64?), the stack_offset only needs to be
3002 adjusted when it has been used. */
3005 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
3009 fprintf_unfiltered (gdb_stdlog
, "\n");
3012 /* Return adjusted stack pointer. */
3016 /* O32 version of push_arguments. */
3019 mips_o32_push_arguments (int nargs
,
3020 struct value
**args
,
3023 CORE_ADDR struct_addr
)
3029 int stack_offset
= 0;
3031 /* First ensure that the stack and structure return address (if any)
3032 are properly aligned. The stack has to be at least 64-bit
3033 aligned even on 32-bit machines, because doubles must be 64-bit
3034 aligned. For n32 and n64, stack frames need to be 128-bit
3035 aligned, so we round to this widest known alignment. */
3037 sp
= ROUND_DOWN (sp
, 16);
3038 struct_addr
= ROUND_DOWN (struct_addr
, 16);
3040 /* Now make space on the stack for the args. */
3041 for (argnum
= 0; argnum
< nargs
; argnum
++)
3042 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3043 MIPS_STACK_ARGSIZE
);
3044 sp
-= ROUND_UP (len
, 16);
3047 fprintf_unfiltered (gdb_stdlog
,
3048 "mips_o32_push_arguments: sp=0x%s allocated %d\n",
3049 paddr_nz (sp
), ROUND_UP (len
, 16));
3051 /* Initialize the integer and float register pointers. */
3053 float_argreg
= FPA0_REGNUM
;
3055 /* The struct_return pointer occupies the first parameter-passing reg. */
3059 fprintf_unfiltered (gdb_stdlog
,
3060 "mips_o32_push_arguments: struct_return reg=%d 0x%s\n",
3061 argreg
, paddr_nz (struct_addr
));
3062 write_register (argreg
++, struct_addr
);
3063 stack_offset
+= MIPS_STACK_ARGSIZE
;
3066 /* Now load as many as possible of the first arguments into
3067 registers, and push the rest onto the stack. Loop thru args
3068 from first to last. */
3069 for (argnum
= 0; argnum
< nargs
; argnum
++)
3072 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
3073 struct value
*arg
= args
[argnum
];
3074 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3075 int len
= TYPE_LENGTH (arg_type
);
3076 enum type_code typecode
= TYPE_CODE (arg_type
);
3079 fprintf_unfiltered (gdb_stdlog
,
3080 "mips_o32_push_arguments: %d len=%d type=%d",
3081 argnum
+ 1, len
, (int) typecode
);
3083 val
= (char *) VALUE_CONTENTS (arg
);
3085 /* 32-bit ABIs always start floating point arguments in an
3086 even-numbered floating point register. Round the FP register
3087 up before the check to see if there are any FP registers
3088 left. O32/O64 targets also pass the FP in the integer
3089 registers so also round up normal registers. */
3090 if (!FP_REGISTER_DOUBLE
3091 && fp_register_arg_p (typecode
, arg_type
))
3093 if ((float_argreg
& 1))
3097 /* Floating point arguments passed in registers have to be
3098 treated specially. On 32-bit architectures, doubles
3099 are passed in register pairs; the even register gets
3100 the low word, and the odd register gets the high word.
3101 On O32/O64, the first two floating point arguments are
3102 also copied to general registers, because MIPS16 functions
3103 don't use float registers for arguments. This duplication of
3104 arguments in general registers can't hurt non-MIPS16 functions
3105 because those registers are normally skipped. */
3107 if (fp_register_arg_p (typecode
, arg_type
)
3108 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3110 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3112 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3113 unsigned long regval
;
3115 /* Write the low word of the double to the even register(s). */
3116 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3118 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3119 float_argreg
, phex (regval
, 4));
3120 write_register (float_argreg
++, regval
);
3122 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3123 argreg
, phex (regval
, 4));
3124 write_register (argreg
++, regval
);
3126 /* Write the high word of the double to the odd register(s). */
3127 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3129 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3130 float_argreg
, phex (regval
, 4));
3131 write_register (float_argreg
++, regval
);
3134 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3135 argreg
, phex (regval
, 4));
3136 write_register (argreg
++, regval
);
3140 /* This is a floating point value that fits entirely
3141 in a single register. */
3142 /* On 32 bit ABI's the float_argreg is further adjusted
3143 above to ensure that it is even register aligned. */
3144 LONGEST regval
= extract_unsigned_integer (val
, len
);
3146 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3147 float_argreg
, phex (regval
, len
));
3148 write_register (float_argreg
++, regval
);
3149 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3150 registers for each argument. The below is (my
3151 guess) to ensure that the corresponding integer
3152 register has reserved the same space. */
3154 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3155 argreg
, phex (regval
, len
));
3156 write_register (argreg
, regval
);
3157 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3159 /* Reserve space for the FP register. */
3160 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
3164 /* Copy the argument to general registers or the stack in
3165 register-sized pieces. Large arguments are split between
3166 registers and stack. */
3167 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3168 are treated specially: Irix cc passes them in registers
3169 where gcc sometimes puts them on the stack. For maximum
3170 compatibility, we will put them in both places. */
3171 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3172 (len
% MIPS_SAVED_REGSIZE
!= 0));
3173 /* Structures should be aligned to eight bytes (even arg registers)
3174 on MIPS_ABI_O32, if their first member has double precision. */
3175 if (MIPS_SAVED_REGSIZE
< 8
3176 && mips_type_needs_double_align (arg_type
))
3181 /* Note: Floating-point values that didn't fit into an FP
3182 register are only written to memory. */
3185 /* Remember if the argument was written to the stack. */
3186 int stack_used_p
= 0;
3188 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3191 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3194 /* Write this portion of the argument to the stack. */
3195 if (argreg
> MIPS_LAST_ARG_REGNUM
3197 || fp_register_arg_p (typecode
, arg_type
))
3199 /* Should shorter than int integer values be
3200 promoted to int before being stored? */
3201 int longword_offset
= 0;
3204 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3206 if (MIPS_STACK_ARGSIZE
== 8 &&
3207 (typecode
== TYPE_CODE_INT
||
3208 typecode
== TYPE_CODE_PTR
||
3209 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3210 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3215 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3216 paddr_nz (stack_offset
));
3217 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3218 paddr_nz (longword_offset
));
3221 addr
= sp
+ stack_offset
+ longword_offset
;
3226 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3228 for (i
= 0; i
< partial_len
; i
++)
3230 fprintf_unfiltered (gdb_stdlog
, "%02x",
3234 write_memory (addr
, val
, partial_len
);
3237 /* Note!!! This is NOT an else clause. Odd sized
3238 structs may go thru BOTH paths. Floating point
3239 arguments will not. */
3240 /* Write this portion of the argument to a general
3241 purpose register. */
3242 if (argreg
<= MIPS_LAST_ARG_REGNUM
3243 && !fp_register_arg_p (typecode
, arg_type
))
3245 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3246 /* Value may need to be sign extended, because
3247 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3249 /* A non-floating-point argument being passed in a
3250 general register. If a struct or union, and if
3251 the remaining length is smaller than the register
3252 size, we have to adjust the register value on
3255 It does not seem to be necessary to do the
3256 same for integral types.
3258 Also don't do this adjustment on O64 binaries.
3260 cagney/2001-07-23: gdb/179: Also, GCC, when
3261 outputting LE O32 with sizeof (struct) <
3262 MIPS_SAVED_REGSIZE, generates a left shift as
3263 part of storing the argument in a register a
3264 register (the left shift isn't generated when
3265 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3266 is quite possible that this is GCC contradicting
3267 the LE/O32 ABI, GDB has not been adjusted to
3268 accommodate this. Either someone needs to
3269 demonstrate that the LE/O32 ABI specifies such a
3270 left shift OR this new ABI gets identified as
3271 such and GDB gets tweaked accordingly. */
3273 if (MIPS_SAVED_REGSIZE
< 8
3274 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3275 && partial_len
< MIPS_SAVED_REGSIZE
3276 && (typecode
== TYPE_CODE_STRUCT
||
3277 typecode
== TYPE_CODE_UNION
))
3278 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3282 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3284 phex (regval
, MIPS_SAVED_REGSIZE
));
3285 write_register (argreg
, regval
);
3288 /* Prevent subsequent floating point arguments from
3289 being passed in floating point registers. */
3290 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3296 /* Compute the the offset into the stack at which we
3297 will copy the next parameter.
3299 In older ABIs, the caller reserved space for
3300 registers that contained arguments. This was loosely
3301 refered to as their "home". Consequently, space is
3302 always allocated. */
3304 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
3308 fprintf_unfiltered (gdb_stdlog
, "\n");
3311 /* Return adjusted stack pointer. */
3315 /* O64 version of push_arguments. */
3318 mips_o64_push_arguments (int nargs
,
3319 struct value
**args
,
3322 CORE_ADDR struct_addr
)
3328 int stack_offset
= 0;
3330 /* First ensure that the stack and structure return address (if any)
3331 are properly aligned. The stack has to be at least 64-bit
3332 aligned even on 32-bit machines, because doubles must be 64-bit
3333 aligned. For n32 and n64, stack frames need to be 128-bit
3334 aligned, so we round to this widest known alignment. */
3336 sp
= ROUND_DOWN (sp
, 16);
3337 struct_addr
= ROUND_DOWN (struct_addr
, 16);
3339 /* Now make space on the stack for the args. */
3340 for (argnum
= 0; argnum
< nargs
; argnum
++)
3341 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])),
3342 MIPS_STACK_ARGSIZE
);
3343 sp
-= ROUND_UP (len
, 16);
3346 fprintf_unfiltered (gdb_stdlog
,
3347 "mips_o64_push_arguments: sp=0x%s allocated %d\n",
3348 paddr_nz (sp
), ROUND_UP (len
, 16));
3350 /* Initialize the integer and float register pointers. */
3352 float_argreg
= FPA0_REGNUM
;
3354 /* The struct_return pointer occupies the first parameter-passing reg. */
3358 fprintf_unfiltered (gdb_stdlog
,
3359 "mips_o64_push_arguments: struct_return reg=%d 0x%s\n",
3360 argreg
, paddr_nz (struct_addr
));
3361 write_register (argreg
++, struct_addr
);
3362 stack_offset
+= MIPS_STACK_ARGSIZE
;
3365 /* Now load as many as possible of the first arguments into
3366 registers, and push the rest onto the stack. Loop thru args
3367 from first to last. */
3368 for (argnum
= 0; argnum
< nargs
; argnum
++)
3371 char *valbuf
= alloca (MAX_REGISTER_RAW_SIZE
);
3372 struct value
*arg
= args
[argnum
];
3373 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
3374 int len
= TYPE_LENGTH (arg_type
);
3375 enum type_code typecode
= TYPE_CODE (arg_type
);
3378 fprintf_unfiltered (gdb_stdlog
,
3379 "mips_o64_push_arguments: %d len=%d type=%d",
3380 argnum
+ 1, len
, (int) typecode
);
3382 val
= (char *) VALUE_CONTENTS (arg
);
3384 /* 32-bit ABIs always start floating point arguments in an
3385 even-numbered floating point register. Round the FP register
3386 up before the check to see if there are any FP registers
3387 left. O32/O64 targets also pass the FP in the integer
3388 registers so also round up normal registers. */
3389 if (!FP_REGISTER_DOUBLE
3390 && fp_register_arg_p (typecode
, arg_type
))
3392 if ((float_argreg
& 1))
3396 /* Floating point arguments passed in registers have to be
3397 treated specially. On 32-bit architectures, doubles
3398 are passed in register pairs; the even register gets
3399 the low word, and the odd register gets the high word.
3400 On O32/O64, the first two floating point arguments are
3401 also copied to general registers, because MIPS16 functions
3402 don't use float registers for arguments. This duplication of
3403 arguments in general registers can't hurt non-MIPS16 functions
3404 because those registers are normally skipped. */
3406 if (fp_register_arg_p (typecode
, arg_type
)
3407 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3409 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3411 int low_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
3412 unsigned long regval
;
3414 /* Write the low word of the double to the even register(s). */
3415 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3417 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3418 float_argreg
, phex (regval
, 4));
3419 write_register (float_argreg
++, regval
);
3421 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3422 argreg
, phex (regval
, 4));
3423 write_register (argreg
++, regval
);
3425 /* Write the high word of the double to the odd register(s). */
3426 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3428 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3429 float_argreg
, phex (regval
, 4));
3430 write_register (float_argreg
++, regval
);
3433 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3434 argreg
, phex (regval
, 4));
3435 write_register (argreg
++, regval
);
3439 /* This is a floating point value that fits entirely
3440 in a single register. */
3441 /* On 32 bit ABI's the float_argreg is further adjusted
3442 above to ensure that it is even register aligned. */
3443 LONGEST regval
= extract_unsigned_integer (val
, len
);
3445 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3446 float_argreg
, phex (regval
, len
));
3447 write_register (float_argreg
++, regval
);
3448 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3449 registers for each argument. The below is (my
3450 guess) to ensure that the corresponding integer
3451 register has reserved the same space. */
3453 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3454 argreg
, phex (regval
, len
));
3455 write_register (argreg
, regval
);
3456 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
3458 /* Reserve space for the FP register. */
3459 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
3463 /* Copy the argument to general registers or the stack in
3464 register-sized pieces. Large arguments are split between
3465 registers and stack. */
3466 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
3467 are treated specially: Irix cc passes them in registers
3468 where gcc sometimes puts them on the stack. For maximum
3469 compatibility, we will put them in both places. */
3470 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
3471 (len
% MIPS_SAVED_REGSIZE
!= 0));
3472 /* Structures should be aligned to eight bytes (even arg registers)
3473 on MIPS_ABI_O32, if their first member has double precision. */
3474 if (MIPS_SAVED_REGSIZE
< 8
3475 && mips_type_needs_double_align (arg_type
))
3480 /* Note: Floating-point values that didn't fit into an FP
3481 register are only written to memory. */
3484 /* Remember if the argument was written to the stack. */
3485 int stack_used_p
= 0;
3487 len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
3490 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3493 /* Write this portion of the argument to the stack. */
3494 if (argreg
> MIPS_LAST_ARG_REGNUM
3496 || fp_register_arg_p (typecode
, arg_type
))
3498 /* Should shorter than int integer values be
3499 promoted to int before being stored? */
3500 int longword_offset
= 0;
3503 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3505 if (MIPS_STACK_ARGSIZE
== 8 &&
3506 (typecode
== TYPE_CODE_INT
||
3507 typecode
== TYPE_CODE_PTR
||
3508 typecode
== TYPE_CODE_FLT
) && len
<= 4)
3509 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
3514 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3515 paddr_nz (stack_offset
));
3516 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3517 paddr_nz (longword_offset
));
3520 addr
= sp
+ stack_offset
+ longword_offset
;
3525 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3527 for (i
= 0; i
< partial_len
; i
++)
3529 fprintf_unfiltered (gdb_stdlog
, "%02x",
3533 write_memory (addr
, val
, partial_len
);
3536 /* Note!!! This is NOT an else clause. Odd sized
3537 structs may go thru BOTH paths. Floating point
3538 arguments will not. */
3539 /* Write this portion of the argument to a general
3540 purpose register. */
3541 if (argreg
<= MIPS_LAST_ARG_REGNUM
3542 && !fp_register_arg_p (typecode
, arg_type
))
3544 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3545 /* Value may need to be sign extended, because
3546 MIPS_REGSIZE != MIPS_SAVED_REGSIZE. */
3548 /* A non-floating-point argument being passed in a
3549 general register. If a struct or union, and if
3550 the remaining length is smaller than the register
3551 size, we have to adjust the register value on
3554 It does not seem to be necessary to do the
3555 same for integral types.
3557 Also don't do this adjustment on O64 binaries.
3559 cagney/2001-07-23: gdb/179: Also, GCC, when
3560 outputting LE O32 with sizeof (struct) <
3561 MIPS_SAVED_REGSIZE, generates a left shift as
3562 part of storing the argument in a register a
3563 register (the left shift isn't generated when
3564 sizeof (struct) >= MIPS_SAVED_REGSIZE). Since it
3565 is quite possible that this is GCC contradicting
3566 the LE/O32 ABI, GDB has not been adjusted to
3567 accommodate this. Either someone needs to
3568 demonstrate that the LE/O32 ABI specifies such a
3569 left shift OR this new ABI gets identified as
3570 such and GDB gets tweaked accordingly. */
3572 if (MIPS_SAVED_REGSIZE
< 8
3573 && TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3574 && partial_len
< MIPS_SAVED_REGSIZE
3575 && (typecode
== TYPE_CODE_STRUCT
||
3576 typecode
== TYPE_CODE_UNION
))
3577 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
3581 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3583 phex (regval
, MIPS_SAVED_REGSIZE
));
3584 write_register (argreg
, regval
);
3587 /* Prevent subsequent floating point arguments from
3588 being passed in floating point registers. */
3589 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3595 /* Compute the the offset into the stack at which we
3596 will copy the next parameter.
3598 In older ABIs, the caller reserved space for
3599 registers that contained arguments. This was loosely
3600 refered to as their "home". Consequently, space is
3601 always allocated. */
3603 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
3607 fprintf_unfiltered (gdb_stdlog
, "\n");
3610 /* Return adjusted stack pointer. */
3615 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
3617 /* Set the return address register to point to the entry
3618 point of the program, where a breakpoint lies in wait. */
3619 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
3624 mips_push_register (CORE_ADDR
* sp
, int regno
)
3626 char *buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
3629 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
3631 regsize
= MIPS_SAVED_REGSIZE
;
3632 offset
= (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3633 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
3638 regsize
= REGISTER_RAW_SIZE (regno
);
3642 read_register_gen (regno
, buffer
);
3643 write_memory (*sp
, buffer
+ offset
, regsize
);
3646 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
3647 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
3650 mips_push_dummy_frame (void)
3653 struct linked_proc_info
*link
= (struct linked_proc_info
*)
3654 xmalloc (sizeof (struct linked_proc_info
));
3655 mips_extra_func_info_t proc_desc
= &link
->info
;
3656 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
3657 CORE_ADDR old_sp
= sp
;
3658 link
->next
= linked_proc_desc_table
;
3659 linked_proc_desc_table
= link
;
3661 /* FIXME! are these correct ? */
3662 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
3663 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
3664 #define FLOAT_REG_SAVE_MASK MASK(0,19)
3665 #define FLOAT_SINGLE_REG_SAVE_MASK \
3666 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
3668 * The registers we must save are all those not preserved across
3669 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
3670 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
3671 * and FP Control/Status registers.
3674 * Dummy frame layout:
3677 * Saved MMHI, MMLO, FPC_CSR
3682 * Saved D18 (i.e. F19, F18)
3684 * Saved D0 (i.e. F1, F0)
3685 * Argument build area and stack arguments written via mips_push_arguments
3689 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
3690 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
3691 PROC_FRAME_OFFSET (proc_desc
) = 0;
3692 PROC_FRAME_ADJUST (proc_desc
) = 0;
3693 mips_push_register (&sp
, PC_REGNUM
);
3694 mips_push_register (&sp
, HI_REGNUM
);
3695 mips_push_register (&sp
, LO_REGNUM
);
3696 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
3698 /* Save general CPU registers */
3699 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
3700 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
3701 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
3702 for (ireg
= 32; --ireg
>= 0;)
3703 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
3704 mips_push_register (&sp
, ireg
);
3706 /* Save floating point registers starting with high order word */
3707 PROC_FREG_MASK (proc_desc
) =
3708 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
3709 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
3710 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
3712 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
3713 for (ireg
= 32; --ireg
>= 0;)
3714 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
3715 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
3717 /* Update the frame pointer for the call dummy and the stack pointer.
3718 Set the procedure's starting and ending addresses to point to the
3719 call dummy address at the entry point. */
3720 write_register (PUSH_FP_REGNUM
, old_sp
);
3721 write_register (SP_REGNUM
, sp
);
3722 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
3723 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
3724 SET_PROC_DESC_IS_DUMMY (proc_desc
);
3725 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
3729 mips_pop_frame (void)
3731 register int regnum
;
3732 struct frame_info
*frame
= get_current_frame ();
3733 CORE_ADDR new_sp
= FRAME_FP (frame
);
3735 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
3737 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
3738 if (frame
->saved_regs
== NULL
)
3739 FRAME_INIT_SAVED_REGS (frame
);
3740 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
3742 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
3743 && frame
->saved_regs
[regnum
])
3744 write_register (regnum
,
3745 read_memory_integer (frame
->saved_regs
[regnum
],
3746 MIPS_SAVED_REGSIZE
));
3748 write_register (SP_REGNUM
, new_sp
);
3749 flush_cached_frames ();
3751 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
3753 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
3755 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
3757 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
3759 if (&pi_ptr
->info
== proc_desc
)
3764 error ("Can't locate dummy extra frame info\n");
3766 if (prev_ptr
!= NULL
)
3767 prev_ptr
->next
= pi_ptr
->next
;
3769 linked_proc_desc_table
= pi_ptr
->next
;
3773 write_register (HI_REGNUM
,
3774 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
3775 MIPS_SAVED_REGSIZE
));
3776 write_register (LO_REGNUM
,
3777 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
3778 MIPS_SAVED_REGSIZE
));
3779 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
3780 write_register (FCRCS_REGNUM
,
3781 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
3782 MIPS_SAVED_REGSIZE
));
3786 /* Floating point register management.
3788 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3789 64bit operations, these early MIPS cpus treat fp register pairs
3790 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3791 registers and offer a compatibility mode that emulates the MIPS2 fp
3792 model. When operating in MIPS2 fp compat mode, later cpu's split
3793 double precision floats into two 32-bit chunks and store them in
3794 consecutive fp regs. To display 64-bit floats stored in this
3795 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3796 Throw in user-configurable endianness and you have a real mess.
3798 The way this works is:
3799 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3800 double-precision value will be split across two logical registers.
3801 The lower-numbered logical register will hold the low-order bits,
3802 regardless of the processor's endianness.
3803 - If we are on a 64-bit processor, and we are looking for a
3804 single-precision value, it will be in the low ordered bits
3805 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3806 save slot in memory.
3807 - If we are in 64-bit mode, everything is straightforward.
3809 Note that this code only deals with "live" registers at the top of the
3810 stack. We will attempt to deal with saved registers later, when
3811 the raw/cooked register interface is in place. (We need a general
3812 interface that can deal with dynamic saved register sizes -- fp
3813 regs could be 32 bits wide in one frame and 64 on the frame above
3816 static struct type
*
3817 mips_float_register_type (void)
3819 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3820 return builtin_type_ieee_single_big
;
3822 return builtin_type_ieee_single_little
;
3825 static struct type
*
3826 mips_double_register_type (void)
3828 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3829 return builtin_type_ieee_double_big
;
3831 return builtin_type_ieee_double_little
;
3834 /* Copy a 32-bit single-precision value from the current frame
3835 into rare_buffer. */
3838 mips_read_fp_register_single (int regno
, char *rare_buffer
)
3840 int raw_size
= REGISTER_RAW_SIZE (regno
);
3841 char *raw_buffer
= alloca (raw_size
);
3843 if (!frame_register_read (selected_frame
, regno
, raw_buffer
))
3844 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3847 /* We have a 64-bit value for this register. Find the low-order
3851 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3856 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
3860 memcpy (rare_buffer
, raw_buffer
, 4);
3864 /* Copy a 64-bit double-precision value from the current frame into
3865 rare_buffer. This may include getting half of it from the next
3869 mips_read_fp_register_double (int regno
, char *rare_buffer
)
3871 int raw_size
= REGISTER_RAW_SIZE (regno
);
3873 if (raw_size
== 8 && !mips2_fp_compat ())
3875 /* We have a 64-bit value for this register, and we should use
3877 if (!frame_register_read (selected_frame
, regno
, rare_buffer
))
3878 error ("can't read register %d (%s)", regno
, REGISTER_NAME (regno
));
3882 if ((regno
- FP0_REGNUM
) & 1)
3883 internal_error (__FILE__
, __LINE__
,
3884 "mips_read_fp_register_double: bad access to "
3885 "odd-numbered FP register");
3887 /* mips_read_fp_register_single will find the correct 32 bits from
3889 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3891 mips_read_fp_register_single (regno
, rare_buffer
+ 4);
3892 mips_read_fp_register_single (regno
+ 1, rare_buffer
);
3896 mips_read_fp_register_single (regno
, rare_buffer
);
3897 mips_read_fp_register_single (regno
+ 1, rare_buffer
+ 4);
3903 mips_print_register (int regnum
, int all
)
3905 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
3907 /* Get the data in raw format. */
3908 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
3910 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
3914 /* If we have a actual 32-bit floating point register (or we are in
3915 32-bit compatibility mode), and the register is even-numbered,
3916 also print it as a double (spanning two registers). */
3917 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
3918 && (REGISTER_RAW_SIZE (regnum
) == 4
3919 || mips2_fp_compat ())
3920 && !((regnum
- FP0_REGNUM
) & 1))
3922 char *dbuffer
= alloca (2 * MAX_REGISTER_RAW_SIZE
);
3924 mips_read_fp_register_double (regnum
, dbuffer
);
3926 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
3927 val_print (mips_double_register_type (), dbuffer
, 0, 0,
3928 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3929 printf_filtered ("); ");
3931 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3933 /* The problem with printing numeric register names (r26, etc.) is that
3934 the user can't use them on input. Probably the best solution is to
3935 fix it so that either the numeric or the funky (a2, etc.) names
3936 are accepted on input. */
3937 if (regnum
< MIPS_NUMREGS
)
3938 printf_filtered ("(r%d): ", regnum
);
3940 printf_filtered (": ");
3942 /* If virtual format is floating, print it that way. */
3943 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
3944 if (REGISTER_RAW_SIZE (regnum
) == 8 && !mips2_fp_compat ())
3946 /* We have a meaningful 64-bit value in this register. Show
3947 it as a 32-bit float and a 64-bit double. */
3948 int offset
= 4 * (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
);
3950 printf_filtered (" (float) ");
3951 val_print (mips_float_register_type (), raw_buffer
+ offset
, 0, 0,
3952 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3953 printf_filtered (", (double) ");
3954 val_print (mips_double_register_type (), raw_buffer
, 0, 0,
3955 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3958 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
3959 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
3960 /* Else print as integer in hex. */
3965 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3966 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
3970 print_scalar_formatted (raw_buffer
+ offset
,
3971 REGISTER_VIRTUAL_TYPE (regnum
),
3972 'x', 0, gdb_stdout
);
3976 /* Replacement for generic do_registers_info.
3977 Print regs in pretty columns. */
3980 do_fp_register_row (int regnum
)
3981 { /* do values for FP (float) regs */
3983 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
3984 int inv1
, inv2
, inv3
;
3986 raw_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
3988 if (REGISTER_RAW_SIZE (regnum
) == 4 || mips2_fp_compat ())
3990 /* 4-byte registers: we can fit two registers per row. */
3991 /* Also print every pair of 4-byte regs as an 8-byte double. */
3992 mips_read_fp_register_single (regnum
, raw_buffer
);
3993 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
3995 mips_read_fp_register_single (regnum
+ 1, raw_buffer
);
3996 flt2
= unpack_double (mips_float_register_type (), raw_buffer
, &inv2
);
3998 mips_read_fp_register_double (regnum
, raw_buffer
);
3999 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
4001 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
4003 printf_filtered (": <invalid float>");
4005 printf_filtered ("%-17.9g", flt1
);
4007 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
4009 printf_filtered (": <invalid float>");
4011 printf_filtered ("%-17.9g", flt2
);
4013 printf_filtered (" dbl: ");
4015 printf_filtered ("<invalid double>");
4017 printf_filtered ("%-24.17g", doub
);
4018 printf_filtered ("\n");
4020 /* may want to do hex display here (future enhancement) */
4025 /* Eight byte registers: print each one as float AND as double. */
4026 mips_read_fp_register_single (regnum
, raw_buffer
);
4027 flt1
= unpack_double (mips_double_register_type (), raw_buffer
, &inv1
);
4029 mips_read_fp_register_double (regnum
, raw_buffer
);
4030 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv3
);
4032 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
4034 printf_filtered ("<invalid float>");
4036 printf_filtered ("flt: %-17.9g", flt1
);
4038 printf_filtered (" dbl: ");
4040 printf_filtered ("<invalid double>");
4042 printf_filtered ("%-24.17g", doub
);
4044 printf_filtered ("\n");
4045 /* may want to do hex display here (future enhancement) */
4051 /* Print a row's worth of GP (int) registers, with name labels above */
4054 do_gp_register_row (int regnum
)
4056 /* do values for GP (int) regs */
4057 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4058 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
4060 int start_regnum
= regnum
;
4061 int numregs
= NUM_REGS
;
4064 /* For GP registers, we print a separate row of names above the vals */
4065 printf_filtered (" ");
4066 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
4068 if (*REGISTER_NAME (regnum
) == '\0')
4069 continue; /* unused register */
4070 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4071 break; /* end the row: reached FP register */
4072 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
4073 REGISTER_NAME (regnum
));
4076 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
4077 start_regnum
); /* print the R0 to R31 names */
4079 regnum
= start_regnum
; /* go back to start of row */
4080 /* now print the values in hex, 4 or 8 to the row */
4081 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
4083 if (*REGISTER_NAME (regnum
) == '\0')
4084 continue; /* unused register */
4085 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4086 break; /* end row: reached FP register */
4087 /* OK: get the data in raw format. */
4088 if (!frame_register_read (selected_frame
, regnum
, raw_buffer
))
4089 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
4090 /* pad small registers */
4091 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
4092 printf_filtered (" ");
4093 /* Now print the register value in hex, endian order. */
4094 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4095 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
4096 byte
< REGISTER_RAW_SIZE (regnum
);
4098 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
4100 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
4103 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
4104 printf_filtered (" ");
4107 if (col
> 0) /* ie. if we actually printed anything... */
4108 printf_filtered ("\n");
4113 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4116 mips_do_registers_info (int regnum
, int fpregs
)
4118 if (regnum
!= -1) /* do one specified register */
4120 if (*(REGISTER_NAME (regnum
)) == '\0')
4121 error ("Not a valid register for the current processor type");
4123 mips_print_register (regnum
, 0);
4124 printf_filtered ("\n");
4127 /* do all (or most) registers */
4130 while (regnum
< NUM_REGS
)
4132 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4133 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
4134 regnum
= do_fp_register_row (regnum
); /* FP regs */
4136 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4138 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
4143 /* Return number of args passed to a frame. described by FIP.
4144 Can return -1, meaning no way to tell. */
4147 mips_frame_num_args (struct frame_info
*frame
)
4152 /* Is this a branch with a delay slot? */
4154 static int is_delayed (unsigned long);
4157 is_delayed (unsigned long insn
)
4160 for (i
= 0; i
< NUMOPCODES
; ++i
)
4161 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4162 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4164 return (i
< NUMOPCODES
4165 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4166 | INSN_COND_BRANCH_DELAY
4167 | INSN_COND_BRANCH_LIKELY
)));
4171 mips_step_skips_delay (CORE_ADDR pc
)
4173 char buf
[MIPS_INSTLEN
];
4175 /* There is no branch delay slot on MIPS16. */
4176 if (pc_is_mips16 (pc
))
4179 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
4180 /* If error reading memory, guess that it is not a delayed branch. */
4182 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
4186 /* Skip the PC past function prologue instructions (32-bit version).
4187 This is a helper function for mips_skip_prologue. */
4190 mips32_skip_prologue (CORE_ADDR pc
)
4194 int seen_sp_adjust
= 0;
4195 int load_immediate_bytes
= 0;
4197 /* Skip the typical prologue instructions. These are the stack adjustment
4198 instruction and the instructions that save registers on the stack
4199 or in the gcc frame. */
4200 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
4202 unsigned long high_word
;
4204 inst
= mips_fetch_instruction (pc
);
4205 high_word
= (inst
>> 16) & 0xffff;
4207 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
4208 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
4210 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
4211 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
4213 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
4214 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
4215 && (inst
& 0x001F0000)) /* reg != $zero */
4218 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
4220 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
4222 continue; /* reg != $zero */
4224 /* move $s8,$sp. With different versions of gas this will be either
4225 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
4226 Accept any one of these. */
4227 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
4230 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
4232 else if (high_word
== 0x3c1c) /* lui $gp,n */
4234 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
4236 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
4237 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
4239 /* The following instructions load $at or $t0 with an immediate
4240 value in preparation for a stack adjustment via
4241 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
4242 a local variable, so we accept them only before a stack adjustment
4243 instruction was seen. */
4244 else if (!seen_sp_adjust
)
4246 if (high_word
== 0x3c01 || /* lui $at,n */
4247 high_word
== 0x3c08) /* lui $t0,n */
4249 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4252 else if (high_word
== 0x3421 || /* ori $at,$at,n */
4253 high_word
== 0x3508 || /* ori $t0,$t0,n */
4254 high_word
== 0x3401 || /* ori $at,$zero,n */
4255 high_word
== 0x3408) /* ori $t0,$zero,n */
4257 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
4267 /* In a frameless function, we might have incorrectly
4268 skipped some load immediate instructions. Undo the skipping
4269 if the load immediate was not followed by a stack adjustment. */
4270 if (load_immediate_bytes
&& !seen_sp_adjust
)
4271 pc
-= load_immediate_bytes
;
4275 /* Skip the PC past function prologue instructions (16-bit version).
4276 This is a helper function for mips_skip_prologue. */
4279 mips16_skip_prologue (CORE_ADDR pc
)
4282 int extend_bytes
= 0;
4283 int prev_extend_bytes
;
4285 /* Table of instructions likely to be found in a function prologue. */
4288 unsigned short inst
;
4289 unsigned short mask
;
4296 , /* addiu $sp,offset */
4300 , /* daddiu $sp,offset */
4304 , /* sw reg,n($sp) */
4308 , /* sd reg,n($sp) */
4312 , /* sw $ra,n($sp) */
4316 , /* sd $ra,n($sp) */
4324 , /* sw $a0-$a3,n($s1) */
4328 , /* move reg,$a0-$a3 */
4332 , /* entry pseudo-op */
4336 , /* addiu $s1,$sp,n */
4339 } /* end of table marker */
4342 /* Skip the typical prologue instructions. These are the stack adjustment
4343 instruction and the instructions that save registers on the stack
4344 or in the gcc frame. */
4345 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
4347 unsigned short inst
;
4350 inst
= mips_fetch_instruction (pc
);
4352 /* Normally we ignore an extend instruction. However, if it is
4353 not followed by a valid prologue instruction, we must adjust
4354 the pc back over the extend so that it won't be considered
4355 part of the prologue. */
4356 if ((inst
& 0xf800) == 0xf000) /* extend */
4358 extend_bytes
= MIPS16_INSTLEN
;
4361 prev_extend_bytes
= extend_bytes
;
4364 /* Check for other valid prologue instructions besides extend. */
4365 for (i
= 0; table
[i
].mask
!= 0; i
++)
4366 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
4368 if (table
[i
].mask
!= 0) /* it was in table? */
4369 continue; /* ignore it */
4373 /* Return the current pc, adjusted backwards by 2 if
4374 the previous instruction was an extend. */
4375 return pc
- prev_extend_bytes
;
4381 /* To skip prologues, I use this predicate. Returns either PC itself
4382 if the code at PC does not look like a function prologue; otherwise
4383 returns an address that (if we're lucky) follows the prologue. If
4384 LENIENT, then we must skip everything which is involved in setting
4385 up the frame (it's OK to skip more, just so long as we don't skip
4386 anything which might clobber the registers which are being saved.
4387 We must skip more in the case where part of the prologue is in the
4388 delay slot of a non-prologue instruction). */
4391 mips_skip_prologue (CORE_ADDR pc
)
4393 /* See if we can determine the end of the prologue via the symbol table.
4394 If so, then return either PC, or the PC after the prologue, whichever
4397 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
4399 if (post_prologue_pc
!= 0)
4400 return max (pc
, post_prologue_pc
);
4402 /* Can't determine prologue from the symbol table, need to examine
4405 if (pc_is_mips16 (pc
))
4406 return mips16_skip_prologue (pc
);
4408 return mips32_skip_prologue (pc
);
4411 /* Determine how a return value is stored within the MIPS register
4412 file, given the return type `valtype'. */
4414 struct return_value_word
4423 return_value_location (struct type
*valtype
,
4424 struct return_value_word
*hi
,
4425 struct return_value_word
*lo
)
4427 int len
= TYPE_LENGTH (valtype
);
4429 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
4430 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
4431 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
4433 if (!FP_REGISTER_DOUBLE
&& len
== 8)
4435 /* We need to break a 64bit float in two 32 bit halves and
4436 spread them across a floating-point register pair. */
4437 lo
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 4 : 0;
4438 hi
->buf_offset
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? 0 : 4;
4439 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4440 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
4442 hi
->reg_offset
= lo
->reg_offset
;
4443 lo
->reg
= FP0_REGNUM
+ 0;
4444 hi
->reg
= FP0_REGNUM
+ 1;
4450 /* The floating point value fits in a single floating-point
4452 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4453 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
4456 lo
->reg
= FP0_REGNUM
;
4467 /* Locate a result possibly spread across two registers. */
4469 lo
->reg
= regnum
+ 0;
4470 hi
->reg
= regnum
+ 1;
4471 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4472 && len
< MIPS_SAVED_REGSIZE
)
4474 /* "un-left-justify" the value in the low register */
4475 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
4480 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4481 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
4482 && len
< MIPS_SAVED_REGSIZE
* 2
4483 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
4484 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
4486 /* "un-left-justify" the value spread across two registers. */
4487 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
4488 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
4490 hi
->len
= len
- lo
->len
;
4494 /* Only perform a partial copy of the second register. */
4497 if (len
> MIPS_SAVED_REGSIZE
)
4499 lo
->len
= MIPS_SAVED_REGSIZE
;
4500 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
4508 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
4509 && REGISTER_RAW_SIZE (regnum
) == 8
4510 && MIPS_SAVED_REGSIZE
== 4)
4512 /* Account for the fact that only the least-signficant part
4513 of the register is being used */
4514 lo
->reg_offset
+= 4;
4515 hi
->reg_offset
+= 4;
4518 hi
->buf_offset
= lo
->len
;
4522 /* Given a return value in `regbuf' with a type `valtype', extract and
4523 copy its value into `valbuf'. */
4526 mips_eabi_extract_return_value (struct type
*valtype
,
4527 char regbuf
[REGISTER_BYTES
],
4530 struct return_value_word lo
;
4531 struct return_value_word hi
;
4532 return_value_location (valtype
, &hi
, &lo
);
4534 memcpy (valbuf
+ lo
.buf_offset
,
4535 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4539 memcpy (valbuf
+ hi
.buf_offset
,
4540 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4545 mips_o32_extract_return_value (struct type
*valtype
,
4546 char regbuf
[REGISTER_BYTES
],
4549 struct return_value_word lo
;
4550 struct return_value_word hi
;
4551 return_value_location (valtype
, &hi
, &lo
);
4553 memcpy (valbuf
+ lo
.buf_offset
,
4554 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4558 memcpy (valbuf
+ hi
.buf_offset
,
4559 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4564 mips_o64_extract_return_value (struct type
*valtype
,
4565 char regbuf
[REGISTER_BYTES
],
4568 struct return_value_word lo
;
4569 struct return_value_word hi
;
4570 return_value_location (valtype
, &hi
, &lo
);
4572 memcpy (valbuf
+ lo
.buf_offset
,
4573 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
4577 memcpy (valbuf
+ hi
.buf_offset
,
4578 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
4582 /* Given a return value in `valbuf' with a type `valtype', write it's
4583 value into the appropriate register. */
4586 mips_eabi_store_return_value (struct type
*valtype
, char *valbuf
)
4588 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4589 struct return_value_word lo
;
4590 struct return_value_word hi
;
4591 return_value_location (valtype
, &hi
, &lo
);
4593 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4594 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4595 write_register_bytes (REGISTER_BYTE (lo
.reg
),
4597 REGISTER_RAW_SIZE (lo
.reg
));
4601 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4602 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4603 write_register_bytes (REGISTER_BYTE (hi
.reg
),
4605 REGISTER_RAW_SIZE (hi
.reg
));
4610 mips_o32_store_return_value (struct type
*valtype
, char *valbuf
)
4612 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4613 struct return_value_word lo
;
4614 struct return_value_word hi
;
4615 return_value_location (valtype
, &hi
, &lo
);
4617 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4618 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4619 write_register_bytes (REGISTER_BYTE (lo
.reg
),
4621 REGISTER_RAW_SIZE (lo
.reg
));
4625 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4626 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4627 write_register_bytes (REGISTER_BYTE (hi
.reg
),
4629 REGISTER_RAW_SIZE (hi
.reg
));
4634 mips_o64_store_return_value (struct type
*valtype
, char *valbuf
)
4636 char *raw_buffer
= alloca (MAX_REGISTER_RAW_SIZE
);
4637 struct return_value_word lo
;
4638 struct return_value_word hi
;
4639 return_value_location (valtype
, &hi
, &lo
);
4641 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4642 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
4643 write_register_bytes (REGISTER_BYTE (lo
.reg
),
4645 REGISTER_RAW_SIZE (lo
.reg
));
4649 memset (raw_buffer
, 0, sizeof (raw_buffer
));
4650 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
4651 write_register_bytes (REGISTER_BYTE (hi
.reg
),
4653 REGISTER_RAW_SIZE (hi
.reg
));
4658 mips_n32n64_xfer_return_value (struct type
*type
,
4659 struct regcache
*regcache
,
4660 bfd_byte
*in
, const bfd_byte
*out
)
4662 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4663 if (TYPE_CODE (type
) == TYPE_CODE_FLT
4664 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4666 /* A floating-point value belongs in the least significant part
4669 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4670 mips_xfer_register (regcache
, FP0_REGNUM
, TYPE_LENGTH (type
),
4671 TARGET_BYTE_ORDER
, in
, out
, 0);
4673 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4674 && TYPE_NFIELDS (type
) <= 2
4675 && TYPE_NFIELDS (type
) >= 1
4676 && ((TYPE_NFIELDS (type
) == 1
4677 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4679 || (TYPE_NFIELDS (type
) == 2
4680 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4682 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4684 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4686 /* A struct that contains one or two floats. Each value is part
4687 in the least significant part of their floating point
4689 bfd_byte
*reg
= alloca (MAX_REGISTER_RAW_SIZE
);
4692 for (field
= 0, regnum
= FP0_REGNUM
;
4693 field
< TYPE_NFIELDS (type
);
4694 field
++, regnum
+= 2)
4696 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4699 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n", offset
);
4700 mips_xfer_register (regcache
, regnum
, TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4701 TARGET_BYTE_ORDER
, in
, out
, offset
);
4704 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4705 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4707 /* A structure or union. Extract the left justified value,
4708 regardless of the byte order. I.e. DO NOT USE
4712 for (offset
= 0, regnum
= V0_REGNUM
;
4713 offset
< TYPE_LENGTH (type
);
4714 offset
+= REGISTER_RAW_SIZE (regnum
), regnum
++)
4716 int xfer
= REGISTER_RAW_SIZE (regnum
);
4717 if (offset
+ xfer
> TYPE_LENGTH (type
))
4718 xfer
= TYPE_LENGTH (type
) - offset
;
4720 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4721 offset
, xfer
, regnum
);
4722 mips_xfer_register (regcache
, regnum
, xfer
, BFD_ENDIAN_UNKNOWN
,
4728 /* A scalar extract each part but least-significant-byte
4732 for (offset
= 0, regnum
= V0_REGNUM
;
4733 offset
< TYPE_LENGTH (type
);
4734 offset
+= REGISTER_RAW_SIZE (regnum
), regnum
++)
4736 int xfer
= REGISTER_RAW_SIZE (regnum
);
4738 if (offset
+ xfer
> TYPE_LENGTH (type
))
4739 xfer
= TYPE_LENGTH (type
) - offset
;
4741 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4742 offset
, xfer
, regnum
);
4743 mips_xfer_register (regcache
, regnum
, xfer
, TARGET_BYTE_ORDER
,
4750 mips_n32n64_extract_return_value (struct type
*type
,
4751 struct regcache
*regcache
,
4754 mips_n32n64_xfer_return_value (type
, regcache
, valbuf
, NULL
);
4758 mips_n32n64_store_return_value (struct type
*type
, char *valbuf
)
4760 mips_n32n64_xfer_return_value (type
, current_regcache
, NULL
, valbuf
);
4763 /* Exported procedure: Is PC in the signal trampoline code */
4766 mips_pc_in_sigtramp (CORE_ADDR pc
, char *ignore
)
4768 if (sigtramp_address
== 0)
4770 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
4773 /* Root of all "set mips "/"show mips " commands. This will eventually be
4774 used for all MIPS-specific commands. */
4777 show_mips_command (char *args
, int from_tty
)
4779 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4783 set_mips_command (char *args
, int from_tty
)
4785 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
4786 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4789 /* Commands to show/set the MIPS FPU type. */
4792 show_mipsfpu_command (char *args
, int from_tty
)
4795 switch (MIPS_FPU_TYPE
)
4797 case MIPS_FPU_SINGLE
:
4798 fpu
= "single-precision";
4800 case MIPS_FPU_DOUBLE
:
4801 fpu
= "double-precision";
4804 fpu
= "absent (none)";
4807 internal_error (__FILE__
, __LINE__
, "bad switch");
4809 if (mips_fpu_type_auto
)
4810 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4813 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
4819 set_mipsfpu_command (char *args
, int from_tty
)
4821 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4822 show_mipsfpu_command (args
, from_tty
);
4826 set_mipsfpu_single_command (char *args
, int from_tty
)
4828 mips_fpu_type
= MIPS_FPU_SINGLE
;
4829 mips_fpu_type_auto
= 0;
4830 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
4834 set_mipsfpu_double_command (char *args
, int from_tty
)
4836 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4837 mips_fpu_type_auto
= 0;
4838 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4842 set_mipsfpu_none_command (char *args
, int from_tty
)
4844 mips_fpu_type
= MIPS_FPU_NONE
;
4845 mips_fpu_type_auto
= 0;
4846 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
4850 set_mipsfpu_auto_command (char *args
, int from_tty
)
4852 mips_fpu_type_auto
= 1;
4855 /* Command to set the processor type. */
4858 mips_set_processor_type_command (char *args
, int from_tty
)
4862 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
4864 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
4865 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
4866 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
4868 /* Restore the value. */
4869 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
4874 if (!mips_set_processor_type (tmp_mips_processor_type
))
4876 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
4877 /* Restore its value. */
4878 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
4883 mips_show_processor_type_command (char *args
, int from_tty
)
4887 /* Modify the actual processor type. */
4890 mips_set_processor_type (char *str
)
4897 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
4899 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
4901 mips_processor_type
= str
;
4902 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
4904 /* FIXME tweak fpu flag too */
4911 /* Attempt to identify the particular processor model by reading the
4915 mips_read_processor_type (void)
4919 prid
= read_register (PRID_REGNUM
);
4921 if ((prid
& ~0xf) == 0x700)
4922 return savestring ("r3041", strlen ("r3041"));
4927 /* Just like reinit_frame_cache, but with the right arguments to be
4928 callable as an sfunc. */
4931 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4932 struct cmd_list_element
*c
)
4934 reinit_frame_cache ();
4938 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
4940 mips_extra_func_info_t proc_desc
;
4942 /* Search for the function containing this address. Set the low bit
4943 of the address when searching, in case we were given an even address
4944 that is the start of a 16-bit function. If we didn't do this,
4945 the search would fail because the symbol table says the function
4946 starts at an odd address, i.e. 1 byte past the given address. */
4947 memaddr
= ADDR_BITS_REMOVE (memaddr
);
4948 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
4950 /* Make an attempt to determine if this is a 16-bit function. If
4951 the procedure descriptor exists and the address therein is odd,
4952 it's definitely a 16-bit function. Otherwise, we have to just
4953 guess that if the address passed in is odd, it's 16-bits. */
4955 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
4956 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
4958 info
->mach
= pc_is_mips16 (memaddr
) ?
4959 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
4961 /* Round down the instruction address to the appropriate boundary. */
4962 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4964 /* Call the appropriate disassembler based on the target endian-ness. */
4965 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4966 return print_insn_big_mips (memaddr
, info
);
4968 return print_insn_little_mips (memaddr
, info
);
4971 /* Old-style breakpoint macros.
4972 The IDT board uses an unusual breakpoint value, and sometimes gets
4973 confused when it sees the usual MIPS breakpoint instruction. */
4975 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
4976 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
4977 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
4978 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
4979 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
4980 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
4981 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
4982 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
4984 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
4985 counter value to determine whether a 16- or 32-bit breakpoint should be
4986 used. It returns a pointer to a string of bytes that encode a breakpoint
4987 instruction, stores the length of the string to *lenptr, and adjusts pc
4988 (if necessary) to point to the actual memory location where the
4989 breakpoint should be inserted. */
4991 const unsigned char *
4992 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
4994 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
4996 if (pc_is_mips16 (*pcptr
))
4998 static unsigned char mips16_big_breakpoint
[] =
4999 MIPS16_BIG_BREAKPOINT
;
5000 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
5001 *lenptr
= sizeof (mips16_big_breakpoint
);
5002 return mips16_big_breakpoint
;
5006 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
5007 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
5008 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
5010 *lenptr
= sizeof (big_breakpoint
);
5012 if (strcmp (target_shortname
, "mips") == 0)
5013 return idt_big_breakpoint
;
5014 else if (strcmp (target_shortname
, "ddb") == 0
5015 || strcmp (target_shortname
, "pmon") == 0
5016 || strcmp (target_shortname
, "lsi") == 0)
5017 return pmon_big_breakpoint
;
5019 return big_breakpoint
;
5024 if (pc_is_mips16 (*pcptr
))
5026 static unsigned char mips16_little_breakpoint
[] =
5027 MIPS16_LITTLE_BREAKPOINT
;
5028 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
5029 *lenptr
= sizeof (mips16_little_breakpoint
);
5030 return mips16_little_breakpoint
;
5034 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
5035 static unsigned char pmon_little_breakpoint
[] =
5036 PMON_LITTLE_BREAKPOINT
;
5037 static unsigned char idt_little_breakpoint
[] =
5038 IDT_LITTLE_BREAKPOINT
;
5040 *lenptr
= sizeof (little_breakpoint
);
5042 if (strcmp (target_shortname
, "mips") == 0)
5043 return idt_little_breakpoint
;
5044 else if (strcmp (target_shortname
, "ddb") == 0
5045 || strcmp (target_shortname
, "pmon") == 0
5046 || strcmp (target_shortname
, "lsi") == 0)
5047 return pmon_little_breakpoint
;
5049 return little_breakpoint
;
5054 /* If PC is in a mips16 call or return stub, return the address of the target
5055 PC, which is either the callee or the caller. There are several
5056 cases which must be handled:
5058 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5059 target PC is in $31 ($ra).
5060 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5061 and the target PC is in $2.
5062 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5063 before the jal instruction, this is effectively a call stub
5064 and the the target PC is in $2. Otherwise this is effectively
5065 a return stub and the target PC is in $18.
5067 See the source code for the stubs in gcc/config/mips/mips16.S for
5070 This function implements the SKIP_TRAMPOLINE_CODE macro.
5074 mips_skip_stub (CORE_ADDR pc
)
5077 CORE_ADDR start_addr
;
5079 /* Find the starting address and name of the function containing the PC. */
5080 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5083 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5084 target PC is in $31 ($ra). */
5085 if (strcmp (name
, "__mips16_ret_sf") == 0
5086 || strcmp (name
, "__mips16_ret_df") == 0)
5087 return read_signed_register (RA_REGNUM
);
5089 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5091 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5092 and the target PC is in $2. */
5093 if (name
[19] >= '0' && name
[19] <= '9')
5094 return read_signed_register (2);
5096 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5097 before the jal instruction, this is effectively a call stub
5098 and the the target PC is in $2. Otherwise this is effectively
5099 a return stub and the target PC is in $18. */
5100 else if (name
[19] == 's' || name
[19] == 'd')
5102 if (pc
== start_addr
)
5104 /* Check if the target of the stub is a compiler-generated
5105 stub. Such a stub for a function bar might have a name
5106 like __fn_stub_bar, and might look like this:
5111 la $1,bar (becomes a lui/addiu pair)
5113 So scan down to the lui/addi and extract the target
5114 address from those two instructions. */
5116 CORE_ADDR target_pc
= read_signed_register (2);
5120 /* See if the name of the target function is __fn_stub_*. */
5121 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
5123 if (strncmp (name
, "__fn_stub_", 10) != 0
5124 && strcmp (name
, "etext") != 0
5125 && strcmp (name
, "_etext") != 0)
5128 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5129 The limit on the search is arbitrarily set to 20
5130 instructions. FIXME. */
5131 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
5133 inst
= mips_fetch_instruction (target_pc
);
5134 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5135 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5136 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5137 return pc
| (inst
& 0xffff); /* low word */
5140 /* Couldn't find the lui/addui pair, so return stub address. */
5144 /* This is the 'return' part of a call stub. The return
5145 address is in $r18. */
5146 return read_signed_register (18);
5149 return 0; /* not a stub */
5153 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
5154 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
5157 mips_in_call_stub (CORE_ADDR pc
, char *name
)
5159 CORE_ADDR start_addr
;
5161 /* Find the starting address of the function containing the PC. If the
5162 caller didn't give us a name, look it up at the same time. */
5163 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
5166 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5168 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
5169 if (name
[19] >= '0' && name
[19] <= '9')
5171 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5172 before the jal instruction, this is effectively a call stub. */
5173 else if (name
[19] == 's' || name
[19] == 'd')
5174 return pc
== start_addr
;
5177 return 0; /* not a stub */
5181 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
5182 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
5185 mips_in_return_stub (CORE_ADDR pc
, char *name
)
5187 CORE_ADDR start_addr
;
5189 /* Find the starting address of the function containing the PC. */
5190 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
5193 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
5194 if (strcmp (name
, "__mips16_ret_sf") == 0
5195 || strcmp (name
, "__mips16_ret_df") == 0)
5198 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
5199 i.e. after the jal instruction, this is effectively a return stub. */
5200 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
5201 && (name
[19] == 's' || name
[19] == 'd')
5202 && pc
!= start_addr
)
5205 return 0; /* not a stub */
5209 /* Return non-zero if the PC is in a library helper function that should
5210 be ignored. This implements the IGNORE_HELPER_CALL macro. */
5213 mips_ignore_helper (CORE_ADDR pc
)
5217 /* Find the starting address and name of the function containing the PC. */
5218 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
5221 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
5222 that we want to ignore. */
5223 return (strcmp (name
, "__mips16_ret_sf") == 0
5224 || strcmp (name
, "__mips16_ret_df") == 0);
5228 /* Return a location where we can set a breakpoint that will be hit
5229 when an inferior function call returns. This is normally the
5230 program's entry point. Executables that don't have an entry
5231 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
5232 whose address is the location where the breakpoint should be placed. */
5235 mips_call_dummy_address (void)
5237 struct minimal_symbol
*sym
;
5239 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
5241 return SYMBOL_VALUE_ADDRESS (sym
);
5243 return entry_point_address ();
5247 /* If the current gcc for this target does not produce correct debugging
5248 information for float parameters, both prototyped and unprototyped, then
5249 define this macro. This forces gdb to always assume that floats are
5250 passed as doubles and then converted in the callee.
5252 For the mips chip, it appears that the debug info marks the parameters as
5253 floats regardless of whether the function is prototyped, but the actual
5254 values are passed as doubles for the non-prototyped case and floats for
5255 the prototyped case. Thus we choose to make the non-prototyped case work
5256 for C and break the prototyped case, since the non-prototyped case is
5257 probably much more common. (FIXME). */
5260 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
5262 return current_language
->la_language
== language_c
;
5265 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
5266 the register stored on the stack (32) is different to its real raw
5267 size (64). The below ensures that registers are fetched from the
5268 stack using their ABI size and then stored into the RAW_BUFFER
5269 using their raw size.
5271 The alternative to adding this function would be to add an ABI
5272 macro - REGISTER_STACK_SIZE(). */
5275 mips_get_saved_register (char *raw_buffer
,
5278 struct frame_info
*frame
,
5280 enum lval_type
*lval
)
5284 if (!target_has_registers
)
5285 error ("No registers.");
5287 /* Normal systems don't optimize out things with register numbers. */
5288 if (optimized
!= NULL
)
5290 addr
= find_saved_register (frame
, regnum
);
5294 *lval
= lval_memory
;
5295 if (regnum
== SP_REGNUM
)
5297 if (raw_buffer
!= NULL
)
5299 /* Put it back in target format. */
5300 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
5307 if (raw_buffer
!= NULL
)
5311 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
5313 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
5315 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
5316 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
5322 *lval
= lval_register
;
5323 addr
= REGISTER_BYTE (regnum
);
5324 if (raw_buffer
!= NULL
)
5325 read_register_gen (regnum
, raw_buffer
);
5331 /* Immediately after a function call, return the saved pc.
5332 Can't always go through the frames for this because on some machines
5333 the new frame is not set up until the new function executes
5334 some instructions. */
5337 mips_saved_pc_after_call (struct frame_info
*frame
)
5339 return read_signed_register (RA_REGNUM
);
5343 /* Convert a dbx stab register number (from `r' declaration) to a gdb
5347 mips_stab_reg_to_regnum (int num
)
5352 return num
+ FP0_REGNUM
- 38;
5355 /* Convert a ecoff register number to a gdb REGNUM */
5358 mips_ecoff_reg_to_regnum (int num
)
5363 return num
+ FP0_REGNUM
- 32;
5366 /* Convert an integer into an address. By first converting the value
5367 into a pointer and then extracting it signed, the address is
5368 guarenteed to be correctly sign extended. */
5371 mips_integer_to_address (struct type
*type
, void *buf
)
5373 char *tmp
= alloca (TYPE_LENGTH (builtin_type_void_data_ptr
));
5374 LONGEST val
= unpack_long (type
, buf
);
5375 store_signed_integer (tmp
, TYPE_LENGTH (builtin_type_void_data_ptr
), val
);
5376 return extract_signed_integer (tmp
,
5377 TYPE_LENGTH (builtin_type_void_data_ptr
));
5381 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5383 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5384 const char *name
= bfd_get_section_name (abfd
, sect
);
5386 if (*abip
!= MIPS_ABI_UNKNOWN
)
5389 if (strncmp (name
, ".mdebug.", 8) != 0)
5392 if (strcmp (name
, ".mdebug.abi32") == 0)
5393 *abip
= MIPS_ABI_O32
;
5394 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5395 *abip
= MIPS_ABI_N32
;
5396 else if (strcmp (name
, ".mdebug.abiN64") == 0)
5397 *abip
= MIPS_ABI_N64
;
5398 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5399 *abip
= MIPS_ABI_O64
;
5400 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5401 *abip
= MIPS_ABI_EABI32
;
5402 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5403 *abip
= MIPS_ABI_EABI64
;
5405 warning ("unsupported ABI %s.", name
+ 8);
5408 static enum mips_abi
5409 global_mips_abi (void)
5413 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5414 if (mips_abi_strings
[i
] == mips_abi_string
)
5415 return (enum mips_abi
) i
;
5417 internal_error (__FILE__
, __LINE__
,
5418 "unknown ABI string");
5421 static struct gdbarch
*
5422 mips_gdbarch_init (struct gdbarch_info info
,
5423 struct gdbarch_list
*arches
)
5425 static LONGEST mips_call_dummy_words
[] =
5427 struct gdbarch
*gdbarch
;
5428 struct gdbarch_tdep
*tdep
;
5430 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5431 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
5433 /* Reset the disassembly info, in case it was set to something
5435 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
5436 tm_print_insn_info
.arch
= bfd_arch_unknown
;
5437 tm_print_insn_info
.mach
= 0;
5443 /* First of all, extract the elf_flags, if available. */
5444 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5445 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5447 /* Try to determine the OS ABI of the object we are loading. If
5448 we end up with `unknown', just leave it that way. */
5449 osabi
= gdbarch_lookup_osabi (info
.abfd
);
5452 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5453 switch ((elf_flags
& EF_MIPS_ABI
))
5455 case E_MIPS_ABI_O32
:
5456 mips_abi
= MIPS_ABI_O32
;
5458 case E_MIPS_ABI_O64
:
5459 mips_abi
= MIPS_ABI_O64
;
5461 case E_MIPS_ABI_EABI32
:
5462 mips_abi
= MIPS_ABI_EABI32
;
5464 case E_MIPS_ABI_EABI64
:
5465 mips_abi
= MIPS_ABI_EABI64
;
5468 if ((elf_flags
& EF_MIPS_ABI2
))
5469 mips_abi
= MIPS_ABI_N32
;
5471 mips_abi
= MIPS_ABI_UNKNOWN
;
5475 /* GCC creates a pseudo-section whose name describes the ABI. */
5476 if (mips_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5477 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &mips_abi
);
5479 /* If we have no bfd, then mips_abi will still be MIPS_ABI_UNKNOWN.
5480 Use the ABI from the last architecture if there is one. */
5481 if (info
.abfd
== NULL
&& arches
!= NULL
)
5482 mips_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5484 /* Try the architecture for any hint of the correct ABI. */
5485 if (mips_abi
== MIPS_ABI_UNKNOWN
5486 && info
.bfd_arch_info
!= NULL
5487 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5489 switch (info
.bfd_arch_info
->mach
)
5491 case bfd_mach_mips3900
:
5492 mips_abi
= MIPS_ABI_EABI32
;
5494 case bfd_mach_mips4100
:
5495 case bfd_mach_mips5000
:
5496 mips_abi
= MIPS_ABI_EABI64
;
5498 case bfd_mach_mips8000
:
5499 case bfd_mach_mips10000
:
5500 /* On Irix, ELF64 executables use the N64 ABI. The
5501 pseudo-sections which describe the ABI aren't present
5502 on IRIX. (Even for executables created by gcc.) */
5503 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5504 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5505 mips_abi
= MIPS_ABI_N64
;
5507 mips_abi
= MIPS_ABI_N32
;
5512 #ifdef MIPS_DEFAULT_ABI
5513 if (mips_abi
== MIPS_ABI_UNKNOWN
)
5514 mips_abi
= MIPS_DEFAULT_ABI
;
5517 if (mips_abi
== MIPS_ABI_UNKNOWN
)
5518 mips_abi
= MIPS_ABI_O32
;
5520 /* Now that we have found what the ABI for this binary would be,
5521 check whether the user is overriding it. */
5522 found_abi
= mips_abi
;
5523 wanted_abi
= global_mips_abi ();
5524 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5525 mips_abi
= wanted_abi
;
5529 fprintf_unfiltered (gdb_stdlog
,
5530 "mips_gdbarch_init: elf_flags = 0x%08x\n",
5532 fprintf_unfiltered (gdb_stdlog
,
5533 "mips_gdbarch_init: mips_abi = %d\n",
5535 fprintf_unfiltered (gdb_stdlog
,
5536 "mips_gdbarch_init: found_mips_abi = %d\n",
5540 /* try to find a pre-existing architecture */
5541 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5543 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5545 /* MIPS needs to be pedantic about which ABI the object is
5547 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5549 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5551 if (gdbarch_tdep (arches
->gdbarch
)->osabi
== osabi
)
5552 return arches
->gdbarch
;
5555 /* Need a new architecture. Fill in a target specific vector. */
5556 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5557 gdbarch
= gdbarch_alloc (&info
, tdep
);
5558 tdep
->elf_flags
= elf_flags
;
5559 tdep
->osabi
= osabi
;
5561 /* Initially set everything according to the default ABI/ISA. */
5562 set_gdbarch_short_bit (gdbarch
, 16);
5563 set_gdbarch_int_bit (gdbarch
, 32);
5564 set_gdbarch_float_bit (gdbarch
, 32);
5565 set_gdbarch_double_bit (gdbarch
, 64);
5566 set_gdbarch_long_double_bit (gdbarch
, 64);
5567 set_gdbarch_register_raw_size (gdbarch
, mips_register_raw_size
);
5568 set_gdbarch_max_register_raw_size (gdbarch
, 8);
5569 set_gdbarch_max_register_virtual_size (gdbarch
, 8);
5570 tdep
->found_abi
= found_abi
;
5571 tdep
->mips_abi
= mips_abi
;
5576 set_gdbarch_push_arguments (gdbarch
, mips_o32_push_arguments
);
5577 set_gdbarch_store_return_value (gdbarch
, mips_o32_store_return_value
);
5578 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o32_extract_return_value
);
5579 tdep
->mips_default_saved_regsize
= 4;
5580 tdep
->mips_default_stack_argsize
= 4;
5581 tdep
->mips_fp_register_double
= 0;
5582 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5583 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5584 tdep
->gdb_target_is_mips64
= 0;
5585 tdep
->default_mask_address_p
= 0;
5586 set_gdbarch_long_bit (gdbarch
, 32);
5587 set_gdbarch_ptr_bit (gdbarch
, 32);
5588 set_gdbarch_long_long_bit (gdbarch
, 64);
5589 set_gdbarch_reg_struct_has_addr (gdbarch
,
5590 mips_o32_reg_struct_has_addr
);
5591 set_gdbarch_use_struct_convention (gdbarch
,
5592 mips_o32_use_struct_convention
);
5595 set_gdbarch_push_arguments (gdbarch
, mips_o64_push_arguments
);
5596 set_gdbarch_store_return_value (gdbarch
, mips_o64_store_return_value
);
5597 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_o64_extract_return_value
);
5598 tdep
->mips_default_saved_regsize
= 8;
5599 tdep
->mips_default_stack_argsize
= 8;
5600 tdep
->mips_fp_register_double
= 1;
5601 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
5602 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
5603 tdep
->gdb_target_is_mips64
= 1;
5604 tdep
->default_mask_address_p
= 0;
5605 set_gdbarch_long_bit (gdbarch
, 32);
5606 set_gdbarch_ptr_bit (gdbarch
, 32);
5607 set_gdbarch_long_long_bit (gdbarch
, 64);
5608 set_gdbarch_reg_struct_has_addr (gdbarch
,
5609 mips_o32_reg_struct_has_addr
);
5610 set_gdbarch_use_struct_convention (gdbarch
,
5611 mips_o32_use_struct_convention
);
5613 case MIPS_ABI_EABI32
:
5614 set_gdbarch_push_arguments (gdbarch
, mips_eabi_push_arguments
);
5615 set_gdbarch_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5616 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5617 tdep
->mips_default_saved_regsize
= 4;
5618 tdep
->mips_default_stack_argsize
= 4;
5619 tdep
->mips_fp_register_double
= 0;
5620 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5621 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5622 tdep
->gdb_target_is_mips64
= 0;
5623 tdep
->default_mask_address_p
= 0;
5624 set_gdbarch_long_bit (gdbarch
, 32);
5625 set_gdbarch_ptr_bit (gdbarch
, 32);
5626 set_gdbarch_long_long_bit (gdbarch
, 64);
5627 set_gdbarch_reg_struct_has_addr (gdbarch
,
5628 mips_eabi_reg_struct_has_addr
);
5629 set_gdbarch_use_struct_convention (gdbarch
,
5630 mips_eabi_use_struct_convention
);
5632 case MIPS_ABI_EABI64
:
5633 set_gdbarch_push_arguments (gdbarch
, mips_eabi_push_arguments
);
5634 set_gdbarch_store_return_value (gdbarch
, mips_eabi_store_return_value
);
5635 set_gdbarch_deprecated_extract_return_value (gdbarch
, mips_eabi_extract_return_value
);
5636 tdep
->mips_default_saved_regsize
= 8;
5637 tdep
->mips_default_stack_argsize
= 8;
5638 tdep
->mips_fp_register_double
= 1;
5639 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5640 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5641 tdep
->gdb_target_is_mips64
= 1;
5642 tdep
->default_mask_address_p
= 0;
5643 set_gdbarch_long_bit (gdbarch
, 64);
5644 set_gdbarch_ptr_bit (gdbarch
, 64);
5645 set_gdbarch_long_long_bit (gdbarch
, 64);
5646 set_gdbarch_reg_struct_has_addr (gdbarch
,
5647 mips_eabi_reg_struct_has_addr
);
5648 set_gdbarch_use_struct_convention (gdbarch
,
5649 mips_eabi_use_struct_convention
);
5652 set_gdbarch_push_arguments (gdbarch
, mips_n32n64_push_arguments
);
5653 set_gdbarch_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5654 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5655 tdep
->mips_default_saved_regsize
= 8;
5656 tdep
->mips_default_stack_argsize
= 8;
5657 tdep
->mips_fp_register_double
= 1;
5658 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5659 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5660 tdep
->gdb_target_is_mips64
= 1;
5661 tdep
->default_mask_address_p
= 0;
5662 set_gdbarch_long_bit (gdbarch
, 32);
5663 set_gdbarch_ptr_bit (gdbarch
, 32);
5664 set_gdbarch_long_long_bit (gdbarch
, 64);
5666 /* Set up the disassembler info, so that we get the right
5667 register names from libopcodes. */
5668 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
5669 tm_print_insn_info
.arch
= bfd_arch_mips
;
5670 if (info
.bfd_arch_info
!= NULL
5671 && info
.bfd_arch_info
->arch
== bfd_arch_mips
5672 && info
.bfd_arch_info
->mach
)
5673 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
5675 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
5677 set_gdbarch_use_struct_convention (gdbarch
,
5678 mips_n32n64_use_struct_convention
);
5679 set_gdbarch_reg_struct_has_addr (gdbarch
,
5680 mips_n32n64_reg_struct_has_addr
);
5683 set_gdbarch_push_arguments (gdbarch
, mips_n32n64_push_arguments
);
5684 set_gdbarch_store_return_value (gdbarch
, mips_n32n64_store_return_value
);
5685 set_gdbarch_extract_return_value (gdbarch
, mips_n32n64_extract_return_value
);
5686 tdep
->mips_default_saved_regsize
= 8;
5687 tdep
->mips_default_stack_argsize
= 8;
5688 tdep
->mips_fp_register_double
= 1;
5689 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
5690 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
5691 tdep
->gdb_target_is_mips64
= 1;
5692 tdep
->default_mask_address_p
= 0;
5693 set_gdbarch_long_bit (gdbarch
, 64);
5694 set_gdbarch_ptr_bit (gdbarch
, 64);
5695 set_gdbarch_long_long_bit (gdbarch
, 64);
5697 /* Set up the disassembler info, so that we get the right
5698 register names from libopcodes. */
5699 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
5700 tm_print_insn_info
.arch
= bfd_arch_mips
;
5701 if (info
.bfd_arch_info
!= NULL
5702 && info
.bfd_arch_info
->arch
== bfd_arch_mips
5703 && info
.bfd_arch_info
->mach
)
5704 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
5706 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
5708 set_gdbarch_use_struct_convention (gdbarch
,
5709 mips_n32n64_use_struct_convention
);
5710 set_gdbarch_reg_struct_has_addr (gdbarch
,
5711 mips_n32n64_reg_struct_has_addr
);
5714 internal_error (__FILE__
, __LINE__
,
5715 "unknown ABI in switch");
5718 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5719 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5722 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5723 flag in object files because to do so would make it impossible to
5724 link with libraries compiled without "-gp32". This is
5725 unnecessarily restrictive.
5727 We could solve this problem by adding "-gp32" multilibs to gcc,
5728 but to set this flag before gcc is built with such multilibs will
5729 break too many systems.''
5731 But even more unhelpfully, the default linker output target for
5732 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5733 for 64-bit programs - you need to change the ABI to change this,
5734 and not all gcc targets support that currently. Therefore using
5735 this flag to detect 32-bit mode would do the wrong thing given
5736 the current gcc - it would make GDB treat these 64-bit programs
5737 as 32-bit programs by default. */
5739 /* enable/disable the MIPS FPU */
5740 if (!mips_fpu_type_auto
)
5741 tdep
->mips_fpu_type
= mips_fpu_type
;
5742 else if (info
.bfd_arch_info
!= NULL
5743 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5744 switch (info
.bfd_arch_info
->mach
)
5746 case bfd_mach_mips3900
:
5747 case bfd_mach_mips4100
:
5748 case bfd_mach_mips4111
:
5749 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
5751 case bfd_mach_mips4650
:
5752 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
5755 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5759 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
5761 /* MIPS version of register names. NOTE: At present the MIPS
5762 register name management is part way between the old -
5763 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
5764 Further work on it is required. */
5765 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5766 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5767 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
5768 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
5769 set_gdbarch_read_sp (gdbarch
, mips_read_sp
);
5770 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
5772 /* Add/remove bits from an address. The MIPS needs be careful to
5773 ensure that all 32 bit addresses are sign extended to 64 bits. */
5774 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5776 /* There's a mess in stack frame creation. See comments in
5777 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
5778 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
5779 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
5781 /* Map debug register numbers onto internal register numbers. */
5782 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5783 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
5785 /* Initialize a frame */
5786 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
5787 set_gdbarch_frame_init_saved_regs (gdbarch
, mips_frame_init_saved_regs
);
5789 /* MIPS version of CALL_DUMMY */
5791 set_gdbarch_call_dummy_p (gdbarch
, 1);
5792 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
5793 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
5794 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
5795 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
5796 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
5797 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
5798 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
5799 set_gdbarch_call_dummy_length (gdbarch
, 0);
5800 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
5801 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
5802 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
5803 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
5804 set_gdbarch_register_convertible (gdbarch
, mips_register_convertible
);
5805 set_gdbarch_register_convert_to_virtual (gdbarch
,
5806 mips_register_convert_to_virtual
);
5807 set_gdbarch_register_convert_to_raw (gdbarch
,
5808 mips_register_convert_to_raw
);
5810 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
5812 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
5813 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
5815 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5816 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5817 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
5819 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5820 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
5822 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5823 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5824 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5826 set_gdbarch_function_start_offset (gdbarch
, 0);
5828 /* There are MIPS targets which do not yet use this since they still
5829 define REGISTER_VIRTUAL_TYPE. */
5830 set_gdbarch_register_virtual_type (gdbarch
, mips_register_virtual_type
);
5831 set_gdbarch_register_virtual_size (gdbarch
, generic_register_size
);
5833 set_gdbarch_do_registers_info (gdbarch
, mips_do_registers_info
);
5834 set_gdbarch_pc_in_sigtramp (gdbarch
, mips_pc_in_sigtramp
);
5836 /* Hook in OS ABI-specific overrides, if they have been registered. */
5837 gdbarch_init_osabi (info
, gdbarch
, osabi
);
5843 mips_abi_update (char *ignore_args
, int from_tty
,
5844 struct cmd_list_element
*c
)
5846 struct gdbarch_info info
;
5848 /* Force the architecture to update, and (if it's a MIPS architecture)
5849 mips_gdbarch_init will take care of the rest. */
5850 gdbarch_info_init (&info
);
5851 gdbarch_update_p (info
);
5855 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5857 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5861 int ef_mips_32bitmode
;
5862 /* determine the ISA */
5863 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5881 /* determine the size of a pointer */
5882 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5883 fprintf_unfiltered (file
,
5884 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5886 fprintf_unfiltered (file
,
5887 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5889 fprintf_unfiltered (file
,
5890 "mips_dump_tdep: ef_mips_arch = %d\n",
5892 fprintf_unfiltered (file
,
5893 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5895 mips_abi_strings
[tdep
->mips_abi
]);
5896 fprintf_unfiltered (file
,
5897 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5898 mips_mask_address_p (),
5899 tdep
->default_mask_address_p
);
5901 fprintf_unfiltered (file
,
5902 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5903 FP_REGISTER_DOUBLE
);
5904 fprintf_unfiltered (file
,
5905 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5906 MIPS_DEFAULT_FPU_TYPE
,
5907 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5908 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5909 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5911 fprintf_unfiltered (file
,
5912 "mips_dump_tdep: MIPS_EABI = %d\n",
5914 fprintf_unfiltered (file
,
5915 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
5916 MIPS_LAST_FP_ARG_REGNUM
,
5917 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
5918 fprintf_unfiltered (file
,
5919 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5921 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5922 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5923 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5925 fprintf_unfiltered (file
,
5926 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
5927 MIPS_DEFAULT_SAVED_REGSIZE
);
5928 fprintf_unfiltered (file
,
5929 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
5930 FP_REGISTER_DOUBLE
);
5931 fprintf_unfiltered (file
,
5932 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
5933 MIPS_DEFAULT_STACK_ARGSIZE
);
5934 fprintf_unfiltered (file
,
5935 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
5936 MIPS_STACK_ARGSIZE
);
5937 fprintf_unfiltered (file
,
5938 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
5940 fprintf_unfiltered (file
,
5941 "mips_dump_tdep: A0_REGNUM = %d\n",
5943 fprintf_unfiltered (file
,
5944 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
5945 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
5946 fprintf_unfiltered (file
,
5947 "mips_dump_tdep: ATTACH_DETACH # %s\n",
5948 XSTRING (ATTACH_DETACH
));
5949 fprintf_unfiltered (file
,
5950 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
5952 fprintf_unfiltered (file
,
5953 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
5954 fprintf_unfiltered (file
,
5955 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
5957 fprintf_unfiltered (file
,
5958 "mips_dump_tdep: CPLUS_MARKER = %c\n",
5960 fprintf_unfiltered (file
,
5961 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
5963 fprintf_unfiltered (file
,
5964 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
5965 XSTRING (DO_REGISTERS_INFO
));
5966 fprintf_unfiltered (file
,
5967 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
5968 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
5969 fprintf_unfiltered (file
,
5970 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
5971 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
5972 fprintf_unfiltered (file
,
5973 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
5974 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
5975 fprintf_unfiltered (file
,
5976 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
5978 fprintf_unfiltered (file
,
5979 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
5981 fprintf_unfiltered (file
,
5982 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
5983 FIRST_EMBED_REGNUM
);
5984 fprintf_unfiltered (file
,
5985 "mips_dump_tdep: FPA0_REGNUM = %d\n",
5987 fprintf_unfiltered (file
,
5988 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
5989 GDB_TARGET_IS_MIPS64
);
5990 fprintf_unfiltered (file
,
5991 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
5992 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
5993 fprintf_unfiltered (file
,
5994 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
5995 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
5996 fprintf_unfiltered (file
,
5997 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
5999 fprintf_unfiltered (file
,
6000 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
6001 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
6002 fprintf_unfiltered (file
,
6003 "mips_dump_tdep: HI_REGNUM = %d\n",
6005 fprintf_unfiltered (file
,
6006 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
6007 fprintf_unfiltered (file
,
6008 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
6009 fprintf_unfiltered (file
,
6010 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
6011 XSTRING (IGNORE_HELPER_CALL (PC
)));
6012 fprintf_unfiltered (file
,
6013 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
6014 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
6015 fprintf_unfiltered (file
,
6016 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
6017 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
6018 fprintf_unfiltered (file
,
6019 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
6020 fprintf_unfiltered (file
,
6021 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
6023 fprintf_unfiltered (file
,
6024 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
6025 fprintf_unfiltered (file
,
6026 "mips_dump_tdep: LO_REGNUM = %d\n",
6028 #ifdef MACHINE_CPROC_FP_OFFSET
6029 fprintf_unfiltered (file
,
6030 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
6031 MACHINE_CPROC_FP_OFFSET
);
6033 #ifdef MACHINE_CPROC_PC_OFFSET
6034 fprintf_unfiltered (file
,
6035 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
6036 MACHINE_CPROC_PC_OFFSET
);
6038 #ifdef MACHINE_CPROC_SP_OFFSET
6039 fprintf_unfiltered (file
,
6040 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
6041 MACHINE_CPROC_SP_OFFSET
);
6043 fprintf_unfiltered (file
,
6044 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
6045 fprintf_unfiltered (file
,
6046 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
6047 fprintf_unfiltered (file
,
6048 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
6050 fprintf_unfiltered (file
,
6051 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
6052 fprintf_unfiltered (file
,
6053 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
6054 fprintf_unfiltered (file
,
6055 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
6056 fprintf_unfiltered (file
,
6057 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
6059 fprintf_unfiltered (file
,
6060 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
6061 MIPS_LAST_ARG_REGNUM
,
6062 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
6063 fprintf_unfiltered (file
,
6064 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
6066 fprintf_unfiltered (file
,
6067 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
6068 fprintf_unfiltered (file
,
6069 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
6070 MIPS_SAVED_REGSIZE
);
6071 fprintf_unfiltered (file
,
6072 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
6073 fprintf_unfiltered (file
,
6074 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
6075 XSTRING (MSYMBOL_SIZE (MSYM
)));
6076 fprintf_unfiltered (file
,
6077 "mips_dump_tdep: OP_LDFPR = used?\n");
6078 fprintf_unfiltered (file
,
6079 "mips_dump_tdep: OP_LDGPR = used?\n");
6080 fprintf_unfiltered (file
,
6081 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
6082 fprintf_unfiltered (file
,
6083 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
6084 fprintf_unfiltered (file
,
6085 "mips_dump_tdep: PRID_REGNUM = %d\n",
6087 fprintf_unfiltered (file
,
6088 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
6089 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
6090 fprintf_unfiltered (file
,
6091 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
6092 fprintf_unfiltered (file
,
6093 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
6094 fprintf_unfiltered (file
,
6095 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
6096 fprintf_unfiltered (file
,
6097 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
6098 fprintf_unfiltered (file
,
6099 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
6100 fprintf_unfiltered (file
,
6101 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
6102 fprintf_unfiltered (file
,
6103 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
6104 fprintf_unfiltered (file
,
6105 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
6106 fprintf_unfiltered (file
,
6107 "mips_dump_tdep: PROC_PC_REG = function?\n");
6108 fprintf_unfiltered (file
,
6109 "mips_dump_tdep: PROC_REG_MASK = function?\n");
6110 fprintf_unfiltered (file
,
6111 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
6112 fprintf_unfiltered (file
,
6113 "mips_dump_tdep: PROC_SYMBOL = function?\n");
6114 fprintf_unfiltered (file
,
6115 "mips_dump_tdep: PS_REGNUM = %d\n",
6117 fprintf_unfiltered (file
,
6118 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
6120 fprintf_unfiltered (file
,
6121 "mips_dump_tdep: RA_REGNUM = %d\n",
6123 fprintf_unfiltered (file
,
6124 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
6125 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
6126 fprintf_unfiltered (file
,
6127 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
6128 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
6129 fprintf_unfiltered (file
,
6130 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
6131 fprintf_unfiltered (file
,
6132 "mips_dump_tdep: ROUND_DOWN = function?\n");
6133 fprintf_unfiltered (file
,
6134 "mips_dump_tdep: ROUND_UP = function?\n");
6136 fprintf_unfiltered (file
,
6137 "mips_dump_tdep: SAVED_BYTES = %d\n",
6141 fprintf_unfiltered (file
,
6142 "mips_dump_tdep: SAVED_FP = %d\n",
6146 fprintf_unfiltered (file
,
6147 "mips_dump_tdep: SAVED_PC = %d\n",
6150 fprintf_unfiltered (file
,
6151 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
6152 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
6153 fprintf_unfiltered (file
,
6154 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
6155 fprintf_unfiltered (file
,
6156 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
6158 fprintf_unfiltered (file
,
6159 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
6160 SIGFRAME_FPREGSAVE_OFF
);
6161 fprintf_unfiltered (file
,
6162 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
6164 fprintf_unfiltered (file
,
6165 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
6166 SIGFRAME_REGSAVE_OFF
);
6167 fprintf_unfiltered (file
,
6168 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
6170 fprintf_unfiltered (file
,
6171 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
6172 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
6173 fprintf_unfiltered (file
,
6174 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
6175 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
6176 fprintf_unfiltered (file
,
6177 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
6178 SOFTWARE_SINGLE_STEP_P ());
6179 fprintf_unfiltered (file
,
6180 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
6181 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
6182 #ifdef STACK_END_ADDR
6183 fprintf_unfiltered (file
,
6184 "mips_dump_tdep: STACK_END_ADDR = %d\n",
6187 fprintf_unfiltered (file
,
6188 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
6189 XSTRING (STEP_SKIPS_DELAY (PC
)));
6190 fprintf_unfiltered (file
,
6191 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
6192 STEP_SKIPS_DELAY_P
);
6193 fprintf_unfiltered (file
,
6194 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
6195 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
6196 fprintf_unfiltered (file
,
6197 "mips_dump_tdep: T9_REGNUM = %d\n",
6199 fprintf_unfiltered (file
,
6200 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
6201 fprintf_unfiltered (file
,
6202 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
6203 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
6204 fprintf_unfiltered (file
,
6205 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
6206 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
6207 fprintf_unfiltered (file
,
6208 "mips_dump_tdep: TARGET_MIPS = used?\n");
6209 fprintf_unfiltered (file
,
6210 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
6211 XSTRING (TM_PRINT_INSN_MACH
));
6213 fprintf_unfiltered (file
,
6214 "mips_dump_tdep: TRACE_CLEAR # %s\n",
6215 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
6218 fprintf_unfiltered (file
,
6219 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
6222 #ifdef TRACE_FLAVOR_SIZE
6223 fprintf_unfiltered (file
,
6224 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
6228 fprintf_unfiltered (file
,
6229 "mips_dump_tdep: TRACE_SET # %s\n",
6230 XSTRING (TRACE_SET (X
,STATE
)));
6232 fprintf_unfiltered (file
,
6233 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
6234 #ifdef UNUSED_REGNUM
6235 fprintf_unfiltered (file
,
6236 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
6239 fprintf_unfiltered (file
,
6240 "mips_dump_tdep: V0_REGNUM = %d\n",
6242 fprintf_unfiltered (file
,
6243 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
6244 (long) VM_MIN_ADDRESS
);
6246 fprintf_unfiltered (file
,
6247 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
6250 fprintf_unfiltered (file
,
6251 "mips_dump_tdep: ZERO_REGNUM = %d\n",
6253 fprintf_unfiltered (file
,
6254 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
6257 fprintf_unfiltered (file
,
6258 "mips_dump_tdep: OS ABI = %s\n",
6259 gdbarch_osabi_name (tdep
->osabi
));
6263 _initialize_mips_tdep (void)
6265 static struct cmd_list_element
*mipsfpulist
= NULL
;
6266 struct cmd_list_element
*c
;
6268 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6269 if (MIPS_ABI_LAST
+ 1
6270 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6271 internal_error (__FILE__
, __LINE__
, "mips_abi_strings out of sync");
6273 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6274 if (!tm_print_insn
) /* Someone may have already set it */
6275 tm_print_insn
= gdb_print_insn_mips
;
6277 /* Add root prefix command for all "set mips"/"show mips" commands */
6278 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6279 "Various MIPS specific commands.",
6280 &setmipscmdlist
, "set mips ", 0, &setlist
);
6282 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6283 "Various MIPS specific commands.",
6284 &showmipscmdlist
, "show mips ", 0, &showlist
);
6286 /* Allow the user to override the saved register size. */
6287 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
6290 &mips_saved_regsize_string
, "\
6291 Set size of general purpose registers saved on the stack.\n\
6292 This option can be set to one of:\n\
6293 32 - Force GDB to treat saved GP registers as 32-bit\n\
6294 64 - Force GDB to treat saved GP registers as 64-bit\n\
6295 auto - Allow GDB to use the target's default setting or autodetect the\n\
6296 saved GP register size from information contained in the executable.\n\
6301 /* Allow the user to override the argument stack size. */
6302 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
6305 &mips_stack_argsize_string
, "\
6306 Set the amount of stack space reserved for each argument.\n\
6307 This option can be set to one of:\n\
6308 32 - Force GDB to allocate 32-bit chunks per argument\n\
6309 64 - Force GDB to allocate 64-bit chunks per argument\n\
6310 auto - Allow GDB to determine the correct setting from the current\n\
6311 target and executable (default)",
6315 /* Allow the user to override the ABI. */
6316 c
= add_set_enum_cmd
6317 ("abi", class_obscure
, mips_abi_strings
, &mips_abi_string
,
6318 "Set the ABI used by this program.\n"
6319 "This option can be set to one of:\n"
6320 " auto - the default ABI associated with the current binary\n"
6328 add_show_from_set (c
, &showmipscmdlist
);
6329 set_cmd_sfunc (c
, mips_abi_update
);
6331 /* Let the user turn off floating point and set the fence post for
6332 heuristic_proc_start. */
6334 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6335 "Set use of MIPS floating-point coprocessor.",
6336 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6337 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6338 "Select single-precision MIPS floating-point coprocessor.",
6340 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6341 "Select double-precision MIPS floating-point coprocessor.",
6343 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6344 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6345 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6346 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6347 "Select no MIPS floating-point coprocessor.",
6349 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6350 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6351 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6352 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6353 "Select MIPS floating-point coprocessor automatically.",
6355 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6356 "Show current use of MIPS floating-point coprocessor target.",
6359 /* We really would like to have both "0" and "unlimited" work, but
6360 command.c doesn't deal with that. So make it a var_zinteger
6361 because the user can always use "999999" or some such for unlimited. */
6362 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
6363 (char *) &heuristic_fence_post
,
6365 Set the distance searched for the start of a function.\n\
6366 If you are debugging a stripped executable, GDB needs to search through the\n\
6367 program for the start of a function. This command sets the distance of the\n\
6368 search. The only need to set it is when debugging a stripped executable.",
6370 /* We need to throw away the frame cache when we set this, since it
6371 might change our ability to get backtraces. */
6372 set_cmd_sfunc (c
, reinit_frame_cache_sfunc
);
6373 add_show_from_set (c
, &showlist
);
6375 /* Allow the user to control whether the upper bits of 64-bit
6376 addresses should be zeroed. */
6377 add_setshow_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
, "\
6378 Set zeroing of upper 32 bits of 64-bit addresses.\n\
6379 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6380 allow GDB to determine the correct value.\n", "\
6381 Show zeroing of upper 32 bits of 64-bit addresses.",
6382 NULL
, show_mask_address
,
6383 &setmipscmdlist
, &showmipscmdlist
);
6385 /* Allow the user to control the size of 32 bit registers within the
6386 raw remote packet. */
6387 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
6390 (char *)&mips64_transfers_32bit_regs_p
, "\
6391 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
6392 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6393 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6394 64 bits for others. Use \"off\" to disable compatibility mode",
6398 /* Debug this files internals. */
6399 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
6400 &mips_debug
, "Set mips debugging.\n\
6401 When non-zero, mips specific debugging is enabled.", &setdebuglist
),