1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2016 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
47 #include "frame-unwind.h"
48 #include "frame-base.h"
49 #include "trad-frame.h"
51 #include "floatformat.h"
53 #include "target-descriptions.h"
54 #include "dwarf2-frame.h"
55 #include "user-regs.h"
60 static const struct objfile_data
*mips_pdr_data
;
62 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
64 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
66 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
67 static int mips16_instruction_has_delay_slot (unsigned short inst
,
70 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
73 CORE_ADDR addr
, int mustbe32
);
74 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
75 CORE_ADDR addr
, int mustbe32
);
77 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
78 struct frame_info
*, const char *);
80 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
81 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
82 #define ST0_FR (1 << 26)
84 /* The sizes of floating point registers. */
88 MIPS_FPU_SINGLE_REGSIZE
= 4,
89 MIPS_FPU_DOUBLE_REGSIZE
= 8
98 static const char *mips_abi_string
;
100 static const char *const mips_abi_strings
[] = {
111 /* For backwards compatibility we default to MIPS16. This flag is
112 overridden as soon as unambiguous ELF file flags tell us the
113 compressed ISA encoding used. */
114 static const char mips_compression_mips16
[] = "mips16";
115 static const char mips_compression_micromips
[] = "micromips";
116 static const char *const mips_compression_strings
[] =
118 mips_compression_mips16
,
119 mips_compression_micromips
,
123 static const char *mips_compression_string
= mips_compression_mips16
;
125 /* The standard register names, and all the valid aliases for them. */
126 struct register_alias
132 /* Aliases for o32 and most other ABIs. */
133 const struct register_alias mips_o32_aliases
[] = {
140 /* Aliases for n32 and n64. */
141 const struct register_alias mips_n32_n64_aliases
[] = {
148 /* Aliases for ABI-independent registers. */
149 const struct register_alias mips_register_aliases
[] = {
150 /* The architecture manuals specify these ABI-independent names for
152 #define R(n) { "r" #n, n }
153 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
154 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
155 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
156 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
159 /* k0 and k1 are sometimes called these instead (for "kernel
164 /* This is the traditional GDB name for the CP0 status register. */
165 { "sr", MIPS_PS_REGNUM
},
167 /* This is the traditional GDB name for the CP0 BadVAddr register. */
168 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
170 /* This is the traditional GDB name for the FCSR. */
171 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
174 const struct register_alias mips_numeric_register_aliases
[] = {
175 #define R(n) { #n, n }
176 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
177 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
178 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
179 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
183 #ifndef MIPS_DEFAULT_FPU_TYPE
184 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
186 static int mips_fpu_type_auto
= 1;
187 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
189 static unsigned int mips_debug
= 0;
191 /* Properties (for struct target_desc) describing the g/G packet
193 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
194 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
196 struct target_desc
*mips_tdesc_gp32
;
197 struct target_desc
*mips_tdesc_gp64
;
199 const struct mips_regnum
*
200 mips_regnum (struct gdbarch
*gdbarch
)
202 return gdbarch_tdep (gdbarch
)->regnum
;
206 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
208 return mips_regnum (gdbarch
)->fp0
+ 12;
211 /* Return 1 if REGNUM refers to a floating-point general register, raw
212 or cooked. Otherwise return 0. */
215 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
217 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
219 return (rawnum
>= mips_regnum (gdbarch
)->fp0
220 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
223 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
225 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
227 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
228 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
230 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
231 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
233 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
235 /* Return the MIPS ABI associated with GDBARCH. */
237 mips_abi (struct gdbarch
*gdbarch
)
239 return gdbarch_tdep (gdbarch
)->mips_abi
;
243 mips_isa_regsize (struct gdbarch
*gdbarch
)
245 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
247 /* If we know how big the registers are, use that size. */
248 if (tdep
->register_size_valid_p
)
249 return tdep
->register_size
;
251 /* Fall back to the previous behavior. */
252 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
253 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
256 /* Return the currently configured (or set) saved register size. */
259 mips_abi_regsize (struct gdbarch
*gdbarch
)
261 switch (mips_abi (gdbarch
))
263 case MIPS_ABI_EABI32
:
269 case MIPS_ABI_EABI64
:
271 case MIPS_ABI_UNKNOWN
:
274 internal_error (__FILE__
, __LINE__
, _("bad switch"));
278 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
279 are some functions to handle addresses associated with compressed
280 code including but not limited to testing, setting, or clearing
281 bit 0 of such addresses. */
283 /* Return one iff compressed code is the MIPS16 instruction set. */
286 is_mips16_isa (struct gdbarch
*gdbarch
)
288 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
291 /* Return one iff compressed code is the microMIPS instruction set. */
294 is_micromips_isa (struct gdbarch
*gdbarch
)
296 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
299 /* Return one iff ADDR denotes compressed code. */
302 is_compact_addr (CORE_ADDR addr
)
307 /* Return one iff ADDR denotes standard ISA code. */
310 is_mips_addr (CORE_ADDR addr
)
312 return !is_compact_addr (addr
);
315 /* Return one iff ADDR denotes MIPS16 code. */
318 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
320 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
323 /* Return one iff ADDR denotes microMIPS code. */
326 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
328 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
331 /* Strip the ISA (compression) bit off from ADDR. */
334 unmake_compact_addr (CORE_ADDR addr
)
336 return ((addr
) & ~(CORE_ADDR
) 1);
339 /* Add the ISA (compression) bit to ADDR. */
342 make_compact_addr (CORE_ADDR addr
)
344 return ((addr
) | (CORE_ADDR
) 1);
347 /* Extern version of unmake_compact_addr; we use a separate function
348 so that unmake_compact_addr can be inlined throughout this file. */
351 mips_unmake_compact_addr (CORE_ADDR addr
)
353 return unmake_compact_addr (addr
);
356 /* Functions for setting and testing a bit in a minimal symbol that
357 marks it as MIPS16 or microMIPS function. The MSB of the minimal
358 symbol's "info" field is used for this purpose.
360 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
361 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
362 one of the "special" bits in a minimal symbol to mark it accordingly.
363 The test checks an ELF-private flag that is valid for true function
364 symbols only; for synthetic symbols such as for PLT stubs that have
365 no ELF-private part at all the MIPS BFD backend arranges for this
366 information to be carried in the asymbol's udata field instead.
368 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
369 in a minimal symbol. */
372 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
374 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
375 unsigned char st_other
;
377 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
378 st_other
= elfsym
->internal_elf_sym
.st_other
;
379 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
380 st_other
= sym
->udata
.i
;
384 if (ELF_ST_IS_MICROMIPS (st_other
))
386 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
387 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
389 else if (ELF_ST_IS_MIPS16 (st_other
))
391 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
392 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
396 /* Return one iff MSYM refers to standard ISA code. */
399 msymbol_is_mips (struct minimal_symbol
*msym
)
401 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
402 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
405 /* Return one iff MSYM refers to MIPS16 code. */
408 msymbol_is_mips16 (struct minimal_symbol
*msym
)
410 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
413 /* Return one iff MSYM refers to microMIPS code. */
416 msymbol_is_micromips (struct minimal_symbol
*msym
)
418 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
421 /* Set the ISA bit in the main symbol too, complementing the corresponding
422 minimal symbol setting and reflecting the run-time value of the symbol.
423 The need for comes from the ISA bit having been cleared as code in
424 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
425 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
426 of symbols referring to compressed code different in GDB to the values
427 used by actual code. That in turn makes them evaluate incorrectly in
428 expressions, producing results different to what the same expressions
429 yield when compiled into the program being debugged. */
432 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
434 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
436 /* We are in symbol reading so it is OK to cast away constness. */
437 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
438 CORE_ADDR compact_block_start
;
439 struct bound_minimal_symbol msym
;
441 compact_block_start
= BLOCK_START (block
) | 1;
442 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
443 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
445 BLOCK_START (block
) = compact_block_start
;
450 /* XFER a value from the big/little/left end of the register.
451 Depending on the size of the value it might occupy the entire
452 register or just part of it. Make an allowance for this, aligning
453 things accordingly. */
456 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
457 int reg_num
, int length
,
458 enum bfd_endian endian
, gdb_byte
*in
,
459 const gdb_byte
*out
, int buf_offset
)
463 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
464 /* Need to transfer the left or right part of the register, based on
465 the targets byte order. */
469 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
471 case BFD_ENDIAN_LITTLE
:
474 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
478 internal_error (__FILE__
, __LINE__
, _("bad switch"));
481 fprintf_unfiltered (gdb_stderr
,
482 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
483 reg_num
, reg_offset
, buf_offset
, length
);
484 if (mips_debug
&& out
!= NULL
)
487 fprintf_unfiltered (gdb_stdlog
, "out ");
488 for (i
= 0; i
< length
; i
++)
489 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
492 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
495 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
497 if (mips_debug
&& in
!= NULL
)
500 fprintf_unfiltered (gdb_stdlog
, "in ");
501 for (i
= 0; i
< length
; i
++)
502 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
505 fprintf_unfiltered (gdb_stdlog
, "\n");
508 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
509 compatiblity mode. A return value of 1 means that we have
510 physical 64-bit registers, but should treat them as 32-bit registers. */
513 mips2_fp_compat (struct frame_info
*frame
)
515 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
516 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
518 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
522 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
523 in all the places we deal with FP registers. PR gdb/413. */
524 /* Otherwise check the FR bit in the status register - it controls
525 the FP compatiblity mode. If it is clear we are in compatibility
527 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
534 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
536 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
538 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
540 /* The list of available "set mips " and "show mips " commands. */
542 static struct cmd_list_element
*setmipscmdlist
= NULL
;
543 static struct cmd_list_element
*showmipscmdlist
= NULL
;
545 /* Integer registers 0 thru 31 are handled explicitly by
546 mips_register_name(). Processor specific registers 32 and above
547 are listed in the following tables. */
550 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
554 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
555 "sr", "lo", "hi", "bad", "cause", "pc",
556 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
557 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
558 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
559 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
563 /* Names of IDT R3041 registers. */
565 static const char *mips_r3041_reg_names
[] = {
566 "sr", "lo", "hi", "bad", "cause", "pc",
567 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
568 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
569 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
570 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
571 "fsr", "fir", "", /*"fp" */ "",
572 "", "", "bus", "ccfg", "", "", "", "",
573 "", "", "port", "cmp", "", "", "epc", "prid",
576 /* Names of tx39 registers. */
578 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
579 "sr", "lo", "hi", "bad", "cause", "pc",
580 "", "", "", "", "", "", "", "",
581 "", "", "", "", "", "", "", "",
582 "", "", "", "", "", "", "", "",
583 "", "", "", "", "", "", "", "",
585 "", "", "", "", "", "", "", "",
586 "", "", "config", "cache", "debug", "depc", "epc",
589 /* Names of IRIX registers. */
590 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
591 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
592 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
593 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
594 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
595 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
598 /* Names of registers with Linux kernels. */
599 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
600 "sr", "lo", "hi", "bad", "cause", "pc",
601 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
602 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
603 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
604 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
609 /* Return the name of the register corresponding to REGNO. */
611 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
613 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
614 /* GPR names for all ABIs other than n32/n64. */
615 static char *mips_gpr_names
[] = {
616 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
617 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
618 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
619 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
622 /* GPR names for n32 and n64 ABIs. */
623 static char *mips_n32_n64_gpr_names
[] = {
624 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
625 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
626 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
627 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
630 enum mips_abi abi
= mips_abi (gdbarch
);
632 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
633 but then don't make the raw register names visible. This (upper)
634 range of user visible register numbers are the pseudo-registers.
636 This approach was adopted accommodate the following scenario:
637 It is possible to debug a 64-bit device using a 32-bit
638 programming model. In such instances, the raw registers are
639 configured to be 64-bits wide, while the pseudo registers are
640 configured to be 32-bits wide. The registers that the user
641 sees - the pseudo registers - match the users expectations
642 given the programming model being used. */
643 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
644 if (regno
< gdbarch_num_regs (gdbarch
))
647 /* The MIPS integer registers are always mapped from 0 to 31. The
648 names of the registers (which reflects the conventions regarding
649 register use) vary depending on the ABI. */
650 if (0 <= rawnum
&& rawnum
< 32)
652 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
653 return mips_n32_n64_gpr_names
[rawnum
];
655 return mips_gpr_names
[rawnum
];
657 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
658 return tdesc_register_name (gdbarch
, rawnum
);
659 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
661 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
662 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
663 return tdep
->mips_processor_reg_names
[rawnum
- 32];
667 internal_error (__FILE__
, __LINE__
,
668 _("mips_register_name: bad register number %d"), rawnum
);
671 /* Return the groups that a MIPS register can be categorised into. */
674 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
675 struct reggroup
*reggroup
)
680 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
681 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
682 if (reggroup
== all_reggroup
)
684 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
685 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
686 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
687 (gdbarch), as not all architectures are multi-arch. */
688 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
689 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
690 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
692 if (reggroup
== float_reggroup
)
693 return float_p
&& pseudo
;
694 if (reggroup
== vector_reggroup
)
695 return vector_p
&& pseudo
;
696 if (reggroup
== general_reggroup
)
697 return (!vector_p
&& !float_p
) && pseudo
;
698 /* Save the pseudo registers. Need to make certain that any code
699 extracting register values from a saved register cache also uses
701 if (reggroup
== save_reggroup
)
702 return raw_p
&& pseudo
;
703 /* Restore the same pseudo register. */
704 if (reggroup
== restore_reggroup
)
705 return raw_p
&& pseudo
;
709 /* Return the groups that a MIPS register can be categorised into.
710 This version is only used if we have a target description which
711 describes real registers (and their groups). */
714 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
715 struct reggroup
*reggroup
)
717 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
718 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
721 /* Only save, restore, and display the pseudo registers. Need to
722 make certain that any code extracting register values from a
723 saved register cache also uses pseudo registers.
725 Note: saving and restoring the pseudo registers is slightly
726 strange; if we have 64 bits, we should save and restore all
727 64 bits. But this is hard and has little benefit. */
731 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
735 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
738 /* Map the symbol table registers which live in the range [1 *
739 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
740 registers. Take care of alignment and size problems. */
742 static enum register_status
743 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
744 int cookednum
, gdb_byte
*buf
)
746 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
747 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
748 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
749 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
750 return regcache_raw_read (regcache
, rawnum
, buf
);
751 else if (register_size (gdbarch
, rawnum
) >
752 register_size (gdbarch
, cookednum
))
754 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
755 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
758 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
760 enum register_status status
;
762 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
763 if (status
== REG_VALID
)
764 store_signed_integer (buf
, 4, byte_order
, regval
);
769 internal_error (__FILE__
, __LINE__
, _("bad register size"));
773 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
774 struct regcache
*regcache
, int cookednum
,
777 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
778 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
779 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
780 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
781 regcache_raw_write (regcache
, rawnum
, buf
);
782 else if (register_size (gdbarch
, rawnum
) >
783 register_size (gdbarch
, cookednum
))
785 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
786 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
789 /* Sign extend the shortened version of the register prior
790 to placing it in the raw register. This is required for
791 some mips64 parts in order to avoid unpredictable behavior. */
792 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
793 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
794 regcache_raw_write_signed (regcache
, rawnum
, regval
);
798 internal_error (__FILE__
, __LINE__
, _("bad register size"));
802 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
803 struct agent_expr
*ax
, int reg
)
805 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
806 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
807 && reg
< 2 * gdbarch_num_regs (gdbarch
));
809 ax_reg_mask (ax
, rawnum
);
815 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
816 struct agent_expr
*ax
, int reg
)
818 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
819 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
820 && reg
< 2 * gdbarch_num_regs (gdbarch
));
821 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
825 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
827 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
828 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
831 ax_simple (ax
, aop_lsh
);
834 ax_simple (ax
, aop_rsh_signed
);
838 internal_error (__FILE__
, __LINE__
, _("bad register size"));
843 /* Table to translate 3-bit register field to actual register number. */
844 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
846 /* Heuristic_proc_start may hunt through the text section for a long
847 time across a 2400 baud serial line. Allows the user to limit this
850 static int heuristic_fence_post
= 0;
852 /* Number of bytes of storage in the actual machine representation for
853 register N. NOTE: This defines the pseudo register type so need to
854 rebuild the architecture vector. */
856 static int mips64_transfers_32bit_regs_p
= 0;
859 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
860 struct cmd_list_element
*c
)
862 struct gdbarch_info info
;
863 gdbarch_info_init (&info
);
864 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
865 instead of relying on globals. Doing that would let generic code
866 handle the search for this specific architecture. */
867 if (!gdbarch_update_p (info
))
869 mips64_transfers_32bit_regs_p
= 0;
870 error (_("32-bit compatibility mode not supported"));
874 /* Convert to/from a register and the corresponding memory value. */
876 /* This predicate tests for the case of an 8 byte floating point
877 value that is being transferred to or from a pair of floating point
878 registers each of which are (or are considered to be) only 4 bytes
881 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
884 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
885 && register_size (gdbarch
, regnum
) == 4
886 && mips_float_register_p (gdbarch
, regnum
)
887 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
890 /* This predicate tests for the case of a value of less than 8
891 bytes in width that is being transfered to or from an 8 byte
892 general purpose register. */
894 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
897 int num_regs
= gdbarch_num_regs (gdbarch
);
899 return (register_size (gdbarch
, regnum
) == 8
900 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
901 && TYPE_LENGTH (type
) < 8);
905 mips_convert_register_p (struct gdbarch
*gdbarch
,
906 int regnum
, struct type
*type
)
908 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
909 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
913 mips_register_to_value (struct frame_info
*frame
, int regnum
,
914 struct type
*type
, gdb_byte
*to
,
915 int *optimizedp
, int *unavailablep
)
917 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
919 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
921 get_frame_register (frame
, regnum
+ 0, to
+ 4);
922 get_frame_register (frame
, regnum
+ 1, to
+ 0);
924 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
925 optimizedp
, unavailablep
))
928 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
929 optimizedp
, unavailablep
))
931 *optimizedp
= *unavailablep
= 0;
934 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
936 int len
= TYPE_LENGTH (type
);
939 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
940 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
941 optimizedp
, unavailablep
))
944 *optimizedp
= *unavailablep
= 0;
949 internal_error (__FILE__
, __LINE__
,
950 _("mips_register_to_value: unrecognized case"));
955 mips_value_to_register (struct frame_info
*frame
, int regnum
,
956 struct type
*type
, const gdb_byte
*from
)
958 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
960 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
962 put_frame_register (frame
, regnum
+ 0, from
+ 4);
963 put_frame_register (frame
, regnum
+ 1, from
+ 0);
965 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
968 int len
= TYPE_LENGTH (type
);
970 /* Sign extend values, irrespective of type, that are stored to
971 a 64-bit general purpose register. (32-bit unsigned values
972 are stored as signed quantities within a 64-bit register.
973 When performing an operation, in compiled code, that combines
974 a 32-bit unsigned value with a signed 64-bit value, a type
975 conversion is first performed that zeroes out the high 32 bits.) */
976 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
979 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
981 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
982 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
983 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
987 if (from
[len
-1] & 0x80)
988 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
990 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
991 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
992 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
997 internal_error (__FILE__
, __LINE__
,
998 _("mips_value_to_register: unrecognized case"));
1002 /* Return the GDB type object for the "standard" data type of data in
1005 static struct type
*
1006 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1008 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1009 if (mips_float_register_p (gdbarch
, regnum
))
1011 /* The floating-point registers raw, or cooked, always match
1012 mips_isa_regsize(), and also map 1:1, byte for byte. */
1013 if (mips_isa_regsize (gdbarch
) == 4)
1014 return builtin_type (gdbarch
)->builtin_float
;
1016 return builtin_type (gdbarch
)->builtin_double
;
1018 else if (regnum
< gdbarch_num_regs (gdbarch
))
1020 /* The raw or ISA registers. These are all sized according to
1022 if (mips_isa_regsize (gdbarch
) == 4)
1023 return builtin_type (gdbarch
)->builtin_int32
;
1025 return builtin_type (gdbarch
)->builtin_int64
;
1029 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1031 /* The cooked or ABI registers. These are sized according to
1032 the ABI (with a few complications). */
1033 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1034 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1035 return builtin_type (gdbarch
)->builtin_int32
;
1036 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1037 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1038 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1039 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1040 /* The pseudo/cooked view of the embedded registers is always
1041 32-bit. The raw view is handled below. */
1042 return builtin_type (gdbarch
)->builtin_int32
;
1043 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1044 /* The target, while possibly using a 64-bit register buffer,
1045 is only transfering 32-bits of each integer register.
1046 Reflect this in the cooked/pseudo (ABI) register value. */
1047 return builtin_type (gdbarch
)->builtin_int32
;
1048 else if (mips_abi_regsize (gdbarch
) == 4)
1049 /* The ABI is restricted to 32-bit registers (the ISA could be
1051 return builtin_type (gdbarch
)->builtin_int32
;
1054 return builtin_type (gdbarch
)->builtin_int64
;
1058 /* Return the GDB type for the pseudo register REGNUM, which is the
1059 ABI-level view. This function is only called if there is a target
1060 description which includes registers, so we know precisely the
1061 types of hardware registers. */
1063 static struct type
*
1064 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1066 const int num_regs
= gdbarch_num_regs (gdbarch
);
1067 int rawnum
= regnum
% num_regs
;
1068 struct type
*rawtype
;
1070 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1072 /* Absent registers are still absent. */
1073 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1074 if (TYPE_LENGTH (rawtype
) == 0)
1077 /* Present the floating point registers however the hardware did;
1078 do not try to convert between FPU layouts. */
1079 if (mips_float_register_p (gdbarch
, rawnum
))
1082 /* Floating-point control registers are always 32-bit even though for
1083 backwards compatibility reasons 64-bit targets will transfer them
1084 as 64-bit quantities even if using XML descriptions. */
1085 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1086 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1087 return builtin_type (gdbarch
)->builtin_int32
;
1089 /* Use pointer types for registers if we can. For n32 we can not,
1090 since we do not have a 64-bit pointer type. */
1091 if (mips_abi_regsize (gdbarch
)
1092 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1094 if (rawnum
== MIPS_SP_REGNUM
1095 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1096 return builtin_type (gdbarch
)->builtin_data_ptr
;
1097 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1098 return builtin_type (gdbarch
)->builtin_func_ptr
;
1101 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1102 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1103 || rawnum
== mips_regnum (gdbarch
)->lo
1104 || rawnum
== mips_regnum (gdbarch
)->hi
1105 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1106 || rawnum
== mips_regnum (gdbarch
)->cause
1107 || rawnum
== mips_regnum (gdbarch
)->pc
1108 || (mips_regnum (gdbarch
)->dspacc
!= -1
1109 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1110 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1111 return builtin_type (gdbarch
)->builtin_int32
;
1113 /* The pseudo/cooked view of embedded registers is always
1114 32-bit, even if the target transfers 64-bit values for them.
1115 New targets relying on XML descriptions should only transfer
1116 the necessary 32 bits, but older versions of GDB expected 64,
1117 so allow the target to provide 64 bits without interfering
1118 with the displayed type. */
1119 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1120 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1121 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1122 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1123 return builtin_type (gdbarch
)->builtin_int32
;
1125 /* For all other registers, pass through the hardware type. */
1129 /* Should the upper word of 64-bit addresses be zeroed? */
1130 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1133 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1135 switch (mask_address_var
)
1137 case AUTO_BOOLEAN_TRUE
:
1139 case AUTO_BOOLEAN_FALSE
:
1142 case AUTO_BOOLEAN_AUTO
:
1143 return tdep
->default_mask_address_p
;
1145 internal_error (__FILE__
, __LINE__
,
1146 _("mips_mask_address_p: bad switch"));
1152 show_mask_address (struct ui_file
*file
, int from_tty
,
1153 struct cmd_list_element
*c
, const char *value
)
1155 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1157 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1158 switch (mask_address_var
)
1160 case AUTO_BOOLEAN_TRUE
:
1161 printf_filtered ("The 32 bit mips address mask is enabled\n");
1163 case AUTO_BOOLEAN_FALSE
:
1164 printf_filtered ("The 32 bit mips address mask is disabled\n");
1166 case AUTO_BOOLEAN_AUTO
:
1168 ("The 32 bit address mask is set automatically. Currently %s\n",
1169 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1172 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1177 /* Tell if the program counter value in MEMADDR is in a standard ISA
1181 mips_pc_is_mips (CORE_ADDR memaddr
)
1183 struct bound_minimal_symbol sym
;
1185 /* Flags indicating that this is a MIPS16 or microMIPS function is
1186 stored by elfread.c in the high bit of the info field. Use this
1187 to decide if the function is standard MIPS. Otherwise if bit 0
1188 of the address is clear, then this is a standard MIPS function. */
1189 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1191 return msymbol_is_mips (sym
.minsym
);
1193 return is_mips_addr (memaddr
);
1196 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1199 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1201 struct bound_minimal_symbol sym
;
1203 /* A flag indicating that this is a MIPS16 function is stored by
1204 elfread.c in the high bit of the info field. Use this to decide
1205 if the function is MIPS16. Otherwise if bit 0 of the address is
1206 set, then ELF file flags will tell if this is a MIPS16 function. */
1207 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1209 return msymbol_is_mips16 (sym
.minsym
);
1211 return is_mips16_addr (gdbarch
, memaddr
);
1214 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1217 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1219 struct bound_minimal_symbol sym
;
1221 /* A flag indicating that this is a microMIPS function is stored by
1222 elfread.c in the high bit of the info field. Use this to decide
1223 if the function is microMIPS. Otherwise if bit 0 of the address
1224 is set, then ELF file flags will tell if this is a microMIPS
1226 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1228 return msymbol_is_micromips (sym
.minsym
);
1230 return is_micromips_addr (gdbarch
, memaddr
);
1233 /* Tell the ISA type of the function the program counter value in MEMADDR
1236 static enum mips_isa
1237 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1239 struct bound_minimal_symbol sym
;
1241 /* A flag indicating that this is a MIPS16 or a microMIPS function
1242 is stored by elfread.c in the high bit of the info field. Use
1243 this to decide if the function is MIPS16 or microMIPS or normal
1244 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1245 flags will tell if this is a MIPS16 or a microMIPS function. */
1246 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1249 if (msymbol_is_micromips (sym
.minsym
))
1250 return ISA_MICROMIPS
;
1251 else if (msymbol_is_mips16 (sym
.minsym
))
1258 if (is_mips_addr (memaddr
))
1260 else if (is_micromips_addr (gdbarch
, memaddr
))
1261 return ISA_MICROMIPS
;
1267 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1268 The need for comes from the ISA bit having been cleared, making
1269 addresses in FDE, range records, etc. referring to compressed code
1270 different to those in line information, the symbol table and finally
1271 the PC register. That in turn confuses many operations. */
1274 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1276 pc
= unmake_compact_addr (pc
);
1277 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1280 /* Recalculate the line record requested so that the resulting PC has
1281 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1282 this adjustment comes from some records associated with compressed
1283 code having the ISA bit cleared, most notably at function prologue
1284 ends. The ISA bit is in this context retrieved from the minimal
1285 symbol covering the address requested, which in turn has been
1286 constructed from the binary's symbol table rather than DWARF-2
1287 information. The correct setting of the ISA bit is required for
1288 breakpoint addresses to correctly match against the stop PC.
1290 As line entries can specify relative address adjustments we need to
1291 keep track of the absolute value of the last line address recorded
1292 in line information, so that we can calculate the actual address to
1293 apply the ISA bit adjustment to. We use PC for this tracking and
1294 keep the original address there.
1296 As such relative address adjustments can be odd within compressed
1297 code we need to keep track of the last line address with the ISA
1298 bit adjustment applied too, as the original address may or may not
1299 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1300 the adjusted address there.
1302 For relative address adjustments we then use these variables to
1303 calculate the address intended by line information, which will be
1304 PC-relative, and return an updated adjustment carrying ISA bit
1305 information, which will be ADJ_PC-relative. For absolute address
1306 adjustments we just return the same address that we store in ADJ_PC
1309 As the first line entry can be relative to an implied address value
1310 of 0 we need to have the initial address set up that we store in PC
1311 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1312 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1315 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1317 static CORE_ADDR adj_pc
;
1318 static CORE_ADDR pc
;
1321 pc
= rel
? pc
+ addr
: addr
;
1322 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1323 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1328 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1330 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1331 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1332 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1333 static const char mips_str_call_stub
[] = "__call_stub_";
1334 static const char mips_str_fn_stub
[] = "__fn_stub_";
1336 /* This is used as a PIC thunk prefix. */
1338 static const char mips_str_pic
[] = ".pic.";
1340 /* Return non-zero if the PC is inside a call thunk (aka stub or
1341 trampoline) that should be treated as a temporary frame. */
1344 mips_in_frame_stub (CORE_ADDR pc
)
1346 CORE_ADDR start_addr
;
1349 /* Find the starting address of the function containing the PC. */
1350 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1353 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1354 if (startswith (name
, mips_str_mips16_call_stub
))
1356 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1357 if (startswith (name
, mips_str_call_stub
))
1359 /* If the PC is in __fn_stub_*, this is a call stub. */
1360 if (startswith (name
, mips_str_fn_stub
))
1363 return 0; /* Not a stub. */
1366 /* MIPS believes that the PC has a sign extended value. Perhaps the
1367 all registers should be sign extended for simplicity? */
1370 mips_read_pc (struct regcache
*regcache
)
1372 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1375 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1380 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1384 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1385 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1386 intermediate frames. In this case we can get the caller's address
1387 from $ra, or if $ra contains an address within a thunk as well, then
1388 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1389 and thus the caller's address is in $s2. */
1390 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1392 pc
= frame_unwind_register_signed
1393 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1394 if (mips_in_frame_stub (pc
))
1395 pc
= frame_unwind_register_signed
1396 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1402 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1404 return frame_unwind_register_signed
1405 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1408 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1409 dummy frame. The frame ID's base needs to match the TOS value
1410 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1413 static struct frame_id
1414 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1416 return frame_id_build
1417 (get_frame_register_signed (this_frame
,
1418 gdbarch_num_regs (gdbarch
)
1420 get_frame_pc (this_frame
));
1423 /* Implement the "write_pc" gdbarch method. */
1426 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1428 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1430 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1433 /* Fetch and return instruction from the specified location. Handle
1434 MIPS16/microMIPS as appropriate. */
1437 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1438 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1440 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1441 gdb_byte buf
[MIPS_INSN32_SIZE
];
1449 instlen
= MIPS_INSN16_SIZE
;
1450 addr
= unmake_compact_addr (addr
);
1453 instlen
= MIPS_INSN32_SIZE
;
1456 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1459 err
= target_read_memory (addr
, buf
, instlen
);
1465 memory_error (TARGET_XFER_E_IO
, addr
);
1468 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1471 /* These are the fields of 32 bit mips instructions. */
1472 #define mips32_op(x) (x >> 26)
1473 #define itype_op(x) (x >> 26)
1474 #define itype_rs(x) ((x >> 21) & 0x1f)
1475 #define itype_rt(x) ((x >> 16) & 0x1f)
1476 #define itype_immediate(x) (x & 0xffff)
1478 #define jtype_op(x) (x >> 26)
1479 #define jtype_target(x) (x & 0x03ffffff)
1481 #define rtype_op(x) (x >> 26)
1482 #define rtype_rs(x) ((x >> 21) & 0x1f)
1483 #define rtype_rt(x) ((x >> 16) & 0x1f)
1484 #define rtype_rd(x) ((x >> 11) & 0x1f)
1485 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1486 #define rtype_funct(x) (x & 0x3f)
1488 /* MicroMIPS instruction fields. */
1489 #define micromips_op(x) ((x) >> 10)
1491 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1492 bit and the size respectively of the field extracted. */
1493 #define b0s4_imm(x) ((x) & 0xf)
1494 #define b0s5_imm(x) ((x) & 0x1f)
1495 #define b0s5_reg(x) ((x) & 0x1f)
1496 #define b0s7_imm(x) ((x) & 0x7f)
1497 #define b0s10_imm(x) ((x) & 0x3ff)
1498 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1499 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1500 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1501 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1502 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1503 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1504 #define b6s4_op(x) (((x) >> 6) & 0xf)
1505 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1507 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1508 respectively of the field extracted. */
1509 #define b0s6_op(x) ((x) & 0x3f)
1510 #define b0s11_op(x) ((x) & 0x7ff)
1511 #define b0s12_imm(x) ((x) & 0xfff)
1512 #define b0s16_imm(x) ((x) & 0xffff)
1513 #define b0s26_imm(x) ((x) & 0x3ffffff)
1514 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1515 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1516 #define b12s4_op(x) (((x) >> 12) & 0xf)
1518 /* Return the size in bytes of the instruction INSN encoded in the ISA
1522 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1527 if ((micromips_op (insn
) & 0x4) == 0x4
1528 || (micromips_op (insn
) & 0x7) == 0x0)
1529 return 2 * MIPS_INSN16_SIZE
;
1531 return MIPS_INSN16_SIZE
;
1533 if ((insn
& 0xf800) == 0xf000)
1534 return 2 * MIPS_INSN16_SIZE
;
1536 return MIPS_INSN16_SIZE
;
1538 return MIPS_INSN32_SIZE
;
1540 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1544 mips32_relative_offset (ULONGEST inst
)
1546 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1549 /* Determine the address of the next instruction executed after the INST
1550 floating condition branch instruction at PC. COUNT specifies the
1551 number of the floating condition bits tested by the branch. */
1554 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1555 ULONGEST inst
, CORE_ADDR pc
, int count
)
1557 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1558 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1559 int tf
= itype_rt (inst
) & 1;
1560 int mask
= (1 << count
) - 1;
1565 /* No way to handle; it'll most likely trap anyway. */
1568 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1569 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1571 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1572 pc
+= mips32_relative_offset (inst
);
1579 /* Return nonzero if the gdbarch is an Octeon series. */
1582 is_octeon (struct gdbarch
*gdbarch
)
1584 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1586 return (info
->mach
== bfd_mach_mips_octeon
1587 || info
->mach
== bfd_mach_mips_octeonp
1588 || info
->mach
== bfd_mach_mips_octeon2
);
1591 /* Return true if the OP represents the Octeon's BBIT instruction. */
1594 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1596 if (!is_octeon (gdbarch
))
1598 /* BBIT0 is encoded as LWC2: 110 010. */
1599 /* BBIT032 is encoded as LDC2: 110 110. */
1600 /* BBIT1 is encoded as SWC2: 111 010. */
1601 /* BBIT132 is encoded as SDC2: 111 110. */
1602 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1608 /* Determine where to set a single step breakpoint while considering
1609 branch prediction. */
1612 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1614 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1617 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1618 op
= itype_op (inst
);
1619 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1623 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1634 goto greater_branch
;
1639 else if (op
== 17 && itype_rs (inst
) == 8)
1640 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1641 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1642 else if (op
== 17 && itype_rs (inst
) == 9
1643 && (itype_rt (inst
) & 2) == 0)
1644 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1645 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1646 else if (op
== 17 && itype_rs (inst
) == 10
1647 && (itype_rt (inst
) & 2) == 0)
1648 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1649 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1652 /* The new PC will be alternate mode. */
1656 reg
= jtype_target (inst
) << 2;
1657 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1658 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1660 else if (is_octeon_bbit_op (op
, gdbarch
))
1664 branch_if
= op
== 58 || op
== 62;
1665 bit
= itype_rt (inst
);
1667 /* Take into account the *32 instructions. */
1668 if (op
== 54 || op
== 62)
1671 if (((get_frame_register_signed (frame
,
1672 itype_rs (inst
)) >> bit
) & 1)
1674 pc
+= mips32_relative_offset (inst
) + 4;
1676 pc
+= 8; /* After the delay slot. */
1680 pc
+= 4; /* Not a branch, next instruction is easy. */
1683 { /* This gets way messy. */
1685 /* Further subdivide into SPECIAL, REGIMM and other. */
1686 switch (op
& 0x07) /* Extract bits 28,27,26. */
1688 case 0: /* SPECIAL */
1689 op
= rtype_funct (inst
);
1694 /* Set PC to that address. */
1695 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1697 case 12: /* SYSCALL */
1699 struct gdbarch_tdep
*tdep
;
1701 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1702 if (tdep
->syscall_next_pc
!= NULL
)
1703 pc
= tdep
->syscall_next_pc (frame
);
1712 break; /* end SPECIAL */
1713 case 1: /* REGIMM */
1715 op
= itype_rt (inst
); /* branch condition */
1720 case 16: /* BLTZAL */
1721 case 18: /* BLTZALL */
1723 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1724 pc
+= mips32_relative_offset (inst
) + 4;
1726 pc
+= 8; /* after the delay slot */
1730 case 17: /* BGEZAL */
1731 case 19: /* BGEZALL */
1732 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1733 pc
+= mips32_relative_offset (inst
) + 4;
1735 pc
+= 8; /* after the delay slot */
1737 case 0x1c: /* BPOSGE32 */
1738 case 0x1e: /* BPOSGE64 */
1740 if (itype_rs (inst
) == 0)
1742 unsigned int pos
= (op
& 2) ? 64 : 32;
1743 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1746 /* No way to handle; it'll most likely trap anyway. */
1749 if ((get_frame_register_unsigned (frame
,
1750 dspctl
) & 0x7f) >= pos
)
1751 pc
+= mips32_relative_offset (inst
);
1756 /* All of the other instructions in the REGIMM category */
1761 break; /* end REGIMM */
1766 reg
= jtype_target (inst
) << 2;
1767 /* Upper four bits get never changed... */
1768 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1771 case 4: /* BEQ, BEQL */
1773 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1774 get_frame_register_signed (frame
, itype_rt (inst
)))
1775 pc
+= mips32_relative_offset (inst
) + 4;
1779 case 5: /* BNE, BNEL */
1781 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1782 get_frame_register_signed (frame
, itype_rt (inst
)))
1783 pc
+= mips32_relative_offset (inst
) + 4;
1787 case 6: /* BLEZ, BLEZL */
1788 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1789 pc
+= mips32_relative_offset (inst
) + 4;
1795 greater_branch
: /* BGTZ, BGTZL */
1796 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1797 pc
+= mips32_relative_offset (inst
) + 4;
1804 } /* mips32_next_pc */
1806 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1810 micromips_relative_offset7 (ULONGEST insn
)
1812 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1815 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1819 micromips_relative_offset10 (ULONGEST insn
)
1821 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1824 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1828 micromips_relative_offset16 (ULONGEST insn
)
1830 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1833 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1836 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1840 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1841 return mips_insn_size (ISA_MICROMIPS
, insn
);
1844 /* Calculate the address of the next microMIPS instruction to execute
1845 after the INSN coprocessor 1 conditional branch instruction at the
1846 address PC. COUNT denotes the number of coprocessor condition bits
1847 examined by the branch. */
1850 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1851 ULONGEST insn
, CORE_ADDR pc
, int count
)
1853 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1854 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1855 int tf
= b5s5_op (insn
>> 16) & 1;
1856 int mask
= (1 << count
) - 1;
1861 /* No way to handle; it'll most likely trap anyway. */
1864 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1865 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1867 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1868 pc
+= micromips_relative_offset16 (insn
);
1870 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1875 /* Calculate the address of the next microMIPS instruction to execute
1876 after the instruction at the address PC. */
1879 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1881 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1884 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1885 pc
+= MIPS_INSN16_SIZE
;
1886 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1888 /* 32-bit instructions. */
1889 case 2 * MIPS_INSN16_SIZE
:
1891 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1892 pc
+= MIPS_INSN16_SIZE
;
1893 switch (micromips_op (insn
>> 16))
1895 case 0x00: /* POOL32A: bits 000000 */
1896 if (b0s6_op (insn
) == 0x3c
1897 /* POOL32Axf: bits 000000 ... 111100 */
1898 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1899 /* JALR, JALR.HB: 000000 000x111100 111100 */
1900 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1901 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1904 case 0x10: /* POOL32I: bits 010000 */
1905 switch (b5s5_op (insn
>> 16))
1907 case 0x00: /* BLTZ: bits 010000 00000 */
1908 case 0x01: /* BLTZAL: bits 010000 00001 */
1909 case 0x11: /* BLTZALS: bits 010000 10001 */
1910 if (get_frame_register_signed (frame
,
1911 b0s5_reg (insn
>> 16)) < 0)
1912 pc
+= micromips_relative_offset16 (insn
);
1914 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1917 case 0x02: /* BGEZ: bits 010000 00010 */
1918 case 0x03: /* BGEZAL: bits 010000 00011 */
1919 case 0x13: /* BGEZALS: bits 010000 10011 */
1920 if (get_frame_register_signed (frame
,
1921 b0s5_reg (insn
>> 16)) >= 0)
1922 pc
+= micromips_relative_offset16 (insn
);
1924 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1927 case 0x04: /* BLEZ: bits 010000 00100 */
1928 if (get_frame_register_signed (frame
,
1929 b0s5_reg (insn
>> 16)) <= 0)
1930 pc
+= micromips_relative_offset16 (insn
);
1932 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1935 case 0x05: /* BNEZC: bits 010000 00101 */
1936 if (get_frame_register_signed (frame
,
1937 b0s5_reg (insn
>> 16)) != 0)
1938 pc
+= micromips_relative_offset16 (insn
);
1941 case 0x06: /* BGTZ: bits 010000 00110 */
1942 if (get_frame_register_signed (frame
,
1943 b0s5_reg (insn
>> 16)) > 0)
1944 pc
+= micromips_relative_offset16 (insn
);
1946 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1949 case 0x07: /* BEQZC: bits 010000 00111 */
1950 if (get_frame_register_signed (frame
,
1951 b0s5_reg (insn
>> 16)) == 0)
1952 pc
+= micromips_relative_offset16 (insn
);
1955 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1956 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1957 if (((insn
>> 16) & 0x3) == 0x0)
1958 /* BC2F, BC2T: don't know how to handle these. */
1962 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1963 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1965 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1966 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1969 /* No way to handle; it'll most likely trap anyway. */
1972 if ((get_frame_register_unsigned (frame
,
1973 dspctl
) & 0x7f) >= pos
)
1974 pc
+= micromips_relative_offset16 (insn
);
1976 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1980 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1981 /* BC1ANY2F: bits 010000 11100 xxx01 */
1982 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1983 /* BC1ANY2T: bits 010000 11101 xxx01 */
1984 if (((insn
>> 16) & 0x2) == 0x0)
1985 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1986 ((insn
>> 16) & 0x1) + 1);
1989 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1990 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1991 if (((insn
>> 16) & 0x3) == 0x1)
1992 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1997 case 0x1d: /* JALS: bits 011101 */
1998 case 0x35: /* J: bits 110101 */
1999 case 0x3d: /* JAL: bits 111101 */
2000 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2003 case 0x25: /* BEQ: bits 100101 */
2004 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
2005 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
2006 pc
+= micromips_relative_offset16 (insn
);
2008 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2011 case 0x2d: /* BNE: bits 101101 */
2012 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
2013 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
2014 pc
+= micromips_relative_offset16 (insn
);
2016 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2019 case 0x3c: /* JALX: bits 111100 */
2020 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2025 /* 16-bit instructions. */
2026 case MIPS_INSN16_SIZE
:
2027 switch (micromips_op (insn
))
2029 case 0x11: /* POOL16C: bits 010001 */
2030 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2031 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2032 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
2033 else if (b5s5_op (insn
) == 0x18)
2034 /* JRADDIUSP: bits 010001 11000 */
2035 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
2038 case 0x23: /* BEQZ16: bits 100011 */
2040 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2042 if (get_frame_register_signed (frame
, rs
) == 0)
2043 pc
+= micromips_relative_offset7 (insn
);
2045 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2049 case 0x2b: /* BNEZ16: bits 101011 */
2051 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2053 if (get_frame_register_signed (frame
, rs
) != 0)
2054 pc
+= micromips_relative_offset7 (insn
);
2056 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2060 case 0x33: /* B16: bits 110011 */
2061 pc
+= micromips_relative_offset10 (insn
);
2070 /* Decoding the next place to set a breakpoint is irregular for the
2071 mips 16 variant, but fortunately, there fewer instructions. We have
2072 to cope ith extensions for 16 bit instructions and a pair of actual
2073 32 bit instructions. We dont want to set a single step instruction
2074 on the extend instruction either. */
2076 /* Lots of mips16 instruction formats */
2077 /* Predicting jumps requires itype,ritype,i8type
2078 and their extensions extItype,extritype,extI8type. */
2079 enum mips16_inst_fmts
2081 itype
, /* 0 immediate 5,10 */
2082 ritype
, /* 1 5,3,8 */
2083 rrtype
, /* 2 5,3,3,5 */
2084 rritype
, /* 3 5,3,3,5 */
2085 rrrtype
, /* 4 5,3,3,3,2 */
2086 rriatype
, /* 5 5,3,3,1,4 */
2087 shifttype
, /* 6 5,3,3,3,2 */
2088 i8type
, /* 7 5,3,8 */
2089 i8movtype
, /* 8 5,3,3,5 */
2090 i8mov32rtype
, /* 9 5,3,5,3 */
2091 i64type
, /* 10 5,3,8 */
2092 ri64type
, /* 11 5,3,3,5 */
2093 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2094 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2095 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2096 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2097 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2098 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2099 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2100 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2101 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2102 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2104 /* I am heaping all the fields of the formats into one structure and
2105 then, only the fields which are involved in instruction extension. */
2109 unsigned int regx
; /* Function in i8 type. */
2114 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2115 for the bits which make up the immediate extension. */
2118 extended_offset (unsigned int extension
)
2122 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2124 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2126 value
|= extension
& 0x1f; /* Extract 4:0. */
2131 /* Only call this function if you know that this is an extendable
2132 instruction. It won't malfunction, but why make excess remote memory
2133 references? If the immediate operands get sign extended or something,
2134 do it after the extension is performed. */
2135 /* FIXME: Every one of these cases needs to worry about sign extension
2136 when the offset is to be used in relative addressing. */
2139 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2141 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2144 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2145 target_read_memory (pc
, buf
, 2);
2146 return extract_unsigned_integer (buf
, 2, byte_order
);
2150 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2151 unsigned int extension
,
2153 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2158 switch (insn_format
)
2165 value
= extended_offset ((extension
<< 16) | inst
);
2166 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2170 value
= inst
& 0x7ff;
2171 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2180 { /* A register identifier and an offset. */
2181 /* Most of the fields are the same as I type but the
2182 immediate value is of a different length. */
2186 value
= extended_offset ((extension
<< 16) | inst
);
2187 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2191 value
= inst
& 0xff; /* 8 bits */
2192 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2195 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2201 unsigned long value
;
2202 unsigned int nexthalf
;
2203 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2204 value
= value
<< 16;
2205 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2206 /* Low bit still set. */
2214 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2216 upk
->offset
= offset
;
2222 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2223 and having a signed 16-bit OFFSET. */
2226 add_offset_16 (CORE_ADDR pc
, int offset
)
2228 return pc
+ (offset
<< 1) + 2;
2232 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2233 unsigned int extension
, unsigned int insn
)
2235 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2236 int op
= (insn
>> 11);
2239 case 2: /* Branch */
2241 struct upk_mips16 upk
;
2242 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2243 pc
= add_offset_16 (pc
, upk
.offset
);
2246 case 3: /* JAL , JALX - Watch out, these are 32 bit
2249 struct upk_mips16 upk
;
2250 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2251 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2252 if ((insn
>> 10) & 0x01) /* Exchange mode */
2253 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2260 struct upk_mips16 upk
;
2262 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2263 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2265 pc
= add_offset_16 (pc
, upk
.offset
);
2272 struct upk_mips16 upk
;
2274 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2275 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2277 pc
= add_offset_16 (pc
, upk
.offset
);
2282 case 12: /* I8 Formats btez btnez */
2284 struct upk_mips16 upk
;
2286 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2287 /* upk.regx contains the opcode */
2288 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2289 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2290 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2291 pc
= add_offset_16 (pc
, upk
.offset
);
2296 case 29: /* RR Formats JR, JALR, JALR-RA */
2298 struct upk_mips16 upk
;
2299 /* upk.fmt = rrtype; */
2304 upk
.regx
= (insn
>> 8) & 0x07;
2305 upk
.regy
= (insn
>> 5) & 0x07;
2306 if ((upk
.regy
& 1) == 0)
2307 reg
= mips_reg3_to_reg
[upk
.regx
];
2309 reg
= 31; /* Function return instruction. */
2310 pc
= get_frame_register_signed (frame
, reg
);
2317 /* This is an instruction extension. Fetch the real instruction
2318 (which follows the extension) and decode things based on
2322 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2323 fetch_mips_16 (gdbarch
, pc
));
2336 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2338 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2339 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2340 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2343 /* The mips_next_pc function supports single_step when the remote
2344 target monitor or stub is not developed enough to do a single_step.
2345 It works by decoding the current instruction and predicting where a
2346 branch will go. This isn't hard because all the data is available.
2347 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2349 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2351 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2353 if (mips_pc_is_mips16 (gdbarch
, pc
))
2354 return mips16_next_pc (frame
, pc
);
2355 else if (mips_pc_is_micromips (gdbarch
, pc
))
2356 return micromips_next_pc (frame
, pc
);
2358 return mips32_next_pc (frame
, pc
);
2361 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2365 mips16_instruction_is_compact_branch (unsigned short insn
)
2367 switch (insn
& 0xf800)
2370 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2372 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2373 case 0x2800: /* BNEZ */
2374 case 0x2000: /* BEQZ */
2375 case 0x1000: /* B */
2382 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2386 micromips_instruction_is_compact_branch (unsigned short insn
)
2388 switch (micromips_op (insn
))
2390 case 0x11: /* POOL16C: bits 010001 */
2391 return (b5s5_op (insn
) == 0x18
2392 /* JRADDIUSP: bits 010001 11000 */
2393 || b5s5_op (insn
) == 0xd);
2394 /* JRC: bits 010011 01101 */
2395 case 0x10: /* POOL32I: bits 010000 */
2396 return (b5s5_op (insn
) & 0x1d) == 0x5;
2397 /* BEQZC/BNEZC: bits 010000 001x1 */
2403 struct mips_frame_cache
2406 struct trad_frame_saved_reg
*saved_regs
;
2409 /* Set a register's saved stack address in temp_saved_regs. If an
2410 address has already been set for this register, do nothing; this
2411 way we will only recognize the first save of a given register in a
2414 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2415 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2416 Strictly speaking, only the second range is used as it is only second
2417 range (the ABI instead of ISA registers) that comes into play when finding
2418 saved registers in a frame. */
2421 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2422 int regnum
, CORE_ADDR offset
)
2424 if (this_cache
!= NULL
2425 && this_cache
->saved_regs
[regnum
].addr
== -1)
2427 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2429 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2435 /* Fetch the immediate value from a MIPS16 instruction.
2436 If the previous instruction was an EXTEND, use it to extend
2437 the upper bits of the immediate value. This is a helper function
2438 for mips16_scan_prologue. */
2441 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2442 unsigned short inst
, /* current instruction */
2443 int nbits
, /* number of bits in imm field */
2444 int scale
, /* scale factor to be applied to imm */
2445 int is_signed
) /* is the imm field signed? */
2449 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2451 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2452 if (offset
& 0x8000) /* check for negative extend */
2453 offset
= 0 - (0x10000 - (offset
& 0xffff));
2454 return offset
| (inst
& 0x1f);
2458 int max_imm
= 1 << nbits
;
2459 int mask
= max_imm
- 1;
2460 int sign_bit
= max_imm
>> 1;
2462 offset
= inst
& mask
;
2463 if (is_signed
&& (offset
& sign_bit
))
2464 offset
= 0 - (max_imm
- offset
);
2465 return offset
* scale
;
2470 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2471 the associated FRAME_CACHE if not null.
2472 Return the address of the first instruction past the prologue. */
2475 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2476 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2477 struct frame_info
*this_frame
,
2478 struct mips_frame_cache
*this_cache
)
2480 int prev_non_prologue_insn
= 0;
2481 int this_non_prologue_insn
;
2482 int non_prologue_insns
= 0;
2485 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2487 long frame_offset
= 0; /* Size of stack frame. */
2488 long frame_adjust
= 0; /* Offset of FP from SP. */
2489 int frame_reg
= MIPS_SP_REGNUM
;
2490 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2491 unsigned inst
= 0; /* current instruction */
2492 unsigned entry_inst
= 0; /* the entry instruction */
2493 unsigned save_inst
= 0; /* the save instruction */
2494 int prev_delay_slot
= 0;
2498 int extend_bytes
= 0;
2499 int prev_extend_bytes
= 0;
2500 CORE_ADDR end_prologue_addr
;
2502 /* Can be called when there's no process, and hence when there's no
2504 if (this_frame
!= NULL
)
2505 sp
= get_frame_register_signed (this_frame
,
2506 gdbarch_num_regs (gdbarch
)
2511 if (limit_pc
> start_pc
+ 200)
2512 limit_pc
= start_pc
+ 200;
2515 /* Permit at most one non-prologue non-control-transfer instruction
2516 in the middle which may have been reordered by the compiler for
2518 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2520 this_non_prologue_insn
= 0;
2523 /* Save the previous instruction. If it's an EXTEND, we'll extract
2524 the immediate offset extension from it in mips16_get_imm. */
2527 /* Fetch and decode the instruction. */
2528 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2531 /* Normally we ignore extend instructions. However, if it is
2532 not followed by a valid prologue instruction, then this
2533 instruction is not part of the prologue either. We must
2534 remember in this case to adjust the end_prologue_addr back
2536 if ((inst
& 0xf800) == 0xf000) /* extend */
2538 extend_bytes
= MIPS_INSN16_SIZE
;
2542 prev_extend_bytes
= extend_bytes
;
2545 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2546 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2548 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2549 if (offset
< 0) /* Negative stack adjustment? */
2550 frame_offset
-= offset
;
2552 /* Exit loop if a positive stack adjustment is found, which
2553 usually means that the stack cleanup code in the function
2554 epilogue is reached. */
2557 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2559 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2560 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2561 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2563 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2565 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2566 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2567 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2569 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2571 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2572 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2574 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2576 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2577 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2579 else if (inst
== 0x673d) /* move $s1, $sp */
2584 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2586 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2587 frame_addr
= sp
+ offset
;
2589 frame_adjust
= offset
;
2591 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2593 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2594 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2595 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2597 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2599 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2600 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2601 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2603 else if ((inst
& 0xf81f) == 0xe809
2604 && (inst
& 0x700) != 0x700) /* entry */
2605 entry_inst
= inst
; /* Save for later processing. */
2606 else if ((inst
& 0xff80) == 0x6480) /* save */
2608 save_inst
= inst
; /* Save for later processing. */
2609 if (prev_extend_bytes
) /* extend */
2610 save_inst
|= prev_inst
<< 16;
2612 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2614 /* This instruction is part of the prologue, but we don't
2615 need to do anything special to handle it. */
2617 else if (mips16_instruction_has_delay_slot (inst
, 0))
2618 /* JAL/JALR/JALX/JR */
2620 /* The instruction in the delay slot can be a part
2621 of the prologue, so move forward once more. */
2623 if (mips16_instruction_has_delay_slot (inst
, 1))
2626 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2627 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2632 this_non_prologue_insn
= 1;
2635 non_prologue_insns
+= this_non_prologue_insn
;
2637 /* A jump or branch, or enough non-prologue insns seen? If so,
2638 then we must have reached the end of the prologue by now. */
2639 if (prev_delay_slot
|| non_prologue_insns
> 1
2640 || mips16_instruction_is_compact_branch (inst
))
2643 prev_non_prologue_insn
= this_non_prologue_insn
;
2644 prev_delay_slot
= in_delay_slot
;
2645 prev_pc
= cur_pc
- prev_extend_bytes
;
2648 /* The entry instruction is typically the first instruction in a function,
2649 and it stores registers at offsets relative to the value of the old SP
2650 (before the prologue). But the value of the sp parameter to this
2651 function is the new SP (after the prologue has been executed). So we
2652 can't calculate those offsets until we've seen the entire prologue,
2653 and can calculate what the old SP must have been. */
2654 if (entry_inst
!= 0)
2656 int areg_count
= (entry_inst
>> 8) & 7;
2657 int sreg_count
= (entry_inst
>> 6) & 3;
2659 /* The entry instruction always subtracts 32 from the SP. */
2662 /* Now we can calculate what the SP must have been at the
2663 start of the function prologue. */
2666 /* Check if a0-a3 were saved in the caller's argument save area. */
2667 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2669 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2670 offset
+= mips_abi_regsize (gdbarch
);
2673 /* Check if the ra register was pushed on the stack. */
2675 if (entry_inst
& 0x20)
2677 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2678 offset
-= mips_abi_regsize (gdbarch
);
2681 /* Check if the s0 and s1 registers were pushed on the stack. */
2682 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2684 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2685 offset
-= mips_abi_regsize (gdbarch
);
2689 /* The SAVE instruction is similar to ENTRY, except that defined by the
2690 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2691 size of the frame is specified as an immediate field of instruction
2692 and an extended variation exists which lets additional registers and
2693 frame space to be specified. The instruction always treats registers
2694 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2695 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2697 static int args_table
[16] = {
2698 0, 0, 0, 0, 1, 1, 1, 1,
2699 2, 2, 2, 0, 3, 3, 4, -1,
2701 static int astatic_table
[16] = {
2702 0, 1, 2, 3, 0, 1, 2, 3,
2703 0, 1, 2, 4, 0, 1, 0, -1,
2705 int aregs
= (save_inst
>> 16) & 0xf;
2706 int xsregs
= (save_inst
>> 24) & 0x7;
2707 int args
= args_table
[aregs
];
2708 int astatic
= astatic_table
[aregs
];
2713 warning (_("Invalid number of argument registers encoded in SAVE."));
2718 warning (_("Invalid number of static registers encoded in SAVE."));
2722 /* For standard SAVE the frame size of 0 means 128. */
2723 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2724 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2727 frame_offset
+= frame_size
;
2729 /* Now we can calculate what the SP must have been at the
2730 start of the function prologue. */
2733 /* Check if A0-A3 were saved in the caller's argument save area. */
2734 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2736 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2737 offset
+= mips_abi_regsize (gdbarch
);
2742 /* Check if the RA register was pushed on the stack. */
2743 if (save_inst
& 0x40)
2745 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2746 offset
-= mips_abi_regsize (gdbarch
);
2749 /* Check if the S8 register was pushed on the stack. */
2752 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2753 offset
-= mips_abi_regsize (gdbarch
);
2756 /* Check if S2-S7 were pushed on the stack. */
2757 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2759 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2760 offset
-= mips_abi_regsize (gdbarch
);
2763 /* Check if the S1 register was pushed on the stack. */
2764 if (save_inst
& 0x10)
2766 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2767 offset
-= mips_abi_regsize (gdbarch
);
2769 /* Check if the S0 register was pushed on the stack. */
2770 if (save_inst
& 0x20)
2772 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2773 offset
-= mips_abi_regsize (gdbarch
);
2776 /* Check if A0-A3 were pushed on the stack. */
2777 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2779 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2780 offset
-= mips_abi_regsize (gdbarch
);
2784 if (this_cache
!= NULL
)
2787 (get_frame_register_signed (this_frame
,
2788 gdbarch_num_regs (gdbarch
) + frame_reg
)
2789 + frame_offset
- frame_adjust
);
2790 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2791 be able to get rid of the assignment below, evetually. But it's
2792 still needed for now. */
2793 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2794 + mips_regnum (gdbarch
)->pc
]
2795 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2798 /* Set end_prologue_addr to the address of the instruction immediately
2799 after the last one we scanned. Unless the last one looked like a
2800 non-prologue instruction (and we looked ahead), in which case use
2801 its address instead. */
2802 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2803 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2805 return end_prologue_addr
;
2808 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2809 Procedures that use the 32-bit instruction set are handled by the
2810 mips_insn32 unwinder. */
2812 static struct mips_frame_cache
*
2813 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2815 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2816 struct mips_frame_cache
*cache
;
2818 if ((*this_cache
) != NULL
)
2819 return (struct mips_frame_cache
*) (*this_cache
);
2820 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2821 (*this_cache
) = cache
;
2822 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2824 /* Analyze the function prologue. */
2826 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2827 CORE_ADDR start_addr
;
2829 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2830 if (start_addr
== 0)
2831 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2832 /* We can't analyze the prologue if we couldn't find the begining
2834 if (start_addr
== 0)
2837 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2838 (struct mips_frame_cache
*) *this_cache
);
2841 /* gdbarch_sp_regnum contains the value and not the address. */
2842 trad_frame_set_value (cache
->saved_regs
,
2843 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2846 return (struct mips_frame_cache
*) (*this_cache
);
2850 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2851 struct frame_id
*this_id
)
2853 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2855 /* This marks the outermost frame. */
2856 if (info
->base
== 0)
2858 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2861 static struct value
*
2862 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2863 void **this_cache
, int regnum
)
2865 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2867 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2871 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2872 struct frame_info
*this_frame
, void **this_cache
)
2874 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2875 CORE_ADDR pc
= get_frame_pc (this_frame
);
2876 if (mips_pc_is_mips16 (gdbarch
, pc
))
2881 static const struct frame_unwind mips_insn16_frame_unwind
=
2884 default_frame_unwind_stop_reason
,
2885 mips_insn16_frame_this_id
,
2886 mips_insn16_frame_prev_register
,
2888 mips_insn16_frame_sniffer
2892 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2895 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2900 static const struct frame_base mips_insn16_frame_base
=
2902 &mips_insn16_frame_unwind
,
2903 mips_insn16_frame_base_address
,
2904 mips_insn16_frame_base_address
,
2905 mips_insn16_frame_base_address
2908 static const struct frame_base
*
2909 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2911 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2912 CORE_ADDR pc
= get_frame_pc (this_frame
);
2913 if (mips_pc_is_mips16 (gdbarch
, pc
))
2914 return &mips_insn16_frame_base
;
2919 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2920 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2921 interpreted directly, and then multiplied by 4. */
2924 micromips_decode_imm9 (int imm
)
2926 imm
= (imm
^ 0x100) - 0x100;
2927 if (imm
> -3 && imm
< 2)
2932 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2933 the address of the first instruction past the prologue. */
2936 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2937 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2938 struct frame_info
*this_frame
,
2939 struct mips_frame_cache
*this_cache
)
2941 CORE_ADDR end_prologue_addr
;
2942 int prev_non_prologue_insn
= 0;
2943 int frame_reg
= MIPS_SP_REGNUM
;
2944 int this_non_prologue_insn
;
2945 int non_prologue_insns
= 0;
2946 long frame_offset
= 0; /* Size of stack frame. */
2947 long frame_adjust
= 0; /* Offset of FP from SP. */
2948 int prev_delay_slot
= 0;
2952 ULONGEST insn
; /* current instruction */
2956 long v1_off
= 0; /* The assumption is LUI will replace it. */
2967 /* Can be called when there's no process, and hence when there's no
2969 if (this_frame
!= NULL
)
2970 sp
= get_frame_register_signed (this_frame
,
2971 gdbarch_num_regs (gdbarch
)
2976 if (limit_pc
> start_pc
+ 200)
2977 limit_pc
= start_pc
+ 200;
2980 /* Permit at most one non-prologue non-control-transfer instruction
2981 in the middle which may have been reordered by the compiler for
2983 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2985 this_non_prologue_insn
= 0;
2989 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2990 loc
+= MIPS_INSN16_SIZE
;
2991 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2993 /* 32-bit instructions. */
2994 case 2 * MIPS_INSN16_SIZE
:
2996 insn
|= mips_fetch_instruction (gdbarch
,
2997 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2998 loc
+= MIPS_INSN16_SIZE
;
2999 switch (micromips_op (insn
>> 16))
3001 /* Record $sp/$fp adjustment. */
3002 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3003 case 0x0: /* POOL32A: bits 000000 */
3004 case 0x16: /* POOL32S: bits 010110 */
3005 op
= b0s11_op (insn
);
3006 sreg
= b0s5_reg (insn
>> 16);
3007 treg
= b5s5_reg (insn
>> 16);
3008 dreg
= b11s5_reg (insn
);
3010 /* SUBU: bits 000000 00111010000 */
3011 /* DSUBU: bits 010110 00111010000 */
3012 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3014 /* (D)SUBU $sp, $v1 */
3016 else if (op
!= 0x150
3017 /* ADDU: bits 000000 00101010000 */
3018 /* DADDU: bits 010110 00101010000 */
3019 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3020 this_non_prologue_insn
= 1;
3023 case 0x8: /* POOL32B: bits 001000 */
3024 op
= b12s4_op (insn
);
3025 breg
= b0s5_reg (insn
>> 16);
3026 reglist
= sreg
= b5s5_reg (insn
>> 16);
3027 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3028 if ((op
== 0x9 || op
== 0xc)
3029 /* SWP: bits 001000 1001 */
3030 /* SDP: bits 001000 1100 */
3031 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3032 /* S[DW]P reg,offset($sp) */
3034 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3035 set_reg_offset (gdbarch
, this_cache
,
3037 set_reg_offset (gdbarch
, this_cache
,
3038 sreg
+ 1, sp
+ offset
+ s
);
3040 else if ((op
== 0xd || op
== 0xf)
3041 /* SWM: bits 001000 1101 */
3042 /* SDM: bits 001000 1111 */
3043 && breg
== MIPS_SP_REGNUM
3044 /* SWM reglist,offset($sp) */
3045 && ((reglist
>= 1 && reglist
<= 9)
3046 || (reglist
>= 16 && reglist
<= 25)))
3048 int sreglist
= std::min(reglist
& 0xf, 8);
3050 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3051 for (i
= 0; i
< sreglist
; i
++)
3052 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3053 if ((reglist
& 0xf) > 8)
3054 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3055 if ((reglist
& 0x10) == 0x10)
3056 set_reg_offset (gdbarch
, this_cache
,
3057 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3060 this_non_prologue_insn
= 1;
3063 /* Record $sp/$fp adjustment. */
3064 /* Discard (D)ADDIU $gp used for PIC code. */
3065 case 0xc: /* ADDIU: bits 001100 */
3066 case 0x17: /* DADDIU: bits 010111 */
3067 sreg
= b0s5_reg (insn
>> 16);
3068 dreg
= b5s5_reg (insn
>> 16);
3069 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3070 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3071 /* (D)ADDIU $sp, imm */
3073 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3074 /* (D)ADDIU $fp, $sp, imm */
3076 frame_adjust
= offset
;
3079 else if (sreg
!= 28 || dreg
!= 28)
3080 /* (D)ADDIU $gp, imm */
3081 this_non_prologue_insn
= 1;
3084 /* LUI $v1 is used for larger $sp adjustments. */
3085 /* Discard LUI $gp used for PIC code. */
3086 case 0x10: /* POOL32I: bits 010000 */
3087 if (b5s5_op (insn
>> 16) == 0xd
3088 /* LUI: bits 010000 001101 */
3089 && b0s5_reg (insn
>> 16) == 3)
3091 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3092 else if (b5s5_op (insn
>> 16) != 0xd
3093 /* LUI: bits 010000 001101 */
3094 || b0s5_reg (insn
>> 16) != 28)
3096 this_non_prologue_insn
= 1;
3099 /* ORI $v1 is used for larger $sp adjustments. */
3100 case 0x14: /* ORI: bits 010100 */
3101 sreg
= b0s5_reg (insn
>> 16);
3102 dreg
= b5s5_reg (insn
>> 16);
3103 if (sreg
== 3 && dreg
== 3)
3105 v1_off
|= b0s16_imm (insn
);
3107 this_non_prologue_insn
= 1;
3110 case 0x26: /* SWC1: bits 100110 */
3111 case 0x2e: /* SDC1: bits 101110 */
3112 breg
= b0s5_reg (insn
>> 16);
3113 if (breg
!= MIPS_SP_REGNUM
)
3114 /* S[DW]C1 reg,offset($sp) */
3115 this_non_prologue_insn
= 1;
3118 case 0x36: /* SD: bits 110110 */
3119 case 0x3e: /* SW: bits 111110 */
3120 breg
= b0s5_reg (insn
>> 16);
3121 sreg
= b5s5_reg (insn
>> 16);
3122 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3123 if (breg
== MIPS_SP_REGNUM
)
3124 /* S[DW] reg,offset($sp) */
3125 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3127 this_non_prologue_insn
= 1;
3131 /* The instruction in the delay slot can be a part
3132 of the prologue, so move forward once more. */
3133 if (micromips_instruction_has_delay_slot (insn
, 0))
3136 this_non_prologue_insn
= 1;
3142 /* 16-bit instructions. */
3143 case MIPS_INSN16_SIZE
:
3144 switch (micromips_op (insn
))
3146 case 0x3: /* MOVE: bits 000011 */
3147 sreg
= b0s5_reg (insn
);
3148 dreg
= b5s5_reg (insn
);
3149 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3152 else if ((sreg
& 0x1c) != 0x4)
3153 /* MOVE reg, $a0-$a3 */
3154 this_non_prologue_insn
= 1;
3157 case 0x11: /* POOL16C: bits 010001 */
3158 if (b6s4_op (insn
) == 0x5)
3159 /* SWM: bits 010001 0101 */
3161 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3162 reglist
= b4s2_regl (insn
);
3163 for (i
= 0; i
<= reglist
; i
++)
3164 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3165 set_reg_offset (gdbarch
, this_cache
,
3166 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3169 this_non_prologue_insn
= 1;
3172 case 0x13: /* POOL16D: bits 010011 */
3173 if ((insn
& 0x1) == 0x1)
3174 /* ADDIUSP: bits 010011 1 */
3175 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3176 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3177 /* ADDIUS5: bits 010011 0 */
3178 /* ADDIUS5 $sp, imm */
3179 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3181 this_non_prologue_insn
= 1;
3184 case 0x32: /* SWSP: bits 110010 */
3185 offset
= b0s5_imm (insn
) << 2;
3186 sreg
= b5s5_reg (insn
);
3187 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3191 /* The instruction in the delay slot can be a part
3192 of the prologue, so move forward once more. */
3193 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3196 this_non_prologue_insn
= 1;
3202 frame_offset
-= sp_adj
;
3204 non_prologue_insns
+= this_non_prologue_insn
;
3206 /* A jump or branch, enough non-prologue insns seen or positive
3207 stack adjustment? If so, then we must have reached the end
3208 of the prologue by now. */
3209 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3210 || micromips_instruction_is_compact_branch (insn
))
3213 prev_non_prologue_insn
= this_non_prologue_insn
;
3214 prev_delay_slot
= in_delay_slot
;
3218 if (this_cache
!= NULL
)
3221 (get_frame_register_signed (this_frame
,
3222 gdbarch_num_regs (gdbarch
) + frame_reg
)
3223 + frame_offset
- frame_adjust
);
3224 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3225 be able to get rid of the assignment below, evetually. But it's
3226 still needed for now. */
3227 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3228 + mips_regnum (gdbarch
)->pc
]
3229 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3232 /* Set end_prologue_addr to the address of the instruction immediately
3233 after the last one we scanned. Unless the last one looked like a
3234 non-prologue instruction (and we looked ahead), in which case use
3235 its address instead. */
3237 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3239 return end_prologue_addr
;
3242 /* Heuristic unwinder for procedures using microMIPS instructions.
3243 Procedures that use the 32-bit instruction set are handled by the
3244 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3246 static struct mips_frame_cache
*
3247 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3249 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3250 struct mips_frame_cache
*cache
;
3252 if ((*this_cache
) != NULL
)
3253 return (struct mips_frame_cache
*) (*this_cache
);
3255 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3256 (*this_cache
) = cache
;
3257 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3259 /* Analyze the function prologue. */
3261 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3262 CORE_ADDR start_addr
;
3264 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3265 if (start_addr
== 0)
3266 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3267 /* We can't analyze the prologue if we couldn't find the begining
3269 if (start_addr
== 0)
3272 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3273 (struct mips_frame_cache
*) *this_cache
);
3276 /* gdbarch_sp_regnum contains the value and not the address. */
3277 trad_frame_set_value (cache
->saved_regs
,
3278 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3281 return (struct mips_frame_cache
*) (*this_cache
);
3285 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3286 struct frame_id
*this_id
)
3288 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3290 /* This marks the outermost frame. */
3291 if (info
->base
== 0)
3293 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3296 static struct value
*
3297 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3298 void **this_cache
, int regnum
)
3300 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3302 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3306 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3307 struct frame_info
*this_frame
, void **this_cache
)
3309 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3310 CORE_ADDR pc
= get_frame_pc (this_frame
);
3312 if (mips_pc_is_micromips (gdbarch
, pc
))
3317 static const struct frame_unwind mips_micro_frame_unwind
=
3320 default_frame_unwind_stop_reason
,
3321 mips_micro_frame_this_id
,
3322 mips_micro_frame_prev_register
,
3324 mips_micro_frame_sniffer
3328 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3331 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3336 static const struct frame_base mips_micro_frame_base
=
3338 &mips_micro_frame_unwind
,
3339 mips_micro_frame_base_address
,
3340 mips_micro_frame_base_address
,
3341 mips_micro_frame_base_address
3344 static const struct frame_base
*
3345 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3347 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3348 CORE_ADDR pc
= get_frame_pc (this_frame
);
3350 if (mips_pc_is_micromips (gdbarch
, pc
))
3351 return &mips_micro_frame_base
;
3356 /* Mark all the registers as unset in the saved_regs array
3357 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3360 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3362 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3366 const int num_regs
= gdbarch_num_regs (gdbarch
);
3369 for (i
= 0; i
< num_regs
; i
++)
3371 this_cache
->saved_regs
[i
].addr
= -1;
3376 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3377 the associated FRAME_CACHE if not null.
3378 Return the address of the first instruction past the prologue. */
3381 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3382 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3383 struct frame_info
*this_frame
,
3384 struct mips_frame_cache
*this_cache
)
3386 int prev_non_prologue_insn
;
3387 int this_non_prologue_insn
;
3388 int non_prologue_insns
;
3389 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3391 int prev_delay_slot
;
3396 int frame_reg
= MIPS_SP_REGNUM
;
3398 CORE_ADDR end_prologue_addr
;
3399 int seen_sp_adjust
= 0;
3400 int load_immediate_bytes
= 0;
3402 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3404 /* Can be called when there's no process, and hence when there's no
3406 if (this_frame
!= NULL
)
3407 sp
= get_frame_register_signed (this_frame
,
3408 gdbarch_num_regs (gdbarch
)
3413 if (limit_pc
> start_pc
+ 200)
3414 limit_pc
= start_pc
+ 200;
3417 prev_non_prologue_insn
= 0;
3418 non_prologue_insns
= 0;
3419 prev_delay_slot
= 0;
3422 /* Permit at most one non-prologue non-control-transfer instruction
3423 in the middle which may have been reordered by the compiler for
3426 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3428 unsigned long inst
, high_word
;
3432 this_non_prologue_insn
= 0;
3435 /* Fetch the instruction. */
3436 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3439 /* Save some code by pre-extracting some useful fields. */
3440 high_word
= (inst
>> 16) & 0xffff;
3441 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3442 reg
= high_word
& 0x1f;
3444 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3445 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3446 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3448 if (offset
< 0) /* Negative stack adjustment? */
3449 frame_offset
-= offset
;
3451 /* Exit loop if a positive stack adjustment is found, which
3452 usually means that the stack cleanup code in the function
3453 epilogue is reached. */
3457 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3458 && !regsize_is_64_bits
)
3460 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3462 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3463 && regsize_is_64_bits
)
3465 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3466 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3468 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3470 /* Old gcc frame, r30 is virtual frame pointer. */
3471 if (offset
!= frame_offset
)
3472 frame_addr
= sp
+ offset
;
3473 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3475 unsigned alloca_adjust
;
3478 frame_addr
= get_frame_register_signed
3479 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3482 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3483 if (alloca_adjust
> 0)
3485 /* FP > SP + frame_size. This may be because of
3486 an alloca or somethings similar. Fix sp to
3487 "pre-alloca" value, and try again. */
3488 sp
+= alloca_adjust
;
3489 /* Need to reset the status of all registers. Otherwise,
3490 we will hit a guard that prevents the new address
3491 for each register to be recomputed during the second
3493 reset_saved_regs (gdbarch
, this_cache
);
3498 /* move $30,$sp. With different versions of gas this will be either
3499 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3500 Accept any one of these. */
3501 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3503 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3504 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3506 unsigned alloca_adjust
;
3509 frame_addr
= get_frame_register_signed
3510 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3512 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3513 if (alloca_adjust
> 0)
3515 /* FP > SP + frame_size. This may be because of
3516 an alloca or somethings similar. Fix sp to
3517 "pre-alloca" value, and try again. */
3519 /* Need to reset the status of all registers. Otherwise,
3520 we will hit a guard that prevents the new address
3521 for each register to be recomputed during the second
3523 reset_saved_regs (gdbarch
, this_cache
);
3528 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3529 && !regsize_is_64_bits
)
3531 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3533 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3534 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3535 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3536 || high_word
== 0x3c1c /* lui $gp,n */
3537 || high_word
== 0x279c /* addiu $gp,$gp,n */
3538 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3539 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3542 /* These instructions are part of the prologue, but we don't
3543 need to do anything special to handle them. */
3545 /* The instructions below load $at or $t0 with an immediate
3546 value in preparation for a stack adjustment via
3547 subu $sp,$sp,[$at,$t0]. These instructions could also
3548 initialize a local variable, so we accept them only before
3549 a stack adjustment instruction was seen. */
3550 else if (!seen_sp_adjust
3552 && (high_word
== 0x3c01 /* lui $at,n */
3553 || high_word
== 0x3c08 /* lui $t0,n */
3554 || high_word
== 0x3421 /* ori $at,$at,n */
3555 || high_word
== 0x3508 /* ori $t0,$t0,n */
3556 || high_word
== 0x3401 /* ori $at,$zero,n */
3557 || high_word
== 0x3408 /* ori $t0,$zero,n */
3560 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3562 /* Check for branches and jumps. The instruction in the delay
3563 slot can be a part of the prologue, so move forward once more. */
3564 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3568 /* This instruction is not an instruction typically found
3569 in a prologue, so we must have reached the end of the
3573 this_non_prologue_insn
= 1;
3576 non_prologue_insns
+= this_non_prologue_insn
;
3578 /* A jump or branch, or enough non-prologue insns seen? If so,
3579 then we must have reached the end of the prologue by now. */
3580 if (prev_delay_slot
|| non_prologue_insns
> 1)
3583 prev_non_prologue_insn
= this_non_prologue_insn
;
3584 prev_delay_slot
= in_delay_slot
;
3588 if (this_cache
!= NULL
)
3591 (get_frame_register_signed (this_frame
,
3592 gdbarch_num_regs (gdbarch
) + frame_reg
)
3594 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3595 this assignment below, eventually. But it's still needed
3597 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3598 + mips_regnum (gdbarch
)->pc
]
3599 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3603 /* Set end_prologue_addr to the address of the instruction immediately
3604 after the last one we scanned. Unless the last one looked like a
3605 non-prologue instruction (and we looked ahead), in which case use
3606 its address instead. */
3608 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3610 /* In a frameless function, we might have incorrectly
3611 skipped some load immediate instructions. Undo the skipping
3612 if the load immediate was not followed by a stack adjustment. */
3613 if (load_immediate_bytes
&& !seen_sp_adjust
)
3614 end_prologue_addr
-= load_immediate_bytes
;
3616 return end_prologue_addr
;
3619 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3620 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3621 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3622 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3624 static struct mips_frame_cache
*
3625 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3627 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3628 struct mips_frame_cache
*cache
;
3630 if ((*this_cache
) != NULL
)
3631 return (struct mips_frame_cache
*) (*this_cache
);
3633 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3634 (*this_cache
) = cache
;
3635 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3637 /* Analyze the function prologue. */
3639 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3640 CORE_ADDR start_addr
;
3642 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3643 if (start_addr
== 0)
3644 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3645 /* We can't analyze the prologue if we couldn't find the begining
3647 if (start_addr
== 0)
3650 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3651 (struct mips_frame_cache
*) *this_cache
);
3654 /* gdbarch_sp_regnum contains the value and not the address. */
3655 trad_frame_set_value (cache
->saved_regs
,
3656 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3659 return (struct mips_frame_cache
*) (*this_cache
);
3663 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3664 struct frame_id
*this_id
)
3666 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3668 /* This marks the outermost frame. */
3669 if (info
->base
== 0)
3671 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3674 static struct value
*
3675 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3676 void **this_cache
, int regnum
)
3678 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3680 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3684 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3685 struct frame_info
*this_frame
, void **this_cache
)
3687 CORE_ADDR pc
= get_frame_pc (this_frame
);
3688 if (mips_pc_is_mips (pc
))
3693 static const struct frame_unwind mips_insn32_frame_unwind
=
3696 default_frame_unwind_stop_reason
,
3697 mips_insn32_frame_this_id
,
3698 mips_insn32_frame_prev_register
,
3700 mips_insn32_frame_sniffer
3704 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3707 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3712 static const struct frame_base mips_insn32_frame_base
=
3714 &mips_insn32_frame_unwind
,
3715 mips_insn32_frame_base_address
,
3716 mips_insn32_frame_base_address
,
3717 mips_insn32_frame_base_address
3720 static const struct frame_base
*
3721 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3723 CORE_ADDR pc
= get_frame_pc (this_frame
);
3724 if (mips_pc_is_mips (pc
))
3725 return &mips_insn32_frame_base
;
3730 static struct trad_frame_cache
*
3731 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3734 CORE_ADDR start_addr
;
3735 CORE_ADDR stack_addr
;
3736 struct trad_frame_cache
*this_trad_cache
;
3737 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3738 int num_regs
= gdbarch_num_regs (gdbarch
);
3740 if ((*this_cache
) != NULL
)
3741 return (struct trad_frame_cache
*) (*this_cache
);
3742 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3743 (*this_cache
) = this_trad_cache
;
3745 /* The return address is in the link register. */
3746 trad_frame_set_reg_realreg (this_trad_cache
,
3747 gdbarch_pc_regnum (gdbarch
),
3748 num_regs
+ MIPS_RA_REGNUM
);
3750 /* Frame ID, since it's a frameless / stackless function, no stack
3751 space is allocated and SP on entry is the current SP. */
3752 pc
= get_frame_pc (this_frame
);
3753 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3754 stack_addr
= get_frame_register_signed (this_frame
,
3755 num_regs
+ MIPS_SP_REGNUM
);
3756 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3758 /* Assume that the frame's base is the same as the
3760 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3762 return this_trad_cache
;
3766 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3767 struct frame_id
*this_id
)
3769 struct trad_frame_cache
*this_trad_cache
3770 = mips_stub_frame_cache (this_frame
, this_cache
);
3771 trad_frame_get_id (this_trad_cache
, this_id
);
3774 static struct value
*
3775 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3776 void **this_cache
, int regnum
)
3778 struct trad_frame_cache
*this_trad_cache
3779 = mips_stub_frame_cache (this_frame
, this_cache
);
3780 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3784 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3785 struct frame_info
*this_frame
, void **this_cache
)
3788 struct obj_section
*s
;
3789 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3790 struct bound_minimal_symbol msym
;
3792 /* Use the stub unwinder for unreadable code. */
3793 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3796 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3799 /* Calling a PIC function from a non-PIC function passes through a
3800 stub. The stub for foo is named ".pic.foo". */
3801 msym
= lookup_minimal_symbol_by_pc (pc
);
3802 if (msym
.minsym
!= NULL
3803 && MSYMBOL_LINKAGE_NAME (msym
.minsym
) != NULL
3804 && startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
3810 static const struct frame_unwind mips_stub_frame_unwind
=
3813 default_frame_unwind_stop_reason
,
3814 mips_stub_frame_this_id
,
3815 mips_stub_frame_prev_register
,
3817 mips_stub_frame_sniffer
3821 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3824 struct trad_frame_cache
*this_trad_cache
3825 = mips_stub_frame_cache (this_frame
, this_cache
);
3826 return trad_frame_get_this_base (this_trad_cache
);
3829 static const struct frame_base mips_stub_frame_base
=
3831 &mips_stub_frame_unwind
,
3832 mips_stub_frame_base_address
,
3833 mips_stub_frame_base_address
,
3834 mips_stub_frame_base_address
3837 static const struct frame_base
*
3838 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3840 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3841 return &mips_stub_frame_base
;
3846 /* mips_addr_bits_remove - remove useless address bits */
3849 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3851 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3853 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3854 /* This hack is a work-around for existing boards using PMON, the
3855 simulator, and any other 64-bit targets that doesn't have true
3856 64-bit addressing. On these targets, the upper 32 bits of
3857 addresses are ignored by the hardware. Thus, the PC or SP are
3858 likely to have been sign extended to all 1s by instruction
3859 sequences that load 32-bit addresses. For example, a typical
3860 piece of code that loads an address is this:
3862 lui $r2, <upper 16 bits>
3863 ori $r2, <lower 16 bits>
3865 But the lui sign-extends the value such that the upper 32 bits
3866 may be all 1s. The workaround is simply to mask off these
3867 bits. In the future, gcc may be changed to support true 64-bit
3868 addressing, and this masking will have to be disabled. */
3869 return addr
&= 0xffffffffUL
;
3875 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3876 instruction and ending with a SC/SCD instruction. If such a sequence
3877 is found, attempt to step through it. A breakpoint is placed at the end of
3880 /* Instructions used during single-stepping of atomic sequences, standard
3882 #define LL_OPCODE 0x30
3883 #define LLD_OPCODE 0x34
3884 #define SC_OPCODE 0x38
3885 #define SCD_OPCODE 0x3c
3888 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3889 struct address_space
*aspace
, CORE_ADDR pc
)
3891 CORE_ADDR breaks
[2] = {-1, -1};
3893 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3897 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3898 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3900 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3901 /* Assume all atomic sequences start with a ll/lld instruction. */
3902 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3905 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3907 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3910 loc
+= MIPS_INSN32_SIZE
;
3911 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3913 /* Assume that there is at most one branch in the atomic
3914 sequence. If a branch is found, put a breakpoint in its
3915 destination address. */
3916 switch (itype_op (insn
))
3918 case 0: /* SPECIAL */
3919 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3920 return 0; /* fallback to the standard single-step code. */
3922 case 1: /* REGIMM */
3923 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3924 || ((itype_rt (insn
) & 0x1e) == 0
3925 && itype_rs (insn
) == 0)); /* BPOSGE* */
3929 return 0; /* fallback to the standard single-step code. */
3936 case 22: /* BLEZL */
3937 case 23: /* BGTTL */
3941 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3942 && (itype_rt (insn
) & 0x2) == 0);
3943 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3948 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3953 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3954 if (last_breakpoint
>= 1)
3955 return 0; /* More than one branch found, fallback to the
3956 standard single-step code. */
3957 breaks
[1] = branch_bp
;
3961 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3965 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3966 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3969 loc
+= MIPS_INSN32_SIZE
;
3971 /* Insert a breakpoint right after the end of the atomic sequence. */
3974 /* Check for duplicated breakpoints. Check also for a breakpoint
3975 placed (branch instruction's destination) in the atomic sequence. */
3976 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3977 last_breakpoint
= 0;
3979 /* Effectively inserts the breakpoints. */
3980 for (index
= 0; index
<= last_breakpoint
; index
++)
3981 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3987 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3988 struct address_space
*aspace
,
3991 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3992 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3993 CORE_ADDR breaks
[2] = {-1, -1};
3994 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4002 /* Assume all atomic sequences start with a ll/lld instruction. */
4003 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4004 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4006 loc
+= MIPS_INSN16_SIZE
;
4008 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4009 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4011 loc
+= MIPS_INSN16_SIZE
;
4013 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4014 that no atomic sequence is longer than "atomic_sequence_length"
4016 for (insn_count
= 0;
4017 !sc_found
&& insn_count
< atomic_sequence_length
;
4022 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4023 loc
+= MIPS_INSN16_SIZE
;
4025 /* Assume that there is at most one conditional branch in the
4026 atomic sequence. If a branch is found, put a breakpoint in
4027 its destination address. */
4028 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4030 /* 32-bit instructions. */
4031 case 2 * MIPS_INSN16_SIZE
:
4032 switch (micromips_op (insn
))
4034 case 0x10: /* POOL32I: bits 010000 */
4035 if ((b5s5_op (insn
) & 0x18) != 0x0
4036 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4037 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4038 && (b5s5_op (insn
) & 0x1d) != 0x11
4039 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4040 && ((b5s5_op (insn
) & 0x1e) != 0x14
4041 || (insn
& 0x3) != 0x0)
4042 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4043 && (b5s5_op (insn
) & 0x1e) != 0x1a
4044 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4045 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4046 || (insn
& 0x3) != 0x0)
4047 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4048 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4049 || (insn
& 0x3) != 0x1))
4050 /* BC1ANY*: bits 010000 111xx xxx01 */
4054 case 0x25: /* BEQ: bits 100101 */
4055 case 0x2d: /* BNE: bits 101101 */
4057 insn
|= mips_fetch_instruction (gdbarch
,
4058 ISA_MICROMIPS
, loc
, NULL
);
4059 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4060 + micromips_relative_offset16 (insn
));
4064 case 0x00: /* POOL32A: bits 000000 */
4066 insn
|= mips_fetch_instruction (gdbarch
,
4067 ISA_MICROMIPS
, loc
, NULL
);
4068 if (b0s6_op (insn
) != 0x3c
4069 /* POOL32Axf: bits 000000 ... 111100 */
4070 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4071 /* JALR, JALR.HB: 000000 000x111100 111100 */
4072 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4076 case 0x1d: /* JALS: bits 011101 */
4077 case 0x35: /* J: bits 110101 */
4078 case 0x3d: /* JAL: bits 111101 */
4079 case 0x3c: /* JALX: bits 111100 */
4080 return 0; /* Fall back to the standard single-step code. */
4082 case 0x18: /* POOL32C: bits 011000 */
4083 if ((b12s4_op (insn
) & 0xb) == 0xb)
4084 /* SC, SCD: bits 011000 1x11 */
4088 loc
+= MIPS_INSN16_SIZE
;
4091 /* 16-bit instructions. */
4092 case MIPS_INSN16_SIZE
:
4093 switch (micromips_op (insn
))
4095 case 0x23: /* BEQZ16: bits 100011 */
4096 case 0x2b: /* BNEZ16: bits 101011 */
4097 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4101 case 0x11: /* POOL16C: bits 010001 */
4102 if ((b5s5_op (insn
) & 0x1c) != 0xc
4103 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4104 && b5s5_op (insn
) != 0x18)
4105 /* JRADDIUSP: bits 010001 11000 */
4107 return 0; /* Fall back to the standard single-step code. */
4109 case 0x33: /* B16: bits 110011 */
4110 return 0; /* Fall back to the standard single-step code. */
4116 if (last_breakpoint
>= 1)
4117 return 0; /* More than one branch found, fallback to the
4118 standard single-step code. */
4119 breaks
[1] = branch_bp
;
4126 /* Insert a breakpoint right after the end of the atomic sequence. */
4129 /* Check for duplicated breakpoints. Check also for a breakpoint
4130 placed (branch instruction's destination) in the atomic sequence */
4131 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4132 last_breakpoint
= 0;
4134 /* Effectively inserts the breakpoints. */
4135 for (index
= 0; index
<= last_breakpoint
; index
++)
4136 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
4142 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4143 struct address_space
*aspace
, CORE_ADDR pc
)
4145 if (mips_pc_is_mips (pc
))
4146 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4147 else if (mips_pc_is_micromips (gdbarch
, pc
))
4148 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
4153 /* mips_software_single_step() is called just before we want to resume
4154 the inferior, if we want to single-step it but there is no hardware
4155 or kernel single-step support (MIPS on GNU/Linux for example). We find
4156 the target of the coming instruction and breakpoint it. */
4159 mips_software_single_step (struct frame_info
*frame
)
4161 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4162 struct address_space
*aspace
= get_frame_address_space (frame
);
4163 CORE_ADDR pc
, next_pc
;
4165 pc
= get_frame_pc (frame
);
4166 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
4169 next_pc
= mips_next_pc (frame
, pc
);
4171 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
4175 /* Test whether the PC points to the return instruction at the
4176 end of a function. */
4179 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4184 /* This used to check for MIPS16, but this piece of code is never
4185 called for MIPS16 functions. And likewise microMIPS ones. */
4186 gdb_assert (mips_pc_is_mips (pc
));
4188 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4190 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4194 /* This fencepost looks highly suspicious to me. Removing it also
4195 seems suspicious as it could affect remote debugging across serial
4199 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4205 struct inferior
*inf
;
4207 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4209 fence
= start_pc
- heuristic_fence_post
;
4213 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4214 fence
= VM_MIN_ADDRESS
;
4216 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4218 inf
= current_inferior ();
4220 /* Search back for previous return. */
4221 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4222 if (start_pc
< fence
)
4224 /* It's not clear to me why we reach this point when
4225 stop_soon, but with this test, at least we
4226 don't print out warnings for every child forked (eg, on
4227 decstation). 22apr93 rich@cygnus.com. */
4228 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4230 static int blurb_printed
= 0;
4232 warning (_("GDB can't find the start of the function at %s."),
4233 paddress (gdbarch
, pc
));
4237 /* This actually happens frequently in embedded
4238 development, when you first connect to a board
4239 and your stack pointer and pc are nowhere in
4240 particular. This message needs to give people
4241 in that situation enough information to
4242 determine that it's no big deal. */
4243 printf_filtered ("\n\
4244 GDB is unable to find the start of the function at %s\n\
4245 and thus can't determine the size of that function's stack frame.\n\
4246 This means that GDB may be unable to access that stack frame, or\n\
4247 the frames below it.\n\
4248 This problem is most likely caused by an invalid program counter or\n\
4250 However, if you think GDB should simply search farther back\n\
4251 from %s for code which looks like the beginning of a\n\
4252 function, you can increase the range of the search using the `set\n\
4253 heuristic-fence-post' command.\n",
4254 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4261 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4263 unsigned short inst
;
4265 /* On MIPS16, any one of the following is likely to be the
4266 start of a function:
4272 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4273 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4274 if ((inst
& 0xff80) == 0x6480) /* save */
4276 if (start_pc
- instlen
>= fence
)
4278 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4279 start_pc
- instlen
, NULL
);
4280 if ((inst
& 0xf800) == 0xf000) /* extend */
4281 start_pc
-= instlen
;
4285 else if (((inst
& 0xf81f) == 0xe809
4286 && (inst
& 0x700) != 0x700) /* entry */
4287 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4288 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4289 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4291 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4292 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4297 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4305 /* On microMIPS, any one of the following is likely to be the
4306 start of a function:
4310 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4311 switch (micromips_op (insn
))
4313 case 0xc: /* ADDIU: bits 001100 */
4314 case 0x17: /* DADDIU: bits 010111 */
4315 sreg
= b0s5_reg (insn
);
4316 dreg
= b5s5_reg (insn
);
4318 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4319 pc
+ MIPS_INSN16_SIZE
, NULL
);
4320 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4321 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4322 /* (D)ADDIU $sp, imm */
4327 case 0x10: /* POOL32I: bits 010000 */
4328 if (b5s5_op (insn
) == 0xd
4329 /* LUI: bits 010000 001101 */
4330 && b0s5_reg (insn
>> 16) == 28)
4335 case 0x13: /* POOL16D: bits 010011 */
4336 if ((insn
& 0x1) == 0x1)
4337 /* ADDIUSP: bits 010011 1 */
4339 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4345 /* ADDIUS5: bits 010011 0 */
4347 dreg
= b5s5_reg (insn
);
4348 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4349 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4350 /* ADDIUS5 $sp, -imm */
4358 else if (mips_about_to_return (gdbarch
, start_pc
))
4360 /* Skip return and its delay slot. */
4361 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4368 struct mips_objfile_private
4374 /* According to the current ABI, should the type be passed in a
4375 floating-point register (assuming that there is space)? When there
4376 is no FPU, FP are not even considered as possible candidates for
4377 FP registers and, consequently this returns false - forces FP
4378 arguments into integer registers. */
4381 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4382 struct type
*arg_type
)
4384 return ((typecode
== TYPE_CODE_FLT
4385 || (MIPS_EABI (gdbarch
)
4386 && (typecode
== TYPE_CODE_STRUCT
4387 || typecode
== TYPE_CODE_UNION
)
4388 && TYPE_NFIELDS (arg_type
) == 1
4389 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4391 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4394 /* On o32, argument passing in GPRs depends on the alignment of the type being
4395 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4398 mips_type_needs_double_align (struct type
*type
)
4400 enum type_code typecode
= TYPE_CODE (type
);
4402 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4404 else if (typecode
== TYPE_CODE_STRUCT
)
4406 if (TYPE_NFIELDS (type
) < 1)
4408 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4410 else if (typecode
== TYPE_CODE_UNION
)
4414 n
= TYPE_NFIELDS (type
);
4415 for (i
= 0; i
< n
; i
++)
4416 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4423 /* Adjust the address downward (direction of stack growth) so that it
4424 is correctly aligned for a new stack frame. */
4426 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4428 return align_down (addr
, 16);
4431 /* Implement the "push_dummy_code" gdbarch method. */
4434 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4435 CORE_ADDR funaddr
, struct value
**args
,
4436 int nargs
, struct type
*value_type
,
4437 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4438 struct regcache
*regcache
)
4440 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4444 /* Reserve enough room on the stack for our breakpoint instruction. */
4445 bp_slot
= sp
- sizeof (nop_insn
);
4447 /* Return to microMIPS mode if calling microMIPS code to avoid
4448 triggering an address error exception on processors that only
4449 support microMIPS execution. */
4450 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4451 ? make_compact_addr (bp_slot
) : bp_slot
);
4453 /* The breakpoint layer automatically adjusts the address of
4454 breakpoints inserted in a branch delay slot. With enough
4455 bad luck, the 4 bytes located just before our breakpoint
4456 instruction could look like a branch instruction, and thus
4457 trigger the adjustement, and break the function call entirely.
4458 So, we reserve those 4 bytes and write a nop instruction
4459 to prevent that from happening. */
4460 nop_addr
= bp_slot
- sizeof (nop_insn
);
4461 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4462 sp
= mips_frame_align (gdbarch
, nop_addr
);
4464 /* Inferior resumes at the function entry point. */
4471 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4472 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4473 int nargs
, struct value
**args
, CORE_ADDR sp
,
4474 int struct_return
, CORE_ADDR struct_addr
)
4480 int stack_offset
= 0;
4481 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4482 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4483 int regsize
= mips_abi_regsize (gdbarch
);
4485 /* For shared libraries, "t9" needs to point at the function
4487 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4489 /* Set the return address register to point to the entry point of
4490 the program, where a breakpoint lies in wait. */
4491 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4493 /* First ensure that the stack and structure return address (if any)
4494 are properly aligned. The stack has to be at least 64-bit
4495 aligned even on 32-bit machines, because doubles must be 64-bit
4496 aligned. For n32 and n64, stack frames need to be 128-bit
4497 aligned, so we round to this widest known alignment. */
4499 sp
= align_down (sp
, 16);
4500 struct_addr
= align_down (struct_addr
, 16);
4502 /* Now make space on the stack for the args. We allocate more
4503 than necessary for EABI, because the first few arguments are
4504 passed in registers, but that's OK. */
4505 for (argnum
= 0; argnum
< nargs
; argnum
++)
4506 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4507 sp
-= align_up (len
, 16);
4510 fprintf_unfiltered (gdb_stdlog
,
4511 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4512 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4514 /* Initialize the integer and float register pointers. */
4515 argreg
= MIPS_A0_REGNUM
;
4516 float_argreg
= mips_fpa0_regnum (gdbarch
);
4518 /* The struct_return pointer occupies the first parameter-passing reg. */
4522 fprintf_unfiltered (gdb_stdlog
,
4523 "mips_eabi_push_dummy_call: "
4524 "struct_return reg=%d %s\n",
4525 argreg
, paddress (gdbarch
, struct_addr
));
4526 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4529 /* Now load as many as possible of the first arguments into
4530 registers, and push the rest onto the stack. Loop thru args
4531 from first to last. */
4532 for (argnum
= 0; argnum
< nargs
; argnum
++)
4534 const gdb_byte
*val
;
4535 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4536 struct value
*arg
= args
[argnum
];
4537 struct type
*arg_type
= check_typedef (value_type (arg
));
4538 int len
= TYPE_LENGTH (arg_type
);
4539 enum type_code typecode
= TYPE_CODE (arg_type
);
4542 fprintf_unfiltered (gdb_stdlog
,
4543 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4544 argnum
+ 1, len
, (int) typecode
);
4546 /* The EABI passes structures that do not fit in a register by
4549 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4551 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4552 value_address (arg
));
4553 typecode
= TYPE_CODE_PTR
;
4557 fprintf_unfiltered (gdb_stdlog
, " push");
4560 val
= value_contents (arg
);
4562 /* 32-bit ABIs always start floating point arguments in an
4563 even-numbered floating point register. Round the FP register
4564 up before the check to see if there are any FP registers
4565 left. Non MIPS_EABI targets also pass the FP in the integer
4566 registers so also round up normal registers. */
4567 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4569 if ((float_argreg
& 1))
4573 /* Floating point arguments passed in registers have to be
4574 treated specially. On 32-bit architectures, doubles
4575 are passed in register pairs; the even register gets
4576 the low word, and the odd register gets the high word.
4577 On non-EABI processors, the first two floating point arguments are
4578 also copied to general registers, because MIPS16 functions
4579 don't use float registers for arguments. This duplication of
4580 arguments in general registers can't hurt non-MIPS16 functions
4581 because those registers are normally skipped. */
4582 /* MIPS_EABI squeezes a struct that contains a single floating
4583 point value into an FP register instead of pushing it onto the
4585 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4586 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4588 /* EABI32 will pass doubles in consecutive registers, even on
4589 64-bit cores. At one time, we used to check the size of
4590 `float_argreg' to determine whether or not to pass doubles
4591 in consecutive registers, but this is not sufficient for
4592 making the ABI determination. */
4593 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4595 int low_offset
= gdbarch_byte_order (gdbarch
)
4596 == BFD_ENDIAN_BIG
? 4 : 0;
4599 /* Write the low word of the double to the even register(s). */
4600 regval
= extract_signed_integer (val
+ low_offset
,
4603 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4604 float_argreg
, phex (regval
, 4));
4605 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4607 /* Write the high word of the double to the odd register(s). */
4608 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4611 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4612 float_argreg
, phex (regval
, 4));
4613 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4617 /* This is a floating point value that fits entirely
4618 in a single register. */
4619 /* On 32 bit ABI's the float_argreg is further adjusted
4620 above to ensure that it is even register aligned. */
4621 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4623 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4624 float_argreg
, phex (regval
, len
));
4625 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4630 /* Copy the argument to general registers or the stack in
4631 register-sized pieces. Large arguments are split between
4632 registers and stack. */
4633 /* Note: structs whose size is not a multiple of regsize
4634 are treated specially: Irix cc passes
4635 them in registers where gcc sometimes puts them on the
4636 stack. For maximum compatibility, we will put them in
4638 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4640 /* Note: Floating-point values that didn't fit into an FP
4641 register are only written to memory. */
4644 /* Remember if the argument was written to the stack. */
4645 int stack_used_p
= 0;
4646 int partial_len
= (len
< regsize
? len
: regsize
);
4649 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4652 /* Write this portion of the argument to the stack. */
4653 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4655 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4657 /* Should shorter than int integer values be
4658 promoted to int before being stored? */
4659 int longword_offset
= 0;
4662 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4665 && (typecode
== TYPE_CODE_INT
4666 || typecode
== TYPE_CODE_PTR
4667 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4668 longword_offset
= regsize
- len
;
4669 else if ((typecode
== TYPE_CODE_STRUCT
4670 || typecode
== TYPE_CODE_UNION
)
4671 && TYPE_LENGTH (arg_type
) < regsize
)
4672 longword_offset
= regsize
- len
;
4677 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4678 paddress (gdbarch
, stack_offset
));
4679 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4680 paddress (gdbarch
, longword_offset
));
4683 addr
= sp
+ stack_offset
+ longword_offset
;
4688 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4689 paddress (gdbarch
, addr
));
4690 for (i
= 0; i
< partial_len
; i
++)
4692 fprintf_unfiltered (gdb_stdlog
, "%02x",
4696 write_memory (addr
, val
, partial_len
);
4699 /* Note!!! This is NOT an else clause. Odd sized
4700 structs may go thru BOTH paths. Floating point
4701 arguments will not. */
4702 /* Write this portion of the argument to a general
4703 purpose register. */
4704 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4705 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4708 extract_signed_integer (val
, partial_len
, byte_order
);
4711 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4713 phex (regval
, regsize
));
4714 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4721 /* Compute the offset into the stack at which we will
4722 copy the next parameter.
4724 In the new EABI (and the NABI32), the stack_offset
4725 only needs to be adjusted when it has been used. */
4728 stack_offset
+= align_up (partial_len
, regsize
);
4732 fprintf_unfiltered (gdb_stdlog
, "\n");
4735 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4737 /* Return adjusted stack pointer. */
4741 /* Determine the return value convention being used. */
4743 static enum return_value_convention
4744 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4745 struct type
*type
, struct regcache
*regcache
,
4746 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4748 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4749 int fp_return_type
= 0;
4750 int offset
, regnum
, xfer
;
4752 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4753 return RETURN_VALUE_STRUCT_CONVENTION
;
4755 /* Floating point type? */
4756 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4758 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4760 /* Structs with a single field of float type
4761 are returned in a floating point register. */
4762 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4763 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4764 && TYPE_NFIELDS (type
) == 1)
4766 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4768 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4775 /* A floating-point value belongs in the least significant part
4778 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4779 regnum
= mips_regnum (gdbarch
)->fp0
;
4783 /* An integer value goes in V0/V1. */
4785 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4786 regnum
= MIPS_V0_REGNUM
;
4789 offset
< TYPE_LENGTH (type
);
4790 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4792 xfer
= mips_abi_regsize (gdbarch
);
4793 if (offset
+ xfer
> TYPE_LENGTH (type
))
4794 xfer
= TYPE_LENGTH (type
) - offset
;
4795 mips_xfer_register (gdbarch
, regcache
,
4796 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4797 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4801 return RETURN_VALUE_REGISTER_CONVENTION
;
4805 /* N32/N64 ABI stuff. */
4807 /* Search for a naturally aligned double at OFFSET inside a struct
4808 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4812 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4817 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4820 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4823 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4826 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4829 struct type
*field_type
;
4831 /* We're only looking at normal fields. */
4832 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4833 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4836 /* If we have gone past the offset, there is no double to pass. */
4837 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4841 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4843 /* If this field is entirely before the requested offset, go
4844 on to the next one. */
4845 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4848 /* If this is our special aligned double, we can stop. */
4849 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4850 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4853 /* This field starts at or before the requested offset, and
4854 overlaps it. If it is a structure, recurse inwards. */
4855 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4862 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4863 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4864 int nargs
, struct value
**args
, CORE_ADDR sp
,
4865 int struct_return
, CORE_ADDR struct_addr
)
4871 int stack_offset
= 0;
4872 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4873 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4875 /* For shared libraries, "t9" needs to point at the function
4877 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4879 /* Set the return address register to point to the entry point of
4880 the program, where a breakpoint lies in wait. */
4881 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4883 /* First ensure that the stack and structure return address (if any)
4884 are properly aligned. The stack has to be at least 64-bit
4885 aligned even on 32-bit machines, because doubles must be 64-bit
4886 aligned. For n32 and n64, stack frames need to be 128-bit
4887 aligned, so we round to this widest known alignment. */
4889 sp
= align_down (sp
, 16);
4890 struct_addr
= align_down (struct_addr
, 16);
4892 /* Now make space on the stack for the args. */
4893 for (argnum
= 0; argnum
< nargs
; argnum
++)
4894 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4895 sp
-= align_up (len
, 16);
4898 fprintf_unfiltered (gdb_stdlog
,
4899 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4900 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4902 /* Initialize the integer and float register pointers. */
4903 argreg
= MIPS_A0_REGNUM
;
4904 float_argreg
= mips_fpa0_regnum (gdbarch
);
4906 /* The struct_return pointer occupies the first parameter-passing reg. */
4910 fprintf_unfiltered (gdb_stdlog
,
4911 "mips_n32n64_push_dummy_call: "
4912 "struct_return reg=%d %s\n",
4913 argreg
, paddress (gdbarch
, struct_addr
));
4914 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4917 /* Now load as many as possible of the first arguments into
4918 registers, and push the rest onto the stack. Loop thru args
4919 from first to last. */
4920 for (argnum
= 0; argnum
< nargs
; argnum
++)
4922 const gdb_byte
*val
;
4923 struct value
*arg
= args
[argnum
];
4924 struct type
*arg_type
= check_typedef (value_type (arg
));
4925 int len
= TYPE_LENGTH (arg_type
);
4926 enum type_code typecode
= TYPE_CODE (arg_type
);
4929 fprintf_unfiltered (gdb_stdlog
,
4930 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4931 argnum
+ 1, len
, (int) typecode
);
4933 val
= value_contents (arg
);
4935 /* A 128-bit long double value requires an even-odd pair of
4936 floating-point registers. */
4938 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4939 && (float_argreg
& 1))
4945 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4946 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4948 /* This is a floating point value that fits entirely
4949 in a single register or a pair of registers. */
4950 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4951 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4953 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4954 float_argreg
, phex (regval
, reglen
));
4955 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4958 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4959 argreg
, phex (regval
, reglen
));
4960 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4965 regval
= extract_unsigned_integer (val
+ reglen
,
4966 reglen
, byte_order
);
4968 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4969 float_argreg
, phex (regval
, reglen
));
4970 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4973 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4974 argreg
, phex (regval
, reglen
));
4975 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4982 /* Copy the argument to general registers or the stack in
4983 register-sized pieces. Large arguments are split between
4984 registers and stack. */
4985 /* For N32/N64, structs, unions, or other composite types are
4986 treated as a sequence of doublewords, and are passed in integer
4987 or floating point registers as though they were simple scalar
4988 parameters to the extent that they fit, with any excess on the
4989 stack packed according to the normal memory layout of the
4991 The caller does not reserve space for the register arguments;
4992 the callee is responsible for reserving it if required. */
4993 /* Note: Floating-point values that didn't fit into an FP
4994 register are only written to memory. */
4997 /* Remember if the argument was written to the stack. */
4998 int stack_used_p
= 0;
4999 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5002 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5005 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5006 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5008 /* Write this portion of the argument to the stack. */
5009 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5011 /* Should shorter than int integer values be
5012 promoted to int before being stored? */
5013 int longword_offset
= 0;
5016 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5018 if ((typecode
== TYPE_CODE_INT
5019 || typecode
== TYPE_CODE_PTR
)
5021 longword_offset
= MIPS64_REGSIZE
- len
;
5026 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5027 paddress (gdbarch
, stack_offset
));
5028 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5029 paddress (gdbarch
, longword_offset
));
5032 addr
= sp
+ stack_offset
+ longword_offset
;
5037 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5038 paddress (gdbarch
, addr
));
5039 for (i
= 0; i
< partial_len
; i
++)
5041 fprintf_unfiltered (gdb_stdlog
, "%02x",
5045 write_memory (addr
, val
, partial_len
);
5048 /* Note!!! This is NOT an else clause. Odd sized
5049 structs may go thru BOTH paths. */
5050 /* Write this portion of the argument to a general
5051 purpose register. */
5052 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5056 /* Sign extend pointers, 32-bit integers and signed
5057 16-bit and 8-bit integers; everything else is taken
5060 if ((partial_len
== 4
5061 && (typecode
== TYPE_CODE_PTR
5062 || typecode
== TYPE_CODE_INT
))
5064 && typecode
== TYPE_CODE_INT
5065 && !TYPE_UNSIGNED (arg_type
)))
5066 regval
= extract_signed_integer (val
, partial_len
,
5069 regval
= extract_unsigned_integer (val
, partial_len
,
5072 /* A non-floating-point argument being passed in a
5073 general register. If a struct or union, and if
5074 the remaining length is smaller than the register
5075 size, we have to adjust the register value on
5078 It does not seem to be necessary to do the
5079 same for integral types. */
5081 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5082 && partial_len
< MIPS64_REGSIZE
5083 && (typecode
== TYPE_CODE_STRUCT
5084 || typecode
== TYPE_CODE_UNION
))
5085 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5089 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5091 phex (regval
, MIPS64_REGSIZE
));
5092 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5094 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5095 TYPE_LENGTH (arg_type
) - len
))
5098 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5100 phex (regval
, MIPS64_REGSIZE
));
5101 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5112 /* Compute the offset into the stack at which we will
5113 copy the next parameter.
5115 In N32 (N64?), the stack_offset only needs to be
5116 adjusted when it has been used. */
5119 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5123 fprintf_unfiltered (gdb_stdlog
, "\n");
5126 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5128 /* Return adjusted stack pointer. */
5132 static enum return_value_convention
5133 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5134 struct type
*type
, struct regcache
*regcache
,
5135 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5137 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5139 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5141 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5142 if needed), as appropriate for the type. Composite results (struct,
5143 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5146 * A struct with only one or two floating point fields is returned in $f0
5147 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5150 * Any other composite results of at most 128 bits are returned in
5151 $2 (first 64 bits) and $3 (remainder, if necessary).
5153 * Larger composite results are handled by converting the function to a
5154 procedure with an implicit first parameter, which is a pointer to an area
5155 reserved by the caller to receive the result. [The o32-bit ABI requires
5156 that all composite results be handled by conversion to implicit first
5157 parameters. The MIPS/SGI Fortran implementation has always made a
5158 specific exception to return COMPLEX results in the floating point
5161 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5162 return RETURN_VALUE_STRUCT_CONVENTION
;
5163 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5164 && TYPE_LENGTH (type
) == 16
5165 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5167 /* A 128-bit floating-point value fills both $f0 and $f2. The
5168 two registers are used in the same as memory order, so the
5169 eight bytes with the lower memory address are in $f0. */
5171 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5172 mips_xfer_register (gdbarch
, regcache
,
5173 (gdbarch_num_regs (gdbarch
)
5174 + mips_regnum (gdbarch
)->fp0
),
5175 8, gdbarch_byte_order (gdbarch
),
5176 readbuf
, writebuf
, 0);
5177 mips_xfer_register (gdbarch
, regcache
,
5178 (gdbarch_num_regs (gdbarch
)
5179 + mips_regnum (gdbarch
)->fp0
+ 2),
5180 8, gdbarch_byte_order (gdbarch
),
5181 readbuf
? readbuf
+ 8 : readbuf
,
5182 writebuf
? writebuf
+ 8 : writebuf
, 0);
5183 return RETURN_VALUE_REGISTER_CONVENTION
;
5185 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5186 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5188 /* A single or double floating-point value that fits in FP0. */
5190 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5191 mips_xfer_register (gdbarch
, regcache
,
5192 (gdbarch_num_regs (gdbarch
)
5193 + mips_regnum (gdbarch
)->fp0
),
5195 gdbarch_byte_order (gdbarch
),
5196 readbuf
, writebuf
, 0);
5197 return RETURN_VALUE_REGISTER_CONVENTION
;
5199 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5200 && TYPE_NFIELDS (type
) <= 2
5201 && TYPE_NFIELDS (type
) >= 1
5202 && ((TYPE_NFIELDS (type
) == 1
5203 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5205 || (TYPE_NFIELDS (type
) == 2
5206 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
5208 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
5209 == TYPE_CODE_FLT
))))
5211 /* A struct that contains one or two floats. Each value is part
5212 in the least significant part of their floating point
5213 register (or GPR, for soft float). */
5216 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5217 ? mips_regnum (gdbarch
)->fp0
5219 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5221 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5224 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5226 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5228 /* A 16-byte long double field goes in two consecutive
5230 mips_xfer_register (gdbarch
, regcache
,
5231 gdbarch_num_regs (gdbarch
) + regnum
,
5233 gdbarch_byte_order (gdbarch
),
5234 readbuf
, writebuf
, offset
);
5235 mips_xfer_register (gdbarch
, regcache
,
5236 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5238 gdbarch_byte_order (gdbarch
),
5239 readbuf
, writebuf
, offset
+ 8);
5242 mips_xfer_register (gdbarch
, regcache
,
5243 gdbarch_num_regs (gdbarch
) + regnum
,
5244 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5245 gdbarch_byte_order (gdbarch
),
5246 readbuf
, writebuf
, offset
);
5248 return RETURN_VALUE_REGISTER_CONVENTION
;
5250 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5251 || TYPE_CODE (type
) == TYPE_CODE_UNION
5252 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5254 /* A composite type. Extract the left justified value,
5255 regardless of the byte order. I.e. DO NOT USE
5259 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5260 offset
< TYPE_LENGTH (type
);
5261 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5263 int xfer
= register_size (gdbarch
, regnum
);
5264 if (offset
+ xfer
> TYPE_LENGTH (type
))
5265 xfer
= TYPE_LENGTH (type
) - offset
;
5267 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5268 offset
, xfer
, regnum
);
5269 mips_xfer_register (gdbarch
, regcache
,
5270 gdbarch_num_regs (gdbarch
) + regnum
,
5271 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5274 return RETURN_VALUE_REGISTER_CONVENTION
;
5278 /* A scalar extract each part but least-significant-byte
5282 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5283 offset
< TYPE_LENGTH (type
);
5284 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5286 int xfer
= register_size (gdbarch
, regnum
);
5287 if (offset
+ xfer
> TYPE_LENGTH (type
))
5288 xfer
= TYPE_LENGTH (type
) - offset
;
5290 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5291 offset
, xfer
, regnum
);
5292 mips_xfer_register (gdbarch
, regcache
,
5293 gdbarch_num_regs (gdbarch
) + regnum
,
5294 xfer
, gdbarch_byte_order (gdbarch
),
5295 readbuf
, writebuf
, offset
);
5297 return RETURN_VALUE_REGISTER_CONVENTION
;
5301 /* Which registers to use for passing floating-point values between
5302 function calls, one of floating-point, general and both kinds of
5303 registers. O32 and O64 use different register kinds for standard
5304 MIPS and MIPS16 code; to make the handling of cases where we may
5305 not know what kind of code is being used (e.g. no debug information)
5306 easier we sometimes use both kinds. */
5315 /* O32 ABI stuff. */
5318 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5319 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5320 int nargs
, struct value
**args
, CORE_ADDR sp
,
5321 int struct_return
, CORE_ADDR struct_addr
)
5327 int stack_offset
= 0;
5328 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5329 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5331 /* For shared libraries, "t9" needs to point at the function
5333 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5335 /* Set the return address register to point to the entry point of
5336 the program, where a breakpoint lies in wait. */
5337 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5339 /* First ensure that the stack and structure return address (if any)
5340 are properly aligned. The stack has to be at least 64-bit
5341 aligned even on 32-bit machines, because doubles must be 64-bit
5342 aligned. For n32 and n64, stack frames need to be 128-bit
5343 aligned, so we round to this widest known alignment. */
5345 sp
= align_down (sp
, 16);
5346 struct_addr
= align_down (struct_addr
, 16);
5348 /* Now make space on the stack for the args. */
5349 for (argnum
= 0; argnum
< nargs
; argnum
++)
5351 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5353 /* Align to double-word if necessary. */
5354 if (mips_type_needs_double_align (arg_type
))
5355 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5356 /* Allocate space on the stack. */
5357 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5359 sp
-= align_up (len
, 16);
5362 fprintf_unfiltered (gdb_stdlog
,
5363 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5364 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5366 /* Initialize the integer and float register pointers. */
5367 argreg
= MIPS_A0_REGNUM
;
5368 float_argreg
= mips_fpa0_regnum (gdbarch
);
5370 /* The struct_return pointer occupies the first parameter-passing reg. */
5374 fprintf_unfiltered (gdb_stdlog
,
5375 "mips_o32_push_dummy_call: "
5376 "struct_return reg=%d %s\n",
5377 argreg
, paddress (gdbarch
, struct_addr
));
5378 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5379 stack_offset
+= MIPS32_REGSIZE
;
5382 /* Now load as many as possible of the first arguments into
5383 registers, and push the rest onto the stack. Loop thru args
5384 from first to last. */
5385 for (argnum
= 0; argnum
< nargs
; argnum
++)
5387 const gdb_byte
*val
;
5388 struct value
*arg
= args
[argnum
];
5389 struct type
*arg_type
= check_typedef (value_type (arg
));
5390 int len
= TYPE_LENGTH (arg_type
);
5391 enum type_code typecode
= TYPE_CODE (arg_type
);
5394 fprintf_unfiltered (gdb_stdlog
,
5395 "mips_o32_push_dummy_call: %d len=%d type=%d",
5396 argnum
+ 1, len
, (int) typecode
);
5398 val
= value_contents (arg
);
5400 /* 32-bit ABIs always start floating point arguments in an
5401 even-numbered floating point register. Round the FP register
5402 up before the check to see if there are any FP registers
5403 left. O32 targets also pass the FP in the integer registers
5404 so also round up normal registers. */
5405 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5407 if ((float_argreg
& 1))
5411 /* Floating point arguments passed in registers have to be
5412 treated specially. On 32-bit architectures, doubles are
5413 passed in register pairs; the even FP register gets the
5414 low word, and the odd FP register gets the high word.
5415 On O32, the first two floating point arguments are also
5416 copied to general registers, following their memory order,
5417 because MIPS16 functions don't use float registers for
5418 arguments. This duplication of arguments in general
5419 registers can't hurt non-MIPS16 functions, because those
5420 registers are normally skipped. */
5422 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5423 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5425 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5427 int freg_offset
= gdbarch_byte_order (gdbarch
)
5428 == BFD_ENDIAN_BIG
? 1 : 0;
5429 unsigned long regval
;
5432 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5434 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5435 float_argreg
+ freg_offset
,
5437 regcache_cooked_write_unsigned (regcache
,
5438 float_argreg
++ + freg_offset
,
5441 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5442 argreg
, phex (regval
, 4));
5443 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5446 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5448 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5449 float_argreg
- freg_offset
,
5451 regcache_cooked_write_unsigned (regcache
,
5452 float_argreg
++ - freg_offset
,
5455 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5456 argreg
, phex (regval
, 4));
5457 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5461 /* This is a floating point value that fits entirely
5462 in a single register. */
5463 /* On 32 bit ABI's the float_argreg is further adjusted
5464 above to ensure that it is even register aligned. */
5465 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5467 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5468 float_argreg
, phex (regval
, len
));
5469 regcache_cooked_write_unsigned (regcache
,
5470 float_argreg
++, regval
);
5471 /* Although two FP registers are reserved for each
5472 argument, only one corresponding integer register is
5475 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5476 argreg
, phex (regval
, len
));
5477 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5479 /* Reserve space for the FP register. */
5480 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5484 /* Copy the argument to general registers or the stack in
5485 register-sized pieces. Large arguments are split between
5486 registers and stack. */
5487 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5488 are treated specially: Irix cc passes
5489 them in registers where gcc sometimes puts them on the
5490 stack. For maximum compatibility, we will put them in
5492 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5493 && len
% MIPS32_REGSIZE
!= 0);
5494 /* Structures should be aligned to eight bytes (even arg registers)
5495 on MIPS_ABI_O32, if their first member has double precision. */
5496 if (mips_type_needs_double_align (arg_type
))
5501 stack_offset
+= MIPS32_REGSIZE
;
5506 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5509 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5512 /* Write this portion of the argument to the stack. */
5513 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5514 || odd_sized_struct
)
5516 /* Should shorter than int integer values be
5517 promoted to int before being stored? */
5518 int longword_offset
= 0;
5523 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5524 paddress (gdbarch
, stack_offset
));
5525 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5526 paddress (gdbarch
, longword_offset
));
5529 addr
= sp
+ stack_offset
+ longword_offset
;
5534 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5535 paddress (gdbarch
, addr
));
5536 for (i
= 0; i
< partial_len
; i
++)
5538 fprintf_unfiltered (gdb_stdlog
, "%02x",
5542 write_memory (addr
, val
, partial_len
);
5545 /* Note!!! This is NOT an else clause. Odd sized
5546 structs may go thru BOTH paths. */
5547 /* Write this portion of the argument to a general
5548 purpose register. */
5549 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5551 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5553 /* Value may need to be sign extended, because
5554 mips_isa_regsize() != mips_abi_regsize(). */
5556 /* A non-floating-point argument being passed in a
5557 general register. If a struct or union, and if
5558 the remaining length is smaller than the register
5559 size, we have to adjust the register value on
5562 It does not seem to be necessary to do the
5563 same for integral types.
5565 Also don't do this adjustment on O64 binaries.
5567 cagney/2001-07-23: gdb/179: Also, GCC, when
5568 outputting LE O32 with sizeof (struct) <
5569 mips_abi_regsize(), generates a left shift
5570 as part of storing the argument in a register
5571 (the left shift isn't generated when
5572 sizeof (struct) >= mips_abi_regsize()). Since
5573 it is quite possible that this is GCC
5574 contradicting the LE/O32 ABI, GDB has not been
5575 adjusted to accommodate this. Either someone
5576 needs to demonstrate that the LE/O32 ABI
5577 specifies such a left shift OR this new ABI gets
5578 identified as such and GDB gets tweaked
5581 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5582 && partial_len
< MIPS32_REGSIZE
5583 && (typecode
== TYPE_CODE_STRUCT
5584 || typecode
== TYPE_CODE_UNION
))
5585 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5589 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5591 phex (regval
, MIPS32_REGSIZE
));
5592 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5595 /* Prevent subsequent floating point arguments from
5596 being passed in floating point registers. */
5597 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5603 /* Compute the offset into the stack at which we will
5604 copy the next parameter.
5606 In older ABIs, the caller reserved space for
5607 registers that contained arguments. This was loosely
5608 refered to as their "home". Consequently, space is
5609 always allocated. */
5611 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5615 fprintf_unfiltered (gdb_stdlog
, "\n");
5618 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5620 /* Return adjusted stack pointer. */
5624 static enum return_value_convention
5625 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5626 struct type
*type
, struct regcache
*regcache
,
5627 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5629 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5630 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5631 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5632 enum mips_fval_reg fval_reg
;
5634 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5635 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5636 || TYPE_CODE (type
) == TYPE_CODE_UNION
5637 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5638 return RETURN_VALUE_STRUCT_CONVENTION
;
5639 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5640 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5642 /* A single-precision floating-point value. If reading in or copying,
5643 then we get it from/put it to FP0 for standard MIPS code or GPR2
5644 for MIPS16 code. If writing out only, then we put it to both FP0
5645 and GPR2. We do not support reading in with no function known, if
5646 this safety check ever triggers, then we'll have to try harder. */
5647 gdb_assert (function
|| !readbuf
);
5652 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5655 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5657 case mips_fval_both
:
5658 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5661 if (fval_reg
!= mips_fval_gpr
)
5662 mips_xfer_register (gdbarch
, regcache
,
5663 (gdbarch_num_regs (gdbarch
)
5664 + mips_regnum (gdbarch
)->fp0
),
5666 gdbarch_byte_order (gdbarch
),
5667 readbuf
, writebuf
, 0);
5668 if (fval_reg
!= mips_fval_fpr
)
5669 mips_xfer_register (gdbarch
, regcache
,
5670 gdbarch_num_regs (gdbarch
) + 2,
5672 gdbarch_byte_order (gdbarch
),
5673 readbuf
, writebuf
, 0);
5674 return RETURN_VALUE_REGISTER_CONVENTION
;
5676 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5677 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5679 /* A double-precision floating-point value. If reading in or copying,
5680 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5681 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5682 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5683 no function known, if this safety check ever triggers, then we'll
5684 have to try harder. */
5685 gdb_assert (function
|| !readbuf
);
5690 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5693 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5695 case mips_fval_both
:
5696 fprintf_unfiltered (gdb_stderr
,
5697 "Return float in $fp1/$fp0 and $2/$3\n");
5700 if (fval_reg
!= mips_fval_gpr
)
5702 /* The most significant part goes in FP1, and the least significant
5704 switch (gdbarch_byte_order (gdbarch
))
5706 case BFD_ENDIAN_LITTLE
:
5707 mips_xfer_register (gdbarch
, regcache
,
5708 (gdbarch_num_regs (gdbarch
)
5709 + mips_regnum (gdbarch
)->fp0
+ 0),
5710 4, gdbarch_byte_order (gdbarch
),
5711 readbuf
, writebuf
, 0);
5712 mips_xfer_register (gdbarch
, regcache
,
5713 (gdbarch_num_regs (gdbarch
)
5714 + mips_regnum (gdbarch
)->fp0
+ 1),
5715 4, gdbarch_byte_order (gdbarch
),
5716 readbuf
, writebuf
, 4);
5718 case BFD_ENDIAN_BIG
:
5719 mips_xfer_register (gdbarch
, regcache
,
5720 (gdbarch_num_regs (gdbarch
)
5721 + mips_regnum (gdbarch
)->fp0
+ 1),
5722 4, gdbarch_byte_order (gdbarch
),
5723 readbuf
, writebuf
, 0);
5724 mips_xfer_register (gdbarch
, regcache
,
5725 (gdbarch_num_regs (gdbarch
)
5726 + mips_regnum (gdbarch
)->fp0
+ 0),
5727 4, gdbarch_byte_order (gdbarch
),
5728 readbuf
, writebuf
, 4);
5731 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5734 if (fval_reg
!= mips_fval_fpr
)
5736 /* The two 32-bit parts are always placed in GPR2 and GPR3
5737 following these registers' memory order. */
5738 mips_xfer_register (gdbarch
, regcache
,
5739 gdbarch_num_regs (gdbarch
) + 2,
5740 4, gdbarch_byte_order (gdbarch
),
5741 readbuf
, writebuf
, 0);
5742 mips_xfer_register (gdbarch
, regcache
,
5743 gdbarch_num_regs (gdbarch
) + 3,
5744 4, gdbarch_byte_order (gdbarch
),
5745 readbuf
, writebuf
, 4);
5747 return RETURN_VALUE_REGISTER_CONVENTION
;
5750 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5751 && TYPE_NFIELDS (type
) <= 2
5752 && TYPE_NFIELDS (type
) >= 1
5753 && ((TYPE_NFIELDS (type
) == 1
5754 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5756 || (TYPE_NFIELDS (type
) == 2
5757 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5759 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5761 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5763 /* A struct that contains one or two floats. Each value is part
5764 in the least significant part of their floating point
5766 gdb_byte reg
[MAX_REGISTER_SIZE
];
5769 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5770 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5772 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5775 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5777 mips_xfer_register (gdbarch
, regcache
,
5778 gdbarch_num_regs (gdbarch
) + regnum
,
5779 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5780 gdbarch_byte_order (gdbarch
),
5781 readbuf
, writebuf
, offset
);
5783 return RETURN_VALUE_REGISTER_CONVENTION
;
5787 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5788 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5790 /* A structure or union. Extract the left justified value,
5791 regardless of the byte order. I.e. DO NOT USE
5795 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5796 offset
< TYPE_LENGTH (type
);
5797 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5799 int xfer
= register_size (gdbarch
, regnum
);
5800 if (offset
+ xfer
> TYPE_LENGTH (type
))
5801 xfer
= TYPE_LENGTH (type
) - offset
;
5803 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5804 offset
, xfer
, regnum
);
5805 mips_xfer_register (gdbarch
, regcache
,
5806 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5807 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5809 return RETURN_VALUE_REGISTER_CONVENTION
;
5814 /* A scalar extract each part but least-significant-byte
5815 justified. o32 thinks registers are 4 byte, regardless of
5819 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5820 offset
< TYPE_LENGTH (type
);
5821 offset
+= MIPS32_REGSIZE
, regnum
++)
5823 int xfer
= MIPS32_REGSIZE
;
5824 if (offset
+ xfer
> TYPE_LENGTH (type
))
5825 xfer
= TYPE_LENGTH (type
) - offset
;
5827 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5828 offset
, xfer
, regnum
);
5829 mips_xfer_register (gdbarch
, regcache
,
5830 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5831 gdbarch_byte_order (gdbarch
),
5832 readbuf
, writebuf
, offset
);
5834 return RETURN_VALUE_REGISTER_CONVENTION
;
5838 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5842 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5843 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5845 struct value
**args
, CORE_ADDR sp
,
5846 int struct_return
, CORE_ADDR struct_addr
)
5852 int stack_offset
= 0;
5853 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5854 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5856 /* For shared libraries, "t9" needs to point at the function
5858 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5860 /* Set the return address register to point to the entry point of
5861 the program, where a breakpoint lies in wait. */
5862 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5864 /* First ensure that the stack and structure return address (if any)
5865 are properly aligned. The stack has to be at least 64-bit
5866 aligned even on 32-bit machines, because doubles must be 64-bit
5867 aligned. For n32 and n64, stack frames need to be 128-bit
5868 aligned, so we round to this widest known alignment. */
5870 sp
= align_down (sp
, 16);
5871 struct_addr
= align_down (struct_addr
, 16);
5873 /* Now make space on the stack for the args. */
5874 for (argnum
= 0; argnum
< nargs
; argnum
++)
5876 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5878 /* Allocate space on the stack. */
5879 len
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5881 sp
-= align_up (len
, 16);
5884 fprintf_unfiltered (gdb_stdlog
,
5885 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5886 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5888 /* Initialize the integer and float register pointers. */
5889 argreg
= MIPS_A0_REGNUM
;
5890 float_argreg
= mips_fpa0_regnum (gdbarch
);
5892 /* The struct_return pointer occupies the first parameter-passing reg. */
5896 fprintf_unfiltered (gdb_stdlog
,
5897 "mips_o64_push_dummy_call: "
5898 "struct_return reg=%d %s\n",
5899 argreg
, paddress (gdbarch
, struct_addr
));
5900 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5901 stack_offset
+= MIPS64_REGSIZE
;
5904 /* Now load as many as possible of the first arguments into
5905 registers, and push the rest onto the stack. Loop thru args
5906 from first to last. */
5907 for (argnum
= 0; argnum
< nargs
; argnum
++)
5909 const gdb_byte
*val
;
5910 struct value
*arg
= args
[argnum
];
5911 struct type
*arg_type
= check_typedef (value_type (arg
));
5912 int len
= TYPE_LENGTH (arg_type
);
5913 enum type_code typecode
= TYPE_CODE (arg_type
);
5916 fprintf_unfiltered (gdb_stdlog
,
5917 "mips_o64_push_dummy_call: %d len=%d type=%d",
5918 argnum
+ 1, len
, (int) typecode
);
5920 val
= value_contents (arg
);
5922 /* Floating point arguments passed in registers have to be
5923 treated specially. On 32-bit architectures, doubles are
5924 passed in register pairs; the even FP register gets the
5925 low word, and the odd FP register gets the high word.
5926 On O64, the first two floating point arguments are also
5927 copied to general registers, because MIPS16 functions
5928 don't use float registers for arguments. This duplication
5929 of arguments in general registers can't hurt non-MIPS16
5930 functions because those registers are normally skipped. */
5932 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5933 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5935 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5937 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5938 float_argreg
, phex (regval
, len
));
5939 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5941 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5942 argreg
, phex (regval
, len
));
5943 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5945 /* Reserve space for the FP register. */
5946 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5950 /* Copy the argument to general registers or the stack in
5951 register-sized pieces. Large arguments are split between
5952 registers and stack. */
5953 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5954 are treated specially: Irix cc passes them in registers
5955 where gcc sometimes puts them on the stack. For maximum
5956 compatibility, we will put them in both places. */
5957 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5958 && len
% MIPS64_REGSIZE
!= 0);
5961 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5964 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5967 /* Write this portion of the argument to the stack. */
5968 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5969 || odd_sized_struct
)
5971 /* Should shorter than int integer values be
5972 promoted to int before being stored? */
5973 int longword_offset
= 0;
5975 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5977 if ((typecode
== TYPE_CODE_INT
5978 || typecode
== TYPE_CODE_PTR
5979 || typecode
== TYPE_CODE_FLT
)
5981 longword_offset
= MIPS64_REGSIZE
- len
;
5986 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5987 paddress (gdbarch
, stack_offset
));
5988 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5989 paddress (gdbarch
, longword_offset
));
5992 addr
= sp
+ stack_offset
+ longword_offset
;
5997 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5998 paddress (gdbarch
, addr
));
5999 for (i
= 0; i
< partial_len
; i
++)
6001 fprintf_unfiltered (gdb_stdlog
, "%02x",
6005 write_memory (addr
, val
, partial_len
);
6008 /* Note!!! This is NOT an else clause. Odd sized
6009 structs may go thru BOTH paths. */
6010 /* Write this portion of the argument to a general
6011 purpose register. */
6012 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6014 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6016 /* Value may need to be sign extended, because
6017 mips_isa_regsize() != mips_abi_regsize(). */
6019 /* A non-floating-point argument being passed in a
6020 general register. If a struct or union, and if
6021 the remaining length is smaller than the register
6022 size, we have to adjust the register value on
6025 It does not seem to be necessary to do the
6026 same for integral types. */
6028 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6029 && partial_len
< MIPS64_REGSIZE
6030 && (typecode
== TYPE_CODE_STRUCT
6031 || typecode
== TYPE_CODE_UNION
))
6032 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6036 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6038 phex (regval
, MIPS64_REGSIZE
));
6039 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6042 /* Prevent subsequent floating point arguments from
6043 being passed in floating point registers. */
6044 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6050 /* Compute the offset into the stack at which we will
6051 copy the next parameter.
6053 In older ABIs, the caller reserved space for
6054 registers that contained arguments. This was loosely
6055 refered to as their "home". Consequently, space is
6056 always allocated. */
6058 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6062 fprintf_unfiltered (gdb_stdlog
, "\n");
6065 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6067 /* Return adjusted stack pointer. */
6071 static enum return_value_convention
6072 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6073 struct type
*type
, struct regcache
*regcache
,
6074 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6076 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6077 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6078 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6079 enum mips_fval_reg fval_reg
;
6081 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6082 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
6083 || TYPE_CODE (type
) == TYPE_CODE_UNION
6084 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
6085 return RETURN_VALUE_STRUCT_CONVENTION
;
6086 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
6088 /* A floating-point value. If reading in or copying, then we get it
6089 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6090 If writing out only, then we put it to both FP0 and GPR2. We do
6091 not support reading in with no function known, if this safety
6092 check ever triggers, then we'll have to try harder. */
6093 gdb_assert (function
|| !readbuf
);
6098 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6101 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6103 case mips_fval_both
:
6104 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6107 if (fval_reg
!= mips_fval_gpr
)
6108 mips_xfer_register (gdbarch
, regcache
,
6109 (gdbarch_num_regs (gdbarch
)
6110 + mips_regnum (gdbarch
)->fp0
),
6112 gdbarch_byte_order (gdbarch
),
6113 readbuf
, writebuf
, 0);
6114 if (fval_reg
!= mips_fval_fpr
)
6115 mips_xfer_register (gdbarch
, regcache
,
6116 gdbarch_num_regs (gdbarch
) + 2,
6118 gdbarch_byte_order (gdbarch
),
6119 readbuf
, writebuf
, 0);
6120 return RETURN_VALUE_REGISTER_CONVENTION
;
6124 /* A scalar extract each part but least-significant-byte
6128 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6129 offset
< TYPE_LENGTH (type
);
6130 offset
+= MIPS64_REGSIZE
, regnum
++)
6132 int xfer
= MIPS64_REGSIZE
;
6133 if (offset
+ xfer
> TYPE_LENGTH (type
))
6134 xfer
= TYPE_LENGTH (type
) - offset
;
6136 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6137 offset
, xfer
, regnum
);
6138 mips_xfer_register (gdbarch
, regcache
,
6139 gdbarch_num_regs (gdbarch
) + regnum
,
6140 xfer
, gdbarch_byte_order (gdbarch
),
6141 readbuf
, writebuf
, offset
);
6143 return RETURN_VALUE_REGISTER_CONVENTION
;
6147 /* Floating point register management.
6149 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6150 64bit operations, these early MIPS cpus treat fp register pairs
6151 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6152 registers and offer a compatibility mode that emulates the MIPS2 fp
6153 model. When operating in MIPS2 fp compat mode, later cpu's split
6154 double precision floats into two 32-bit chunks and store them in
6155 consecutive fp regs. To display 64-bit floats stored in this
6156 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6157 Throw in user-configurable endianness and you have a real mess.
6159 The way this works is:
6160 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6161 double-precision value will be split across two logical registers.
6162 The lower-numbered logical register will hold the low-order bits,
6163 regardless of the processor's endianness.
6164 - If we are on a 64-bit processor, and we are looking for a
6165 single-precision value, it will be in the low ordered bits
6166 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6167 save slot in memory.
6168 - If we are in 64-bit mode, everything is straightforward.
6170 Note that this code only deals with "live" registers at the top of the
6171 stack. We will attempt to deal with saved registers later, when
6172 the raw/cooked register interface is in place. (We need a general
6173 interface that can deal with dynamic saved register sizes -- fp
6174 regs could be 32 bits wide in one frame and 64 on the frame above
6177 /* Copy a 32-bit single-precision value from the current frame
6178 into rare_buffer. */
6181 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6182 gdb_byte
*rare_buffer
)
6184 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6185 int raw_size
= register_size (gdbarch
, regno
);
6186 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6188 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6189 error (_("can't read register %d (%s)"),
6190 regno
, gdbarch_register_name (gdbarch
, regno
));
6193 /* We have a 64-bit value for this register. Find the low-order
6197 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6202 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6206 memcpy (rare_buffer
, raw_buffer
, 4);
6210 /* Copy a 64-bit double-precision value from the current frame into
6211 rare_buffer. This may include getting half of it from the next
6215 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6216 gdb_byte
*rare_buffer
)
6218 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6219 int raw_size
= register_size (gdbarch
, regno
);
6221 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6223 /* We have a 64-bit value for this register, and we should use
6225 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6226 error (_("can't read register %d (%s)"),
6227 regno
, gdbarch_register_name (gdbarch
, regno
));
6231 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6233 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6234 internal_error (__FILE__
, __LINE__
,
6235 _("mips_read_fp_register_double: bad access to "
6236 "odd-numbered FP register"));
6238 /* mips_read_fp_register_single will find the correct 32 bits from
6240 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6242 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6243 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6247 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6248 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6254 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6256 { /* Do values for FP (float) regs. */
6257 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6258 gdb_byte
*raw_buffer
;
6259 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6264 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6266 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6267 fprintf_filtered (file
, "%*s",
6268 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6271 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6273 struct value_print_options opts
;
6275 /* 4-byte registers: Print hex and floating. Also print even
6276 numbered registers as doubles. */
6277 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6278 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6281 get_formatted_print_options (&opts
, 'x');
6282 print_scalar_formatted (raw_buffer
,
6283 builtin_type (gdbarch
)->builtin_uint32
,
6286 fprintf_filtered (file
, " flt: ");
6288 fprintf_filtered (file
, " <invalid float> ");
6290 fprintf_filtered (file
, "%-17.9g", flt1
);
6292 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6294 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6295 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6298 fprintf_filtered (file
, " dbl: ");
6300 fprintf_filtered (file
, "<invalid double>");
6302 fprintf_filtered (file
, "%-24.17g", doub
);
6307 struct value_print_options opts
;
6309 /* Eight byte registers: print each one as hex, float and double. */
6310 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6311 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6314 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6315 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6318 get_formatted_print_options (&opts
, 'x');
6319 print_scalar_formatted (raw_buffer
,
6320 builtin_type (gdbarch
)->builtin_uint64
,
6323 fprintf_filtered (file
, " flt: ");
6325 fprintf_filtered (file
, "<invalid float>");
6327 fprintf_filtered (file
, "%-17.9g", flt1
);
6329 fprintf_filtered (file
, " dbl: ");
6331 fprintf_filtered (file
, "<invalid double>");
6333 fprintf_filtered (file
, "%-24.17g", doub
);
6338 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6341 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6342 struct value_print_options opts
;
6345 if (mips_float_register_p (gdbarch
, regnum
))
6347 mips_print_fp_register (file
, frame
, regnum
);
6351 val
= get_frame_register_value (frame
, regnum
);
6353 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6355 /* The problem with printing numeric register names (r26, etc.) is that
6356 the user can't use them on input. Probably the best solution is to
6357 fix it so that either the numeric or the funky (a2, etc.) names
6358 are accepted on input. */
6359 if (regnum
< MIPS_NUMREGS
)
6360 fprintf_filtered (file
, "(r%d): ", regnum
);
6362 fprintf_filtered (file
, ": ");
6364 get_formatted_print_options (&opts
, 'x');
6365 val_print_scalar_formatted (value_type (val
),
6366 value_contents_for_printing (val
),
6367 value_embedded_offset (val
),
6372 /* Print IEEE exception condition bits in FLAGS. */
6375 print_fpu_flags (struct ui_file
*file
, int flags
)
6377 if (flags
& (1 << 0))
6378 fputs_filtered (" inexact", file
);
6379 if (flags
& (1 << 1))
6380 fputs_filtered (" uflow", file
);
6381 if (flags
& (1 << 2))
6382 fputs_filtered (" oflow", file
);
6383 if (flags
& (1 << 3))
6384 fputs_filtered (" div0", file
);
6385 if (flags
& (1 << 4))
6386 fputs_filtered (" inval", file
);
6387 if (flags
& (1 << 5))
6388 fputs_filtered (" unimp", file
);
6389 fputc_filtered ('\n', file
);
6392 /* Print interesting information about the floating point processor
6393 (if present) or emulator. */
6396 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6397 struct frame_info
*frame
, const char *args
)
6399 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6400 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6404 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6405 type
= MIPS_FPU_NONE
;
6407 fprintf_filtered (file
, "fpu type: %s\n",
6408 type
== MIPS_FPU_DOUBLE
? "double-precision"
6409 : type
== MIPS_FPU_SINGLE
? "single-precision"
6412 if (type
== MIPS_FPU_NONE
)
6415 fprintf_filtered (file
, "reg size: %d bits\n",
6416 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6418 fputs_filtered ("cond :", file
);
6419 if (fcs
& (1 << 23))
6420 fputs_filtered (" 0", file
);
6421 for (i
= 1; i
<= 7; i
++)
6422 if (fcs
& (1 << (24 + i
)))
6423 fprintf_filtered (file
, " %d", i
);
6424 fputc_filtered ('\n', file
);
6426 fputs_filtered ("cause :", file
);
6427 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6428 fputs ("mask :", stdout
);
6429 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6430 fputs ("flags :", stdout
);
6431 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6433 fputs_filtered ("rounding: ", file
);
6436 case 0: fputs_filtered ("nearest\n", file
); break;
6437 case 1: fputs_filtered ("zero\n", file
); break;
6438 case 2: fputs_filtered ("+inf\n", file
); break;
6439 case 3: fputs_filtered ("-inf\n", file
); break;
6442 fputs_filtered ("flush :", file
);
6443 if (fcs
& (1 << 21))
6444 fputs_filtered (" nearest", file
);
6445 if (fcs
& (1 << 22))
6446 fputs_filtered (" override", file
);
6447 if (fcs
& (1 << 24))
6448 fputs_filtered (" zero", file
);
6449 if ((fcs
& (0xb << 21)) == 0)
6450 fputs_filtered (" no", file
);
6451 fputc_filtered ('\n', file
);
6453 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6454 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6455 fputc_filtered ('\n', file
);
6457 default_print_float_info (gdbarch
, file
, frame
, args
);
6460 /* Replacement for generic do_registers_info.
6461 Print regs in pretty columns. */
6464 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6467 fprintf_filtered (file
, " ");
6468 mips_print_fp_register (file
, frame
, regnum
);
6469 fprintf_filtered (file
, "\n");
6474 /* Print a row's worth of GP (int) registers, with name labels above. */
6477 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6480 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6481 /* Do values for GP (int) regs. */
6482 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6483 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6488 /* For GP registers, we print a separate row of names above the vals. */
6489 for (col
= 0, regnum
= start_regnum
;
6490 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6491 + gdbarch_num_pseudo_regs (gdbarch
);
6494 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6495 continue; /* unused register */
6496 if (mips_float_register_p (gdbarch
, regnum
))
6497 break; /* End the row: reached FP register. */
6498 /* Large registers are handled separately. */
6499 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6502 break; /* End the row before this register. */
6504 /* Print this register on a row by itself. */
6505 mips_print_register (file
, frame
, regnum
);
6506 fprintf_filtered (file
, "\n");
6510 fprintf_filtered (file
, " ");
6511 fprintf_filtered (file
,
6512 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6513 gdbarch_register_name (gdbarch
, regnum
));
6520 /* Print the R0 to R31 names. */
6521 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6522 fprintf_filtered (file
, "\n R%-4d",
6523 start_regnum
% gdbarch_num_regs (gdbarch
));
6525 fprintf_filtered (file
, "\n ");
6527 /* Now print the values in hex, 4 or 8 to the row. */
6528 for (col
= 0, regnum
= start_regnum
;
6529 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6530 + gdbarch_num_pseudo_regs (gdbarch
);
6533 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6534 continue; /* unused register */
6535 if (mips_float_register_p (gdbarch
, regnum
))
6536 break; /* End row: reached FP register. */
6537 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6538 break; /* End row: large register. */
6540 /* OK: get the data in raw format. */
6541 if (!deprecated_frame_register_read (frame
, regnum
, raw_buffer
))
6542 error (_("can't read register %d (%s)"),
6543 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6544 /* pad small registers */
6546 byte
< (mips_abi_regsize (gdbarch
)
6547 - register_size (gdbarch
, regnum
)); byte
++)
6548 printf_filtered (" ");
6549 /* Now print the register value in hex, endian order. */
6550 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6552 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6553 byte
< register_size (gdbarch
, regnum
); byte
++)
6554 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6556 for (byte
= register_size (gdbarch
, regnum
) - 1;
6558 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6559 fprintf_filtered (file
, " ");
6562 if (col
> 0) /* ie. if we actually printed anything... */
6563 fprintf_filtered (file
, "\n");
6568 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6571 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6572 struct frame_info
*frame
, int regnum
, int all
)
6574 if (regnum
!= -1) /* Do one specified register. */
6576 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6577 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6578 error (_("Not a valid register for the current processor type"));
6580 mips_print_register (file
, frame
, regnum
);
6581 fprintf_filtered (file
, "\n");
6584 /* Do all (or most) registers. */
6586 regnum
= gdbarch_num_regs (gdbarch
);
6587 while (regnum
< gdbarch_num_regs (gdbarch
)
6588 + gdbarch_num_pseudo_regs (gdbarch
))
6590 if (mips_float_register_p (gdbarch
, regnum
))
6592 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6593 regnum
= print_fp_register_row (file
, frame
, regnum
);
6595 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6598 regnum
= print_gp_register_row (file
, frame
, regnum
);
6604 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6605 struct frame_info
*frame
)
6607 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6608 CORE_ADDR pc
= get_frame_pc (frame
);
6609 struct address_space
*aspace
;
6615 if ((mips_pc_is_mips (pc
)
6616 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6617 || (mips_pc_is_micromips (gdbarch
, pc
)
6618 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6619 || (mips_pc_is_mips16 (gdbarch
, pc
)
6620 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6623 isa
= mips_pc_isa (gdbarch
, pc
);
6624 /* _has_delay_slot above will have validated the read. */
6625 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6626 size
= mips_insn_size (isa
, insn
);
6627 aspace
= get_frame_address_space (frame
);
6628 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6631 /* To skip prologues, I use this predicate. Returns either PC itself
6632 if the code at PC does not look like a function prologue; otherwise
6633 returns an address that (if we're lucky) follows the prologue. If
6634 LENIENT, then we must skip everything which is involved in setting
6635 up the frame (it's OK to skip more, just so long as we don't skip
6636 anything which might clobber the registers which are being saved.
6637 We must skip more in the case where part of the prologue is in the
6638 delay slot of a non-prologue instruction). */
6641 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6644 CORE_ADDR func_addr
;
6646 /* See if we can determine the end of the prologue via the symbol table.
6647 If so, then return either PC, or the PC after the prologue, whichever
6649 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6651 CORE_ADDR post_prologue_pc
6652 = skip_prologue_using_sal (gdbarch
, func_addr
);
6653 if (post_prologue_pc
!= 0)
6654 return std::max (pc
, post_prologue_pc
);
6657 /* Can't determine prologue from the symbol table, need to examine
6660 /* Find an upper limit on the function prologue using the debug
6661 information. If the debug information could not be used to provide
6662 that bound, then use an arbitrary large number as the upper bound. */
6663 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6665 limit_pc
= pc
+ 100; /* Magic. */
6667 if (mips_pc_is_mips16 (gdbarch
, pc
))
6668 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6669 else if (mips_pc_is_micromips (gdbarch
, pc
))
6670 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6672 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6675 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6676 This is a helper function for mips_stack_frame_destroyed_p. */
6679 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6681 CORE_ADDR func_addr
= 0, func_end
= 0;
6683 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6685 /* The MIPS epilogue is max. 12 bytes long. */
6686 CORE_ADDR addr
= func_end
- 12;
6688 if (addr
< func_addr
+ 4)
6689 addr
= func_addr
+ 4;
6693 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6695 unsigned long high_word
;
6698 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6699 high_word
= (inst
>> 16) & 0xffff;
6701 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6702 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6703 && inst
!= 0x03e00008 /* jr $ra */
6704 && inst
!= 0x00000000) /* nop */
6714 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6715 This is a helper function for mips_stack_frame_destroyed_p. */
6718 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6720 CORE_ADDR func_addr
= 0;
6721 CORE_ADDR func_end
= 0;
6729 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6732 /* The microMIPS epilogue is max. 12 bytes long. */
6733 addr
= func_end
- 12;
6735 if (addr
< func_addr
+ 2)
6736 addr
= func_addr
+ 2;
6740 for (; pc
< func_end
; pc
+= loc
)
6743 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6744 loc
+= MIPS_INSN16_SIZE
;
6745 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6747 /* 32-bit instructions. */
6748 case 2 * MIPS_INSN16_SIZE
:
6750 insn
|= mips_fetch_instruction (gdbarch
,
6751 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6752 loc
+= MIPS_INSN16_SIZE
;
6753 switch (micromips_op (insn
>> 16))
6755 case 0xc: /* ADDIU: bits 001100 */
6756 case 0x17: /* DADDIU: bits 010111 */
6757 sreg
= b0s5_reg (insn
>> 16);
6758 dreg
= b5s5_reg (insn
>> 16);
6759 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6760 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6761 /* (D)ADDIU $sp, imm */
6771 /* 16-bit instructions. */
6772 case MIPS_INSN16_SIZE
:
6773 switch (micromips_op (insn
))
6775 case 0x3: /* MOVE: bits 000011 */
6776 sreg
= b0s5_reg (insn
);
6777 dreg
= b5s5_reg (insn
);
6778 if (sreg
== 0 && dreg
== 0)
6779 /* MOVE $zero, $zero aka NOP */
6783 case 0x11: /* POOL16C: bits 010001 */
6784 if (b5s5_op (insn
) == 0x18
6785 /* JRADDIUSP: bits 010011 11000 */
6786 || (b5s5_op (insn
) == 0xd
6787 /* JRC: bits 010011 01101 */
6788 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6793 case 0x13: /* POOL16D: bits 010011 */
6794 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6795 if ((insn
& 0x1) == 0x1
6796 /* ADDIUSP: bits 010011 1 */
6810 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6811 This is a helper function for mips_stack_frame_destroyed_p. */
6814 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6816 CORE_ADDR func_addr
= 0, func_end
= 0;
6818 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6820 /* The MIPS epilogue is max. 12 bytes long. */
6821 CORE_ADDR addr
= func_end
- 12;
6823 if (addr
< func_addr
+ 4)
6824 addr
= func_addr
+ 4;
6828 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6830 unsigned short inst
;
6832 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6834 if ((inst
& 0xf800) == 0xf000) /* extend */
6837 if (inst
!= 0x6300 /* addiu $sp,offset */
6838 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6839 && inst
!= 0xe820 /* jr $ra */
6840 && inst
!= 0xe8a0 /* jrc $ra */
6841 && inst
!= 0x6500) /* nop */
6851 /* Implement the stack_frame_destroyed_p gdbarch method.
6853 The epilogue is defined here as the area at the end of a function,
6854 after an instruction which destroys the function's stack frame. */
6857 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6859 if (mips_pc_is_mips16 (gdbarch
, pc
))
6860 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6861 else if (mips_pc_is_micromips (gdbarch
, pc
))
6862 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6864 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6867 /* Root of all "set mips "/"show mips " commands. This will eventually be
6868 used for all MIPS-specific commands. */
6871 show_mips_command (char *args
, int from_tty
)
6873 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6877 set_mips_command (char *args
, int from_tty
)
6880 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6881 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6884 /* Commands to show/set the MIPS FPU type. */
6887 show_mipsfpu_command (char *args
, int from_tty
)
6891 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6894 ("The MIPS floating-point coprocessor is unknown "
6895 "because the current architecture is not MIPS.\n");
6899 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6901 case MIPS_FPU_SINGLE
:
6902 fpu
= "single-precision";
6904 case MIPS_FPU_DOUBLE
:
6905 fpu
= "double-precision";
6908 fpu
= "absent (none)";
6911 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6913 if (mips_fpu_type_auto
)
6914 printf_unfiltered ("The MIPS floating-point coprocessor "
6915 "is set automatically (currently %s)\n",
6919 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6924 set_mipsfpu_command (char *args
, int from_tty
)
6926 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6927 "\"single\",\"none\" or \"auto\".\n");
6928 show_mipsfpu_command (args
, from_tty
);
6932 set_mipsfpu_single_command (char *args
, int from_tty
)
6934 struct gdbarch_info info
;
6935 gdbarch_info_init (&info
);
6936 mips_fpu_type
= MIPS_FPU_SINGLE
;
6937 mips_fpu_type_auto
= 0;
6938 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6939 instead of relying on globals. Doing that would let generic code
6940 handle the search for this specific architecture. */
6941 if (!gdbarch_update_p (info
))
6942 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6946 set_mipsfpu_double_command (char *args
, int from_tty
)
6948 struct gdbarch_info info
;
6949 gdbarch_info_init (&info
);
6950 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6951 mips_fpu_type_auto
= 0;
6952 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6953 instead of relying on globals. Doing that would let generic code
6954 handle the search for this specific architecture. */
6955 if (!gdbarch_update_p (info
))
6956 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6960 set_mipsfpu_none_command (char *args
, int from_tty
)
6962 struct gdbarch_info info
;
6963 gdbarch_info_init (&info
);
6964 mips_fpu_type
= MIPS_FPU_NONE
;
6965 mips_fpu_type_auto
= 0;
6966 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6967 instead of relying on globals. Doing that would let generic code
6968 handle the search for this specific architecture. */
6969 if (!gdbarch_update_p (info
))
6970 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6974 set_mipsfpu_auto_command (char *args
, int from_tty
)
6976 mips_fpu_type_auto
= 1;
6979 /* Just like reinit_frame_cache, but with the right arguments to be
6980 callable as an sfunc. */
6983 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6984 struct cmd_list_element
*c
)
6986 reinit_frame_cache ();
6990 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6992 struct gdbarch
*gdbarch
= (struct gdbarch
*) info
->application_data
;
6994 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6995 disassembler needs to be able to locally determine the ISA, and
6996 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6998 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6999 info
->mach
= bfd_mach_mips16
;
7000 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
7001 info
->mach
= bfd_mach_mips_micromips
;
7003 /* Round down the instruction address to the appropriate boundary. */
7004 memaddr
&= (info
->mach
== bfd_mach_mips16
7005 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
7007 /* Set the disassembler options. */
7008 if (!info
->disassembler_options
)
7009 /* This string is not recognized explicitly by the disassembler,
7010 but it tells the disassembler to not try to guess the ABI from
7011 the bfd elf headers, such that, if the user overrides the ABI
7012 of a program linked as NewABI, the disassembly will follow the
7013 register naming conventions specified by the user. */
7014 info
->disassembler_options
= "gpr-names=32";
7016 /* Call the appropriate disassembler based on the target endian-ness. */
7017 if (info
->endian
== BFD_ENDIAN_BIG
)
7018 return print_insn_big_mips (memaddr
, info
);
7020 return print_insn_little_mips (memaddr
, info
);
7024 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
7026 /* Set up the disassembler info, so that we get the right
7027 register names from libopcodes. */
7028 info
->disassembler_options
= "gpr-names=n32";
7029 info
->flavour
= bfd_target_elf_flavour
;
7031 return gdb_print_insn_mips (memaddr
, info
);
7035 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
7037 /* Set up the disassembler info, so that we get the right
7038 register names from libopcodes. */
7039 info
->disassembler_options
= "gpr-names=64";
7040 info
->flavour
= bfd_target_elf_flavour
;
7042 return gdb_print_insn_mips (memaddr
, info
);
7045 /* This function implements gdbarch_breakpoint_from_pc. It uses the
7046 program counter value to determine whether a 16- or 32-bit breakpoint
7047 should be used. It returns a pointer to a string of bytes that encode a
7048 breakpoint instruction, stores the length of the string to *lenptr, and
7049 adjusts pc (if necessary) to point to the actual memory location where
7050 the breakpoint should be inserted. */
7052 static const gdb_byte
*
7053 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
7054 CORE_ADDR
*pcptr
, int *lenptr
)
7056 CORE_ADDR pc
= *pcptr
;
7058 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
7060 if (mips_pc_is_mips16 (gdbarch
, pc
))
7062 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7063 *pcptr
= unmake_compact_addr (pc
);
7064 *lenptr
= sizeof (mips16_big_breakpoint
);
7065 return mips16_big_breakpoint
;
7067 else if (mips_pc_is_micromips (gdbarch
, pc
))
7069 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7070 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7075 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &err
);
7076 size
= err
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
);
7077 *pcptr
= unmake_compact_addr (pc
);
7079 return (size
== 2) ? micromips16_big_breakpoint
7080 : micromips32_big_breakpoint
;
7084 /* The IDT board uses an unusual breakpoint value, and
7085 sometimes gets confused when it sees the usual MIPS
7086 breakpoint instruction. */
7087 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7088 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
7089 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
7090 /* Likewise, IRIX appears to expect a different breakpoint,
7091 although this is not apparent until you try to use pthreads. */
7092 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
7094 *lenptr
= sizeof (big_breakpoint
);
7096 if (strcmp (target_shortname
, "mips") == 0)
7097 return idt_big_breakpoint
;
7098 else if (strcmp (target_shortname
, "ddb") == 0
7099 || strcmp (target_shortname
, "pmon") == 0
7100 || strcmp (target_shortname
, "lsi") == 0)
7101 return pmon_big_breakpoint
;
7102 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
7103 return irix_big_breakpoint
;
7105 return big_breakpoint
;
7110 if (mips_pc_is_mips16 (gdbarch
, pc
))
7112 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7113 *pcptr
= unmake_compact_addr (pc
);
7114 *lenptr
= sizeof (mips16_little_breakpoint
);
7115 return mips16_little_breakpoint
;
7117 else if (mips_pc_is_micromips (gdbarch
, pc
))
7119 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7120 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7125 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &err
);
7126 size
= err
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
);
7127 *pcptr
= unmake_compact_addr (pc
);
7129 return (size
== 2) ? micromips16_little_breakpoint
7130 : micromips32_little_breakpoint
;
7134 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7135 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
7136 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
7138 *lenptr
= sizeof (little_breakpoint
);
7140 if (strcmp (target_shortname
, "mips") == 0)
7141 return idt_little_breakpoint
;
7142 else if (strcmp (target_shortname
, "ddb") == 0
7143 || strcmp (target_shortname
, "pmon") == 0
7144 || strcmp (target_shortname
, "lsi") == 0)
7145 return pmon_little_breakpoint
;
7147 return little_breakpoint
;
7152 /* Determine the remote breakpoint kind suitable for the PC. The following
7155 * 2 -- 16-bit MIPS16 mode breakpoint,
7157 * 3 -- 16-bit microMIPS mode breakpoint,
7159 * 4 -- 32-bit standard MIPS mode breakpoint,
7161 * 5 -- 32-bit microMIPS mode breakpoint. */
7164 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
7167 CORE_ADDR pc
= *pcptr
;
7169 if (mips_pc_is_mips16 (gdbarch
, pc
))
7171 *pcptr
= unmake_compact_addr (pc
);
7174 else if (mips_pc_is_micromips (gdbarch
, pc
))
7180 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7181 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
7182 *pcptr
= unmake_compact_addr (pc
);
7183 *kindptr
= size
| 1;
7189 /* Return non-zero if the standard MIPS instruction INST has a branch
7190 delay slot (i.e. it is a jump or branch instruction). This function
7191 is based on mips32_next_pc. */
7194 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7200 op
= itype_op (inst
);
7201 if ((inst
& 0xe0000000) != 0)
7203 rs
= itype_rs (inst
);
7204 rt
= itype_rt (inst
);
7205 return (is_octeon_bbit_op (op
, gdbarch
)
7206 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7207 || op
== 29 /* JALX: bits 011101 */
7210 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7211 || (rs
== 9 && (rt
& 0x2) == 0)
7212 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7213 || (rs
== 10 && (rt
& 0x2) == 0))));
7214 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7217 switch (op
& 0x07) /* extract bits 28,27,26 */
7219 case 0: /* SPECIAL */
7220 op
= rtype_funct (inst
);
7221 return (op
== 8 /* JR */
7222 || op
== 9); /* JALR */
7223 break; /* end SPECIAL */
7224 case 1: /* REGIMM */
7225 rs
= itype_rs (inst
);
7226 rt
= itype_rt (inst
); /* branch condition */
7227 return ((rt
& 0xc) == 0
7228 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7229 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7230 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7231 /* BPOSGE32, BPOSGE64: bits 1110x */
7232 break; /* end REGIMM */
7233 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7239 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7240 delay slot (i.e. it is a jump or branch instruction). */
7243 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7248 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7252 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7255 /* Return non-zero if the microMIPS instruction INSN, comprising the
7256 16-bit major opcode word in the high 16 bits and any second word
7257 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7258 jump or branch instruction). The instruction must be 32-bit if
7259 MUSTBE32 is set or can be any instruction otherwise. */
7262 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7264 ULONGEST major
= insn
>> 16;
7266 switch (micromips_op (major
))
7268 /* 16-bit instructions. */
7269 case 0x33: /* B16: bits 110011 */
7270 case 0x2b: /* BNEZ16: bits 101011 */
7271 case 0x23: /* BEQZ16: bits 100011 */
7273 case 0x11: /* POOL16C: bits 010001 */
7275 && ((b5s5_op (major
) == 0xc
7276 /* JR16: bits 010001 01100 */
7277 || (b5s5_op (major
) & 0x1e) == 0xe)));
7278 /* JALR16, JALRS16: bits 010001 0111x */
7279 /* 32-bit instructions. */
7280 case 0x3d: /* JAL: bits 111101 */
7281 case 0x3c: /* JALX: bits 111100 */
7282 case 0x35: /* J: bits 110101 */
7283 case 0x2d: /* BNE: bits 101101 */
7284 case 0x25: /* BEQ: bits 100101 */
7285 case 0x1d: /* JALS: bits 011101 */
7287 case 0x10: /* POOL32I: bits 010000 */
7288 return ((b5s5_op (major
) & 0x1c) == 0x0
7289 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7290 || (b5s5_op (major
) & 0x1d) == 0x4
7291 /* BLEZ, BGTZ: bits 010000 001x0 */
7292 || (b5s5_op (major
) & 0x1d) == 0x11
7293 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7294 || ((b5s5_op (major
) & 0x1e) == 0x14
7295 && (major
& 0x3) == 0x0)
7296 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7297 || (b5s5_op (major
) & 0x1e) == 0x1a
7298 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7299 || ((b5s5_op (major
) & 0x1e) == 0x1c
7300 && (major
& 0x3) == 0x0)
7301 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7302 || ((b5s5_op (major
) & 0x1c) == 0x1c
7303 && (major
& 0x3) == 0x1));
7304 /* BC1ANY*: bits 010000 111xx xxx01 */
7305 case 0x0: /* POOL32A: bits 000000 */
7306 return (b0s6_op (insn
) == 0x3c
7307 /* POOL32Axf: bits 000000 ... 111100 */
7308 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7309 /* JALR, JALR.HB: 000000 000x111100 111100 */
7310 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7316 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7317 slot (i.e. it is a non-compact jump instruction). The instruction
7318 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7321 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7322 CORE_ADDR addr
, int mustbe32
)
7328 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7331 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7333 if (size
== 2 * MIPS_INSN16_SIZE
)
7335 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7340 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7343 /* Return non-zero if the MIPS16 instruction INST, which must be
7344 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7345 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7346 instruction). This function is based on mips16_next_pc. */
7349 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7351 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7353 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7356 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7357 slot (i.e. it is a non-compact jump instruction). The instruction
7358 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7361 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7362 CORE_ADDR addr
, int mustbe32
)
7364 unsigned short insn
;
7367 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7371 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7374 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7375 This assumes KSSEG exists. */
7378 mips_segment_boundary (CORE_ADDR bpaddr
)
7380 CORE_ADDR mask
= CORE_ADDR_MAX
;
7383 if (sizeof (CORE_ADDR
) == 8)
7384 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7385 a compiler warning produced where CORE_ADDR is a 32-bit type even
7386 though in that case this is dead code). */
7387 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7390 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7391 segsize
= 29; /* 32-bit compatibility segment */
7393 segsize
= 62; /* xkseg */
7395 case 2: /* xkphys */
7398 default: /* xksseg (1), xkuseg/kuseg (0) */
7402 else if (bpaddr
& 0x80000000) /* kernel segment */
7405 segsize
= 31; /* user segment */
7407 return bpaddr
& mask
;
7410 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7411 it backwards if necessary. Return the address of the new location. */
7414 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7416 CORE_ADDR prev_addr
;
7418 CORE_ADDR func_addr
;
7420 /* If a breakpoint is set on the instruction in a branch delay slot,
7421 GDB gets confused. When the breakpoint is hit, the PC isn't on
7422 the instruction in the branch delay slot, the PC will point to
7423 the branch instruction. Since the PC doesn't match any known
7424 breakpoints, GDB reports a trap exception.
7426 There are two possible fixes for this problem.
7428 1) When the breakpoint gets hit, see if the BD bit is set in the
7429 Cause register (which indicates the last exception occurred in a
7430 branch delay slot). If the BD bit is set, fix the PC to point to
7431 the instruction in the branch delay slot.
7433 2) When the user sets the breakpoint, don't allow him to set the
7434 breakpoint on the instruction in the branch delay slot. Instead
7435 move the breakpoint to the branch instruction (which will have
7438 The problem with the first solution is that if the user then
7439 single-steps the processor, the branch instruction will get
7440 skipped (since GDB thinks the PC is on the instruction in the
7443 So, we'll use the second solution. To do this we need to know if
7444 the instruction we're trying to set the breakpoint on is in the
7445 branch delay slot. */
7447 boundary
= mips_segment_boundary (bpaddr
);
7449 /* Make sure we don't scan back before the beginning of the current
7450 function, since we may fetch constant data or insns that look like
7451 a jump. Of course we might do that anyway if the compiler has
7452 moved constants inline. :-( */
7453 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7454 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7455 boundary
= func_addr
;
7457 if (mips_pc_is_mips (bpaddr
))
7459 if (bpaddr
== boundary
)
7462 /* If the previous instruction has a branch delay slot, we have
7463 to move the breakpoint to the branch instruction. */
7464 prev_addr
= bpaddr
- 4;
7465 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7470 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7471 CORE_ADDR addr
, jmpaddr
;
7474 boundary
= unmake_compact_addr (boundary
);
7476 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7477 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7478 so try for that first, then try the 2 byte JALR/JR.
7479 The microMIPS ASE has a whole range of jumps and branches
7480 with delay slots, some of which take 4 bytes and some take
7481 2 bytes, so the idea is the same.
7482 FIXME: We have to assume that bpaddr is not the second half
7483 of an extended instruction. */
7484 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7485 ? micromips_insn_at_pc_has_delay_slot
7486 : mips16_insn_at_pc_has_delay_slot
);
7490 for (i
= 1; i
< 4; i
++)
7492 if (unmake_compact_addr (addr
) == boundary
)
7494 addr
-= MIPS_INSN16_SIZE
;
7495 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7496 /* Looks like a JR/JALR at [target-1], but it could be
7497 the second word of a previous JAL/JALX, so record it
7498 and check back one more. */
7500 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7503 /* Looks like a JAL/JALX at [target-2], but it could also
7504 be the second word of a previous JAL/JALX, record it,
7505 and check back one more. */
7508 /* Looks like a JAL/JALX at [target-3], so any previously
7509 recorded JAL/JALX or JR/JALR must be wrong, because:
7512 -2: JAL-ext (can't be JAL/JALX)
7513 -1: bdslot (can't be JR/JALR)
7516 Of course it could be another JAL-ext which looks
7517 like a JAL, but in that case we'd have broken out
7518 of this loop at [target-2]:
7522 -2: bdslot (can't be jmp)
7529 /* Not a jump instruction: if we're at [target-1] this
7530 could be the second word of a JAL/JALX, so continue;
7531 otherwise we're done. */
7544 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7545 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7548 mips_is_stub_suffix (const char *suffix
, int zero
)
7553 return zero
&& suffix
[1] == '\0';
7555 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7560 return suffix
[1] == '\0';
7566 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7567 call stubs, one of sf, df, sc, or dc. */
7570 mips_is_stub_mode (const char *mode
)
7572 return ((mode
[0] == 's' || mode
[0] == 'd')
7573 && (mode
[1] == 'f' || mode
[1] == 'c'));
7576 /* Code at PC is a compiler-generated stub. Such a stub for a function
7577 bar might have a name like __fn_stub_bar, and might look like this:
7584 followed by (or interspersed with):
7591 addiu $25, $25, %lo(bar)
7594 ($1 may be used in old code; for robustness we accept any register)
7597 lui $28, %hi(_gp_disp)
7598 addiu $28, $28, %lo(_gp_disp)
7601 addiu $25, $25, %lo(bar)
7604 In the case of a __call_stub_bar stub, the sequence to set up
7605 arguments might look like this:
7612 followed by (or interspersed with) one of the jump sequences above.
7614 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7615 of J or JR, respectively, followed by:
7621 We are at the beginning of the stub here, and scan down and extract
7622 the target address from the jump immediate instruction or, if a jump
7623 register instruction is used, from the register referred. Return
7624 the value of PC calculated or 0 if inconclusive.
7626 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7629 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7631 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7632 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7633 int addrreg
= MIPS_ZERO_REGNUM
;
7634 CORE_ADDR start_pc
= pc
;
7635 CORE_ADDR target_pc
= 0;
7642 status
== 0 && target_pc
== 0 && i
< 20;
7643 i
++, pc
+= MIPS_INSN32_SIZE
)
7645 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7651 switch (itype_op (inst
))
7653 case 0: /* SPECIAL */
7654 switch (rtype_funct (inst
))
7658 rs
= rtype_rs (inst
);
7659 if (rs
== MIPS_GP_REGNUM
)
7660 target_pc
= gp
; /* Hmm... */
7661 else if (rs
== addrreg
)
7665 case 0x21: /* ADDU */
7666 rt
= rtype_rt (inst
);
7667 rs
= rtype_rs (inst
);
7668 rd
= rtype_rd (inst
);
7669 if (rd
== MIPS_GP_REGNUM
7670 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7671 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7679 target_pc
= jtype_target (inst
) << 2;
7680 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7684 rt
= itype_rt (inst
);
7685 rs
= itype_rs (inst
);
7688 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7689 if (rt
== MIPS_GP_REGNUM
)
7691 else if (rt
== addrreg
)
7697 rt
= itype_rt (inst
);
7698 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7699 if (rt
== MIPS_GP_REGNUM
)
7701 else if (rt
!= MIPS_ZERO_REGNUM
)
7709 rt
= itype_rt (inst
);
7710 rs
= itype_rs (inst
);
7711 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7712 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7716 memset (buf
, 0, sizeof (buf
));
7717 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7719 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7728 /* If PC is in a MIPS16 call or return stub, return the address of the
7729 target PC, which is either the callee or the caller. There are several
7730 cases which must be handled:
7732 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7733 and the target PC is in $31 ($ra).
7734 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7735 and the target PC is in $2.
7736 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7737 i.e. before the JALR instruction, this is effectively a call stub
7738 and the target PC is in $2. Otherwise this is effectively
7739 a return stub and the target PC is in $18.
7740 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7741 JAL or JALR instruction, this is effectively a call stub and the
7742 target PC is buried in the instruction stream. Otherwise this
7743 is effectively a return stub and the target PC is in $18.
7744 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7745 stub and the target PC is buried in the instruction stream.
7747 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7748 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7752 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7754 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7755 CORE_ADDR start_addr
;
7759 /* Find the starting address and name of the function containing the PC. */
7760 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7763 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7764 and the target PC is in $31 ($ra). */
7765 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7766 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7767 && mips_is_stub_mode (name
+ prefixlen
)
7768 && name
[prefixlen
+ 2] == '\0')
7769 return get_frame_register_signed
7770 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7772 /* If the PC is in __mips16_call_stub_*, this is one of the call
7773 call/return stubs. */
7774 prefixlen
= strlen (mips_str_mips16_call_stub
);
7775 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7777 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7778 and the target PC is in $2. */
7779 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7780 return get_frame_register_signed
7781 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7783 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7784 i.e. before the JALR instruction, this is effectively a call stub
7785 and the target PC is in $2. Otherwise this is effectively
7786 a return stub and the target PC is in $18. */
7787 else if (mips_is_stub_mode (name
+ prefixlen
)
7788 && name
[prefixlen
+ 2] == '_'
7789 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7791 if (pc
== start_addr
)
7792 /* This is the 'call' part of a call stub. The return
7793 address is in $2. */
7794 return get_frame_register_signed
7795 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7797 /* This is the 'return' part of a call stub. The return
7798 address is in $18. */
7799 return get_frame_register_signed
7800 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7803 return 0; /* Not a stub. */
7806 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7807 compiler-generated call or call/return stubs. */
7808 if (startswith (name
, mips_str_fn_stub
)
7809 || startswith (name
, mips_str_call_stub
))
7811 if (pc
== start_addr
)
7812 /* This is the 'call' part of a call stub. Call this helper
7813 to scan through this code for interesting instructions
7814 and determine the final PC. */
7815 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7817 /* This is the 'return' part of a call stub. The return address
7819 return get_frame_register_signed
7820 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7823 return 0; /* Not a stub. */
7826 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7827 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7830 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7832 CORE_ADDR start_addr
;
7835 /* Find the starting address of the function containing the PC. */
7836 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7839 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7840 the start, i.e. after the JALR instruction, this is effectively
7842 prefixlen
= strlen (mips_str_mips16_call_stub
);
7843 if (pc
!= start_addr
7844 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7845 && mips_is_stub_mode (name
+ prefixlen
)
7846 && name
[prefixlen
+ 2] == '_'
7847 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7850 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7851 the JAL or JALR instruction, this is effectively a return stub. */
7852 prefixlen
= strlen (mips_str_call_fp_stub
);
7853 if (pc
!= start_addr
7854 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7857 /* Consume the .pic. prefix of any PIC stub, this function must return
7858 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7859 or the call stub path will trigger in handle_inferior_event causing
7861 prefixlen
= strlen (mips_str_pic
);
7862 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7865 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7866 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7867 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7868 && mips_is_stub_mode (name
+ prefixlen
)
7869 && name
[prefixlen
+ 2] == '\0')
7872 return 0; /* Not a stub. */
7875 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7876 PC of the stub target. The stub just loads $t9 and jumps to it,
7877 so that $t9 has the correct value at function entry. */
7880 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7882 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7883 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7884 struct bound_minimal_symbol msym
;
7886 gdb_byte stub_code
[16];
7887 int32_t stub_words
[4];
7889 /* The stub for foo is named ".pic.foo", and is either two
7890 instructions inserted before foo or a three instruction sequence
7891 which jumps to foo. */
7892 msym
= lookup_minimal_symbol_by_pc (pc
);
7893 if (msym
.minsym
== NULL
7894 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7895 || MSYMBOL_LINKAGE_NAME (msym
.minsym
) == NULL
7896 || !startswith (MSYMBOL_LINKAGE_NAME (msym
.minsym
), ".pic."))
7899 /* A two-instruction header. */
7900 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7903 /* A three-instruction (plus delay slot) trampoline. */
7904 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7906 if (target_read_memory (pc
, stub_code
, 16) != 0)
7908 for (i
= 0; i
< 4; i
++)
7909 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7912 /* A stub contains these instructions:
7915 addiu t9, t9, %lo(target)
7918 This works even for N64, since stubs are only generated with
7920 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7921 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7922 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7923 && stub_words
[3] == 0x00000000)
7924 return ((((stub_words
[0] & 0x0000ffff) << 16)
7925 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7928 /* Not a recognized stub. */
7933 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7935 CORE_ADDR requested_pc
= pc
;
7936 CORE_ADDR target_pc
;
7943 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7947 new_pc
= find_solib_trampoline_target (frame
, pc
);
7951 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7955 while (pc
!= target_pc
);
7957 return pc
!= requested_pc
? pc
: 0;
7960 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7961 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7964 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7967 if (num
>= 0 && num
< 32)
7969 else if (num
>= 38 && num
< 70)
7970 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7972 regnum
= mips_regnum (gdbarch
)->hi
;
7974 regnum
= mips_regnum (gdbarch
)->lo
;
7975 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7976 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7979 return gdbarch_num_regs (gdbarch
) + regnum
;
7983 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7984 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7987 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7990 if (num
>= 0 && num
< 32)
7992 else if (num
>= 32 && num
< 64)
7993 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7995 regnum
= mips_regnum (gdbarch
)->hi
;
7997 regnum
= mips_regnum (gdbarch
)->lo
;
7998 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7999 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
8002 return gdbarch_num_regs (gdbarch
) + regnum
;
8006 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
8008 /* Only makes sense to supply raw registers. */
8009 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
8010 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
8011 decide if it is valid. Should instead define a standard sim/gdb
8012 register numbering scheme. */
8013 if (gdbarch_register_name (gdbarch
,
8014 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
8015 && gdbarch_register_name (gdbarch
,
8016 gdbarch_num_regs (gdbarch
)
8017 + regnum
)[0] != '\0')
8020 return LEGACY_SIM_REGNO_IGNORE
;
8024 /* Convert an integer into an address. Extracting the value signed
8025 guarantees a correctly sign extended address. */
8028 mips_integer_to_address (struct gdbarch
*gdbarch
,
8029 struct type
*type
, const gdb_byte
*buf
)
8031 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
8032 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
8035 /* Dummy virtual frame pointer method. This is no more or less accurate
8036 than most other architectures; we just need to be explicit about it,
8037 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
8038 an assertion failure. */
8041 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
8042 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
8044 *reg
= MIPS_SP_REGNUM
;
8049 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
8051 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
8052 const char *name
= bfd_get_section_name (abfd
, sect
);
8054 if (*abip
!= MIPS_ABI_UNKNOWN
)
8057 if (!startswith (name
, ".mdebug."))
8060 if (strcmp (name
, ".mdebug.abi32") == 0)
8061 *abip
= MIPS_ABI_O32
;
8062 else if (strcmp (name
, ".mdebug.abiN32") == 0)
8063 *abip
= MIPS_ABI_N32
;
8064 else if (strcmp (name
, ".mdebug.abi64") == 0)
8065 *abip
= MIPS_ABI_N64
;
8066 else if (strcmp (name
, ".mdebug.abiO64") == 0)
8067 *abip
= MIPS_ABI_O64
;
8068 else if (strcmp (name
, ".mdebug.eabi32") == 0)
8069 *abip
= MIPS_ABI_EABI32
;
8070 else if (strcmp (name
, ".mdebug.eabi64") == 0)
8071 *abip
= MIPS_ABI_EABI64
;
8073 warning (_("unsupported ABI %s."), name
+ 8);
8077 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
8079 int *lbp
= (int *) obj
;
8080 const char *name
= bfd_get_section_name (abfd
, sect
);
8082 if (startswith (name
, ".gcc_compiled_long32"))
8084 else if (startswith (name
, ".gcc_compiled_long64"))
8086 else if (startswith (name
, ".gcc_compiled_long"))
8087 warning (_("unrecognized .gcc_compiled_longXX"));
8090 static enum mips_abi
8091 global_mips_abi (void)
8095 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
8096 if (mips_abi_strings
[i
] == mips_abi_string
)
8097 return (enum mips_abi
) i
;
8099 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
8102 /* Return the default compressed instruction set, either of MIPS16
8103 or microMIPS, selected when none could have been determined from
8104 the ELF header of the binary being executed (or no binary has been
8107 static enum mips_isa
8108 global_mips_compression (void)
8112 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8113 if (mips_compression_strings
[i
] == mips_compression_string
)
8114 return (enum mips_isa
) i
;
8116 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8120 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8122 /* If the size matches the set of 32-bit or 64-bit integer registers,
8123 assume that's what we've got. */
8124 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8125 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8127 /* If the size matches the full set of registers GDB traditionally
8128 knows about, including floating point, for either 32-bit or
8129 64-bit, assume that's what we've got. */
8130 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8131 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8133 /* Otherwise we don't have a useful guess. */
8136 static struct value
*
8137 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8139 const int *reg_p
= (const int *) baton
;
8140 return value_of_register (*reg_p
, frame
);
8143 static struct gdbarch
*
8144 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8146 struct gdbarch
*gdbarch
;
8147 struct gdbarch_tdep
*tdep
;
8149 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8151 enum mips_fpu_type fpu_type
;
8152 struct tdesc_arch_data
*tdesc_data
= NULL
;
8153 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8154 const char **reg_names
;
8155 struct mips_regnum mips_regnum
, *regnum
;
8156 enum mips_isa mips_isa
;
8160 /* Fill in the OS dependent register numbers and names. */
8161 if (info
.osabi
== GDB_OSABI_IRIX
)
8163 mips_regnum
.fp0
= 32;
8164 mips_regnum
.pc
= 64;
8165 mips_regnum
.cause
= 65;
8166 mips_regnum
.badvaddr
= 66;
8167 mips_regnum
.hi
= 67;
8168 mips_regnum
.lo
= 68;
8169 mips_regnum
.fp_control_status
= 69;
8170 mips_regnum
.fp_implementation_revision
= 70;
8171 mips_regnum
.dspacc
= dspacc
= -1;
8172 mips_regnum
.dspctl
= dspctl
= -1;
8174 reg_names
= mips_irix_reg_names
;
8176 else if (info
.osabi
== GDB_OSABI_LINUX
)
8178 mips_regnum
.fp0
= 38;
8179 mips_regnum
.pc
= 37;
8180 mips_regnum
.cause
= 36;
8181 mips_regnum
.badvaddr
= 35;
8182 mips_regnum
.hi
= 34;
8183 mips_regnum
.lo
= 33;
8184 mips_regnum
.fp_control_status
= 70;
8185 mips_regnum
.fp_implementation_revision
= 71;
8186 mips_regnum
.dspacc
= -1;
8187 mips_regnum
.dspctl
= -1;
8191 reg_names
= mips_linux_reg_names
;
8195 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8196 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8197 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8198 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8199 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8200 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8201 mips_regnum
.fp_control_status
= 70;
8202 mips_regnum
.fp_implementation_revision
= 71;
8203 mips_regnum
.dspacc
= dspacc
= -1;
8204 mips_regnum
.dspctl
= dspctl
= -1;
8205 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8206 if (info
.bfd_arch_info
!= NULL
8207 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8208 reg_names
= mips_tx39_reg_names
;
8210 reg_names
= mips_generic_reg_names
;
8213 /* Check any target description for validity. */
8214 if (tdesc_has_registers (info
.target_desc
))
8216 static const char *const mips_gprs
[] = {
8217 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8218 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8219 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8220 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8222 static const char *const mips_fprs
[] = {
8223 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8224 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8225 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8226 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8229 const struct tdesc_feature
*feature
;
8232 feature
= tdesc_find_feature (info
.target_desc
,
8233 "org.gnu.gdb.mips.cpu");
8234 if (feature
== NULL
)
8237 tdesc_data
= tdesc_data_alloc ();
8240 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8241 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
8245 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8246 mips_regnum
.lo
, "lo");
8247 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8248 mips_regnum
.hi
, "hi");
8249 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8250 mips_regnum
.pc
, "pc");
8254 tdesc_data_cleanup (tdesc_data
);
8258 feature
= tdesc_find_feature (info
.target_desc
,
8259 "org.gnu.gdb.mips.cp0");
8260 if (feature
== NULL
)
8262 tdesc_data_cleanup (tdesc_data
);
8267 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8268 mips_regnum
.badvaddr
, "badvaddr");
8269 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8270 MIPS_PS_REGNUM
, "status");
8271 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8272 mips_regnum
.cause
, "cause");
8276 tdesc_data_cleanup (tdesc_data
);
8280 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8281 backend is not prepared for that, though. */
8282 feature
= tdesc_find_feature (info
.target_desc
,
8283 "org.gnu.gdb.mips.fpu");
8284 if (feature
== NULL
)
8286 tdesc_data_cleanup (tdesc_data
);
8291 for (i
= 0; i
< 32; i
++)
8292 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8293 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8295 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8296 mips_regnum
.fp_control_status
,
8299 &= tdesc_numbered_register (feature
, tdesc_data
,
8300 mips_regnum
.fp_implementation_revision
,
8305 tdesc_data_cleanup (tdesc_data
);
8309 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8313 feature
= tdesc_find_feature (info
.target_desc
,
8314 "org.gnu.gdb.mips.dsp");
8315 /* The DSP registers are optional; it's OK if they are absent. */
8316 if (feature
!= NULL
)
8320 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8321 dspacc
+ i
++, "hi1");
8322 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8323 dspacc
+ i
++, "lo1");
8324 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8325 dspacc
+ i
++, "hi2");
8326 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8327 dspacc
+ i
++, "lo2");
8328 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8329 dspacc
+ i
++, "hi3");
8330 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8331 dspacc
+ i
++, "lo3");
8333 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8338 tdesc_data_cleanup (tdesc_data
);
8342 mips_regnum
.dspacc
= dspacc
;
8343 mips_regnum
.dspctl
= dspctl
;
8345 num_regs
= mips_regnum
.dspctl
+ 1;
8349 /* It would be nice to detect an attempt to use a 64-bit ABI
8350 when only 32-bit registers are provided. */
8354 /* First of all, extract the elf_flags, if available. */
8355 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8356 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8357 else if (arches
!= NULL
)
8358 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8362 fprintf_unfiltered (gdb_stdlog
,
8363 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8365 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8366 switch ((elf_flags
& EF_MIPS_ABI
))
8368 case E_MIPS_ABI_O32
:
8369 found_abi
= MIPS_ABI_O32
;
8371 case E_MIPS_ABI_O64
:
8372 found_abi
= MIPS_ABI_O64
;
8374 case E_MIPS_ABI_EABI32
:
8375 found_abi
= MIPS_ABI_EABI32
;
8377 case E_MIPS_ABI_EABI64
:
8378 found_abi
= MIPS_ABI_EABI64
;
8381 if ((elf_flags
& EF_MIPS_ABI2
))
8382 found_abi
= MIPS_ABI_N32
;
8384 found_abi
= MIPS_ABI_UNKNOWN
;
8388 /* GCC creates a pseudo-section whose name describes the ABI. */
8389 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8390 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8392 /* If we have no useful BFD information, use the ABI from the last
8393 MIPS architecture (if there is one). */
8394 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8395 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8397 /* Try the architecture for any hint of the correct ABI. */
8398 if (found_abi
== MIPS_ABI_UNKNOWN
8399 && info
.bfd_arch_info
!= NULL
8400 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8402 switch (info
.bfd_arch_info
->mach
)
8404 case bfd_mach_mips3900
:
8405 found_abi
= MIPS_ABI_EABI32
;
8407 case bfd_mach_mips4100
:
8408 case bfd_mach_mips5000
:
8409 found_abi
= MIPS_ABI_EABI64
;
8411 case bfd_mach_mips8000
:
8412 case bfd_mach_mips10000
:
8413 /* On Irix, ELF64 executables use the N64 ABI. The
8414 pseudo-sections which describe the ABI aren't present
8415 on IRIX. (Even for executables created by gcc.) */
8416 if (info
.abfd
!= NULL
8417 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8418 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8419 found_abi
= MIPS_ABI_N64
;
8421 found_abi
= MIPS_ABI_N32
;
8426 /* Default 64-bit objects to N64 instead of O32. */
8427 if (found_abi
== MIPS_ABI_UNKNOWN
8428 && info
.abfd
!= NULL
8429 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8430 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8431 found_abi
= MIPS_ABI_N64
;
8434 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8437 /* What has the user specified from the command line? */
8438 wanted_abi
= global_mips_abi ();
8440 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8443 /* Now that we have found what the ABI for this binary would be,
8444 check whether the user is overriding it. */
8445 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8446 mips_abi
= wanted_abi
;
8447 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8448 mips_abi
= found_abi
;
8450 mips_abi
= MIPS_ABI_O32
;
8452 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8455 /* Determine the default compressed ISA. */
8456 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8457 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8458 mips_isa
= ISA_MICROMIPS
;
8459 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8460 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8461 mips_isa
= ISA_MIPS16
;
8463 mips_isa
= global_mips_compression ();
8464 mips_compression_string
= mips_compression_strings
[mips_isa
];
8466 /* Also used when doing an architecture lookup. */
8468 fprintf_unfiltered (gdb_stdlog
,
8469 "mips_gdbarch_init: "
8470 "mips64_transfers_32bit_regs_p = %d\n",
8471 mips64_transfers_32bit_regs_p
);
8473 /* Determine the MIPS FPU type. */
8476 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8477 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8478 Tag_GNU_MIPS_ABI_FP
);
8479 #endif /* HAVE_ELF */
8481 if (!mips_fpu_type_auto
)
8482 fpu_type
= mips_fpu_type
;
8483 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8485 switch (elf_fpu_type
)
8487 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8488 fpu_type
= MIPS_FPU_DOUBLE
;
8490 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8491 fpu_type
= MIPS_FPU_SINGLE
;
8493 case Val_GNU_MIPS_ABI_FP_SOFT
:
8495 /* Soft float or unknown. */
8496 fpu_type
= MIPS_FPU_NONE
;
8500 else if (info
.bfd_arch_info
!= NULL
8501 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8502 switch (info
.bfd_arch_info
->mach
)
8504 case bfd_mach_mips3900
:
8505 case bfd_mach_mips4100
:
8506 case bfd_mach_mips4111
:
8507 case bfd_mach_mips4120
:
8508 fpu_type
= MIPS_FPU_NONE
;
8510 case bfd_mach_mips4650
:
8511 fpu_type
= MIPS_FPU_SINGLE
;
8514 fpu_type
= MIPS_FPU_DOUBLE
;
8517 else if (arches
!= NULL
)
8518 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8520 fpu_type
= MIPS_FPU_DOUBLE
;
8522 fprintf_unfiltered (gdb_stdlog
,
8523 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8525 /* Check for blatant incompatibilities. */
8527 /* If we have only 32-bit registers, then we can't debug a 64-bit
8529 if (info
.target_desc
8530 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8531 && mips_abi
!= MIPS_ABI_EABI32
8532 && mips_abi
!= MIPS_ABI_O32
)
8534 if (tdesc_data
!= NULL
)
8535 tdesc_data_cleanup (tdesc_data
);
8539 /* Try to find a pre-existing architecture. */
8540 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8542 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8544 /* MIPS needs to be pedantic about which ABI and the compressed
8545 ISA variation the object is using. */
8546 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8548 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8550 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8552 /* Need to be pedantic about which register virtual size is
8554 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8555 != mips64_transfers_32bit_regs_p
)
8557 /* Be pedantic about which FPU is selected. */
8558 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8561 if (tdesc_data
!= NULL
)
8562 tdesc_data_cleanup (tdesc_data
);
8563 return arches
->gdbarch
;
8566 /* Need a new architecture. Fill in a target specific vector. */
8567 tdep
= XNEW (struct gdbarch_tdep
);
8568 gdbarch
= gdbarch_alloc (&info
, tdep
);
8569 tdep
->elf_flags
= elf_flags
;
8570 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8571 tdep
->found_abi
= found_abi
;
8572 tdep
->mips_abi
= mips_abi
;
8573 tdep
->mips_isa
= mips_isa
;
8574 tdep
->mips_fpu_type
= fpu_type
;
8575 tdep
->register_size_valid_p
= 0;
8576 tdep
->register_size
= 0;
8578 if (info
.target_desc
)
8580 /* Some useful properties can be inferred from the target. */
8581 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8583 tdep
->register_size_valid_p
= 1;
8584 tdep
->register_size
= 4;
8586 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8588 tdep
->register_size_valid_p
= 1;
8589 tdep
->register_size
= 8;
8593 /* Initially set everything according to the default ABI/ISA. */
8594 set_gdbarch_short_bit (gdbarch
, 16);
8595 set_gdbarch_int_bit (gdbarch
, 32);
8596 set_gdbarch_float_bit (gdbarch
, 32);
8597 set_gdbarch_double_bit (gdbarch
, 64);
8598 set_gdbarch_long_double_bit (gdbarch
, 64);
8599 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8600 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8601 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8603 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8604 mips_ax_pseudo_register_collect
);
8605 set_gdbarch_ax_pseudo_register_push_stack
8606 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8608 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8609 mips_elf_make_msymbol_special
);
8610 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8611 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8612 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8614 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8615 *regnum
= mips_regnum
;
8616 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8617 set_gdbarch_num_regs (gdbarch
, num_regs
);
8618 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8619 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8620 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8621 tdep
->mips_processor_reg_names
= reg_names
;
8622 tdep
->regnum
= regnum
;
8627 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8628 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8629 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8630 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8631 tdep
->default_mask_address_p
= 0;
8632 set_gdbarch_long_bit (gdbarch
, 32);
8633 set_gdbarch_ptr_bit (gdbarch
, 32);
8634 set_gdbarch_long_long_bit (gdbarch
, 64);
8637 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8638 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8639 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8640 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8641 tdep
->default_mask_address_p
= 0;
8642 set_gdbarch_long_bit (gdbarch
, 32);
8643 set_gdbarch_ptr_bit (gdbarch
, 32);
8644 set_gdbarch_long_long_bit (gdbarch
, 64);
8646 case MIPS_ABI_EABI32
:
8647 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8648 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8649 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8650 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8651 tdep
->default_mask_address_p
= 0;
8652 set_gdbarch_long_bit (gdbarch
, 32);
8653 set_gdbarch_ptr_bit (gdbarch
, 32);
8654 set_gdbarch_long_long_bit (gdbarch
, 64);
8656 case MIPS_ABI_EABI64
:
8657 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8658 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8659 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8660 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8661 tdep
->default_mask_address_p
= 0;
8662 set_gdbarch_long_bit (gdbarch
, 64);
8663 set_gdbarch_ptr_bit (gdbarch
, 64);
8664 set_gdbarch_long_long_bit (gdbarch
, 64);
8667 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8668 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8669 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8670 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8671 tdep
->default_mask_address_p
= 0;
8672 set_gdbarch_long_bit (gdbarch
, 32);
8673 set_gdbarch_ptr_bit (gdbarch
, 32);
8674 set_gdbarch_long_long_bit (gdbarch
, 64);
8675 set_gdbarch_long_double_bit (gdbarch
, 128);
8676 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8679 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8680 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8681 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8682 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8683 tdep
->default_mask_address_p
= 0;
8684 set_gdbarch_long_bit (gdbarch
, 64);
8685 set_gdbarch_ptr_bit (gdbarch
, 64);
8686 set_gdbarch_long_long_bit (gdbarch
, 64);
8687 set_gdbarch_long_double_bit (gdbarch
, 128);
8688 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8691 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8694 /* GCC creates a pseudo-section whose name specifies the size of
8695 longs, since -mlong32 or -mlong64 may be used independent of
8696 other options. How those options affect pointer sizes is ABI and
8697 architecture dependent, so use them to override the default sizes
8698 set by the ABI. This table shows the relationship between ABI,
8699 -mlongXX, and size of pointers:
8701 ABI -mlongXX ptr bits
8702 --- -------- --------
8716 Note that for o32 and eabi32, pointers are always 32 bits
8717 regardless of any -mlongXX option. For all others, pointers and
8718 longs are the same, as set by -mlongXX or set by defaults. */
8720 if (info
.abfd
!= NULL
)
8724 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8727 set_gdbarch_long_bit (gdbarch
, long_bit
);
8731 case MIPS_ABI_EABI32
:
8736 case MIPS_ABI_EABI64
:
8737 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8740 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8745 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8746 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8749 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8750 flag in object files because to do so would make it impossible to
8751 link with libraries compiled without "-gp32". This is
8752 unnecessarily restrictive.
8754 We could solve this problem by adding "-gp32" multilibs to gcc,
8755 but to set this flag before gcc is built with such multilibs will
8756 break too many systems.''
8758 But even more unhelpfully, the default linker output target for
8759 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8760 for 64-bit programs - you need to change the ABI to change this,
8761 and not all gcc targets support that currently. Therefore using
8762 this flag to detect 32-bit mode would do the wrong thing given
8763 the current gcc - it would make GDB treat these 64-bit programs
8764 as 32-bit programs by default. */
8766 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8767 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8769 /* Add/remove bits from an address. The MIPS needs be careful to
8770 ensure that all 32 bit addresses are sign extended to 64 bits. */
8771 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8773 /* Unwind the frame. */
8774 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8775 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8776 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8778 /* Map debug register numbers onto internal register numbers. */
8779 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8780 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8781 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8782 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8783 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8784 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8786 /* MIPS version of CALL_DUMMY. */
8788 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8789 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8790 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8792 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8794 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8795 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8796 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8798 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8799 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8800 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8801 mips_remote_breakpoint_from_pc
);
8802 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8803 mips_adjust_breakpoint_address
);
8805 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8807 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8809 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8810 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8811 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8813 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8815 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8817 if (mips_abi
== MIPS_ABI_N32
)
8818 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8819 else if (mips_abi
== MIPS_ABI_N64
)
8820 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8822 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8824 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8825 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8826 need to all be folded into the target vector. Since they are
8827 being used as guards for target_stopped_by_watchpoint, why not have
8828 target_stopped_by_watchpoint return the type of watchpoint that the code
8830 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8832 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8834 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8835 to support MIPS16. This is a bad thing. Make sure not to do it
8836 if we have an OS ABI that actually supports shared libraries, since
8837 shared library support is more important. If we have an OS someday
8838 that supports both shared libraries and MIPS16, we'll have to find
8839 a better place for these.
8840 macro/2012-04-25: But that applies to return trampolines only and
8841 currently no MIPS OS ABI uses shared libraries that have them. */
8842 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8844 set_gdbarch_single_step_through_delay (gdbarch
,
8845 mips_single_step_through_delay
);
8847 /* Virtual tables. */
8848 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8850 mips_register_g_packet_guesses (gdbarch
);
8852 /* Hook in OS ABI-specific overrides, if they have been registered. */
8853 info
.tdep_info
= tdesc_data
;
8854 gdbarch_init_osabi (info
, gdbarch
);
8856 /* The hook may have adjusted num_regs, fetch the final value and
8857 set pc_regnum and sp_regnum now that it has been fixed. */
8858 num_regs
= gdbarch_num_regs (gdbarch
);
8859 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8860 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8862 /* Unwind the frame. */
8863 dwarf2_append_unwinders (gdbarch
);
8864 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8865 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8866 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8867 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8868 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8869 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8870 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8871 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8872 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8876 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8877 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8879 /* Override the normal target description methods to handle our
8880 dual real and pseudo registers. */
8881 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8882 set_gdbarch_register_reggroup_p (gdbarch
,
8883 mips_tdesc_register_reggroup_p
);
8885 num_regs
= gdbarch_num_regs (gdbarch
);
8886 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8887 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8888 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8891 /* Add ABI-specific aliases for the registers. */
8892 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8893 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8894 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8895 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8897 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8898 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8899 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8901 /* Add some other standard aliases. */
8902 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8903 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8904 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8906 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8907 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8908 value_of_mips_user_reg
,
8909 &mips_numeric_register_aliases
[i
].regnum
);
8915 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8917 struct gdbarch_info info
;
8919 /* Force the architecture to update, and (if it's a MIPS architecture)
8920 mips_gdbarch_init will take care of the rest. */
8921 gdbarch_info_init (&info
);
8922 gdbarch_update_p (info
);
8925 /* Print out which MIPS ABI is in use. */
8928 show_mips_abi (struct ui_file
*file
,
8930 struct cmd_list_element
*ignored_cmd
,
8931 const char *ignored_value
)
8933 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8936 "The MIPS ABI is unknown because the current architecture "
8940 enum mips_abi global_abi
= global_mips_abi ();
8941 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8942 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8944 if (global_abi
== MIPS_ABI_UNKNOWN
)
8947 "The MIPS ABI is set automatically (currently \"%s\").\n",
8949 else if (global_abi
== actual_abi
)
8952 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8956 /* Probably shouldn't happen... */
8957 fprintf_filtered (file
,
8958 "The (auto detected) MIPS ABI \"%s\" is in use "
8959 "even though the user setting was \"%s\".\n",
8960 actual_abi_str
, mips_abi_strings
[global_abi
]);
8965 /* Print out which MIPS compressed ISA encoding is used. */
8968 show_mips_compression (struct ui_file
*file
, int from_tty
,
8969 struct cmd_list_element
*c
, const char *value
)
8971 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8976 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8978 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8982 int ef_mips_32bitmode
;
8983 /* Determine the ISA. */
8984 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
9002 /* Determine the size of a pointer. */
9003 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
9004 fprintf_unfiltered (file
,
9005 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
9007 fprintf_unfiltered (file
,
9008 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
9010 fprintf_unfiltered (file
,
9011 "mips_dump_tdep: ef_mips_arch = %d\n",
9013 fprintf_unfiltered (file
,
9014 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
9015 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
9016 fprintf_unfiltered (file
,
9018 "mips_mask_address_p() %d (default %d)\n",
9019 mips_mask_address_p (tdep
),
9020 tdep
->default_mask_address_p
);
9022 fprintf_unfiltered (file
,
9023 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
9024 MIPS_DEFAULT_FPU_TYPE
,
9025 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
9026 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
9027 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
9029 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
9030 MIPS_EABI (gdbarch
));
9031 fprintf_unfiltered (file
,
9032 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
9033 MIPS_FPU_TYPE (gdbarch
),
9034 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
9035 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
9036 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
9040 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
9043 _initialize_mips_tdep (void)
9045 static struct cmd_list_element
*mipsfpulist
= NULL
;
9046 struct cmd_list_element
*c
;
9048 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
9049 if (MIPS_ABI_LAST
+ 1
9050 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
9051 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
9053 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
9055 mips_pdr_data
= register_objfile_data ();
9057 /* Create feature sets with the appropriate properties. The values
9058 are not important. */
9059 mips_tdesc_gp32
= allocate_target_description ();
9060 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
9062 mips_tdesc_gp64
= allocate_target_description ();
9063 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
9065 /* Add root prefix command for all "set mips"/"show mips" commands. */
9066 add_prefix_cmd ("mips", no_class
, set_mips_command
,
9067 _("Various MIPS specific commands."),
9068 &setmipscmdlist
, "set mips ", 0, &setlist
);
9070 add_prefix_cmd ("mips", no_class
, show_mips_command
,
9071 _("Various MIPS specific commands."),
9072 &showmipscmdlist
, "show mips ", 0, &showlist
);
9074 /* Allow the user to override the ABI. */
9075 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
9076 &mips_abi_string
, _("\
9077 Set the MIPS ABI used by this program."), _("\
9078 Show the MIPS ABI used by this program."), _("\
9079 This option can be set to one of:\n\
9080 auto - the default ABI associated with the current binary\n\
9089 &setmipscmdlist
, &showmipscmdlist
);
9091 /* Allow the user to set the ISA to assume for compressed code if ELF
9092 file flags don't tell or there is no program file selected. This
9093 setting is updated whenever unambiguous ELF file flags are interpreted,
9094 and carried over to subsequent sessions. */
9095 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
9096 &mips_compression_string
, _("\
9097 Set the compressed ISA encoding used by MIPS code."), _("\
9098 Show the compressed ISA encoding used by MIPS code."), _("\
9099 Select the compressed ISA encoding used in functions that have no symbol\n\
9100 information available. The encoding can be set to either of:\n\
9103 and is updated automatically from ELF file flags if available."),
9105 show_mips_compression
,
9106 &setmipscmdlist
, &showmipscmdlist
);
9108 /* Let the user turn off floating point and set the fence post for
9109 heuristic_proc_start. */
9111 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
9112 _("Set use of MIPS floating-point coprocessor."),
9113 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
9114 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
9115 _("Select single-precision MIPS floating-point coprocessor."),
9117 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
9118 _("Select double-precision MIPS floating-point coprocessor."),
9120 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9121 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9122 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9123 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9124 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9125 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9126 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9127 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9128 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9129 _("Select MIPS floating-point coprocessor automatically."),
9131 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9132 _("Show current use of MIPS floating-point coprocessor target."),
9135 /* We really would like to have both "0" and "unlimited" work, but
9136 command.c doesn't deal with that. So make it a var_zinteger
9137 because the user can always use "999999" or some such for unlimited. */
9138 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9139 &heuristic_fence_post
, _("\
9140 Set the distance searched for the start of a function."), _("\
9141 Show the distance searched for the start of a function."), _("\
9142 If you are debugging a stripped executable, GDB needs to search through the\n\
9143 program for the start of a function. This command sets the distance of the\n\
9144 search. The only need to set it is when debugging a stripped executable."),
9145 reinit_frame_cache_sfunc
,
9146 NULL
, /* FIXME: i18n: The distance searched for
9147 the start of a function is %s. */
9148 &setlist
, &showlist
);
9150 /* Allow the user to control whether the upper bits of 64-bit
9151 addresses should be zeroed. */
9152 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9153 &mask_address_var
, _("\
9154 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9155 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9156 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9157 allow GDB to determine the correct value."),
9158 NULL
, show_mask_address
,
9159 &setmipscmdlist
, &showmipscmdlist
);
9161 /* Allow the user to control the size of 32 bit registers within the
9162 raw remote packet. */
9163 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9164 &mips64_transfers_32bit_regs_p
, _("\
9165 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9167 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9169 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9170 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9171 64 bits for others. Use \"off\" to disable compatibility mode"),
9172 set_mips64_transfers_32bit_regs
,
9173 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9174 MIPS target that transfers 32-bit
9175 quantities is %s. */
9176 &setlist
, &showlist
);
9178 /* Debug this files internals. */
9179 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9181 Set mips debugging."), _("\
9182 Show mips debugging."), _("\
9183 When non-zero, mips specific debugging is enabled."),
9185 NULL
, /* FIXME: i18n: Mips debugging is
9187 &setdebuglist
, &showdebuglist
);