1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *const mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 const struct register_alias mips_numeric_register_aliases
[] = {
146 #define R(n) { #n, n }
147 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
148 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
149 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
150 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
154 #ifndef MIPS_DEFAULT_FPU_TYPE
155 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
157 static int mips_fpu_type_auto
= 1;
158 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
160 static int mips_debug
= 0;
162 /* Properties (for struct target_desc) describing the g/G packet
164 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
165 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
167 struct target_desc
*mips_tdesc_gp32
;
168 struct target_desc
*mips_tdesc_gp64
;
170 const struct mips_regnum
*
171 mips_regnum (struct gdbarch
*gdbarch
)
173 return gdbarch_tdep (gdbarch
)->regnum
;
177 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
179 return mips_regnum (gdbarch
)->fp0
+ 12;
182 /* Return 1 if REGNUM refers to a floating-point general register, raw
183 or cooked. Otherwise return 0. */
186 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
188 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
190 return (rawnum
>= mips_regnum (gdbarch
)->fp0
191 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
194 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
196 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
198 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
199 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
201 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
202 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
204 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
206 /* Return the MIPS ABI associated with GDBARCH. */
208 mips_abi (struct gdbarch
*gdbarch
)
210 return gdbarch_tdep (gdbarch
)->mips_abi
;
214 mips_isa_regsize (struct gdbarch
*gdbarch
)
216 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
218 /* If we know how big the registers are, use that size. */
219 if (tdep
->register_size_valid_p
)
220 return tdep
->register_size
;
222 /* Fall back to the previous behavior. */
223 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
224 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
227 /* Return the currently configured (or set) saved register size. */
230 mips_abi_regsize (struct gdbarch
*gdbarch
)
232 switch (mips_abi (gdbarch
))
234 case MIPS_ABI_EABI32
:
240 case MIPS_ABI_EABI64
:
242 case MIPS_ABI_UNKNOWN
:
245 internal_error (__FILE__
, __LINE__
, _("bad switch"));
249 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
250 functions to test, set, or clear bit 0 of addresses. */
253 is_mips16_addr (CORE_ADDR addr
)
259 unmake_mips16_addr (CORE_ADDR addr
)
261 return ((addr
) & ~(CORE_ADDR
) 1);
265 make_mips16_addr (CORE_ADDR addr
)
267 return ((addr
) | (CORE_ADDR
) 1);
270 /* Functions for setting and testing a bit in a minimal symbol that
271 marks it as 16-bit function. The MSB of the minimal symbol's
272 "info" field is used for this purpose.
274 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
275 i.e. refers to a 16-bit function, and sets a "special" bit in a
276 minimal symbol to mark it as a 16-bit function
278 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
281 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
283 if (ELF_ST_IS_MIPS16 (((elf_symbol_type
*)
284 (sym
))->internal_elf_sym
.st_other
))
286 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
291 msymbol_is_special (struct minimal_symbol
*msym
)
293 return MSYMBOL_TARGET_FLAG_1 (msym
);
296 /* XFER a value from the big/little/left end of the register.
297 Depending on the size of the value it might occupy the entire
298 register or just part of it. Make an allowance for this, aligning
299 things accordingly. */
302 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
303 int reg_num
, int length
,
304 enum bfd_endian endian
, gdb_byte
*in
,
305 const gdb_byte
*out
, int buf_offset
)
309 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
310 /* Need to transfer the left or right part of the register, based on
311 the targets byte order. */
315 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
317 case BFD_ENDIAN_LITTLE
:
320 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
324 internal_error (__FILE__
, __LINE__
, _("bad switch"));
327 fprintf_unfiltered (gdb_stderr
,
328 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
329 reg_num
, reg_offset
, buf_offset
, length
);
330 if (mips_debug
&& out
!= NULL
)
333 fprintf_unfiltered (gdb_stdlog
, "out ");
334 for (i
= 0; i
< length
; i
++)
335 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
338 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
341 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
343 if (mips_debug
&& in
!= NULL
)
346 fprintf_unfiltered (gdb_stdlog
, "in ");
347 for (i
= 0; i
< length
; i
++)
348 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
351 fprintf_unfiltered (gdb_stdlog
, "\n");
354 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
355 compatiblity mode. A return value of 1 means that we have
356 physical 64-bit registers, but should treat them as 32-bit registers. */
359 mips2_fp_compat (struct frame_info
*frame
)
361 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
362 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
364 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
368 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
369 in all the places we deal with FP registers. PR gdb/413. */
370 /* Otherwise check the FR bit in the status register - it controls
371 the FP compatiblity mode. If it is clear we are in compatibility
373 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
380 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
382 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
384 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
386 /* The list of available "set mips " and "show mips " commands. */
388 static struct cmd_list_element
*setmipscmdlist
= NULL
;
389 static struct cmd_list_element
*showmipscmdlist
= NULL
;
391 /* Integer registers 0 thru 31 are handled explicitly by
392 mips_register_name(). Processor specific registers 32 and above
393 are listed in the following tables. */
396 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
400 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
401 "sr", "lo", "hi", "bad", "cause", "pc",
402 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
403 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
404 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
405 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
409 /* Names of IDT R3041 registers. */
411 static const char *mips_r3041_reg_names
[] = {
412 "sr", "lo", "hi", "bad", "cause", "pc",
413 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
414 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
415 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
416 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
417 "fsr", "fir", "", /*"fp" */ "",
418 "", "", "bus", "ccfg", "", "", "", "",
419 "", "", "port", "cmp", "", "", "epc", "prid",
422 /* Names of tx39 registers. */
424 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
425 "sr", "lo", "hi", "bad", "cause", "pc",
426 "", "", "", "", "", "", "", "",
427 "", "", "", "", "", "", "", "",
428 "", "", "", "", "", "", "", "",
429 "", "", "", "", "", "", "", "",
431 "", "", "", "", "", "", "", "",
432 "", "", "config", "cache", "debug", "depc", "epc",
435 /* Names of IRIX registers. */
436 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
437 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
438 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
439 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
440 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
441 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
444 /* Names of registers with Linux kernels. */
445 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
446 "sr", "lo", "hi", "bad", "cause", "pc",
447 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
448 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
449 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
450 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
455 /* Return the name of the register corresponding to REGNO. */
457 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
459 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
460 /* GPR names for all ABIs other than n32/n64. */
461 static char *mips_gpr_names
[] = {
462 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
463 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
464 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
465 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
468 /* GPR names for n32 and n64 ABIs. */
469 static char *mips_n32_n64_gpr_names
[] = {
470 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
471 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
472 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
473 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
476 enum mips_abi abi
= mips_abi (gdbarch
);
478 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
479 but then don't make the raw register names visible. This (upper)
480 range of user visible register numbers are the pseudo-registers.
482 This approach was adopted accommodate the following scenario:
483 It is possible to debug a 64-bit device using a 32-bit
484 programming model. In such instances, the raw registers are
485 configured to be 64-bits wide, while the pseudo registers are
486 configured to be 32-bits wide. The registers that the user
487 sees - the pseudo registers - match the users expectations
488 given the programming model being used. */
489 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
490 if (regno
< gdbarch_num_regs (gdbarch
))
493 /* The MIPS integer registers are always mapped from 0 to 31. The
494 names of the registers (which reflects the conventions regarding
495 register use) vary depending on the ABI. */
496 if (0 <= rawnum
&& rawnum
< 32)
498 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
499 return mips_n32_n64_gpr_names
[rawnum
];
501 return mips_gpr_names
[rawnum
];
503 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
504 return tdesc_register_name (gdbarch
, rawnum
);
505 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
507 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
508 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
509 return tdep
->mips_processor_reg_names
[rawnum
- 32];
513 internal_error (__FILE__
, __LINE__
,
514 _("mips_register_name: bad register number %d"), rawnum
);
517 /* Return the groups that a MIPS register can be categorised into. */
520 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
521 struct reggroup
*reggroup
)
526 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
527 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
528 if (reggroup
== all_reggroup
)
530 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
531 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
532 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
533 (gdbarch), as not all architectures are multi-arch. */
534 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
535 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
536 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
538 if (reggroup
== float_reggroup
)
539 return float_p
&& pseudo
;
540 if (reggroup
== vector_reggroup
)
541 return vector_p
&& pseudo
;
542 if (reggroup
== general_reggroup
)
543 return (!vector_p
&& !float_p
) && pseudo
;
544 /* Save the pseudo registers. Need to make certain that any code
545 extracting register values from a saved register cache also uses
547 if (reggroup
== save_reggroup
)
548 return raw_p
&& pseudo
;
549 /* Restore the same pseudo register. */
550 if (reggroup
== restore_reggroup
)
551 return raw_p
&& pseudo
;
555 /* Return the groups that a MIPS register can be categorised into.
556 This version is only used if we have a target description which
557 describes real registers (and their groups). */
560 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
561 struct reggroup
*reggroup
)
563 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
564 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
567 /* Only save, restore, and display the pseudo registers. Need to
568 make certain that any code extracting register values from a
569 saved register cache also uses pseudo registers.
571 Note: saving and restoring the pseudo registers is slightly
572 strange; if we have 64 bits, we should save and restore all
573 64 bits. But this is hard and has little benefit. */
577 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
581 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
584 /* Map the symbol table registers which live in the range [1 *
585 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
586 registers. Take care of alignment and size problems. */
588 static enum register_status
589 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
590 int cookednum
, gdb_byte
*buf
)
592 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
593 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
594 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
595 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
596 return regcache_raw_read (regcache
, rawnum
, buf
);
597 else if (register_size (gdbarch
, rawnum
) >
598 register_size (gdbarch
, cookednum
))
600 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
601 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
604 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
606 enum register_status status
;
608 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
609 if (status
== REG_VALID
)
610 store_signed_integer (buf
, 4, byte_order
, regval
);
615 internal_error (__FILE__
, __LINE__
, _("bad register size"));
619 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
620 struct regcache
*regcache
, int cookednum
,
623 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
624 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
625 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
626 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
627 regcache_raw_write (regcache
, rawnum
, buf
);
628 else if (register_size (gdbarch
, rawnum
) >
629 register_size (gdbarch
, cookednum
))
631 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
632 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
635 /* Sign extend the shortened version of the register prior
636 to placing it in the raw register. This is required for
637 some mips64 parts in order to avoid unpredictable behavior. */
638 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
639 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
640 regcache_raw_write_signed (regcache
, rawnum
, regval
);
644 internal_error (__FILE__
, __LINE__
, _("bad register size"));
648 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
649 struct agent_expr
*ax
, int reg
)
651 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
652 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
653 && reg
< 2 * gdbarch_num_regs (gdbarch
));
655 ax_reg_mask (ax
, rawnum
);
661 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
662 struct agent_expr
*ax
, int reg
)
664 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
665 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
666 && reg
< 2 * gdbarch_num_regs (gdbarch
));
667 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
671 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
673 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
674 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
677 ax_simple (ax
, aop_lsh
);
680 ax_simple (ax
, aop_rsh_signed
);
684 internal_error (__FILE__
, __LINE__
, _("bad register size"));
689 /* Table to translate MIPS16 register field to actual register number. */
690 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
692 /* Heuristic_proc_start may hunt through the text section for a long
693 time across a 2400 baud serial line. Allows the user to limit this
696 static unsigned int heuristic_fence_post
= 0;
698 /* Number of bytes of storage in the actual machine representation for
699 register N. NOTE: This defines the pseudo register type so need to
700 rebuild the architecture vector. */
702 static int mips64_transfers_32bit_regs_p
= 0;
705 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
706 struct cmd_list_element
*c
)
708 struct gdbarch_info info
;
709 gdbarch_info_init (&info
);
710 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
711 instead of relying on globals. Doing that would let generic code
712 handle the search for this specific architecture. */
713 if (!gdbarch_update_p (info
))
715 mips64_transfers_32bit_regs_p
= 0;
716 error (_("32-bit compatibility mode not supported"));
720 /* Convert to/from a register and the corresponding memory value. */
722 /* This predicate tests for the case of an 8 byte floating point
723 value that is being transferred to or from a pair of floating point
724 registers each of which are (or are considered to be) only 4 bytes
727 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
730 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
731 && register_size (gdbarch
, regnum
) == 4
732 && mips_float_register_p (gdbarch
, regnum
)
733 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
736 /* This predicate tests for the case of a value of less than 8
737 bytes in width that is being transfered to or from an 8 byte
738 general purpose register. */
740 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
743 int num_regs
= gdbarch_num_regs (gdbarch
);
745 return (register_size (gdbarch
, regnum
) == 8
746 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
747 && TYPE_LENGTH (type
) < 8);
751 mips_convert_register_p (struct gdbarch
*gdbarch
,
752 int regnum
, struct type
*type
)
754 return mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
755 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
);
759 mips_register_to_value (struct frame_info
*frame
, int regnum
,
760 struct type
*type
, gdb_byte
*to
,
761 int *optimizedp
, int *unavailablep
)
763 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
765 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
767 get_frame_register (frame
, regnum
+ 0, to
+ 4);
768 get_frame_register (frame
, regnum
+ 1, to
+ 0);
770 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
771 optimizedp
, unavailablep
))
774 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
775 optimizedp
, unavailablep
))
777 *optimizedp
= *unavailablep
= 0;
780 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
782 int len
= TYPE_LENGTH (type
);
785 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
786 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
787 optimizedp
, unavailablep
))
790 *optimizedp
= *unavailablep
= 0;
795 internal_error (__FILE__
, __LINE__
,
796 _("mips_register_to_value: unrecognized case"));
801 mips_value_to_register (struct frame_info
*frame
, int regnum
,
802 struct type
*type
, const gdb_byte
*from
)
804 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
806 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
808 put_frame_register (frame
, regnum
+ 0, from
+ 4);
809 put_frame_register (frame
, regnum
+ 1, from
+ 0);
811 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
814 int len
= TYPE_LENGTH (type
);
816 /* Sign extend values, irrespective of type, that are stored to
817 a 64-bit general purpose register. (32-bit unsigned values
818 are stored as signed quantities within a 64-bit register.
819 When performing an operation, in compiled code, that combines
820 a 32-bit unsigned value with a signed 64-bit value, a type
821 conversion is first performed that zeroes out the high 32 bits.) */
822 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
825 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
827 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
828 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
829 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
833 if (from
[len
-1] & 0x80)
834 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
836 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
837 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
838 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
843 internal_error (__FILE__
, __LINE__
,
844 _("mips_value_to_register: unrecognized case"));
848 /* Return the GDB type object for the "standard" data type of data in
852 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
854 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
855 if (mips_float_register_p (gdbarch
, regnum
))
857 /* The floating-point registers raw, or cooked, always match
858 mips_isa_regsize(), and also map 1:1, byte for byte. */
859 if (mips_isa_regsize (gdbarch
) == 4)
860 return builtin_type (gdbarch
)->builtin_float
;
862 return builtin_type (gdbarch
)->builtin_double
;
864 else if (regnum
< gdbarch_num_regs (gdbarch
))
866 /* The raw or ISA registers. These are all sized according to
868 if (mips_isa_regsize (gdbarch
) == 4)
869 return builtin_type (gdbarch
)->builtin_int32
;
871 return builtin_type (gdbarch
)->builtin_int64
;
875 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
877 /* The cooked or ABI registers. These are sized according to
878 the ABI (with a few complications). */
879 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
880 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
881 return builtin_type (gdbarch
)->builtin_int32
;
882 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
883 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
884 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
885 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
886 /* The pseudo/cooked view of the embedded registers is always
887 32-bit. The raw view is handled below. */
888 return builtin_type (gdbarch
)->builtin_int32
;
889 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
890 /* The target, while possibly using a 64-bit register buffer,
891 is only transfering 32-bits of each integer register.
892 Reflect this in the cooked/pseudo (ABI) register value. */
893 return builtin_type (gdbarch
)->builtin_int32
;
894 else if (mips_abi_regsize (gdbarch
) == 4)
895 /* The ABI is restricted to 32-bit registers (the ISA could be
897 return builtin_type (gdbarch
)->builtin_int32
;
900 return builtin_type (gdbarch
)->builtin_int64
;
904 /* Return the GDB type for the pseudo register REGNUM, which is the
905 ABI-level view. This function is only called if there is a target
906 description which includes registers, so we know precisely the
907 types of hardware registers. */
910 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
912 const int num_regs
= gdbarch_num_regs (gdbarch
);
913 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
914 int rawnum
= regnum
% num_regs
;
915 struct type
*rawtype
;
917 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
919 /* Absent registers are still absent. */
920 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
921 if (TYPE_LENGTH (rawtype
) == 0)
924 if (rawnum
>= mips_regnum (gdbarch
)->fp0
925 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32)
926 /* Present the floating point registers however the hardware did;
927 do not try to convert between FPU layouts. */
930 /* Use pointer types for registers if we can. For n32 we can not,
931 since we do not have a 64-bit pointer type. */
932 if (mips_abi_regsize (gdbarch
)
933 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
935 if (rawnum
== MIPS_SP_REGNUM
936 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
937 return builtin_type (gdbarch
)->builtin_data_ptr
;
938 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
939 return builtin_type (gdbarch
)->builtin_func_ptr
;
942 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
943 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
944 || rawnum
== mips_regnum (gdbarch
)->lo
945 || rawnum
== mips_regnum (gdbarch
)->hi
946 || rawnum
== mips_regnum (gdbarch
)->badvaddr
947 || rawnum
== mips_regnum (gdbarch
)->cause
948 || rawnum
== mips_regnum (gdbarch
)->pc
949 || (mips_regnum (gdbarch
)->dspacc
!= -1
950 && rawnum
>= mips_regnum (gdbarch
)->dspacc
951 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
952 return builtin_type (gdbarch
)->builtin_int32
;
954 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
955 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
956 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
957 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
959 /* The pseudo/cooked view of embedded registers is always
960 32-bit, even if the target transfers 64-bit values for them.
961 New targets relying on XML descriptions should only transfer
962 the necessary 32 bits, but older versions of GDB expected 64,
963 so allow the target to provide 64 bits without interfering
964 with the displayed type. */
965 return builtin_type (gdbarch
)->builtin_int32
;
968 /* For all other registers, pass through the hardware type. */
972 /* Should the upper word of 64-bit addresses be zeroed? */
973 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
976 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
978 switch (mask_address_var
)
980 case AUTO_BOOLEAN_TRUE
:
982 case AUTO_BOOLEAN_FALSE
:
985 case AUTO_BOOLEAN_AUTO
:
986 return tdep
->default_mask_address_p
;
988 internal_error (__FILE__
, __LINE__
,
989 _("mips_mask_address_p: bad switch"));
995 show_mask_address (struct ui_file
*file
, int from_tty
,
996 struct cmd_list_element
*c
, const char *value
)
998 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
1000 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1001 switch (mask_address_var
)
1003 case AUTO_BOOLEAN_TRUE
:
1004 printf_filtered ("The 32 bit mips address mask is enabled\n");
1006 case AUTO_BOOLEAN_FALSE
:
1007 printf_filtered ("The 32 bit mips address mask is disabled\n");
1009 case AUTO_BOOLEAN_AUTO
:
1011 ("The 32 bit address mask is set automatically. Currently %s\n",
1012 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1015 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1020 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1023 mips_pc_is_mips16 (CORE_ADDR memaddr
)
1025 struct minimal_symbol
*sym
;
1027 /* A flag indicating that this is a MIPS16 function is stored by
1028 elfread.c in the high bit of the info field. Use this to decide
1029 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of
1030 the address is set, assume this is a MIPS16 address. */
1031 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1033 return msymbol_is_special (sym
);
1035 return is_mips16_addr (memaddr
);
1038 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1040 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1041 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1042 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1043 static const char mips_str_call_stub
[] = "__call_stub_";
1044 static const char mips_str_fn_stub
[] = "__fn_stub_";
1046 /* This is used as a PIC thunk prefix. */
1048 static const char mips_str_pic
[] = ".pic.";
1050 /* Return non-zero if the PC is inside a call thunk (aka stub or
1051 trampoline) that should be treated as a temporary frame. */
1054 mips_in_frame_stub (CORE_ADDR pc
)
1056 CORE_ADDR start_addr
;
1059 /* Find the starting address of the function containing the PC. */
1060 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1063 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1064 if (strncmp (name
, mips_str_mips16_call_stub
,
1065 strlen (mips_str_mips16_call_stub
)) == 0)
1067 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1068 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1070 /* If the PC is in __fn_stub_*, this is a call stub. */
1071 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1074 return 0; /* Not a stub. */
1077 /* MIPS believes that the PC has a sign extended value. Perhaps the
1078 all registers should be sign extended for simplicity? */
1081 mips_read_pc (struct regcache
*regcache
)
1083 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1086 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1087 if (is_mips16_addr (pc
))
1088 pc
= unmake_mips16_addr (pc
);
1093 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1097 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1098 if (is_mips16_addr (pc
))
1099 pc
= unmake_mips16_addr (pc
);
1100 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1101 intermediate frames. In this case we can get the caller's address
1102 from $ra, or if $ra contains an address within a thunk as well, then
1103 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1104 and thus the caller's address is in $s2. */
1105 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1107 pc
= frame_unwind_register_signed
1108 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1109 if (is_mips16_addr (pc
))
1110 pc
= unmake_mips16_addr (pc
);
1111 if (mips_in_frame_stub (pc
))
1113 pc
= frame_unwind_register_signed
1114 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1115 if (is_mips16_addr (pc
))
1116 pc
= unmake_mips16_addr (pc
);
1123 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1125 return frame_unwind_register_signed
1126 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1129 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1130 dummy frame. The frame ID's base needs to match the TOS value
1131 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1134 static struct frame_id
1135 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1137 return frame_id_build
1138 (get_frame_register_signed (this_frame
,
1139 gdbarch_num_regs (gdbarch
)
1141 get_frame_pc (this_frame
));
1144 /* Implement the "write_pc" gdbarch method. */
1147 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1149 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1151 if (mips_pc_is_mips16 (pc
))
1152 regcache_cooked_write_unsigned (regcache
, regnum
, make_mips16_addr (pc
));
1154 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1157 /* Fetch and return instruction from the specified location. If the PC
1158 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
1161 mips_fetch_instruction (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1163 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1164 gdb_byte buf
[MIPS_INSN32_SIZE
];
1168 if (mips_pc_is_mips16 (addr
))
1170 instlen
= MIPS_INSN16_SIZE
;
1171 addr
= unmake_mips16_addr (addr
);
1174 instlen
= MIPS_INSN32_SIZE
;
1175 status
= target_read_memory (addr
, buf
, instlen
);
1177 memory_error (status
, addr
);
1178 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1181 /* These are the fields of 32 bit mips instructions. */
1182 #define mips32_op(x) (x >> 26)
1183 #define itype_op(x) (x >> 26)
1184 #define itype_rs(x) ((x >> 21) & 0x1f)
1185 #define itype_rt(x) ((x >> 16) & 0x1f)
1186 #define itype_immediate(x) (x & 0xffff)
1188 #define jtype_op(x) (x >> 26)
1189 #define jtype_target(x) (x & 0x03ffffff)
1191 #define rtype_op(x) (x >> 26)
1192 #define rtype_rs(x) ((x >> 21) & 0x1f)
1193 #define rtype_rt(x) ((x >> 16) & 0x1f)
1194 #define rtype_rd(x) ((x >> 11) & 0x1f)
1195 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1196 #define rtype_funct(x) (x & 0x3f)
1199 mips32_relative_offset (ULONGEST inst
)
1201 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1204 /* Determine the address of the next instruction executed after the INST
1205 floating condition branch instruction at PC. COUNT specifies the
1206 number of the floating condition bits tested by the branch. */
1209 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1210 ULONGEST inst
, CORE_ADDR pc
, int count
)
1212 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1213 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1214 int tf
= itype_rt (inst
) & 1;
1215 int mask
= (1 << count
) - 1;
1220 /* No way to handle; it'll most likely trap anyway. */
1223 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1224 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1226 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1227 pc
+= mips32_relative_offset (inst
);
1234 /* Determine where to set a single step breakpoint while considering
1235 branch prediction. */
1237 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1239 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1242 inst
= mips_fetch_instruction (gdbarch
, pc
);
1243 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1246 if (itype_op (inst
) >> 2 == 5)
1247 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1249 op
= (itype_op (inst
) & 0x03);
1259 goto greater_branch
;
1264 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1265 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1266 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1267 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 9
1268 && (itype_rt (inst
) & 2) == 0)
1269 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1270 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1271 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 10
1272 && (itype_rt (inst
) & 2) == 0)
1273 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1274 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1275 else if (itype_op (inst
) == 29)
1277 /* The new PC will be alternate mode. */
1281 reg
= jtype_target (inst
) << 2;
1282 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1283 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1286 pc
+= 4; /* Not a branch, next instruction is easy. */
1289 { /* This gets way messy. */
1291 /* Further subdivide into SPECIAL, REGIMM and other. */
1292 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1294 case 0: /* SPECIAL */
1295 op
= rtype_funct (inst
);
1300 /* Set PC to that address. */
1301 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1303 case 12: /* SYSCALL */
1305 struct gdbarch_tdep
*tdep
;
1307 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1308 if (tdep
->syscall_next_pc
!= NULL
)
1309 pc
= tdep
->syscall_next_pc (frame
);
1318 break; /* end SPECIAL */
1319 case 1: /* REGIMM */
1321 op
= itype_rt (inst
); /* branch condition */
1326 case 16: /* BLTZAL */
1327 case 18: /* BLTZALL */
1329 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1330 pc
+= mips32_relative_offset (inst
) + 4;
1332 pc
+= 8; /* after the delay slot */
1336 case 17: /* BGEZAL */
1337 case 19: /* BGEZALL */
1338 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1339 pc
+= mips32_relative_offset (inst
) + 4;
1341 pc
+= 8; /* after the delay slot */
1343 case 0x1c: /* BPOSGE32 */
1344 case 0x1e: /* BPOSGE64 */
1346 if (itype_rs (inst
) == 0)
1348 unsigned int pos
= (op
& 2) ? 64 : 32;
1349 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1352 /* No way to handle; it'll most likely trap anyway. */
1355 if ((get_frame_register_unsigned (frame
,
1356 dspctl
) & 0x7f) >= pos
)
1357 pc
+= mips32_relative_offset (inst
);
1362 /* All of the other instructions in the REGIMM category */
1367 break; /* end REGIMM */
1372 reg
= jtype_target (inst
) << 2;
1373 /* Upper four bits get never changed... */
1374 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1377 case 4: /* BEQ, BEQL */
1379 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1380 get_frame_register_signed (frame
, itype_rt (inst
)))
1381 pc
+= mips32_relative_offset (inst
) + 4;
1385 case 5: /* BNE, BNEL */
1387 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1388 get_frame_register_signed (frame
, itype_rt (inst
)))
1389 pc
+= mips32_relative_offset (inst
) + 4;
1393 case 6: /* BLEZ, BLEZL */
1394 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1395 pc
+= mips32_relative_offset (inst
) + 4;
1401 greater_branch
: /* BGTZ, BGTZL */
1402 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1403 pc
+= mips32_relative_offset (inst
) + 4;
1410 } /* mips32_next_pc */
1412 /* Decoding the next place to set a breakpoint is irregular for the
1413 mips 16 variant, but fortunately, there fewer instructions. We have
1414 to cope ith extensions for 16 bit instructions and a pair of actual
1415 32 bit instructions. We dont want to set a single step instruction
1416 on the extend instruction either. */
1418 /* Lots of mips16 instruction formats */
1419 /* Predicting jumps requires itype,ritype,i8type
1420 and their extensions extItype,extritype,extI8type. */
1421 enum mips16_inst_fmts
1423 itype
, /* 0 immediate 5,10 */
1424 ritype
, /* 1 5,3,8 */
1425 rrtype
, /* 2 5,3,3,5 */
1426 rritype
, /* 3 5,3,3,5 */
1427 rrrtype
, /* 4 5,3,3,3,2 */
1428 rriatype
, /* 5 5,3,3,1,4 */
1429 shifttype
, /* 6 5,3,3,3,2 */
1430 i8type
, /* 7 5,3,8 */
1431 i8movtype
, /* 8 5,3,3,5 */
1432 i8mov32rtype
, /* 9 5,3,5,3 */
1433 i64type
, /* 10 5,3,8 */
1434 ri64type
, /* 11 5,3,3,5 */
1435 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1436 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1437 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1438 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1439 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1440 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1441 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1442 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1443 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1444 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1446 /* I am heaping all the fields of the formats into one structure and
1447 then, only the fields which are involved in instruction extension. */
1451 unsigned int regx
; /* Function in i8 type. */
1456 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1457 for the bits which make up the immediate extension. */
1460 extended_offset (unsigned int extension
)
1464 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1466 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1468 value
|= extension
& 0x1f; /* Extract 4:0. */
1473 /* Only call this function if you know that this is an extendable
1474 instruction. It won't malfunction, but why make excess remote memory
1475 references? If the immediate operands get sign extended or something,
1476 do it after the extension is performed. */
1477 /* FIXME: Every one of these cases needs to worry about sign extension
1478 when the offset is to be used in relative addressing. */
1481 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1483 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1485 pc
&= 0xfffffffe; /* Clear the low order bit. */
1486 target_read_memory (pc
, buf
, 2);
1487 return extract_unsigned_integer (buf
, 2, byte_order
);
1491 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1492 unsigned int extension
,
1494 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1499 switch (insn_format
)
1506 value
= extended_offset ((extension
<< 16) | inst
);
1507 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1511 value
= inst
& 0x7ff;
1512 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
1521 { /* A register identifier and an offset. */
1522 /* Most of the fields are the same as I type but the
1523 immediate value is of a different length. */
1527 value
= extended_offset ((extension
<< 16) | inst
);
1528 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
1532 value
= inst
& 0xff; /* 8 bits */
1533 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
1536 regx
= (inst
>> 8) & 0x07; /* i8 funct */
1542 unsigned long value
;
1543 unsigned int nexthalf
;
1544 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1545 value
= value
<< 16;
1546 nexthalf
= mips_fetch_instruction (gdbarch
, pc
+ 2); /* low bit
1555 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1557 upk
->offset
= offset
;
1564 add_offset_16 (CORE_ADDR pc
, int offset
)
1566 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1570 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1571 unsigned int extension
, unsigned int insn
)
1573 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1574 int op
= (insn
>> 11);
1577 case 2: /* Branch */
1579 struct upk_mips16 upk
;
1580 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
1581 pc
+= (upk
.offset
<< 1) + 2;
1584 case 3: /* JAL , JALX - Watch out, these are 32 bit
1587 struct upk_mips16 upk
;
1588 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
1589 pc
= add_offset_16 (pc
, upk
.offset
);
1590 if ((insn
>> 10) & 0x01) /* Exchange mode */
1591 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
1598 struct upk_mips16 upk
;
1600 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1601 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1603 pc
+= (upk
.offset
<< 1) + 2;
1610 struct upk_mips16 upk
;
1612 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
1613 reg
= get_frame_register_signed (frame
, mips16_to_32_reg
[upk
.regx
]);
1615 pc
+= (upk
.offset
<< 1) + 2;
1620 case 12: /* I8 Formats btez btnez */
1622 struct upk_mips16 upk
;
1624 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
1625 /* upk.regx contains the opcode */
1626 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1627 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1628 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1629 /* pc = add_offset_16(pc,upk.offset) ; */
1630 pc
+= (upk
.offset
<< 1) + 2;
1635 case 29: /* RR Formats JR, JALR, JALR-RA */
1637 struct upk_mips16 upk
;
1638 /* upk.fmt = rrtype; */
1643 upk
.regx
= (insn
>> 8) & 0x07;
1644 upk
.regy
= (insn
>> 5) & 0x07;
1645 if ((upk
.regy
& 1) == 0)
1646 reg
= mips16_to_32_reg
[upk
.regx
];
1648 reg
= 31; /* Function return instruction. */
1649 pc
= get_frame_register_signed (frame
, reg
);
1656 /* This is an instruction extension. Fetch the real instruction
1657 (which follows the extension) and decode things based on
1661 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
1662 fetch_mips_16 (gdbarch
, pc
));
1675 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1677 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1678 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
1679 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1682 /* The mips_next_pc function supports single_step when the remote
1683 target monitor or stub is not developed enough to do a single_step.
1684 It works by decoding the current instruction and predicting where a
1685 branch will go. This isnt hard because all the data is available.
1686 The MIPS32 and MIPS16 variants are quite different. */
1688 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1690 if (mips_pc_is_mips16 (pc
))
1691 return mips16_next_pc (frame
, pc
);
1693 return mips32_next_pc (frame
, pc
);
1696 struct mips_frame_cache
1699 struct trad_frame_saved_reg
*saved_regs
;
1702 /* Set a register's saved stack address in temp_saved_regs. If an
1703 address has already been set for this register, do nothing; this
1704 way we will only recognize the first save of a given register in a
1707 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1708 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1709 Strictly speaking, only the second range is used as it is only second
1710 range (the ABI instead of ISA registers) that comes into play when finding
1711 saved registers in a frame. */
1714 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1715 int regnum
, CORE_ADDR offset
)
1717 if (this_cache
!= NULL
1718 && this_cache
->saved_regs
[regnum
].addr
== -1)
1720 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1722 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1728 /* Fetch the immediate value from a MIPS16 instruction.
1729 If the previous instruction was an EXTEND, use it to extend
1730 the upper bits of the immediate value. This is a helper function
1731 for mips16_scan_prologue. */
1734 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1735 unsigned short inst
, /* current instruction */
1736 int nbits
, /* number of bits in imm field */
1737 int scale
, /* scale factor to be applied to imm */
1738 int is_signed
) /* is the imm field signed? */
1742 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1744 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1745 if (offset
& 0x8000) /* check for negative extend */
1746 offset
= 0 - (0x10000 - (offset
& 0xffff));
1747 return offset
| (inst
& 0x1f);
1751 int max_imm
= 1 << nbits
;
1752 int mask
= max_imm
- 1;
1753 int sign_bit
= max_imm
>> 1;
1755 offset
= inst
& mask
;
1756 if (is_signed
&& (offset
& sign_bit
))
1757 offset
= 0 - (max_imm
- offset
);
1758 return offset
* scale
;
1763 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1764 the associated FRAME_CACHE if not null.
1765 Return the address of the first instruction past the prologue. */
1768 mips16_scan_prologue (struct gdbarch
*gdbarch
,
1769 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1770 struct frame_info
*this_frame
,
1771 struct mips_frame_cache
*this_cache
)
1774 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
1776 long frame_offset
= 0; /* Size of stack frame. */
1777 long frame_adjust
= 0; /* Offset of FP from SP. */
1778 int frame_reg
= MIPS_SP_REGNUM
;
1779 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
1780 unsigned inst
= 0; /* current instruction */
1781 unsigned entry_inst
= 0; /* the entry instruction */
1782 unsigned save_inst
= 0; /* the save instruction */
1785 int extend_bytes
= 0;
1786 int prev_extend_bytes
;
1787 CORE_ADDR end_prologue_addr
= 0;
1789 /* Can be called when there's no process, and hence when there's no
1791 if (this_frame
!= NULL
)
1792 sp
= get_frame_register_signed (this_frame
,
1793 gdbarch_num_regs (gdbarch
)
1798 if (limit_pc
> start_pc
+ 200)
1799 limit_pc
= start_pc
+ 200;
1801 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1803 /* Save the previous instruction. If it's an EXTEND, we'll extract
1804 the immediate offset extension from it in mips16_get_imm. */
1807 /* Fetch and decode the instruction. */
1808 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, cur_pc
);
1810 /* Normally we ignore extend instructions. However, if it is
1811 not followed by a valid prologue instruction, then this
1812 instruction is not part of the prologue either. We must
1813 remember in this case to adjust the end_prologue_addr back
1815 if ((inst
& 0xf800) == 0xf000) /* extend */
1817 extend_bytes
= MIPS_INSN16_SIZE
;
1821 prev_extend_bytes
= extend_bytes
;
1824 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1825 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1827 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1828 if (offset
< 0) /* Negative stack adjustment? */
1829 frame_offset
-= offset
;
1831 /* Exit loop if a positive stack adjustment is found, which
1832 usually means that the stack cleanup code in the function
1833 epilogue is reached. */
1836 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1838 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1839 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1840 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1842 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1844 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1845 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1846 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1848 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1850 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1851 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1853 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1855 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1856 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1858 else if (inst
== 0x673d) /* move $s1, $sp */
1863 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1865 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1866 frame_addr
= sp
+ offset
;
1868 frame_adjust
= offset
;
1870 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1872 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1873 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1874 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1876 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1878 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1879 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1880 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1882 else if ((inst
& 0xf81f) == 0xe809
1883 && (inst
& 0x700) != 0x700) /* entry */
1884 entry_inst
= inst
; /* Save for later processing. */
1885 else if ((inst
& 0xff80) == 0x6480) /* save */
1887 save_inst
= inst
; /* Save for later processing. */
1888 if (prev_extend_bytes
) /* extend */
1889 save_inst
|= prev_inst
<< 16;
1891 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1892 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1893 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1895 /* This instruction is part of the prologue, but we don't
1896 need to do anything special to handle it. */
1900 /* This instruction is not an instruction typically found
1901 in a prologue, so we must have reached the end of the
1903 if (end_prologue_addr
== 0)
1904 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1908 /* The entry instruction is typically the first instruction in a function,
1909 and it stores registers at offsets relative to the value of the old SP
1910 (before the prologue). But the value of the sp parameter to this
1911 function is the new SP (after the prologue has been executed). So we
1912 can't calculate those offsets until we've seen the entire prologue,
1913 and can calculate what the old SP must have been. */
1914 if (entry_inst
!= 0)
1916 int areg_count
= (entry_inst
>> 8) & 7;
1917 int sreg_count
= (entry_inst
>> 6) & 3;
1919 /* The entry instruction always subtracts 32 from the SP. */
1922 /* Now we can calculate what the SP must have been at the
1923 start of the function prologue. */
1926 /* Check if a0-a3 were saved in the caller's argument save area. */
1927 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1929 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1930 offset
+= mips_abi_regsize (gdbarch
);
1933 /* Check if the ra register was pushed on the stack. */
1935 if (entry_inst
& 0x20)
1937 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1938 offset
-= mips_abi_regsize (gdbarch
);
1941 /* Check if the s0 and s1 registers were pushed on the stack. */
1942 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1944 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1945 offset
-= mips_abi_regsize (gdbarch
);
1949 /* The SAVE instruction is similar to ENTRY, except that defined by the
1950 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1951 size of the frame is specified as an immediate field of instruction
1952 and an extended variation exists which lets additional registers and
1953 frame space to be specified. The instruction always treats registers
1954 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1955 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1957 static int args_table
[16] = {
1958 0, 0, 0, 0, 1, 1, 1, 1,
1959 2, 2, 2, 0, 3, 3, 4, -1,
1961 static int astatic_table
[16] = {
1962 0, 1, 2, 3, 0, 1, 2, 3,
1963 0, 1, 2, 4, 0, 1, 0, -1,
1965 int aregs
= (save_inst
>> 16) & 0xf;
1966 int xsregs
= (save_inst
>> 24) & 0x7;
1967 int args
= args_table
[aregs
];
1968 int astatic
= astatic_table
[aregs
];
1973 warning (_("Invalid number of argument registers encoded in SAVE."));
1978 warning (_("Invalid number of static registers encoded in SAVE."));
1982 /* For standard SAVE the frame size of 0 means 128. */
1983 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1984 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1987 frame_offset
+= frame_size
;
1989 /* Now we can calculate what the SP must have been at the
1990 start of the function prologue. */
1993 /* Check if A0-A3 were saved in the caller's argument save area. */
1994 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1996 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1997 offset
+= mips_abi_regsize (gdbarch
);
2002 /* Check if the RA register was pushed on the stack. */
2003 if (save_inst
& 0x40)
2005 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2006 offset
-= mips_abi_regsize (gdbarch
);
2009 /* Check if the S8 register was pushed on the stack. */
2012 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2013 offset
-= mips_abi_regsize (gdbarch
);
2016 /* Check if S2-S7 were pushed on the stack. */
2017 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2019 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2020 offset
-= mips_abi_regsize (gdbarch
);
2023 /* Check if the S1 register was pushed on the stack. */
2024 if (save_inst
& 0x10)
2026 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2027 offset
-= mips_abi_regsize (gdbarch
);
2029 /* Check if the S0 register was pushed on the stack. */
2030 if (save_inst
& 0x20)
2032 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2033 offset
-= mips_abi_regsize (gdbarch
);
2036 /* Check if A0-A3 were pushed on the stack. */
2037 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2039 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2040 offset
-= mips_abi_regsize (gdbarch
);
2044 if (this_cache
!= NULL
)
2047 (get_frame_register_signed (this_frame
,
2048 gdbarch_num_regs (gdbarch
) + frame_reg
)
2049 + frame_offset
- frame_adjust
);
2050 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2051 be able to get rid of the assignment below, evetually. But it's
2052 still needed for now. */
2053 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2054 + mips_regnum (gdbarch
)->pc
]
2055 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2058 /* If we didn't reach the end of the prologue when scanning the function
2059 instructions, then set end_prologue_addr to the address of the
2060 instruction immediately after the last one we scanned. */
2061 if (end_prologue_addr
== 0)
2062 end_prologue_addr
= cur_pc
;
2064 return end_prologue_addr
;
2067 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2068 Procedures that use the 32-bit instruction set are handled by the
2069 mips_insn32 unwinder. */
2071 static struct mips_frame_cache
*
2072 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2074 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2075 struct mips_frame_cache
*cache
;
2077 if ((*this_cache
) != NULL
)
2078 return (*this_cache
);
2079 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2080 (*this_cache
) = cache
;
2081 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2083 /* Analyze the function prologue. */
2085 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2086 CORE_ADDR start_addr
;
2088 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2089 if (start_addr
== 0)
2090 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2091 /* We can't analyze the prologue if we couldn't find the begining
2093 if (start_addr
== 0)
2096 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2099 /* gdbarch_sp_regnum contains the value and not the address. */
2100 trad_frame_set_value (cache
->saved_regs
,
2101 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2104 return (*this_cache
);
2108 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2109 struct frame_id
*this_id
)
2111 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2113 /* This marks the outermost frame. */
2114 if (info
->base
== 0)
2116 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2119 static struct value
*
2120 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2121 void **this_cache
, int regnum
)
2123 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2125 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2129 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2130 struct frame_info
*this_frame
, void **this_cache
)
2132 CORE_ADDR pc
= get_frame_pc (this_frame
);
2133 if (mips_pc_is_mips16 (pc
))
2138 static const struct frame_unwind mips_insn16_frame_unwind
=
2141 default_frame_unwind_stop_reason
,
2142 mips_insn16_frame_this_id
,
2143 mips_insn16_frame_prev_register
,
2145 mips_insn16_frame_sniffer
2149 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2152 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2157 static const struct frame_base mips_insn16_frame_base
=
2159 &mips_insn16_frame_unwind
,
2160 mips_insn16_frame_base_address
,
2161 mips_insn16_frame_base_address
,
2162 mips_insn16_frame_base_address
2165 static const struct frame_base
*
2166 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2168 CORE_ADDR pc
= get_frame_pc (this_frame
);
2169 if (mips_pc_is_mips16 (pc
))
2170 return &mips_insn16_frame_base
;
2175 /* Mark all the registers as unset in the saved_regs array
2176 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
2179 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
2181 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
2185 const int num_regs
= gdbarch_num_regs (gdbarch
);
2188 for (i
= 0; i
< num_regs
; i
++)
2190 this_cache
->saved_regs
[i
].addr
= -1;
2195 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2196 the associated FRAME_CACHE if not null.
2197 Return the address of the first instruction past the prologue. */
2200 mips32_scan_prologue (struct gdbarch
*gdbarch
,
2201 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2202 struct frame_info
*this_frame
,
2203 struct mips_frame_cache
*this_cache
)
2206 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
2210 int frame_reg
= MIPS_SP_REGNUM
;
2212 CORE_ADDR end_prologue_addr
= 0;
2213 int seen_sp_adjust
= 0;
2214 int load_immediate_bytes
= 0;
2215 int in_delay_slot
= 0;
2216 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
2218 /* Can be called when there's no process, and hence when there's no
2220 if (this_frame
!= NULL
)
2221 sp
= get_frame_register_signed (this_frame
,
2222 gdbarch_num_regs (gdbarch
)
2227 if (limit_pc
> start_pc
+ 200)
2228 limit_pc
= start_pc
+ 200;
2233 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
2235 unsigned long inst
, high_word
, low_word
;
2238 /* Fetch the instruction. */
2239 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, cur_pc
);
2241 /* Save some code by pre-extracting some useful fields. */
2242 high_word
= (inst
>> 16) & 0xffff;
2243 low_word
= inst
& 0xffff;
2244 reg
= high_word
& 0x1f;
2246 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
2247 || high_word
== 0x23bd /* addi $sp,$sp,-i */
2248 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
2250 if (low_word
& 0x8000) /* Negative stack adjustment? */
2251 frame_offset
+= 0x10000 - low_word
;
2253 /* Exit loop if a positive stack adjustment is found, which
2254 usually means that the stack cleanup code in the function
2255 epilogue is reached. */
2259 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
2260 && !regsize_is_64_bits
)
2262 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2264 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
2265 && regsize_is_64_bits
)
2267 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
2268 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
2270 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
2272 /* Old gcc frame, r30 is virtual frame pointer. */
2273 if ((long) low_word
!= frame_offset
)
2274 frame_addr
= sp
+ low_word
;
2275 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2277 unsigned alloca_adjust
;
2280 frame_addr
= get_frame_register_signed
2281 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2283 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
2284 if (alloca_adjust
> 0)
2286 /* FP > SP + frame_size. This may be because of
2287 an alloca or somethings similar. Fix sp to
2288 "pre-alloca" value, and try again. */
2289 sp
+= alloca_adjust
;
2290 /* Need to reset the status of all registers. Otherwise,
2291 we will hit a guard that prevents the new address
2292 for each register to be recomputed during the second
2294 reset_saved_regs (gdbarch
, this_cache
);
2299 /* move $30,$sp. With different versions of gas this will be either
2300 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
2301 Accept any one of these. */
2302 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2304 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
2305 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
2307 unsigned alloca_adjust
;
2310 frame_addr
= get_frame_register_signed
2311 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
2313 alloca_adjust
= (unsigned) (frame_addr
- sp
);
2314 if (alloca_adjust
> 0)
2316 /* FP > SP + frame_size. This may be because of
2317 an alloca or somethings similar. Fix sp to
2318 "pre-alloca" value, and try again. */
2320 /* Need to reset the status of all registers. Otherwise,
2321 we will hit a guard that prevents the new address
2322 for each register to be recomputed during the second
2324 reset_saved_regs (gdbarch
, this_cache
);
2329 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2330 && !regsize_is_64_bits
)
2332 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2334 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2335 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2336 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2337 || high_word
== 0x3c1c /* lui $gp,n */
2338 || high_word
== 0x279c /* addiu $gp,$gp,n */
2339 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2340 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2343 /* These instructions are part of the prologue, but we don't
2344 need to do anything special to handle them. */
2346 /* The instructions below load $at or $t0 with an immediate
2347 value in preparation for a stack adjustment via
2348 subu $sp,$sp,[$at,$t0]. These instructions could also
2349 initialize a local variable, so we accept them only before
2350 a stack adjustment instruction was seen. */
2351 else if (!seen_sp_adjust
2352 && (high_word
== 0x3c01 /* lui $at,n */
2353 || high_word
== 0x3c08 /* lui $t0,n */
2354 || high_word
== 0x3421 /* ori $at,$at,n */
2355 || high_word
== 0x3508 /* ori $t0,$t0,n */
2356 || high_word
== 0x3401 /* ori $at,$zero,n */
2357 || high_word
== 0x3408 /* ori $t0,$zero,n */
2360 if (end_prologue_addr
== 0)
2361 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2365 /* This instruction is not an instruction typically found
2366 in a prologue, so we must have reached the end of the
2368 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2369 loop now? Why would we need to continue scanning the function
2371 if (end_prologue_addr
== 0)
2372 end_prologue_addr
= cur_pc
;
2374 /* Check for branches and jumps. For now, only jump to
2375 register are caught (i.e. returns). */
2376 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
2380 /* If the previous instruction was a jump, we must have reached
2381 the end of the prologue by now. Stop scanning so that we do
2382 not go past the function return. */
2387 if (this_cache
!= NULL
)
2390 (get_frame_register_signed (this_frame
,
2391 gdbarch_num_regs (gdbarch
) + frame_reg
)
2393 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2394 this assignment below, eventually. But it's still needed
2396 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2397 + mips_regnum (gdbarch
)->pc
]
2398 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2402 /* If we didn't reach the end of the prologue when scanning the function
2403 instructions, then set end_prologue_addr to the address of the
2404 instruction immediately after the last one we scanned. */
2405 /* brobecker/2004-10-10: I don't think this would ever happen, but
2406 we may as well be careful and do our best if we have a null
2407 end_prologue_addr. */
2408 if (end_prologue_addr
== 0)
2409 end_prologue_addr
= cur_pc
;
2411 /* In a frameless function, we might have incorrectly
2412 skipped some load immediate instructions. Undo the skipping
2413 if the load immediate was not followed by a stack adjustment. */
2414 if (load_immediate_bytes
&& !seen_sp_adjust
)
2415 end_prologue_addr
-= load_immediate_bytes
;
2417 return end_prologue_addr
;
2420 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2421 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2422 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2425 static struct mips_frame_cache
*
2426 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2428 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2429 struct mips_frame_cache
*cache
;
2431 if ((*this_cache
) != NULL
)
2432 return (*this_cache
);
2434 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2435 (*this_cache
) = cache
;
2436 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2438 /* Analyze the function prologue. */
2440 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2441 CORE_ADDR start_addr
;
2443 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2444 if (start_addr
== 0)
2445 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2446 /* We can't analyze the prologue if we couldn't find the begining
2448 if (start_addr
== 0)
2451 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2454 /* gdbarch_sp_regnum contains the value and not the address. */
2455 trad_frame_set_value (cache
->saved_regs
,
2456 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2459 return (*this_cache
);
2463 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2464 struct frame_id
*this_id
)
2466 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2468 /* This marks the outermost frame. */
2469 if (info
->base
== 0)
2471 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2474 static struct value
*
2475 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2476 void **this_cache
, int regnum
)
2478 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2480 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2484 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2485 struct frame_info
*this_frame
, void **this_cache
)
2487 CORE_ADDR pc
= get_frame_pc (this_frame
);
2488 if (! mips_pc_is_mips16 (pc
))
2493 static const struct frame_unwind mips_insn32_frame_unwind
=
2496 default_frame_unwind_stop_reason
,
2497 mips_insn32_frame_this_id
,
2498 mips_insn32_frame_prev_register
,
2500 mips_insn32_frame_sniffer
2504 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2507 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2512 static const struct frame_base mips_insn32_frame_base
=
2514 &mips_insn32_frame_unwind
,
2515 mips_insn32_frame_base_address
,
2516 mips_insn32_frame_base_address
,
2517 mips_insn32_frame_base_address
2520 static const struct frame_base
*
2521 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2523 CORE_ADDR pc
= get_frame_pc (this_frame
);
2524 if (! mips_pc_is_mips16 (pc
))
2525 return &mips_insn32_frame_base
;
2530 static struct trad_frame_cache
*
2531 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2534 CORE_ADDR start_addr
;
2535 CORE_ADDR stack_addr
;
2536 struct trad_frame_cache
*this_trad_cache
;
2537 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2538 int num_regs
= gdbarch_num_regs (gdbarch
);
2540 if ((*this_cache
) != NULL
)
2541 return (*this_cache
);
2542 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2543 (*this_cache
) = this_trad_cache
;
2545 /* The return address is in the link register. */
2546 trad_frame_set_reg_realreg (this_trad_cache
,
2547 gdbarch_pc_regnum (gdbarch
),
2548 num_regs
+ MIPS_RA_REGNUM
);
2550 /* Frame ID, since it's a frameless / stackless function, no stack
2551 space is allocated and SP on entry is the current SP. */
2552 pc
= get_frame_pc (this_frame
);
2553 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2554 stack_addr
= get_frame_register_signed (this_frame
,
2555 num_regs
+ MIPS_SP_REGNUM
);
2556 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2558 /* Assume that the frame's base is the same as the
2560 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2562 return this_trad_cache
;
2566 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2567 struct frame_id
*this_id
)
2569 struct trad_frame_cache
*this_trad_cache
2570 = mips_stub_frame_cache (this_frame
, this_cache
);
2571 trad_frame_get_id (this_trad_cache
, this_id
);
2574 static struct value
*
2575 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2576 void **this_cache
, int regnum
)
2578 struct trad_frame_cache
*this_trad_cache
2579 = mips_stub_frame_cache (this_frame
, this_cache
);
2580 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2584 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2585 struct frame_info
*this_frame
, void **this_cache
)
2588 struct obj_section
*s
;
2589 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2590 struct minimal_symbol
*msym
;
2592 /* Use the stub unwinder for unreadable code. */
2593 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2596 if (in_plt_section (pc
, NULL
))
2599 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2600 s
= find_pc_section (pc
);
2603 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2604 ".MIPS.stubs") == 0)
2607 /* Calling a PIC function from a non-PIC function passes through a
2608 stub. The stub for foo is named ".pic.foo". */
2609 msym
= lookup_minimal_symbol_by_pc (pc
);
2611 && SYMBOL_LINKAGE_NAME (msym
) != NULL
2612 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
2618 static const struct frame_unwind mips_stub_frame_unwind
=
2621 default_frame_unwind_stop_reason
,
2622 mips_stub_frame_this_id
,
2623 mips_stub_frame_prev_register
,
2625 mips_stub_frame_sniffer
2629 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2632 struct trad_frame_cache
*this_trad_cache
2633 = mips_stub_frame_cache (this_frame
, this_cache
);
2634 return trad_frame_get_this_base (this_trad_cache
);
2637 static const struct frame_base mips_stub_frame_base
=
2639 &mips_stub_frame_unwind
,
2640 mips_stub_frame_base_address
,
2641 mips_stub_frame_base_address
,
2642 mips_stub_frame_base_address
2645 static const struct frame_base
*
2646 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2648 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2649 return &mips_stub_frame_base
;
2654 /* mips_addr_bits_remove - remove useless address bits */
2657 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2659 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2661 if (is_mips16_addr (addr
))
2662 addr
= unmake_mips16_addr (addr
);
2664 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2665 /* This hack is a work-around for existing boards using PMON, the
2666 simulator, and any other 64-bit targets that doesn't have true
2667 64-bit addressing. On these targets, the upper 32 bits of
2668 addresses are ignored by the hardware. Thus, the PC or SP are
2669 likely to have been sign extended to all 1s by instruction
2670 sequences that load 32-bit addresses. For example, a typical
2671 piece of code that loads an address is this:
2673 lui $r2, <upper 16 bits>
2674 ori $r2, <lower 16 bits>
2676 But the lui sign-extends the value such that the upper 32 bits
2677 may be all 1s. The workaround is simply to mask off these
2678 bits. In the future, gcc may be changed to support true 64-bit
2679 addressing, and this masking will have to be disabled. */
2680 return addr
&= 0xffffffffUL
;
2685 /* Instructions used during single-stepping of atomic sequences. */
2686 #define LL_OPCODE 0x30
2687 #define LLD_OPCODE 0x34
2688 #define SC_OPCODE 0x38
2689 #define SCD_OPCODE 0x3c
2691 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2692 instruction and ending with a SC/SCD instruction. If such a sequence
2693 is found, attempt to step through it. A breakpoint is placed at the end of
2697 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
2698 struct address_space
*aspace
, CORE_ADDR pc
)
2700 CORE_ADDR breaks
[2] = {-1, -1};
2702 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2706 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2707 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2712 insn
= mips_fetch_instruction (gdbarch
, loc
);
2713 /* Assume all atomic sequences start with a ll/lld instruction. */
2714 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2717 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2719 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2722 loc
+= MIPS_INSN32_SIZE
;
2723 insn
= mips_fetch_instruction (gdbarch
, loc
);
2725 /* Assume that there is at most one branch in the atomic
2726 sequence. If a branch is found, put a breakpoint in its
2727 destination address. */
2728 switch (itype_op (insn
))
2730 case 0: /* SPECIAL */
2731 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2732 return 0; /* fallback to the standard single-step code. */
2734 case 1: /* REGIMM */
2735 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
2736 || ((itype_rt (insn
) & 0x1e) == 0
2737 && itype_rs (insn
) == 0)); /* BPOSGE* */
2741 return 0; /* fallback to the standard single-step code. */
2748 case 22: /* BLEZL */
2749 case 23: /* BGTTL */
2753 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
2754 && (itype_rt (insn
) & 0x2) == 0);
2755 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
2760 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2765 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2766 if (last_breakpoint
>= 1)
2767 return 0; /* More than one branch found, fallback to the
2768 standard single-step code. */
2769 breaks
[1] = branch_bp
;
2773 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2777 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2778 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2781 loc
+= MIPS_INSN32_SIZE
;
2783 /* Insert a breakpoint right after the end of the atomic sequence. */
2786 /* Check for duplicated breakpoints. Check also for a breakpoint
2787 placed (branch instruction's destination) in the atomic sequence. */
2788 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2789 last_breakpoint
= 0;
2791 /* Effectively inserts the breakpoints. */
2792 for (index
= 0; index
<= last_breakpoint
; index
++)
2793 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
2798 /* mips_software_single_step() is called just before we want to resume
2799 the inferior, if we want to single-step it but there is no hardware
2800 or kernel single-step support (MIPS on GNU/Linux for example). We find
2801 the target of the coming instruction and breakpoint it. */
2804 mips_software_single_step (struct frame_info
*frame
)
2806 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2807 struct address_space
*aspace
= get_frame_address_space (frame
);
2808 CORE_ADDR pc
, next_pc
;
2810 pc
= get_frame_pc (frame
);
2811 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
2814 next_pc
= mips_next_pc (frame
, pc
);
2816 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2820 /* Test whether the PC points to the return instruction at the
2821 end of a function. */
2824 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2829 /* This used to check for MIPS16, but this piece of code is never
2830 called for MIPS16 functions. */
2831 gdb_assert (!mips_pc_is_mips16 (pc
));
2833 insn
= mips_fetch_instruction (gdbarch
, pc
);
2835 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
2839 /* This fencepost looks highly suspicious to me. Removing it also
2840 seems suspicious as it could affect remote debugging across serial
2844 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2850 struct inferior
*inf
;
2852 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2854 fence
= start_pc
- heuristic_fence_post
;
2858 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2859 fence
= VM_MIN_ADDRESS
;
2861 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2863 inf
= current_inferior ();
2865 /* Search back for previous return. */
2866 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2867 if (start_pc
< fence
)
2869 /* It's not clear to me why we reach this point when
2870 stop_soon, but with this test, at least we
2871 don't print out warnings for every child forked (eg, on
2872 decstation). 22apr93 rich@cygnus.com. */
2873 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
2875 static int blurb_printed
= 0;
2877 warning (_("GDB can't find the start of the function at %s."),
2878 paddress (gdbarch
, pc
));
2882 /* This actually happens frequently in embedded
2883 development, when you first connect to a board
2884 and your stack pointer and pc are nowhere in
2885 particular. This message needs to give people
2886 in that situation enough information to
2887 determine that it's no big deal. */
2888 printf_filtered ("\n\
2889 GDB is unable to find the start of the function at %s\n\
2890 and thus can't determine the size of that function's stack frame.\n\
2891 This means that GDB may be unable to access that stack frame, or\n\
2892 the frames below it.\n\
2893 This problem is most likely caused by an invalid program counter or\n\
2895 However, if you think GDB should simply search farther back\n\
2896 from %s for code which looks like the beginning of a\n\
2897 function, you can increase the range of the search using the `set\n\
2898 heuristic-fence-post' command.\n",
2899 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
2906 else if (mips_pc_is_mips16 (start_pc
))
2908 unsigned short inst
;
2910 /* On MIPS16, any one of the following is likely to be the
2911 start of a function:
2917 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
2918 inst
= mips_fetch_instruction (gdbarch
, start_pc
);
2919 if ((inst
& 0xff80) == 0x6480) /* save */
2921 if (start_pc
- instlen
>= fence
)
2923 inst
= mips_fetch_instruction (gdbarch
, start_pc
- instlen
);
2924 if ((inst
& 0xf800) == 0xf000) /* extend */
2925 start_pc
-= instlen
;
2929 else if (((inst
& 0xf81f) == 0xe809
2930 && (inst
& 0x700) != 0x700) /* entry */
2931 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2932 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2933 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2935 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2936 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2941 else if (mips_about_to_return (gdbarch
, start_pc
))
2943 /* Skip return and its delay slot. */
2944 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2951 struct mips_objfile_private
2957 /* According to the current ABI, should the type be passed in a
2958 floating-point register (assuming that there is space)? When there
2959 is no FPU, FP are not even considered as possible candidates for
2960 FP registers and, consequently this returns false - forces FP
2961 arguments into integer registers. */
2964 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2965 struct type
*arg_type
)
2967 return ((typecode
== TYPE_CODE_FLT
2968 || (MIPS_EABI (gdbarch
)
2969 && (typecode
== TYPE_CODE_STRUCT
2970 || typecode
== TYPE_CODE_UNION
)
2971 && TYPE_NFIELDS (arg_type
) == 1
2972 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2974 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2977 /* On o32, argument passing in GPRs depends on the alignment of the type being
2978 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2981 mips_type_needs_double_align (struct type
*type
)
2983 enum type_code typecode
= TYPE_CODE (type
);
2985 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2987 else if (typecode
== TYPE_CODE_STRUCT
)
2989 if (TYPE_NFIELDS (type
) < 1)
2991 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2993 else if (typecode
== TYPE_CODE_UNION
)
2997 n
= TYPE_NFIELDS (type
);
2998 for (i
= 0; i
< n
; i
++)
2999 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
3006 /* Adjust the address downward (direction of stack growth) so that it
3007 is correctly aligned for a new stack frame. */
3009 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3011 return align_down (addr
, 16);
3014 /* Implement the "push_dummy_code" gdbarch method. */
3017 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
3018 CORE_ADDR funaddr
, struct value
**args
,
3019 int nargs
, struct type
*value_type
,
3020 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
3021 struct regcache
*regcache
)
3024 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
3026 /* Reserve enough room on the stack for our breakpoint instruction. */
3027 *bp_addr
= sp
- sizeof (nop_insn
);
3029 /* The breakpoint layer automatically adjusts the address of
3030 breakpoints inserted in a branch delay slot. With enough
3031 bad luck, the 4 bytes located just before our breakpoint
3032 instruction could look like a branch instruction, and thus
3033 trigger the adjustement, and break the function call entirely.
3034 So, we reserve those 4 bytes and write a nop instruction
3035 to prevent that from happening. */
3036 nop_addr
= *bp_addr
- sizeof (nop_insn
);
3037 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
3038 sp
= mips_frame_align (gdbarch
, nop_addr
);
3040 /* Inferior resumes at the function entry point. */
3047 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3048 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3049 int nargs
, struct value
**args
, CORE_ADDR sp
,
3050 int struct_return
, CORE_ADDR struct_addr
)
3056 int stack_offset
= 0;
3057 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3058 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3059 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3060 int regsize
= mips_abi_regsize (gdbarch
);
3062 /* For shared libraries, "t9" needs to point at the function
3064 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3066 /* Set the return address register to point to the entry point of
3067 the program, where a breakpoint lies in wait. */
3068 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3070 /* First ensure that the stack and structure return address (if any)
3071 are properly aligned. The stack has to be at least 64-bit
3072 aligned even on 32-bit machines, because doubles must be 64-bit
3073 aligned. For n32 and n64, stack frames need to be 128-bit
3074 aligned, so we round to this widest known alignment. */
3076 sp
= align_down (sp
, 16);
3077 struct_addr
= align_down (struct_addr
, 16);
3079 /* Now make space on the stack for the args. We allocate more
3080 than necessary for EABI, because the first few arguments are
3081 passed in registers, but that's OK. */
3082 for (argnum
= 0; argnum
< nargs
; argnum
++)
3083 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
3084 sp
-= align_up (len
, 16);
3087 fprintf_unfiltered (gdb_stdlog
,
3088 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
3089 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3091 /* Initialize the integer and float register pointers. */
3092 argreg
= MIPS_A0_REGNUM
;
3093 float_argreg
= mips_fpa0_regnum (gdbarch
);
3095 /* The struct_return pointer occupies the first parameter-passing reg. */
3099 fprintf_unfiltered (gdb_stdlog
,
3100 "mips_eabi_push_dummy_call: "
3101 "struct_return reg=%d %s\n",
3102 argreg
, paddress (gdbarch
, struct_addr
));
3103 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3106 /* Now load as many as possible of the first arguments into
3107 registers, and push the rest onto the stack. Loop thru args
3108 from first to last. */
3109 for (argnum
= 0; argnum
< nargs
; argnum
++)
3111 const gdb_byte
*val
;
3112 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
3113 struct value
*arg
= args
[argnum
];
3114 struct type
*arg_type
= check_typedef (value_type (arg
));
3115 int len
= TYPE_LENGTH (arg_type
);
3116 enum type_code typecode
= TYPE_CODE (arg_type
);
3119 fprintf_unfiltered (gdb_stdlog
,
3120 "mips_eabi_push_dummy_call: %d len=%d type=%d",
3121 argnum
+ 1, len
, (int) typecode
);
3123 /* Function pointer arguments to mips16 code need to be made into
3125 if (typecode
== TYPE_CODE_PTR
3126 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
3128 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
3130 if (mips_pc_is_mips16 (addr
))
3132 store_signed_integer (valbuf
, len
, byte_order
,
3133 make_mips16_addr (addr
));
3137 val
= value_contents (arg
);
3139 /* The EABI passes structures that do not fit in a register by
3141 else if (len
> regsize
3142 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
3144 store_unsigned_integer (valbuf
, regsize
, byte_order
,
3145 value_address (arg
));
3146 typecode
= TYPE_CODE_PTR
;
3150 fprintf_unfiltered (gdb_stdlog
, " push");
3153 val
= value_contents (arg
);
3155 /* 32-bit ABIs always start floating point arguments in an
3156 even-numbered floating point register. Round the FP register
3157 up before the check to see if there are any FP registers
3158 left. Non MIPS_EABI targets also pass the FP in the integer
3159 registers so also round up normal registers. */
3160 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3162 if ((float_argreg
& 1))
3166 /* Floating point arguments passed in registers have to be
3167 treated specially. On 32-bit architectures, doubles
3168 are passed in register pairs; the even register gets
3169 the low word, and the odd register gets the high word.
3170 On non-EABI processors, the first two floating point arguments are
3171 also copied to general registers, because MIPS16 functions
3172 don't use float registers for arguments. This duplication of
3173 arguments in general registers can't hurt non-MIPS16 functions
3174 because those registers are normally skipped. */
3175 /* MIPS_EABI squeezes a struct that contains a single floating
3176 point value into an FP register instead of pushing it onto the
3178 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3179 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3181 /* EABI32 will pass doubles in consecutive registers, even on
3182 64-bit cores. At one time, we used to check the size of
3183 `float_argreg' to determine whether or not to pass doubles
3184 in consecutive registers, but this is not sufficient for
3185 making the ABI determination. */
3186 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
3188 int low_offset
= gdbarch_byte_order (gdbarch
)
3189 == BFD_ENDIAN_BIG
? 4 : 0;
3192 /* Write the low word of the double to the even register(s). */
3193 regval
= extract_signed_integer (val
+ low_offset
,
3196 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3197 float_argreg
, phex (regval
, 4));
3198 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3200 /* Write the high word of the double to the odd register(s). */
3201 regval
= extract_signed_integer (val
+ 4 - low_offset
,
3204 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3205 float_argreg
, phex (regval
, 4));
3206 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3210 /* This is a floating point value that fits entirely
3211 in a single register. */
3212 /* On 32 bit ABI's the float_argreg is further adjusted
3213 above to ensure that it is even register aligned. */
3214 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
3216 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3217 float_argreg
, phex (regval
, len
));
3218 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
3223 /* Copy the argument to general registers or the stack in
3224 register-sized pieces. Large arguments are split between
3225 registers and stack. */
3226 /* Note: structs whose size is not a multiple of regsize
3227 are treated specially: Irix cc passes
3228 them in registers where gcc sometimes puts them on the
3229 stack. For maximum compatibility, we will put them in
3231 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
3233 /* Note: Floating-point values that didn't fit into an FP
3234 register are only written to memory. */
3237 /* Remember if the argument was written to the stack. */
3238 int stack_used_p
= 0;
3239 int partial_len
= (len
< regsize
? len
: regsize
);
3242 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3245 /* Write this portion of the argument to the stack. */
3246 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3248 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3250 /* Should shorter than int integer values be
3251 promoted to int before being stored? */
3252 int longword_offset
= 0;
3255 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3258 && (typecode
== TYPE_CODE_INT
3259 || typecode
== TYPE_CODE_PTR
3260 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
3261 longword_offset
= regsize
- len
;
3262 else if ((typecode
== TYPE_CODE_STRUCT
3263 || typecode
== TYPE_CODE_UNION
)
3264 && TYPE_LENGTH (arg_type
) < regsize
)
3265 longword_offset
= regsize
- len
;
3270 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3271 paddress (gdbarch
, stack_offset
));
3272 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3273 paddress (gdbarch
, longword_offset
));
3276 addr
= sp
+ stack_offset
+ longword_offset
;
3281 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3282 paddress (gdbarch
, addr
));
3283 for (i
= 0; i
< partial_len
; i
++)
3285 fprintf_unfiltered (gdb_stdlog
, "%02x",
3289 write_memory (addr
, val
, partial_len
);
3292 /* Note!!! This is NOT an else clause. Odd sized
3293 structs may go thru BOTH paths. Floating point
3294 arguments will not. */
3295 /* Write this portion of the argument to a general
3296 purpose register. */
3297 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
3298 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3301 extract_signed_integer (val
, partial_len
, byte_order
);
3304 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3306 phex (regval
, regsize
));
3307 regcache_cooked_write_signed (regcache
, argreg
, regval
);
3314 /* Compute the offset into the stack at which we will
3315 copy the next parameter.
3317 In the new EABI (and the NABI32), the stack_offset
3318 only needs to be adjusted when it has been used. */
3321 stack_offset
+= align_up (partial_len
, regsize
);
3325 fprintf_unfiltered (gdb_stdlog
, "\n");
3328 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3330 /* Return adjusted stack pointer. */
3334 /* Determine the return value convention being used. */
3336 static enum return_value_convention
3337 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
3338 struct type
*type
, struct regcache
*regcache
,
3339 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3341 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3342 int fp_return_type
= 0;
3343 int offset
, regnum
, xfer
;
3345 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
3346 return RETURN_VALUE_STRUCT_CONVENTION
;
3348 /* Floating point type? */
3349 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3351 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
3353 /* Structs with a single field of float type
3354 are returned in a floating point register. */
3355 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
3356 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3357 && TYPE_NFIELDS (type
) == 1)
3359 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
3361 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
3368 /* A floating-point value belongs in the least significant part
3371 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3372 regnum
= mips_regnum (gdbarch
)->fp0
;
3376 /* An integer value goes in V0/V1. */
3378 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
3379 regnum
= MIPS_V0_REGNUM
;
3382 offset
< TYPE_LENGTH (type
);
3383 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
3385 xfer
= mips_abi_regsize (gdbarch
);
3386 if (offset
+ xfer
> TYPE_LENGTH (type
))
3387 xfer
= TYPE_LENGTH (type
) - offset
;
3388 mips_xfer_register (gdbarch
, regcache
,
3389 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3390 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
3394 return RETURN_VALUE_REGISTER_CONVENTION
;
3398 /* N32/N64 ABI stuff. */
3400 /* Search for a naturally aligned double at OFFSET inside a struct
3401 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
3405 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
3410 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3413 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3416 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3419 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3422 struct type
*field_type
;
3424 /* We're only looking at normal fields. */
3425 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
3426 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3429 /* If we have gone past the offset, there is no double to pass. */
3430 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3434 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3436 /* If this field is entirely before the requested offset, go
3437 on to the next one. */
3438 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3441 /* If this is our special aligned double, we can stop. */
3442 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3443 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3446 /* This field starts at or before the requested offset, and
3447 overlaps it. If it is a structure, recurse inwards. */
3448 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3455 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3456 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3457 int nargs
, struct value
**args
, CORE_ADDR sp
,
3458 int struct_return
, CORE_ADDR struct_addr
)
3464 int stack_offset
= 0;
3465 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3466 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3467 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3469 /* For shared libraries, "t9" needs to point at the function
3471 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3473 /* Set the return address register to point to the entry point of
3474 the program, where a breakpoint lies in wait. */
3475 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3477 /* First ensure that the stack and structure return address (if any)
3478 are properly aligned. The stack has to be at least 64-bit
3479 aligned even on 32-bit machines, because doubles must be 64-bit
3480 aligned. For n32 and n64, stack frames need to be 128-bit
3481 aligned, so we round to this widest known alignment. */
3483 sp
= align_down (sp
, 16);
3484 struct_addr
= align_down (struct_addr
, 16);
3486 /* Now make space on the stack for the args. */
3487 for (argnum
= 0; argnum
< nargs
; argnum
++)
3488 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3489 sp
-= align_up (len
, 16);
3492 fprintf_unfiltered (gdb_stdlog
,
3493 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
3494 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3496 /* Initialize the integer and float register pointers. */
3497 argreg
= MIPS_A0_REGNUM
;
3498 float_argreg
= mips_fpa0_regnum (gdbarch
);
3500 /* The struct_return pointer occupies the first parameter-passing reg. */
3504 fprintf_unfiltered (gdb_stdlog
,
3505 "mips_n32n64_push_dummy_call: "
3506 "struct_return reg=%d %s\n",
3507 argreg
, paddress (gdbarch
, struct_addr
));
3508 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3511 /* Now load as many as possible of the first arguments into
3512 registers, and push the rest onto the stack. Loop thru args
3513 from first to last. */
3514 for (argnum
= 0; argnum
< nargs
; argnum
++)
3516 const gdb_byte
*val
;
3517 struct value
*arg
= args
[argnum
];
3518 struct type
*arg_type
= check_typedef (value_type (arg
));
3519 int len
= TYPE_LENGTH (arg_type
);
3520 enum type_code typecode
= TYPE_CODE (arg_type
);
3523 fprintf_unfiltered (gdb_stdlog
,
3524 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3525 argnum
+ 1, len
, (int) typecode
);
3527 val
= value_contents (arg
);
3529 /* A 128-bit long double value requires an even-odd pair of
3530 floating-point registers. */
3532 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3533 && (float_argreg
& 1))
3539 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3540 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3542 /* This is a floating point value that fits entirely
3543 in a single register or a pair of registers. */
3544 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3545 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
3547 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3548 float_argreg
, phex (regval
, reglen
));
3549 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3552 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3553 argreg
, phex (regval
, reglen
));
3554 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3559 regval
= extract_unsigned_integer (val
+ reglen
,
3560 reglen
, byte_order
);
3562 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3563 float_argreg
, phex (regval
, reglen
));
3564 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3567 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3568 argreg
, phex (regval
, reglen
));
3569 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3576 /* Copy the argument to general registers or the stack in
3577 register-sized pieces. Large arguments are split between
3578 registers and stack. */
3579 /* For N32/N64, structs, unions, or other composite types are
3580 treated as a sequence of doublewords, and are passed in integer
3581 or floating point registers as though they were simple scalar
3582 parameters to the extent that they fit, with any excess on the
3583 stack packed according to the normal memory layout of the
3585 The caller does not reserve space for the register arguments;
3586 the callee is responsible for reserving it if required. */
3587 /* Note: Floating-point values that didn't fit into an FP
3588 register are only written to memory. */
3591 /* Remember if the argument was written to the stack. */
3592 int stack_used_p
= 0;
3593 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3596 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3599 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3600 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3602 /* Write this portion of the argument to the stack. */
3603 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3605 /* Should shorter than int integer values be
3606 promoted to int before being stored? */
3607 int longword_offset
= 0;
3610 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3612 if ((typecode
== TYPE_CODE_INT
3613 || typecode
== TYPE_CODE_PTR
)
3615 longword_offset
= MIPS64_REGSIZE
- len
;
3620 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
3621 paddress (gdbarch
, stack_offset
));
3622 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
3623 paddress (gdbarch
, longword_offset
));
3626 addr
= sp
+ stack_offset
+ longword_offset
;
3631 fprintf_unfiltered (gdb_stdlog
, " @%s ",
3632 paddress (gdbarch
, addr
));
3633 for (i
= 0; i
< partial_len
; i
++)
3635 fprintf_unfiltered (gdb_stdlog
, "%02x",
3639 write_memory (addr
, val
, partial_len
);
3642 /* Note!!! This is NOT an else clause. Odd sized
3643 structs may go thru BOTH paths. */
3644 /* Write this portion of the argument to a general
3645 purpose register. */
3646 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3650 /* Sign extend pointers, 32-bit integers and signed
3651 16-bit and 8-bit integers; everything else is taken
3654 if ((partial_len
== 4
3655 && (typecode
== TYPE_CODE_PTR
3656 || typecode
== TYPE_CODE_INT
))
3658 && typecode
== TYPE_CODE_INT
3659 && !TYPE_UNSIGNED (arg_type
)))
3660 regval
= extract_signed_integer (val
, partial_len
,
3663 regval
= extract_unsigned_integer (val
, partial_len
,
3666 /* A non-floating-point argument being passed in a
3667 general register. If a struct or union, and if
3668 the remaining length is smaller than the register
3669 size, we have to adjust the register value on
3672 It does not seem to be necessary to do the
3673 same for integral types. */
3675 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3676 && partial_len
< MIPS64_REGSIZE
3677 && (typecode
== TYPE_CODE_STRUCT
3678 || typecode
== TYPE_CODE_UNION
))
3679 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3683 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3685 phex (regval
, MIPS64_REGSIZE
));
3686 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3688 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3689 TYPE_LENGTH (arg_type
) - len
))
3692 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3694 phex (regval
, MIPS64_REGSIZE
));
3695 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3706 /* Compute the offset into the stack at which we will
3707 copy the next parameter.
3709 In N32 (N64?), the stack_offset only needs to be
3710 adjusted when it has been used. */
3713 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3717 fprintf_unfiltered (gdb_stdlog
, "\n");
3720 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3722 /* Return adjusted stack pointer. */
3726 static enum return_value_convention
3727 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
3728 struct type
*type
, struct regcache
*regcache
,
3729 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3731 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3733 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3735 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3736 if needed), as appropriate for the type. Composite results (struct,
3737 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3740 * A struct with only one or two floating point fields is returned in $f0
3741 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3744 * Any other composite results of at most 128 bits are returned in
3745 $2 (first 64 bits) and $3 (remainder, if necessary).
3747 * Larger composite results are handled by converting the function to a
3748 procedure with an implicit first parameter, which is a pointer to an area
3749 reserved by the caller to receive the result. [The o32-bit ABI requires
3750 that all composite results be handled by conversion to implicit first
3751 parameters. The MIPS/SGI Fortran implementation has always made a
3752 specific exception to return COMPLEX results in the floating point
3755 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3756 return RETURN_VALUE_STRUCT_CONVENTION
;
3757 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3758 && TYPE_LENGTH (type
) == 16
3759 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3761 /* A 128-bit floating-point value fills both $f0 and $f2. The
3762 two registers are used in the same as memory order, so the
3763 eight bytes with the lower memory address are in $f0. */
3765 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3766 mips_xfer_register (gdbarch
, regcache
,
3767 (gdbarch_num_regs (gdbarch
)
3768 + mips_regnum (gdbarch
)->fp0
),
3769 8, gdbarch_byte_order (gdbarch
),
3770 readbuf
, writebuf
, 0);
3771 mips_xfer_register (gdbarch
, regcache
,
3772 (gdbarch_num_regs (gdbarch
)
3773 + mips_regnum (gdbarch
)->fp0
+ 2),
3774 8, gdbarch_byte_order (gdbarch
),
3775 readbuf
? readbuf
+ 8 : readbuf
,
3776 writebuf
? writebuf
+ 8 : writebuf
, 0);
3777 return RETURN_VALUE_REGISTER_CONVENTION
;
3779 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3780 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3782 /* A single or double floating-point value that fits in FP0. */
3784 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3785 mips_xfer_register (gdbarch
, regcache
,
3786 (gdbarch_num_regs (gdbarch
)
3787 + mips_regnum (gdbarch
)->fp0
),
3789 gdbarch_byte_order (gdbarch
),
3790 readbuf
, writebuf
, 0);
3791 return RETURN_VALUE_REGISTER_CONVENTION
;
3793 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3794 && TYPE_NFIELDS (type
) <= 2
3795 && TYPE_NFIELDS (type
) >= 1
3796 && ((TYPE_NFIELDS (type
) == 1
3797 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3799 || (TYPE_NFIELDS (type
) == 2
3800 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3802 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3803 == TYPE_CODE_FLT
))))
3805 /* A struct that contains one or two floats. Each value is part
3806 in the least significant part of their floating point
3807 register (or GPR, for soft float). */
3810 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3811 ? mips_regnum (gdbarch
)->fp0
3813 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3815 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3818 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3820 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3822 /* A 16-byte long double field goes in two consecutive
3824 mips_xfer_register (gdbarch
, regcache
,
3825 gdbarch_num_regs (gdbarch
) + regnum
,
3827 gdbarch_byte_order (gdbarch
),
3828 readbuf
, writebuf
, offset
);
3829 mips_xfer_register (gdbarch
, regcache
,
3830 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3832 gdbarch_byte_order (gdbarch
),
3833 readbuf
, writebuf
, offset
+ 8);
3836 mips_xfer_register (gdbarch
, regcache
,
3837 gdbarch_num_regs (gdbarch
) + regnum
,
3838 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3839 gdbarch_byte_order (gdbarch
),
3840 readbuf
, writebuf
, offset
);
3842 return RETURN_VALUE_REGISTER_CONVENTION
;
3844 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3845 || TYPE_CODE (type
) == TYPE_CODE_UNION
3846 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3848 /* A composite type. Extract the left justified value,
3849 regardless of the byte order. I.e. DO NOT USE
3853 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3854 offset
< TYPE_LENGTH (type
);
3855 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3857 int xfer
= register_size (gdbarch
, regnum
);
3858 if (offset
+ xfer
> TYPE_LENGTH (type
))
3859 xfer
= TYPE_LENGTH (type
) - offset
;
3861 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3862 offset
, xfer
, regnum
);
3863 mips_xfer_register (gdbarch
, regcache
,
3864 gdbarch_num_regs (gdbarch
) + regnum
,
3865 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3868 return RETURN_VALUE_REGISTER_CONVENTION
;
3872 /* A scalar extract each part but least-significant-byte
3876 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3877 offset
< TYPE_LENGTH (type
);
3878 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3880 int xfer
= register_size (gdbarch
, regnum
);
3881 if (offset
+ xfer
> TYPE_LENGTH (type
))
3882 xfer
= TYPE_LENGTH (type
) - offset
;
3884 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3885 offset
, xfer
, regnum
);
3886 mips_xfer_register (gdbarch
, regcache
,
3887 gdbarch_num_regs (gdbarch
) + regnum
,
3888 xfer
, gdbarch_byte_order (gdbarch
),
3889 readbuf
, writebuf
, offset
);
3891 return RETURN_VALUE_REGISTER_CONVENTION
;
3895 /* Which registers to use for passing floating-point values between
3896 function calls, one of floating-point, general and both kinds of
3897 registers. O32 and O64 use different register kinds for standard
3898 MIPS and MIPS16 code; to make the handling of cases where we may
3899 not know what kind of code is being used (e.g. no debug information)
3900 easier we sometimes use both kinds. */
3909 /* O32 ABI stuff. */
3912 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3913 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3914 int nargs
, struct value
**args
, CORE_ADDR sp
,
3915 int struct_return
, CORE_ADDR struct_addr
)
3921 int stack_offset
= 0;
3922 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3923 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3924 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3926 /* For shared libraries, "t9" needs to point at the function
3928 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3930 /* Set the return address register to point to the entry point of
3931 the program, where a breakpoint lies in wait. */
3932 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3934 /* First ensure that the stack and structure return address (if any)
3935 are properly aligned. The stack has to be at least 64-bit
3936 aligned even on 32-bit machines, because doubles must be 64-bit
3937 aligned. For n32 and n64, stack frames need to be 128-bit
3938 aligned, so we round to this widest known alignment. */
3940 sp
= align_down (sp
, 16);
3941 struct_addr
= align_down (struct_addr
, 16);
3943 /* Now make space on the stack for the args. */
3944 for (argnum
= 0; argnum
< nargs
; argnum
++)
3946 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3947 int arglen
= TYPE_LENGTH (arg_type
);
3949 /* Align to double-word if necessary. */
3950 if (mips_type_needs_double_align (arg_type
))
3951 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3952 /* Allocate space on the stack. */
3953 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3955 sp
-= align_up (len
, 16);
3958 fprintf_unfiltered (gdb_stdlog
,
3959 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
3960 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
3962 /* Initialize the integer and float register pointers. */
3963 argreg
= MIPS_A0_REGNUM
;
3964 float_argreg
= mips_fpa0_regnum (gdbarch
);
3966 /* The struct_return pointer occupies the first parameter-passing reg. */
3970 fprintf_unfiltered (gdb_stdlog
,
3971 "mips_o32_push_dummy_call: "
3972 "struct_return reg=%d %s\n",
3973 argreg
, paddress (gdbarch
, struct_addr
));
3974 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3975 stack_offset
+= MIPS32_REGSIZE
;
3978 /* Now load as many as possible of the first arguments into
3979 registers, and push the rest onto the stack. Loop thru args
3980 from first to last. */
3981 for (argnum
= 0; argnum
< nargs
; argnum
++)
3983 const gdb_byte
*val
;
3984 struct value
*arg
= args
[argnum
];
3985 struct type
*arg_type
= check_typedef (value_type (arg
));
3986 int len
= TYPE_LENGTH (arg_type
);
3987 enum type_code typecode
= TYPE_CODE (arg_type
);
3990 fprintf_unfiltered (gdb_stdlog
,
3991 "mips_o32_push_dummy_call: %d len=%d type=%d",
3992 argnum
+ 1, len
, (int) typecode
);
3994 val
= value_contents (arg
);
3996 /* 32-bit ABIs always start floating point arguments in an
3997 even-numbered floating point register. Round the FP register
3998 up before the check to see if there are any FP registers
3999 left. O32 targets also pass the FP in the integer registers
4000 so also round up normal registers. */
4001 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4003 if ((float_argreg
& 1))
4007 /* Floating point arguments passed in registers have to be
4008 treated specially. On 32-bit architectures, doubles are
4009 passed in register pairs; the even FP register gets the
4010 low word, and the odd FP register gets the high word.
4011 On O32, the first two floating point arguments are also
4012 copied to general registers, following their memory order,
4013 because MIPS16 functions don't use float registers for
4014 arguments. This duplication of arguments in general
4015 registers can't hurt non-MIPS16 functions, because those
4016 registers are normally skipped. */
4018 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4019 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4021 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
4023 int freg_offset
= gdbarch_byte_order (gdbarch
)
4024 == BFD_ENDIAN_BIG
? 1 : 0;
4025 unsigned long regval
;
4028 regval
= extract_unsigned_integer (val
, 4, byte_order
);
4030 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4031 float_argreg
+ freg_offset
,
4033 regcache_cooked_write_unsigned (regcache
,
4034 float_argreg
++ + freg_offset
,
4037 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4038 argreg
, phex (regval
, 4));
4039 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
4042 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
4044 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4045 float_argreg
- freg_offset
,
4047 regcache_cooked_write_unsigned (regcache
,
4048 float_argreg
++ - freg_offset
,
4051 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4052 argreg
, phex (regval
, 4));
4053 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
4057 /* This is a floating point value that fits entirely
4058 in a single register. */
4059 /* On 32 bit ABI's the float_argreg is further adjusted
4060 above to ensure that it is even register aligned. */
4061 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4063 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4064 float_argreg
, phex (regval
, len
));
4065 regcache_cooked_write_unsigned (regcache
,
4066 float_argreg
++, regval
);
4067 /* Although two FP registers are reserved for each
4068 argument, only one corresponding integer register is
4071 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4072 argreg
, phex (regval
, len
));
4073 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
4075 /* Reserve space for the FP register. */
4076 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
4080 /* Copy the argument to general registers or the stack in
4081 register-sized pieces. Large arguments are split between
4082 registers and stack. */
4083 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
4084 are treated specially: Irix cc passes
4085 them in registers where gcc sometimes puts them on the
4086 stack. For maximum compatibility, we will put them in
4088 int odd_sized_struct
= (len
> MIPS32_REGSIZE
4089 && len
% MIPS32_REGSIZE
!= 0);
4090 /* Structures should be aligned to eight bytes (even arg registers)
4091 on MIPS_ABI_O32, if their first member has double precision. */
4092 if (mips_type_needs_double_align (arg_type
))
4097 stack_offset
+= MIPS32_REGSIZE
;
4102 /* Remember if the argument was written to the stack. */
4103 int stack_used_p
= 0;
4104 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
4107 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4110 /* Write this portion of the argument to the stack. */
4111 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4112 || odd_sized_struct
)
4114 /* Should shorter than int integer values be
4115 promoted to int before being stored? */
4116 int longword_offset
= 0;
4122 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4123 paddress (gdbarch
, stack_offset
));
4124 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4125 paddress (gdbarch
, longword_offset
));
4128 addr
= sp
+ stack_offset
+ longword_offset
;
4133 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4134 paddress (gdbarch
, addr
));
4135 for (i
= 0; i
< partial_len
; i
++)
4137 fprintf_unfiltered (gdb_stdlog
, "%02x",
4141 write_memory (addr
, val
, partial_len
);
4144 /* Note!!! This is NOT an else clause. Odd sized
4145 structs may go thru BOTH paths. */
4146 /* Write this portion of the argument to a general
4147 purpose register. */
4148 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4150 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4152 /* Value may need to be sign extended, because
4153 mips_isa_regsize() != mips_abi_regsize(). */
4155 /* A non-floating-point argument being passed in a
4156 general register. If a struct or union, and if
4157 the remaining length is smaller than the register
4158 size, we have to adjust the register value on
4161 It does not seem to be necessary to do the
4162 same for integral types.
4164 Also don't do this adjustment on O64 binaries.
4166 cagney/2001-07-23: gdb/179: Also, GCC, when
4167 outputting LE O32 with sizeof (struct) <
4168 mips_abi_regsize(), generates a left shift
4169 as part of storing the argument in a register
4170 (the left shift isn't generated when
4171 sizeof (struct) >= mips_abi_regsize()). Since
4172 it is quite possible that this is GCC
4173 contradicting the LE/O32 ABI, GDB has not been
4174 adjusted to accommodate this. Either someone
4175 needs to demonstrate that the LE/O32 ABI
4176 specifies such a left shift OR this new ABI gets
4177 identified as such and GDB gets tweaked
4180 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4181 && partial_len
< MIPS32_REGSIZE
4182 && (typecode
== TYPE_CODE_STRUCT
4183 || typecode
== TYPE_CODE_UNION
))
4184 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
4188 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4190 phex (regval
, MIPS32_REGSIZE
));
4191 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4194 /* Prevent subsequent floating point arguments from
4195 being passed in floating point registers. */
4196 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4202 /* Compute the offset into the stack at which we will
4203 copy the next parameter.
4205 In older ABIs, the caller reserved space for
4206 registers that contained arguments. This was loosely
4207 refered to as their "home". Consequently, space is
4208 always allocated. */
4210 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
4214 fprintf_unfiltered (gdb_stdlog
, "\n");
4217 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4219 /* Return adjusted stack pointer. */
4223 static enum return_value_convention
4224 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4225 struct type
*type
, struct regcache
*regcache
,
4226 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4228 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
4229 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4230 int mips16
= mips_pc_is_mips16 (func_addr
);
4231 enum mips_fval_reg fval_reg
;
4233 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
4234 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4235 || TYPE_CODE (type
) == TYPE_CODE_UNION
4236 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4237 return RETURN_VALUE_STRUCT_CONVENTION
;
4238 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4239 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4241 /* A single-precision floating-point value. If reading in or copying,
4242 then we get it from/put it to FP0 for standard MIPS code or GPR2
4243 for MIPS16 code. If writing out only, then we put it to both FP0
4244 and GPR2. We do not support reading in with no function known, if
4245 this safety check ever triggers, then we'll have to try harder. */
4246 gdb_assert (function
|| !readbuf
);
4251 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4254 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
4256 case mips_fval_both
:
4257 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
4260 if (fval_reg
!= mips_fval_gpr
)
4261 mips_xfer_register (gdbarch
, regcache
,
4262 (gdbarch_num_regs (gdbarch
)
4263 + mips_regnum (gdbarch
)->fp0
),
4265 gdbarch_byte_order (gdbarch
),
4266 readbuf
, writebuf
, 0);
4267 if (fval_reg
!= mips_fval_fpr
)
4268 mips_xfer_register (gdbarch
, regcache
,
4269 gdbarch_num_regs (gdbarch
) + 2,
4271 gdbarch_byte_order (gdbarch
),
4272 readbuf
, writebuf
, 0);
4273 return RETURN_VALUE_REGISTER_CONVENTION
;
4275 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4276 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4278 /* A double-precision floating-point value. If reading in or copying,
4279 then we get it from/put it to FP1 and FP0 for standard MIPS code or
4280 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
4281 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
4282 no function known, if this safety check ever triggers, then we'll
4283 have to try harder. */
4284 gdb_assert (function
|| !readbuf
);
4289 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
4292 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
4294 case mips_fval_both
:
4295 fprintf_unfiltered (gdb_stderr
,
4296 "Return float in $fp1/$fp0 and $2/$3\n");
4299 if (fval_reg
!= mips_fval_gpr
)
4301 /* The most significant part goes in FP1, and the least significant
4303 switch (gdbarch_byte_order (gdbarch
))
4305 case BFD_ENDIAN_LITTLE
:
4306 mips_xfer_register (gdbarch
, regcache
,
4307 (gdbarch_num_regs (gdbarch
)
4308 + mips_regnum (gdbarch
)->fp0
+ 0),
4309 4, gdbarch_byte_order (gdbarch
),
4310 readbuf
, writebuf
, 0);
4311 mips_xfer_register (gdbarch
, regcache
,
4312 (gdbarch_num_regs (gdbarch
)
4313 + mips_regnum (gdbarch
)->fp0
+ 1),
4314 4, gdbarch_byte_order (gdbarch
),
4315 readbuf
, writebuf
, 4);
4317 case BFD_ENDIAN_BIG
:
4318 mips_xfer_register (gdbarch
, regcache
,
4319 (gdbarch_num_regs (gdbarch
)
4320 + mips_regnum (gdbarch
)->fp0
+ 1),
4321 4, gdbarch_byte_order (gdbarch
),
4322 readbuf
, writebuf
, 0);
4323 mips_xfer_register (gdbarch
, regcache
,
4324 (gdbarch_num_regs (gdbarch
)
4325 + mips_regnum (gdbarch
)->fp0
+ 0),
4326 4, gdbarch_byte_order (gdbarch
),
4327 readbuf
, writebuf
, 4);
4330 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4333 if (fval_reg
!= mips_fval_fpr
)
4335 /* The two 32-bit parts are always placed in GPR2 and GPR3
4336 following these registers' memory order. */
4337 mips_xfer_register (gdbarch
, regcache
,
4338 gdbarch_num_regs (gdbarch
) + 2,
4339 4, gdbarch_byte_order (gdbarch
),
4340 readbuf
, writebuf
, 0);
4341 mips_xfer_register (gdbarch
, regcache
,
4342 gdbarch_num_regs (gdbarch
) + 3,
4343 4, gdbarch_byte_order (gdbarch
),
4344 readbuf
, writebuf
, 4);
4346 return RETURN_VALUE_REGISTER_CONVENTION
;
4349 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4350 && TYPE_NFIELDS (type
) <= 2
4351 && TYPE_NFIELDS (type
) >= 1
4352 && ((TYPE_NFIELDS (type
) == 1
4353 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4355 || (TYPE_NFIELDS (type
) == 2
4356 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
4358 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
4360 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4362 /* A struct that contains one or two floats. Each value is part
4363 in the least significant part of their floating point
4365 gdb_byte reg
[MAX_REGISTER_SIZE
];
4368 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
4369 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4371 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4374 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4376 mips_xfer_register (gdbarch
, regcache
,
4377 gdbarch_num_regs (gdbarch
) + regnum
,
4378 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
4379 gdbarch_byte_order (gdbarch
),
4380 readbuf
, writebuf
, offset
);
4382 return RETURN_VALUE_REGISTER_CONVENTION
;
4386 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4387 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4389 /* A structure or union. Extract the left justified value,
4390 regardless of the byte order. I.e. DO NOT USE
4394 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4395 offset
< TYPE_LENGTH (type
);
4396 offset
+= register_size (gdbarch
, regnum
), regnum
++)
4398 int xfer
= register_size (gdbarch
, regnum
);
4399 if (offset
+ xfer
> TYPE_LENGTH (type
))
4400 xfer
= TYPE_LENGTH (type
) - offset
;
4402 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
4403 offset
, xfer
, regnum
);
4404 mips_xfer_register (gdbarch
, regcache
,
4405 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4406 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
4408 return RETURN_VALUE_REGISTER_CONVENTION
;
4413 /* A scalar extract each part but least-significant-byte
4414 justified. o32 thinks registers are 4 byte, regardless of
4418 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4419 offset
< TYPE_LENGTH (type
);
4420 offset
+= MIPS32_REGSIZE
, regnum
++)
4422 int xfer
= MIPS32_REGSIZE
;
4423 if (offset
+ xfer
> TYPE_LENGTH (type
))
4424 xfer
= TYPE_LENGTH (type
) - offset
;
4426 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4427 offset
, xfer
, regnum
);
4428 mips_xfer_register (gdbarch
, regcache
,
4429 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4430 gdbarch_byte_order (gdbarch
),
4431 readbuf
, writebuf
, offset
);
4433 return RETURN_VALUE_REGISTER_CONVENTION
;
4437 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
4441 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4442 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4444 struct value
**args
, CORE_ADDR sp
,
4445 int struct_return
, CORE_ADDR struct_addr
)
4451 int stack_offset
= 0;
4452 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4453 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4454 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4456 /* For shared libraries, "t9" needs to point at the function
4458 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4460 /* Set the return address register to point to the entry point of
4461 the program, where a breakpoint lies in wait. */
4462 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4464 /* First ensure that the stack and structure return address (if any)
4465 are properly aligned. The stack has to be at least 64-bit
4466 aligned even on 32-bit machines, because doubles must be 64-bit
4467 aligned. For n32 and n64, stack frames need to be 128-bit
4468 aligned, so we round to this widest known alignment. */
4470 sp
= align_down (sp
, 16);
4471 struct_addr
= align_down (struct_addr
, 16);
4473 /* Now make space on the stack for the args. */
4474 for (argnum
= 0; argnum
< nargs
; argnum
++)
4476 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
4477 int arglen
= TYPE_LENGTH (arg_type
);
4479 /* Allocate space on the stack. */
4480 len
+= align_up (arglen
, MIPS64_REGSIZE
);
4482 sp
-= align_up (len
, 16);
4485 fprintf_unfiltered (gdb_stdlog
,
4486 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
4487 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4489 /* Initialize the integer and float register pointers. */
4490 argreg
= MIPS_A0_REGNUM
;
4491 float_argreg
= mips_fpa0_regnum (gdbarch
);
4493 /* The struct_return pointer occupies the first parameter-passing reg. */
4497 fprintf_unfiltered (gdb_stdlog
,
4498 "mips_o64_push_dummy_call: "
4499 "struct_return reg=%d %s\n",
4500 argreg
, paddress (gdbarch
, struct_addr
));
4501 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4502 stack_offset
+= MIPS64_REGSIZE
;
4505 /* Now load as many as possible of the first arguments into
4506 registers, and push the rest onto the stack. Loop thru args
4507 from first to last. */
4508 for (argnum
= 0; argnum
< nargs
; argnum
++)
4510 const gdb_byte
*val
;
4511 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4512 struct value
*arg
= args
[argnum
];
4513 struct type
*arg_type
= check_typedef (value_type (arg
));
4514 int len
= TYPE_LENGTH (arg_type
);
4515 enum type_code typecode
= TYPE_CODE (arg_type
);
4518 fprintf_unfiltered (gdb_stdlog
,
4519 "mips_o64_push_dummy_call: %d len=%d type=%d",
4520 argnum
+ 1, len
, (int) typecode
);
4522 val
= value_contents (arg
);
4524 /* Function pointer arguments to mips16 code need to be made into
4526 if (typecode
== TYPE_CODE_PTR
4527 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4529 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4531 if (mips_pc_is_mips16 (addr
))
4533 store_signed_integer (valbuf
, len
, byte_order
,
4534 make_mips16_addr (addr
));
4539 /* Floating point arguments passed in registers have to be
4540 treated specially. On 32-bit architectures, doubles are
4541 passed in register pairs; the even FP register gets the
4542 low word, and the odd FP register gets the high word.
4543 On O64, the first two floating point arguments are also
4544 copied to general registers, because MIPS16 functions
4545 don't use float registers for arguments. This duplication
4546 of arguments in general registers can't hurt non-MIPS16
4547 functions because those registers are normally skipped. */
4549 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4550 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4552 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
4554 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4555 float_argreg
, phex (regval
, len
));
4556 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4558 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4559 argreg
, phex (regval
, len
));
4560 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4562 /* Reserve space for the FP register. */
4563 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4567 /* Copy the argument to general registers or the stack in
4568 register-sized pieces. Large arguments are split between
4569 registers and stack. */
4570 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4571 are treated specially: Irix cc passes them in registers
4572 where gcc sometimes puts them on the stack. For maximum
4573 compatibility, we will put them in both places. */
4574 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4575 && len
% MIPS64_REGSIZE
!= 0);
4578 /* Remember if the argument was written to the stack. */
4579 int stack_used_p
= 0;
4580 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4583 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4586 /* Write this portion of the argument to the stack. */
4587 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4588 || odd_sized_struct
)
4590 /* Should shorter than int integer values be
4591 promoted to int before being stored? */
4592 int longword_offset
= 0;
4595 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4597 if ((typecode
== TYPE_CODE_INT
4598 || typecode
== TYPE_CODE_PTR
4599 || typecode
== TYPE_CODE_FLT
)
4601 longword_offset
= MIPS64_REGSIZE
- len
;
4606 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4607 paddress (gdbarch
, stack_offset
));
4608 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4609 paddress (gdbarch
, longword_offset
));
4612 addr
= sp
+ stack_offset
+ longword_offset
;
4617 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4618 paddress (gdbarch
, addr
));
4619 for (i
= 0; i
< partial_len
; i
++)
4621 fprintf_unfiltered (gdb_stdlog
, "%02x",
4625 write_memory (addr
, val
, partial_len
);
4628 /* Note!!! This is NOT an else clause. Odd sized
4629 structs may go thru BOTH paths. */
4630 /* Write this portion of the argument to a general
4631 purpose register. */
4632 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4634 LONGEST regval
= extract_signed_integer (val
, partial_len
,
4636 /* Value may need to be sign extended, because
4637 mips_isa_regsize() != mips_abi_regsize(). */
4639 /* A non-floating-point argument being passed in a
4640 general register. If a struct or union, and if
4641 the remaining length is smaller than the register
4642 size, we have to adjust the register value on
4645 It does not seem to be necessary to do the
4646 same for integral types. */
4648 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4649 && partial_len
< MIPS64_REGSIZE
4650 && (typecode
== TYPE_CODE_STRUCT
4651 || typecode
== TYPE_CODE_UNION
))
4652 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4656 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4658 phex (regval
, MIPS64_REGSIZE
));
4659 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4662 /* Prevent subsequent floating point arguments from
4663 being passed in floating point registers. */
4664 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4670 /* Compute the offset into the stack at which we will
4671 copy the next parameter.
4673 In older ABIs, the caller reserved space for
4674 registers that contained arguments. This was loosely
4675 refered to as their "home". Consequently, space is
4676 always allocated. */
4678 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4682 fprintf_unfiltered (gdb_stdlog
, "\n");
4685 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4687 /* Return adjusted stack pointer. */
4691 static enum return_value_convention
4692 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4693 struct type
*type
, struct regcache
*regcache
,
4694 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4696 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
4697 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4698 int mips16
= mips_pc_is_mips16 (func_addr
);
4699 enum mips_fval_reg fval_reg
;
4701 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
4702 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4703 || TYPE_CODE (type
) == TYPE_CODE_UNION
4704 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4705 return RETURN_VALUE_STRUCT_CONVENTION
;
4706 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4708 /* A floating-point value. If reading in or copying, then we get it
4709 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
4710 If writing out only, then we put it to both FP0 and GPR2. We do
4711 not support reading in with no function known, if this safety
4712 check ever triggers, then we'll have to try harder. */
4713 gdb_assert (function
|| !readbuf
);
4718 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4721 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
4723 case mips_fval_both
:
4724 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
4727 if (fval_reg
!= mips_fval_gpr
)
4728 mips_xfer_register (gdbarch
, regcache
,
4729 (gdbarch_num_regs (gdbarch
)
4730 + mips_regnum (gdbarch
)->fp0
),
4732 gdbarch_byte_order (gdbarch
),
4733 readbuf
, writebuf
, 0);
4734 if (fval_reg
!= mips_fval_fpr
)
4735 mips_xfer_register (gdbarch
, regcache
,
4736 gdbarch_num_regs (gdbarch
) + 2,
4738 gdbarch_byte_order (gdbarch
),
4739 readbuf
, writebuf
, 0);
4740 return RETURN_VALUE_REGISTER_CONVENTION
;
4744 /* A scalar extract each part but least-significant-byte
4748 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4749 offset
< TYPE_LENGTH (type
);
4750 offset
+= MIPS64_REGSIZE
, regnum
++)
4752 int xfer
= MIPS64_REGSIZE
;
4753 if (offset
+ xfer
> TYPE_LENGTH (type
))
4754 xfer
= TYPE_LENGTH (type
) - offset
;
4756 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4757 offset
, xfer
, regnum
);
4758 mips_xfer_register (gdbarch
, regcache
,
4759 gdbarch_num_regs (gdbarch
) + regnum
,
4760 xfer
, gdbarch_byte_order (gdbarch
),
4761 readbuf
, writebuf
, offset
);
4763 return RETURN_VALUE_REGISTER_CONVENTION
;
4767 /* Floating point register management.
4769 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4770 64bit operations, these early MIPS cpus treat fp register pairs
4771 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4772 registers and offer a compatibility mode that emulates the MIPS2 fp
4773 model. When operating in MIPS2 fp compat mode, later cpu's split
4774 double precision floats into two 32-bit chunks and store them in
4775 consecutive fp regs. To display 64-bit floats stored in this
4776 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4777 Throw in user-configurable endianness and you have a real mess.
4779 The way this works is:
4780 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4781 double-precision value will be split across two logical registers.
4782 The lower-numbered logical register will hold the low-order bits,
4783 regardless of the processor's endianness.
4784 - If we are on a 64-bit processor, and we are looking for a
4785 single-precision value, it will be in the low ordered bits
4786 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4787 save slot in memory.
4788 - If we are in 64-bit mode, everything is straightforward.
4790 Note that this code only deals with "live" registers at the top of the
4791 stack. We will attempt to deal with saved registers later, when
4792 the raw/cooked register interface is in place. (We need a general
4793 interface that can deal with dynamic saved register sizes -- fp
4794 regs could be 32 bits wide in one frame and 64 on the frame above
4797 /* Copy a 32-bit single-precision value from the current frame
4798 into rare_buffer. */
4801 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4802 gdb_byte
*rare_buffer
)
4804 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4805 int raw_size
= register_size (gdbarch
, regno
);
4806 gdb_byte
*raw_buffer
= alloca (raw_size
);
4808 if (!frame_register_read (frame
, regno
, raw_buffer
))
4809 error (_("can't read register %d (%s)"),
4810 regno
, gdbarch_register_name (gdbarch
, regno
));
4813 /* We have a 64-bit value for this register. Find the low-order
4817 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4822 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4826 memcpy (rare_buffer
, raw_buffer
, 4);
4830 /* Copy a 64-bit double-precision value from the current frame into
4831 rare_buffer. This may include getting half of it from the next
4835 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4836 gdb_byte
*rare_buffer
)
4838 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4839 int raw_size
= register_size (gdbarch
, regno
);
4841 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4843 /* We have a 64-bit value for this register, and we should use
4845 if (!frame_register_read (frame
, regno
, rare_buffer
))
4846 error (_("can't read register %d (%s)"),
4847 regno
, gdbarch_register_name (gdbarch
, regno
));
4851 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4853 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4854 internal_error (__FILE__
, __LINE__
,
4855 _("mips_read_fp_register_double: bad access to "
4856 "odd-numbered FP register"));
4858 /* mips_read_fp_register_single will find the correct 32 bits from
4860 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4862 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4863 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4867 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4868 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4874 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4876 { /* Do values for FP (float) regs. */
4877 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4878 gdb_byte
*raw_buffer
;
4879 double doub
, flt1
; /* Doubles extracted from raw hex data. */
4882 raw_buffer
= alloca (2 * register_size (gdbarch
,
4883 mips_regnum (gdbarch
)->fp0
));
4885 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4886 fprintf_filtered (file
, "%*s",
4887 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4890 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4892 struct value_print_options opts
;
4894 /* 4-byte registers: Print hex and floating. Also print even
4895 numbered registers as doubles. */
4896 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4897 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4900 get_formatted_print_options (&opts
, 'x');
4901 print_scalar_formatted (raw_buffer
,
4902 builtin_type (gdbarch
)->builtin_uint32
,
4905 fprintf_filtered (file
, " flt: ");
4907 fprintf_filtered (file
, " <invalid float> ");
4909 fprintf_filtered (file
, "%-17.9g", flt1
);
4911 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4913 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4914 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4917 fprintf_filtered (file
, " dbl: ");
4919 fprintf_filtered (file
, "<invalid double>");
4921 fprintf_filtered (file
, "%-24.17g", doub
);
4926 struct value_print_options opts
;
4928 /* Eight byte registers: print each one as hex, float and double. */
4929 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4930 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
4933 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4934 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
4937 get_formatted_print_options (&opts
, 'x');
4938 print_scalar_formatted (raw_buffer
,
4939 builtin_type (gdbarch
)->builtin_uint64
,
4942 fprintf_filtered (file
, " flt: ");
4944 fprintf_filtered (file
, "<invalid float>");
4946 fprintf_filtered (file
, "%-17.9g", flt1
);
4948 fprintf_filtered (file
, " dbl: ");
4950 fprintf_filtered (file
, "<invalid double>");
4952 fprintf_filtered (file
, "%-24.17g", doub
);
4957 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4960 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4961 struct value_print_options opts
;
4964 if (mips_float_register_p (gdbarch
, regnum
))
4966 mips_print_fp_register (file
, frame
, regnum
);
4970 val
= get_frame_register_value (frame
, regnum
);
4971 if (value_optimized_out (val
))
4973 fprintf_filtered (file
, "%s: [Invalid]",
4974 gdbarch_register_name (gdbarch
, regnum
));
4978 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4980 /* The problem with printing numeric register names (r26, etc.) is that
4981 the user can't use them on input. Probably the best solution is to
4982 fix it so that either the numeric or the funky (a2, etc.) names
4983 are accepted on input. */
4984 if (regnum
< MIPS_NUMREGS
)
4985 fprintf_filtered (file
, "(r%d): ", regnum
);
4987 fprintf_filtered (file
, ": ");
4989 get_formatted_print_options (&opts
, 'x');
4990 val_print_scalar_formatted (value_type (val
),
4991 value_contents_for_printing (val
),
4992 value_embedded_offset (val
),
4997 /* Replacement for generic do_registers_info.
4998 Print regs in pretty columns. */
5001 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5004 fprintf_filtered (file
, " ");
5005 mips_print_fp_register (file
, frame
, regnum
);
5006 fprintf_filtered (file
, "\n");
5011 /* Print a row's worth of GP (int) registers, with name labels above. */
5014 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
5017 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5018 /* Do values for GP (int) regs. */
5019 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
5020 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
5025 /* For GP registers, we print a separate row of names above the vals. */
5026 for (col
= 0, regnum
= start_regnum
;
5027 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
5028 + gdbarch_num_pseudo_regs (gdbarch
);
5031 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
5032 continue; /* unused register */
5033 if (mips_float_register_p (gdbarch
, regnum
))
5034 break; /* End the row: reached FP register. */
5035 /* Large registers are handled separately. */
5036 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
5039 break; /* End the row before this register. */
5041 /* Print this register on a row by itself. */
5042 mips_print_register (file
, frame
, regnum
);
5043 fprintf_filtered (file
, "\n");
5047 fprintf_filtered (file
, " ");
5048 fprintf_filtered (file
,
5049 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
5050 gdbarch_register_name (gdbarch
, regnum
));
5057 /* Print the R0 to R31 names. */
5058 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
5059 fprintf_filtered (file
, "\n R%-4d",
5060 start_regnum
% gdbarch_num_regs (gdbarch
));
5062 fprintf_filtered (file
, "\n ");
5064 /* Now print the values in hex, 4 or 8 to the row. */
5065 for (col
= 0, regnum
= start_regnum
;
5066 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
5067 + gdbarch_num_pseudo_regs (gdbarch
);
5070 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
5071 continue; /* unused register */
5072 if (mips_float_register_p (gdbarch
, regnum
))
5073 break; /* End row: reached FP register. */
5074 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
5075 break; /* End row: large register. */
5077 /* OK: get the data in raw format. */
5078 if (!frame_register_read (frame
, regnum
, raw_buffer
))
5079 error (_("can't read register %d (%s)"),
5080 regnum
, gdbarch_register_name (gdbarch
, regnum
));
5081 /* pad small registers */
5083 byte
< (mips_abi_regsize (gdbarch
)
5084 - register_size (gdbarch
, regnum
)); byte
++)
5085 printf_filtered (" ");
5086 /* Now print the register value in hex, endian order. */
5087 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5089 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
5090 byte
< register_size (gdbarch
, regnum
); byte
++)
5091 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
5093 for (byte
= register_size (gdbarch
, regnum
) - 1;
5095 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
5096 fprintf_filtered (file
, " ");
5099 if (col
> 0) /* ie. if we actually printed anything... */
5100 fprintf_filtered (file
, "\n");
5105 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
5108 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
5109 struct frame_info
*frame
, int regnum
, int all
)
5111 if (regnum
!= -1) /* Do one specified register. */
5113 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
5114 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
5115 error (_("Not a valid register for the current processor type"));
5117 mips_print_register (file
, frame
, regnum
);
5118 fprintf_filtered (file
, "\n");
5121 /* Do all (or most) registers. */
5123 regnum
= gdbarch_num_regs (gdbarch
);
5124 while (regnum
< gdbarch_num_regs (gdbarch
)
5125 + gdbarch_num_pseudo_regs (gdbarch
))
5127 if (mips_float_register_p (gdbarch
, regnum
))
5129 if (all
) /* True for "INFO ALL-REGISTERS" command. */
5130 regnum
= print_fp_register_row (file
, frame
, regnum
);
5132 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
5135 regnum
= print_gp_register_row (file
, frame
, regnum
);
5140 /* Is this a branch with a delay slot? */
5143 is_delayed (unsigned long insn
)
5146 for (i
= 0; i
< NUMOPCODES
; ++i
)
5147 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
5148 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
5150 return (i
< NUMOPCODES
5151 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
5152 | INSN_COND_BRANCH_DELAY
5153 | INSN_COND_BRANCH_LIKELY
)));
5157 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
5158 struct frame_info
*frame
)
5160 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5161 CORE_ADDR pc
= get_frame_pc (frame
);
5162 gdb_byte buf
[MIPS_INSN32_SIZE
];
5164 /* There is no branch delay slot on MIPS16. */
5165 if (mips_pc_is_mips16 (pc
))
5168 if (!breakpoint_here_p (get_frame_address_space (frame
), pc
+ 4))
5171 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
5172 /* If error reading memory, guess that it is not a delayed
5175 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
, byte_order
));
5178 /* To skip prologues, I use this predicate. Returns either PC itself
5179 if the code at PC does not look like a function prologue; otherwise
5180 returns an address that (if we're lucky) follows the prologue. If
5181 LENIENT, then we must skip everything which is involved in setting
5182 up the frame (it's OK to skip more, just so long as we don't skip
5183 anything which might clobber the registers which are being saved.
5184 We must skip more in the case where part of the prologue is in the
5185 delay slot of a non-prologue instruction). */
5188 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5191 CORE_ADDR func_addr
;
5193 /* See if we can determine the end of the prologue via the symbol table.
5194 If so, then return either PC, or the PC after the prologue, whichever
5196 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
5198 CORE_ADDR post_prologue_pc
5199 = skip_prologue_using_sal (gdbarch
, func_addr
);
5200 if (post_prologue_pc
!= 0)
5201 return max (pc
, post_prologue_pc
);
5204 /* Can't determine prologue from the symbol table, need to examine
5207 /* Find an upper limit on the function prologue using the debug
5208 information. If the debug information could not be used to provide
5209 that bound, then use an arbitrary large number as the upper bound. */
5210 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
5212 limit_pc
= pc
+ 100; /* Magic. */
5214 if (mips_pc_is_mips16 (pc
))
5215 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5217 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
5220 /* Check whether the PC is in a function epilogue (32-bit version).
5221 This is a helper function for mips_in_function_epilogue_p. */
5223 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5225 CORE_ADDR func_addr
= 0, func_end
= 0;
5227 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5229 /* The MIPS epilogue is max. 12 bytes long. */
5230 CORE_ADDR addr
= func_end
- 12;
5232 if (addr
< func_addr
+ 4)
5233 addr
= func_addr
+ 4;
5237 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
5239 unsigned long high_word
;
5242 inst
= mips_fetch_instruction (gdbarch
, pc
);
5243 high_word
= (inst
>> 16) & 0xffff;
5245 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
5246 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
5247 && inst
!= 0x03e00008 /* jr $ra */
5248 && inst
!= 0x00000000) /* nop */
5258 /* Check whether the PC is in a function epilogue (16-bit version).
5259 This is a helper function for mips_in_function_epilogue_p. */
5261 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5263 CORE_ADDR func_addr
= 0, func_end
= 0;
5265 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
5267 /* The MIPS epilogue is max. 12 bytes long. */
5268 CORE_ADDR addr
= func_end
- 12;
5270 if (addr
< func_addr
+ 4)
5271 addr
= func_addr
+ 4;
5275 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
5277 unsigned short inst
;
5279 inst
= mips_fetch_instruction (gdbarch
, pc
);
5281 if ((inst
& 0xf800) == 0xf000) /* extend */
5284 if (inst
!= 0x6300 /* addiu $sp,offset */
5285 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
5286 && inst
!= 0xe820 /* jr $ra */
5287 && inst
!= 0xe8a0 /* jrc $ra */
5288 && inst
!= 0x6500) /* nop */
5298 /* The epilogue is defined here as the area at the end of a function,
5299 after an instruction which destroys the function's stack frame. */
5301 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
5303 if (mips_pc_is_mips16 (pc
))
5304 return mips16_in_function_epilogue_p (gdbarch
, pc
);
5306 return mips32_in_function_epilogue_p (gdbarch
, pc
);
5309 /* Root of all "set mips "/"show mips " commands. This will eventually be
5310 used for all MIPS-specific commands. */
5313 show_mips_command (char *args
, int from_tty
)
5315 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
5319 set_mips_command (char *args
, int from_tty
)
5322 ("\"set mips\" must be followed by an appropriate subcommand.\n");
5323 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
5326 /* Commands to show/set the MIPS FPU type. */
5329 show_mipsfpu_command (char *args
, int from_tty
)
5333 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5336 ("The MIPS floating-point coprocessor is unknown "
5337 "because the current architecture is not MIPS.\n");
5341 switch (MIPS_FPU_TYPE (target_gdbarch
))
5343 case MIPS_FPU_SINGLE
:
5344 fpu
= "single-precision";
5346 case MIPS_FPU_DOUBLE
:
5347 fpu
= "double-precision";
5350 fpu
= "absent (none)";
5353 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5355 if (mips_fpu_type_auto
)
5356 printf_unfiltered ("The MIPS floating-point coprocessor "
5357 "is set automatically (currently %s)\n",
5361 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
5366 set_mipsfpu_command (char *args
, int from_tty
)
5368 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
5369 "\"single\",\"none\" or \"auto\".\n");
5370 show_mipsfpu_command (args
, from_tty
);
5374 set_mipsfpu_single_command (char *args
, int from_tty
)
5376 struct gdbarch_info info
;
5377 gdbarch_info_init (&info
);
5378 mips_fpu_type
= MIPS_FPU_SINGLE
;
5379 mips_fpu_type_auto
= 0;
5380 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5381 instead of relying on globals. Doing that would let generic code
5382 handle the search for this specific architecture. */
5383 if (!gdbarch_update_p (info
))
5384 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5388 set_mipsfpu_double_command (char *args
, int from_tty
)
5390 struct gdbarch_info info
;
5391 gdbarch_info_init (&info
);
5392 mips_fpu_type
= MIPS_FPU_DOUBLE
;
5393 mips_fpu_type_auto
= 0;
5394 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5395 instead of relying on globals. Doing that would let generic code
5396 handle the search for this specific architecture. */
5397 if (!gdbarch_update_p (info
))
5398 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5402 set_mipsfpu_none_command (char *args
, int from_tty
)
5404 struct gdbarch_info info
;
5405 gdbarch_info_init (&info
);
5406 mips_fpu_type
= MIPS_FPU_NONE
;
5407 mips_fpu_type_auto
= 0;
5408 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
5409 instead of relying on globals. Doing that would let generic code
5410 handle the search for this specific architecture. */
5411 if (!gdbarch_update_p (info
))
5412 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
5416 set_mipsfpu_auto_command (char *args
, int from_tty
)
5418 mips_fpu_type_auto
= 1;
5421 /* Attempt to identify the particular processor model by reading the
5422 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
5423 the relevant processor still exists (it dates back to '94) and
5424 secondly this is not the way to do this. The processor type should
5425 be set by forcing an architecture change. */
5428 deprecated_mips_set_processor_regs_hack (void)
5430 struct regcache
*regcache
= get_current_regcache ();
5431 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
5432 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5435 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
5436 if ((prid
& ~0xf) == 0x700)
5437 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
5440 /* Just like reinit_frame_cache, but with the right arguments to be
5441 callable as an sfunc. */
5444 reinit_frame_cache_sfunc (char *args
, int from_tty
,
5445 struct cmd_list_element
*c
)
5447 reinit_frame_cache ();
5451 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
5453 /* FIXME: cagney/2003-06-26: Is this even necessary? The
5454 disassembler needs to be able to locally determine the ISA, and
5455 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
5457 if (mips_pc_is_mips16 (memaddr
))
5458 info
->mach
= bfd_mach_mips16
;
5460 /* Round down the instruction address to the appropriate boundary. */
5461 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
5463 /* Set the disassembler options. */
5464 if (!info
->disassembler_options
)
5465 /* This string is not recognized explicitly by the disassembler,
5466 but it tells the disassembler to not try to guess the ABI from
5467 the bfd elf headers, such that, if the user overrides the ABI
5468 of a program linked as NewABI, the disassembly will follow the
5469 register naming conventions specified by the user. */
5470 info
->disassembler_options
= "gpr-names=32";
5472 /* Call the appropriate disassembler based on the target endian-ness. */
5473 if (info
->endian
== BFD_ENDIAN_BIG
)
5474 return print_insn_big_mips (memaddr
, info
);
5476 return print_insn_little_mips (memaddr
, info
);
5480 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
5482 /* Set up the disassembler info, so that we get the right
5483 register names from libopcodes. */
5484 info
->disassembler_options
= "gpr-names=n32";
5485 info
->flavour
= bfd_target_elf_flavour
;
5487 return gdb_print_insn_mips (memaddr
, info
);
5491 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
5493 /* Set up the disassembler info, so that we get the right
5494 register names from libopcodes. */
5495 info
->disassembler_options
= "gpr-names=64";
5496 info
->flavour
= bfd_target_elf_flavour
;
5498 return gdb_print_insn_mips (memaddr
, info
);
5501 /* This function implements gdbarch_breakpoint_from_pc. It uses the
5502 program counter value to determine whether a 16- or 32-bit breakpoint
5503 should be used. It returns a pointer to a string of bytes that encode a
5504 breakpoint instruction, stores the length of the string to *lenptr, and
5505 adjusts pc (if necessary) to point to the actual memory location where
5506 the breakpoint should be inserted. */
5508 static const gdb_byte
*
5509 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
5510 CORE_ADDR
*pcptr
, int *lenptr
)
5512 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5514 if (mips_pc_is_mips16 (*pcptr
))
5516 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
5517 *pcptr
= unmake_mips16_addr (*pcptr
);
5518 *lenptr
= sizeof (mips16_big_breakpoint
);
5519 return mips16_big_breakpoint
;
5523 /* The IDT board uses an unusual breakpoint value, and
5524 sometimes gets confused when it sees the usual MIPS
5525 breakpoint instruction. */
5526 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
5527 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
5528 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
5529 /* Likewise, IRIX appears to expect a different breakpoint,
5530 although this is not apparent until you try to use pthreads. */
5531 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
5533 *lenptr
= sizeof (big_breakpoint
);
5535 if (strcmp (target_shortname
, "mips") == 0)
5536 return idt_big_breakpoint
;
5537 else if (strcmp (target_shortname
, "ddb") == 0
5538 || strcmp (target_shortname
, "pmon") == 0
5539 || strcmp (target_shortname
, "lsi") == 0)
5540 return pmon_big_breakpoint
;
5541 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
5542 return irix_big_breakpoint
;
5544 return big_breakpoint
;
5549 if (mips_pc_is_mips16 (*pcptr
))
5551 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
5552 *pcptr
= unmake_mips16_addr (*pcptr
);
5553 *lenptr
= sizeof (mips16_little_breakpoint
);
5554 return mips16_little_breakpoint
;
5558 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5559 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5560 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5562 *lenptr
= sizeof (little_breakpoint
);
5564 if (strcmp (target_shortname
, "mips") == 0)
5565 return idt_little_breakpoint
;
5566 else if (strcmp (target_shortname
, "ddb") == 0
5567 || strcmp (target_shortname
, "pmon") == 0
5568 || strcmp (target_shortname
, "lsi") == 0)
5569 return pmon_little_breakpoint
;
5571 return little_breakpoint
;
5576 /* Return non-zero if the ADDR instruction has a branch delay slot
5577 (i.e. it is a jump or branch instruction). This function is based
5578 on mips32_next_pc. */
5581 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
5583 gdb_byte buf
[MIPS_INSN32_SIZE
];
5590 status
= target_read_memory (addr
, buf
, MIPS_INSN32_SIZE
);
5594 inst
= mips_fetch_instruction (gdbarch
, addr
);
5595 op
= itype_op (inst
);
5596 if ((inst
& 0xe0000000) != 0)
5598 rs
= itype_rs (inst
);
5599 rt
= itype_rt (inst
);
5600 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
5601 || op
== 29 /* JALX: bits 011101 */
5604 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
5605 || (rs
== 9 && (rt
& 0x2) == 0)
5606 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
5607 || (rs
== 10 && (rt
& 0x2) == 0))));
5608 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
5611 switch (op
& 0x07) /* extract bits 28,27,26 */
5613 case 0: /* SPECIAL */
5614 op
= rtype_funct (inst
);
5615 return (op
== 8 /* JR */
5616 || op
== 9); /* JALR */
5617 break; /* end SPECIAL */
5618 case 1: /* REGIMM */
5619 rs
= itype_rs (inst
);
5620 rt
= itype_rt (inst
); /* branch condition */
5621 return ((rt
& 0xc) == 0
5622 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
5623 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
5624 || ((rt
& 0x1e) == 0x1c && rs
== 0));
5625 /* BPOSGE32, BPOSGE64: bits 1110x */
5626 break; /* end REGIMM */
5627 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
5633 /* Return non-zero if the ADDR instruction, which must be a 32-bit
5634 instruction if MUSTBE32 is set or can be any instruction otherwise,
5635 has a branch delay slot (i.e. it is a non-compact jump instruction). */
5638 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
5641 gdb_byte buf
[MIPS_INSN16_SIZE
];
5642 unsigned short inst
;
5645 status
= target_read_memory (addr
, buf
, MIPS_INSN16_SIZE
);
5649 inst
= mips_fetch_instruction (gdbarch
, addr
);
5651 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
5652 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
5655 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
5656 This assumes KSSEG exists. */
5659 mips_segment_boundary (CORE_ADDR bpaddr
)
5661 CORE_ADDR mask
= CORE_ADDR_MAX
;
5664 if (sizeof (CORE_ADDR
) == 8)
5665 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
5666 a compiler warning produced where CORE_ADDR is a 32-bit type even
5667 though in that case this is dead code). */
5668 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
5671 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
5672 segsize
= 29; /* 32-bit compatibility segment */
5674 segsize
= 62; /* xkseg */
5676 case 2: /* xkphys */
5679 default: /* xksseg (1), xkuseg/kuseg (0) */
5683 else if (bpaddr
& 0x80000000) /* kernel segment */
5686 segsize
= 31; /* user segment */
5688 return bpaddr
& mask
;
5691 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
5692 it backwards if necessary. Return the address of the new location. */
5695 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
5697 CORE_ADDR prev_addr
;
5699 CORE_ADDR func_addr
;
5701 /* If a breakpoint is set on the instruction in a branch delay slot,
5702 GDB gets confused. When the breakpoint is hit, the PC isn't on
5703 the instruction in the branch delay slot, the PC will point to
5704 the branch instruction. Since the PC doesn't match any known
5705 breakpoints, GDB reports a trap exception.
5707 There are two possible fixes for this problem.
5709 1) When the breakpoint gets hit, see if the BD bit is set in the
5710 Cause register (which indicates the last exception occurred in a
5711 branch delay slot). If the BD bit is set, fix the PC to point to
5712 the instruction in the branch delay slot.
5714 2) When the user sets the breakpoint, don't allow him to set the
5715 breakpoint on the instruction in the branch delay slot. Instead
5716 move the breakpoint to the branch instruction (which will have
5719 The problem with the first solution is that if the user then
5720 single-steps the processor, the branch instruction will get
5721 skipped (since GDB thinks the PC is on the instruction in the
5724 So, we'll use the second solution. To do this we need to know if
5725 the instruction we're trying to set the breakpoint on is in the
5726 branch delay slot. */
5728 boundary
= mips_segment_boundary (bpaddr
);
5730 /* Make sure we don't scan back before the beginning of the current
5731 function, since we may fetch constant data or insns that look like
5732 a jump. Of course we might do that anyway if the compiler has
5733 moved constants inline. :-( */
5734 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
5735 && func_addr
> boundary
&& func_addr
<= bpaddr
)
5736 boundary
= func_addr
;
5738 if (!mips_pc_is_mips16 (bpaddr
))
5740 if (bpaddr
== boundary
)
5743 /* If the previous instruction has a branch delay slot, we have
5744 to move the breakpoint to the branch instruction. */
5745 prev_addr
= bpaddr
- 4;
5746 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
5751 CORE_ADDR addr
, jmpaddr
;
5754 boundary
= unmake_mips16_addr (boundary
);
5756 /* The only MIPS16 instructions with delay slots are JAL, JALX,
5757 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
5758 so try for that first, then try the 2 byte JALR/JR.
5759 FIXME: We have to assume that bpaddr is not the second half
5760 of an extended instruction. */
5764 for (i
= 1; i
< 4; i
++)
5766 if (unmake_mips16_addr (addr
) == boundary
)
5769 if (i
== 1 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 0))
5770 /* Looks like a JR/JALR at [target-1], but it could be
5771 the second word of a previous JAL/JALX, so record it
5772 and check back one more. */
5775 && mips16_instruction_has_delay_slot (gdbarch
, addr
, 1))
5778 /* Looks like a JAL/JALX at [target-2], but it could also
5779 be the second word of a previous JAL/JALX, record it,
5780 and check back one more. */
5783 /* Looks like a JAL/JALX at [target-3], so any previously
5784 recorded JAL/JALX or JR/JALR must be wrong, because:
5787 -2: JAL-ext (can't be JAL/JALX)
5788 -1: bdslot (can't be JR/JALR)
5791 Of course it could be another JAL-ext which looks
5792 like a JAL, but in that case we'd have broken out
5793 of this loop at [target-2]:
5797 -2: bdslot (can't be jmp)
5804 /* Not a jump instruction: if we're at [target-1] this
5805 could be the second word of a JAL/JALX, so continue;
5806 otherwise we're done. */
5819 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
5820 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
5823 mips_is_stub_suffix (const char *suffix
, int zero
)
5828 return zero
&& suffix
[1] == '\0';
5830 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
5835 return suffix
[1] == '\0';
5841 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
5842 call stubs, one of sf, df, sc, or dc. */
5845 mips_is_stub_mode (const char *mode
)
5847 return ((mode
[0] == 's' || mode
[0] == 'd')
5848 && (mode
[1] == 'f' || mode
[1] == 'c'));
5851 /* Code at PC is a compiler-generated stub. Such a stub for a function
5852 bar might have a name like __fn_stub_bar, and might look like this:
5859 followed by (or interspersed with):
5866 addiu $25, $25, %lo(bar)
5869 ($1 may be used in old code; for robustness we accept any register)
5872 lui $28, %hi(_gp_disp)
5873 addiu $28, $28, %lo(_gp_disp)
5876 addiu $25, $25, %lo(bar)
5879 In the case of a __call_stub_bar stub, the sequence to set up
5880 arguments might look like this:
5887 followed by (or interspersed with) one of the jump sequences above.
5889 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
5890 of J or JR, respectively, followed by:
5896 We are at the beginning of the stub here, and scan down and extract
5897 the target address from the jump immediate instruction or, if a jump
5898 register instruction is used, from the register referred. Return
5899 the value of PC calculated or 0 if inconclusive.
5901 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
5904 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
5906 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5907 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5908 int addrreg
= MIPS_ZERO_REGNUM
;
5909 CORE_ADDR start_pc
= pc
;
5910 CORE_ADDR target_pc
= 0;
5917 status
== 0 && target_pc
== 0 && i
< 20;
5918 i
++, pc
+= MIPS_INSN32_SIZE
)
5920 ULONGEST inst
= mips_fetch_instruction (gdbarch
, pc
);
5926 switch (itype_op (inst
))
5928 case 0: /* SPECIAL */
5929 switch (rtype_funct (inst
))
5933 rs
= rtype_rs (inst
);
5934 if (rs
== MIPS_GP_REGNUM
)
5935 target_pc
= gp
; /* Hmm... */
5936 else if (rs
== addrreg
)
5940 case 0x21: /* ADDU */
5941 rt
= rtype_rt (inst
);
5942 rs
= rtype_rs (inst
);
5943 rd
= rtype_rd (inst
);
5944 if (rd
== MIPS_GP_REGNUM
5945 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
5946 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
5954 target_pc
= jtype_target (inst
) << 2;
5955 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
5959 rt
= itype_rt (inst
);
5960 rs
= itype_rs (inst
);
5963 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
5964 if (rt
== MIPS_GP_REGNUM
)
5966 else if (rt
== addrreg
)
5972 rt
= itype_rt (inst
);
5973 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
5974 if (rt
== MIPS_GP_REGNUM
)
5976 else if (rt
!= MIPS_ZERO_REGNUM
)
5984 rt
= itype_rt (inst
);
5985 rs
= itype_rs (inst
);
5986 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
5987 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
5991 memset (buf
, 0, sizeof (buf
));
5992 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
5994 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
6003 /* If PC is in a MIPS16 call or return stub, return the address of the
6004 target PC, which is either the callee or the caller. There are several
6005 cases which must be handled:
6007 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
6008 and the target PC is in $31 ($ra).
6009 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
6010 and the target PC is in $2.
6011 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
6012 i.e. before the JALR instruction, this is effectively a call stub
6013 and the target PC is in $2. Otherwise this is effectively
6014 a return stub and the target PC is in $18.
6015 * If the PC is at the start of __call_stub_fp_*, i.e. before the
6016 JAL or JALR instruction, this is effectively a call stub and the
6017 target PC is buried in the instruction stream. Otherwise this
6018 is effectively a return stub and the target PC is in $18.
6019 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
6020 stub and the target PC is buried in the instruction stream.
6022 See the source code for the stubs in gcc/config/mips/mips16.S, or the
6023 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
6027 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
6029 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6030 CORE_ADDR start_addr
;
6034 /* Find the starting address and name of the function containing the PC. */
6035 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
6038 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
6039 and the target PC is in $31 ($ra). */
6040 prefixlen
= strlen (mips_str_mips16_ret_stub
);
6041 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
6042 && mips_is_stub_mode (name
+ prefixlen
)
6043 && name
[prefixlen
+ 2] == '\0')
6044 return get_frame_register_signed
6045 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
6047 /* If the PC is in __mips16_call_stub_*, this is one of the call
6048 call/return stubs. */
6049 prefixlen
= strlen (mips_str_mips16_call_stub
);
6050 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
6052 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
6053 and the target PC is in $2. */
6054 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
6055 return get_frame_register_signed
6056 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
6058 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
6059 i.e. before the JALR instruction, this is effectively a call stub
6060 and the target PC is in $2. Otherwise this is effectively
6061 a return stub and the target PC is in $18. */
6062 else if (mips_is_stub_mode (name
+ prefixlen
)
6063 && name
[prefixlen
+ 2] == '_'
6064 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
6066 if (pc
== start_addr
)
6067 /* This is the 'call' part of a call stub. The return
6068 address is in $2. */
6069 return get_frame_register_signed
6070 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
6072 /* This is the 'return' part of a call stub. The return
6073 address is in $18. */
6074 return get_frame_register_signed
6075 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
6078 return 0; /* Not a stub. */
6081 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
6082 compiler-generated call or call/return stubs. */
6083 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
6084 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
6086 if (pc
== start_addr
)
6087 /* This is the 'call' part of a call stub. Call this helper
6088 to scan through this code for interesting instructions
6089 and determine the final PC. */
6090 return mips_get_mips16_fn_stub_pc (frame
, pc
);
6092 /* This is the 'return' part of a call stub. The return address
6094 return get_frame_register_signed
6095 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
6098 return 0; /* Not a stub. */
6101 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
6102 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
6105 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
6107 CORE_ADDR start_addr
;
6110 /* Find the starting address of the function containing the PC. */
6111 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
6114 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
6115 the start, i.e. after the JALR instruction, this is effectively
6117 prefixlen
= strlen (mips_str_mips16_call_stub
);
6118 if (pc
!= start_addr
6119 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
6120 && mips_is_stub_mode (name
+ prefixlen
)
6121 && name
[prefixlen
+ 2] == '_'
6122 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
6125 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
6126 the JAL or JALR instruction, this is effectively a return stub. */
6127 prefixlen
= strlen (mips_str_call_fp_stub
);
6128 if (pc
!= start_addr
6129 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
6132 /* Consume the .pic. prefix of any PIC stub, this function must return
6133 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
6134 or the call stub path will trigger in handle_inferior_event causing
6136 prefixlen
= strlen (mips_str_pic
);
6137 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
6140 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
6141 prefixlen
= strlen (mips_str_mips16_ret_stub
);
6142 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
6143 && mips_is_stub_mode (name
+ prefixlen
)
6144 && name
[prefixlen
+ 2] == '\0')
6147 return 0; /* Not a stub. */
6150 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
6151 PC of the stub target. The stub just loads $t9 and jumps to it,
6152 so that $t9 has the correct value at function entry. */
6155 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
6157 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6158 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6159 struct minimal_symbol
*msym
;
6161 gdb_byte stub_code
[16];
6162 int32_t stub_words
[4];
6164 /* The stub for foo is named ".pic.foo", and is either two
6165 instructions inserted before foo or a three instruction sequence
6166 which jumps to foo. */
6167 msym
= lookup_minimal_symbol_by_pc (pc
);
6169 || SYMBOL_VALUE_ADDRESS (msym
) != pc
6170 || SYMBOL_LINKAGE_NAME (msym
) == NULL
6171 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
6174 /* A two-instruction header. */
6175 if (MSYMBOL_SIZE (msym
) == 8)
6178 /* A three-instruction (plus delay slot) trampoline. */
6179 if (MSYMBOL_SIZE (msym
) == 16)
6181 if (target_read_memory (pc
, stub_code
, 16) != 0)
6183 for (i
= 0; i
< 4; i
++)
6184 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
6187 /* A stub contains these instructions:
6190 addiu t9, t9, %lo(target)
6193 This works even for N64, since stubs are only generated with
6195 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
6196 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
6197 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
6198 && stub_words
[3] == 0x00000000)
6199 return ((((stub_words
[0] & 0x0000ffff) << 16)
6200 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
6203 /* Not a recognized stub. */
6208 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
6210 CORE_ADDR requested_pc
= pc
;
6211 CORE_ADDR target_pc
;
6218 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
6222 if (is_mips16_addr (pc
))
6223 pc
= unmake_mips16_addr (pc
);
6226 new_pc
= find_solib_trampoline_target (frame
, pc
);
6230 if (is_mips16_addr (pc
))
6231 pc
= unmake_mips16_addr (pc
);
6234 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
6238 if (is_mips16_addr (pc
))
6239 pc
= unmake_mips16_addr (pc
);
6242 while (pc
!= target_pc
);
6244 return pc
!= requested_pc
? pc
: 0;
6247 /* Convert a dbx stab register number (from `r' declaration) to a GDB
6248 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
6251 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
6254 if (num
>= 0 && num
< 32)
6256 else if (num
>= 38 && num
< 70)
6257 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
6259 regnum
= mips_regnum (gdbarch
)->hi
;
6261 regnum
= mips_regnum (gdbarch
)->lo
;
6262 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
6263 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
6265 /* This will hopefully (eventually) provoke a warning. Should
6266 we be calling complaint() here? */
6267 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
6268 return gdbarch_num_regs (gdbarch
) + regnum
;
6272 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
6273 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
6276 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
6279 if (num
>= 0 && num
< 32)
6281 else if (num
>= 32 && num
< 64)
6282 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
6284 regnum
= mips_regnum (gdbarch
)->hi
;
6286 regnum
= mips_regnum (gdbarch
)->lo
;
6287 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
6288 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
6290 /* This will hopefully (eventually) provoke a warning. Should we
6291 be calling complaint() here? */
6292 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
6293 return gdbarch_num_regs (gdbarch
) + regnum
;
6297 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
6299 /* Only makes sense to supply raw registers. */
6300 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
6301 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
6302 decide if it is valid. Should instead define a standard sim/gdb
6303 register numbering scheme. */
6304 if (gdbarch_register_name (gdbarch
,
6305 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
6306 && gdbarch_register_name (gdbarch
,
6307 gdbarch_num_regs (gdbarch
)
6308 + regnum
)[0] != '\0')
6311 return LEGACY_SIM_REGNO_IGNORE
;
6315 /* Convert an integer into an address. Extracting the value signed
6316 guarantees a correctly sign extended address. */
6319 mips_integer_to_address (struct gdbarch
*gdbarch
,
6320 struct type
*type
, const gdb_byte
*buf
)
6322 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6323 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
6326 /* Dummy virtual frame pointer method. This is no more or less accurate
6327 than most other architectures; we just need to be explicit about it,
6328 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
6329 an assertion failure. */
6332 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
6333 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
6335 *reg
= MIPS_SP_REGNUM
;
6340 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
6342 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
6343 const char *name
= bfd_get_section_name (abfd
, sect
);
6345 if (*abip
!= MIPS_ABI_UNKNOWN
)
6348 if (strncmp (name
, ".mdebug.", 8) != 0)
6351 if (strcmp (name
, ".mdebug.abi32") == 0)
6352 *abip
= MIPS_ABI_O32
;
6353 else if (strcmp (name
, ".mdebug.abiN32") == 0)
6354 *abip
= MIPS_ABI_N32
;
6355 else if (strcmp (name
, ".mdebug.abi64") == 0)
6356 *abip
= MIPS_ABI_N64
;
6357 else if (strcmp (name
, ".mdebug.abiO64") == 0)
6358 *abip
= MIPS_ABI_O64
;
6359 else if (strcmp (name
, ".mdebug.eabi32") == 0)
6360 *abip
= MIPS_ABI_EABI32
;
6361 else if (strcmp (name
, ".mdebug.eabi64") == 0)
6362 *abip
= MIPS_ABI_EABI64
;
6364 warning (_("unsupported ABI %s."), name
+ 8);
6368 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
6370 int *lbp
= (int *) obj
;
6371 const char *name
= bfd_get_section_name (abfd
, sect
);
6373 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
6375 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
6377 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
6378 warning (_("unrecognized .gcc_compiled_longXX"));
6381 static enum mips_abi
6382 global_mips_abi (void)
6386 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
6387 if (mips_abi_strings
[i
] == mips_abi_string
)
6388 return (enum mips_abi
) i
;
6390 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
6394 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
6396 /* If the size matches the set of 32-bit or 64-bit integer registers,
6397 assume that's what we've got. */
6398 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
6399 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
6401 /* If the size matches the full set of registers GDB traditionally
6402 knows about, including floating point, for either 32-bit or
6403 64-bit, assume that's what we've got. */
6404 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
6405 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
6407 /* Otherwise we don't have a useful guess. */
6410 static struct value
*
6411 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
6413 const int *reg_p
= baton
;
6414 return value_of_register (*reg_p
, frame
);
6417 static struct gdbarch
*
6418 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
6420 struct gdbarch
*gdbarch
;
6421 struct gdbarch_tdep
*tdep
;
6423 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
6425 enum mips_fpu_type fpu_type
;
6426 struct tdesc_arch_data
*tdesc_data
= NULL
;
6427 int elf_fpu_type
= 0;
6428 const char **reg_names
;
6429 struct mips_regnum mips_regnum
, *regnum
;
6433 /* Fill in the OS dependent register numbers and names. */
6434 if (info
.osabi
== GDB_OSABI_IRIX
)
6436 mips_regnum
.fp0
= 32;
6437 mips_regnum
.pc
= 64;
6438 mips_regnum
.cause
= 65;
6439 mips_regnum
.badvaddr
= 66;
6440 mips_regnum
.hi
= 67;
6441 mips_regnum
.lo
= 68;
6442 mips_regnum
.fp_control_status
= 69;
6443 mips_regnum
.fp_implementation_revision
= 70;
6444 mips_regnum
.dspacc
= dspacc
= -1;
6445 mips_regnum
.dspctl
= dspctl
= -1;
6447 reg_names
= mips_irix_reg_names
;
6449 else if (info
.osabi
== GDB_OSABI_LINUX
)
6451 mips_regnum
.fp0
= 38;
6452 mips_regnum
.pc
= 37;
6453 mips_regnum
.cause
= 36;
6454 mips_regnum
.badvaddr
= 35;
6455 mips_regnum
.hi
= 34;
6456 mips_regnum
.lo
= 33;
6457 mips_regnum
.fp_control_status
= 70;
6458 mips_regnum
.fp_implementation_revision
= 71;
6459 mips_regnum
.dspacc
= -1;
6460 mips_regnum
.dspctl
= -1;
6464 reg_names
= mips_linux_reg_names
;
6468 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
6469 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
6470 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
6471 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
6472 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
6473 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
6474 mips_regnum
.fp_control_status
= 70;
6475 mips_regnum
.fp_implementation_revision
= 71;
6476 mips_regnum
.dspacc
= dspacc
= -1;
6477 mips_regnum
.dspctl
= dspctl
= -1;
6478 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
6479 if (info
.bfd_arch_info
!= NULL
6480 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
6481 reg_names
= mips_tx39_reg_names
;
6483 reg_names
= mips_generic_reg_names
;
6486 /* Check any target description for validity. */
6487 if (tdesc_has_registers (info
.target_desc
))
6489 static const char *const mips_gprs
[] = {
6490 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6491 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6492 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6493 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6495 static const char *const mips_fprs
[] = {
6496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
6502 const struct tdesc_feature
*feature
;
6505 feature
= tdesc_find_feature (info
.target_desc
,
6506 "org.gnu.gdb.mips.cpu");
6507 if (feature
== NULL
)
6510 tdesc_data
= tdesc_data_alloc ();
6513 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
6514 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
6518 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6519 mips_regnum
.lo
, "lo");
6520 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6521 mips_regnum
.hi
, "hi");
6522 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6523 mips_regnum
.pc
, "pc");
6527 tdesc_data_cleanup (tdesc_data
);
6531 feature
= tdesc_find_feature (info
.target_desc
,
6532 "org.gnu.gdb.mips.cp0");
6533 if (feature
== NULL
)
6535 tdesc_data_cleanup (tdesc_data
);
6540 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6541 mips_regnum
.badvaddr
, "badvaddr");
6542 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6543 MIPS_PS_REGNUM
, "status");
6544 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6545 mips_regnum
.cause
, "cause");
6549 tdesc_data_cleanup (tdesc_data
);
6553 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
6554 backend is not prepared for that, though. */
6555 feature
= tdesc_find_feature (info
.target_desc
,
6556 "org.gnu.gdb.mips.fpu");
6557 if (feature
== NULL
)
6559 tdesc_data_cleanup (tdesc_data
);
6564 for (i
= 0; i
< 32; i
++)
6565 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6566 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
6568 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6569 mips_regnum
.fp_control_status
,
6572 &= tdesc_numbered_register (feature
, tdesc_data
,
6573 mips_regnum
.fp_implementation_revision
,
6578 tdesc_data_cleanup (tdesc_data
);
6584 feature
= tdesc_find_feature (info
.target_desc
,
6585 "org.gnu.gdb.mips.dsp");
6586 /* The DSP registers are optional; it's OK if they are absent. */
6587 if (feature
!= NULL
)
6591 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6592 dspacc
+ i
++, "hi1");
6593 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6594 dspacc
+ i
++, "lo1");
6595 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6596 dspacc
+ i
++, "hi2");
6597 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6598 dspacc
+ i
++, "lo2");
6599 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6600 dspacc
+ i
++, "hi3");
6601 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6602 dspacc
+ i
++, "lo3");
6604 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6609 tdesc_data_cleanup (tdesc_data
);
6613 mips_regnum
.dspacc
= dspacc
;
6614 mips_regnum
.dspctl
= dspctl
;
6618 /* It would be nice to detect an attempt to use a 64-bit ABI
6619 when only 32-bit registers are provided. */
6623 /* First of all, extract the elf_flags, if available. */
6624 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6625 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
6626 else if (arches
!= NULL
)
6627 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
6631 fprintf_unfiltered (gdb_stdlog
,
6632 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
6634 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
6635 switch ((elf_flags
& EF_MIPS_ABI
))
6637 case E_MIPS_ABI_O32
:
6638 found_abi
= MIPS_ABI_O32
;
6640 case E_MIPS_ABI_O64
:
6641 found_abi
= MIPS_ABI_O64
;
6643 case E_MIPS_ABI_EABI32
:
6644 found_abi
= MIPS_ABI_EABI32
;
6646 case E_MIPS_ABI_EABI64
:
6647 found_abi
= MIPS_ABI_EABI64
;
6650 if ((elf_flags
& EF_MIPS_ABI2
))
6651 found_abi
= MIPS_ABI_N32
;
6653 found_abi
= MIPS_ABI_UNKNOWN
;
6657 /* GCC creates a pseudo-section whose name describes the ABI. */
6658 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
6659 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
6661 /* If we have no useful BFD information, use the ABI from the last
6662 MIPS architecture (if there is one). */
6663 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
6664 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
6666 /* Try the architecture for any hint of the correct ABI. */
6667 if (found_abi
== MIPS_ABI_UNKNOWN
6668 && info
.bfd_arch_info
!= NULL
6669 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6671 switch (info
.bfd_arch_info
->mach
)
6673 case bfd_mach_mips3900
:
6674 found_abi
= MIPS_ABI_EABI32
;
6676 case bfd_mach_mips4100
:
6677 case bfd_mach_mips5000
:
6678 found_abi
= MIPS_ABI_EABI64
;
6680 case bfd_mach_mips8000
:
6681 case bfd_mach_mips10000
:
6682 /* On Irix, ELF64 executables use the N64 ABI. The
6683 pseudo-sections which describe the ABI aren't present
6684 on IRIX. (Even for executables created by gcc.) */
6685 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6686 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6687 found_abi
= MIPS_ABI_N64
;
6689 found_abi
= MIPS_ABI_N32
;
6694 /* Default 64-bit objects to N64 instead of O32. */
6695 if (found_abi
== MIPS_ABI_UNKNOWN
6696 && info
.abfd
!= NULL
6697 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
6698 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6699 found_abi
= MIPS_ABI_N64
;
6702 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
6705 /* What has the user specified from the command line? */
6706 wanted_abi
= global_mips_abi ();
6708 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
6711 /* Now that we have found what the ABI for this binary would be,
6712 check whether the user is overriding it. */
6713 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
6714 mips_abi
= wanted_abi
;
6715 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
6716 mips_abi
= found_abi
;
6718 mips_abi
= MIPS_ABI_O32
;
6720 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
6723 /* Also used when doing an architecture lookup. */
6725 fprintf_unfiltered (gdb_stdlog
,
6726 "mips_gdbarch_init: "
6727 "mips64_transfers_32bit_regs_p = %d\n",
6728 mips64_transfers_32bit_regs_p
);
6730 /* Determine the MIPS FPU type. */
6733 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
6734 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6735 Tag_GNU_MIPS_ABI_FP
);
6736 #endif /* HAVE_ELF */
6738 if (!mips_fpu_type_auto
)
6739 fpu_type
= mips_fpu_type
;
6740 else if (elf_fpu_type
!= 0)
6742 switch (elf_fpu_type
)
6745 fpu_type
= MIPS_FPU_DOUBLE
;
6748 fpu_type
= MIPS_FPU_SINGLE
;
6752 /* Soft float or unknown. */
6753 fpu_type
= MIPS_FPU_NONE
;
6757 else if (info
.bfd_arch_info
!= NULL
6758 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
6759 switch (info
.bfd_arch_info
->mach
)
6761 case bfd_mach_mips3900
:
6762 case bfd_mach_mips4100
:
6763 case bfd_mach_mips4111
:
6764 case bfd_mach_mips4120
:
6765 fpu_type
= MIPS_FPU_NONE
;
6767 case bfd_mach_mips4650
:
6768 fpu_type
= MIPS_FPU_SINGLE
;
6771 fpu_type
= MIPS_FPU_DOUBLE
;
6774 else if (arches
!= NULL
)
6775 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
6777 fpu_type
= MIPS_FPU_DOUBLE
;
6779 fprintf_unfiltered (gdb_stdlog
,
6780 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
6782 /* Check for blatant incompatibilities. */
6784 /* If we have only 32-bit registers, then we can't debug a 64-bit
6786 if (info
.target_desc
6787 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
6788 && mips_abi
!= MIPS_ABI_EABI32
6789 && mips_abi
!= MIPS_ABI_O32
)
6791 if (tdesc_data
!= NULL
)
6792 tdesc_data_cleanup (tdesc_data
);
6796 /* Try to find a pre-existing architecture. */
6797 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6799 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6801 /* MIPS needs to be pedantic about which ABI the object is
6803 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
6805 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
6807 /* Need to be pedantic about which register virtual size is
6809 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
6810 != mips64_transfers_32bit_regs_p
)
6812 /* Be pedantic about which FPU is selected. */
6813 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
6816 if (tdesc_data
!= NULL
)
6817 tdesc_data_cleanup (tdesc_data
);
6818 return arches
->gdbarch
;
6821 /* Need a new architecture. Fill in a target specific vector. */
6822 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
6823 gdbarch
= gdbarch_alloc (&info
, tdep
);
6824 tdep
->elf_flags
= elf_flags
;
6825 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
6826 tdep
->found_abi
= found_abi
;
6827 tdep
->mips_abi
= mips_abi
;
6828 tdep
->mips_fpu_type
= fpu_type
;
6829 tdep
->register_size_valid_p
= 0;
6830 tdep
->register_size
= 0;
6831 tdep
->gregset
= NULL
;
6832 tdep
->gregset64
= NULL
;
6833 tdep
->fpregset
= NULL
;
6834 tdep
->fpregset64
= NULL
;
6836 if (info
.target_desc
)
6838 /* Some useful properties can be inferred from the target. */
6839 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
6841 tdep
->register_size_valid_p
= 1;
6842 tdep
->register_size
= 4;
6844 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
6846 tdep
->register_size_valid_p
= 1;
6847 tdep
->register_size
= 8;
6851 /* Initially set everything according to the default ABI/ISA. */
6852 set_gdbarch_short_bit (gdbarch
, 16);
6853 set_gdbarch_int_bit (gdbarch
, 32);
6854 set_gdbarch_float_bit (gdbarch
, 32);
6855 set_gdbarch_double_bit (gdbarch
, 64);
6856 set_gdbarch_long_double_bit (gdbarch
, 64);
6857 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
6858 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
6859 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
6861 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6862 mips_ax_pseudo_register_collect
);
6863 set_gdbarch_ax_pseudo_register_push_stack
6864 (gdbarch
, mips_ax_pseudo_register_push_stack
);
6866 set_gdbarch_elf_make_msymbol_special (gdbarch
,
6867 mips_elf_make_msymbol_special
);
6869 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
6870 *regnum
= mips_regnum
;
6871 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
6872 set_gdbarch_num_regs (gdbarch
, num_regs
);
6873 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
6874 set_gdbarch_register_name (gdbarch
, mips_register_name
);
6875 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
6876 tdep
->mips_processor_reg_names
= reg_names
;
6877 tdep
->regnum
= regnum
;
6882 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
6883 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
6884 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6885 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6886 tdep
->default_mask_address_p
= 0;
6887 set_gdbarch_long_bit (gdbarch
, 32);
6888 set_gdbarch_ptr_bit (gdbarch
, 32);
6889 set_gdbarch_long_long_bit (gdbarch
, 64);
6892 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
6893 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
6894 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
6895 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
6896 tdep
->default_mask_address_p
= 0;
6897 set_gdbarch_long_bit (gdbarch
, 32);
6898 set_gdbarch_ptr_bit (gdbarch
, 32);
6899 set_gdbarch_long_long_bit (gdbarch
, 64);
6901 case MIPS_ABI_EABI32
:
6902 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6903 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6904 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6905 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6906 tdep
->default_mask_address_p
= 0;
6907 set_gdbarch_long_bit (gdbarch
, 32);
6908 set_gdbarch_ptr_bit (gdbarch
, 32);
6909 set_gdbarch_long_long_bit (gdbarch
, 64);
6911 case MIPS_ABI_EABI64
:
6912 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
6913 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
6914 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6915 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6916 tdep
->default_mask_address_p
= 0;
6917 set_gdbarch_long_bit (gdbarch
, 64);
6918 set_gdbarch_ptr_bit (gdbarch
, 64);
6919 set_gdbarch_long_long_bit (gdbarch
, 64);
6922 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6923 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6924 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6925 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6926 tdep
->default_mask_address_p
= 0;
6927 set_gdbarch_long_bit (gdbarch
, 32);
6928 set_gdbarch_ptr_bit (gdbarch
, 32);
6929 set_gdbarch_long_long_bit (gdbarch
, 64);
6930 set_gdbarch_long_double_bit (gdbarch
, 128);
6931 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6934 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
6935 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
6936 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
6937 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
6938 tdep
->default_mask_address_p
= 0;
6939 set_gdbarch_long_bit (gdbarch
, 64);
6940 set_gdbarch_ptr_bit (gdbarch
, 64);
6941 set_gdbarch_long_long_bit (gdbarch
, 64);
6942 set_gdbarch_long_double_bit (gdbarch
, 128);
6943 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
6946 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
6949 /* GCC creates a pseudo-section whose name specifies the size of
6950 longs, since -mlong32 or -mlong64 may be used independent of
6951 other options. How those options affect pointer sizes is ABI and
6952 architecture dependent, so use them to override the default sizes
6953 set by the ABI. This table shows the relationship between ABI,
6954 -mlongXX, and size of pointers:
6956 ABI -mlongXX ptr bits
6957 --- -------- --------
6971 Note that for o32 and eabi32, pointers are always 32 bits
6972 regardless of any -mlongXX option. For all others, pointers and
6973 longs are the same, as set by -mlongXX or set by defaults. */
6975 if (info
.abfd
!= NULL
)
6979 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
6982 set_gdbarch_long_bit (gdbarch
, long_bit
);
6986 case MIPS_ABI_EABI32
:
6991 case MIPS_ABI_EABI64
:
6992 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
6995 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
7000 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
7001 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
7004 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
7005 flag in object files because to do so would make it impossible to
7006 link with libraries compiled without "-gp32". This is
7007 unnecessarily restrictive.
7009 We could solve this problem by adding "-gp32" multilibs to gcc,
7010 but to set this flag before gcc is built with such multilibs will
7011 break too many systems.''
7013 But even more unhelpfully, the default linker output target for
7014 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
7015 for 64-bit programs - you need to change the ABI to change this,
7016 and not all gcc targets support that currently. Therefore using
7017 this flag to detect 32-bit mode would do the wrong thing given
7018 the current gcc - it would make GDB treat these 64-bit programs
7019 as 32-bit programs by default. */
7021 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
7022 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
7024 /* Add/remove bits from an address. The MIPS needs be careful to
7025 ensure that all 32 bit addresses are sign extended to 64 bits. */
7026 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
7028 /* Unwind the frame. */
7029 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
7030 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
7031 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
7033 /* Map debug register numbers onto internal register numbers. */
7034 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
7035 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
7036 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
7037 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
7038 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
7039 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
7041 /* MIPS version of CALL_DUMMY. */
7043 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
7044 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
7045 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
7047 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
7048 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
7049 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
7051 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
7052 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
7053 set_gdbarch_adjust_breakpoint_address (gdbarch
,
7054 mips_adjust_breakpoint_address
);
7056 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
7058 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
7060 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
7061 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
7062 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
7064 set_gdbarch_register_type (gdbarch
, mips_register_type
);
7066 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
7068 if (mips_abi
== MIPS_ABI_N32
)
7069 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
7070 else if (mips_abi
== MIPS_ABI_N64
)
7071 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
7073 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
7075 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
7076 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
7077 need to all be folded into the target vector. Since they are
7078 being used as guards for target_stopped_by_watchpoint, why not have
7079 target_stopped_by_watchpoint return the type of watchpoint that the code
7081 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
7083 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
7085 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
7086 to support MIPS16. This is a bad thing. Make sure not to do it
7087 if we have an OS ABI that actually supports shared libraries, since
7088 shared library support is more important. If we have an OS someday
7089 that supports both shared libraries and MIPS16, we'll have to find
7090 a better place for these.
7091 macro/2012-04-25: But that applies to return trampolines only and
7092 currently no MIPS OS ABI uses shared libraries that have them. */
7093 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
7095 set_gdbarch_single_step_through_delay (gdbarch
,
7096 mips_single_step_through_delay
);
7098 /* Virtual tables. */
7099 set_gdbarch_vbit_in_delta (gdbarch
, 1);
7101 mips_register_g_packet_guesses (gdbarch
);
7103 /* Hook in OS ABI-specific overrides, if they have been registered. */
7104 info
.tdep_info
= (void *) tdesc_data
;
7105 gdbarch_init_osabi (info
, gdbarch
);
7107 /* The hook may have adjusted num_regs, fetch the final value and
7108 set pc_regnum and sp_regnum now that it has been fixed. */
7109 num_regs
= gdbarch_num_regs (gdbarch
);
7110 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
7111 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
7113 /* Unwind the frame. */
7114 dwarf2_append_unwinders (gdbarch
);
7115 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
7116 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
7117 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
7118 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
7119 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
7120 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
7121 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
7125 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
7126 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
7128 /* Override the normal target description methods to handle our
7129 dual real and pseudo registers. */
7130 set_gdbarch_register_name (gdbarch
, mips_register_name
);
7131 set_gdbarch_register_reggroup_p (gdbarch
,
7132 mips_tdesc_register_reggroup_p
);
7134 num_regs
= gdbarch_num_regs (gdbarch
);
7135 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
7136 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
7137 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
7140 /* Add ABI-specific aliases for the registers. */
7141 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
7142 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
7143 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
7144 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
7146 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
7147 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
7148 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
7150 /* Add some other standard aliases. */
7151 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
7152 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
7153 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
7155 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
7156 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
7157 value_of_mips_user_reg
,
7158 &mips_numeric_register_aliases
[i
].regnum
);
7164 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
7166 struct gdbarch_info info
;
7168 /* Force the architecture to update, and (if it's a MIPS architecture)
7169 mips_gdbarch_init will take care of the rest. */
7170 gdbarch_info_init (&info
);
7171 gdbarch_update_p (info
);
7174 /* Print out which MIPS ABI is in use. */
7177 show_mips_abi (struct ui_file
*file
,
7179 struct cmd_list_element
*ignored_cmd
,
7180 const char *ignored_value
)
7182 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
7185 "The MIPS ABI is unknown because the current architecture "
7189 enum mips_abi global_abi
= global_mips_abi ();
7190 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
7191 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
7193 if (global_abi
== MIPS_ABI_UNKNOWN
)
7196 "The MIPS ABI is set automatically (currently \"%s\").\n",
7198 else if (global_abi
== actual_abi
)
7201 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
7205 /* Probably shouldn't happen... */
7206 fprintf_filtered (file
,
7207 "The (auto detected) MIPS ABI \"%s\" is in use "
7208 "even though the user setting was \"%s\".\n",
7209 actual_abi_str
, mips_abi_strings
[global_abi
]);
7215 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
7217 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
7221 int ef_mips_32bitmode
;
7222 /* Determine the ISA. */
7223 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
7241 /* Determine the size of a pointer. */
7242 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
7243 fprintf_unfiltered (file
,
7244 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
7246 fprintf_unfiltered (file
,
7247 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
7249 fprintf_unfiltered (file
,
7250 "mips_dump_tdep: ef_mips_arch = %d\n",
7252 fprintf_unfiltered (file
,
7253 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
7254 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
7255 fprintf_unfiltered (file
,
7257 "mips_mask_address_p() %d (default %d)\n",
7258 mips_mask_address_p (tdep
),
7259 tdep
->default_mask_address_p
);
7261 fprintf_unfiltered (file
,
7262 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
7263 MIPS_DEFAULT_FPU_TYPE
,
7264 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
7265 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
7266 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
7268 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
7269 MIPS_EABI (gdbarch
));
7270 fprintf_unfiltered (file
,
7271 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
7272 MIPS_FPU_TYPE (gdbarch
),
7273 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
7274 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
7275 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
7279 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
7282 _initialize_mips_tdep (void)
7284 static struct cmd_list_element
*mipsfpulist
= NULL
;
7285 struct cmd_list_element
*c
;
7287 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
7288 if (MIPS_ABI_LAST
+ 1
7289 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
7290 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
7292 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
7294 mips_pdr_data
= register_objfile_data ();
7296 /* Create feature sets with the appropriate properties. The values
7297 are not important. */
7298 mips_tdesc_gp32
= allocate_target_description ();
7299 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
7301 mips_tdesc_gp64
= allocate_target_description ();
7302 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
7304 /* Add root prefix command for all "set mips"/"show mips" commands. */
7305 add_prefix_cmd ("mips", no_class
, set_mips_command
,
7306 _("Various MIPS specific commands."),
7307 &setmipscmdlist
, "set mips ", 0, &setlist
);
7309 add_prefix_cmd ("mips", no_class
, show_mips_command
,
7310 _("Various MIPS specific commands."),
7311 &showmipscmdlist
, "show mips ", 0, &showlist
);
7313 /* Allow the user to override the ABI. */
7314 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
7315 &mips_abi_string
, _("\
7316 Set the MIPS ABI used by this program."), _("\
7317 Show the MIPS ABI used by this program."), _("\
7318 This option can be set to one of:\n\
7319 auto - the default ABI associated with the current binary\n\
7328 &setmipscmdlist
, &showmipscmdlist
);
7330 /* Let the user turn off floating point and set the fence post for
7331 heuristic_proc_start. */
7333 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
7334 _("Set use of MIPS floating-point coprocessor."),
7335 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
7336 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
7337 _("Select single-precision MIPS floating-point coprocessor."),
7339 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
7340 _("Select double-precision MIPS floating-point coprocessor."),
7342 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
7343 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
7344 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
7345 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
7346 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
7347 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
7348 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
7349 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
7350 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
7351 _("Select MIPS floating-point coprocessor automatically."),
7353 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
7354 _("Show current use of MIPS floating-point coprocessor target."),
7357 /* We really would like to have both "0" and "unlimited" work, but
7358 command.c doesn't deal with that. So make it a var_zinteger
7359 because the user can always use "999999" or some such for unlimited. */
7360 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
7361 &heuristic_fence_post
, _("\
7362 Set the distance searched for the start of a function."), _("\
7363 Show the distance searched for the start of a function."), _("\
7364 If you are debugging a stripped executable, GDB needs to search through the\n\
7365 program for the start of a function. This command sets the distance of the\n\
7366 search. The only need to set it is when debugging a stripped executable."),
7367 reinit_frame_cache_sfunc
,
7368 NULL
, /* FIXME: i18n: The distance searched for
7369 the start of a function is %s. */
7370 &setlist
, &showlist
);
7372 /* Allow the user to control whether the upper bits of 64-bit
7373 addresses should be zeroed. */
7374 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
7375 &mask_address_var
, _("\
7376 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
7377 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
7378 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
7379 allow GDB to determine the correct value."),
7380 NULL
, show_mask_address
,
7381 &setmipscmdlist
, &showmipscmdlist
);
7383 /* Allow the user to control the size of 32 bit registers within the
7384 raw remote packet. */
7385 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
7386 &mips64_transfers_32bit_regs_p
, _("\
7387 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
7389 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
7391 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
7392 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
7393 64 bits for others. Use \"off\" to disable compatibility mode"),
7394 set_mips64_transfers_32bit_regs
,
7395 NULL
, /* FIXME: i18n: Compatibility with 64-bit
7396 MIPS target that transfers 32-bit
7397 quantities is %s. */
7398 &setlist
, &showlist
);
7400 /* Debug this files internals. */
7401 add_setshow_zinteger_cmd ("mips", class_maintenance
,
7403 Set mips debugging."), _("\
7404 Show mips debugging."), _("\
7405 When non-zero, mips specific debugging is enabled."),
7407 NULL
, /* FIXME: i18n: Mips debugging is
7409 &setdebuglist
, &showdebuglist
);