1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
7 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
9 This file is part of GDB.
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 #include "gdb_string.h"
39 #include "arch-utils.h"
42 #include "opcode/mips.h"
47 /* The sizes of floating point registers. */
51 MIPS_FPU_SINGLE_REGSIZE
= 4,
52 MIPS_FPU_DOUBLE_REGSIZE
= 8
55 /* All the possible MIPS ABIs. */
67 struct frame_extra_info
69 mips_extra_func_info_t proc_desc
;
73 /* Various MIPS ISA options (related to stack analysis) can be
74 overridden dynamically. Establish an enum/array for managing
77 static const char size_auto
[] = "auto";
78 static const char size_32
[] = "32";
79 static const char size_64
[] = "64";
81 static const char *size_enums
[] = {
88 /* Some MIPS boards don't support floating point while others only
89 support single-precision floating-point operations. See also
90 FP_REGISTER_DOUBLE. */
94 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
95 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
96 MIPS_FPU_NONE
/* No floating point. */
99 #ifndef MIPS_DEFAULT_FPU_TYPE
100 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
102 static int mips_fpu_type_auto
= 1;
103 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
104 #define MIPS_FPU_TYPE mips_fpu_type
106 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
107 #ifndef FP_REGISTER_DOUBLE
108 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
111 static int mips_debug
= 0;
113 /* MIPS specific per-architecture information */
116 /* from the elf header */
119 enum mips_abi mips_abi
;
120 const char *mips_abi_string
;
121 enum mips_fpu_type mips_fpu_type
;
122 int mips_last_arg_regnum
;
123 int mips_last_fp_arg_regnum
;
124 int mips_default_saved_regsize
;
125 int mips_fp_register_double
;
126 int mips_regs_have_home_p
;
127 int mips_default_stack_argsize
;
128 int gdb_target_is_mips64
;
129 int default_mask_address_p
;
134 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
135 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
139 #undef MIPS_LAST_FP_ARG_REGNUM
140 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
144 #undef MIPS_LAST_ARG_REGNUM
145 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
150 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
153 /* Return the currently configured (or set) saved register size. */
156 #undef MIPS_DEFAULT_SAVED_REGSIZE
157 #define MIPS_DEFAULT_SAVED_REGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_saved_regsize)
158 #elif !defined (MIPS_DEFAULT_SAVED_REGSIZE)
159 #define MIPS_DEFAULT_SAVED_REGSIZE MIPS_REGSIZE
162 static const char *mips_saved_regsize_string
= size_auto
;
164 #define MIPS_SAVED_REGSIZE (mips_saved_regsize())
167 mips_saved_regsize (void)
169 if (mips_saved_regsize_string
== size_auto
)
170 return MIPS_DEFAULT_SAVED_REGSIZE
;
171 else if (mips_saved_regsize_string
== size_64
)
173 else /* if (mips_saved_regsize_string == size_32) */
177 /* Indicate that the ABI makes use of double-precision registers
178 provided by the FPU (rather than combining pairs of registers to
179 form double-precision values). Do not use "TARGET_IS_MIPS64" to
180 determine if the ABI is using double-precision registers. See also
183 #undef FP_REGISTER_DOUBLE
184 #define FP_REGISTER_DOUBLE (gdbarch_tdep (current_gdbarch)->mips_fp_register_double)
187 /* Does the caller allocate a ``home'' for each register used in the
188 function call? The N32 ABI and MIPS_EABI do not, the others do. */
191 #undef MIPS_REGS_HAVE_HOME_P
192 #define MIPS_REGS_HAVE_HOME_P (gdbarch_tdep (current_gdbarch)->mips_regs_have_home_p)
193 #elif !defined (MIPS_REGS_HAVE_HOME_P)
194 #define MIPS_REGS_HAVE_HOME_P (!MIPS_EABI)
197 /* The amount of space reserved on the stack for registers. This is
198 different to MIPS_SAVED_REGSIZE as it determines the alignment of
199 data allocated after the registers have run out. */
202 #undef MIPS_DEFAULT_STACK_ARGSIZE
203 #define MIPS_DEFAULT_STACK_ARGSIZE (gdbarch_tdep (current_gdbarch)->mips_default_stack_argsize)
204 #elif !defined (MIPS_DEFAULT_STACK_ARGSIZE)
205 #define MIPS_DEFAULT_STACK_ARGSIZE (MIPS_DEFAULT_SAVED_REGSIZE)
208 #define MIPS_STACK_ARGSIZE (mips_stack_argsize ())
210 static const char *mips_stack_argsize_string
= size_auto
;
213 mips_stack_argsize (void)
215 if (mips_stack_argsize_string
== size_auto
)
216 return MIPS_DEFAULT_STACK_ARGSIZE
;
217 else if (mips_stack_argsize_string
== size_64
)
219 else /* if (mips_stack_argsize_string == size_32) */
224 #undef GDB_TARGET_IS_MIPS64
225 #define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
229 #undef MIPS_DEFAULT_MASK_ADDRESS_P
230 #define MIPS_DEFAULT_MASK_ADDRESS_P (gdbarch_tdep (current_gdbarch)->default_mask_address_p)
231 #elif !defined (MIPS_DEFAULT_MASK_ADDRESS_P)
232 #define MIPS_DEFAULT_MASK_ADDRESS_P (0)
235 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
237 int gdb_print_insn_mips (bfd_vma
, disassemble_info
*);
239 static void mips_print_register (int, int);
241 static mips_extra_func_info_t
242 heuristic_proc_desc (CORE_ADDR
, CORE_ADDR
, struct frame_info
*);
244 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
246 static CORE_ADDR
read_next_frame_reg (struct frame_info
*, int);
248 int mips_set_processor_type (char *);
250 static void mips_show_processor_type_command (char *, int);
252 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
254 static mips_extra_func_info_t
255 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
);
257 static CORE_ADDR
after_prologue (CORE_ADDR pc
,
258 mips_extra_func_info_t proc_desc
);
260 /* This value is the model of MIPS in use. It is derived from the value
261 of the PrID register. */
263 char *mips_processor_type
;
265 char *tmp_mips_processor_type
;
267 /* The list of available "set mips " and "show mips " commands */
269 static struct cmd_list_element
*setmipscmdlist
= NULL
;
270 static struct cmd_list_element
*showmipscmdlist
= NULL
;
272 /* A set of original names, to be used when restoring back to generic
273 registers from a specific set. */
275 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
276 char **mips_processor_reg_names
= mips_generic_reg_names
;
279 mips_register_name (int i
)
281 return mips_processor_reg_names
[i
];
284 /* Names of IDT R3041 registers. */
286 char *mips_r3041_reg_names
[] = {
287 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
288 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
289 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
290 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
291 "sr", "lo", "hi", "bad", "cause","pc",
292 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
293 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
294 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
295 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
296 "fsr", "fir", "fp", "",
297 "", "", "bus", "ccfg", "", "", "", "",
298 "", "", "port", "cmp", "", "", "epc", "prid",
301 /* Names of IDT R3051 registers. */
303 char *mips_r3051_reg_names
[] = {
304 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
305 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
306 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
307 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
308 "sr", "lo", "hi", "bad", "cause","pc",
309 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
310 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
311 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
312 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
313 "fsr", "fir", "fp", "",
314 "inx", "rand", "elo", "", "ctxt", "", "", "",
315 "", "", "ehi", "", "", "", "epc", "prid",
318 /* Names of IDT R3081 registers. */
320 char *mips_r3081_reg_names
[] = {
321 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
322 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
323 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
324 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
325 "sr", "lo", "hi", "bad", "cause","pc",
326 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
327 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
328 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
329 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
330 "fsr", "fir", "fp", "",
331 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
332 "", "", "ehi", "", "", "", "epc", "prid",
335 /* Names of LSI 33k registers. */
337 char *mips_lsi33k_reg_names
[] = {
338 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
339 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
340 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
341 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
342 "epc", "hi", "lo", "sr", "cause","badvaddr",
343 "dcic", "bpc", "bda", "", "", "", "", "",
344 "", "", "", "", "", "", "", "",
345 "", "", "", "", "", "", "", "",
346 "", "", "", "", "", "", "", "",
348 "", "", "", "", "", "", "", "",
349 "", "", "", "", "", "", "", "",
355 } mips_processor_type_table
[] = {
356 { "generic", mips_generic_reg_names
},
357 { "r3041", mips_r3041_reg_names
},
358 { "r3051", mips_r3051_reg_names
},
359 { "r3071", mips_r3081_reg_names
},
360 { "r3081", mips_r3081_reg_names
},
361 { "lsi33k", mips_lsi33k_reg_names
},
369 /* Table to translate MIPS16 register field to actual register number. */
370 static int mips16_to_32_reg
[8] =
371 {16, 17, 2, 3, 4, 5, 6, 7};
373 /* Heuristic_proc_start may hunt through the text section for a long
374 time across a 2400 baud serial line. Allows the user to limit this
377 static unsigned int heuristic_fence_post
= 0;
379 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
380 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
381 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
382 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
383 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
384 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
385 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
386 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
387 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
388 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
389 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
390 #define _PROC_MAGIC_ 0x0F0F0F0F
391 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
392 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
394 struct linked_proc_info
396 struct mips_extra_func_info info
;
397 struct linked_proc_info
*next
;
399 *linked_proc_desc_table
= NULL
;
402 mips_print_extra_frame_info (struct frame_info
*fi
)
406 && fi
->extra_info
->proc_desc
407 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
408 printf_filtered (" frame pointer is at %s+%s\n",
409 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
410 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
413 /* Convert between RAW and VIRTUAL registers. The RAW register size
414 defines the remote-gdb packet. */
416 static int mips64_transfers_32bit_regs_p
= 0;
419 mips_register_raw_size (int reg_nr
)
421 if (mips64_transfers_32bit_regs_p
)
422 return REGISTER_VIRTUAL_SIZE (reg_nr
);
423 else if (reg_nr
>= FP0_REGNUM
&& reg_nr
< FP0_REGNUM
+ 32
424 && FP_REGISTER_DOUBLE
)
425 /* For MIPS_ABI_N32 (for example) we need 8 byte floating point
433 mips_register_convertible (int reg_nr
)
435 if (mips64_transfers_32bit_regs_p
)
438 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
442 mips_register_convert_to_virtual (int n
, struct type
*virtual_type
,
443 char *raw_buf
, char *virt_buf
)
445 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
447 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
448 TYPE_LENGTH (virtual_type
));
452 TYPE_LENGTH (virtual_type
));
456 mips_register_convert_to_raw (struct type
*virtual_type
, int n
,
457 char *virt_buf
, char *raw_buf
)
459 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
460 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
461 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
463 TYPE_LENGTH (virtual_type
));
467 TYPE_LENGTH (virtual_type
));
470 /* Should the upper word of 64-bit addresses be zeroed? */
471 enum cmd_auto_boolean mask_address_var
= CMD_AUTO_BOOLEAN_AUTO
;
474 mips_mask_address_p (void)
476 switch (mask_address_var
)
478 case CMD_AUTO_BOOLEAN_TRUE
:
480 case CMD_AUTO_BOOLEAN_FALSE
:
483 case CMD_AUTO_BOOLEAN_AUTO
:
484 return MIPS_DEFAULT_MASK_ADDRESS_P
;
486 internal_error (__FILE__
, __LINE__
,
487 "mips_mask_address_p: bad switch");
493 show_mask_address (char *cmd
, int from_tty
)
495 switch (mask_address_var
)
497 case CMD_AUTO_BOOLEAN_TRUE
:
498 printf_filtered ("The 32 bit mips address mask is enabled\n");
500 case CMD_AUTO_BOOLEAN_FALSE
:
501 printf_filtered ("The 32 bit mips address mask is disabled\n");
503 case CMD_AUTO_BOOLEAN_AUTO
:
504 printf_filtered ("The 32 bit address mask is set automatically. Currently %s\n",
505 mips_mask_address_p () ? "enabled" : "disabled");
508 internal_error (__FILE__
, __LINE__
,
509 "show_mask_address: bad switch");
514 /* Should call_function allocate stack space for a struct return? */
516 mips_use_struct_convention (int gcc_p
, struct type
*type
)
519 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
521 return 1; /* Structures are returned by ref in extra arg0 */
524 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
527 pc_is_mips16 (bfd_vma memaddr
)
529 struct minimal_symbol
*sym
;
531 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
532 if (IS_MIPS16_ADDR (memaddr
))
535 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
536 the high bit of the info field. Use this to decide if the function is
537 MIPS16 or normal MIPS. */
538 sym
= lookup_minimal_symbol_by_pc (memaddr
);
540 return MSYMBOL_IS_SPECIAL (sym
);
545 /* MIPS believes that the PC has a sign extended value. Perhaphs the
546 all registers should be sign extended for simplicity? */
549 mips_read_pc (ptid_t ptid
)
551 return read_signed_register_pid (PC_REGNUM
, ptid
);
554 /* This returns the PC of the first inst after the prologue. If we can't
555 find the prologue, then return 0. */
558 after_prologue (CORE_ADDR pc
,
559 mips_extra_func_info_t proc_desc
)
561 struct symtab_and_line sal
;
562 CORE_ADDR func_addr
, func_end
;
565 proc_desc
= find_proc_desc (pc
, NULL
);
569 /* If function is frameless, then we need to do it the hard way. I
570 strongly suspect that frameless always means prologueless... */
571 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
572 && PROC_FRAME_OFFSET (proc_desc
) == 0)
576 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
577 return 0; /* Unknown */
579 sal
= find_pc_line (func_addr
, 0);
581 if (sal
.end
< func_end
)
584 /* The line after the prologue is after the end of the function. In this
585 case, tell the caller to find the prologue the hard way. */
590 /* Decode a MIPS32 instruction that saves a register in the stack, and
591 set the appropriate bit in the general register mask or float register mask
592 to indicate which register is saved. This is a helper function
593 for mips_find_saved_regs. */
596 mips32_decode_reg_save (t_inst inst
, unsigned long *gen_mask
,
597 unsigned long *float_mask
)
601 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
602 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
603 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
605 /* It might be possible to use the instruction to
606 find the offset, rather than the code below which
607 is based on things being in a certain order in the
608 frame, but figuring out what the instruction's offset
609 is relative to might be a little tricky. */
610 reg
= (inst
& 0x001f0000) >> 16;
611 *gen_mask
|= (1 << reg
);
613 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
614 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
615 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
618 reg
= ((inst
& 0x001f0000) >> 16);
619 *float_mask
|= (1 << reg
);
623 /* Decode a MIPS16 instruction that saves a register in the stack, and
624 set the appropriate bit in the general register or float register mask
625 to indicate which register is saved. This is a helper function
626 for mips_find_saved_regs. */
629 mips16_decode_reg_save (t_inst inst
, unsigned long *gen_mask
)
631 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
633 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
634 *gen_mask
|= (1 << reg
);
636 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
638 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
639 *gen_mask
|= (1 << reg
);
641 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
642 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
643 *gen_mask
|= (1 << RA_REGNUM
);
647 /* Fetch and return instruction from the specified location. If the PC
648 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
651 mips_fetch_instruction (CORE_ADDR addr
)
653 char buf
[MIPS_INSTLEN
];
657 if (pc_is_mips16 (addr
))
659 instlen
= MIPS16_INSTLEN
;
660 addr
= UNMAKE_MIPS16_ADDR (addr
);
663 instlen
= MIPS_INSTLEN
;
664 status
= read_memory_nobpt (addr
, buf
, instlen
);
666 memory_error (status
, addr
);
667 return extract_unsigned_integer (buf
, instlen
);
671 /* These the fields of 32 bit mips instructions */
672 #define mips32_op(x) (x >> 25)
673 #define itype_op(x) (x >> 25)
674 #define itype_rs(x) ((x >> 21)& 0x1f)
675 #define itype_rt(x) ((x >> 16) & 0x1f)
676 #define itype_immediate(x) ( x & 0xffff)
678 #define jtype_op(x) (x >> 25)
679 #define jtype_target(x) ( x & 0x03fffff)
681 #define rtype_op(x) (x >>25)
682 #define rtype_rs(x) ((x>>21) & 0x1f)
683 #define rtype_rt(x) ((x>>16) & 0x1f)
684 #define rtype_rd(x) ((x>>11) & 0x1f)
685 #define rtype_shamt(x) ((x>>6) & 0x1f)
686 #define rtype_funct(x) (x & 0x3f )
689 mips32_relative_offset (unsigned long inst
)
692 x
= itype_immediate (inst
);
693 if (x
& 0x8000) /* sign bit set */
695 x
|= 0xffff0000; /* sign extension */
701 /* Determine whate to set a single step breakpoint while considering
704 mips32_next_pc (CORE_ADDR pc
)
708 inst
= mips_fetch_instruction (pc
);
709 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
711 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
713 op
= ((inst
>> 25) & 0x03);
717 goto equal_branch
; /* BEQL */
719 goto neq_branch
; /* BNEZ */
721 goto less_branch
; /* BLEZ */
723 goto greater_branch
; /* BGTZ */
729 pc
+= 4; /* Not a branch, next instruction is easy */
732 { /* This gets way messy */
734 /* Further subdivide into SPECIAL, REGIMM and other */
735 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
737 case 0: /* SPECIAL */
738 op
= rtype_funct (inst
);
743 /* Set PC to that address */
744 pc
= read_signed_register (rtype_rs (inst
));
750 break; /* end special */
753 op
= jtype_op (inst
); /* branch condition */
754 switch (jtype_op (inst
))
758 case 16: /* BLTZALL */
759 case 18: /* BLTZALL */
761 if (read_signed_register (itype_rs (inst
)) < 0)
762 pc
+= mips32_relative_offset (inst
) + 4;
764 pc
+= 8; /* after the delay slot */
768 case 17: /* BGEZAL */
769 case 19: /* BGEZALL */
770 greater_equal_branch
:
771 if (read_signed_register (itype_rs (inst
)) >= 0)
772 pc
+= mips32_relative_offset (inst
) + 4;
774 pc
+= 8; /* after the delay slot */
776 /* All of the other intructions in the REGIMM catagory */
781 break; /* end REGIMM */
786 reg
= jtype_target (inst
) << 2;
787 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
788 /* Whats this mysterious 0xf000000 adjustment ??? */
791 /* FIXME case JALX : */
794 reg
= jtype_target (inst
) << 2;
795 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
796 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
798 break; /* The new PC will be alternate mode */
799 case 4: /* BEQ , BEQL */
801 if (read_signed_register (itype_rs (inst
)) ==
802 read_signed_register (itype_rt (inst
)))
803 pc
+= mips32_relative_offset (inst
) + 4;
807 case 5: /* BNE , BNEL */
809 if (read_signed_register (itype_rs (inst
)) !=
810 read_signed_register (itype_rs (inst
)))
811 pc
+= mips32_relative_offset (inst
) + 4;
815 case 6: /* BLEZ , BLEZL */
817 if (read_signed_register (itype_rs (inst
) <= 0))
818 pc
+= mips32_relative_offset (inst
) + 4;
823 greater_branch
: /* BGTZ BGTZL */
824 if (read_signed_register (itype_rs (inst
) > 0))
825 pc
+= mips32_relative_offset (inst
) + 4;
834 } /* mips32_next_pc */
836 /* Decoding the next place to set a breakpoint is irregular for the
837 mips 16 variant, but fortunately, there fewer instructions. We have to cope
838 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
839 We dont want to set a single step instruction on the extend instruction
843 /* Lots of mips16 instruction formats */
844 /* Predicting jumps requires itype,ritype,i8type
845 and their extensions extItype,extritype,extI8type
847 enum mips16_inst_fmts
849 itype
, /* 0 immediate 5,10 */
850 ritype
, /* 1 5,3,8 */
851 rrtype
, /* 2 5,3,3,5 */
852 rritype
, /* 3 5,3,3,5 */
853 rrrtype
, /* 4 5,3,3,3,2 */
854 rriatype
, /* 5 5,3,3,1,4 */
855 shifttype
, /* 6 5,3,3,3,2 */
856 i8type
, /* 7 5,3,8 */
857 i8movtype
, /* 8 5,3,3,5 */
858 i8mov32rtype
, /* 9 5,3,5,3 */
859 i64type
, /* 10 5,3,8 */
860 ri64type
, /* 11 5,3,3,5 */
861 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
862 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
863 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
864 extRRItype
, /* 15 5,5,5,5,3,3,5 */
865 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
866 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
867 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
868 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
869 extRi64type
, /* 20 5,6,5,5,3,3,5 */
870 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
872 /* I am heaping all the fields of the formats into one structure and
873 then, only the fields which are involved in instruction extension */
877 unsigned int regx
; /* Function in i8 type */
882 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
883 for the bits which make up the immediatate extension. */
886 extended_offset (unsigned int extension
)
889 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
891 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
893 value
|= extension
& 0x01f; /* extract 4:0 */
897 /* Only call this function if you know that this is an extendable
898 instruction, It wont malfunction, but why make excess remote memory references?
899 If the immediate operands get sign extended or somthing, do it after
900 the extension is performed.
902 /* FIXME: Every one of these cases needs to worry about sign extension
903 when the offset is to be used in relative addressing */
907 fetch_mips_16 (CORE_ADDR pc
)
910 pc
&= 0xfffffffe; /* clear the low order bit */
911 target_read_memory (pc
, buf
, 2);
912 return extract_unsigned_integer (buf
, 2);
916 unpack_mips16 (CORE_ADDR pc
,
917 unsigned int extension
,
919 enum mips16_inst_fmts insn_format
,
920 struct upk_mips16
*upk
)
932 value
= extended_offset (extension
);
933 value
= value
<< 11; /* rom for the original value */
934 value
|= inst
& 0x7ff; /* eleven bits from instruction */
938 value
= inst
& 0x7ff;
939 /* FIXME : Consider sign extension */
948 { /* A register identifier and an offset */
949 /* Most of the fields are the same as I type but the
950 immediate value is of a different length */
954 value
= extended_offset (extension
);
955 value
= value
<< 8; /* from the original instruction */
956 value
|= inst
& 0xff; /* eleven bits from instruction */
957 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
958 if (value
& 0x4000) /* test the sign bit , bit 26 */
960 value
&= ~0x3fff; /* remove the sign bit */
966 value
= inst
& 0xff; /* 8 bits */
967 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
968 /* FIXME: Do sign extension , this format needs it */
969 if (value
& 0x80) /* THIS CONFUSES ME */
971 value
&= 0xef; /* remove the sign bit */
982 unsigned int nexthalf
;
983 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
985 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
993 internal_error (__FILE__
, __LINE__
,
996 upk
->offset
= offset
;
1003 add_offset_16 (CORE_ADDR pc
, int offset
)
1005 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
1010 extended_mips16_next_pc (CORE_ADDR pc
,
1011 unsigned int extension
,
1014 int op
= (insn
>> 11);
1017 case 2: /* Branch */
1020 struct upk_mips16 upk
;
1021 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1022 offset
= upk
.offset
;
1028 pc
+= (offset
<< 1) + 2;
1031 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1033 struct upk_mips16 upk
;
1034 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1035 pc
= add_offset_16 (pc
, upk
.offset
);
1036 if ((insn
>> 10) & 0x01) /* Exchange mode */
1037 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1044 struct upk_mips16 upk
;
1046 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1047 reg
= read_signed_register (upk
.regx
);
1049 pc
+= (upk
.offset
<< 1) + 2;
1056 struct upk_mips16 upk
;
1058 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1059 reg
= read_signed_register (upk
.regx
);
1061 pc
+= (upk
.offset
<< 1) + 2;
1066 case 12: /* I8 Formats btez btnez */
1068 struct upk_mips16 upk
;
1070 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1071 /* upk.regx contains the opcode */
1072 reg
= read_signed_register (24); /* Test register is 24 */
1073 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1074 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1075 /* pc = add_offset_16(pc,upk.offset) ; */
1076 pc
+= (upk
.offset
<< 1) + 2;
1081 case 29: /* RR Formats JR, JALR, JALR-RA */
1083 struct upk_mips16 upk
;
1084 /* upk.fmt = rrtype; */
1089 upk
.regx
= (insn
>> 8) & 0x07;
1090 upk
.regy
= (insn
>> 5) & 0x07;
1098 break; /* Function return instruction */
1104 break; /* BOGUS Guess */
1106 pc
= read_signed_register (reg
);
1113 /* This is an instruction extension. Fetch the real instruction
1114 (which follows the extension) and decode things based on
1118 pc
= extended_mips16_next_pc (pc
, insn
, fetch_mips_16 (pc
));
1131 mips16_next_pc (CORE_ADDR pc
)
1133 unsigned int insn
= fetch_mips_16 (pc
);
1134 return extended_mips16_next_pc (pc
, 0, insn
);
1137 /* The mips_next_pc function supports single_step when the remote
1138 target monitor or stub is not developed enough to do a single_step.
1139 It works by decoding the current instruction and predicting where a
1140 branch will go. This isnt hard because all the data is available.
1141 The MIPS32 and MIPS16 variants are quite different */
1143 mips_next_pc (CORE_ADDR pc
)
1146 return mips16_next_pc (pc
);
1148 return mips32_next_pc (pc
);
1151 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
1155 mips_find_saved_regs (struct frame_info
*fci
)
1158 CORE_ADDR reg_position
;
1159 /* r0 bit means kernel trap */
1161 /* What registers have been saved? Bitmasks. */
1162 unsigned long gen_mask
, float_mask
;
1163 mips_extra_func_info_t proc_desc
;
1166 frame_saved_regs_zalloc (fci
);
1168 /* If it is the frame for sigtramp, the saved registers are located
1169 in a sigcontext structure somewhere on the stack.
1170 If the stack layout for sigtramp changes we might have to change these
1171 constants and the companion fixup_sigtramp in mdebugread.c */
1172 #ifndef SIGFRAME_BASE
1173 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
1174 above the sigtramp frame. */
1175 #define SIGFRAME_BASE MIPS_REGSIZE
1176 /* FIXME! Are these correct?? */
1177 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
1178 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
1179 #define SIGFRAME_FPREGSAVE_OFF \
1180 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
1182 #ifndef SIGFRAME_REG_SIZE
1183 /* FIXME! Is this correct?? */
1184 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
1186 if (fci
->signal_handler_caller
)
1188 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1190 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1191 + ireg
* SIGFRAME_REG_SIZE
;
1192 fci
->saved_regs
[ireg
] = reg_position
;
1194 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1196 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1197 + ireg
* SIGFRAME_REG_SIZE
;
1198 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1200 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1204 proc_desc
= fci
->extra_info
->proc_desc
;
1205 if (proc_desc
== NULL
)
1206 /* I'm not sure how/whether this can happen. Normally when we can't
1207 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1208 and set the saved_regs right away. */
1211 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1212 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1213 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1215 if ( /* In any frame other than the innermost or a frame interrupted by
1216 a signal, we assume that all registers have been saved.
1217 This assumes that all register saves in a function happen before
1218 the first function call. */
1219 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1221 /* In a dummy frame we know exactly where things are saved. */
1222 && !PROC_DESC_IS_DUMMY (proc_desc
)
1224 /* Don't bother unless we are inside a function prologue. Outside the
1225 prologue, we know where everything is. */
1227 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1229 /* Not sure exactly what kernel_trap means, but if it means
1230 the kernel saves the registers without a prologue doing it,
1231 we better not examine the prologue to see whether registers
1232 have been saved yet. */
1235 /* We need to figure out whether the registers that the proc_desc
1236 claims are saved have been saved yet. */
1240 /* Bitmasks; set if we have found a save for the register. */
1241 unsigned long gen_save_found
= 0;
1242 unsigned long float_save_found
= 0;
1245 /* If the address is odd, assume this is MIPS16 code. */
1246 addr
= PROC_LOW_ADDR (proc_desc
);
1247 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1249 /* Scan through this function's instructions preceding the current
1250 PC, and look for those that save registers. */
1251 while (addr
< fci
->pc
)
1253 inst
= mips_fetch_instruction (addr
);
1254 if (pc_is_mips16 (addr
))
1255 mips16_decode_reg_save (inst
, &gen_save_found
);
1257 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1260 gen_mask
= gen_save_found
;
1261 float_mask
= float_save_found
;
1264 /* Fill in the offsets for the registers which gen_mask says
1266 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1267 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1268 if (gen_mask
& 0x80000000)
1270 fci
->saved_regs
[ireg
] = reg_position
;
1271 reg_position
-= MIPS_SAVED_REGSIZE
;
1274 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1275 of that normally used by gcc. Therefore, we have to fetch the first
1276 instruction of the function, and if it's an entry instruction that
1277 saves $s0 or $s1, correct their saved addresses. */
1278 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1280 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1281 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1284 int sreg_count
= (inst
>> 6) & 3;
1286 /* Check if the ra register was pushed on the stack. */
1287 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1289 reg_position
-= MIPS_SAVED_REGSIZE
;
1291 /* Check if the s0 and s1 registers were pushed on the stack. */
1292 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1294 fci
->saved_regs
[reg
] = reg_position
;
1295 reg_position
-= MIPS_SAVED_REGSIZE
;
1300 /* Fill in the offsets for the registers which float_mask says
1302 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1304 /* The freg_offset points to where the first *double* register
1305 is saved. So skip to the high-order word. */
1306 if (!GDB_TARGET_IS_MIPS64
)
1307 reg_position
+= MIPS_SAVED_REGSIZE
;
1309 /* Fill in the offsets for the float registers which float_mask says
1311 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1312 if (float_mask
& 0x80000000)
1314 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1315 reg_position
-= MIPS_SAVED_REGSIZE
;
1318 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1322 read_next_frame_reg (struct frame_info
*fi
, int regno
)
1324 for (; fi
; fi
= fi
->next
)
1326 /* We have to get the saved sp from the sigcontext
1327 if it is a signal handler frame. */
1328 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1332 if (fi
->saved_regs
== NULL
)
1333 mips_find_saved_regs (fi
);
1334 if (fi
->saved_regs
[regno
])
1335 return read_memory_integer (ADDR_BITS_REMOVE (fi
->saved_regs
[regno
]), MIPS_SAVED_REGSIZE
);
1338 return read_signed_register (regno
);
1341 /* mips_addr_bits_remove - remove useless address bits */
1344 mips_addr_bits_remove (CORE_ADDR addr
)
1346 if (GDB_TARGET_IS_MIPS64
)
1348 if (mips_mask_address_p () && (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1350 /* This hack is a work-around for existing boards using
1351 PMON, the simulator, and any other 64-bit targets that
1352 doesn't have true 64-bit addressing. On these targets,
1353 the upper 32 bits of addresses are ignored by the
1354 hardware. Thus, the PC or SP are likely to have been
1355 sign extended to all 1s by instruction sequences that
1356 load 32-bit addresses. For example, a typical piece of
1357 code that loads an address is this:
1358 lui $r2, <upper 16 bits>
1359 ori $r2, <lower 16 bits>
1360 But the lui sign-extends the value such that the upper 32
1361 bits may be all 1s. The workaround is simply to mask off
1362 these bits. In the future, gcc may be changed to support
1363 true 64-bit addressing, and this masking will have to be
1365 addr
&= (CORE_ADDR
) 0xffffffff;
1368 else if (mips_mask_address_p ())
1370 /* FIXME: This is wrong! mips_addr_bits_remove() shouldn't be
1371 masking off bits, instead, the actual target should be asking
1372 for the address to be converted to a valid pointer. */
1373 /* Even when GDB is configured for some 32-bit targets
1374 (e.g. mips-elf), BFD is configured to handle 64-bit targets,
1375 so CORE_ADDR is 64 bits. So we still have to mask off
1376 useless bits from addresses. */
1377 addr
&= (CORE_ADDR
) 0xffffffff;
1382 /* mips_software_single_step() is called just before we want to resume
1383 the inferior, if we want to single-step it but there is no hardware
1384 or kernel single-step support (MIPS on Linux for example). We find
1385 the target of the coming instruction and breakpoint it.
1387 single_step is also called just after the inferior stops. If we had
1388 set up a simulated single-step, we undo our damage. */
1391 mips_software_single_step (enum target_signal sig
, int insert_breakpoints_p
)
1393 static CORE_ADDR next_pc
;
1394 typedef char binsn_quantum
[BREAKPOINT_MAX
];
1395 static binsn_quantum break_mem
;
1398 if (insert_breakpoints_p
)
1400 pc
= read_register (PC_REGNUM
);
1401 next_pc
= mips_next_pc (pc
);
1403 target_insert_breakpoint (next_pc
, break_mem
);
1406 target_remove_breakpoint (next_pc
, break_mem
);
1410 mips_init_frame_pc_first (int fromleaf
, struct frame_info
*prev
)
1414 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1415 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1416 tmp
= mips_skip_stub (pc
);
1417 prev
->pc
= tmp
? tmp
: pc
;
1422 mips_frame_saved_pc (struct frame_info
*frame
)
1425 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1426 /* We have to get the saved pc from the sigcontext
1427 if it is a signal handler frame. */
1428 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1429 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1431 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1432 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1434 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1436 return ADDR_BITS_REMOVE (saved_pc
);
1439 static struct mips_extra_func_info temp_proc_desc
;
1440 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1442 /* Set a register's saved stack address in temp_saved_regs. If an address
1443 has already been set for this register, do nothing; this way we will
1444 only recognize the first save of a given register in a function prologue.
1445 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1448 set_reg_offset (int regno
, CORE_ADDR offset
)
1450 if (temp_saved_regs
[regno
] == 0)
1451 temp_saved_regs
[regno
] = offset
;
1455 /* Test whether the PC points to the return instruction at the
1456 end of a function. */
1459 mips_about_to_return (CORE_ADDR pc
)
1461 if (pc_is_mips16 (pc
))
1462 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1463 generates a "jr $ra"; other times it generates code to load
1464 the return address from the stack to an accessible register (such
1465 as $a3), then a "jr" using that register. This second case
1466 is almost impossible to distinguish from an indirect jump
1467 used for switch statements, so we don't even try. */
1468 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1470 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1474 /* This fencepost looks highly suspicious to me. Removing it also
1475 seems suspicious as it could affect remote debugging across serial
1479 heuristic_proc_start (CORE_ADDR pc
)
1486 pc
= ADDR_BITS_REMOVE (pc
);
1488 fence
= start_pc
- heuristic_fence_post
;
1492 if (heuristic_fence_post
== UINT_MAX
1493 || fence
< VM_MIN_ADDRESS
)
1494 fence
= VM_MIN_ADDRESS
;
1496 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1498 /* search back for previous return */
1499 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1500 if (start_pc
< fence
)
1502 /* It's not clear to me why we reach this point when
1503 stop_soon_quietly, but with this test, at least we
1504 don't print out warnings for every child forked (eg, on
1505 decstation). 22apr93 rich@cygnus.com. */
1506 if (!stop_soon_quietly
)
1508 static int blurb_printed
= 0;
1510 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1515 /* This actually happens frequently in embedded
1516 development, when you first connect to a board
1517 and your stack pointer and pc are nowhere in
1518 particular. This message needs to give people
1519 in that situation enough information to
1520 determine that it's no big deal. */
1521 printf_filtered ("\n\
1522 GDB is unable to find the start of the function at 0x%s\n\
1523 and thus can't determine the size of that function's stack frame.\n\
1524 This means that GDB may be unable to access that stack frame, or\n\
1525 the frames below it.\n\
1526 This problem is most likely caused by an invalid program counter or\n\
1528 However, if you think GDB should simply search farther back\n\
1529 from 0x%s for code which looks like the beginning of a\n\
1530 function, you can increase the range of the search using the `set\n\
1531 heuristic-fence-post' command.\n",
1532 paddr_nz (pc
), paddr_nz (pc
));
1539 else if (pc_is_mips16 (start_pc
))
1541 unsigned short inst
;
1543 /* On MIPS16, any one of the following is likely to be the
1544 start of a function:
1548 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1549 inst
= mips_fetch_instruction (start_pc
);
1550 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1551 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1552 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1553 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1555 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1556 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1561 else if (mips_about_to_return (start_pc
))
1563 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1570 /* Fetch the immediate value from a MIPS16 instruction.
1571 If the previous instruction was an EXTEND, use it to extend
1572 the upper bits of the immediate value. This is a helper function
1573 for mips16_heuristic_proc_desc. */
1576 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1577 unsigned short inst
, /* current instruction */
1578 int nbits
, /* number of bits in imm field */
1579 int scale
, /* scale factor to be applied to imm */
1580 int is_signed
) /* is the imm field signed? */
1584 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1586 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1587 if (offset
& 0x8000) /* check for negative extend */
1588 offset
= 0 - (0x10000 - (offset
& 0xffff));
1589 return offset
| (inst
& 0x1f);
1593 int max_imm
= 1 << nbits
;
1594 int mask
= max_imm
- 1;
1595 int sign_bit
= max_imm
>> 1;
1597 offset
= inst
& mask
;
1598 if (is_signed
&& (offset
& sign_bit
))
1599 offset
= 0 - (max_imm
- offset
);
1600 return offset
* scale
;
1605 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1606 stream from start_pc to limit_pc. */
1609 mips16_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1610 struct frame_info
*next_frame
, CORE_ADDR sp
)
1613 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1614 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1615 unsigned inst
= 0; /* current instruction */
1616 unsigned entry_inst
= 0; /* the entry instruction */
1619 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1620 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1622 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1624 /* Save the previous instruction. If it's an EXTEND, we'll extract
1625 the immediate offset extension from it in mips16_get_imm. */
1628 /* Fetch and decode the instruction. */
1629 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1630 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1631 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1633 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1634 if (offset
< 0) /* negative stack adjustment? */
1635 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1637 /* Exit loop if a positive stack adjustment is found, which
1638 usually means that the stack cleanup code in the function
1639 epilogue is reached. */
1642 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1644 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1645 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1646 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1647 set_reg_offset (reg
, sp
+ offset
);
1649 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1651 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1652 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1653 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1654 set_reg_offset (reg
, sp
+ offset
);
1656 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1658 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1659 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1660 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1662 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1664 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1665 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1666 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1668 else if (inst
== 0x673d) /* move $s1, $sp */
1671 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1673 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1675 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1676 frame_addr
= sp
+ offset
;
1677 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1678 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1680 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1682 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1683 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1684 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1685 set_reg_offset (reg
, frame_addr
+ offset
);
1687 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1689 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1690 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1691 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1692 set_reg_offset (reg
, frame_addr
+ offset
);
1694 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1695 entry_inst
= inst
; /* save for later processing */
1696 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1697 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1700 /* The entry instruction is typically the first instruction in a function,
1701 and it stores registers at offsets relative to the value of the old SP
1702 (before the prologue). But the value of the sp parameter to this
1703 function is the new SP (after the prologue has been executed). So we
1704 can't calculate those offsets until we've seen the entire prologue,
1705 and can calculate what the old SP must have been. */
1706 if (entry_inst
!= 0)
1708 int areg_count
= (entry_inst
>> 8) & 7;
1709 int sreg_count
= (entry_inst
>> 6) & 3;
1711 /* The entry instruction always subtracts 32 from the SP. */
1712 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1714 /* Now we can calculate what the SP must have been at the
1715 start of the function prologue. */
1716 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1718 /* Check if a0-a3 were saved in the caller's argument save area. */
1719 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1721 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1722 set_reg_offset (reg
, sp
+ offset
);
1723 offset
+= MIPS_SAVED_REGSIZE
;
1726 /* Check if the ra register was pushed on the stack. */
1728 if (entry_inst
& 0x20)
1730 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1731 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1732 offset
-= MIPS_SAVED_REGSIZE
;
1735 /* Check if the s0 and s1 registers were pushed on the stack. */
1736 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1738 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1739 set_reg_offset (reg
, sp
+ offset
);
1740 offset
-= MIPS_SAVED_REGSIZE
;
1746 mips32_heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1747 struct frame_info
*next_frame
, CORE_ADDR sp
)
1750 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1752 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1753 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1754 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1755 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1757 unsigned long inst
, high_word
, low_word
;
1760 /* Fetch the instruction. */
1761 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1763 /* Save some code by pre-extracting some useful fields. */
1764 high_word
= (inst
>> 16) & 0xffff;
1765 low_word
= inst
& 0xffff;
1766 reg
= high_word
& 0x1f;
1768 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1769 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1770 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1772 if (low_word
& 0x8000) /* negative stack adjustment? */
1773 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1775 /* Exit loop if a positive stack adjustment is found, which
1776 usually means that the stack cleanup code in the function
1777 epilogue is reached. */
1780 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1782 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1783 set_reg_offset (reg
, sp
+ low_word
);
1785 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1787 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1788 but the register size used is only 32 bits. Make the address
1789 for the saved register point to the lower 32 bits. */
1790 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1791 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1793 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1795 /* Old gcc frame, r30 is virtual frame pointer. */
1796 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1797 frame_addr
= sp
+ low_word
;
1798 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1800 unsigned alloca_adjust
;
1801 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1802 frame_addr
= read_next_frame_reg (next_frame
, 30);
1803 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1804 if (alloca_adjust
> 0)
1806 /* FP > SP + frame_size. This may be because
1807 * of an alloca or somethings similar.
1808 * Fix sp to "pre-alloca" value, and try again.
1810 sp
+= alloca_adjust
;
1815 /* move $30,$sp. With different versions of gas this will be either
1816 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1817 Accept any one of these. */
1818 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1820 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1821 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1823 unsigned alloca_adjust
;
1824 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1825 frame_addr
= read_next_frame_reg (next_frame
, 30);
1826 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1827 if (alloca_adjust
> 0)
1829 /* FP > SP + frame_size. This may be because
1830 * of an alloca or somethings similar.
1831 * Fix sp to "pre-alloca" value, and try again.
1833 sp
+= alloca_adjust
;
1838 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1840 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1841 set_reg_offset (reg
, frame_addr
+ low_word
);
1846 static mips_extra_func_info_t
1847 heuristic_proc_desc (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1848 struct frame_info
*next_frame
)
1850 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1854 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1855 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1856 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1857 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1858 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1860 if (start_pc
+ 200 < limit_pc
)
1861 limit_pc
= start_pc
+ 200;
1862 if (pc_is_mips16 (start_pc
))
1863 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1865 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1866 return &temp_proc_desc
;
1869 static mips_extra_func_info_t
1870 non_heuristic_proc_desc (CORE_ADDR pc
, CORE_ADDR
*addrptr
)
1872 CORE_ADDR startaddr
;
1873 mips_extra_func_info_t proc_desc
;
1874 struct block
*b
= block_for_pc (pc
);
1877 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1879 *addrptr
= startaddr
;
1880 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1884 if (startaddr
> BLOCK_START (b
))
1885 /* This is the "pathological" case referred to in a comment in
1886 print_frame_info. It might be better to move this check into
1890 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1893 /* If we never found a PDR for this function in symbol reading, then
1894 examine prologues to find the information. */
1897 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1898 if (PROC_FRAME_REG (proc_desc
) == -1)
1908 static mips_extra_func_info_t
1909 find_proc_desc (CORE_ADDR pc
, struct frame_info
*next_frame
)
1911 mips_extra_func_info_t proc_desc
;
1912 CORE_ADDR startaddr
;
1914 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1918 /* IF this is the topmost frame AND
1919 * (this proc does not have debugging information OR
1920 * the PC is in the procedure prologue)
1921 * THEN create a "heuristic" proc_desc (by analyzing
1922 * the actual code) to replace the "official" proc_desc.
1924 if (next_frame
== NULL
)
1926 struct symtab_and_line val
;
1927 struct symbol
*proc_symbol
=
1928 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1932 val
= find_pc_line (BLOCK_START
1933 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1935 val
.pc
= val
.end
? val
.end
: pc
;
1937 if (!proc_symbol
|| pc
< val
.pc
)
1939 mips_extra_func_info_t found_heuristic
=
1940 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1942 if (found_heuristic
)
1943 proc_desc
= found_heuristic
;
1949 /* Is linked_proc_desc_table really necessary? It only seems to be used
1950 by procedure call dummys. However, the procedures being called ought
1951 to have their own proc_descs, and even if they don't,
1952 heuristic_proc_desc knows how to create them! */
1954 register struct linked_proc_info
*link
;
1956 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1957 if (PROC_LOW_ADDR (&link
->info
) <= pc
1958 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1962 startaddr
= heuristic_proc_start (pc
);
1965 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1971 get_frame_pointer (struct frame_info
*frame
,
1972 mips_extra_func_info_t proc_desc
)
1974 return ADDR_BITS_REMOVE (
1975 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1976 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1979 mips_extra_func_info_t cached_proc_desc
;
1982 mips_frame_chain (struct frame_info
*frame
)
1984 mips_extra_func_info_t proc_desc
;
1986 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1988 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1991 /* Check if the PC is inside a call stub. If it is, fetch the
1992 PC of the caller of that stub. */
1993 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1996 /* Look up the procedure descriptor for this PC. */
1997 proc_desc
= find_proc_desc (saved_pc
, frame
);
2001 cached_proc_desc
= proc_desc
;
2003 /* If no frame pointer and frame size is zero, we must be at end
2004 of stack (or otherwise hosed). If we don't check frame size,
2005 we loop forever if we see a zero size frame. */
2006 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
2007 && PROC_FRAME_OFFSET (proc_desc
) == 0
2008 /* The previous frame from a sigtramp frame might be frameless
2009 and have frame size zero. */
2010 && !frame
->signal_handler_caller
)
2013 return get_frame_pointer (frame
, proc_desc
);
2017 mips_init_extra_frame_info (int fromleaf
, struct frame_info
*fci
)
2021 /* Use proc_desc calculated in frame_chain */
2022 mips_extra_func_info_t proc_desc
=
2023 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
2025 fci
->extra_info
= (struct frame_extra_info
*)
2026 frame_obstack_alloc (sizeof (struct frame_extra_info
));
2028 fci
->saved_regs
= NULL
;
2029 fci
->extra_info
->proc_desc
=
2030 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
2033 /* Fixup frame-pointer - only needed for top frame */
2034 /* This may not be quite right, if proc has a real frame register.
2035 Get the value of the frame relative sp, procedure might have been
2036 interrupted by a signal at it's very start. */
2037 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
2038 && !PROC_DESC_IS_DUMMY (proc_desc
))
2039 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
2041 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
2043 if (proc_desc
== &temp_proc_desc
)
2047 /* Do not set the saved registers for a sigtramp frame,
2048 mips_find_saved_registers will do that for us.
2049 We can't use fci->signal_handler_caller, it is not yet set. */
2050 find_pc_partial_function (fci
->pc
, &name
,
2051 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
2052 if (!IN_SIGTRAMP (fci
->pc
, name
))
2054 frame_saved_regs_zalloc (fci
);
2055 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
2056 fci
->saved_regs
[PC_REGNUM
]
2057 = fci
->saved_regs
[RA_REGNUM
];
2061 /* hack: if argument regs are saved, guess these contain args */
2062 /* assume we can't tell how many args for now */
2063 fci
->extra_info
->num_args
= -1;
2064 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
2066 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
2068 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
2075 /* MIPS stack frames are almost impenetrable. When execution stops,
2076 we basically have to look at symbol information for the function
2077 that we stopped in, which tells us *which* register (if any) is
2078 the base of the frame pointer, and what offset from that register
2079 the frame itself is at.
2081 This presents a problem when trying to examine a stack in memory
2082 (that isn't executing at the moment), using the "frame" command. We
2083 don't have a PC, nor do we have any registers except SP.
2085 This routine takes two arguments, SP and PC, and tries to make the
2086 cached frames look as if these two arguments defined a frame on the
2087 cache. This allows the rest of info frame to extract the important
2088 arguments without difficulty. */
2091 setup_arbitrary_frame (int argc
, CORE_ADDR
*argv
)
2094 error ("MIPS frame specifications require two arguments: sp and pc");
2096 return create_new_frame (argv
[0], argv
[1]);
2099 /* According to the current ABI, should the type be passed in a
2100 floating-point register (assuming that there is space)? When there
2101 is no FPU, FP are not even considered as possibile candidates for
2102 FP registers and, consequently this returns false - forces FP
2103 arguments into integer registers. */
2106 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2108 return ((typecode
== TYPE_CODE_FLT
2110 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
2111 && TYPE_NFIELDS (arg_type
) == 1
2112 && TYPE_CODE (TYPE_FIELD_TYPE (arg_type
, 0)) == TYPE_CODE_FLT
))
2113 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2117 mips_push_arguments (int nargs
,
2121 CORE_ADDR struct_addr
)
2127 int stack_offset
= 0;
2129 /* Macros to round N up or down to the next A boundary; A must be
2131 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
2132 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
2134 /* First ensure that the stack and structure return address (if any)
2135 are properly aligned. The stack has to be at least 64-bit aligned
2136 even on 32-bit machines, because doubles must be 64-bit aligned.
2137 On at least one MIPS variant, stack frames need to be 128-bit
2138 aligned, so we round to this widest known alignment. */
2139 sp
= ROUND_DOWN (sp
, 16);
2140 struct_addr
= ROUND_DOWN (struct_addr
, 16);
2142 /* Now make space on the stack for the args. We allocate more
2143 than necessary for EABI, because the first few arguments are
2144 passed in registers, but that's OK. */
2145 for (argnum
= 0; argnum
< nargs
; argnum
++)
2146 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_STACK_ARGSIZE
);
2147 sp
-= ROUND_UP (len
, 16);
2150 fprintf_unfiltered (gdb_stdlog
, "mips_push_arguments: sp=0x%lx allocated %d\n",
2151 (long) sp
, ROUND_UP (len
, 16));
2153 /* Initialize the integer and float register pointers. */
2155 float_argreg
= FPA0_REGNUM
;
2157 /* the struct_return pointer occupies the first parameter-passing reg */
2161 fprintf_unfiltered (gdb_stdlog
,
2162 "mips_push_arguments: struct_return reg=%d 0x%lx\n",
2163 argreg
, (long) struct_addr
);
2164 write_register (argreg
++, struct_addr
);
2165 if (MIPS_REGS_HAVE_HOME_P
)
2166 stack_offset
+= MIPS_STACK_ARGSIZE
;
2169 /* Now load as many as possible of the first arguments into
2170 registers, and push the rest onto the stack. Loop thru args
2171 from first to last. */
2172 for (argnum
= 0; argnum
< nargs
; argnum
++)
2175 char valbuf
[MAX_REGISTER_RAW_SIZE
];
2176 value_ptr arg
= args
[argnum
];
2177 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
2178 int len
= TYPE_LENGTH (arg_type
);
2179 enum type_code typecode
= TYPE_CODE (arg_type
);
2182 fprintf_unfiltered (gdb_stdlog
,
2183 "mips_push_arguments: %d len=%d type=%d",
2184 argnum
+ 1, len
, (int) typecode
);
2186 /* The EABI passes structures that do not fit in a register by
2187 reference. In all other cases, pass the structure by value. */
2189 && len
> MIPS_SAVED_REGSIZE
2190 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2192 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
2193 typecode
= TYPE_CODE_PTR
;
2194 len
= MIPS_SAVED_REGSIZE
;
2197 fprintf_unfiltered (gdb_stdlog
, " push");
2200 val
= (char *) VALUE_CONTENTS (arg
);
2202 /* 32-bit ABIs always start floating point arguments in an
2203 even-numbered floating point register. Round the FP register
2204 up before the check to see if there are any FP registers
2205 left. Non MIPS_EABI targets also pass the FP in the integer
2206 registers so also round up normal registers. */
2207 if (!FP_REGISTER_DOUBLE
2208 && fp_register_arg_p (typecode
, arg_type
))
2210 if ((float_argreg
& 1))
2214 /* Floating point arguments passed in registers have to be
2215 treated specially. On 32-bit architectures, doubles
2216 are passed in register pairs; the even register gets
2217 the low word, and the odd register gets the high word.
2218 On non-EABI processors, the first two floating point arguments are
2219 also copied to general registers, because MIPS16 functions
2220 don't use float registers for arguments. This duplication of
2221 arguments in general registers can't hurt non-MIPS16 functions
2222 because those registers are normally skipped. */
2223 /* MIPS_EABI squeezes a struct that contains a single floating
2224 point value into an FP register instead of pushing it onto the
2226 if (fp_register_arg_p (typecode
, arg_type
)
2227 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2229 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2231 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2232 unsigned long regval
;
2234 /* Write the low word of the double to the even register(s). */
2235 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2237 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2238 float_argreg
, phex (regval
, 4));
2239 write_register (float_argreg
++, regval
);
2243 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2244 argreg
, phex (regval
, 4));
2245 write_register (argreg
++, regval
);
2248 /* Write the high word of the double to the odd register(s). */
2249 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2251 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2252 float_argreg
, phex (regval
, 4));
2253 write_register (float_argreg
++, regval
);
2257 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2258 argreg
, phex (regval
, 4));
2259 write_register (argreg
++, regval
);
2265 /* This is a floating point value that fits entirely
2266 in a single register. */
2267 /* On 32 bit ABI's the float_argreg is further adjusted
2268 above to ensure that it is even register aligned. */
2269 LONGEST regval
= extract_unsigned_integer (val
, len
);
2271 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2272 float_argreg
, phex (regval
, len
));
2273 write_register (float_argreg
++, regval
);
2276 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2277 registers for each argument. The below is (my
2278 guess) to ensure that the corresponding integer
2279 register has reserved the same space. */
2281 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2282 argreg
, phex (regval
, len
));
2283 write_register (argreg
, regval
);
2284 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2287 /* Reserve space for the FP register. */
2288 if (MIPS_REGS_HAVE_HOME_P
)
2289 stack_offset
+= ROUND_UP (len
, MIPS_STACK_ARGSIZE
);
2293 /* Copy the argument to general registers or the stack in
2294 register-sized pieces. Large arguments are split between
2295 registers and stack. */
2296 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2297 are treated specially: Irix cc passes them in registers
2298 where gcc sometimes puts them on the stack. For maximum
2299 compatibility, we will put them in both places. */
2300 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2301 (len
% MIPS_SAVED_REGSIZE
!= 0));
2302 /* Note: Floating-point values that didn't fit into an FP
2303 register are only written to memory. */
2306 /* Rememer if the argument was written to the stack. */
2307 int stack_used_p
= 0;
2308 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2311 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2314 /* Write this portion of the argument to the stack. */
2315 if (argreg
> MIPS_LAST_ARG_REGNUM
2317 || fp_register_arg_p (typecode
, arg_type
))
2319 /* Should shorter than int integer values be
2320 promoted to int before being stored? */
2321 int longword_offset
= 0;
2324 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2326 if (MIPS_STACK_ARGSIZE
== 8 &&
2327 (typecode
== TYPE_CODE_INT
||
2328 typecode
== TYPE_CODE_PTR
||
2329 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2330 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2331 else if ((typecode
== TYPE_CODE_STRUCT
||
2332 typecode
== TYPE_CODE_UNION
) &&
2333 TYPE_LENGTH (arg_type
) < MIPS_STACK_ARGSIZE
)
2334 longword_offset
= MIPS_STACK_ARGSIZE
- len
;
2339 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%lx",
2340 (long) stack_offset
);
2341 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%lx",
2342 (long) longword_offset
);
2345 addr
= sp
+ stack_offset
+ longword_offset
;
2350 fprintf_unfiltered (gdb_stdlog
, " @0x%lx ", (long) addr
);
2351 for (i
= 0; i
< partial_len
; i
++)
2353 fprintf_unfiltered (gdb_stdlog
, "%02x", val
[i
] & 0xff);
2356 write_memory (addr
, val
, partial_len
);
2359 /* Note!!! This is NOT an else clause. Odd sized
2360 structs may go thru BOTH paths. Floating point
2361 arguments will not. */
2362 /* Write this portion of the argument to a general
2363 purpose register. */
2364 if (argreg
<= MIPS_LAST_ARG_REGNUM
2365 && !fp_register_arg_p (typecode
, arg_type
))
2367 LONGEST regval
= extract_unsigned_integer (val
, partial_len
);
2369 /* A non-floating-point argument being passed in a
2370 general register. If a struct or union, and if
2371 the remaining length is smaller than the register
2372 size, we have to adjust the register value on
2375 It does not seem to be necessary to do the
2376 same for integral types.
2378 Also don't do this adjustment on EABI and O64
2382 && MIPS_SAVED_REGSIZE
< 8
2383 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2384 && partial_len
< MIPS_SAVED_REGSIZE
2385 && (typecode
== TYPE_CODE_STRUCT
||
2386 typecode
== TYPE_CODE_UNION
))
2387 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2391 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2393 phex (regval
, MIPS_SAVED_REGSIZE
));
2394 write_register (argreg
, regval
);
2397 /* If this is the old ABI, prevent subsequent floating
2398 point arguments from being passed in floating point
2401 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2407 /* Compute the the offset into the stack at which we
2408 will copy the next parameter.
2410 In older ABIs, the caller reserved space for
2411 registers that contained arguments. This was loosely
2412 refered to as their "home". Consequently, space is
2415 In the new EABI (and the NABI32), the stack_offset
2416 only needs to be adjusted when it has been used.. */
2418 if (MIPS_REGS_HAVE_HOME_P
|| stack_used_p
)
2419 stack_offset
+= ROUND_UP (partial_len
, MIPS_STACK_ARGSIZE
);
2423 fprintf_unfiltered (gdb_stdlog
, "\n");
2426 /* Return adjusted stack pointer. */
2431 mips_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2433 /* Set the return address register to point to the entry
2434 point of the program, where a breakpoint lies in wait. */
2435 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2440 mips_push_register (CORE_ADDR
* sp
, int regno
)
2442 char buffer
[MAX_REGISTER_RAW_SIZE
];
2445 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2447 regsize
= MIPS_SAVED_REGSIZE
;
2448 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2449 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2454 regsize
= REGISTER_RAW_SIZE (regno
);
2458 read_register_gen (regno
, buffer
);
2459 write_memory (*sp
, buffer
+ offset
, regsize
);
2462 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2463 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2466 mips_push_dummy_frame (void)
2469 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2470 xmalloc (sizeof (struct linked_proc_info
));
2471 mips_extra_func_info_t proc_desc
= &link
->info
;
2472 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_signed_register (SP_REGNUM
));
2473 CORE_ADDR old_sp
= sp
;
2474 link
->next
= linked_proc_desc_table
;
2475 linked_proc_desc_table
= link
;
2477 /* FIXME! are these correct ? */
2478 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2479 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2480 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2481 #define FLOAT_SINGLE_REG_SAVE_MASK \
2482 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2484 * The registers we must save are all those not preserved across
2485 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2486 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2487 * and FP Control/Status registers.
2490 * Dummy frame layout:
2493 * Saved MMHI, MMLO, FPC_CSR
2498 * Saved D18 (i.e. F19, F18)
2500 * Saved D0 (i.e. F1, F0)
2501 * Argument build area and stack arguments written via mips_push_arguments
2505 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2506 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2507 PROC_FRAME_OFFSET (proc_desc
) = 0;
2508 PROC_FRAME_ADJUST (proc_desc
) = 0;
2509 mips_push_register (&sp
, PC_REGNUM
);
2510 mips_push_register (&sp
, HI_REGNUM
);
2511 mips_push_register (&sp
, LO_REGNUM
);
2512 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2514 /* Save general CPU registers */
2515 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2516 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2517 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2518 for (ireg
= 32; --ireg
>= 0;)
2519 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2520 mips_push_register (&sp
, ireg
);
2522 /* Save floating point registers starting with high order word */
2523 PROC_FREG_MASK (proc_desc
) =
2524 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2525 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2526 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2528 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2529 for (ireg
= 32; --ireg
>= 0;)
2530 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2531 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2533 /* Update the frame pointer for the call dummy and the stack pointer.
2534 Set the procedure's starting and ending addresses to point to the
2535 call dummy address at the entry point. */
2536 write_register (PUSH_FP_REGNUM
, old_sp
);
2537 write_register (SP_REGNUM
, sp
);
2538 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2539 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2540 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2541 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2545 mips_pop_frame (void)
2547 register int regnum
;
2548 struct frame_info
*frame
= get_current_frame ();
2549 CORE_ADDR new_sp
= FRAME_FP (frame
);
2551 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2553 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2554 if (frame
->saved_regs
== NULL
)
2555 mips_find_saved_regs (frame
);
2556 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2558 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2559 && frame
->saved_regs
[regnum
])
2560 write_register (regnum
,
2561 read_memory_integer (frame
->saved_regs
[regnum
],
2562 MIPS_SAVED_REGSIZE
));
2564 write_register (SP_REGNUM
, new_sp
);
2565 flush_cached_frames ();
2567 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2569 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2571 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2573 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2575 if (&pi_ptr
->info
== proc_desc
)
2580 error ("Can't locate dummy extra frame info\n");
2582 if (prev_ptr
!= NULL
)
2583 prev_ptr
->next
= pi_ptr
->next
;
2585 linked_proc_desc_table
= pi_ptr
->next
;
2589 write_register (HI_REGNUM
,
2590 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2591 MIPS_SAVED_REGSIZE
));
2592 write_register (LO_REGNUM
,
2593 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2594 MIPS_SAVED_REGSIZE
));
2595 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2596 write_register (FCRCS_REGNUM
,
2597 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2598 MIPS_SAVED_REGSIZE
));
2603 mips_print_register (int regnum
, int all
)
2605 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2607 /* Get the data in raw format. */
2608 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2610 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2614 /* If an even floating point register, also print as double. */
2615 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2616 && !((regnum
- FP0_REGNUM
) & 1))
2617 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2619 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2621 read_relative_register_raw_bytes (regnum
, dbuffer
);
2622 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2623 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2625 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2626 val_print (builtin_type_double
, dbuffer
, 0, 0,
2627 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2628 printf_filtered ("); ");
2630 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2632 /* The problem with printing numeric register names (r26, etc.) is that
2633 the user can't use them on input. Probably the best solution is to
2634 fix it so that either the numeric or the funky (a2, etc.) names
2635 are accepted on input. */
2636 if (regnum
< MIPS_NUMREGS
)
2637 printf_filtered ("(r%d): ", regnum
);
2639 printf_filtered (": ");
2641 /* If virtual format is floating, print it that way. */
2642 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2643 if (FP_REGISTER_DOUBLE
)
2644 { /* show 8-byte floats as float AND double: */
2645 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2647 printf_filtered (" (float) ");
2648 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2649 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2650 printf_filtered (", (double) ");
2651 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2652 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2655 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2656 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2657 /* Else print as integer in hex. */
2662 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2663 offset
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2667 print_scalar_formatted (raw_buffer
+ offset
,
2668 REGISTER_VIRTUAL_TYPE (regnum
),
2669 'x', 0, gdb_stdout
);
2673 /* Replacement for generic do_registers_info.
2674 Print regs in pretty columns. */
2677 do_fp_register_row (int regnum
)
2678 { /* do values for FP (float) regs */
2679 char *raw_buffer
[2];
2681 /* use HI and LO to control the order of combining two flt regs */
2682 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2683 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2684 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2685 int inv1
, inv2
, inv3
;
2687 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2688 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2689 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2691 /* Get the data in raw format. */
2692 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2693 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2694 if (REGISTER_RAW_SIZE (regnum
) == 4)
2696 /* 4-byte registers: we can fit two registers per row. */
2697 /* Also print every pair of 4-byte regs as an 8-byte double. */
2698 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2699 error ("can't read register %d (%s)",
2700 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2702 /* copy the two floats into one double, and unpack both */
2703 memcpy (dbl_buffer
, raw_buffer
, 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2704 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2705 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2706 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2708 printf_filtered (" %-5s", REGISTER_NAME (regnum
));
2710 printf_filtered (": <invalid float>");
2712 printf_filtered ("%-17.9g", flt1
);
2714 printf_filtered (" %-5s", REGISTER_NAME (regnum
+ 1));
2716 printf_filtered (": <invalid float>");
2718 printf_filtered ("%-17.9g", flt2
);
2720 printf_filtered (" dbl: ");
2722 printf_filtered ("<invalid double>");
2724 printf_filtered ("%-24.17g", doub
);
2725 printf_filtered ("\n");
2727 /* may want to do hex display here (future enhancement) */
2731 { /* eight byte registers: print each one as float AND as double. */
2732 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2734 memcpy (dbl_buffer
, raw_buffer
[HI
], 2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2735 flt1
= unpack_double (builtin_type_float
,
2736 &raw_buffer
[HI
][offset
], &inv1
);
2737 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2739 printf_filtered (" %-5s: ", REGISTER_NAME (regnum
));
2741 printf_filtered ("<invalid float>");
2743 printf_filtered ("flt: %-17.9g", flt1
);
2745 printf_filtered (" dbl: ");
2747 printf_filtered ("<invalid double>");
2749 printf_filtered ("%-24.17g", doub
);
2751 printf_filtered ("\n");
2752 /* may want to do hex display here (future enhancement) */
2758 /* Print a row's worth of GP (int) registers, with name labels above */
2761 do_gp_register_row (int regnum
)
2763 /* do values for GP (int) regs */
2764 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2765 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2767 int start_regnum
= regnum
;
2768 int numregs
= NUM_REGS
;
2771 /* For GP registers, we print a separate row of names above the vals */
2772 printf_filtered (" ");
2773 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2775 if (*REGISTER_NAME (regnum
) == '\0')
2776 continue; /* unused register */
2777 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2778 break; /* end the row: reached FP register */
2779 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2780 REGISTER_NAME (regnum
));
2783 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2784 start_regnum
); /* print the R0 to R31 names */
2786 regnum
= start_regnum
; /* go back to start of row */
2787 /* now print the values in hex, 4 or 8 to the row */
2788 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2790 if (*REGISTER_NAME (regnum
) == '\0')
2791 continue; /* unused register */
2792 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2793 break; /* end row: reached FP register */
2794 /* OK: get the data in raw format. */
2795 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2796 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2797 /* pad small registers */
2798 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2799 printf_filtered (" ");
2800 /* Now print the register value in hex, endian order. */
2801 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2802 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2803 byte
< REGISTER_RAW_SIZE (regnum
);
2805 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2807 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2810 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2811 printf_filtered (" ");
2814 if (col
> 0) /* ie. if we actually printed anything... */
2815 printf_filtered ("\n");
2820 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2823 mips_do_registers_info (int regnum
, int fpregs
)
2825 if (regnum
!= -1) /* do one specified register */
2827 if (*(REGISTER_NAME (regnum
)) == '\0')
2828 error ("Not a valid register for the current processor type");
2830 mips_print_register (regnum
, 0);
2831 printf_filtered ("\n");
2834 /* do all (or most) registers */
2837 while (regnum
< NUM_REGS
)
2839 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2840 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2841 regnum
= do_fp_register_row (regnum
); /* FP regs */
2843 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2845 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2850 /* Return number of args passed to a frame. described by FIP.
2851 Can return -1, meaning no way to tell. */
2854 mips_frame_num_args (struct frame_info
*frame
)
2859 /* Is this a branch with a delay slot? */
2861 static int is_delayed (unsigned long);
2864 is_delayed (unsigned long insn
)
2867 for (i
= 0; i
< NUMOPCODES
; ++i
)
2868 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2869 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2871 return (i
< NUMOPCODES
2872 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2873 | INSN_COND_BRANCH_DELAY
2874 | INSN_COND_BRANCH_LIKELY
)));
2878 mips_step_skips_delay (CORE_ADDR pc
)
2880 char buf
[MIPS_INSTLEN
];
2882 /* There is no branch delay slot on MIPS16. */
2883 if (pc_is_mips16 (pc
))
2886 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2887 /* If error reading memory, guess that it is not a delayed branch. */
2889 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2893 /* Skip the PC past function prologue instructions (32-bit version).
2894 This is a helper function for mips_skip_prologue. */
2897 mips32_skip_prologue (CORE_ADDR pc
)
2901 int seen_sp_adjust
= 0;
2902 int load_immediate_bytes
= 0;
2904 /* Skip the typical prologue instructions. These are the stack adjustment
2905 instruction and the instructions that save registers on the stack
2906 or in the gcc frame. */
2907 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2909 unsigned long high_word
;
2911 inst
= mips_fetch_instruction (pc
);
2912 high_word
= (inst
>> 16) & 0xffff;
2914 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2915 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2917 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2918 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2920 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2921 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2922 && (inst
& 0x001F0000)) /* reg != $zero */
2925 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2927 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2929 continue; /* reg != $zero */
2931 /* move $s8,$sp. With different versions of gas this will be either
2932 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2933 Accept any one of these. */
2934 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2937 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2939 else if (high_word
== 0x3c1c) /* lui $gp,n */
2941 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2943 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2944 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2946 /* The following instructions load $at or $t0 with an immediate
2947 value in preparation for a stack adjustment via
2948 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2949 a local variable, so we accept them only before a stack adjustment
2950 instruction was seen. */
2951 else if (!seen_sp_adjust
)
2953 if (high_word
== 0x3c01 || /* lui $at,n */
2954 high_word
== 0x3c08) /* lui $t0,n */
2956 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2959 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2960 high_word
== 0x3508 || /* ori $t0,$t0,n */
2961 high_word
== 0x3401 || /* ori $at,$zero,n */
2962 high_word
== 0x3408) /* ori $t0,$zero,n */
2964 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2974 /* In a frameless function, we might have incorrectly
2975 skipped some load immediate instructions. Undo the skipping
2976 if the load immediate was not followed by a stack adjustment. */
2977 if (load_immediate_bytes
&& !seen_sp_adjust
)
2978 pc
-= load_immediate_bytes
;
2982 /* Skip the PC past function prologue instructions (16-bit version).
2983 This is a helper function for mips_skip_prologue. */
2986 mips16_skip_prologue (CORE_ADDR pc
)
2989 int extend_bytes
= 0;
2990 int prev_extend_bytes
;
2992 /* Table of instructions likely to be found in a function prologue. */
2995 unsigned short inst
;
2996 unsigned short mask
;
3003 , /* addiu $sp,offset */
3007 , /* daddiu $sp,offset */
3011 , /* sw reg,n($sp) */
3015 , /* sd reg,n($sp) */
3019 , /* sw $ra,n($sp) */
3023 , /* sd $ra,n($sp) */
3031 , /* sw $a0-$a3,n($s1) */
3035 , /* move reg,$a0-$a3 */
3039 , /* entry pseudo-op */
3043 , /* addiu $s1,$sp,n */
3046 } /* end of table marker */
3049 /* Skip the typical prologue instructions. These are the stack adjustment
3050 instruction and the instructions that save registers on the stack
3051 or in the gcc frame. */
3052 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
3054 unsigned short inst
;
3057 inst
= mips_fetch_instruction (pc
);
3059 /* Normally we ignore an extend instruction. However, if it is
3060 not followed by a valid prologue instruction, we must adjust
3061 the pc back over the extend so that it won't be considered
3062 part of the prologue. */
3063 if ((inst
& 0xf800) == 0xf000) /* extend */
3065 extend_bytes
= MIPS16_INSTLEN
;
3068 prev_extend_bytes
= extend_bytes
;
3071 /* Check for other valid prologue instructions besides extend. */
3072 for (i
= 0; table
[i
].mask
!= 0; i
++)
3073 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
3075 if (table
[i
].mask
!= 0) /* it was in table? */
3076 continue; /* ignore it */
3080 /* Return the current pc, adjusted backwards by 2 if
3081 the previous instruction was an extend. */
3082 return pc
- prev_extend_bytes
;
3088 /* To skip prologues, I use this predicate. Returns either PC itself
3089 if the code at PC does not look like a function prologue; otherwise
3090 returns an address that (if we're lucky) follows the prologue. If
3091 LENIENT, then we must skip everything which is involved in setting
3092 up the frame (it's OK to skip more, just so long as we don't skip
3093 anything which might clobber the registers which are being saved.
3094 We must skip more in the case where part of the prologue is in the
3095 delay slot of a non-prologue instruction). */
3098 mips_skip_prologue (CORE_ADDR pc
)
3100 /* See if we can determine the end of the prologue via the symbol table.
3101 If so, then return either PC, or the PC after the prologue, whichever
3104 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
3106 if (post_prologue_pc
!= 0)
3107 return max (pc
, post_prologue_pc
);
3109 /* Can't determine prologue from the symbol table, need to examine
3112 if (pc_is_mips16 (pc
))
3113 return mips16_skip_prologue (pc
);
3115 return mips32_skip_prologue (pc
);
3118 /* Determine how a return value is stored within the MIPS register
3119 file, given the return type `valtype'. */
3121 struct return_value_word
3130 return_value_location (struct type
*valtype
,
3131 struct return_value_word
*hi
,
3132 struct return_value_word
*lo
)
3134 int len
= TYPE_LENGTH (valtype
);
3136 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3137 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
3138 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
3140 if (!FP_REGISTER_DOUBLE
&& len
== 8)
3142 /* We need to break a 64bit float in two 32 bit halves and
3143 spread them across a floating-point register pair. */
3144 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
3145 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
3146 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3147 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
3149 hi
->reg_offset
= lo
->reg_offset
;
3150 lo
->reg
= FP0_REGNUM
+ 0;
3151 hi
->reg
= FP0_REGNUM
+ 1;
3157 /* The floating point value fits in a single floating-point
3159 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
3160 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
3163 lo
->reg
= FP0_REGNUM
;
3174 /* Locate a result possibly spread across two registers. */
3176 lo
->reg
= regnum
+ 0;
3177 hi
->reg
= regnum
+ 1;
3178 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3179 && len
< MIPS_SAVED_REGSIZE
)
3181 /* "un-left-justify" the value in the low register */
3182 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
3187 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3188 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
3189 && len
< MIPS_SAVED_REGSIZE
* 2
3190 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3191 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3193 /* "un-left-justify" the value spread across two registers. */
3194 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
3195 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
3197 hi
->len
= len
- lo
->len
;
3201 /* Only perform a partial copy of the second register. */
3204 if (len
> MIPS_SAVED_REGSIZE
)
3206 lo
->len
= MIPS_SAVED_REGSIZE
;
3207 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
3215 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
3216 && REGISTER_RAW_SIZE (regnum
) == 8
3217 && MIPS_SAVED_REGSIZE
== 4)
3219 /* Account for the fact that only the least-signficant part
3220 of the register is being used */
3221 lo
->reg_offset
+= 4;
3222 hi
->reg_offset
+= 4;
3225 hi
->buf_offset
= lo
->len
;
3229 /* Given a return value in `regbuf' with a type `valtype', extract and
3230 copy its value into `valbuf'. */
3233 mips_extract_return_value (struct type
*valtype
,
3234 char regbuf
[REGISTER_BYTES
],
3237 struct return_value_word lo
;
3238 struct return_value_word hi
;
3239 return_value_location (valtype
, &hi
, &lo
);
3241 memcpy (valbuf
+ lo
.buf_offset
,
3242 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
3246 memcpy (valbuf
+ hi
.buf_offset
,
3247 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
3251 /* Given a return value in `valbuf' with a type `valtype', write it's
3252 value into the appropriate register. */
3255 mips_store_return_value (struct type
*valtype
, char *valbuf
)
3257 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3258 struct return_value_word lo
;
3259 struct return_value_word hi
;
3260 return_value_location (valtype
, &hi
, &lo
);
3262 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3263 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3264 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3266 REGISTER_RAW_SIZE (lo
.reg
));
3270 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3271 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3272 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3274 REGISTER_RAW_SIZE (hi
.reg
));
3278 /* Exported procedure: Is PC in the signal trampoline code */
3281 in_sigtramp (CORE_ADDR pc
, char *ignore
)
3283 if (sigtramp_address
== 0)
3285 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3288 /* Root of all "set mips "/"show mips " commands. This will eventually be
3289 used for all MIPS-specific commands. */
3292 show_mips_command (char *args
, int from_tty
)
3294 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
3298 set_mips_command (char *args
, int from_tty
)
3300 printf_unfiltered ("\"set mips\" must be followed by an appropriate subcommand.\n");
3301 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
3304 /* Commands to show/set the MIPS FPU type. */
3307 show_mipsfpu_command (char *args
, int from_tty
)
3310 switch (MIPS_FPU_TYPE
)
3312 case MIPS_FPU_SINGLE
:
3313 fpu
= "single-precision";
3315 case MIPS_FPU_DOUBLE
:
3316 fpu
= "double-precision";
3319 fpu
= "absent (none)";
3322 internal_error (__FILE__
, __LINE__
, "bad switch");
3324 if (mips_fpu_type_auto
)
3325 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3328 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3334 set_mipsfpu_command (char *args
, int from_tty
)
3336 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3337 show_mipsfpu_command (args
, from_tty
);
3341 set_mipsfpu_single_command (char *args
, int from_tty
)
3343 mips_fpu_type
= MIPS_FPU_SINGLE
;
3344 mips_fpu_type_auto
= 0;
3347 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_SINGLE
;
3352 set_mipsfpu_double_command (char *args
, int from_tty
)
3354 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3355 mips_fpu_type_auto
= 0;
3358 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_DOUBLE
;
3363 set_mipsfpu_none_command (char *args
, int from_tty
)
3365 mips_fpu_type
= MIPS_FPU_NONE
;
3366 mips_fpu_type_auto
= 0;
3369 gdbarch_tdep (current_gdbarch
)->mips_fpu_type
= MIPS_FPU_NONE
;
3374 set_mipsfpu_auto_command (char *args
, int from_tty
)
3376 mips_fpu_type_auto
= 1;
3379 /* Command to set the processor type. */
3382 mips_set_processor_type_command (char *args
, int from_tty
)
3386 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3388 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3389 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3390 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3392 /* Restore the value. */
3393 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3398 if (!mips_set_processor_type (tmp_mips_processor_type
))
3400 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3401 /* Restore its value. */
3402 tmp_mips_processor_type
= xstrdup (mips_processor_type
);
3407 mips_show_processor_type_command (char *args
, int from_tty
)
3411 /* Modify the actual processor type. */
3414 mips_set_processor_type (char *str
)
3421 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3423 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3425 mips_processor_type
= str
;
3426 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3428 /* FIXME tweak fpu flag too */
3435 /* Attempt to identify the particular processor model by reading the
3439 mips_read_processor_type (void)
3443 prid
= read_register (PRID_REGNUM
);
3445 if ((prid
& ~0xf) == 0x700)
3446 return savestring ("r3041", strlen ("r3041"));
3451 /* Just like reinit_frame_cache, but with the right arguments to be
3452 callable as an sfunc. */
3455 reinit_frame_cache_sfunc (char *args
, int from_tty
,
3456 struct cmd_list_element
*c
)
3458 reinit_frame_cache ();
3462 gdb_print_insn_mips (bfd_vma memaddr
, disassemble_info
*info
)
3464 mips_extra_func_info_t proc_desc
;
3466 /* Search for the function containing this address. Set the low bit
3467 of the address when searching, in case we were given an even address
3468 that is the start of a 16-bit function. If we didn't do this,
3469 the search would fail because the symbol table says the function
3470 starts at an odd address, i.e. 1 byte past the given address. */
3471 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3472 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3474 /* Make an attempt to determine if this is a 16-bit function. If
3475 the procedure descriptor exists and the address therein is odd,
3476 it's definitely a 16-bit function. Otherwise, we have to just
3477 guess that if the address passed in is odd, it's 16-bits. */
3479 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ?
3480 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3482 info
->mach
= pc_is_mips16 (memaddr
) ?
3483 bfd_mach_mips16
: TM_PRINT_INSN_MACH
;
3485 /* Round down the instruction address to the appropriate boundary. */
3486 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
3488 /* Call the appropriate disassembler based on the target endian-ness. */
3489 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3490 return print_insn_big_mips (memaddr
, info
);
3492 return print_insn_little_mips (memaddr
, info
);
3495 /* Old-style breakpoint macros.
3496 The IDT board uses an unusual breakpoint value, and sometimes gets
3497 confused when it sees the usual MIPS breakpoint instruction. */
3499 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3500 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3501 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3502 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3503 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3504 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3505 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3506 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3508 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3509 counter value to determine whether a 16- or 32-bit breakpoint should be
3510 used. It returns a pointer to a string of bytes that encode a breakpoint
3511 instruction, stores the length of the string to *lenptr, and adjusts pc
3512 (if necessary) to point to the actual memory location where the
3513 breakpoint should be inserted. */
3516 mips_breakpoint_from_pc (CORE_ADDR
* pcptr
, int *lenptr
)
3518 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3520 if (pc_is_mips16 (*pcptr
))
3522 static unsigned char mips16_big_breakpoint
[] =
3523 MIPS16_BIG_BREAKPOINT
;
3524 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3525 *lenptr
= sizeof (mips16_big_breakpoint
);
3526 return mips16_big_breakpoint
;
3530 static unsigned char big_breakpoint
[] = BIG_BREAKPOINT
;
3531 static unsigned char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3532 static unsigned char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3534 *lenptr
= sizeof (big_breakpoint
);
3536 if (strcmp (target_shortname
, "mips") == 0)
3537 return idt_big_breakpoint
;
3538 else if (strcmp (target_shortname
, "ddb") == 0
3539 || strcmp (target_shortname
, "pmon") == 0
3540 || strcmp (target_shortname
, "lsi") == 0)
3541 return pmon_big_breakpoint
;
3543 return big_breakpoint
;
3548 if (pc_is_mips16 (*pcptr
))
3550 static unsigned char mips16_little_breakpoint
[] =
3551 MIPS16_LITTLE_BREAKPOINT
;
3552 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3553 *lenptr
= sizeof (mips16_little_breakpoint
);
3554 return mips16_little_breakpoint
;
3558 static unsigned char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3559 static unsigned char pmon_little_breakpoint
[] =
3560 PMON_LITTLE_BREAKPOINT
;
3561 static unsigned char idt_little_breakpoint
[] =
3562 IDT_LITTLE_BREAKPOINT
;
3564 *lenptr
= sizeof (little_breakpoint
);
3566 if (strcmp (target_shortname
, "mips") == 0)
3567 return idt_little_breakpoint
;
3568 else if (strcmp (target_shortname
, "ddb") == 0
3569 || strcmp (target_shortname
, "pmon") == 0
3570 || strcmp (target_shortname
, "lsi") == 0)
3571 return pmon_little_breakpoint
;
3573 return little_breakpoint
;
3578 /* If PC is in a mips16 call or return stub, return the address of the target
3579 PC, which is either the callee or the caller. There are several
3580 cases which must be handled:
3582 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3583 target PC is in $31 ($ra).
3584 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3585 and the target PC is in $2.
3586 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3587 before the jal instruction, this is effectively a call stub
3588 and the the target PC is in $2. Otherwise this is effectively
3589 a return stub and the target PC is in $18.
3591 See the source code for the stubs in gcc/config/mips/mips16.S for
3594 This function implements the SKIP_TRAMPOLINE_CODE macro.
3598 mips_skip_stub (CORE_ADDR pc
)
3601 CORE_ADDR start_addr
;
3603 /* Find the starting address and name of the function containing the PC. */
3604 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3607 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3608 target PC is in $31 ($ra). */
3609 if (strcmp (name
, "__mips16_ret_sf") == 0
3610 || strcmp (name
, "__mips16_ret_df") == 0)
3611 return read_signed_register (RA_REGNUM
);
3613 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3615 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3616 and the target PC is in $2. */
3617 if (name
[19] >= '0' && name
[19] <= '9')
3618 return read_signed_register (2);
3620 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3621 before the jal instruction, this is effectively a call stub
3622 and the the target PC is in $2. Otherwise this is effectively
3623 a return stub and the target PC is in $18. */
3624 else if (name
[19] == 's' || name
[19] == 'd')
3626 if (pc
== start_addr
)
3628 /* Check if the target of the stub is a compiler-generated
3629 stub. Such a stub for a function bar might have a name
3630 like __fn_stub_bar, and might look like this:
3635 la $1,bar (becomes a lui/addiu pair)
3637 So scan down to the lui/addi and extract the target
3638 address from those two instructions. */
3640 CORE_ADDR target_pc
= read_signed_register (2);
3644 /* See if the name of the target function is __fn_stub_*. */
3645 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3647 if (strncmp (name
, "__fn_stub_", 10) != 0
3648 && strcmp (name
, "etext") != 0
3649 && strcmp (name
, "_etext") != 0)
3652 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3653 The limit on the search is arbitrarily set to 20
3654 instructions. FIXME. */
3655 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3657 inst
= mips_fetch_instruction (target_pc
);
3658 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3659 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3660 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3661 return pc
| (inst
& 0xffff); /* low word */
3664 /* Couldn't find the lui/addui pair, so return stub address. */
3668 /* This is the 'return' part of a call stub. The return
3669 address is in $r18. */
3670 return read_signed_register (18);
3673 return 0; /* not a stub */
3677 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3678 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3681 mips_in_call_stub (CORE_ADDR pc
, char *name
)
3683 CORE_ADDR start_addr
;
3685 /* Find the starting address of the function containing the PC. If the
3686 caller didn't give us a name, look it up at the same time. */
3687 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3690 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3692 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3693 if (name
[19] >= '0' && name
[19] <= '9')
3695 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3696 before the jal instruction, this is effectively a call stub. */
3697 else if (name
[19] == 's' || name
[19] == 'd')
3698 return pc
== start_addr
;
3701 return 0; /* not a stub */
3705 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3706 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3709 mips_in_return_stub (CORE_ADDR pc
, char *name
)
3711 CORE_ADDR start_addr
;
3713 /* Find the starting address of the function containing the PC. */
3714 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3717 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3718 if (strcmp (name
, "__mips16_ret_sf") == 0
3719 || strcmp (name
, "__mips16_ret_df") == 0)
3722 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3723 i.e. after the jal instruction, this is effectively a return stub. */
3724 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3725 && (name
[19] == 's' || name
[19] == 'd')
3726 && pc
!= start_addr
)
3729 return 0; /* not a stub */
3733 /* Return non-zero if the PC is in a library helper function that should
3734 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3737 mips_ignore_helper (CORE_ADDR pc
)
3741 /* Find the starting address and name of the function containing the PC. */
3742 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3745 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3746 that we want to ignore. */
3747 return (strcmp (name
, "__mips16_ret_sf") == 0
3748 || strcmp (name
, "__mips16_ret_df") == 0);
3752 /* Return a location where we can set a breakpoint that will be hit
3753 when an inferior function call returns. This is normally the
3754 program's entry point. Executables that don't have an entry
3755 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3756 whose address is the location where the breakpoint should be placed. */
3759 mips_call_dummy_address (void)
3761 struct minimal_symbol
*sym
;
3763 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3765 return SYMBOL_VALUE_ADDRESS (sym
);
3767 return entry_point_address ();
3771 /* If the current gcc for this target does not produce correct debugging
3772 information for float parameters, both prototyped and unprototyped, then
3773 define this macro. This forces gdb to always assume that floats are
3774 passed as doubles and then converted in the callee.
3776 For the mips chip, it appears that the debug info marks the parameters as
3777 floats regardless of whether the function is prototyped, but the actual
3778 values are passed as doubles for the non-prototyped case and floats for
3779 the prototyped case. Thus we choose to make the non-prototyped case work
3780 for C and break the prototyped case, since the non-prototyped case is
3781 probably much more common. (FIXME). */
3784 mips_coerce_float_to_double (struct type
*formal
, struct type
*actual
)
3786 return current_language
->la_language
== language_c
;
3789 /* When debugging a 64 MIPS target running a 32 bit ABI, the size of
3790 the register stored on the stack (32) is different to its real raw
3791 size (64). The below ensures that registers are fetched from the
3792 stack using their ABI size and then stored into the RAW_BUFFER
3793 using their raw size.
3795 The alternative to adding this function would be to add an ABI
3796 macro - REGISTER_STACK_SIZE(). */
3799 mips_get_saved_register (char *raw_buffer
,
3802 struct frame_info
*frame
,
3804 enum lval_type
*lval
)
3808 if (!target_has_registers
)
3809 error ("No registers.");
3811 /* Normal systems don't optimize out things with register numbers. */
3812 if (optimized
!= NULL
)
3814 addr
= find_saved_register (frame
, regnum
);
3818 *lval
= lval_memory
;
3819 if (regnum
== SP_REGNUM
)
3821 if (raw_buffer
!= NULL
)
3823 /* Put it back in target format. */
3824 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
3831 if (raw_buffer
!= NULL
)
3835 /* Only MIPS_SAVED_REGSIZE bytes of GP registers are
3837 val
= read_memory_integer (addr
, MIPS_SAVED_REGSIZE
);
3839 val
= read_memory_integer (addr
, REGISTER_RAW_SIZE (regnum
));
3840 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
), val
);
3846 *lval
= lval_register
;
3847 addr
= REGISTER_BYTE (regnum
);
3848 if (raw_buffer
!= NULL
)
3849 read_register_gen (regnum
, raw_buffer
);
3855 /* Immediately after a function call, return the saved pc.
3856 Can't always go through the frames for this because on some machines
3857 the new frame is not set up until the new function executes
3858 some instructions. */
3861 mips_saved_pc_after_call (struct frame_info
*frame
)
3863 return read_signed_register (RA_REGNUM
);
3867 /* Convert a dbx stab register number (from `r' declaration) to a gdb
3871 mips_stab_reg_to_regnum (int num
)
3876 return num
+ FP0_REGNUM
- 38;
3879 /* Convert a ecoff register number to a gdb REGNUM */
3882 mips_ecoff_reg_to_regnum (int num
)
3887 return num
+ FP0_REGNUM
- 32;
3890 static struct gdbarch
*
3891 mips_gdbarch_init (struct gdbarch_info info
,
3892 struct gdbarch_list
*arches
)
3894 static LONGEST mips_call_dummy_words
[] =
3896 struct gdbarch
*gdbarch
;
3897 struct gdbarch_tdep
*tdep
;
3899 enum mips_abi mips_abi
;
3901 /* Reset the disassembly info, in case it was set to something
3903 tm_print_insn_info
.flavour
= bfd_target_unknown_flavour
;
3904 tm_print_insn_info
.arch
= bfd_arch_unknown
;
3905 tm_print_insn_info
.mach
= 0;
3907 /* Extract the elf_flags if available */
3908 if (info
.abfd
!= NULL
3909 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
3910 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
3914 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
3915 switch ((elf_flags
& EF_MIPS_ABI
))
3917 case E_MIPS_ABI_O32
:
3918 mips_abi
= MIPS_ABI_O32
;
3920 case E_MIPS_ABI_O64
:
3921 mips_abi
= MIPS_ABI_O64
;
3923 case E_MIPS_ABI_EABI32
:
3924 mips_abi
= MIPS_ABI_EABI32
;
3926 case E_MIPS_ABI_EABI64
:
3927 mips_abi
= MIPS_ABI_EABI64
;
3930 if ((elf_flags
& EF_MIPS_ABI2
))
3931 mips_abi
= MIPS_ABI_N32
;
3933 mips_abi
= MIPS_ABI_UNKNOWN
;
3937 /* Try the architecture for any hint of the corect ABI */
3938 if (mips_abi
== MIPS_ABI_UNKNOWN
3939 && info
.bfd_arch_info
!= NULL
3940 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
3942 switch (info
.bfd_arch_info
->mach
)
3944 case bfd_mach_mips3900
:
3945 mips_abi
= MIPS_ABI_EABI32
;
3947 case bfd_mach_mips4100
:
3948 case bfd_mach_mips5000
:
3949 mips_abi
= MIPS_ABI_EABI64
;
3951 case bfd_mach_mips8000
:
3952 case bfd_mach_mips10000
:
3953 mips_abi
= MIPS_ABI_N32
;
3957 #ifdef MIPS_DEFAULT_ABI
3958 if (mips_abi
== MIPS_ABI_UNKNOWN
)
3959 mips_abi
= MIPS_DEFAULT_ABI
;
3964 fprintf_unfiltered (gdb_stdlog
,
3965 "mips_gdbarch_init: elf_flags = 0x%08x\n",
3967 fprintf_unfiltered (gdb_stdlog
,
3968 "mips_gdbarch_init: mips_abi = %d\n",
3972 /* try to find a pre-existing architecture */
3973 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3975 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3977 /* MIPS needs to be pedantic about which ABI the object is
3979 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
3981 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
3983 return arches
->gdbarch
;
3986 /* Need a new architecture. Fill in a target specific vector. */
3987 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
3988 gdbarch
= gdbarch_alloc (&info
, tdep
);
3989 tdep
->elf_flags
= elf_flags
;
3991 /* Initially set everything according to the ABI. */
3992 set_gdbarch_short_bit (gdbarch
, 16);
3993 set_gdbarch_int_bit (gdbarch
, 32);
3994 set_gdbarch_float_bit (gdbarch
, 32);
3995 set_gdbarch_double_bit (gdbarch
, 64);
3996 set_gdbarch_long_double_bit (gdbarch
, 64);
3997 tdep
->mips_abi
= mips_abi
;
4002 tdep
->mips_abi_string
= "o32";
4003 tdep
->mips_default_saved_regsize
= 4;
4004 tdep
->mips_default_stack_argsize
= 4;
4005 tdep
->mips_fp_register_double
= 0;
4006 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4007 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4008 tdep
->mips_regs_have_home_p
= 1;
4009 tdep
->gdb_target_is_mips64
= 0;
4010 tdep
->default_mask_address_p
= 0;
4011 set_gdbarch_long_bit (gdbarch
, 32);
4012 set_gdbarch_ptr_bit (gdbarch
, 32);
4013 set_gdbarch_long_long_bit (gdbarch
, 64);
4016 tdep
->mips_abi_string
= "o64";
4017 tdep
->mips_default_saved_regsize
= 8;
4018 tdep
->mips_default_stack_argsize
= 8;
4019 tdep
->mips_fp_register_double
= 1;
4020 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 4 - 1;
4021 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 4 - 1;
4022 tdep
->mips_regs_have_home_p
= 1;
4023 tdep
->gdb_target_is_mips64
= 1;
4024 tdep
->default_mask_address_p
= 0;
4025 set_gdbarch_long_bit (gdbarch
, 32);
4026 set_gdbarch_ptr_bit (gdbarch
, 32);
4027 set_gdbarch_long_long_bit (gdbarch
, 64);
4029 case MIPS_ABI_EABI32
:
4030 tdep
->mips_abi_string
= "eabi32";
4031 tdep
->mips_default_saved_regsize
= 4;
4032 tdep
->mips_default_stack_argsize
= 4;
4033 tdep
->mips_fp_register_double
= 0;
4034 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4035 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4036 tdep
->mips_regs_have_home_p
= 0;
4037 tdep
->gdb_target_is_mips64
= 0;
4038 tdep
->default_mask_address_p
= 0;
4039 set_gdbarch_long_bit (gdbarch
, 32);
4040 set_gdbarch_ptr_bit (gdbarch
, 32);
4041 set_gdbarch_long_long_bit (gdbarch
, 64);
4043 case MIPS_ABI_EABI64
:
4044 tdep
->mips_abi_string
= "eabi64";
4045 tdep
->mips_default_saved_regsize
= 8;
4046 tdep
->mips_default_stack_argsize
= 8;
4047 tdep
->mips_fp_register_double
= 1;
4048 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4049 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4050 tdep
->mips_regs_have_home_p
= 0;
4051 tdep
->gdb_target_is_mips64
= 1;
4052 tdep
->default_mask_address_p
= 0;
4053 set_gdbarch_long_bit (gdbarch
, 64);
4054 set_gdbarch_ptr_bit (gdbarch
, 64);
4055 set_gdbarch_long_long_bit (gdbarch
, 64);
4058 tdep
->mips_abi_string
= "n32";
4059 tdep
->mips_default_saved_regsize
= 4;
4060 tdep
->mips_default_stack_argsize
= 8;
4061 tdep
->mips_fp_register_double
= 1;
4062 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4063 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4064 tdep
->mips_regs_have_home_p
= 0;
4065 tdep
->gdb_target_is_mips64
= 0;
4066 tdep
->default_mask_address_p
= 0;
4067 set_gdbarch_long_bit (gdbarch
, 32);
4068 set_gdbarch_ptr_bit (gdbarch
, 32);
4069 set_gdbarch_long_long_bit (gdbarch
, 64);
4071 /* Set up the disassembler info, so that we get the right
4072 register names from libopcodes. */
4073 tm_print_insn_info
.flavour
= bfd_target_elf_flavour
;
4074 tm_print_insn_info
.arch
= bfd_arch_mips
;
4075 if (info
.bfd_arch_info
!= NULL
4076 && info
.bfd_arch_info
->arch
== bfd_arch_mips
4077 && info
.bfd_arch_info
->mach
)
4078 tm_print_insn_info
.mach
= info
.bfd_arch_info
->mach
;
4080 tm_print_insn_info
.mach
= bfd_mach_mips8000
;
4083 tdep
->mips_abi_string
= "default";
4084 tdep
->mips_default_saved_regsize
= MIPS_REGSIZE
;
4085 tdep
->mips_default_stack_argsize
= MIPS_REGSIZE
;
4086 tdep
->mips_fp_register_double
= (REGISTER_VIRTUAL_SIZE (FP0_REGNUM
) == 8);
4087 tdep
->mips_last_arg_regnum
= A0_REGNUM
+ 8 - 1;
4088 tdep
->mips_last_fp_arg_regnum
= FPA0_REGNUM
+ 8 - 1;
4089 tdep
->mips_regs_have_home_p
= 1;
4090 tdep
->gdb_target_is_mips64
= 0;
4091 tdep
->default_mask_address_p
= 0;
4092 set_gdbarch_long_bit (gdbarch
, 32);
4093 set_gdbarch_ptr_bit (gdbarch
, 32);
4094 set_gdbarch_long_long_bit (gdbarch
, 64);
4098 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
4099 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
4102 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
4103 flag in object files because to do so would make it impossible to
4104 link with libraries compiled without "-gp32". This is
4105 unnecessarily restrictive.
4107 We could solve this problem by adding "-gp32" multilibs to gcc,
4108 but to set this flag before gcc is built with such multilibs will
4109 break too many systems.''
4111 But even more unhelpfully, the default linker output target for
4112 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
4113 for 64-bit programs - you need to change the ABI to change this,
4114 and not all gcc targets support that currently. Therefore using
4115 this flag to detect 32-bit mode would do the wrong thing given
4116 the current gcc - it would make GDB treat these 64-bit programs
4117 as 32-bit programs by default. */
4119 /* enable/disable the MIPS FPU */
4120 if (!mips_fpu_type_auto
)
4121 tdep
->mips_fpu_type
= mips_fpu_type
;
4122 else if (info
.bfd_arch_info
!= NULL
4123 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
4124 switch (info
.bfd_arch_info
->mach
)
4126 case bfd_mach_mips3900
:
4127 case bfd_mach_mips4100
:
4128 case bfd_mach_mips4111
:
4129 tdep
->mips_fpu_type
= MIPS_FPU_NONE
;
4131 case bfd_mach_mips4650
:
4132 tdep
->mips_fpu_type
= MIPS_FPU_SINGLE
;
4135 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4139 tdep
->mips_fpu_type
= MIPS_FPU_DOUBLE
;
4141 /* MIPS version of register names. NOTE: At present the MIPS
4142 register name management is part way between the old -
4143 #undef/#define REGISTER_NAMES and the new REGISTER_NAME(nr).
4144 Further work on it is required. */
4145 set_gdbarch_register_name (gdbarch
, mips_register_name
);
4146 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
4147 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4148 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4149 set_gdbarch_write_fp (gdbarch
, generic_target_write_fp
);
4150 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4151 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4153 /* Add/remove bits from an address. The MIPS needs be careful to
4154 ensure that all 32 bit addresses are sign extended to 64 bits. */
4155 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
4157 /* There's a mess in stack frame creation. See comments in
4158 blockframe.c near reference to INIT_FRAME_PC_FIRST. */
4159 set_gdbarch_init_frame_pc_first (gdbarch
, mips_init_frame_pc_first
);
4160 set_gdbarch_init_frame_pc (gdbarch
, init_frame_pc_noop
);
4162 /* Map debug register numbers onto internal register numbers. */
4163 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
4164 set_gdbarch_ecoff_reg_to_regnum (gdbarch
, mips_ecoff_reg_to_regnum
);
4166 /* Initialize a frame */
4167 set_gdbarch_init_extra_frame_info (gdbarch
, mips_init_extra_frame_info
);
4169 /* MIPS version of CALL_DUMMY */
4171 set_gdbarch_call_dummy_p (gdbarch
, 1);
4172 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4173 set_gdbarch_use_generic_dummy_frames (gdbarch
, 0);
4174 set_gdbarch_call_dummy_location (gdbarch
, AT_ENTRY_POINT
);
4175 set_gdbarch_call_dummy_address (gdbarch
, mips_call_dummy_address
);
4176 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4177 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1);
4178 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4179 set_gdbarch_call_dummy_length (gdbarch
, 0);
4180 set_gdbarch_pc_in_call_dummy (gdbarch
, pc_in_call_dummy_at_entry_point
);
4181 set_gdbarch_call_dummy_words (gdbarch
, mips_call_dummy_words
);
4182 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (mips_call_dummy_words
));
4183 set_gdbarch_push_return_address (gdbarch
, mips_push_return_address
);
4184 set_gdbarch_push_arguments (gdbarch
, mips_push_arguments
);
4185 set_gdbarch_register_convertible (gdbarch
, generic_register_convertible_not
);
4186 set_gdbarch_coerce_float_to_double (gdbarch
, mips_coerce_float_to_double
);
4188 set_gdbarch_frame_chain_valid (gdbarch
, func_frame_chain_valid
);
4189 set_gdbarch_get_saved_register (gdbarch
, mips_get_saved_register
);
4191 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4192 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
4193 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4194 set_gdbarch_ieee_float (gdbarch
, 1);
4196 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
4197 set_gdbarch_saved_pc_after_call (gdbarch
, mips_saved_pc_after_call
);
4203 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4205 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4209 int ef_mips_32bitmode
;
4210 /* determine the ISA */
4211 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
4229 /* determine the size of a pointer */
4230 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
4231 fprintf_unfiltered (file
,
4232 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
4234 fprintf_unfiltered (file
,
4235 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
4237 fprintf_unfiltered (file
,
4238 "mips_dump_tdep: ef_mips_arch = %d\n",
4240 fprintf_unfiltered (file
,
4241 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
4243 tdep
->mips_abi_string
);
4244 fprintf_unfiltered (file
,
4245 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
4246 mips_mask_address_p (),
4247 tdep
->default_mask_address_p
);
4249 fprintf_unfiltered (file
,
4250 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4251 FP_REGISTER_DOUBLE
);
4252 fprintf_unfiltered (file
,
4253 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
4254 MIPS_DEFAULT_FPU_TYPE
,
4255 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4256 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4257 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4259 fprintf_unfiltered (file
,
4260 "mips_dump_tdep: MIPS_EABI = %d\n",
4262 fprintf_unfiltered (file
,
4263 "mips_dump_tdep: MIPS_LAST_FP_ARG_REGNUM = %d (%d regs)\n",
4264 MIPS_LAST_FP_ARG_REGNUM
,
4265 MIPS_LAST_FP_ARG_REGNUM
- FPA0_REGNUM
+ 1);
4266 fprintf_unfiltered (file
,
4267 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
4269 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
4270 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
4271 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
4273 fprintf_unfiltered (file
,
4274 "mips_dump_tdep: MIPS_DEFAULT_SAVED_REGSIZE = %d\n",
4275 MIPS_DEFAULT_SAVED_REGSIZE
);
4276 fprintf_unfiltered (file
,
4277 "mips_dump_tdep: FP_REGISTER_DOUBLE = %d\n",
4278 FP_REGISTER_DOUBLE
);
4279 fprintf_unfiltered (file
,
4280 "mips_dump_tdep: MIPS_REGS_HAVE_HOME_P = %d\n",
4281 MIPS_REGS_HAVE_HOME_P
);
4282 fprintf_unfiltered (file
,
4283 "mips_dump_tdep: MIPS_DEFAULT_STACK_ARGSIZE = %d\n",
4284 MIPS_DEFAULT_STACK_ARGSIZE
);
4285 fprintf_unfiltered (file
,
4286 "mips_dump_tdep: MIPS_STACK_ARGSIZE = %d\n",
4287 MIPS_STACK_ARGSIZE
);
4288 fprintf_unfiltered (file
,
4289 "mips_dump_tdep: MIPS_REGSIZE = %d\n",
4291 fprintf_unfiltered (file
,
4292 "mips_dump_tdep: A0_REGNUM = %d\n",
4294 fprintf_unfiltered (file
,
4295 "mips_dump_tdep: ADDR_BITS_REMOVE # %s\n",
4296 XSTRING (ADDR_BITS_REMOVE(ADDR
)));
4297 fprintf_unfiltered (file
,
4298 "mips_dump_tdep: ATTACH_DETACH # %s\n",
4299 XSTRING (ATTACH_DETACH
));
4300 fprintf_unfiltered (file
,
4301 "mips_dump_tdep: BADVADDR_REGNUM = %d\n",
4303 fprintf_unfiltered (file
,
4304 "mips_dump_tdep: BIG_BREAKPOINT = delete?\n");
4305 fprintf_unfiltered (file
,
4306 "mips_dump_tdep: CAUSE_REGNUM = %d\n",
4308 fprintf_unfiltered (file
,
4309 "mips_dump_tdep: CPLUS_MARKER = %c\n",
4311 fprintf_unfiltered (file
,
4312 "mips_dump_tdep: DEFAULT_MIPS_TYPE = %s\n",
4314 fprintf_unfiltered (file
,
4315 "mips_dump_tdep: DO_REGISTERS_INFO # %s\n",
4316 XSTRING (DO_REGISTERS_INFO
));
4317 fprintf_unfiltered (file
,
4318 "mips_dump_tdep: DWARF_REG_TO_REGNUM # %s\n",
4319 XSTRING (DWARF_REG_TO_REGNUM (REGNUM
)));
4320 fprintf_unfiltered (file
,
4321 "mips_dump_tdep: ECOFF_REG_TO_REGNUM # %s\n",
4322 XSTRING (ECOFF_REG_TO_REGNUM (REGNUM
)));
4323 fprintf_unfiltered (file
,
4324 "mips_dump_tdep: ELF_MAKE_MSYMBOL_SPECIAL # %s\n",
4325 XSTRING (ELF_MAKE_MSYMBOL_SPECIAL (SYM
, MSYM
)));
4326 fprintf_unfiltered (file
,
4327 "mips_dump_tdep: FCRCS_REGNUM = %d\n",
4329 fprintf_unfiltered (file
,
4330 "mips_dump_tdep: FCRIR_REGNUM = %d\n",
4332 fprintf_unfiltered (file
,
4333 "mips_dump_tdep: FIRST_EMBED_REGNUM = %d\n",
4334 FIRST_EMBED_REGNUM
);
4335 fprintf_unfiltered (file
,
4336 "mips_dump_tdep: FPA0_REGNUM = %d\n",
4338 fprintf_unfiltered (file
,
4339 "mips_dump_tdep: GDB_TARGET_IS_MIPS64 = %d\n",
4340 GDB_TARGET_IS_MIPS64
);
4341 fprintf_unfiltered (file
,
4342 "mips_dump_tdep: GDB_TARGET_MASK_DISAS_PC # %s\n",
4343 XSTRING (GDB_TARGET_MASK_DISAS_PC (PC
)));
4344 fprintf_unfiltered (file
,
4345 "mips_dump_tdep: GDB_TARGET_UNMASK_DISAS_PC # %s\n",
4346 XSTRING (GDB_TARGET_UNMASK_DISAS_PC (PC
)));
4347 fprintf_unfiltered (file
,
4348 "mips_dump_tdep: GEN_REG_SAVE_MASK = %d\n",
4350 fprintf_unfiltered (file
,
4351 "mips_dump_tdep: HAVE_NONSTEPPABLE_WATCHPOINT # %s\n",
4352 XSTRING (HAVE_NONSTEPPABLE_WATCHPOINT
));
4353 fprintf_unfiltered (file
,
4354 "mips_dump_tdep: HI_REGNUM = %d\n",
4356 fprintf_unfiltered (file
,
4357 "mips_dump_tdep: IDT_BIG_BREAKPOINT = delete?\n");
4358 fprintf_unfiltered (file
,
4359 "mips_dump_tdep: IDT_LITTLE_BREAKPOINT = delete?\n");
4360 fprintf_unfiltered (file
,
4361 "mips_dump_tdep: IGNORE_HELPER_CALL # %s\n",
4362 XSTRING (IGNORE_HELPER_CALL (PC
)));
4363 fprintf_unfiltered (file
,
4364 "mips_dump_tdep: IN_SIGTRAMP # %s\n",
4365 XSTRING (IN_SIGTRAMP (PC
, NAME
)));
4366 fprintf_unfiltered (file
,
4367 "mips_dump_tdep: IN_SOLIB_CALL_TRAMPOLINE # %s\n",
4368 XSTRING (IN_SOLIB_CALL_TRAMPOLINE (PC
, NAME
)));
4369 fprintf_unfiltered (file
,
4370 "mips_dump_tdep: IN_SOLIB_RETURN_TRAMPOLINE # %s\n",
4371 XSTRING (IN_SOLIB_RETURN_TRAMPOLINE (PC
, NAME
)));
4372 fprintf_unfiltered (file
,
4373 "mips_dump_tdep: IS_MIPS16_ADDR = FIXME!\n");
4374 fprintf_unfiltered (file
,
4375 "mips_dump_tdep: LAST_EMBED_REGNUM = %d\n",
4377 fprintf_unfiltered (file
,
4378 "mips_dump_tdep: LITTLE_BREAKPOINT = delete?\n");
4379 fprintf_unfiltered (file
,
4380 "mips_dump_tdep: LO_REGNUM = %d\n",
4382 #ifdef MACHINE_CPROC_FP_OFFSET
4383 fprintf_unfiltered (file
,
4384 "mips_dump_tdep: MACHINE_CPROC_FP_OFFSET = %d\n",
4385 MACHINE_CPROC_FP_OFFSET
);
4387 #ifdef MACHINE_CPROC_PC_OFFSET
4388 fprintf_unfiltered (file
,
4389 "mips_dump_tdep: MACHINE_CPROC_PC_OFFSET = %d\n",
4390 MACHINE_CPROC_PC_OFFSET
);
4392 #ifdef MACHINE_CPROC_SP_OFFSET
4393 fprintf_unfiltered (file
,
4394 "mips_dump_tdep: MACHINE_CPROC_SP_OFFSET = %d\n",
4395 MACHINE_CPROC_SP_OFFSET
);
4397 fprintf_unfiltered (file
,
4398 "mips_dump_tdep: MAKE_MIPS16_ADDR = FIXME!\n");
4399 fprintf_unfiltered (file
,
4400 "mips_dump_tdep: MIPS16_BIG_BREAKPOINT = delete?\n");
4401 fprintf_unfiltered (file
,
4402 "mips_dump_tdep: MIPS16_INSTLEN = %d\n",
4404 fprintf_unfiltered (file
,
4405 "mips_dump_tdep: MIPS16_LITTLE_BREAKPOINT = delete?\n");
4406 fprintf_unfiltered (file
,
4407 "mips_dump_tdep: MIPS_DEFAULT_ABI = FIXME!\n");
4408 fprintf_unfiltered (file
,
4409 "mips_dump_tdep: MIPS_EFI_SYMBOL_NAME = multi-arch!!\n");
4410 fprintf_unfiltered (file
,
4411 "mips_dump_tdep: MIPS_INSTLEN = %d\n",
4413 fprintf_unfiltered (file
,
4414 "mips_dump_tdep: MIPS_LAST_ARG_REGNUM = %d (%d regs)\n",
4415 MIPS_LAST_ARG_REGNUM
,
4416 MIPS_LAST_ARG_REGNUM
- A0_REGNUM
+ 1);
4417 fprintf_unfiltered (file
,
4418 "mips_dump_tdep: MIPS_NUMREGS = %d\n",
4420 fprintf_unfiltered (file
,
4421 "mips_dump_tdep: MIPS_REGISTER_NAMES = delete?\n");
4422 fprintf_unfiltered (file
,
4423 "mips_dump_tdep: MIPS_SAVED_REGSIZE = %d\n",
4424 MIPS_SAVED_REGSIZE
);
4425 fprintf_unfiltered (file
,
4426 "mips_dump_tdep: MSYMBOL_IS_SPECIAL = function?\n");
4427 fprintf_unfiltered (file
,
4428 "mips_dump_tdep: MSYMBOL_SIZE # %s\n",
4429 XSTRING (MSYMBOL_SIZE (MSYM
)));
4430 fprintf_unfiltered (file
,
4431 "mips_dump_tdep: OP_LDFPR = used?\n");
4432 fprintf_unfiltered (file
,
4433 "mips_dump_tdep: OP_LDGPR = used?\n");
4434 fprintf_unfiltered (file
,
4435 "mips_dump_tdep: PMON_BIG_BREAKPOINT = delete?\n");
4436 fprintf_unfiltered (file
,
4437 "mips_dump_tdep: PMON_LITTLE_BREAKPOINT = delete?\n");
4438 fprintf_unfiltered (file
,
4439 "mips_dump_tdep: PRID_REGNUM = %d\n",
4441 fprintf_unfiltered (file
,
4442 "mips_dump_tdep: PRINT_EXTRA_FRAME_INFO # %s\n",
4443 XSTRING (PRINT_EXTRA_FRAME_INFO (FRAME
)));
4444 fprintf_unfiltered (file
,
4445 "mips_dump_tdep: PROC_DESC_IS_DUMMY = function?\n");
4446 fprintf_unfiltered (file
,
4447 "mips_dump_tdep: PROC_FRAME_ADJUST = function?\n");
4448 fprintf_unfiltered (file
,
4449 "mips_dump_tdep: PROC_FRAME_OFFSET = function?\n");
4450 fprintf_unfiltered (file
,
4451 "mips_dump_tdep: PROC_FRAME_REG = function?\n");
4452 fprintf_unfiltered (file
,
4453 "mips_dump_tdep: PROC_FREG_MASK = function?\n");
4454 fprintf_unfiltered (file
,
4455 "mips_dump_tdep: PROC_FREG_OFFSET = function?\n");
4456 fprintf_unfiltered (file
,
4457 "mips_dump_tdep: PROC_HIGH_ADDR = function?\n");
4458 fprintf_unfiltered (file
,
4459 "mips_dump_tdep: PROC_LOW_ADDR = function?\n");
4460 fprintf_unfiltered (file
,
4461 "mips_dump_tdep: PROC_PC_REG = function?\n");
4462 fprintf_unfiltered (file
,
4463 "mips_dump_tdep: PROC_REG_MASK = function?\n");
4464 fprintf_unfiltered (file
,
4465 "mips_dump_tdep: PROC_REG_OFFSET = function?\n");
4466 fprintf_unfiltered (file
,
4467 "mips_dump_tdep: PROC_SYMBOL = function?\n");
4468 fprintf_unfiltered (file
,
4469 "mips_dump_tdep: PS_REGNUM = %d\n",
4471 fprintf_unfiltered (file
,
4472 "mips_dump_tdep: PUSH_FP_REGNUM = %d\n",
4474 fprintf_unfiltered (file
,
4475 "mips_dump_tdep: RA_REGNUM = %d\n",
4477 fprintf_unfiltered (file
,
4478 "mips_dump_tdep: REGISTER_CONVERT_FROM_TYPE # %s\n",
4479 XSTRING (REGISTER_CONVERT_FROM_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4480 fprintf_unfiltered (file
,
4481 "mips_dump_tdep: REGISTER_CONVERT_TO_TYPE # %s\n",
4482 XSTRING (REGISTER_CONVERT_TO_TYPE (REGNUM
, VALTYPE
, RAW_BUFFER
)));
4483 fprintf_unfiltered (file
,
4484 "mips_dump_tdep: REGISTER_NAMES = delete?\n");
4485 fprintf_unfiltered (file
,
4486 "mips_dump_tdep: ROUND_DOWN = function?\n");
4487 fprintf_unfiltered (file
,
4488 "mips_dump_tdep: ROUND_UP = function?\n");
4490 fprintf_unfiltered (file
,
4491 "mips_dump_tdep: SAVED_BYTES = %d\n",
4495 fprintf_unfiltered (file
,
4496 "mips_dump_tdep: SAVED_FP = %d\n",
4500 fprintf_unfiltered (file
,
4501 "mips_dump_tdep: SAVED_PC = %d\n",
4504 fprintf_unfiltered (file
,
4505 "mips_dump_tdep: SETUP_ARBITRARY_FRAME # %s\n",
4506 XSTRING (SETUP_ARBITRARY_FRAME (NUMARGS
, ARGS
)));
4507 fprintf_unfiltered (file
,
4508 "mips_dump_tdep: SET_PROC_DESC_IS_DUMMY = function?\n");
4509 fprintf_unfiltered (file
,
4510 "mips_dump_tdep: SIGFRAME_BASE = %d\n",
4512 fprintf_unfiltered (file
,
4513 "mips_dump_tdep: SIGFRAME_FPREGSAVE_OFF = %d\n",
4514 SIGFRAME_FPREGSAVE_OFF
);
4515 fprintf_unfiltered (file
,
4516 "mips_dump_tdep: SIGFRAME_PC_OFF = %d\n",
4518 fprintf_unfiltered (file
,
4519 "mips_dump_tdep: SIGFRAME_REGSAVE_OFF = %d\n",
4520 SIGFRAME_REGSAVE_OFF
);
4521 fprintf_unfiltered (file
,
4522 "mips_dump_tdep: SIGFRAME_REG_SIZE = %d\n",
4524 fprintf_unfiltered (file
,
4525 "mips_dump_tdep: SKIP_TRAMPOLINE_CODE # %s\n",
4526 XSTRING (SKIP_TRAMPOLINE_CODE (PC
)));
4527 fprintf_unfiltered (file
,
4528 "mips_dump_tdep: SOFTWARE_SINGLE_STEP # %s\n",
4529 XSTRING (SOFTWARE_SINGLE_STEP (SIG
, BP_P
)));
4530 fprintf_unfiltered (file
,
4531 "mips_dump_tdep: SOFTWARE_SINGLE_STEP_P () = %d\n",
4532 SOFTWARE_SINGLE_STEP_P ());
4533 fprintf_unfiltered (file
,
4534 "mips_dump_tdep: STAB_REG_TO_REGNUM # %s\n",
4535 XSTRING (STAB_REG_TO_REGNUM (REGNUM
)));
4536 #ifdef STACK_END_ADDR
4537 fprintf_unfiltered (file
,
4538 "mips_dump_tdep: STACK_END_ADDR = %d\n",
4541 fprintf_unfiltered (file
,
4542 "mips_dump_tdep: STEP_SKIPS_DELAY # %s\n",
4543 XSTRING (STEP_SKIPS_DELAY (PC
)));
4544 fprintf_unfiltered (file
,
4545 "mips_dump_tdep: STEP_SKIPS_DELAY_P = %d\n",
4546 STEP_SKIPS_DELAY_P
);
4547 fprintf_unfiltered (file
,
4548 "mips_dump_tdep: STOPPED_BY_WATCHPOINT # %s\n",
4549 XSTRING (STOPPED_BY_WATCHPOINT (WS
)));
4550 fprintf_unfiltered (file
,
4551 "mips_dump_tdep: T9_REGNUM = %d\n",
4553 fprintf_unfiltered (file
,
4554 "mips_dump_tdep: TABULAR_REGISTER_OUTPUT = used?\n");
4555 fprintf_unfiltered (file
,
4556 "mips_dump_tdep: TARGET_CAN_USE_HARDWARE_WATCHPOINT # %s\n",
4557 XSTRING (TARGET_CAN_USE_HARDWARE_WATCHPOINT (TYPE
,CNT
,OTHERTYPE
)));
4558 fprintf_unfiltered (file
,
4559 "mips_dump_tdep: TARGET_HAS_HARDWARE_WATCHPOINTS # %s\n",
4560 XSTRING (TARGET_HAS_HARDWARE_WATCHPOINTS
));
4561 fprintf_unfiltered (file
,
4562 "mips_dump_tdep: TARGET_MIPS = used?\n");
4563 fprintf_unfiltered (file
,
4564 "mips_dump_tdep: TM_PRINT_INSN_MACH # %s\n",
4565 XSTRING (TM_PRINT_INSN_MACH
));
4567 fprintf_unfiltered (file
,
4568 "mips_dump_tdep: TRACE_CLEAR # %s\n",
4569 XSTRING (TRACE_CLEAR (THREAD
, STATE
)));
4572 fprintf_unfiltered (file
,
4573 "mips_dump_tdep: TRACE_FLAVOR = %d\n",
4576 #ifdef TRACE_FLAVOR_SIZE
4577 fprintf_unfiltered (file
,
4578 "mips_dump_tdep: TRACE_FLAVOR_SIZE = %d\n",
4582 fprintf_unfiltered (file
,
4583 "mips_dump_tdep: TRACE_SET # %s\n",
4584 XSTRING (TRACE_SET (X
,STATE
)));
4586 fprintf_unfiltered (file
,
4587 "mips_dump_tdep: UNMAKE_MIPS16_ADDR = function?\n");
4588 #ifdef UNUSED_REGNUM
4589 fprintf_unfiltered (file
,
4590 "mips_dump_tdep: UNUSED_REGNUM = %d\n",
4593 fprintf_unfiltered (file
,
4594 "mips_dump_tdep: V0_REGNUM = %d\n",
4596 fprintf_unfiltered (file
,
4597 "mips_dump_tdep: VM_MIN_ADDRESS = %ld\n",
4598 (long) VM_MIN_ADDRESS
);
4600 fprintf_unfiltered (file
,
4601 "mips_dump_tdep: VX_NUM_REGS = %d (used?)\n",
4604 fprintf_unfiltered (file
,
4605 "mips_dump_tdep: ZERO_REGNUM = %d\n",
4607 fprintf_unfiltered (file
,
4608 "mips_dump_tdep: _PROC_MAGIC_ = %d\n",
4613 _initialize_mips_tdep (void)
4615 static struct cmd_list_element
*mipsfpulist
= NULL
;
4616 struct cmd_list_element
*c
;
4618 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
4619 if (!tm_print_insn
) /* Someone may have already set it */
4620 tm_print_insn
= gdb_print_insn_mips
;
4622 /* Add root prefix command for all "set mips"/"show mips" commands */
4623 add_prefix_cmd ("mips", no_class
, set_mips_command
,
4624 "Various MIPS specific commands.",
4625 &setmipscmdlist
, "set mips ", 0, &setlist
);
4627 add_prefix_cmd ("mips", no_class
, show_mips_command
,
4628 "Various MIPS specific commands.",
4629 &showmipscmdlist
, "show mips ", 0, &showlist
);
4631 /* Allow the user to override the saved register size. */
4632 add_show_from_set (add_set_enum_cmd ("saved-gpreg-size",
4635 &mips_saved_regsize_string
, "\
4636 Set size of general purpose registers saved on the stack.\n\
4637 This option can be set to one of:\n\
4638 32 - Force GDB to treat saved GP registers as 32-bit\n\
4639 64 - Force GDB to treat saved GP registers as 64-bit\n\
4640 auto - Allow GDB to use the target's default setting or autodetect the\n\
4641 saved GP register size from information contained in the executable.\n\
4646 /* Allow the user to override the argument stack size. */
4647 add_show_from_set (add_set_enum_cmd ("stack-arg-size",
4650 &mips_stack_argsize_string
, "\
4651 Set the amount of stack space reserved for each argument.\n\
4652 This option can be set to one of:\n\
4653 32 - Force GDB to allocate 32-bit chunks per argument\n\
4654 64 - Force GDB to allocate 64-bit chunks per argument\n\
4655 auto - Allow GDB to determine the correct setting from the current\n\
4656 target and executable (default)",
4660 /* Let the user turn off floating point and set the fence post for
4661 heuristic_proc_start. */
4663 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
4664 "Set use of MIPS floating-point coprocessor.",
4665 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
4666 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
4667 "Select single-precision MIPS floating-point coprocessor.",
4669 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
4670 "Select double-precision MIPS floating-point coprocessor.",
4672 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
4673 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
4674 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
4675 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
4676 "Select no MIPS floating-point coprocessor.",
4678 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
4679 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
4680 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
4681 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
4682 "Select MIPS floating-point coprocessor automatically.",
4684 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
4685 "Show current use of MIPS floating-point coprocessor target.",
4689 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
4690 (char *) &tmp_mips_processor_type
,
4691 "Set the type of MIPS processor in use.\n\
4692 Set this to be able to access processor-type-specific registers.\n\
4695 c
->function
.cfunc
= mips_set_processor_type_command
;
4696 c
= add_show_from_set (c
, &showlist
);
4697 c
->function
.cfunc
= mips_show_processor_type_command
;
4699 tmp_mips_processor_type
= xstrdup (DEFAULT_MIPS_TYPE
);
4700 mips_set_processor_type_command (xstrdup (DEFAULT_MIPS_TYPE
), 0);
4703 /* We really would like to have both "0" and "unlimited" work, but
4704 command.c doesn't deal with that. So make it a var_zinteger
4705 because the user can always use "999999" or some such for unlimited. */
4706 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
4707 (char *) &heuristic_fence_post
,
4709 Set the distance searched for the start of a function.\n\
4710 If you are debugging a stripped executable, GDB needs to search through the\n\
4711 program for the start of a function. This command sets the distance of the\n\
4712 search. The only need to set it is when debugging a stripped executable.",
4714 /* We need to throw away the frame cache when we set this, since it
4715 might change our ability to get backtraces. */
4716 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
4717 add_show_from_set (c
, &showlist
);
4719 /* Allow the user to control whether the upper bits of 64-bit
4720 addresses should be zeroed. */
4721 c
= add_set_auto_boolean_cmd ("mask-address", no_class
, &mask_address_var
,
4722 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
4723 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to allow GDB to determine\n\
4724 the correct value.\n",
4726 add_cmd ("mask-address", no_class
, show_mask_address
,
4727 "Show current mask-address value", &showmipscmdlist
);
4729 /* Allow the user to control the size of 32 bit registers within the
4730 raw remote packet. */
4731 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
4734 (char *)&mips64_transfers_32bit_regs_p
, "\
4735 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
4736 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
4737 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
4738 64 bits for others. Use \"off\" to disable compatibility mode",
4742 /* Debug this files internals. */
4743 add_show_from_set (add_set_cmd ("mips", class_maintenance
, var_zinteger
,
4744 &mips_debug
, "Set mips debugging.\n\
4745 When non-zero, mips specific debugging is enabled.", &setdebuglist
),