1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
2 Copyright 1988-1999, Free Software Foundation, Inc.
3 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
4 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #include "gdb_string.h"
37 #include "opcode/mips.h"
39 struct frame_extra_info
41 mips_extra_func_info_t proc_desc
;
45 /* Some MIPS boards don't support floating point while others only
46 support single-precision floating-point operations. See also
47 FP_REGISTER_DOUBLE. */
51 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
52 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
53 MIPS_FPU_NONE
/* No floating point. */
56 #ifndef MIPS_DEFAULT_FPU_TYPE
57 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
59 static int mips_fpu_type_auto
= 1;
60 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
61 #define MIPS_FPU_TYPE mips_fpu_type
63 #ifndef MIPS_SAVED_REGSIZE
64 #define MIPS_SAVED_REGSIZE MIPS_REGSIZE
67 /* Do not use "TARGET_IS_MIPS64" to test the size of floating point registers */
68 #ifndef FP_REGISTER_DOUBLE
69 #define FP_REGISTER_DOUBLE (REGISTER_VIRTUAL_SIZE(FP0_REGNUM) == 8)
73 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
76 static int mips_in_lenient_prologue
PARAMS ((CORE_ADDR
, CORE_ADDR
));
79 int gdb_print_insn_mips
PARAMS ((bfd_vma
, disassemble_info
*));
81 static void mips_print_register
PARAMS ((int, int));
83 static mips_extra_func_info_t
84 heuristic_proc_desc
PARAMS ((CORE_ADDR
, CORE_ADDR
, struct frame_info
*));
86 static CORE_ADDR heuristic_proc_start
PARAMS ((CORE_ADDR
));
88 static CORE_ADDR read_next_frame_reg
PARAMS ((struct frame_info
*, int));
90 int mips_set_processor_type
PARAMS ((char *));
92 static void mips_show_processor_type_command
PARAMS ((char *, int));
94 static void reinit_frame_cache_sfunc
PARAMS ((char *, int,
95 struct cmd_list_element
*));
97 static mips_extra_func_info_t
98 find_proc_desc
PARAMS ((CORE_ADDR pc
, struct frame_info
* next_frame
));
100 static CORE_ADDR after_prologue
PARAMS ((CORE_ADDR pc
,
101 mips_extra_func_info_t proc_desc
));
103 /* This value is the model of MIPS in use. It is derived from the value
104 of the PrID register. */
106 char *mips_processor_type
;
108 char *tmp_mips_processor_type
;
110 /* A set of original names, to be used when restoring back to generic
111 registers from a specific set. */
113 char *mips_generic_reg_names
[] = MIPS_REGISTER_NAMES
;
114 char **mips_processor_reg_names
= mips_generic_reg_names
;
117 mips_register_name (i
)
120 return mips_processor_reg_names
[i
];
123 /* Names of IDT R3041 registers. */
125 char *mips_r3041_reg_names
[] = {
126 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
127 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
128 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
129 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
130 "sr", "lo", "hi", "bad", "cause","pc",
131 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
132 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
133 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
134 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
135 "fsr", "fir", "fp", "",
136 "", "", "bus", "ccfg", "", "", "", "",
137 "", "", "port", "cmp", "", "", "epc", "prid",
140 /* Names of IDT R3051 registers. */
142 char *mips_r3051_reg_names
[] = {
143 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
144 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
145 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
146 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
147 "sr", "lo", "hi", "bad", "cause","pc",
148 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
149 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
150 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
151 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
152 "fsr", "fir", "fp", "",
153 "inx", "rand", "elo", "", "ctxt", "", "", "",
154 "", "", "ehi", "", "", "", "epc", "prid",
157 /* Names of IDT R3081 registers. */
159 char *mips_r3081_reg_names
[] = {
160 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
161 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
162 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
163 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
164 "sr", "lo", "hi", "bad", "cause","pc",
165 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
166 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
167 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
168 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
169 "fsr", "fir", "fp", "",
170 "inx", "rand", "elo", "cfg", "ctxt", "", "", "",
171 "", "", "ehi", "", "", "", "epc", "prid",
174 /* Names of LSI 33k registers. */
176 char *mips_lsi33k_reg_names
[] = {
177 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
178 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
179 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
180 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
181 "epc", "hi", "lo", "sr", "cause","badvaddr",
182 "dcic", "bpc", "bda", "", "", "", "", "",
183 "", "", "", "", "", "", "", "",
184 "", "", "", "", "", "", "", "",
185 "", "", "", "", "", "", "", "",
187 "", "", "", "", "", "", "", "",
188 "", "", "", "", "", "", "", "",
194 } mips_processor_type_table
[] = {
195 { "generic", mips_generic_reg_names
},
196 { "r3041", mips_r3041_reg_names
},
197 { "r3051", mips_r3051_reg_names
},
198 { "r3071", mips_r3081_reg_names
},
199 { "r3081", mips_r3081_reg_names
},
200 { "lsi33k", mips_lsi33k_reg_names
},
208 /* Table to translate MIPS16 register field to actual register number. */
209 static int mips16_to_32_reg
[8] =
210 {16, 17, 2, 3, 4, 5, 6, 7};
212 /* Heuristic_proc_start may hunt through the text section for a long
213 time across a 2400 baud serial line. Allows the user to limit this
216 static unsigned int heuristic_fence_post
= 0;
218 #define PROC_LOW_ADDR(proc) ((proc)->pdr.adr) /* least address */
219 #define PROC_HIGH_ADDR(proc) ((proc)->high_addr) /* upper address bound */
220 #define PROC_FRAME_OFFSET(proc) ((proc)->pdr.frameoffset)
221 #define PROC_FRAME_REG(proc) ((proc)->pdr.framereg)
222 #define PROC_FRAME_ADJUST(proc) ((proc)->frame_adjust)
223 #define PROC_REG_MASK(proc) ((proc)->pdr.regmask)
224 #define PROC_FREG_MASK(proc) ((proc)->pdr.fregmask)
225 #define PROC_REG_OFFSET(proc) ((proc)->pdr.regoffset)
226 #define PROC_FREG_OFFSET(proc) ((proc)->pdr.fregoffset)
227 #define PROC_PC_REG(proc) ((proc)->pdr.pcreg)
228 #define PROC_SYMBOL(proc) (*(struct symbol**)&(proc)->pdr.isym)
229 #define _PROC_MAGIC_ 0x0F0F0F0F
230 #define PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym == _PROC_MAGIC_)
231 #define SET_PROC_DESC_IS_DUMMY(proc) ((proc)->pdr.isym = _PROC_MAGIC_)
233 struct linked_proc_info
235 struct mips_extra_func_info info
;
236 struct linked_proc_info
*next
;
238 *linked_proc_desc_table
= NULL
;
241 mips_print_extra_frame_info (fi
)
242 struct frame_info
*fi
;
246 && fi
->extra_info
->proc_desc
247 && fi
->extra_info
->proc_desc
->pdr
.framereg
< NUM_REGS
)
248 printf_filtered (" frame pointer is at %s+%s\n",
249 REGISTER_NAME (fi
->extra_info
->proc_desc
->pdr
.framereg
),
250 paddr_d (fi
->extra_info
->proc_desc
->pdr
.frameoffset
));
253 /* Convert between RAW and VIRTUAL registers. The RAW register size
254 defines the remote-gdb packet. */
256 static int mips64_transfers_32bit_regs_p
= 0;
259 mips_register_raw_size (reg_nr
)
262 if (mips64_transfers_32bit_regs_p
)
263 return REGISTER_VIRTUAL_SIZE (reg_nr
);
269 mips_register_convertible (reg_nr
)
272 if (mips64_transfers_32bit_regs_p
)
275 return (REGISTER_RAW_SIZE (reg_nr
) > REGISTER_VIRTUAL_SIZE (reg_nr
));
279 mips_register_convert_to_virtual (n
, virtual_type
, raw_buf
, virt_buf
)
281 struct type
*virtual_type
;
285 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
287 raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
288 TYPE_LENGTH (virtual_type
));
292 TYPE_LENGTH (virtual_type
));
296 mips_register_convert_to_raw (virtual_type
, n
, virt_buf
, raw_buf
)
297 struct type
*virtual_type
;
302 memset (raw_buf
, 0, REGISTER_RAW_SIZE (n
));
303 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
304 memcpy (raw_buf
+ (REGISTER_RAW_SIZE (n
) - TYPE_LENGTH (virtual_type
)),
306 TYPE_LENGTH (virtual_type
));
310 TYPE_LENGTH (virtual_type
));
313 /* Should the upper word of 64-bit addresses be zeroed? */
314 static int mask_address_p
= 1;
316 /* Should call_function allocate stack space for a struct return? */
318 mips_use_struct_convention (gcc_p
, type
)
323 return (TYPE_LENGTH (type
) > 2 * MIPS_SAVED_REGSIZE
);
325 return 1; /* Structures are returned by ref in extra arg0 */
328 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
331 pc_is_mips16 (bfd_vma memaddr
)
333 struct minimal_symbol
*sym
;
335 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
336 if (IS_MIPS16_ADDR (memaddr
))
339 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
340 the high bit of the info field. Use this to decide if the function is
341 MIPS16 or normal MIPS. */
342 sym
= lookup_minimal_symbol_by_pc (memaddr
);
344 return MSYMBOL_IS_SPECIAL (sym
);
350 /* This returns the PC of the first inst after the prologue. If we can't
351 find the prologue, then return 0. */
354 after_prologue (pc
, proc_desc
)
356 mips_extra_func_info_t proc_desc
;
358 struct symtab_and_line sal
;
359 CORE_ADDR func_addr
, func_end
;
362 proc_desc
= find_proc_desc (pc
, NULL
);
366 /* If function is frameless, then we need to do it the hard way. I
367 strongly suspect that frameless always means prologueless... */
368 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
369 && PROC_FRAME_OFFSET (proc_desc
) == 0)
373 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
374 return 0; /* Unknown */
376 sal
= find_pc_line (func_addr
, 0);
378 if (sal
.end
< func_end
)
381 /* The line after the prologue is after the end of the function. In this
382 case, tell the caller to find the prologue the hard way. */
387 /* Decode a MIPS32 instruction that saves a register in the stack, and
388 set the appropriate bit in the general register mask or float register mask
389 to indicate which register is saved. This is a helper function
390 for mips_find_saved_regs. */
393 mips32_decode_reg_save (inst
, gen_mask
, float_mask
)
395 unsigned long *gen_mask
;
396 unsigned long *float_mask
;
400 if ((inst
& 0xffe00000) == 0xafa00000 /* sw reg,n($sp) */
401 || (inst
& 0xffe00000) == 0xafc00000 /* sw reg,n($r30) */
402 || (inst
& 0xffe00000) == 0xffa00000) /* sd reg,n($sp) */
404 /* It might be possible to use the instruction to
405 find the offset, rather than the code below which
406 is based on things being in a certain order in the
407 frame, but figuring out what the instruction's offset
408 is relative to might be a little tricky. */
409 reg
= (inst
& 0x001f0000) >> 16;
410 *gen_mask
|= (1 << reg
);
412 else if ((inst
& 0xffe00000) == 0xe7a00000 /* swc1 freg,n($sp) */
413 || (inst
& 0xffe00000) == 0xe7c00000 /* swc1 freg,n($r30) */
414 || (inst
& 0xffe00000) == 0xf7a00000) /* sdc1 freg,n($sp) */
417 reg
= ((inst
& 0x001f0000) >> 16);
418 *float_mask
|= (1 << reg
);
422 /* Decode a MIPS16 instruction that saves a register in the stack, and
423 set the appropriate bit in the general register or float register mask
424 to indicate which register is saved. This is a helper function
425 for mips_find_saved_regs. */
428 mips16_decode_reg_save (inst
, gen_mask
)
430 unsigned long *gen_mask
;
432 if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
434 int reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
435 *gen_mask
|= (1 << reg
);
437 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
439 int reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
440 *gen_mask
|= (1 << reg
);
442 else if ((inst
& 0xff00) == 0x6200 /* sw $ra,n($sp) */
443 || (inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
444 *gen_mask
|= (1 << RA_REGNUM
);
448 /* Fetch and return instruction from the specified location. If the PC
449 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
452 mips_fetch_instruction (addr
)
455 char buf
[MIPS_INSTLEN
];
459 if (pc_is_mips16 (addr
))
461 instlen
= MIPS16_INSTLEN
;
462 addr
= UNMAKE_MIPS16_ADDR (addr
);
465 instlen
= MIPS_INSTLEN
;
466 status
= read_memory_nobpt (addr
, buf
, instlen
);
468 memory_error (status
, addr
);
469 return extract_unsigned_integer (buf
, instlen
);
473 /* These the fields of 32 bit mips instructions */
474 #define mips32_op(x) (x >> 25)
475 #define itype_op(x) (x >> 25)
476 #define itype_rs(x) ((x >> 21)& 0x1f)
477 #define itype_rt(x) ((x >> 16) & 0x1f)
478 #define itype_immediate(x) ( x & 0xffff)
480 #define jtype_op(x) (x >> 25)
481 #define jtype_target(x) ( x & 0x03fffff)
483 #define rtype_op(x) (x >>25)
484 #define rtype_rs(x) ((x>>21) & 0x1f)
485 #define rtype_rt(x) ((x>>16) & 0x1f)
486 #define rtype_rd(x) ((x>>11) & 0x1f)
487 #define rtype_shamt(x) ((x>>6) & 0x1f)
488 #define rtype_funct(x) (x & 0x3f )
491 mips32_relative_offset (unsigned long inst
)
494 x
= itype_immediate (inst
);
495 if (x
& 0x8000) /* sign bit set */
497 x
|= 0xffff0000; /* sign extension */
503 /* Determine whate to set a single step breakpoint while considering
506 mips32_next_pc (CORE_ADDR pc
)
510 inst
= mips_fetch_instruction (pc
);
511 if ((inst
& 0xe0000000) != 0) /* Not a special, junp or branch instruction */
513 if ((inst
>> 27) == 5) /* BEQL BNEZ BLEZL BGTZE , bits 0101xx */
515 op
= ((inst
>> 25) & 0x03);
519 goto equal_branch
; /* BEQL */
521 goto neq_branch
; /* BNEZ */
523 goto less_branch
; /* BLEZ */
525 goto greater_branch
; /* BGTZ */
531 pc
+= 4; /* Not a branch, next instruction is easy */
534 { /* This gets way messy */
536 /* Further subdivide into SPECIAL, REGIMM and other */
537 switch (op
= ((inst
>> 26) & 0x07)) /* extract bits 28,27,26 */
539 case 0: /* SPECIAL */
540 op
= rtype_funct (inst
);
545 pc
= read_register (rtype_rs (inst
)); /* Set PC to that address */
551 break; /* end special */
554 op
= jtype_op (inst
); /* branch condition */
555 switch (jtype_op (inst
))
559 case 16: /* BLTZALL */
560 case 18: /* BLTZALL */
562 if (read_register (itype_rs (inst
)) < 0)
563 pc
+= mips32_relative_offset (inst
) + 4;
565 pc
+= 8; /* after the delay slot */
569 case 17: /* BGEZAL */
570 case 19: /* BGEZALL */
571 greater_equal_branch
:
572 if (read_register (itype_rs (inst
)) >= 0)
573 pc
+= mips32_relative_offset (inst
) + 4;
575 pc
+= 8; /* after the delay slot */
577 /* All of the other intructions in the REGIMM catagory */
582 break; /* end REGIMM */
587 reg
= jtype_target (inst
) << 2;
588 pc
= reg
+ ((pc
+ 4) & 0xf0000000);
589 /* Whats this mysterious 0xf000000 adjustment ??? */
592 /* FIXME case JALX : */
595 reg
= jtype_target (inst
) << 2;
596 pc
= reg
+ ((pc
+ 4) & 0xf0000000) + 1; /* yes, +1 */
597 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
599 break; /* The new PC will be alternate mode */
600 case 4: /* BEQ , BEQL */
602 if (read_register (itype_rs (inst
)) ==
603 read_register (itype_rt (inst
)))
604 pc
+= mips32_relative_offset (inst
) + 4;
608 case 5: /* BNE , BNEL */
610 if (read_register (itype_rs (inst
)) !=
611 read_register (itype_rs (inst
)))
612 pc
+= mips32_relative_offset (inst
) + 4;
616 case 6: /* BLEZ , BLEZL */
618 if (read_register (itype_rs (inst
) <= 0))
619 pc
+= mips32_relative_offset (inst
) + 4;
624 greater_branch
: /* BGTZ BGTZL */
625 if (read_register (itype_rs (inst
) > 0))
626 pc
+= mips32_relative_offset (inst
) + 4;
635 } /* mips32_next_pc */
637 /* Decoding the next place to set a breakpoint is irregular for the
638 mips 16 variant, but fortunatly, there fewer instructions. We have to cope
639 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
640 We dont want to set a single step instruction on the extend instruction
644 /* Lots of mips16 instruction formats */
645 /* Predicting jumps requires itype,ritype,i8type
646 and their extensions extItype,extritype,extI8type
648 enum mips16_inst_fmts
650 itype
, /* 0 immediate 5,10 */
651 ritype
, /* 1 5,3,8 */
652 rrtype
, /* 2 5,3,3,5 */
653 rritype
, /* 3 5,3,3,5 */
654 rrrtype
, /* 4 5,3,3,3,2 */
655 rriatype
, /* 5 5,3,3,1,4 */
656 shifttype
, /* 6 5,3,3,3,2 */
657 i8type
, /* 7 5,3,8 */
658 i8movtype
, /* 8 5,3,3,5 */
659 i8mov32rtype
, /* 9 5,3,5,3 */
660 i64type
, /* 10 5,3,8 */
661 ri64type
, /* 11 5,3,3,5 */
662 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
663 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
664 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
665 extRRItype
, /* 15 5,5,5,5,3,3,5 */
666 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
667 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
668 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
669 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
670 extRi64type
, /* 20 5,6,5,5,3,3,5 */
671 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
673 /* I am heaping all the fields of the formats into one structure and then,
674 only the fields which are involved in instruction extension */
678 enum mips16_inst_fmts fmt
;
679 unsigned long offset
;
680 unsigned int regx
; /* Function in i8 type */
687 print_unpack (char *comment
,
688 struct upk_mips16
*u
)
690 printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
691 comment
, u
->inst
, u
->fmt
, paddr (u
->offset
), u
->regx
, u
->regy
);
694 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
695 format for the bits which make up the immediatate extension.
698 extended_offset (unsigned long extension
)
701 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
703 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
705 value
|= extension
& 0x01f; /* extract 4:0 */
709 /* Only call this function if you know that this is an extendable
710 instruction, It wont malfunction, but why make excess remote memory references?
711 If the immediate operands get sign extended or somthing, do it after
712 the extension is performed.
714 /* FIXME: Every one of these cases needs to worry about sign extension
715 when the offset is to be used in relative addressing */
718 static unsigned short
719 fetch_mips_16 (CORE_ADDR pc
)
722 pc
&= 0xfffffffe; /* clear the low order bit */
723 target_read_memory (pc
, buf
, 2);
724 return extract_unsigned_integer (buf
, 2);
728 unpack_mips16 (CORE_ADDR pc
,
729 struct upk_mips16
*upk
)
732 unsigned long extension
;
734 extpc
= (pc
- 4) & ~0x01; /* Extensions are 32 bit instructions */
735 /* Decrement to previous address and loose the 16bit mode flag */
736 /* return if the instruction was extendable, but not actually extended */
737 extended
= ((mips32_op (extension
) == 30) ? 1 : 0);
740 extension
= mips_fetch_instruction (extpc
);
749 value
= extended_offset (extension
);
750 value
= value
<< 11; /* rom for the original value */
751 value
|= upk
->inst
& 0x7ff; /* eleven bits from instruction */
755 value
= upk
->inst
& 0x7ff;
756 /* FIXME : Consider sign extension */
763 { /* A register identifier and an offset */
764 /* Most of the fields are the same as I type but the
765 immediate value is of a different length */
769 value
= extended_offset (extension
);
770 value
= value
<< 8; /* from the original instruction */
771 value
|= upk
->inst
& 0xff; /* eleven bits from instruction */
772 upk
->regx
= (extension
>> 8) & 0x07; /* or i8 funct */
773 if (value
& 0x4000) /* test the sign bit , bit 26 */
775 value
&= ~0x3fff; /* remove the sign bit */
781 value
= upk
->inst
& 0xff; /* 8 bits */
782 upk
->regx
= (upk
->inst
>> 8) & 0x07; /* or i8 funct */
783 /* FIXME: Do sign extension , this format needs it */
784 if (value
& 0x80) /* THIS CONFUSES ME */
786 value
&= 0xef; /* remove the sign bit */
797 unsigned short nexthalf
;
798 value
= ((upk
->inst
& 0x1f) << 5) | ((upk
->inst
>> 5) & 0x1f);
800 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
806 printf_filtered ("Decoding unimplemented instruction format type\n");
809 /* print_unpack("UPK",upk) ; */
813 #define mips16_op(x) (x >> 11)
815 /* This is a map of the opcodes which ae known to perform branches */
816 static unsigned char map16
[32] =
817 {0, 0, 1, 1, 1, 1, 0, 0,
818 0, 0, 0, 0, 1, 0, 0, 0,
819 0, 0, 0, 0, 0, 0, 0, 0,
820 0, 0, 0, 0, 0, 1, 1, 0
824 add_offset_16 (CORE_ADDR pc
, int offset
)
826 return ((offset
<< 2) | ((pc
+ 2) & (0xf0000000)));
832 static struct upk_mips16 upk
;
835 mips16_next_pc (CORE_ADDR pc
)
839 /* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
840 inst
= fetch_mips_16 (pc
);
842 op
= mips16_op (upk
.inst
);
850 unpack_mips16 (pc
, &upk
);
859 pc
+= (offset
<< 1) + 2;
862 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
864 unpack_mips16 (pc
, &upk
);
865 pc
= add_offset_16 (pc
, upk
.offset
);
866 if ((upk
.inst
>> 10) & 0x01) /* Exchange mode */
867 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
873 unpack_mips16 (pc
, &upk
);
874 reg
= read_register (upk
.regx
);
876 pc
+= (upk
.offset
<< 1) + 2;
882 unpack_mips16 (pc
, &upk
);
883 reg
= read_register (upk
.regx
);
885 pc
+= (upk
.offset
<< 1) + 2;
889 case 12: /* I8 Formats btez btnez */
891 unpack_mips16 (pc
, &upk
);
892 /* upk.regx contains the opcode */
893 reg
= read_register (24); /* Test register is 24 */
894 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
895 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
896 /* pc = add_offset_16(pc,upk.offset) ; */
897 pc
+= (upk
.offset
<< 1) + 2;
901 case 29: /* RR Formats JR, JALR, JALR-RA */
903 op
= upk
.inst
& 0x1f;
906 upk
.regx
= (upk
.inst
>> 8) & 0x07;
907 upk
.regy
= (upk
.inst
>> 5) & 0x07;
915 break; /* Function return instruction */
921 break; /* BOGUS Guess */
923 pc
= read_register (reg
);
928 case 30: /* This is an extend instruction */
929 pc
+= 4; /* Dont be setting breakpints on the second half */
932 printf ("Filtered - next PC probably incorrrect due to jump inst\n");
938 pc
+= 2; /* just a good old instruction */
939 /* See if we CAN actually break on the next instruction */
940 /* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
942 } /* mips16_next_pc */
944 /* The mips_next_pc function supports single_tep when the remote target monitor or
945 stub is not developed enough to so a single_step.
946 It works by decoding the current instruction and predicting where a branch
947 will go. This isnt hard because all the data is available.
948 The MIPS32 and MIPS16 variants are quite different
951 mips_next_pc (CORE_ADDR pc
)
954 /* inst = mips_fetch_instruction(pc) ; */
955 /* if (pc_is_mips16) <----- This is failing */
957 return mips16_next_pc (pc
);
959 return mips32_next_pc (pc
);
962 /* Guaranteed to set fci->saved_regs to some values (it never leaves it
966 mips_find_saved_regs (fci
)
967 struct frame_info
*fci
;
970 CORE_ADDR reg_position
;
971 /* r0 bit means kernel trap */
973 /* What registers have been saved? Bitmasks. */
974 unsigned long gen_mask
, float_mask
;
975 mips_extra_func_info_t proc_desc
;
978 frame_saved_regs_zalloc (fci
);
980 /* If it is the frame for sigtramp, the saved registers are located
981 in a sigcontext structure somewhere on the stack.
982 If the stack layout for sigtramp changes we might have to change these
983 constants and the companion fixup_sigtramp in mdebugread.c */
984 #ifndef SIGFRAME_BASE
985 /* To satisfy alignment restrictions, sigcontext is located 4 bytes
986 above the sigtramp frame. */
987 #define SIGFRAME_BASE MIPS_REGSIZE
988 /* FIXME! Are these correct?? */
989 #define SIGFRAME_PC_OFF (SIGFRAME_BASE + 2 * MIPS_REGSIZE)
990 #define SIGFRAME_REGSAVE_OFF (SIGFRAME_BASE + 3 * MIPS_REGSIZE)
991 #define SIGFRAME_FPREGSAVE_OFF \
992 (SIGFRAME_REGSAVE_OFF + MIPS_NUMREGS * MIPS_REGSIZE + 3 * MIPS_REGSIZE)
994 #ifndef SIGFRAME_REG_SIZE
995 /* FIXME! Is this correct?? */
996 #define SIGFRAME_REG_SIZE MIPS_REGSIZE
998 if (fci
->signal_handler_caller
)
1000 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1002 reg_position
= fci
->frame
+ SIGFRAME_REGSAVE_OFF
1003 + ireg
* SIGFRAME_REG_SIZE
;
1004 fci
->saved_regs
[ireg
] = reg_position
;
1006 for (ireg
= 0; ireg
< MIPS_NUMREGS
; ireg
++)
1008 reg_position
= fci
->frame
+ SIGFRAME_FPREGSAVE_OFF
1009 + ireg
* SIGFRAME_REG_SIZE
;
1010 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1012 fci
->saved_regs
[PC_REGNUM
] = fci
->frame
+ SIGFRAME_PC_OFF
;
1016 proc_desc
= fci
->extra_info
->proc_desc
;
1017 if (proc_desc
== NULL
)
1018 /* I'm not sure how/whether this can happen. Normally when we can't
1019 find a proc_desc, we "synthesize" one using heuristic_proc_desc
1020 and set the saved_regs right away. */
1023 kernel_trap
= PROC_REG_MASK (proc_desc
) & 1;
1024 gen_mask
= kernel_trap
? 0xFFFFFFFF : PROC_REG_MASK (proc_desc
);
1025 float_mask
= kernel_trap
? 0xFFFFFFFF : PROC_FREG_MASK (proc_desc
);
1027 if ( /* In any frame other than the innermost or a frame interrupted by
1028 a signal, we assume that all registers have been saved.
1029 This assumes that all register saves in a function happen before
1030 the first function call. */
1031 (fci
->next
== NULL
|| fci
->next
->signal_handler_caller
)
1033 /* In a dummy frame we know exactly where things are saved. */
1034 && !PROC_DESC_IS_DUMMY (proc_desc
)
1036 /* Don't bother unless we are inside a function prologue. Outside the
1037 prologue, we know where everything is. */
1039 && in_prologue (fci
->pc
, PROC_LOW_ADDR (proc_desc
))
1041 /* Not sure exactly what kernel_trap means, but if it means
1042 the kernel saves the registers without a prologue doing it,
1043 we better not examine the prologue to see whether registers
1044 have been saved yet. */
1047 /* We need to figure out whether the registers that the proc_desc
1048 claims are saved have been saved yet. */
1052 /* Bitmasks; set if we have found a save for the register. */
1053 unsigned long gen_save_found
= 0;
1054 unsigned long float_save_found
= 0;
1057 /* If the address is odd, assume this is MIPS16 code. */
1058 addr
= PROC_LOW_ADDR (proc_desc
);
1059 instlen
= pc_is_mips16 (addr
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1061 /* Scan through this function's instructions preceding the current
1062 PC, and look for those that save registers. */
1063 while (addr
< fci
->pc
)
1065 inst
= mips_fetch_instruction (addr
);
1066 if (pc_is_mips16 (addr
))
1067 mips16_decode_reg_save (inst
, &gen_save_found
);
1069 mips32_decode_reg_save (inst
, &gen_save_found
, &float_save_found
);
1072 gen_mask
= gen_save_found
;
1073 float_mask
= float_save_found
;
1076 /* Fill in the offsets for the registers which gen_mask says
1078 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1079 for (ireg
= MIPS_NUMREGS
- 1; gen_mask
; --ireg
, gen_mask
<<= 1)
1080 if (gen_mask
& 0x80000000)
1082 fci
->saved_regs
[ireg
] = reg_position
;
1083 reg_position
-= MIPS_SAVED_REGSIZE
;
1086 /* The MIPS16 entry instruction saves $s0 and $s1 in the reverse order
1087 of that normally used by gcc. Therefore, we have to fetch the first
1088 instruction of the function, and if it's an entry instruction that
1089 saves $s0 or $s1, correct their saved addresses. */
1090 if (pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)))
1092 inst
= mips_fetch_instruction (PROC_LOW_ADDR (proc_desc
));
1093 if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1096 int sreg_count
= (inst
>> 6) & 3;
1098 /* Check if the ra register was pushed on the stack. */
1099 reg_position
= fci
->frame
+ PROC_REG_OFFSET (proc_desc
);
1101 reg_position
-= MIPS_SAVED_REGSIZE
;
1103 /* Check if the s0 and s1 registers were pushed on the stack. */
1104 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1106 fci
->saved_regs
[reg
] = reg_position
;
1107 reg_position
-= MIPS_SAVED_REGSIZE
;
1112 /* Fill in the offsets for the registers which float_mask says
1114 reg_position
= fci
->frame
+ PROC_FREG_OFFSET (proc_desc
);
1116 /* The freg_offset points to where the first *double* register
1117 is saved. So skip to the high-order word. */
1118 if (!GDB_TARGET_IS_MIPS64
)
1119 reg_position
+= MIPS_SAVED_REGSIZE
;
1121 /* Fill in the offsets for the float registers which float_mask says
1123 for (ireg
= MIPS_NUMREGS
- 1; float_mask
; --ireg
, float_mask
<<= 1)
1124 if (float_mask
& 0x80000000)
1126 fci
->saved_regs
[FP0_REGNUM
+ ireg
] = reg_position
;
1127 reg_position
-= MIPS_SAVED_REGSIZE
;
1130 fci
->saved_regs
[PC_REGNUM
] = fci
->saved_regs
[RA_REGNUM
];
1134 read_next_frame_reg (fi
, regno
)
1135 struct frame_info
*fi
;
1138 for (; fi
; fi
= fi
->next
)
1140 /* We have to get the saved sp from the sigcontext
1141 if it is a signal handler frame. */
1142 if (regno
== SP_REGNUM
&& !fi
->signal_handler_caller
)
1146 if (fi
->saved_regs
== NULL
)
1147 mips_find_saved_regs (fi
);
1148 if (fi
->saved_regs
[regno
])
1149 return read_memory_integer (fi
->saved_regs
[regno
], MIPS_SAVED_REGSIZE
);
1152 return read_register (regno
);
1155 /* mips_addr_bits_remove - remove useless address bits */
1158 mips_addr_bits_remove (addr
)
1161 #if GDB_TARGET_IS_MIPS64
1162 if (mask_address_p
&& (addr
>> 32 == (CORE_ADDR
) 0xffffffff))
1164 /* This hack is a work-around for existing boards using PMON,
1165 the simulator, and any other 64-bit targets that doesn't have
1166 true 64-bit addressing. On these targets, the upper 32 bits
1167 of addresses are ignored by the hardware. Thus, the PC or SP
1168 are likely to have been sign extended to all 1s by instruction
1169 sequences that load 32-bit addresses. For example, a typical
1170 piece of code that loads an address is this:
1171 lui $r2, <upper 16 bits>
1172 ori $r2, <lower 16 bits>
1173 But the lui sign-extends the value such that the upper 32 bits
1174 may be all 1s. The workaround is simply to mask off these bits.
1175 In the future, gcc may be changed to support true 64-bit
1176 addressing, and this masking will have to be disabled. */
1177 addr
&= (CORE_ADDR
) 0xffffffff;
1180 /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
1181 BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
1182 So we still have to mask off useless bits from addresses. */
1183 addr
&= (CORE_ADDR
) 0xffffffff;
1190 mips_init_frame_pc_first (fromleaf
, prev
)
1192 struct frame_info
*prev
;
1196 pc
= ((fromleaf
) ? SAVED_PC_AFTER_CALL (prev
->next
) :
1197 prev
->next
? FRAME_SAVED_PC (prev
->next
) : read_pc ());
1198 tmp
= mips_skip_stub (pc
);
1199 prev
->pc
= tmp
? tmp
: pc
;
1204 mips_frame_saved_pc (frame
)
1205 struct frame_info
*frame
;
1208 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
1209 /* We have to get the saved pc from the sigcontext
1210 if it is a signal handler frame. */
1211 int pcreg
= frame
->signal_handler_caller
? PC_REGNUM
1212 : (proc_desc
? PROC_PC_REG (proc_desc
) : RA_REGNUM
);
1214 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
1215 saved_pc
= read_memory_integer (frame
->frame
- MIPS_SAVED_REGSIZE
, MIPS_SAVED_REGSIZE
);
1217 saved_pc
= read_next_frame_reg (frame
, pcreg
);
1219 return ADDR_BITS_REMOVE (saved_pc
);
1222 static struct mips_extra_func_info temp_proc_desc
;
1223 static CORE_ADDR temp_saved_regs
[NUM_REGS
];
1225 /* Set a register's saved stack address in temp_saved_regs. If an address
1226 has already been set for this register, do nothing; this way we will
1227 only recognize the first save of a given register in a function prologue.
1228 This is a helper function for mips{16,32}_heuristic_proc_desc. */
1231 set_reg_offset (regno
, offset
)
1235 if (temp_saved_regs
[regno
] == 0)
1236 temp_saved_regs
[regno
] = offset
;
1240 /* Test whether the PC points to the return instruction at the
1241 end of a function. */
1244 mips_about_to_return (pc
)
1247 if (pc_is_mips16 (pc
))
1248 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
1249 generates a "jr $ra"; other times it generates code to load
1250 the return address from the stack to an accessible register (such
1251 as $a3), then a "jr" using that register. This second case
1252 is almost impossible to distinguish from an indirect jump
1253 used for switch statements, so we don't even try. */
1254 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
1256 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
1260 /* This fencepost looks highly suspicious to me. Removing it also
1261 seems suspicious as it could affect remote debugging across serial
1265 heuristic_proc_start (pc
)
1273 pc
= ADDR_BITS_REMOVE (pc
);
1275 fence
= start_pc
- heuristic_fence_post
;
1279 if (heuristic_fence_post
== UINT_MAX
1280 || fence
< VM_MIN_ADDRESS
)
1281 fence
= VM_MIN_ADDRESS
;
1283 instlen
= pc_is_mips16 (pc
) ? MIPS16_INSTLEN
: MIPS_INSTLEN
;
1285 /* search back for previous return */
1286 for (start_pc
-= instlen
;; start_pc
-= instlen
)
1287 if (start_pc
< fence
)
1289 /* It's not clear to me why we reach this point when
1290 stop_soon_quietly, but with this test, at least we
1291 don't print out warnings for every child forked (eg, on
1292 decstation). 22apr93 rich@cygnus.com. */
1293 if (!stop_soon_quietly
)
1295 static int blurb_printed
= 0;
1297 warning ("Warning: GDB can't find the start of the function at 0x%s.",
1302 /* This actually happens frequently in embedded
1303 development, when you first connect to a board
1304 and your stack pointer and pc are nowhere in
1305 particular. This message needs to give people
1306 in that situation enough information to
1307 determine that it's no big deal. */
1308 printf_filtered ("\n\
1309 GDB is unable to find the start of the function at 0x%s\n\
1310 and thus can't determine the size of that function's stack frame.\n\
1311 This means that GDB may be unable to access that stack frame, or\n\
1312 the frames below it.\n\
1313 This problem is most likely caused by an invalid program counter or\n\
1315 However, if you think GDB should simply search farther back\n\
1316 from 0x%s for code which looks like the beginning of a\n\
1317 function, you can increase the range of the search using the `set\n\
1318 heuristic-fence-post' command.\n",
1319 paddr_nz (pc
), paddr_nz (pc
));
1326 else if (pc_is_mips16 (start_pc
))
1328 unsigned short inst
;
1330 /* On MIPS16, any one of the following is likely to be the
1331 start of a function:
1335 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
1336 inst
= mips_fetch_instruction (start_pc
);
1337 if (((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1338 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
1339 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
1340 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
1342 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1343 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1348 else if (mips_about_to_return (start_pc
))
1350 start_pc
+= 2 * MIPS_INSTLEN
; /* skip return, and its delay slot */
1355 /* skip nops (usually 1) 0 - is this */
1356 while (start_pc
< pc
&& read_memory_integer (start_pc
, MIPS_INSTLEN
) == 0)
1357 start_pc
+= MIPS_INSTLEN
;
1362 /* Fetch the immediate value from a MIPS16 instruction.
1363 If the previous instruction was an EXTEND, use it to extend
1364 the upper bits of the immediate value. This is a helper function
1365 for mips16_heuristic_proc_desc. */
1368 mips16_get_imm (prev_inst
, inst
, nbits
, scale
, is_signed
)
1369 unsigned short prev_inst
; /* previous instruction */
1370 unsigned short inst
; /* current instruction */
1371 int nbits
; /* number of bits in imm field */
1372 int scale
; /* scale factor to be applied to imm */
1373 int is_signed
; /* is the imm field signed? */
1377 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1379 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1380 if (offset
& 0x8000) /* check for negative extend */
1381 offset
= 0 - (0x10000 - (offset
& 0xffff));
1382 return offset
| (inst
& 0x1f);
1386 int max_imm
= 1 << nbits
;
1387 int mask
= max_imm
- 1;
1388 int sign_bit
= max_imm
>> 1;
1390 offset
= inst
& mask
;
1391 if (is_signed
&& (offset
& sign_bit
))
1392 offset
= 0 - (max_imm
- offset
);
1393 return offset
* scale
;
1398 /* Fill in values in temp_proc_desc based on the MIPS16 instruction
1399 stream from start_pc to limit_pc. */
1402 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1403 CORE_ADDR start_pc
, limit_pc
;
1404 struct frame_info
*next_frame
;
1408 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1409 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1410 unsigned inst
= 0; /* current instruction */
1411 unsigned entry_inst
= 0; /* the entry instruction */
1414 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0; /* size of stack frame */
1415 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1417 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS16_INSTLEN
)
1419 /* Save the previous instruction. If it's an EXTEND, we'll extract
1420 the immediate offset extension from it in mips16_get_imm. */
1423 /* Fetch and decode the instruction. */
1424 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1425 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1426 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1428 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1429 if (offset
< 0) /* negative stack adjustment? */
1430 PROC_FRAME_OFFSET (&temp_proc_desc
) -= offset
;
1432 /* Exit loop if a positive stack adjustment is found, which
1433 usually means that the stack cleanup code in the function
1434 epilogue is reached. */
1437 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1439 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1440 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1441 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1442 set_reg_offset (reg
, sp
+ offset
);
1444 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1446 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1447 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1448 PROC_REG_MASK (&temp_proc_desc
) |= (1 << reg
);
1449 set_reg_offset (reg
, sp
+ offset
);
1451 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1453 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1454 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1455 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1457 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1459 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1460 PROC_REG_MASK (&temp_proc_desc
) |= (1 << RA_REGNUM
);
1461 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1463 else if (inst
== 0x673d) /* move $s1, $sp */
1466 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1468 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1470 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1471 frame_addr
= sp
+ offset
;
1472 PROC_FRAME_REG (&temp_proc_desc
) = 17;
1473 PROC_FRAME_ADJUST (&temp_proc_desc
) = offset
;
1475 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1477 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1478 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1479 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1480 set_reg_offset (reg
, frame_addr
+ offset
);
1482 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1484 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1485 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1486 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1487 set_reg_offset (reg
, frame_addr
+ offset
);
1489 else if ((inst
& 0xf81f) == 0xe809 && (inst
& 0x700) != 0x700) /* entry */
1490 entry_inst
= inst
; /* save for later processing */
1491 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1492 cur_pc
+= MIPS16_INSTLEN
; /* 32-bit instruction */
1495 /* The entry instruction is typically the first instruction in a function,
1496 and it stores registers at offsets relative to the value of the old SP
1497 (before the prologue). But the value of the sp parameter to this
1498 function is the new SP (after the prologue has been executed). So we
1499 can't calculate those offsets until we've seen the entire prologue,
1500 and can calculate what the old SP must have been. */
1501 if (entry_inst
!= 0)
1503 int areg_count
= (entry_inst
>> 8) & 7;
1504 int sreg_count
= (entry_inst
>> 6) & 3;
1506 /* The entry instruction always subtracts 32 from the SP. */
1507 PROC_FRAME_OFFSET (&temp_proc_desc
) += 32;
1509 /* Now we can calculate what the SP must have been at the
1510 start of the function prologue. */
1511 sp
+= PROC_FRAME_OFFSET (&temp_proc_desc
);
1513 /* Check if a0-a3 were saved in the caller's argument save area. */
1514 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1516 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1517 set_reg_offset (reg
, sp
+ offset
);
1518 offset
+= MIPS_SAVED_REGSIZE
;
1521 /* Check if the ra register was pushed on the stack. */
1523 if (entry_inst
& 0x20)
1525 PROC_REG_MASK (&temp_proc_desc
) |= 1 << RA_REGNUM
;
1526 set_reg_offset (RA_REGNUM
, sp
+ offset
);
1527 offset
-= MIPS_SAVED_REGSIZE
;
1530 /* Check if the s0 and s1 registers were pushed on the stack. */
1531 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1533 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1534 set_reg_offset (reg
, sp
+ offset
);
1535 offset
-= MIPS_SAVED_REGSIZE
;
1541 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
)
1542 CORE_ADDR start_pc
, limit_pc
;
1543 struct frame_info
*next_frame
;
1547 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1549 memset (temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1550 PROC_FRAME_OFFSET (&temp_proc_desc
) = 0;
1551 PROC_FRAME_ADJUST (&temp_proc_desc
) = 0; /* offset of FP from SP */
1552 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSTLEN
)
1554 unsigned long inst
, high_word
, low_word
;
1557 /* Fetch the instruction. */
1558 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1560 /* Save some code by pre-extracting some useful fields. */
1561 high_word
= (inst
>> 16) & 0xffff;
1562 low_word
= inst
& 0xffff;
1563 reg
= high_word
& 0x1f;
1565 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1566 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1567 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1569 if (low_word
& 0x8000) /* negative stack adjustment? */
1570 PROC_FRAME_OFFSET (&temp_proc_desc
) += 0x10000 - low_word
;
1572 /* Exit loop if a positive stack adjustment is found, which
1573 usually means that the stack cleanup code in the function
1574 epilogue is reached. */
1577 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1579 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1580 set_reg_offset (reg
, sp
+ low_word
);
1582 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1584 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra,
1585 but the register size used is only 32 bits. Make the address
1586 for the saved register point to the lower 32 bits. */
1587 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1588 set_reg_offset (reg
, sp
+ low_word
+ 8 - MIPS_REGSIZE
);
1590 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1592 /* Old gcc frame, r30 is virtual frame pointer. */
1593 if ((long) low_word
!= PROC_FRAME_OFFSET (&temp_proc_desc
))
1594 frame_addr
= sp
+ low_word
;
1595 else if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1597 unsigned alloca_adjust
;
1598 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1599 frame_addr
= read_next_frame_reg (next_frame
, 30);
1600 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1601 if (alloca_adjust
> 0)
1603 /* FP > SP + frame_size. This may be because
1604 * of an alloca or somethings similar.
1605 * Fix sp to "pre-alloca" value, and try again.
1607 sp
+= alloca_adjust
;
1612 /* move $30,$sp. With different versions of gas this will be either
1613 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1614 Accept any one of these. */
1615 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1617 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1618 if (PROC_FRAME_REG (&temp_proc_desc
) == SP_REGNUM
)
1620 unsigned alloca_adjust
;
1621 PROC_FRAME_REG (&temp_proc_desc
) = 30;
1622 frame_addr
= read_next_frame_reg (next_frame
, 30);
1623 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1624 if (alloca_adjust
> 0)
1626 /* FP > SP + frame_size. This may be because
1627 * of an alloca or somethings similar.
1628 * Fix sp to "pre-alloca" value, and try again.
1630 sp
+= alloca_adjust
;
1635 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1637 PROC_REG_MASK (&temp_proc_desc
) |= 1 << reg
;
1638 set_reg_offset (reg
, frame_addr
+ low_word
);
1643 static mips_extra_func_info_t
1644 heuristic_proc_desc (start_pc
, limit_pc
, next_frame
)
1645 CORE_ADDR start_pc
, limit_pc
;
1646 struct frame_info
*next_frame
;
1648 CORE_ADDR sp
= read_next_frame_reg (next_frame
, SP_REGNUM
);
1652 memset (&temp_proc_desc
, '\0', sizeof (temp_proc_desc
));
1653 memset (&temp_saved_regs
, '\0', SIZEOF_FRAME_SAVED_REGS
);
1654 PROC_LOW_ADDR (&temp_proc_desc
) = start_pc
;
1655 PROC_FRAME_REG (&temp_proc_desc
) = SP_REGNUM
;
1656 PROC_PC_REG (&temp_proc_desc
) = RA_REGNUM
;
1658 if (start_pc
+ 200 < limit_pc
)
1659 limit_pc
= start_pc
+ 200;
1660 if (pc_is_mips16 (start_pc
))
1661 mips16_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1663 mips32_heuristic_proc_desc (start_pc
, limit_pc
, next_frame
, sp
);
1664 return &temp_proc_desc
;
1667 static mips_extra_func_info_t
1668 non_heuristic_proc_desc (pc
, addrptr
)
1672 CORE_ADDR startaddr
;
1673 mips_extra_func_info_t proc_desc
;
1674 struct block
*b
= block_for_pc (pc
);
1677 find_pc_partial_function (pc
, NULL
, &startaddr
, NULL
);
1679 *addrptr
= startaddr
;
1680 if (b
== NULL
|| PC_IN_CALL_DUMMY (pc
, 0, 0))
1684 if (startaddr
> BLOCK_START (b
))
1685 /* This is the "pathological" case referred to in a comment in
1686 print_frame_info. It might be better to move this check into
1690 sym
= lookup_symbol (MIPS_EFI_SYMBOL_NAME
, b
, LABEL_NAMESPACE
, 0, NULL
);
1693 /* If we never found a PDR for this function in symbol reading, then
1694 examine prologues to find the information. */
1697 proc_desc
= (mips_extra_func_info_t
) SYMBOL_VALUE (sym
);
1698 if (PROC_FRAME_REG (proc_desc
) == -1)
1708 static mips_extra_func_info_t
1709 find_proc_desc (pc
, next_frame
)
1711 struct frame_info
*next_frame
;
1713 mips_extra_func_info_t proc_desc
;
1714 CORE_ADDR startaddr
;
1716 proc_desc
= non_heuristic_proc_desc (pc
, &startaddr
);
1720 /* IF this is the topmost frame AND
1721 * (this proc does not have debugging information OR
1722 * the PC is in the procedure prologue)
1723 * THEN create a "heuristic" proc_desc (by analyzing
1724 * the actual code) to replace the "official" proc_desc.
1726 if (next_frame
== NULL
)
1728 struct symtab_and_line val
;
1729 struct symbol
*proc_symbol
=
1730 PROC_DESC_IS_DUMMY (proc_desc
) ? 0 : PROC_SYMBOL (proc_desc
);
1734 val
= find_pc_line (BLOCK_START
1735 (SYMBOL_BLOCK_VALUE (proc_symbol
)),
1737 val
.pc
= val
.end
? val
.end
: pc
;
1739 if (!proc_symbol
|| pc
< val
.pc
)
1741 mips_extra_func_info_t found_heuristic
=
1742 heuristic_proc_desc (PROC_LOW_ADDR (proc_desc
),
1744 if (found_heuristic
)
1745 proc_desc
= found_heuristic
;
1751 /* Is linked_proc_desc_table really necessary? It only seems to be used
1752 by procedure call dummys. However, the procedures being called ought
1753 to have their own proc_descs, and even if they don't,
1754 heuristic_proc_desc knows how to create them! */
1756 register struct linked_proc_info
*link
;
1758 for (link
= linked_proc_desc_table
; link
; link
= link
->next
)
1759 if (PROC_LOW_ADDR (&link
->info
) <= pc
1760 && PROC_HIGH_ADDR (&link
->info
) > pc
)
1764 startaddr
= heuristic_proc_start (pc
);
1767 heuristic_proc_desc (startaddr
, pc
, next_frame
);
1773 get_frame_pointer (frame
, proc_desc
)
1774 struct frame_info
*frame
;
1775 mips_extra_func_info_t proc_desc
;
1777 return ADDR_BITS_REMOVE (
1778 read_next_frame_reg (frame
, PROC_FRAME_REG (proc_desc
)) +
1779 PROC_FRAME_OFFSET (proc_desc
) - PROC_FRAME_ADJUST (proc_desc
));
1782 mips_extra_func_info_t cached_proc_desc
;
1785 mips_frame_chain (frame
)
1786 struct frame_info
*frame
;
1788 mips_extra_func_info_t proc_desc
;
1790 CORE_ADDR saved_pc
= FRAME_SAVED_PC (frame
);
1792 if (saved_pc
== 0 || inside_entry_file (saved_pc
))
1795 /* Check if the PC is inside a call stub. If it is, fetch the
1796 PC of the caller of that stub. */
1797 if ((tmp
= mips_skip_stub (saved_pc
)) != 0)
1800 /* Look up the procedure descriptor for this PC. */
1801 proc_desc
= find_proc_desc (saved_pc
, frame
);
1805 cached_proc_desc
= proc_desc
;
1807 /* If no frame pointer and frame size is zero, we must be at end
1808 of stack (or otherwise hosed). If we don't check frame size,
1809 we loop forever if we see a zero size frame. */
1810 if (PROC_FRAME_REG (proc_desc
) == SP_REGNUM
1811 && PROC_FRAME_OFFSET (proc_desc
) == 0
1812 /* The previous frame from a sigtramp frame might be frameless
1813 and have frame size zero. */
1814 && !frame
->signal_handler_caller
)
1817 return get_frame_pointer (frame
, proc_desc
);
1821 mips_init_extra_frame_info (fromleaf
, fci
)
1823 struct frame_info
*fci
;
1827 /* Use proc_desc calculated in frame_chain */
1828 mips_extra_func_info_t proc_desc
=
1829 fci
->next
? cached_proc_desc
: find_proc_desc (fci
->pc
, fci
->next
);
1831 fci
->extra_info
= (struct frame_extra_info
*)
1832 frame_obstack_alloc (sizeof (struct frame_extra_info
));
1834 fci
->saved_regs
= NULL
;
1835 fci
->extra_info
->proc_desc
=
1836 proc_desc
== &temp_proc_desc
? 0 : proc_desc
;
1839 /* Fixup frame-pointer - only needed for top frame */
1840 /* This may not be quite right, if proc has a real frame register.
1841 Get the value of the frame relative sp, procedure might have been
1842 interrupted by a signal at it's very start. */
1843 if (fci
->pc
== PROC_LOW_ADDR (proc_desc
)
1844 && !PROC_DESC_IS_DUMMY (proc_desc
))
1845 fci
->frame
= read_next_frame_reg (fci
->next
, SP_REGNUM
);
1847 fci
->frame
= get_frame_pointer (fci
->next
, proc_desc
);
1849 if (proc_desc
== &temp_proc_desc
)
1853 /* Do not set the saved registers for a sigtramp frame,
1854 mips_find_saved_registers will do that for us.
1855 We can't use fci->signal_handler_caller, it is not yet set. */
1856 find_pc_partial_function (fci
->pc
, &name
,
1857 (CORE_ADDR
*) NULL
, (CORE_ADDR
*) NULL
);
1858 if (!IN_SIGTRAMP (fci
->pc
, name
))
1860 frame_saved_regs_zalloc (fci
);
1861 memcpy (fci
->saved_regs
, temp_saved_regs
, SIZEOF_FRAME_SAVED_REGS
);
1862 fci
->saved_regs
[PC_REGNUM
]
1863 = fci
->saved_regs
[RA_REGNUM
];
1867 /* hack: if argument regs are saved, guess these contain args */
1868 /* assume we can't tell how many args for now */
1869 fci
->extra_info
->num_args
= -1;
1870 for (regnum
= MIPS_LAST_ARG_REGNUM
; regnum
>= A0_REGNUM
; regnum
--)
1872 if (PROC_REG_MASK (proc_desc
) & (1 << regnum
))
1874 fci
->extra_info
->num_args
= regnum
- A0_REGNUM
+ 1;
1881 /* MIPS stack frames are almost impenetrable. When execution stops,
1882 we basically have to look at symbol information for the function
1883 that we stopped in, which tells us *which* register (if any) is
1884 the base of the frame pointer, and what offset from that register
1885 the frame itself is at.
1887 This presents a problem when trying to examine a stack in memory
1888 (that isn't executing at the moment), using the "frame" command. We
1889 don't have a PC, nor do we have any registers except SP.
1891 This routine takes two arguments, SP and PC, and tries to make the
1892 cached frames look as if these two arguments defined a frame on the
1893 cache. This allows the rest of info frame to extract the important
1894 arguments without difficulty. */
1897 setup_arbitrary_frame (argc
, argv
)
1902 error ("MIPS frame specifications require two arguments: sp and pc");
1904 return create_new_frame (argv
[0], argv
[1]);
1908 * STACK_ARGSIZE -- how many bytes does a pushed function arg take up on the stack?
1910 * For n32 ABI, eight.
1911 * For all others, he same as the size of a general register.
1913 #if defined (_MIPS_SIM_NABI32) && _MIPS_SIM == _MIPS_SIM_NABI32
1914 #define MIPS_NABI32 1
1915 #define STACK_ARGSIZE 8
1917 #define MIPS_NABI32 0
1918 #define STACK_ARGSIZE MIPS_SAVED_REGSIZE
1922 mips_push_arguments (nargs
, args
, sp
, struct_return
, struct_addr
)
1927 CORE_ADDR struct_addr
;
1933 int stack_offset
= 0;
1935 /* Macros to round N up or down to the next A boundary; A must be
1937 #define ROUND_DOWN(n,a) ((n) & ~((a)-1))
1938 #define ROUND_UP(n,a) (((n)+(a)-1) & ~((a)-1))
1940 /* First ensure that the stack and structure return address (if any)
1941 are properly aligned. The stack has to be at least 64-bit aligned
1942 even on 32-bit machines, because doubles must be 64-bit aligned.
1943 On at least one MIPS variant, stack frames need to be 128-bit
1944 aligned, so we round to this widest known alignment. */
1945 sp
= ROUND_DOWN (sp
, 16);
1946 struct_addr
= ROUND_DOWN (struct_addr
, MIPS_SAVED_REGSIZE
);
1948 /* Now make space on the stack for the args. We allocate more
1949 than necessary for EABI, because the first few arguments are
1950 passed in registers, but that's OK. */
1951 for (argnum
= 0; argnum
< nargs
; argnum
++)
1952 len
+= ROUND_UP (TYPE_LENGTH (VALUE_TYPE (args
[argnum
])), MIPS_SAVED_REGSIZE
);
1953 sp
-= ROUND_UP (len
, 16);
1955 /* Initialize the integer and float register pointers. */
1957 float_argreg
= FPA0_REGNUM
;
1959 /* the struct_return pointer occupies the first parameter-passing reg */
1961 write_register (argreg
++, struct_addr
);
1963 /* Now load as many as possible of the first arguments into
1964 registers, and push the rest onto the stack. Loop thru args
1965 from first to last. */
1966 for (argnum
= 0; argnum
< nargs
; argnum
++)
1969 char valbuf
[MAX_REGISTER_RAW_SIZE
];
1970 value_ptr arg
= args
[argnum
];
1971 struct type
*arg_type
= check_typedef (VALUE_TYPE (arg
));
1972 int len
= TYPE_LENGTH (arg_type
);
1973 enum type_code typecode
= TYPE_CODE (arg_type
);
1975 /* The EABI passes structures that do not fit in a register by
1976 reference. In all other cases, pass the structure by value. */
1977 if (MIPS_EABI
&& len
> MIPS_SAVED_REGSIZE
&&
1978 (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1980 store_address (valbuf
, MIPS_SAVED_REGSIZE
, VALUE_ADDRESS (arg
));
1981 typecode
= TYPE_CODE_PTR
;
1982 len
= MIPS_SAVED_REGSIZE
;
1986 val
= (char *) VALUE_CONTENTS (arg
);
1988 /* 32-bit ABIs always start floating point arguments in an
1989 even-numbered floating point register. */
1990 if (!FP_REGISTER_DOUBLE
&& typecode
== TYPE_CODE_FLT
1991 && (float_argreg
& 1))
1994 /* Floating point arguments passed in registers have to be
1995 treated specially. On 32-bit architectures, doubles
1996 are passed in register pairs; the even register gets
1997 the low word, and the odd register gets the high word.
1998 On non-EABI processors, the first two floating point arguments are
1999 also copied to general registers, because MIPS16 functions
2000 don't use float registers for arguments. This duplication of
2001 arguments in general registers can't hurt non-MIPS16 functions
2002 because those registers are normally skipped. */
2003 if (typecode
== TYPE_CODE_FLT
2004 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
2005 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2007 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2009 int low_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2010 unsigned long regval
;
2012 /* Write the low word of the double to the even register(s). */
2013 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2014 write_register (float_argreg
++, regval
);
2016 write_register (argreg
+ 1, regval
);
2018 /* Write the high word of the double to the odd register(s). */
2019 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2020 write_register (float_argreg
++, regval
);
2023 write_register (argreg
, regval
);
2030 /* This is a floating point value that fits entirely
2031 in a single register. */
2032 /* On 32 bit ABI's the float_argreg is further adjusted
2033 above to ensure that it is even register aligned. */
2034 CORE_ADDR regval
= extract_address (val
, len
);
2035 write_register (float_argreg
++, regval
);
2038 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
2039 registers for each argument. The below is (my
2040 guess) to ensure that the corresponding integer
2041 register has reserved the same space. */
2042 write_register (argreg
, regval
);
2043 argreg
+= FP_REGISTER_DOUBLE
? 1 : 2;
2049 /* Copy the argument to general registers or the stack in
2050 register-sized pieces. Large arguments are split between
2051 registers and stack. */
2052 /* Note: structs whose size is not a multiple of MIPS_REGSIZE
2053 are treated specially: Irix cc passes them in registers
2054 where gcc sometimes puts them on the stack. For maximum
2055 compatibility, we will put them in both places. */
2057 int odd_sized_struct
= ((len
> MIPS_SAVED_REGSIZE
) &&
2058 (len
% MIPS_SAVED_REGSIZE
!= 0));
2061 int partial_len
= len
< MIPS_SAVED_REGSIZE
? len
: MIPS_SAVED_REGSIZE
;
2063 if (argreg
> MIPS_LAST_ARG_REGNUM
|| odd_sized_struct
)
2065 /* Write this portion of the argument to the stack. */
2066 /* Should shorter than int integer values be
2067 promoted to int before being stored? */
2069 int longword_offset
= 0;
2070 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2072 if (STACK_ARGSIZE
== 8 &&
2073 (typecode
== TYPE_CODE_INT
||
2074 typecode
== TYPE_CODE_PTR
||
2075 typecode
== TYPE_CODE_FLT
) && len
<= 4)
2076 longword_offset
= STACK_ARGSIZE
- len
;
2077 else if ((typecode
== TYPE_CODE_STRUCT
||
2078 typecode
== TYPE_CODE_UNION
) &&
2079 TYPE_LENGTH (arg_type
) < STACK_ARGSIZE
)
2080 longword_offset
= STACK_ARGSIZE
- len
;
2083 write_memory (sp
+ stack_offset
+ longword_offset
,
2087 /* Note!!! This is NOT an else clause.
2088 Odd sized structs may go thru BOTH paths. */
2089 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
2091 CORE_ADDR regval
= extract_address (val
, partial_len
);
2093 /* A non-floating-point argument being passed in a
2094 general register. If a struct or union, and if
2095 the remaining length is smaller than the register
2096 size, we have to adjust the register value on
2099 It does not seem to be necessary to do the
2100 same for integral types.
2102 Also don't do this adjustment on EABI and O64
2106 && MIPS_SAVED_REGSIZE
< 8
2107 && TARGET_BYTE_ORDER
== BIG_ENDIAN
2108 && partial_len
< MIPS_SAVED_REGSIZE
2109 && (typecode
== TYPE_CODE_STRUCT
||
2110 typecode
== TYPE_CODE_UNION
))
2111 regval
<<= ((MIPS_SAVED_REGSIZE
- partial_len
) *
2114 write_register (argreg
, regval
);
2117 /* If this is the old ABI, prevent subsequent floating
2118 point arguments from being passed in floating point
2121 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
2127 /* The offset onto the stack at which we will start
2128 copying parameters (after the registers are used up)
2129 begins at (4 * MIPS_REGSIZE) in the old ABI. This
2130 leaves room for the "home" area for register parameters.
2132 In the new EABI (and the NABI32), the 8 register parameters
2133 do not have "home" stack space reserved for them, so the
2134 stack offset does not get incremented until after
2135 we have used up the 8 parameter registers. */
2137 if (!(MIPS_EABI
|| MIPS_NABI32
) ||
2139 stack_offset
+= ROUND_UP (partial_len
, STACK_ARGSIZE
);
2144 /* Return adjusted stack pointer. */
2149 mips_push_return_address (pc
, sp
)
2153 /* Set the return address register to point to the entry
2154 point of the program, where a breakpoint lies in wait. */
2155 write_register (RA_REGNUM
, CALL_DUMMY_ADDRESS ());
2160 mips_push_register (CORE_ADDR
* sp
, int regno
)
2162 char buffer
[MAX_REGISTER_RAW_SIZE
];
2165 if (MIPS_SAVED_REGSIZE
< REGISTER_RAW_SIZE (regno
))
2167 regsize
= MIPS_SAVED_REGSIZE
;
2168 offset
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
2169 ? REGISTER_RAW_SIZE (regno
) - MIPS_SAVED_REGSIZE
2174 regsize
= REGISTER_RAW_SIZE (regno
);
2178 read_register_gen (regno
, buffer
);
2179 write_memory (*sp
, buffer
+ offset
, regsize
);
2182 /* MASK(i,j) == (1<<i) + (1<<(i+1)) + ... + (1<<j)). Assume i<=j<(MIPS_NUMREGS-1). */
2183 #define MASK(i,j) (((1 << ((j)+1))-1) ^ ((1 << (i))-1))
2186 mips_push_dummy_frame ()
2189 struct linked_proc_info
*link
= (struct linked_proc_info
*)
2190 xmalloc (sizeof (struct linked_proc_info
));
2191 mips_extra_func_info_t proc_desc
= &link
->info
;
2192 CORE_ADDR sp
= ADDR_BITS_REMOVE (read_register (SP_REGNUM
));
2193 CORE_ADDR old_sp
= sp
;
2194 link
->next
= linked_proc_desc_table
;
2195 linked_proc_desc_table
= link
;
2197 /* FIXME! are these correct ? */
2198 #define PUSH_FP_REGNUM 16 /* must be a register preserved across calls */
2199 #define GEN_REG_SAVE_MASK MASK(1,16)|MASK(24,28)|(1<<(MIPS_NUMREGS-1))
2200 #define FLOAT_REG_SAVE_MASK MASK(0,19)
2201 #define FLOAT_SINGLE_REG_SAVE_MASK \
2202 ((1<<18)|(1<<16)|(1<<14)|(1<<12)|(1<<10)|(1<<8)|(1<<6)|(1<<4)|(1<<2)|(1<<0))
2204 * The registers we must save are all those not preserved across
2205 * procedure calls. Dest_Reg (see tm-mips.h) must also be saved.
2206 * In addition, we must save the PC, PUSH_FP_REGNUM, MMLO/-HI
2207 * and FP Control/Status registers.
2210 * Dummy frame layout:
2213 * Saved MMHI, MMLO, FPC_CSR
2218 * Saved D18 (i.e. F19, F18)
2220 * Saved D0 (i.e. F1, F0)
2221 * Argument build area and stack arguments written via mips_push_arguments
2225 /* Save special registers (PC, MMHI, MMLO, FPC_CSR) */
2226 PROC_FRAME_REG (proc_desc
) = PUSH_FP_REGNUM
;
2227 PROC_FRAME_OFFSET (proc_desc
) = 0;
2228 PROC_FRAME_ADJUST (proc_desc
) = 0;
2229 mips_push_register (&sp
, PC_REGNUM
);
2230 mips_push_register (&sp
, HI_REGNUM
);
2231 mips_push_register (&sp
, LO_REGNUM
);
2232 mips_push_register (&sp
, MIPS_FPU_TYPE
== MIPS_FPU_NONE
? 0 : FCRCS_REGNUM
);
2234 /* Save general CPU registers */
2235 PROC_REG_MASK (proc_desc
) = GEN_REG_SAVE_MASK
;
2236 /* PROC_REG_OFFSET is the offset of the first saved register from FP. */
2237 PROC_REG_OFFSET (proc_desc
) = sp
- old_sp
- MIPS_SAVED_REGSIZE
;
2238 for (ireg
= 32; --ireg
>= 0;)
2239 if (PROC_REG_MASK (proc_desc
) & (1 << ireg
))
2240 mips_push_register (&sp
, ireg
);
2242 /* Save floating point registers starting with high order word */
2243 PROC_FREG_MASK (proc_desc
) =
2244 MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? FLOAT_REG_SAVE_MASK
2245 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? FLOAT_SINGLE_REG_SAVE_MASK
: 0;
2246 /* PROC_FREG_OFFSET is the offset of the first saved *double* register
2248 PROC_FREG_OFFSET (proc_desc
) = sp
- old_sp
- 8;
2249 for (ireg
= 32; --ireg
>= 0;)
2250 if (PROC_FREG_MASK (proc_desc
) & (1 << ireg
))
2251 mips_push_register (&sp
, ireg
+ FP0_REGNUM
);
2253 /* Update the frame pointer for the call dummy and the stack pointer.
2254 Set the procedure's starting and ending addresses to point to the
2255 call dummy address at the entry point. */
2256 write_register (PUSH_FP_REGNUM
, old_sp
);
2257 write_register (SP_REGNUM
, sp
);
2258 PROC_LOW_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS ();
2259 PROC_HIGH_ADDR (proc_desc
) = CALL_DUMMY_ADDRESS () + 4;
2260 SET_PROC_DESC_IS_DUMMY (proc_desc
);
2261 PROC_PC_REG (proc_desc
) = RA_REGNUM
;
2267 register int regnum
;
2268 struct frame_info
*frame
= get_current_frame ();
2269 CORE_ADDR new_sp
= FRAME_FP (frame
);
2271 mips_extra_func_info_t proc_desc
= frame
->extra_info
->proc_desc
;
2273 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
2274 if (frame
->saved_regs
== NULL
)
2275 mips_find_saved_regs (frame
);
2276 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
2278 if (regnum
!= SP_REGNUM
&& regnum
!= PC_REGNUM
2279 && frame
->saved_regs
[regnum
])
2280 write_register (regnum
,
2281 read_memory_integer (frame
->saved_regs
[regnum
],
2282 MIPS_SAVED_REGSIZE
));
2284 write_register (SP_REGNUM
, new_sp
);
2285 flush_cached_frames ();
2287 if (proc_desc
&& PROC_DESC_IS_DUMMY (proc_desc
))
2289 struct linked_proc_info
*pi_ptr
, *prev_ptr
;
2291 for (pi_ptr
= linked_proc_desc_table
, prev_ptr
= NULL
;
2293 prev_ptr
= pi_ptr
, pi_ptr
= pi_ptr
->next
)
2295 if (&pi_ptr
->info
== proc_desc
)
2300 error ("Can't locate dummy extra frame info\n");
2302 if (prev_ptr
!= NULL
)
2303 prev_ptr
->next
= pi_ptr
->next
;
2305 linked_proc_desc_table
= pi_ptr
->next
;
2309 write_register (HI_REGNUM
,
2310 read_memory_integer (new_sp
- 2 * MIPS_SAVED_REGSIZE
,
2311 MIPS_SAVED_REGSIZE
));
2312 write_register (LO_REGNUM
,
2313 read_memory_integer (new_sp
- 3 * MIPS_SAVED_REGSIZE
,
2314 MIPS_SAVED_REGSIZE
));
2315 if (MIPS_FPU_TYPE
!= MIPS_FPU_NONE
)
2316 write_register (FCRCS_REGNUM
,
2317 read_memory_integer (new_sp
- 4 * MIPS_SAVED_REGSIZE
,
2318 MIPS_SAVED_REGSIZE
));
2323 mips_print_register (regnum
, all
)
2326 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2328 /* Get the data in raw format. */
2329 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2331 printf_filtered ("%s: [Invalid]", REGISTER_NAME (regnum
));
2335 /* If an even floating point register, also print as double. */
2336 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
2337 && !((regnum
- FP0_REGNUM
) & 1))
2338 if (REGISTER_RAW_SIZE (regnum
) == 4) /* this would be silly on MIPS64 or N32 (Irix 6) */
2340 char dbuffer
[2 * MAX_REGISTER_RAW_SIZE
];
2342 read_relative_register_raw_bytes (regnum
, dbuffer
);
2343 read_relative_register_raw_bytes (regnum
+ 1, dbuffer
+ MIPS_REGSIZE
);
2344 REGISTER_CONVERT_TO_TYPE (regnum
, builtin_type_double
, dbuffer
);
2346 printf_filtered ("(d%d: ", regnum
- FP0_REGNUM
);
2347 val_print (builtin_type_double
, dbuffer
, 0, 0,
2348 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2349 printf_filtered ("); ");
2351 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
2353 /* The problem with printing numeric register names (r26, etc.) is that
2354 the user can't use them on input. Probably the best solution is to
2355 fix it so that either the numeric or the funky (a2, etc.) names
2356 are accepted on input. */
2357 if (regnum
< MIPS_NUMREGS
)
2358 printf_filtered ("(r%d): ", regnum
);
2360 printf_filtered (": ");
2362 /* If virtual format is floating, print it that way. */
2363 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2364 if (FP_REGISTER_DOUBLE
)
2365 { /* show 8-byte floats as float AND double: */
2366 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2368 printf_filtered (" (float) ");
2369 val_print (builtin_type_float
, raw_buffer
+ offset
, 0, 0,
2370 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2371 printf_filtered (", (double) ");
2372 val_print (builtin_type_double
, raw_buffer
, 0, 0,
2373 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2376 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
2377 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
2378 /* Else print as integer in hex. */
2380 print_scalar_formatted (raw_buffer
, REGISTER_VIRTUAL_TYPE (regnum
),
2381 'x', 0, gdb_stdout
);
2384 /* Replacement for generic do_registers_info.
2385 Print regs in pretty columns. */
2388 do_fp_register_row (regnum
)
2390 { /* do values for FP (float) regs */
2391 char *raw_buffer
[2];
2393 /* use HI and LO to control the order of combining two flt regs */
2394 int HI
= (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2395 int LO
= (TARGET_BYTE_ORDER
!= BIG_ENDIAN
);
2396 double doub
, flt1
, flt2
; /* doubles extracted from raw hex data */
2397 int inv1
, inv2
, inv3
;
2399 raw_buffer
[0] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2400 raw_buffer
[1] = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
2401 dbl_buffer
= (char *) alloca (2 * REGISTER_RAW_SIZE (FP0_REGNUM
));
2403 /* Get the data in raw format. */
2404 if (read_relative_register_raw_bytes (regnum
, raw_buffer
[HI
]))
2405 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2406 if (REGISTER_RAW_SIZE (regnum
) == 4)
2408 /* 4-byte registers: we can fit two registers per row. */
2409 /* Also print every pair of 4-byte regs as an 8-byte double. */
2410 if (read_relative_register_raw_bytes (regnum
+ 1, raw_buffer
[LO
]))
2411 error ("can't read register %d (%s)",
2412 regnum
+ 1, REGISTER_NAME (regnum
+ 1));
2414 /* copy the two floats into one double, and unpack both */
2415 memcpy (dbl_buffer
, raw_buffer
, sizeof (dbl_buffer
));
2416 flt1
= unpack_double (builtin_type_float
, raw_buffer
[HI
], &inv1
);
2417 flt2
= unpack_double (builtin_type_float
, raw_buffer
[LO
], &inv2
);
2418 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2420 printf_filtered (inv1
? " %-5s: <invalid float>" :
2421 " %-5s%-17.9g", REGISTER_NAME (regnum
), flt1
);
2422 printf_filtered (inv2
? " %-5s: <invalid float>" :
2423 " %-5s%-17.9g", REGISTER_NAME (regnum
+ 1), flt2
);
2424 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2425 " dbl: %-24.17g\n", doub
);
2426 /* may want to do hex display here (future enhancement) */
2430 { /* eight byte registers: print each one as float AND as double. */
2431 int offset
= 4 * (TARGET_BYTE_ORDER
== BIG_ENDIAN
);
2433 memcpy (dbl_buffer
, raw_buffer
[HI
], sizeof (dbl_buffer
));
2434 flt1
= unpack_double (builtin_type_float
,
2435 &raw_buffer
[HI
][offset
], &inv1
);
2436 doub
= unpack_double (builtin_type_double
, dbl_buffer
, &inv3
);
2438 printf_filtered (inv1
? " %-5s: <invalid float>" :
2439 " %-5s flt: %-17.9g", REGISTER_NAME (regnum
), flt1
);
2440 printf_filtered (inv3
? " dbl: <invalid double>\n" :
2441 " dbl: %-24.17g\n", doub
);
2442 /* may want to do hex display here (future enhancement) */
2448 /* Print a row's worth of GP (int) registers, with name labels above */
2451 do_gp_register_row (regnum
)
2454 /* do values for GP (int) regs */
2455 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
2456 int ncols
= (MIPS_REGSIZE
== 8 ? 4 : 8); /* display cols per row */
2458 int start_regnum
= regnum
;
2459 int numregs
= NUM_REGS
;
2462 /* For GP registers, we print a separate row of names above the vals */
2463 printf_filtered (" ");
2464 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2466 if (*REGISTER_NAME (regnum
) == '\0')
2467 continue; /* unused register */
2468 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2469 break; /* end the row: reached FP register */
2470 printf_filtered (MIPS_REGSIZE
== 8 ? "%17s" : "%9s",
2471 REGISTER_NAME (regnum
));
2474 printf_filtered (start_regnum
< MIPS_NUMREGS
? "\n R%-4d" : "\n ",
2475 start_regnum
); /* print the R0 to R31 names */
2477 regnum
= start_regnum
; /* go back to start of row */
2478 /* now print the values in hex, 4 or 8 to the row */
2479 for (col
= 0; col
< ncols
&& regnum
< numregs
; regnum
++)
2481 if (*REGISTER_NAME (regnum
) == '\0')
2482 continue; /* unused register */
2483 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2484 break; /* end row: reached FP register */
2485 /* OK: get the data in raw format. */
2486 if (read_relative_register_raw_bytes (regnum
, raw_buffer
))
2487 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
2488 /* pad small registers */
2489 for (byte
= 0; byte
< (MIPS_REGSIZE
- REGISTER_VIRTUAL_SIZE (regnum
)); byte
++)
2490 printf_filtered (" ");
2491 /* Now print the register value in hex, endian order. */
2492 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2493 for (byte
= REGISTER_RAW_SIZE (regnum
) - REGISTER_VIRTUAL_SIZE (regnum
);
2494 byte
< REGISTER_RAW_SIZE (regnum
);
2496 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2498 for (byte
= REGISTER_VIRTUAL_SIZE (regnum
) - 1;
2501 printf_filtered ("%02x", (unsigned char) raw_buffer
[byte
]);
2502 printf_filtered (" ");
2505 if (col
> 0) /* ie. if we actually printed anything... */
2506 printf_filtered ("\n");
2511 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
2514 mips_do_registers_info (regnum
, fpregs
)
2518 if (regnum
!= -1) /* do one specified register */
2520 if (*(REGISTER_NAME (regnum
)) == '\0')
2521 error ("Not a valid register for the current processor type");
2523 mips_print_register (regnum
, 0);
2524 printf_filtered ("\n");
2527 /* do all (or most) registers */
2530 while (regnum
< NUM_REGS
)
2532 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
2533 if (fpregs
) /* true for "INFO ALL-REGISTERS" command */
2534 regnum
= do_fp_register_row (regnum
); /* FP regs */
2536 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
2538 regnum
= do_gp_register_row (regnum
); /* GP (int) regs */
2543 /* Return number of args passed to a frame. described by FIP.
2544 Can return -1, meaning no way to tell. */
2547 mips_frame_num_args (frame
)
2548 struct frame_info
*frame
;
2550 #if 0 /* FIXME Use or lose this! */
2551 struct chain_info_t
*p
;
2553 p
= mips_find_cached_frame (FRAME_FP (frame
));
2555 return p
->the_info
.numargs
;
2560 /* Is this a branch with a delay slot? */
2562 static int is_delayed
PARAMS ((unsigned long));
2569 for (i
= 0; i
< NUMOPCODES
; ++i
)
2570 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
2571 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
2573 return (i
< NUMOPCODES
2574 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
2575 | INSN_COND_BRANCH_DELAY
2576 | INSN_COND_BRANCH_LIKELY
)));
2580 mips_step_skips_delay (pc
)
2583 char buf
[MIPS_INSTLEN
];
2585 /* There is no branch delay slot on MIPS16. */
2586 if (pc_is_mips16 (pc
))
2589 if (target_read_memory (pc
, buf
, MIPS_INSTLEN
) != 0)
2590 /* If error reading memory, guess that it is not a delayed branch. */
2592 return is_delayed ((unsigned long) extract_unsigned_integer (buf
, MIPS_INSTLEN
));
2596 /* Skip the PC past function prologue instructions (32-bit version).
2597 This is a helper function for mips_skip_prologue. */
2600 mips32_skip_prologue (pc
, lenient
)
2601 CORE_ADDR pc
; /* starting PC to search from */
2606 int seen_sp_adjust
= 0;
2607 int load_immediate_bytes
= 0;
2609 /* Skip the typical prologue instructions. These are the stack adjustment
2610 instruction and the instructions that save registers on the stack
2611 or in the gcc frame. */
2612 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS_INSTLEN
)
2614 unsigned long high_word
;
2616 inst
= mips_fetch_instruction (pc
);
2617 high_word
= (inst
>> 16) & 0xffff;
2620 if (lenient
&& is_delayed (inst
))
2624 if (high_word
== 0x27bd /* addiu $sp,$sp,offset */
2625 || high_word
== 0x67bd) /* daddiu $sp,$sp,offset */
2627 else if (inst
== 0x03a1e823 || /* subu $sp,$sp,$at */
2628 inst
== 0x03a8e823) /* subu $sp,$sp,$t0 */
2630 else if (((inst
& 0xFFE00000) == 0xAFA00000 /* sw reg,n($sp) */
2631 || (inst
& 0xFFE00000) == 0xFFA00000) /* sd reg,n($sp) */
2632 && (inst
& 0x001F0000)) /* reg != $zero */
2635 else if ((inst
& 0xFFE00000) == 0xE7A00000) /* swc1 freg,n($sp) */
2637 else if ((inst
& 0xF3E00000) == 0xA3C00000 && (inst
& 0x001F0000))
2639 continue; /* reg != $zero */
2641 /* move $s8,$sp. With different versions of gas this will be either
2642 `addu $s8,$sp,$zero' or `or $s8,$sp,$zero' or `daddu s8,sp,$0'.
2643 Accept any one of these. */
2644 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
2647 else if ((inst
& 0xFF9F07FF) == 0x00800021) /* move reg,$a0-$a3 */
2649 else if (high_word
== 0x3c1c) /* lui $gp,n */
2651 else if (high_word
== 0x279c) /* addiu $gp,$gp,n */
2653 else if (inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2654 || inst
== 0x033ce021) /* addu $gp,$t9,$gp */
2656 /* The following instructions load $at or $t0 with an immediate
2657 value in preparation for a stack adjustment via
2658 subu $sp,$sp,[$at,$t0]. These instructions could also initialize
2659 a local variable, so we accept them only before a stack adjustment
2660 instruction was seen. */
2661 else if (!seen_sp_adjust
)
2663 if (high_word
== 0x3c01 || /* lui $at,n */
2664 high_word
== 0x3c08) /* lui $t0,n */
2666 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2669 else if (high_word
== 0x3421 || /* ori $at,$at,n */
2670 high_word
== 0x3508 || /* ori $t0,$t0,n */
2671 high_word
== 0x3401 || /* ori $at,$zero,n */
2672 high_word
== 0x3408) /* ori $t0,$zero,n */
2674 load_immediate_bytes
+= MIPS_INSTLEN
; /* FIXME!! */
2684 /* In a frameless function, we might have incorrectly
2685 skipped some load immediate instructions. Undo the skipping
2686 if the load immediate was not followed by a stack adjustment. */
2687 if (load_immediate_bytes
&& !seen_sp_adjust
)
2688 pc
-= load_immediate_bytes
;
2692 /* Skip the PC past function prologue instructions (16-bit version).
2693 This is a helper function for mips_skip_prologue. */
2696 mips16_skip_prologue (pc
, lenient
)
2697 CORE_ADDR pc
; /* starting PC to search from */
2701 int extend_bytes
= 0;
2702 int prev_extend_bytes
;
2704 /* Table of instructions likely to be found in a function prologue. */
2707 unsigned short inst
;
2708 unsigned short mask
;
2715 , /* addiu $sp,offset */
2719 , /* daddiu $sp,offset */
2723 , /* sw reg,n($sp) */
2727 , /* sd reg,n($sp) */
2731 , /* sw $ra,n($sp) */
2735 , /* sd $ra,n($sp) */
2743 , /* sw $a0-$a3,n($s1) */
2747 , /* move reg,$a0-$a3 */
2751 , /* entry pseudo-op */
2755 , /* addiu $s1,$sp,n */
2758 } /* end of table marker */
2761 /* Skip the typical prologue instructions. These are the stack adjustment
2762 instruction and the instructions that save registers on the stack
2763 or in the gcc frame. */
2764 for (end_pc
= pc
+ 100; pc
< end_pc
; pc
+= MIPS16_INSTLEN
)
2766 unsigned short inst
;
2769 inst
= mips_fetch_instruction (pc
);
2771 /* Normally we ignore an extend instruction. However, if it is
2772 not followed by a valid prologue instruction, we must adjust
2773 the pc back over the extend so that it won't be considered
2774 part of the prologue. */
2775 if ((inst
& 0xf800) == 0xf000) /* extend */
2777 extend_bytes
= MIPS16_INSTLEN
;
2780 prev_extend_bytes
= extend_bytes
;
2783 /* Check for other valid prologue instructions besides extend. */
2784 for (i
= 0; table
[i
].mask
!= 0; i
++)
2785 if ((inst
& table
[i
].mask
) == table
[i
].inst
) /* found, get out */
2787 if (table
[i
].mask
!= 0) /* it was in table? */
2788 continue; /* ignore it */
2792 /* Return the current pc, adjusted backwards by 2 if
2793 the previous instruction was an extend. */
2794 return pc
- prev_extend_bytes
;
2800 /* To skip prologues, I use this predicate. Returns either PC itself
2801 if the code at PC does not look like a function prologue; otherwise
2802 returns an address that (if we're lucky) follows the prologue. If
2803 LENIENT, then we must skip everything which is involved in setting
2804 up the frame (it's OK to skip more, just so long as we don't skip
2805 anything which might clobber the registers which are being saved.
2806 We must skip more in the case where part of the prologue is in the
2807 delay slot of a non-prologue instruction). */
2810 mips_skip_prologue (pc
, lenient
)
2814 /* See if we can determine the end of the prologue via the symbol table.
2815 If so, then return either PC, or the PC after the prologue, whichever
2818 CORE_ADDR post_prologue_pc
= after_prologue (pc
, NULL
);
2820 if (post_prologue_pc
!= 0)
2821 return max (pc
, post_prologue_pc
);
2823 /* Can't determine prologue from the symbol table, need to examine
2826 if (pc_is_mips16 (pc
))
2827 return mips16_skip_prologue (pc
, lenient
);
2829 return mips32_skip_prologue (pc
, lenient
);
2833 /* The lenient prologue stuff should be superseded by the code in
2834 init_extra_frame_info which looks to see whether the stores mentioned
2835 in the proc_desc have actually taken place. */
2837 /* Is address PC in the prologue (loosely defined) for function at
2841 mips_in_lenient_prologue (startaddr
, pc
)
2842 CORE_ADDR startaddr
;
2845 CORE_ADDR end_prologue
= mips_skip_prologue (startaddr
, 1);
2846 return pc
>= startaddr
&& pc
< end_prologue
;
2850 /* Determine how a return value is stored within the MIPS register
2851 file, given the return type `valtype'. */
2853 struct return_value_word
2861 static void return_value_location
PARAMS ((struct type
*, struct return_value_word
*, struct return_value_word
*));
2864 return_value_location (valtype
, hi
, lo
)
2865 struct type
*valtype
;
2866 struct return_value_word
*hi
;
2867 struct return_value_word
*lo
;
2869 int len
= TYPE_LENGTH (valtype
);
2871 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2872 && ((MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
&& (len
== 4 || len
== 8))
2873 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
&& len
== 4)))
2875 if (!FP_REGISTER_DOUBLE
&& len
== 8)
2877 /* We need to break a 64bit float in two 32 bit halves and
2878 spread them across a floating-point register pair. */
2879 lo
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 4 : 0;
2880 hi
->buf_offset
= TARGET_BYTE_ORDER
== BIG_ENDIAN
? 0 : 4;
2881 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2882 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8)
2884 hi
->reg_offset
= lo
->reg_offset
;
2885 lo
->reg
= FP0_REGNUM
+ 0;
2886 hi
->reg
= FP0_REGNUM
+ 1;
2892 /* The floating point value fits in a single floating-point
2894 lo
->reg_offset
= ((TARGET_BYTE_ORDER
== BIG_ENDIAN
2895 && REGISTER_RAW_SIZE (FP0_REGNUM
) == 8
2898 lo
->reg
= FP0_REGNUM
;
2909 /* Locate a result possibly spread across two registers. */
2911 lo
->reg
= regnum
+ 0;
2912 hi
->reg
= regnum
+ 1;
2913 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2914 && len
< MIPS_SAVED_REGSIZE
)
2916 /* "un-left-justify" the value in the low register */
2917 lo
->reg_offset
= MIPS_SAVED_REGSIZE
- len
;
2922 else if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2923 && len
> MIPS_SAVED_REGSIZE
/* odd-size structs */
2924 && len
< MIPS_SAVED_REGSIZE
* 2
2925 && (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
2926 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
2928 /* "un-left-justify" the value spread across two registers. */
2929 lo
->reg_offset
= 2 * MIPS_SAVED_REGSIZE
- len
;
2930 lo
->len
= MIPS_SAVED_REGSIZE
- lo
->reg_offset
;
2932 hi
->len
= len
- lo
->len
;
2936 /* Only perform a partial copy of the second register. */
2939 if (len
> MIPS_SAVED_REGSIZE
)
2941 lo
->len
= MIPS_SAVED_REGSIZE
;
2942 hi
->len
= len
- MIPS_SAVED_REGSIZE
;
2950 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
2951 && REGISTER_RAW_SIZE (regnum
) == 8
2952 && MIPS_SAVED_REGSIZE
== 4)
2954 /* Account for the fact that only the least-signficant part
2955 of the register is being used */
2956 lo
->reg_offset
+= 4;
2957 hi
->reg_offset
+= 4;
2960 hi
->buf_offset
= lo
->len
;
2964 /* Given a return value in `regbuf' with a type `valtype', extract and
2965 copy its value into `valbuf'. */
2968 mips_extract_return_value (valtype
, regbuf
, valbuf
)
2969 struct type
*valtype
;
2970 char regbuf
[REGISTER_BYTES
];
2973 struct return_value_word lo
;
2974 struct return_value_word hi
;
2975 return_value_location (valtype
, &lo
, &hi
);
2977 memcpy (valbuf
+ lo
.buf_offset
,
2978 regbuf
+ REGISTER_BYTE (lo
.reg
) + lo
.reg_offset
,
2982 memcpy (valbuf
+ hi
.buf_offset
,
2983 regbuf
+ REGISTER_BYTE (hi
.reg
) + hi
.reg_offset
,
2989 int len
= TYPE_LENGTH (valtype
);
2992 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
2993 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
2994 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
2995 && len
<= MIPS_FPU_SINGLE_REGSIZE
)))
2996 regnum
= FP0_REGNUM
;
2998 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
2999 { /* "un-left-justify" the value from the register */
3000 if (len
< REGISTER_RAW_SIZE (regnum
))
3001 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3002 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3003 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3004 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3005 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3006 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3008 memcpy (valbuf
, regbuf
+ REGISTER_BYTE (regnum
) + offset
, len
);
3009 REGISTER_CONVERT_TO_TYPE (regnum
, valtype
, valbuf
);
3013 /* Given a return value in `valbuf' with a type `valtype', write it's
3014 value into the appropriate register. */
3017 mips_store_return_value (valtype
, valbuf
)
3018 struct type
*valtype
;
3021 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3022 struct return_value_word lo
;
3023 struct return_value_word hi
;
3024 return_value_location (valtype
, &lo
, &hi
);
3026 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3027 memcpy (raw_buffer
+ lo
.reg_offset
, valbuf
+ lo
.buf_offset
, lo
.len
);
3028 write_register_bytes (REGISTER_BYTE (lo
.reg
),
3030 REGISTER_RAW_SIZE (lo
.reg
));
3034 memset (raw_buffer
, 0, sizeof (raw_buffer
));
3035 memcpy (raw_buffer
+ hi
.reg_offset
, valbuf
+ hi
.buf_offset
, hi
.len
);
3036 write_register_bytes (REGISTER_BYTE (hi
.reg
),
3038 REGISTER_RAW_SIZE (hi
.reg
));
3044 int len
= TYPE_LENGTH (valtype
);
3045 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
3048 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
3049 && (MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
3050 || (MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
3051 && len
<= MIPS_REGSIZE
)))
3052 regnum
= FP0_REGNUM
;
3054 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3055 { /* "left-justify" the value in the register */
3056 if (len
< REGISTER_RAW_SIZE (regnum
))
3057 offset
= REGISTER_RAW_SIZE (regnum
) - len
;
3058 if (len
> REGISTER_RAW_SIZE (regnum
) && /* odd-size structs */
3059 len
< REGISTER_RAW_SIZE (regnum
) * 2 &&
3060 (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
||
3061 TYPE_CODE (valtype
) == TYPE_CODE_UNION
))
3062 offset
= 2 * REGISTER_RAW_SIZE (regnum
) - len
;
3064 memcpy (raw_buffer
+ offset
, valbuf
, len
);
3065 REGISTER_CONVERT_FROM_TYPE (regnum
, valtype
, raw_buffer
);
3066 write_register_bytes (REGISTER_BYTE (regnum
), raw_buffer
,
3067 len
> REGISTER_RAW_SIZE (regnum
) ?
3068 len
: REGISTER_RAW_SIZE (regnum
));
3072 /* Exported procedure: Is PC in the signal trampoline code */
3075 in_sigtramp (pc
, ignore
)
3077 char *ignore
; /* function name */
3079 if (sigtramp_address
== 0)
3081 return (pc
>= sigtramp_address
&& pc
< sigtramp_end
);
3084 /* Commands to show/set the MIPS FPU type. */
3086 static void show_mipsfpu_command
PARAMS ((char *, int));
3088 show_mipsfpu_command (args
, from_tty
)
3094 switch (MIPS_FPU_TYPE
)
3096 case MIPS_FPU_SINGLE
:
3097 fpu
= "single-precision";
3099 case MIPS_FPU_DOUBLE
:
3100 fpu
= "double-precision";
3103 fpu
= "absent (none)";
3106 if (mips_fpu_type_auto
)
3107 printf_unfiltered ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
3110 printf_unfiltered ("The MIPS floating-point coprocessor is assumed to be %s\n",
3115 static void set_mipsfpu_command
PARAMS ((char *, int));
3117 set_mipsfpu_command (args
, from_tty
)
3121 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
3122 show_mipsfpu_command (args
, from_tty
);
3125 static void set_mipsfpu_single_command
PARAMS ((char *, int));
3127 set_mipsfpu_single_command (args
, from_tty
)
3131 mips_fpu_type
= MIPS_FPU_SINGLE
;
3132 mips_fpu_type_auto
= 0;
3135 static void set_mipsfpu_double_command
PARAMS ((char *, int));
3137 set_mipsfpu_double_command (args
, from_tty
)
3141 mips_fpu_type
= MIPS_FPU_DOUBLE
;
3142 mips_fpu_type_auto
= 0;
3145 static void set_mipsfpu_none_command
PARAMS ((char *, int));
3147 set_mipsfpu_none_command (args
, from_tty
)
3151 mips_fpu_type
= MIPS_FPU_NONE
;
3152 mips_fpu_type_auto
= 0;
3155 static void set_mipsfpu_auto_command
PARAMS ((char *, int));
3157 set_mipsfpu_auto_command (args
, from_tty
)
3161 mips_fpu_type_auto
= 1;
3164 /* Command to set the processor type. */
3167 mips_set_processor_type_command (args
, from_tty
)
3173 if (tmp_mips_processor_type
== NULL
|| *tmp_mips_processor_type
== '\0')
3175 printf_unfiltered ("The known MIPS processor types are as follows:\n\n");
3176 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3177 printf_unfiltered ("%s\n", mips_processor_type_table
[i
].name
);
3179 /* Restore the value. */
3180 tmp_mips_processor_type
= strsave (mips_processor_type
);
3185 if (!mips_set_processor_type (tmp_mips_processor_type
))
3187 error ("Unknown processor type `%s'.", tmp_mips_processor_type
);
3188 /* Restore its value. */
3189 tmp_mips_processor_type
= strsave (mips_processor_type
);
3194 mips_show_processor_type_command (args
, from_tty
)
3200 /* Modify the actual processor type. */
3203 mips_set_processor_type (str
)
3211 for (i
= 0; mips_processor_type_table
[i
].name
!= NULL
; ++i
)
3213 if (strcasecmp (str
, mips_processor_type_table
[i
].name
) == 0)
3215 mips_processor_type
= str
;
3216 mips_processor_reg_names
= mips_processor_type_table
[i
].regnames
;
3218 /* FIXME tweak fpu flag too */
3225 /* Attempt to identify the particular processor model by reading the
3229 mips_read_processor_type ()
3233 prid
= read_register (PRID_REGNUM
);
3235 if ((prid
& ~0xf) == 0x700)
3236 return savestring ("r3041", strlen ("r3041"));
3241 /* Just like reinit_frame_cache, but with the right arguments to be
3242 callable as an sfunc. */
3245 reinit_frame_cache_sfunc (args
, from_tty
, c
)
3248 struct cmd_list_element
*c
;
3250 reinit_frame_cache ();
3254 gdb_print_insn_mips (memaddr
, info
)
3256 disassemble_info
*info
;
3258 mips_extra_func_info_t proc_desc
;
3260 /* Search for the function containing this address. Set the low bit
3261 of the address when searching, in case we were given an even address
3262 that is the start of a 16-bit function. If we didn't do this,
3263 the search would fail because the symbol table says the function
3264 starts at an odd address, i.e. 1 byte past the given address. */
3265 memaddr
= ADDR_BITS_REMOVE (memaddr
);
3266 proc_desc
= non_heuristic_proc_desc (MAKE_MIPS16_ADDR (memaddr
), NULL
);
3268 /* Make an attempt to determine if this is a 16-bit function. If
3269 the procedure descriptor exists and the address therein is odd,
3270 it's definitely a 16-bit function. Otherwise, we have to just
3271 guess that if the address passed in is odd, it's 16-bits. */
3273 info
->mach
= pc_is_mips16 (PROC_LOW_ADDR (proc_desc
)) ? 16 : TM_PRINT_INSN_MACH
;
3275 info
->mach
= pc_is_mips16 (memaddr
) ? 16 : TM_PRINT_INSN_MACH
;
3277 /* Round down the instruction address to the appropriate boundary. */
3278 memaddr
&= (info
->mach
== 16 ? ~1 : ~3);
3280 /* Call the appropriate disassembler based on the target endian-ness. */
3281 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3282 return print_insn_big_mips (memaddr
, info
);
3284 return print_insn_little_mips (memaddr
, info
);
3287 /* Old-style breakpoint macros.
3288 The IDT board uses an unusual breakpoint value, and sometimes gets
3289 confused when it sees the usual MIPS breakpoint instruction. */
3291 #define BIG_BREAKPOINT {0, 0x5, 0, 0xd}
3292 #define LITTLE_BREAKPOINT {0xd, 0, 0x5, 0}
3293 #define PMON_BIG_BREAKPOINT {0, 0, 0, 0xd}
3294 #define PMON_LITTLE_BREAKPOINT {0xd, 0, 0, 0}
3295 #define IDT_BIG_BREAKPOINT {0, 0, 0x0a, 0xd}
3296 #define IDT_LITTLE_BREAKPOINT {0xd, 0x0a, 0, 0}
3297 #define MIPS16_BIG_BREAKPOINT {0xe8, 0xa5}
3298 #define MIPS16_LITTLE_BREAKPOINT {0xa5, 0xe8}
3300 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the program
3301 counter value to determine whether a 16- or 32-bit breakpoint should be
3302 used. It returns a pointer to a string of bytes that encode a breakpoint
3303 instruction, stores the length of the string to *lenptr, and adjusts pc
3304 (if necessary) to point to the actual memory location where the
3305 breakpoint should be inserted. */
3308 mips_breakpoint_from_pc (pcptr
, lenptr
)
3312 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
3314 if (pc_is_mips16 (*pcptr
))
3316 static char mips16_big_breakpoint
[] = MIPS16_BIG_BREAKPOINT
;
3317 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3318 *lenptr
= sizeof (mips16_big_breakpoint
);
3319 return mips16_big_breakpoint
;
3323 static char big_breakpoint
[] = BIG_BREAKPOINT
;
3324 static char pmon_big_breakpoint
[] = PMON_BIG_BREAKPOINT
;
3325 static char idt_big_breakpoint
[] = IDT_BIG_BREAKPOINT
;
3327 *lenptr
= sizeof (big_breakpoint
);
3329 if (strcmp (target_shortname
, "mips") == 0)
3330 return idt_big_breakpoint
;
3331 else if (strcmp (target_shortname
, "ddb") == 0
3332 || strcmp (target_shortname
, "pmon") == 0
3333 || strcmp (target_shortname
, "lsi") == 0)
3334 return pmon_big_breakpoint
;
3336 return big_breakpoint
;
3341 if (pc_is_mips16 (*pcptr
))
3343 static char mips16_little_breakpoint
[] = MIPS16_LITTLE_BREAKPOINT
;
3344 *pcptr
= UNMAKE_MIPS16_ADDR (*pcptr
);
3345 *lenptr
= sizeof (mips16_little_breakpoint
);
3346 return mips16_little_breakpoint
;
3350 static char little_breakpoint
[] = LITTLE_BREAKPOINT
;
3351 static char pmon_little_breakpoint
[] = PMON_LITTLE_BREAKPOINT
;
3352 static char idt_little_breakpoint
[] = IDT_LITTLE_BREAKPOINT
;
3354 *lenptr
= sizeof (little_breakpoint
);
3356 if (strcmp (target_shortname
, "mips") == 0)
3357 return idt_little_breakpoint
;
3358 else if (strcmp (target_shortname
, "ddb") == 0
3359 || strcmp (target_shortname
, "pmon") == 0
3360 || strcmp (target_shortname
, "lsi") == 0)
3361 return pmon_little_breakpoint
;
3363 return little_breakpoint
;
3368 /* If PC is in a mips16 call or return stub, return the address of the target
3369 PC, which is either the callee or the caller. There are several
3370 cases which must be handled:
3372 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3373 target PC is in $31 ($ra).
3374 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3375 and the target PC is in $2.
3376 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3377 before the jal instruction, this is effectively a call stub
3378 and the the target PC is in $2. Otherwise this is effectively
3379 a return stub and the target PC is in $18.
3381 See the source code for the stubs in gcc/config/mips/mips16.S for
3384 This function implements the SKIP_TRAMPOLINE_CODE macro.
3392 CORE_ADDR start_addr
;
3394 /* Find the starting address and name of the function containing the PC. */
3395 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
3398 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
3399 target PC is in $31 ($ra). */
3400 if (strcmp (name
, "__mips16_ret_sf") == 0
3401 || strcmp (name
, "__mips16_ret_df") == 0)
3402 return read_register (RA_REGNUM
);
3404 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3406 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
3407 and the target PC is in $2. */
3408 if (name
[19] >= '0' && name
[19] <= '9')
3409 return read_register (2);
3411 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3412 before the jal instruction, this is effectively a call stub
3413 and the the target PC is in $2. Otherwise this is effectively
3414 a return stub and the target PC is in $18. */
3415 else if (name
[19] == 's' || name
[19] == 'd')
3417 if (pc
== start_addr
)
3419 /* Check if the target of the stub is a compiler-generated
3420 stub. Such a stub for a function bar might have a name
3421 like __fn_stub_bar, and might look like this:
3426 la $1,bar (becomes a lui/addiu pair)
3428 So scan down to the lui/addi and extract the target
3429 address from those two instructions. */
3431 CORE_ADDR target_pc
= read_register (2);
3435 /* See if the name of the target function is __fn_stub_*. */
3436 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) == 0)
3438 if (strncmp (name
, "__fn_stub_", 10) != 0
3439 && strcmp (name
, "etext") != 0
3440 && strcmp (name
, "_etext") != 0)
3443 /* Scan through this _fn_stub_ code for the lui/addiu pair.
3444 The limit on the search is arbitrarily set to 20
3445 instructions. FIXME. */
3446 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSTLEN
)
3448 inst
= mips_fetch_instruction (target_pc
);
3449 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
3450 pc
= (inst
<< 16) & 0xffff0000; /* high word */
3451 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
3452 return pc
| (inst
& 0xffff); /* low word */
3455 /* Couldn't find the lui/addui pair, so return stub address. */
3459 /* This is the 'return' part of a call stub. The return
3460 address is in $r18. */
3461 return read_register (18);
3464 return 0; /* not a stub */
3468 /* Return non-zero if the PC is inside a call thunk (aka stub or trampoline).
3469 This implements the IN_SOLIB_CALL_TRAMPOLINE macro. */
3472 mips_in_call_stub (pc
, name
)
3476 CORE_ADDR start_addr
;
3478 /* Find the starting address of the function containing the PC. If the
3479 caller didn't give us a name, look it up at the same time. */
3480 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
3483 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
3485 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub. */
3486 if (name
[19] >= '0' && name
[19] <= '9')
3488 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
3489 before the jal instruction, this is effectively a call stub. */
3490 else if (name
[19] == 's' || name
[19] == 'd')
3491 return pc
== start_addr
;
3494 return 0; /* not a stub */
3498 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
3499 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
3502 mips_in_return_stub (pc
, name
)
3506 CORE_ADDR start_addr
;
3508 /* Find the starting address of the function containing the PC. */
3509 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
3512 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub. */
3513 if (strcmp (name
, "__mips16_ret_sf") == 0
3514 || strcmp (name
, "__mips16_ret_df") == 0)
3517 /* If the PC is in __mips16_call_stub_{s,d}f_{0..10} but not at the start,
3518 i.e. after the jal instruction, this is effectively a return stub. */
3519 if (strncmp (name
, "__mips16_call_stub_", 19) == 0
3520 && (name
[19] == 's' || name
[19] == 'd')
3521 && pc
!= start_addr
)
3524 return 0; /* not a stub */
3528 /* Return non-zero if the PC is in a library helper function that should
3529 be ignored. This implements the IGNORE_HELPER_CALL macro. */
3532 mips_ignore_helper (pc
)
3537 /* Find the starting address and name of the function containing the PC. */
3538 if (find_pc_partial_function (pc
, &name
, NULL
, NULL
) == 0)
3541 /* If the PC is in __mips16_ret_{d,s}f, this is a library helper function
3542 that we want to ignore. */
3543 return (strcmp (name
, "__mips16_ret_sf") == 0
3544 || strcmp (name
, "__mips16_ret_df") == 0);
3548 /* Return a location where we can set a breakpoint that will be hit
3549 when an inferior function call returns. This is normally the
3550 program's entry point. Executables that don't have an entry
3551 point (e.g. programs in ROM) should define a symbol __CALL_DUMMY_ADDRESS
3552 whose address is the location where the breakpoint should be placed. */
3555 mips_call_dummy_address ()
3557 struct minimal_symbol
*sym
;
3559 sym
= lookup_minimal_symbol ("__CALL_DUMMY_ADDRESS", NULL
, NULL
);
3561 return SYMBOL_VALUE_ADDRESS (sym
);
3563 return entry_point_address ();
3568 _initialize_mips_tdep ()
3570 static struct cmd_list_element
*mipsfpulist
= NULL
;
3571 struct cmd_list_element
*c
;
3573 if (!tm_print_insn
) /* Someone may have already set it */
3574 tm_print_insn
= gdb_print_insn_mips
;
3576 /* Let the user turn off floating point and set the fence post for
3577 heuristic_proc_start. */
3579 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
3580 "Set use of MIPS floating-point coprocessor.",
3581 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
3582 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
3583 "Select single-precision MIPS floating-point coprocessor.",
3585 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
3586 "Select double-precision MIPS floating-point coprocessor .",
3588 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
3589 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
3590 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
3591 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
3592 "Select no MIPS floating-point coprocessor.",
3594 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
3595 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
3596 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
3597 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
3598 "Select MIPS floating-point coprocessor automatically.",
3600 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
3601 "Show current use of MIPS floating-point coprocessor target.",
3604 c
= add_set_cmd ("processor", class_support
, var_string_noescape
,
3605 (char *) &tmp_mips_processor_type
,
3606 "Set the type of MIPS processor in use.\n\
3607 Set this to be able to access processor-type-specific registers.\n\
3610 c
->function
.cfunc
= mips_set_processor_type_command
;
3611 c
= add_show_from_set (c
, &showlist
);
3612 c
->function
.cfunc
= mips_show_processor_type_command
;
3614 tmp_mips_processor_type
= strsave (DEFAULT_MIPS_TYPE
);
3615 mips_set_processor_type_command (strsave (DEFAULT_MIPS_TYPE
), 0);
3617 /* We really would like to have both "0" and "unlimited" work, but
3618 command.c doesn't deal with that. So make it a var_zinteger
3619 because the user can always use "999999" or some such for unlimited. */
3620 c
= add_set_cmd ("heuristic-fence-post", class_support
, var_zinteger
,
3621 (char *) &heuristic_fence_post
,
3623 Set the distance searched for the start of a function.\n\
3624 If you are debugging a stripped executable, GDB needs to search through the\n\
3625 program for the start of a function. This command sets the distance of the\n\
3626 search. The only need to set it is when debugging a stripped executable.",
3628 /* We need to throw away the frame cache when we set this, since it
3629 might change our ability to get backtraces. */
3630 c
->function
.sfunc
= reinit_frame_cache_sfunc
;
3631 add_show_from_set (c
, &showlist
);
3633 /* Allow the user to control whether the upper bits of 64-bit
3634 addresses should be zeroed. */
3636 (add_set_cmd ("mask-address", no_class
, var_boolean
, (char *) &mask_address_p
,
3637 "Set zeroing of upper 32 bits of 64-bit addresses.\n\
3638 Use \"on\" to enable the masking, and \"off\" to disable it.\n\
3639 Without an argument, zeroing of upper address bits is enabled.", &setlist
),
3642 /* Allow the user to control the size of 32 bit registers within the
3643 raw remote packet. */
3644 add_show_from_set (add_set_cmd ("remote-mips64-transfers-32bit-regs",
3647 (char *)&mips64_transfers_32bit_regs_p
, "\
3648 Set compatibility with MIPS targets that transfers 32 and 64 bit quantities.\n\
3649 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
3650 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
3651 64 bits for others. Use \"off\" to disable compatibility mode",