1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2012 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "gdb_string.h"
25 #include "gdb_assert.h"
37 #include "arch-utils.h"
40 #include "mips-tdep.h"
42 #include "reggroups.h"
43 #include "opcode/mips.h"
47 #include "sim-regno.h"
49 #include "frame-unwind.h"
50 #include "frame-base.h"
51 #include "trad-frame.h"
53 #include "floatformat.h"
55 #include "target-descriptions.h"
56 #include "dwarf2-frame.h"
57 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 static int mips32_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
);
66 static int micromips_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
,
68 static int mips16_instruction_has_delay_slot (struct gdbarch
*, CORE_ADDR
,
71 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
72 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
73 #define ST0_FR (1 << 26)
75 /* The sizes of floating point registers. */
79 MIPS_FPU_SINGLE_REGSIZE
= 4,
80 MIPS_FPU_DOUBLE_REGSIZE
= 8
89 static const char *mips_abi_string
;
91 static const char *const mips_abi_strings
[] = {
102 /* For backwards compatibility we default to MIPS16. This flag is
103 overridden as soon as unambiguous ELF file flags tell us the
104 compressed ISA encoding used. */
105 static const char mips_compression_mips16
[] = "mips16";
106 static const char mips_compression_micromips
[] = "micromips";
107 static const char *const mips_compression_strings
[] =
109 mips_compression_mips16
,
110 mips_compression_micromips
,
114 static const char *mips_compression_string
= mips_compression_mips16
;
116 /* The standard register names, and all the valid aliases for them. */
117 struct register_alias
123 /* Aliases for o32 and most other ABIs. */
124 const struct register_alias mips_o32_aliases
[] = {
131 /* Aliases for n32 and n64. */
132 const struct register_alias mips_n32_n64_aliases
[] = {
139 /* Aliases for ABI-independent registers. */
140 const struct register_alias mips_register_aliases
[] = {
141 /* The architecture manuals specify these ABI-independent names for
143 #define R(n) { "r" #n, n }
144 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
145 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
146 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
147 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
150 /* k0 and k1 are sometimes called these instead (for "kernel
155 /* This is the traditional GDB name for the CP0 status register. */
156 { "sr", MIPS_PS_REGNUM
},
158 /* This is the traditional GDB name for the CP0 BadVAddr register. */
159 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
161 /* This is the traditional GDB name for the FCSR. */
162 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
165 const struct register_alias mips_numeric_register_aliases
[] = {
166 #define R(n) { #n, n }
167 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
168 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
169 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
170 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
174 #ifndef MIPS_DEFAULT_FPU_TYPE
175 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
177 static int mips_fpu_type_auto
= 1;
178 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
180 static int mips_debug
= 0;
182 /* Properties (for struct target_desc) describing the g/G packet
184 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
185 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
187 struct target_desc
*mips_tdesc_gp32
;
188 struct target_desc
*mips_tdesc_gp64
;
190 const struct mips_regnum
*
191 mips_regnum (struct gdbarch
*gdbarch
)
193 return gdbarch_tdep (gdbarch
)->regnum
;
197 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
199 return mips_regnum (gdbarch
)->fp0
+ 12;
202 /* Return 1 if REGNUM refers to a floating-point general register, raw
203 or cooked. Otherwise return 0. */
206 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
208 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
210 return (rawnum
>= mips_regnum (gdbarch
)->fp0
211 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
214 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
216 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
218 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
219 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
221 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
222 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
224 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
226 /* Return the MIPS ABI associated with GDBARCH. */
228 mips_abi (struct gdbarch
*gdbarch
)
230 return gdbarch_tdep (gdbarch
)->mips_abi
;
234 mips_isa_regsize (struct gdbarch
*gdbarch
)
236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
238 /* If we know how big the registers are, use that size. */
239 if (tdep
->register_size_valid_p
)
240 return tdep
->register_size
;
242 /* Fall back to the previous behavior. */
243 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
244 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
247 /* Return the currently configured (or set) saved register size. */
250 mips_abi_regsize (struct gdbarch
*gdbarch
)
252 switch (mips_abi (gdbarch
))
254 case MIPS_ABI_EABI32
:
260 case MIPS_ABI_EABI64
:
262 case MIPS_ABI_UNKNOWN
:
265 internal_error (__FILE__
, __LINE__
, _("bad switch"));
269 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
270 are some functions to handle addresses associated with compressed
271 code including but not limited to testing, setting, or clearing
272 bit 0 of such addresses. */
274 /* Return one iff compressed code is the MIPS16 instruction set. */
277 is_mips16_isa (struct gdbarch
*gdbarch
)
279 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
282 /* Return one iff compressed code is the microMIPS instruction set. */
285 is_micromips_isa (struct gdbarch
*gdbarch
)
287 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
290 /* Return one iff ADDR denotes compressed code. */
293 is_compact_addr (CORE_ADDR addr
)
298 /* Return one iff ADDR denotes standard ISA code. */
301 is_mips_addr (CORE_ADDR addr
)
303 return !is_compact_addr (addr
);
306 /* Return one iff ADDR denotes MIPS16 code. */
309 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
311 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
314 /* Return one iff ADDR denotes microMIPS code. */
317 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
319 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
322 /* Strip the ISA (compression) bit off from ADDR. */
325 unmake_compact_addr (CORE_ADDR addr
)
327 return ((addr
) & ~(CORE_ADDR
) 1);
330 /* Add the ISA (compression) bit to ADDR. */
333 make_compact_addr (CORE_ADDR addr
)
335 return ((addr
) | (CORE_ADDR
) 1);
338 /* Functions for setting and testing a bit in a minimal symbol that
339 marks it as MIPS16 or microMIPS function. The MSB of the minimal
340 symbol's "info" field is used for this purpose.
342 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
343 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
344 one of the "special" bits in a minimal symbol to mark it accordingly.
345 The test checks an ELF-private flag that is valid for true function
346 symbols only; in particular synthetic symbols such as for PLT stubs
347 have no ELF-private part at all.
349 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
350 in a minimal symbol. */
353 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
355 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
357 if ((sym
->flags
& BSF_SYNTHETIC
) != 0)
360 if (ELF_ST_IS_MICROMIPS (elfsym
->internal_elf_sym
.st_other
))
361 MSYMBOL_TARGET_FLAG_2 (msym
) = 1;
362 else if (ELF_ST_IS_MIPS16 (elfsym
->internal_elf_sym
.st_other
))
363 MSYMBOL_TARGET_FLAG_1 (msym
) = 1;
366 /* Return one iff MSYM refers to standard ISA code. */
369 msymbol_is_mips (struct minimal_symbol
*msym
)
371 return !(MSYMBOL_TARGET_FLAG_1 (msym
) | MSYMBOL_TARGET_FLAG_2 (msym
));
374 /* Return one iff MSYM refers to MIPS16 code. */
377 msymbol_is_mips16 (struct minimal_symbol
*msym
)
379 return MSYMBOL_TARGET_FLAG_1 (msym
);
382 /* Return one iff MSYM refers to microMIPS code. */
385 msymbol_is_micromips (struct minimal_symbol
*msym
)
387 return MSYMBOL_TARGET_FLAG_2 (msym
);
390 /* XFER a value from the big/little/left end of the register.
391 Depending on the size of the value it might occupy the entire
392 register or just part of it. Make an allowance for this, aligning
393 things accordingly. */
396 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
397 int reg_num
, int length
,
398 enum bfd_endian endian
, gdb_byte
*in
,
399 const gdb_byte
*out
, int buf_offset
)
403 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
404 /* Need to transfer the left or right part of the register, based on
405 the targets byte order. */
409 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
411 case BFD_ENDIAN_LITTLE
:
414 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
418 internal_error (__FILE__
, __LINE__
, _("bad switch"));
421 fprintf_unfiltered (gdb_stderr
,
422 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
423 reg_num
, reg_offset
, buf_offset
, length
);
424 if (mips_debug
&& out
!= NULL
)
427 fprintf_unfiltered (gdb_stdlog
, "out ");
428 for (i
= 0; i
< length
; i
++)
429 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
432 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
435 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
437 if (mips_debug
&& in
!= NULL
)
440 fprintf_unfiltered (gdb_stdlog
, "in ");
441 for (i
= 0; i
< length
; i
++)
442 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
445 fprintf_unfiltered (gdb_stdlog
, "\n");
448 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
449 compatiblity mode. A return value of 1 means that we have
450 physical 64-bit registers, but should treat them as 32-bit registers. */
453 mips2_fp_compat (struct frame_info
*frame
)
455 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
456 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
458 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
462 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
463 in all the places we deal with FP registers. PR gdb/413. */
464 /* Otherwise check the FR bit in the status register - it controls
465 the FP compatiblity mode. If it is clear we are in compatibility
467 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
474 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
476 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
478 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
480 /* The list of available "set mips " and "show mips " commands. */
482 static struct cmd_list_element
*setmipscmdlist
= NULL
;
483 static struct cmd_list_element
*showmipscmdlist
= NULL
;
485 /* Integer registers 0 thru 31 are handled explicitly by
486 mips_register_name(). Processor specific registers 32 and above
487 are listed in the following tables. */
490 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
494 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
495 "sr", "lo", "hi", "bad", "cause", "pc",
496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
503 /* Names of IDT R3041 registers. */
505 static const char *mips_r3041_reg_names
[] = {
506 "sr", "lo", "hi", "bad", "cause", "pc",
507 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
508 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
509 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
510 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
511 "fsr", "fir", "", /*"fp" */ "",
512 "", "", "bus", "ccfg", "", "", "", "",
513 "", "", "port", "cmp", "", "", "epc", "prid",
516 /* Names of tx39 registers. */
518 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
519 "sr", "lo", "hi", "bad", "cause", "pc",
520 "", "", "", "", "", "", "", "",
521 "", "", "", "", "", "", "", "",
522 "", "", "", "", "", "", "", "",
523 "", "", "", "", "", "", "", "",
525 "", "", "", "", "", "", "", "",
526 "", "", "config", "cache", "debug", "depc", "epc",
529 /* Names of IRIX registers. */
530 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
531 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
532 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
533 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
534 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
535 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
538 /* Names of registers with Linux kernels. */
539 static const char *mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
540 "sr", "lo", "hi", "bad", "cause", "pc",
541 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
542 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
543 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
544 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
549 /* Return the name of the register corresponding to REGNO. */
551 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
553 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
554 /* GPR names for all ABIs other than n32/n64. */
555 static char *mips_gpr_names
[] = {
556 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
557 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
558 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
559 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
562 /* GPR names for n32 and n64 ABIs. */
563 static char *mips_n32_n64_gpr_names
[] = {
564 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
565 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
566 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
567 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
570 enum mips_abi abi
= mips_abi (gdbarch
);
572 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
573 but then don't make the raw register names visible. This (upper)
574 range of user visible register numbers are the pseudo-registers.
576 This approach was adopted accommodate the following scenario:
577 It is possible to debug a 64-bit device using a 32-bit
578 programming model. In such instances, the raw registers are
579 configured to be 64-bits wide, while the pseudo registers are
580 configured to be 32-bits wide. The registers that the user
581 sees - the pseudo registers - match the users expectations
582 given the programming model being used. */
583 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
584 if (regno
< gdbarch_num_regs (gdbarch
))
587 /* The MIPS integer registers are always mapped from 0 to 31. The
588 names of the registers (which reflects the conventions regarding
589 register use) vary depending on the ABI. */
590 if (0 <= rawnum
&& rawnum
< 32)
592 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
593 return mips_n32_n64_gpr_names
[rawnum
];
595 return mips_gpr_names
[rawnum
];
597 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
598 return tdesc_register_name (gdbarch
, rawnum
);
599 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
601 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
602 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
603 return tdep
->mips_processor_reg_names
[rawnum
- 32];
607 internal_error (__FILE__
, __LINE__
,
608 _("mips_register_name: bad register number %d"), rawnum
);
611 /* Return the groups that a MIPS register can be categorised into. */
614 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
615 struct reggroup
*reggroup
)
620 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
621 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
622 if (reggroup
== all_reggroup
)
624 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
625 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
626 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
627 (gdbarch), as not all architectures are multi-arch. */
628 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
629 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
630 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
632 if (reggroup
== float_reggroup
)
633 return float_p
&& pseudo
;
634 if (reggroup
== vector_reggroup
)
635 return vector_p
&& pseudo
;
636 if (reggroup
== general_reggroup
)
637 return (!vector_p
&& !float_p
) && pseudo
;
638 /* Save the pseudo registers. Need to make certain that any code
639 extracting register values from a saved register cache also uses
641 if (reggroup
== save_reggroup
)
642 return raw_p
&& pseudo
;
643 /* Restore the same pseudo register. */
644 if (reggroup
== restore_reggroup
)
645 return raw_p
&& pseudo
;
649 /* Return the groups that a MIPS register can be categorised into.
650 This version is only used if we have a target description which
651 describes real registers (and their groups). */
654 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
655 struct reggroup
*reggroup
)
657 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
658 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
661 /* Only save, restore, and display the pseudo registers. Need to
662 make certain that any code extracting register values from a
663 saved register cache also uses pseudo registers.
665 Note: saving and restoring the pseudo registers is slightly
666 strange; if we have 64 bits, we should save and restore all
667 64 bits. But this is hard and has little benefit. */
671 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
675 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
678 /* Map the symbol table registers which live in the range [1 *
679 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
680 registers. Take care of alignment and size problems. */
682 static enum register_status
683 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
684 int cookednum
, gdb_byte
*buf
)
686 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
687 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
688 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
689 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
690 return regcache_raw_read (regcache
, rawnum
, buf
);
691 else if (register_size (gdbarch
, rawnum
) >
692 register_size (gdbarch
, cookednum
))
694 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
695 return regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
698 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
700 enum register_status status
;
702 status
= regcache_raw_read_signed (regcache
, rawnum
, ®val
);
703 if (status
== REG_VALID
)
704 store_signed_integer (buf
, 4, byte_order
, regval
);
709 internal_error (__FILE__
, __LINE__
, _("bad register size"));
713 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
714 struct regcache
*regcache
, int cookednum
,
717 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
718 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
719 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
720 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
721 regcache_raw_write (regcache
, rawnum
, buf
);
722 else if (register_size (gdbarch
, rawnum
) >
723 register_size (gdbarch
, cookednum
))
725 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
726 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
729 /* Sign extend the shortened version of the register prior
730 to placing it in the raw register. This is required for
731 some mips64 parts in order to avoid unpredictable behavior. */
732 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
733 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
734 regcache_raw_write_signed (regcache
, rawnum
, regval
);
738 internal_error (__FILE__
, __LINE__
, _("bad register size"));
742 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
743 struct agent_expr
*ax
, int reg
)
745 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
746 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
747 && reg
< 2 * gdbarch_num_regs (gdbarch
));
749 ax_reg_mask (ax
, rawnum
);
755 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
756 struct agent_expr
*ax
, int reg
)
758 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
759 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
760 && reg
< 2 * gdbarch_num_regs (gdbarch
));
761 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
765 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
767 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
768 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
771 ax_simple (ax
, aop_lsh
);
774 ax_simple (ax
, aop_rsh_signed
);
778 internal_error (__FILE__
, __LINE__
, _("bad register size"));
783 /* Table to translate 3-bit register field to actual register number. */
784 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
786 /* Heuristic_proc_start may hunt through the text section for a long
787 time across a 2400 baud serial line. Allows the user to limit this
790 static unsigned int heuristic_fence_post
= 0;
792 /* Number of bytes of storage in the actual machine representation for
793 register N. NOTE: This defines the pseudo register type so need to
794 rebuild the architecture vector. */
796 static int mips64_transfers_32bit_regs_p
= 0;
799 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
800 struct cmd_list_element
*c
)
802 struct gdbarch_info info
;
803 gdbarch_info_init (&info
);
804 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
805 instead of relying on globals. Doing that would let generic code
806 handle the search for this specific architecture. */
807 if (!gdbarch_update_p (info
))
809 mips64_transfers_32bit_regs_p
= 0;
810 error (_("32-bit compatibility mode not supported"));
814 /* Convert to/from a register and the corresponding memory value. */
816 /* This predicate tests for the case of an 8 byte floating point
817 value that is being transferred to or from a pair of floating point
818 registers each of which are (or are considered to be) only 4 bytes
821 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
824 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
825 && register_size (gdbarch
, regnum
) == 4
826 && mips_float_register_p (gdbarch
, regnum
)
827 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
830 /* This predicate tests for the case of a value of less than 8
831 bytes in width that is being transfered to or from an 8 byte
832 general purpose register. */
834 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
837 int num_regs
= gdbarch_num_regs (gdbarch
);
839 return (register_size (gdbarch
, regnum
) == 8
840 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
841 && TYPE_LENGTH (type
) < 8);
845 mips_convert_register_p (struct gdbarch
*gdbarch
,
846 int regnum
, struct type
*type
)
848 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
849 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
853 mips_register_to_value (struct frame_info
*frame
, int regnum
,
854 struct type
*type
, gdb_byte
*to
,
855 int *optimizedp
, int *unavailablep
)
857 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
859 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
861 get_frame_register (frame
, regnum
+ 0, to
+ 4);
862 get_frame_register (frame
, regnum
+ 1, to
+ 0);
864 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, 4, to
+ 4,
865 optimizedp
, unavailablep
))
868 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, 4, to
+ 0,
869 optimizedp
, unavailablep
))
871 *optimizedp
= *unavailablep
= 0;
874 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
876 int len
= TYPE_LENGTH (type
);
879 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
880 if (!get_frame_register_bytes (frame
, regnum
, offset
, len
, to
,
881 optimizedp
, unavailablep
))
884 *optimizedp
= *unavailablep
= 0;
889 internal_error (__FILE__
, __LINE__
,
890 _("mips_register_to_value: unrecognized case"));
895 mips_value_to_register (struct frame_info
*frame
, int regnum
,
896 struct type
*type
, const gdb_byte
*from
)
898 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
900 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
902 put_frame_register (frame
, regnum
+ 0, from
+ 4);
903 put_frame_register (frame
, regnum
+ 1, from
+ 0);
905 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
908 int len
= TYPE_LENGTH (type
);
910 /* Sign extend values, irrespective of type, that are stored to
911 a 64-bit general purpose register. (32-bit unsigned values
912 are stored as signed quantities within a 64-bit register.
913 When performing an operation, in compiled code, that combines
914 a 32-bit unsigned value with a signed 64-bit value, a type
915 conversion is first performed that zeroes out the high 32 bits.) */
916 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
919 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
921 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
922 put_frame_register_bytes (frame
, regnum
, 0, 8 - len
, fill
);
923 put_frame_register_bytes (frame
, regnum
, 8 - len
, len
, from
);
927 if (from
[len
-1] & 0x80)
928 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
930 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
931 put_frame_register_bytes (frame
, regnum
, 0, len
, from
);
932 put_frame_register_bytes (frame
, regnum
, len
, 8 - len
, fill
);
937 internal_error (__FILE__
, __LINE__
,
938 _("mips_value_to_register: unrecognized case"));
942 /* Return the GDB type object for the "standard" data type of data in
946 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
948 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
949 if (mips_float_register_p (gdbarch
, regnum
))
951 /* The floating-point registers raw, or cooked, always match
952 mips_isa_regsize(), and also map 1:1, byte for byte. */
953 if (mips_isa_regsize (gdbarch
) == 4)
954 return builtin_type (gdbarch
)->builtin_float
;
956 return builtin_type (gdbarch
)->builtin_double
;
958 else if (regnum
< gdbarch_num_regs (gdbarch
))
960 /* The raw or ISA registers. These are all sized according to
962 if (mips_isa_regsize (gdbarch
) == 4)
963 return builtin_type (gdbarch
)->builtin_int32
;
965 return builtin_type (gdbarch
)->builtin_int64
;
969 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
971 /* The cooked or ABI registers. These are sized according to
972 the ABI (with a few complications). */
973 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
974 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
975 return builtin_type (gdbarch
)->builtin_int32
;
976 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
977 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
978 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
979 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
980 /* The pseudo/cooked view of the embedded registers is always
981 32-bit. The raw view is handled below. */
982 return builtin_type (gdbarch
)->builtin_int32
;
983 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
984 /* The target, while possibly using a 64-bit register buffer,
985 is only transfering 32-bits of each integer register.
986 Reflect this in the cooked/pseudo (ABI) register value. */
987 return builtin_type (gdbarch
)->builtin_int32
;
988 else if (mips_abi_regsize (gdbarch
) == 4)
989 /* The ABI is restricted to 32-bit registers (the ISA could be
991 return builtin_type (gdbarch
)->builtin_int32
;
994 return builtin_type (gdbarch
)->builtin_int64
;
998 /* Return the GDB type for the pseudo register REGNUM, which is the
999 ABI-level view. This function is only called if there is a target
1000 description which includes registers, so we know precisely the
1001 types of hardware registers. */
1003 static struct type
*
1004 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1006 const int num_regs
= gdbarch_num_regs (gdbarch
);
1007 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1008 int rawnum
= regnum
% num_regs
;
1009 struct type
*rawtype
;
1011 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1013 /* Absent registers are still absent. */
1014 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1015 if (TYPE_LENGTH (rawtype
) == 0)
1018 if (mips_float_register_p (gdbarch
, rawnum
))
1019 /* Present the floating point registers however the hardware did;
1020 do not try to convert between FPU layouts. */
1023 /* Use pointer types for registers if we can. For n32 we can not,
1024 since we do not have a 64-bit pointer type. */
1025 if (mips_abi_regsize (gdbarch
)
1026 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1028 if (rawnum
== MIPS_SP_REGNUM
1029 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1030 return builtin_type (gdbarch
)->builtin_data_ptr
;
1031 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1032 return builtin_type (gdbarch
)->builtin_func_ptr
;
1035 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1036 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1037 || rawnum
== mips_regnum (gdbarch
)->lo
1038 || rawnum
== mips_regnum (gdbarch
)->hi
1039 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1040 || rawnum
== mips_regnum (gdbarch
)->cause
1041 || rawnum
== mips_regnum (gdbarch
)->pc
1042 || (mips_regnum (gdbarch
)->dspacc
!= -1
1043 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1044 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1045 return builtin_type (gdbarch
)->builtin_int32
;
1047 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_IRIX
1048 && gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1049 && rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32
1050 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1052 /* The pseudo/cooked view of embedded registers is always
1053 32-bit, even if the target transfers 64-bit values for them.
1054 New targets relying on XML descriptions should only transfer
1055 the necessary 32 bits, but older versions of GDB expected 64,
1056 so allow the target to provide 64 bits without interfering
1057 with the displayed type. */
1058 return builtin_type (gdbarch
)->builtin_int32
;
1061 /* For all other registers, pass through the hardware type. */
1065 /* Should the upper word of 64-bit addresses be zeroed? */
1066 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1069 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1071 switch (mask_address_var
)
1073 case AUTO_BOOLEAN_TRUE
:
1075 case AUTO_BOOLEAN_FALSE
:
1078 case AUTO_BOOLEAN_AUTO
:
1079 return tdep
->default_mask_address_p
;
1081 internal_error (__FILE__
, __LINE__
,
1082 _("mips_mask_address_p: bad switch"));
1088 show_mask_address (struct ui_file
*file
, int from_tty
,
1089 struct cmd_list_element
*c
, const char *value
)
1091 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
1093 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1094 switch (mask_address_var
)
1096 case AUTO_BOOLEAN_TRUE
:
1097 printf_filtered ("The 32 bit mips address mask is enabled\n");
1099 case AUTO_BOOLEAN_FALSE
:
1100 printf_filtered ("The 32 bit mips address mask is disabled\n");
1102 case AUTO_BOOLEAN_AUTO
:
1104 ("The 32 bit address mask is set automatically. Currently %s\n",
1105 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1108 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1113 /* Tell if the program counter value in MEMADDR is in a standard ISA
1117 mips_pc_is_mips (CORE_ADDR memaddr
)
1119 struct minimal_symbol
*sym
;
1121 /* Flags indicating that this is a MIPS16 or microMIPS function is
1122 stored by elfread.c in the high bit of the info field. Use this
1123 to decide if the function is standard MIPS. Otherwise if bit 0
1124 of the address is clear, then this is a standard MIPS function. */
1125 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1127 return msymbol_is_mips (sym
);
1129 return is_mips_addr (memaddr
);
1132 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1135 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1137 struct minimal_symbol
*sym
;
1139 /* A flag indicating that this is a MIPS16 function is stored by
1140 elfread.c in the high bit of the info field. Use this to decide
1141 if the function is MIPS16. Otherwise if bit 0 of the address is
1142 set, then ELF file flags will tell if this is a MIPS16 function. */
1143 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1145 return msymbol_is_mips16 (sym
);
1147 return is_mips16_addr (gdbarch
, memaddr
);
1150 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1153 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1155 struct minimal_symbol
*sym
;
1157 /* A flag indicating that this is a microMIPS function is stored by
1158 elfread.c in the high bit of the info field. Use this to decide
1159 if the function is microMIPS. Otherwise if bit 0 of the address
1160 is set, then ELF file flags will tell if this is a microMIPS
1162 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1164 return msymbol_is_micromips (sym
);
1166 return is_micromips_addr (gdbarch
, memaddr
);
1169 /* Tell the ISA type of the function the program counter value in MEMADDR
1172 static enum mips_isa
1173 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1175 struct minimal_symbol
*sym
;
1177 /* A flag indicating that this is a MIPS16 or a microMIPS function
1178 is stored by elfread.c in the high bit of the info field. Use
1179 this to decide if the function is MIPS16 or microMIPS or normal
1180 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1181 flags will tell if this is a MIPS16 or a microMIPS function. */
1182 sym
= lookup_minimal_symbol_by_pc (memaddr
);
1185 if (msymbol_is_micromips (sym
))
1186 return ISA_MICROMIPS
;
1187 else if (msymbol_is_mips16 (sym
))
1194 if (is_mips_addr (memaddr
))
1196 else if (is_micromips_addr (gdbarch
, memaddr
))
1197 return ISA_MICROMIPS
;
1203 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1205 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1206 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1207 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1208 static const char mips_str_call_stub
[] = "__call_stub_";
1209 static const char mips_str_fn_stub
[] = "__fn_stub_";
1211 /* This is used as a PIC thunk prefix. */
1213 static const char mips_str_pic
[] = ".pic.";
1215 /* Return non-zero if the PC is inside a call thunk (aka stub or
1216 trampoline) that should be treated as a temporary frame. */
1219 mips_in_frame_stub (CORE_ADDR pc
)
1221 CORE_ADDR start_addr
;
1224 /* Find the starting address of the function containing the PC. */
1225 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1228 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1229 if (strncmp (name
, mips_str_mips16_call_stub
,
1230 strlen (mips_str_mips16_call_stub
)) == 0)
1232 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1233 if (strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
1235 /* If the PC is in __fn_stub_*, this is a call stub. */
1236 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0)
1239 return 0; /* Not a stub. */
1242 /* MIPS believes that the PC has a sign extended value. Perhaps the
1243 all registers should be sign extended for simplicity? */
1246 mips_read_pc (struct regcache
*regcache
)
1248 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1251 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
1252 if (is_compact_addr (pc
))
1253 pc
= unmake_compact_addr (pc
);
1258 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1262 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1263 if (is_compact_addr (pc
))
1264 pc
= unmake_compact_addr (pc
);
1265 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1266 intermediate frames. In this case we can get the caller's address
1267 from $ra, or if $ra contains an address within a thunk as well, then
1268 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1269 and thus the caller's address is in $s2. */
1270 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1272 pc
= frame_unwind_register_signed
1273 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1274 if (is_compact_addr (pc
))
1275 pc
= unmake_compact_addr (pc
);
1276 if (mips_in_frame_stub (pc
))
1278 pc
= frame_unwind_register_signed
1279 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1280 if (is_compact_addr (pc
))
1281 pc
= unmake_compact_addr (pc
);
1288 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1290 return frame_unwind_register_signed
1291 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1294 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1295 dummy frame. The frame ID's base needs to match the TOS value
1296 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1299 static struct frame_id
1300 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1302 return frame_id_build
1303 (get_frame_register_signed (this_frame
,
1304 gdbarch_num_regs (gdbarch
)
1306 get_frame_pc (this_frame
));
1309 /* Implement the "write_pc" gdbarch method. */
1312 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1314 int regnum
= gdbarch_pc_regnum (get_regcache_arch (regcache
));
1316 if (mips_pc_is_mips (pc
))
1317 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1319 regcache_cooked_write_unsigned (regcache
, regnum
, make_compact_addr (pc
));
1322 /* Fetch and return instruction from the specified location. Handle
1323 MIPS16/microMIPS as appropriate. */
1326 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1327 enum mips_isa isa
, CORE_ADDR addr
, int *statusp
)
1329 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1330 gdb_byte buf
[MIPS_INSN32_SIZE
];
1338 instlen
= MIPS_INSN16_SIZE
;
1339 addr
= unmake_compact_addr (addr
);
1342 instlen
= MIPS_INSN32_SIZE
;
1345 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1348 status
= target_read_memory (addr
, buf
, instlen
);
1349 if (statusp
!= NULL
)
1353 if (statusp
== NULL
)
1354 memory_error (status
, addr
);
1357 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1360 /* These are the fields of 32 bit mips instructions. */
1361 #define mips32_op(x) (x >> 26)
1362 #define itype_op(x) (x >> 26)
1363 #define itype_rs(x) ((x >> 21) & 0x1f)
1364 #define itype_rt(x) ((x >> 16) & 0x1f)
1365 #define itype_immediate(x) (x & 0xffff)
1367 #define jtype_op(x) (x >> 26)
1368 #define jtype_target(x) (x & 0x03ffffff)
1370 #define rtype_op(x) (x >> 26)
1371 #define rtype_rs(x) ((x >> 21) & 0x1f)
1372 #define rtype_rt(x) ((x >> 16) & 0x1f)
1373 #define rtype_rd(x) ((x >> 11) & 0x1f)
1374 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1375 #define rtype_funct(x) (x & 0x3f)
1377 /* MicroMIPS instruction fields. */
1378 #define micromips_op(x) ((x) >> 10)
1380 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1381 bit and the size respectively of the field extracted. */
1382 #define b0s4_imm(x) ((x) & 0xf)
1383 #define b0s5_imm(x) ((x) & 0x1f)
1384 #define b0s5_reg(x) ((x) & 0x1f)
1385 #define b0s7_imm(x) ((x) & 0x7f)
1386 #define b0s10_imm(x) ((x) & 0x3ff)
1387 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1388 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1389 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1390 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1391 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1392 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1393 #define b6s4_op(x) (((x) >> 6) & 0xf)
1394 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1396 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1397 respectively of the field extracted. */
1398 #define b0s6_op(x) ((x) & 0x3f)
1399 #define b0s11_op(x) ((x) & 0x7ff)
1400 #define b0s12_imm(x) ((x) & 0xfff)
1401 #define b0s16_imm(x) ((x) & 0xffff)
1402 #define b0s26_imm(x) ((x) & 0x3ffffff)
1403 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1404 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1405 #define b12s4_op(x) (((x) >> 12) & 0xf)
1407 /* Return the size in bytes of the instruction INSN encoded in the ISA
1411 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1416 if (micromips_op (insn
) == 0x1f)
1417 return 3 * MIPS_INSN16_SIZE
;
1418 else if (((micromips_op (insn
) & 0x4) == 0x4)
1419 || ((micromips_op (insn
) & 0x7) == 0x0))
1420 return 2 * MIPS_INSN16_SIZE
;
1422 return MIPS_INSN16_SIZE
;
1424 if ((insn
& 0xf800) == 0xf000)
1425 return 2 * MIPS_INSN16_SIZE
;
1427 return MIPS_INSN16_SIZE
;
1429 return MIPS_INSN32_SIZE
;
1431 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1435 mips32_relative_offset (ULONGEST inst
)
1437 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1440 /* Determine the address of the next instruction executed after the INST
1441 floating condition branch instruction at PC. COUNT specifies the
1442 number of the floating condition bits tested by the branch. */
1445 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1446 ULONGEST inst
, CORE_ADDR pc
, int count
)
1448 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1449 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1450 int tf
= itype_rt (inst
) & 1;
1451 int mask
= (1 << count
) - 1;
1456 /* No way to handle; it'll most likely trap anyway. */
1459 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1460 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1462 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1463 pc
+= mips32_relative_offset (inst
);
1470 /* Determine where to set a single step breakpoint while considering
1471 branch prediction. */
1473 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1475 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1478 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1479 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1482 if (itype_op (inst
) >> 2 == 5)
1483 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1485 op
= (itype_op (inst
) & 0x03);
1495 goto greater_branch
;
1500 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1501 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1502 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 1);
1503 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 9
1504 && (itype_rt (inst
) & 2) == 0)
1505 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1506 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 2);
1507 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 10
1508 && (itype_rt (inst
) & 2) == 0)
1509 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1510 pc
= mips32_bc1_pc (gdbarch
, frame
, inst
, pc
+ 4, 4);
1511 else if (itype_op (inst
) == 29)
1513 /* The new PC will be alternate mode. */
1517 reg
= jtype_target (inst
) << 2;
1518 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1519 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1522 pc
+= 4; /* Not a branch, next instruction is easy. */
1525 { /* This gets way messy. */
1527 /* Further subdivide into SPECIAL, REGIMM and other. */
1528 switch (op
= itype_op (inst
) & 0x07) /* Extract bits 28,27,26. */
1530 case 0: /* SPECIAL */
1531 op
= rtype_funct (inst
);
1536 /* Set PC to that address. */
1537 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1539 case 12: /* SYSCALL */
1541 struct gdbarch_tdep
*tdep
;
1543 tdep
= gdbarch_tdep (get_frame_arch (frame
));
1544 if (tdep
->syscall_next_pc
!= NULL
)
1545 pc
= tdep
->syscall_next_pc (frame
);
1554 break; /* end SPECIAL */
1555 case 1: /* REGIMM */
1557 op
= itype_rt (inst
); /* branch condition */
1562 case 16: /* BLTZAL */
1563 case 18: /* BLTZALL */
1565 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1566 pc
+= mips32_relative_offset (inst
) + 4;
1568 pc
+= 8; /* after the delay slot */
1572 case 17: /* BGEZAL */
1573 case 19: /* BGEZALL */
1574 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1575 pc
+= mips32_relative_offset (inst
) + 4;
1577 pc
+= 8; /* after the delay slot */
1579 case 0x1c: /* BPOSGE32 */
1580 case 0x1e: /* BPOSGE64 */
1582 if (itype_rs (inst
) == 0)
1584 unsigned int pos
= (op
& 2) ? 64 : 32;
1585 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1588 /* No way to handle; it'll most likely trap anyway. */
1591 if ((get_frame_register_unsigned (frame
,
1592 dspctl
) & 0x7f) >= pos
)
1593 pc
+= mips32_relative_offset (inst
);
1598 /* All of the other instructions in the REGIMM category */
1603 break; /* end REGIMM */
1608 reg
= jtype_target (inst
) << 2;
1609 /* Upper four bits get never changed... */
1610 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1613 case 4: /* BEQ, BEQL */
1615 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1616 get_frame_register_signed (frame
, itype_rt (inst
)))
1617 pc
+= mips32_relative_offset (inst
) + 4;
1621 case 5: /* BNE, BNEL */
1623 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1624 get_frame_register_signed (frame
, itype_rt (inst
)))
1625 pc
+= mips32_relative_offset (inst
) + 4;
1629 case 6: /* BLEZ, BLEZL */
1630 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1631 pc
+= mips32_relative_offset (inst
) + 4;
1637 greater_branch
: /* BGTZ, BGTZL */
1638 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1639 pc
+= mips32_relative_offset (inst
) + 4;
1646 } /* mips32_next_pc */
1648 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1652 micromips_relative_offset7 (ULONGEST insn
)
1654 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1657 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1661 micromips_relative_offset10 (ULONGEST insn
)
1663 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1666 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1670 micromips_relative_offset16 (ULONGEST insn
)
1672 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1675 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1678 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1682 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1683 return mips_insn_size (ISA_MICROMIPS
, insn
);
1686 /* Calculate the address of the next microMIPS instruction to execute
1687 after the INSN coprocessor 1 conditional branch instruction at the
1688 address PC. COUNT denotes the number of coprocessor condition bits
1689 examined by the branch. */
1692 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct frame_info
*frame
,
1693 ULONGEST insn
, CORE_ADDR pc
, int count
)
1695 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1696 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1697 int tf
= b5s5_op (insn
>> 16) & 1;
1698 int mask
= (1 << count
) - 1;
1703 /* No way to handle; it'll most likely trap anyway. */
1706 fcs
= get_frame_register_unsigned (frame
, fcsr
);
1707 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1709 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1710 pc
+= micromips_relative_offset16 (insn
);
1712 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1717 /* Calculate the address of the next microMIPS instruction to execute
1718 after the instruction at the address PC. */
1721 micromips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1723 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1726 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1727 pc
+= MIPS_INSN16_SIZE
;
1728 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1730 /* 48-bit instructions. */
1731 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
1732 /* No branch or jump instructions in this category. */
1733 pc
+= 2 * MIPS_INSN16_SIZE
;
1736 /* 32-bit instructions. */
1737 case 2 * MIPS_INSN16_SIZE
:
1739 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1740 pc
+= MIPS_INSN16_SIZE
;
1741 switch (micromips_op (insn
>> 16))
1743 case 0x00: /* POOL32A: bits 000000 */
1744 if (b0s6_op (insn
) == 0x3c
1745 /* POOL32Axf: bits 000000 ... 111100 */
1746 && (b6s10_ext (insn
) & 0x2bf) == 0x3c)
1747 /* JALR, JALR.HB: 000000 000x111100 111100 */
1748 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
1749 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
>> 16));
1752 case 0x10: /* POOL32I: bits 010000 */
1753 switch (b5s5_op (insn
>> 16))
1755 case 0x00: /* BLTZ: bits 010000 00000 */
1756 case 0x01: /* BLTZAL: bits 010000 00001 */
1757 case 0x11: /* BLTZALS: bits 010000 10001 */
1758 if (get_frame_register_signed (frame
,
1759 b0s5_reg (insn
>> 16)) < 0)
1760 pc
+= micromips_relative_offset16 (insn
);
1762 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1765 case 0x02: /* BGEZ: bits 010000 00010 */
1766 case 0x03: /* BGEZAL: bits 010000 00011 */
1767 case 0x13: /* BGEZALS: bits 010000 10011 */
1768 if (get_frame_register_signed (frame
,
1769 b0s5_reg (insn
>> 16)) >= 0)
1770 pc
+= micromips_relative_offset16 (insn
);
1772 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1775 case 0x04: /* BLEZ: bits 010000 00100 */
1776 if (get_frame_register_signed (frame
,
1777 b0s5_reg (insn
>> 16)) <= 0)
1778 pc
+= micromips_relative_offset16 (insn
);
1780 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1783 case 0x05: /* BNEZC: bits 010000 00101 */
1784 if (get_frame_register_signed (frame
,
1785 b0s5_reg (insn
>> 16)) != 0)
1786 pc
+= micromips_relative_offset16 (insn
);
1789 case 0x06: /* BGTZ: bits 010000 00110 */
1790 if (get_frame_register_signed (frame
,
1791 b0s5_reg (insn
>> 16)) > 0)
1792 pc
+= micromips_relative_offset16 (insn
);
1794 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1797 case 0x07: /* BEQZC: bits 010000 00111 */
1798 if (get_frame_register_signed (frame
,
1799 b0s5_reg (insn
>> 16)) == 0)
1800 pc
+= micromips_relative_offset16 (insn
);
1803 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1804 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1805 if (((insn
>> 16) & 0x3) == 0x0)
1806 /* BC2F, BC2T: don't know how to handle these. */
1810 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1811 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1813 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1814 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1817 /* No way to handle; it'll most likely trap anyway. */
1820 if ((get_frame_register_unsigned (frame
,
1821 dspctl
) & 0x7f) >= pos
)
1822 pc
+= micromips_relative_offset16 (insn
);
1824 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1828 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
1829 /* BC1ANY2F: bits 010000 11100 xxx01 */
1830 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
1831 /* BC1ANY2T: bits 010000 11101 xxx01 */
1832 if (((insn
>> 16) & 0x2) == 0x0)
1833 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
,
1834 ((insn
>> 16) & 0x1) + 1);
1837 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
1838 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
1839 if (((insn
>> 16) & 0x3) == 0x1)
1840 pc
= micromips_bc1_pc (gdbarch
, frame
, insn
, pc
, 4);
1845 case 0x1d: /* JALS: bits 011101 */
1846 case 0x35: /* J: bits 110101 */
1847 case 0x3d: /* JAL: bits 111101 */
1848 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
1851 case 0x25: /* BEQ: bits 100101 */
1852 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1853 == get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1854 pc
+= micromips_relative_offset16 (insn
);
1856 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1859 case 0x2d: /* BNE: bits 101101 */
1860 if (get_frame_register_signed (frame
, b0s5_reg (insn
>> 16))
1861 != get_frame_register_signed (frame
, b5s5_reg (insn
>> 16)))
1862 pc
+= micromips_relative_offset16 (insn
);
1864 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1867 case 0x3c: /* JALX: bits 111100 */
1868 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
1873 /* 16-bit instructions. */
1874 case MIPS_INSN16_SIZE
:
1875 switch (micromips_op (insn
))
1877 case 0x11: /* POOL16C: bits 010001 */
1878 if ((b5s5_op (insn
) & 0x1c) == 0xc)
1879 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
1880 pc
= get_frame_register_signed (frame
, b0s5_reg (insn
));
1881 else if (b5s5_op (insn
) == 0x18)
1882 /* JRADDIUSP: bits 010001 11000 */
1883 pc
= get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
1886 case 0x23: /* BEQZ16: bits 100011 */
1888 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1890 if (get_frame_register_signed (frame
, rs
) == 0)
1891 pc
+= micromips_relative_offset7 (insn
);
1893 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1897 case 0x2b: /* BNEZ16: bits 101011 */
1899 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
1901 if (get_frame_register_signed (frame
, rs
) != 0)
1902 pc
+= micromips_relative_offset7 (insn
);
1904 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1908 case 0x33: /* B16: bits 110011 */
1909 pc
+= micromips_relative_offset10 (insn
);
1918 /* Decoding the next place to set a breakpoint is irregular for the
1919 mips 16 variant, but fortunately, there fewer instructions. We have
1920 to cope ith extensions for 16 bit instructions and a pair of actual
1921 32 bit instructions. We dont want to set a single step instruction
1922 on the extend instruction either. */
1924 /* Lots of mips16 instruction formats */
1925 /* Predicting jumps requires itype,ritype,i8type
1926 and their extensions extItype,extritype,extI8type. */
1927 enum mips16_inst_fmts
1929 itype
, /* 0 immediate 5,10 */
1930 ritype
, /* 1 5,3,8 */
1931 rrtype
, /* 2 5,3,3,5 */
1932 rritype
, /* 3 5,3,3,5 */
1933 rrrtype
, /* 4 5,3,3,3,2 */
1934 rriatype
, /* 5 5,3,3,1,4 */
1935 shifttype
, /* 6 5,3,3,3,2 */
1936 i8type
, /* 7 5,3,8 */
1937 i8movtype
, /* 8 5,3,3,5 */
1938 i8mov32rtype
, /* 9 5,3,5,3 */
1939 i64type
, /* 10 5,3,8 */
1940 ri64type
, /* 11 5,3,3,5 */
1941 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1942 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1943 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1944 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1945 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1946 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1947 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1948 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1949 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1950 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1952 /* I am heaping all the fields of the formats into one structure and
1953 then, only the fields which are involved in instruction extension. */
1957 unsigned int regx
; /* Function in i8 type. */
1962 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1963 for the bits which make up the immediate extension. */
1966 extended_offset (unsigned int extension
)
1970 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
1972 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
1974 value
|= extension
& 0x1f; /* Extract 4:0. */
1979 /* Only call this function if you know that this is an extendable
1980 instruction. It won't malfunction, but why make excess remote memory
1981 references? If the immediate operands get sign extended or something,
1982 do it after the extension is performed. */
1983 /* FIXME: Every one of these cases needs to worry about sign extension
1984 when the offset is to be used in relative addressing. */
1987 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1989 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1991 pc
&= 0xfffffffe; /* Clear the low order bit. */
1992 target_read_memory (pc
, buf
, 2);
1993 return extract_unsigned_integer (buf
, 2, byte_order
);
1997 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
1998 unsigned int extension
,
2000 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2005 switch (insn_format
)
2012 value
= extended_offset ((extension
<< 16) | inst
);
2013 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2017 value
= inst
& 0x7ff;
2018 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2027 { /* A register identifier and an offset. */
2028 /* Most of the fields are the same as I type but the
2029 immediate value is of a different length. */
2033 value
= extended_offset ((extension
<< 16) | inst
);
2034 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2038 value
= inst
& 0xff; /* 8 bits */
2039 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2042 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2048 unsigned long value
;
2049 unsigned int nexthalf
;
2050 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2051 value
= value
<< 16;
2052 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2053 /* Low bit still set. */
2061 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2063 upk
->offset
= offset
;
2070 add_offset_16 (CORE_ADDR pc
, int offset
)
2072 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
2076 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
2077 unsigned int extension
, unsigned int insn
)
2079 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2080 int op
= (insn
>> 11);
2083 case 2: /* Branch */
2085 struct upk_mips16 upk
;
2086 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2087 pc
+= (upk
.offset
<< 1) + 2;
2090 case 3: /* JAL , JALX - Watch out, these are 32 bit
2093 struct upk_mips16 upk
;
2094 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2095 pc
= add_offset_16 (pc
, upk
.offset
);
2096 if ((insn
>> 10) & 0x01) /* Exchange mode */
2097 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2104 struct upk_mips16 upk
;
2106 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2107 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2109 pc
+= (upk
.offset
<< 1) + 2;
2116 struct upk_mips16 upk
;
2118 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2119 reg
= get_frame_register_signed (frame
, mips_reg3_to_reg
[upk
.regx
]);
2121 pc
+= (upk
.offset
<< 1) + 2;
2126 case 12: /* I8 Formats btez btnez */
2128 struct upk_mips16 upk
;
2130 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2131 /* upk.regx contains the opcode */
2132 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
2133 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2134 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2135 /* pc = add_offset_16(pc,upk.offset) ; */
2136 pc
+= (upk
.offset
<< 1) + 2;
2141 case 29: /* RR Formats JR, JALR, JALR-RA */
2143 struct upk_mips16 upk
;
2144 /* upk.fmt = rrtype; */
2149 upk
.regx
= (insn
>> 8) & 0x07;
2150 upk
.regy
= (insn
>> 5) & 0x07;
2151 if ((upk
.regy
& 1) == 0)
2152 reg
= mips_reg3_to_reg
[upk
.regx
];
2154 reg
= 31; /* Function return instruction. */
2155 pc
= get_frame_register_signed (frame
, reg
);
2162 /* This is an instruction extension. Fetch the real instruction
2163 (which follows the extension) and decode things based on
2167 pc
= extended_mips16_next_pc (frame
, pc
, insn
,
2168 fetch_mips_16 (gdbarch
, pc
));
2181 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2183 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2184 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2185 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
2188 /* The mips_next_pc function supports single_step when the remote
2189 target monitor or stub is not developed enough to do a single_step.
2190 It works by decoding the current instruction and predicting where a
2191 branch will go. This isnt hard because all the data is available.
2192 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2194 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2196 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2198 if (mips_pc_is_mips16 (gdbarch
, pc
))
2199 return mips16_next_pc (frame
, pc
);
2200 else if (mips_pc_is_micromips (gdbarch
, pc
))
2201 return micromips_next_pc (frame
, pc
);
2203 return mips32_next_pc (frame
, pc
);
2206 struct mips_frame_cache
2209 struct trad_frame_saved_reg
*saved_regs
;
2212 /* Set a register's saved stack address in temp_saved_regs. If an
2213 address has already been set for this register, do nothing; this
2214 way we will only recognize the first save of a given register in a
2217 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2218 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2219 Strictly speaking, only the second range is used as it is only second
2220 range (the ABI instead of ISA registers) that comes into play when finding
2221 saved registers in a frame. */
2224 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2225 int regnum
, CORE_ADDR offset
)
2227 if (this_cache
!= NULL
2228 && this_cache
->saved_regs
[regnum
].addr
== -1)
2230 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
2232 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
2238 /* Fetch the immediate value from a MIPS16 instruction.
2239 If the previous instruction was an EXTEND, use it to extend
2240 the upper bits of the immediate value. This is a helper function
2241 for mips16_scan_prologue. */
2244 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2245 unsigned short inst
, /* current instruction */
2246 int nbits
, /* number of bits in imm field */
2247 int scale
, /* scale factor to be applied to imm */
2248 int is_signed
) /* is the imm field signed? */
2252 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2254 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2255 if (offset
& 0x8000) /* check for negative extend */
2256 offset
= 0 - (0x10000 - (offset
& 0xffff));
2257 return offset
| (inst
& 0x1f);
2261 int max_imm
= 1 << nbits
;
2262 int mask
= max_imm
- 1;
2263 int sign_bit
= max_imm
>> 1;
2265 offset
= inst
& mask
;
2266 if (is_signed
&& (offset
& sign_bit
))
2267 offset
= 0 - (max_imm
- offset
);
2268 return offset
* scale
;
2273 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2274 the associated FRAME_CACHE if not null.
2275 Return the address of the first instruction past the prologue. */
2278 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2279 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2280 struct frame_info
*this_frame
,
2281 struct mips_frame_cache
*this_cache
)
2284 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2286 long frame_offset
= 0; /* Size of stack frame. */
2287 long frame_adjust
= 0; /* Offset of FP from SP. */
2288 int frame_reg
= MIPS_SP_REGNUM
;
2289 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2290 unsigned inst
= 0; /* current instruction */
2291 unsigned entry_inst
= 0; /* the entry instruction */
2292 unsigned save_inst
= 0; /* the save instruction */
2295 int extend_bytes
= 0;
2296 int prev_extend_bytes
;
2297 CORE_ADDR end_prologue_addr
= 0;
2299 /* Can be called when there's no process, and hence when there's no
2301 if (this_frame
!= NULL
)
2302 sp
= get_frame_register_signed (this_frame
,
2303 gdbarch_num_regs (gdbarch
)
2308 if (limit_pc
> start_pc
+ 200)
2309 limit_pc
= start_pc
+ 200;
2311 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2313 /* Save the previous instruction. If it's an EXTEND, we'll extract
2314 the immediate offset extension from it in mips16_get_imm. */
2317 /* Fetch and decode the instruction. */
2318 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2321 /* Normally we ignore extend instructions. However, if it is
2322 not followed by a valid prologue instruction, then this
2323 instruction is not part of the prologue either. We must
2324 remember in this case to adjust the end_prologue_addr back
2326 if ((inst
& 0xf800) == 0xf000) /* extend */
2328 extend_bytes
= MIPS_INSN16_SIZE
;
2332 prev_extend_bytes
= extend_bytes
;
2335 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2336 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2338 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2339 if (offset
< 0) /* Negative stack adjustment? */
2340 frame_offset
-= offset
;
2342 /* Exit loop if a positive stack adjustment is found, which
2343 usually means that the stack cleanup code in the function
2344 epilogue is reached. */
2347 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2349 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2350 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2351 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2353 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2355 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2356 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2357 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2359 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2361 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2362 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2364 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2366 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2367 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2369 else if (inst
== 0x673d) /* move $s1, $sp */
2374 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2376 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2377 frame_addr
= sp
+ offset
;
2379 frame_adjust
= offset
;
2381 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2383 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2384 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2385 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2387 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2389 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2390 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2391 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2393 else if ((inst
& 0xf81f) == 0xe809
2394 && (inst
& 0x700) != 0x700) /* entry */
2395 entry_inst
= inst
; /* Save for later processing. */
2396 else if ((inst
& 0xff80) == 0x6480) /* save */
2398 save_inst
= inst
; /* Save for later processing. */
2399 if (prev_extend_bytes
) /* extend */
2400 save_inst
|= prev_inst
<< 16;
2402 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
2403 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2404 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2406 /* This instruction is part of the prologue, but we don't
2407 need to do anything special to handle it. */
2411 /* This instruction is not an instruction typically found
2412 in a prologue, so we must have reached the end of the
2414 if (end_prologue_addr
== 0)
2415 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
2419 /* The entry instruction is typically the first instruction in a function,
2420 and it stores registers at offsets relative to the value of the old SP
2421 (before the prologue). But the value of the sp parameter to this
2422 function is the new SP (after the prologue has been executed). So we
2423 can't calculate those offsets until we've seen the entire prologue,
2424 and can calculate what the old SP must have been. */
2425 if (entry_inst
!= 0)
2427 int areg_count
= (entry_inst
>> 8) & 7;
2428 int sreg_count
= (entry_inst
>> 6) & 3;
2430 /* The entry instruction always subtracts 32 from the SP. */
2433 /* Now we can calculate what the SP must have been at the
2434 start of the function prologue. */
2437 /* Check if a0-a3 were saved in the caller's argument save area. */
2438 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2440 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2441 offset
+= mips_abi_regsize (gdbarch
);
2444 /* Check if the ra register was pushed on the stack. */
2446 if (entry_inst
& 0x20)
2448 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2449 offset
-= mips_abi_regsize (gdbarch
);
2452 /* Check if the s0 and s1 registers were pushed on the stack. */
2453 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2455 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2456 offset
-= mips_abi_regsize (gdbarch
);
2460 /* The SAVE instruction is similar to ENTRY, except that defined by the
2461 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2462 size of the frame is specified as an immediate field of instruction
2463 and an extended variation exists which lets additional registers and
2464 frame space to be specified. The instruction always treats registers
2465 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2466 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2468 static int args_table
[16] = {
2469 0, 0, 0, 0, 1, 1, 1, 1,
2470 2, 2, 2, 0, 3, 3, 4, -1,
2472 static int astatic_table
[16] = {
2473 0, 1, 2, 3, 0, 1, 2, 3,
2474 0, 1, 2, 4, 0, 1, 0, -1,
2476 int aregs
= (save_inst
>> 16) & 0xf;
2477 int xsregs
= (save_inst
>> 24) & 0x7;
2478 int args
= args_table
[aregs
];
2479 int astatic
= astatic_table
[aregs
];
2484 warning (_("Invalid number of argument registers encoded in SAVE."));
2489 warning (_("Invalid number of static registers encoded in SAVE."));
2493 /* For standard SAVE the frame size of 0 means 128. */
2494 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2495 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2498 frame_offset
+= frame_size
;
2500 /* Now we can calculate what the SP must have been at the
2501 start of the function prologue. */
2504 /* Check if A0-A3 were saved in the caller's argument save area. */
2505 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2507 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2508 offset
+= mips_abi_regsize (gdbarch
);
2513 /* Check if the RA register was pushed on the stack. */
2514 if (save_inst
& 0x40)
2516 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2517 offset
-= mips_abi_regsize (gdbarch
);
2520 /* Check if the S8 register was pushed on the stack. */
2523 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2524 offset
-= mips_abi_regsize (gdbarch
);
2527 /* Check if S2-S7 were pushed on the stack. */
2528 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2530 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2531 offset
-= mips_abi_regsize (gdbarch
);
2534 /* Check if the S1 register was pushed on the stack. */
2535 if (save_inst
& 0x10)
2537 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2538 offset
-= mips_abi_regsize (gdbarch
);
2540 /* Check if the S0 register was pushed on the stack. */
2541 if (save_inst
& 0x20)
2543 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2544 offset
-= mips_abi_regsize (gdbarch
);
2547 /* Check if A0-A3 were pushed on the stack. */
2548 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2550 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2551 offset
-= mips_abi_regsize (gdbarch
);
2555 if (this_cache
!= NULL
)
2558 (get_frame_register_signed (this_frame
,
2559 gdbarch_num_regs (gdbarch
) + frame_reg
)
2560 + frame_offset
- frame_adjust
);
2561 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2562 be able to get rid of the assignment below, evetually. But it's
2563 still needed for now. */
2564 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2565 + mips_regnum (gdbarch
)->pc
]
2566 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2569 /* If we didn't reach the end of the prologue when scanning the function
2570 instructions, then set end_prologue_addr to the address of the
2571 instruction immediately after the last one we scanned. */
2572 if (end_prologue_addr
== 0)
2573 end_prologue_addr
= cur_pc
;
2575 return end_prologue_addr
;
2578 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2579 Procedures that use the 32-bit instruction set are handled by the
2580 mips_insn32 unwinder. */
2582 static struct mips_frame_cache
*
2583 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2585 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2586 struct mips_frame_cache
*cache
;
2588 if ((*this_cache
) != NULL
)
2589 return (*this_cache
);
2590 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2591 (*this_cache
) = cache
;
2592 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2594 /* Analyze the function prologue. */
2596 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2597 CORE_ADDR start_addr
;
2599 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2600 if (start_addr
== 0)
2601 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2602 /* We can't analyze the prologue if we couldn't find the begining
2604 if (start_addr
== 0)
2607 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
2610 /* gdbarch_sp_regnum contains the value and not the address. */
2611 trad_frame_set_value (cache
->saved_regs
,
2612 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
2615 return (*this_cache
);
2619 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2620 struct frame_id
*this_id
)
2622 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2624 /* This marks the outermost frame. */
2625 if (info
->base
== 0)
2627 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2630 static struct value
*
2631 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2632 void **this_cache
, int regnum
)
2634 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2636 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2640 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2641 struct frame_info
*this_frame
, void **this_cache
)
2643 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2644 CORE_ADDR pc
= get_frame_pc (this_frame
);
2645 if (mips_pc_is_mips16 (gdbarch
, pc
))
2650 static const struct frame_unwind mips_insn16_frame_unwind
=
2653 default_frame_unwind_stop_reason
,
2654 mips_insn16_frame_this_id
,
2655 mips_insn16_frame_prev_register
,
2657 mips_insn16_frame_sniffer
2661 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2664 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2669 static const struct frame_base mips_insn16_frame_base
=
2671 &mips_insn16_frame_unwind
,
2672 mips_insn16_frame_base_address
,
2673 mips_insn16_frame_base_address
,
2674 mips_insn16_frame_base_address
2677 static const struct frame_base
*
2678 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2680 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2681 CORE_ADDR pc
= get_frame_pc (this_frame
);
2682 if (mips_pc_is_mips16 (gdbarch
, pc
))
2683 return &mips_insn16_frame_base
;
2688 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2689 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2690 interpreted directly, and then multiplied by 4. */
2693 micromips_decode_imm9 (int imm
)
2695 imm
= (imm
^ 0x100) - 0x100;
2696 if (imm
> -3 && imm
< 2)
2701 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2702 the address of the first instruction past the prologue. */
2705 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2706 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2707 struct frame_info
*this_frame
,
2708 struct mips_frame_cache
*this_cache
)
2710 CORE_ADDR end_prologue_addr
= 0;
2711 int prev_non_prologue_insn
= 0;
2712 int frame_reg
= MIPS_SP_REGNUM
;
2713 int this_non_prologue_insn
;
2714 int non_prologue_insns
= 0;
2715 long frame_offset
= 0; /* Size of stack frame. */
2716 long frame_adjust
= 0; /* Offset of FP from SP. */
2717 CORE_ADDR frame_addr
= 0; /* Value of $30, used as frame pointer. */
2720 ULONGEST insn
; /* current instruction */
2724 long v1_off
= 0; /* The assumption is LUI will replace it. */
2735 /* Can be called when there's no process, and hence when there's no
2737 if (this_frame
!= NULL
)
2738 sp
= get_frame_register_signed (this_frame
,
2739 gdbarch_num_regs (gdbarch
)
2744 if (limit_pc
> start_pc
+ 200)
2745 limit_pc
= start_pc
+ 200;
2748 /* Permit at most one non-prologue non-control-transfer instruction
2749 in the middle which may have been reordered by the compiler for
2751 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
2753 this_non_prologue_insn
= 0;
2756 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
2757 loc
+= MIPS_INSN16_SIZE
;
2758 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
2760 /* 48-bit instructions. */
2761 case 3 * MIPS_INSN16_SIZE
:
2762 /* No prologue instructions in this category. */
2763 this_non_prologue_insn
= 1;
2764 loc
+= 2 * MIPS_INSN16_SIZE
;
2767 /* 32-bit instructions. */
2768 case 2 * MIPS_INSN16_SIZE
:
2770 insn
|= mips_fetch_instruction (gdbarch
,
2771 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
2772 loc
+= MIPS_INSN16_SIZE
;
2773 switch (micromips_op (insn
>> 16))
2775 /* Record $sp/$fp adjustment. */
2776 /* Discard (D)ADDU $gp,$jp used for PIC code. */
2777 case 0x0: /* POOL32A: bits 000000 */
2778 case 0x16: /* POOL32S: bits 010110 */
2779 op
= b0s11_op (insn
);
2780 sreg
= b0s5_reg (insn
>> 16);
2781 treg
= b5s5_reg (insn
>> 16);
2782 dreg
= b11s5_reg (insn
);
2784 /* SUBU: bits 000000 00111010000 */
2785 /* DSUBU: bits 010110 00111010000 */
2786 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
2788 /* (D)SUBU $sp, $v1 */
2790 else if (op
!= 0x150
2791 /* ADDU: bits 000000 00101010000 */
2792 /* DADDU: bits 010110 00101010000 */
2793 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
2794 this_non_prologue_insn
= 1;
2797 case 0x8: /* POOL32B: bits 001000 */
2798 op
= b12s4_op (insn
);
2799 breg
= b0s5_reg (insn
>> 16);
2800 reglist
= sreg
= b5s5_reg (insn
>> 16);
2801 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
2802 if ((op
== 0x9 || op
== 0xc)
2803 /* SWP: bits 001000 1001 */
2804 /* SDP: bits 001000 1100 */
2805 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
2806 /* S[DW]P reg,offset($sp) */
2808 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
2809 set_reg_offset (gdbarch
, this_cache
,
2811 set_reg_offset (gdbarch
, this_cache
,
2812 sreg
+ 1, sp
+ offset
+ s
);
2814 else if ((op
== 0xd || op
== 0xf)
2815 /* SWM: bits 001000 1101 */
2816 /* SDM: bits 001000 1111 */
2817 && breg
== MIPS_SP_REGNUM
2818 /* SWM reglist,offset($sp) */
2819 && ((reglist
>= 1 && reglist
<= 9)
2820 || (reglist
>= 16 && reglist
<= 25)))
2822 int sreglist
= min(reglist
& 0xf, 8);
2824 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
2825 for (i
= 0; i
< sreglist
; i
++)
2826 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
2827 if ((reglist
& 0xf) > 8)
2828 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
2829 if ((reglist
& 0x10) == 0x10)
2830 set_reg_offset (gdbarch
, this_cache
,
2831 MIPS_RA_REGNUM
, sp
+ s
* i
++);
2834 this_non_prologue_insn
= 1;
2837 /* Record $sp/$fp adjustment. */
2838 /* Discard (D)ADDIU $gp used for PIC code. */
2839 case 0xc: /* ADDIU: bits 001100 */
2840 case 0x17: /* DADDIU: bits 010111 */
2841 sreg
= b0s5_reg (insn
>> 16);
2842 dreg
= b5s5_reg (insn
>> 16);
2843 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2844 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
2845 /* (D)ADDIU $sp, imm */
2847 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2848 /* (D)ADDIU $fp, $sp, imm */
2850 frame_addr
= sp
+ offset
;
2851 frame_adjust
= offset
;
2854 else if (sreg
!= 28 || dreg
!= 28)
2855 /* (D)ADDIU $gp, imm */
2856 this_non_prologue_insn
= 1;
2859 /* LUI $v1 is used for larger $sp adjustments. */
2860 /* Discard LUI $gp is used for PIC code. */
2861 case 0x10: /* POOL32I: bits 010000 */
2862 if (b5s5_op (insn
>> 16) == 0xd
2863 /* LUI: bits 010000 001101 */
2864 && b0s5_reg (insn
>> 16) == 3)
2866 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
2867 else if (b5s5_op (insn
>> 16) != 0xd
2868 /* LUI: bits 010000 001101 */
2869 || b0s5_reg (insn
>> 16) != 28)
2871 this_non_prologue_insn
= 1;
2874 /* ORI $v1 is used for larger $sp adjustments. */
2875 case 0x14: /* ORI: bits 010100 */
2876 sreg
= b0s5_reg (insn
>> 16);
2877 dreg
= b5s5_reg (insn
>> 16);
2878 if (sreg
== 3 && dreg
== 3)
2880 v1_off
|= b0s16_imm (insn
);
2882 this_non_prologue_insn
= 1;
2885 case 0x26: /* SWC1: bits 100110 */
2886 case 0x2e: /* SDC1: bits 101110 */
2887 breg
= b0s5_reg (insn
>> 16);
2888 if (breg
!= MIPS_SP_REGNUM
)
2889 /* S[DW]C1 reg,offset($sp) */
2890 this_non_prologue_insn
= 1;
2893 case 0x36: /* SD: bits 110110 */
2894 case 0x3e: /* SW: bits 111110 */
2895 breg
= b0s5_reg (insn
>> 16);
2896 sreg
= b5s5_reg (insn
>> 16);
2897 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
2898 if (breg
== MIPS_SP_REGNUM
)
2899 /* S[DW] reg,offset($sp) */
2900 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
2902 this_non_prologue_insn
= 1;
2906 this_non_prologue_insn
= 1;
2911 /* 16-bit instructions. */
2912 case MIPS_INSN16_SIZE
:
2913 switch (micromips_op (insn
))
2915 case 0x3: /* MOVE: bits 000011 */
2916 sreg
= b0s5_reg (insn
);
2917 dreg
= b5s5_reg (insn
);
2918 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
2924 else if ((sreg
& 0x1c) != 0x4)
2925 /* MOVE reg, $a0-$a3 */
2926 this_non_prologue_insn
= 1;
2929 case 0x11: /* POOL16C: bits 010001 */
2930 if (b6s4_op (insn
) == 0x5)
2931 /* SWM: bits 010001 0101 */
2933 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
2934 reglist
= b4s2_regl (insn
);
2935 for (i
= 0; i
<= reglist
; i
++)
2936 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
2937 set_reg_offset (gdbarch
, this_cache
,
2938 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
2941 this_non_prologue_insn
= 1;
2944 case 0x13: /* POOL16D: bits 010011 */
2945 if ((insn
& 0x1) == 0x1)
2946 /* ADDIUSP: bits 010011 1 */
2947 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
2948 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
2949 /* ADDIUS5: bits 010011 0 */
2950 /* ADDIUS5 $sp, imm */
2951 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
2953 this_non_prologue_insn
= 1;
2956 case 0x32: /* SWSP: bits 110010 */
2957 offset
= b0s5_imm (insn
) << 2;
2958 sreg
= b5s5_reg (insn
);
2959 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
2963 this_non_prologue_insn
= 1;
2969 frame_offset
-= sp_adj
;
2971 non_prologue_insns
+= this_non_prologue_insn
;
2972 /* Enough non-prologue insns seen or positive stack adjustment? */
2973 if (end_prologue_addr
== 0 && (non_prologue_insns
> 1 || sp_adj
> 0))
2975 end_prologue_addr
= prev_non_prologue_insn
? prev_pc
: cur_pc
;
2978 prev_non_prologue_insn
= this_non_prologue_insn
;
2982 if (this_cache
!= NULL
)
2985 (get_frame_register_signed (this_frame
,
2986 gdbarch_num_regs (gdbarch
) + frame_reg
)
2987 + frame_offset
- frame_adjust
);
2988 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2989 be able to get rid of the assignment below, evetually. But it's
2990 still needed for now. */
2991 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2992 + mips_regnum (gdbarch
)->pc
]
2993 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2996 /* If we didn't reach the end of the prologue when scanning the function
2997 instructions, then set end_prologue_addr to the address of the
2998 instruction immediately after the last one we scanned. Unless the
2999 last one looked like a non-prologue instruction (and we looked ahead),
3000 in which case use its address instead. */
3001 if (end_prologue_addr
== 0)
3002 end_prologue_addr
= prev_non_prologue_insn
? prev_pc
: cur_pc
;
3004 return end_prologue_addr
;
3007 /* Heuristic unwinder for procedures using microMIPS instructions.
3008 Procedures that use the 32-bit instruction set are handled by the
3009 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3011 static struct mips_frame_cache
*
3012 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3014 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3015 struct mips_frame_cache
*cache
;
3017 if ((*this_cache
) != NULL
)
3018 return (*this_cache
);
3020 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3021 (*this_cache
) = cache
;
3022 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3024 /* Analyze the function prologue. */
3026 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3027 CORE_ADDR start_addr
;
3029 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3030 if (start_addr
== 0)
3031 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3032 /* We can't analyze the prologue if we couldn't find the begining
3034 if (start_addr
== 0)
3037 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3040 /* gdbarch_sp_regnum contains the value and not the address. */
3041 trad_frame_set_value (cache
->saved_regs
,
3042 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3045 return (*this_cache
);
3049 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3050 struct frame_id
*this_id
)
3052 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3054 /* This marks the outermost frame. */
3055 if (info
->base
== 0)
3057 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3060 static struct value
*
3061 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3062 void **this_cache
, int regnum
)
3064 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3066 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3070 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3071 struct frame_info
*this_frame
, void **this_cache
)
3073 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3074 CORE_ADDR pc
= get_frame_pc (this_frame
);
3076 if (mips_pc_is_micromips (gdbarch
, pc
))
3081 static const struct frame_unwind mips_micro_frame_unwind
=
3084 default_frame_unwind_stop_reason
,
3085 mips_micro_frame_this_id
,
3086 mips_micro_frame_prev_register
,
3088 mips_micro_frame_sniffer
3092 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3095 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3100 static const struct frame_base mips_micro_frame_base
=
3102 &mips_micro_frame_unwind
,
3103 mips_micro_frame_base_address
,
3104 mips_micro_frame_base_address
,
3105 mips_micro_frame_base_address
3108 static const struct frame_base
*
3109 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3111 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3112 CORE_ADDR pc
= get_frame_pc (this_frame
);
3114 if (mips_pc_is_micromips (gdbarch
, pc
))
3115 return &mips_micro_frame_base
;
3120 /* Mark all the registers as unset in the saved_regs array
3121 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3124 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3126 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3130 const int num_regs
= gdbarch_num_regs (gdbarch
);
3133 for (i
= 0; i
< num_regs
; i
++)
3135 this_cache
->saved_regs
[i
].addr
= -1;
3140 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3141 the associated FRAME_CACHE if not null.
3142 Return the address of the first instruction past the prologue. */
3145 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3146 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3147 struct frame_info
*this_frame
,
3148 struct mips_frame_cache
*this_cache
)
3151 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3155 int frame_reg
= MIPS_SP_REGNUM
;
3157 CORE_ADDR end_prologue_addr
= 0;
3158 int seen_sp_adjust
= 0;
3159 int load_immediate_bytes
= 0;
3160 int in_delay_slot
= 0;
3161 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3163 /* Can be called when there's no process, and hence when there's no
3165 if (this_frame
!= NULL
)
3166 sp
= get_frame_register_signed (this_frame
,
3167 gdbarch_num_regs (gdbarch
)
3172 if (limit_pc
> start_pc
+ 200)
3173 limit_pc
= start_pc
+ 200;
3178 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3180 unsigned long inst
, high_word
, low_word
;
3183 /* Fetch the instruction. */
3184 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3187 /* Save some code by pre-extracting some useful fields. */
3188 high_word
= (inst
>> 16) & 0xffff;
3189 low_word
= inst
& 0xffff;
3190 reg
= high_word
& 0x1f;
3192 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3193 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3194 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3196 if (low_word
& 0x8000) /* Negative stack adjustment? */
3197 frame_offset
+= 0x10000 - low_word
;
3199 /* Exit loop if a positive stack adjustment is found, which
3200 usually means that the stack cleanup code in the function
3201 epilogue is reached. */
3205 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3206 && !regsize_is_64_bits
)
3208 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3210 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3211 && regsize_is_64_bits
)
3213 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3214 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
3216 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3218 /* Old gcc frame, r30 is virtual frame pointer. */
3219 if ((long) low_word
!= frame_offset
)
3220 frame_addr
= sp
+ low_word
;
3221 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3223 unsigned alloca_adjust
;
3226 frame_addr
= get_frame_register_signed
3227 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3229 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
3230 if (alloca_adjust
> 0)
3232 /* FP > SP + frame_size. This may be because of
3233 an alloca or somethings similar. Fix sp to
3234 "pre-alloca" value, and try again. */
3235 sp
+= alloca_adjust
;
3236 /* Need to reset the status of all registers. Otherwise,
3237 we will hit a guard that prevents the new address
3238 for each register to be recomputed during the second
3240 reset_saved_regs (gdbarch
, this_cache
);
3245 /* move $30,$sp. With different versions of gas this will be either
3246 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3247 Accept any one of these. */
3248 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3250 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3251 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3253 unsigned alloca_adjust
;
3256 frame_addr
= get_frame_register_signed
3257 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3259 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3260 if (alloca_adjust
> 0)
3262 /* FP > SP + frame_size. This may be because of
3263 an alloca or somethings similar. Fix sp to
3264 "pre-alloca" value, and try again. */
3266 /* Need to reset the status of all registers. Otherwise,
3267 we will hit a guard that prevents the new address
3268 for each register to be recomputed during the second
3270 reset_saved_regs (gdbarch
, this_cache
);
3275 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3276 && !regsize_is_64_bits
)
3278 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
3280 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3281 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3282 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3283 || high_word
== 0x3c1c /* lui $gp,n */
3284 || high_word
== 0x279c /* addiu $gp,$gp,n */
3285 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3286 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3289 /* These instructions are part of the prologue, but we don't
3290 need to do anything special to handle them. */
3292 /* The instructions below load $at or $t0 with an immediate
3293 value in preparation for a stack adjustment via
3294 subu $sp,$sp,[$at,$t0]. These instructions could also
3295 initialize a local variable, so we accept them only before
3296 a stack adjustment instruction was seen. */
3297 else if (!seen_sp_adjust
3298 && (high_word
== 0x3c01 /* lui $at,n */
3299 || high_word
== 0x3c08 /* lui $t0,n */
3300 || high_word
== 0x3421 /* ori $at,$at,n */
3301 || high_word
== 0x3508 /* ori $t0,$t0,n */
3302 || high_word
== 0x3401 /* ori $at,$zero,n */
3303 || high_word
== 0x3408 /* ori $t0,$zero,n */
3306 if (end_prologue_addr
== 0)
3307 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3311 /* This instruction is not an instruction typically found
3312 in a prologue, so we must have reached the end of the
3314 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
3315 loop now? Why would we need to continue scanning the function
3317 if (end_prologue_addr
== 0)
3318 end_prologue_addr
= cur_pc
;
3320 /* Check for branches and jumps. For now, only jump to
3321 register are caught (i.e. returns). */
3322 if ((itype_op (inst
) & 0x07) == 0 && rtype_funct (inst
) == 8)
3326 /* If the previous instruction was a jump, we must have reached
3327 the end of the prologue by now. Stop scanning so that we do
3328 not go past the function return. */
3333 if (this_cache
!= NULL
)
3336 (get_frame_register_signed (this_frame
,
3337 gdbarch_num_regs (gdbarch
) + frame_reg
)
3339 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3340 this assignment below, eventually. But it's still needed
3342 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3343 + mips_regnum (gdbarch
)->pc
]
3344 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3348 /* If we didn't reach the end of the prologue when scanning the function
3349 instructions, then set end_prologue_addr to the address of the
3350 instruction immediately after the last one we scanned. */
3351 /* brobecker/2004-10-10: I don't think this would ever happen, but
3352 we may as well be careful and do our best if we have a null
3353 end_prologue_addr. */
3354 if (end_prologue_addr
== 0)
3355 end_prologue_addr
= cur_pc
;
3357 /* In a frameless function, we might have incorrectly
3358 skipped some load immediate instructions. Undo the skipping
3359 if the load immediate was not followed by a stack adjustment. */
3360 if (load_immediate_bytes
&& !seen_sp_adjust
)
3361 end_prologue_addr
-= load_immediate_bytes
;
3363 return end_prologue_addr
;
3366 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3367 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3368 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3369 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3371 static struct mips_frame_cache
*
3372 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3374 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3375 struct mips_frame_cache
*cache
;
3377 if ((*this_cache
) != NULL
)
3378 return (*this_cache
);
3380 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3381 (*this_cache
) = cache
;
3382 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3384 /* Analyze the function prologue. */
3386 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3387 CORE_ADDR start_addr
;
3389 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3390 if (start_addr
== 0)
3391 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3392 /* We can't analyze the prologue if we couldn't find the begining
3394 if (start_addr
== 0)
3397 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
, *this_cache
);
3400 /* gdbarch_sp_regnum contains the value and not the address. */
3401 trad_frame_set_value (cache
->saved_regs
,
3402 gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
,
3405 return (*this_cache
);
3409 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3410 struct frame_id
*this_id
)
3412 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3414 /* This marks the outermost frame. */
3415 if (info
->base
== 0)
3417 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3420 static struct value
*
3421 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3422 void **this_cache
, int regnum
)
3424 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3426 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3430 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3431 struct frame_info
*this_frame
, void **this_cache
)
3433 CORE_ADDR pc
= get_frame_pc (this_frame
);
3434 if (mips_pc_is_mips (pc
))
3439 static const struct frame_unwind mips_insn32_frame_unwind
=
3442 default_frame_unwind_stop_reason
,
3443 mips_insn32_frame_this_id
,
3444 mips_insn32_frame_prev_register
,
3446 mips_insn32_frame_sniffer
3450 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3453 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3458 static const struct frame_base mips_insn32_frame_base
=
3460 &mips_insn32_frame_unwind
,
3461 mips_insn32_frame_base_address
,
3462 mips_insn32_frame_base_address
,
3463 mips_insn32_frame_base_address
3466 static const struct frame_base
*
3467 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3469 CORE_ADDR pc
= get_frame_pc (this_frame
);
3470 if (mips_pc_is_mips (pc
))
3471 return &mips_insn32_frame_base
;
3476 static struct trad_frame_cache
*
3477 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3480 CORE_ADDR start_addr
;
3481 CORE_ADDR stack_addr
;
3482 struct trad_frame_cache
*this_trad_cache
;
3483 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3484 int num_regs
= gdbarch_num_regs (gdbarch
);
3486 if ((*this_cache
) != NULL
)
3487 return (*this_cache
);
3488 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3489 (*this_cache
) = this_trad_cache
;
3491 /* The return address is in the link register. */
3492 trad_frame_set_reg_realreg (this_trad_cache
,
3493 gdbarch_pc_regnum (gdbarch
),
3494 num_regs
+ MIPS_RA_REGNUM
);
3496 /* Frame ID, since it's a frameless / stackless function, no stack
3497 space is allocated and SP on entry is the current SP. */
3498 pc
= get_frame_pc (this_frame
);
3499 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3500 stack_addr
= get_frame_register_signed (this_frame
,
3501 num_regs
+ MIPS_SP_REGNUM
);
3502 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3504 /* Assume that the frame's base is the same as the
3506 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3508 return this_trad_cache
;
3512 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3513 struct frame_id
*this_id
)
3515 struct trad_frame_cache
*this_trad_cache
3516 = mips_stub_frame_cache (this_frame
, this_cache
);
3517 trad_frame_get_id (this_trad_cache
, this_id
);
3520 static struct value
*
3521 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3522 void **this_cache
, int regnum
)
3524 struct trad_frame_cache
*this_trad_cache
3525 = mips_stub_frame_cache (this_frame
, this_cache
);
3526 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3530 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3531 struct frame_info
*this_frame
, void **this_cache
)
3534 struct obj_section
*s
;
3535 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3536 struct minimal_symbol
*msym
;
3538 /* Use the stub unwinder for unreadable code. */
3539 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3542 if (in_plt_section (pc
, NULL
))
3545 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
3546 s
= find_pc_section (pc
);
3549 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
3550 ".MIPS.stubs") == 0)
3553 /* Calling a PIC function from a non-PIC function passes through a
3554 stub. The stub for foo is named ".pic.foo". */
3555 msym
= lookup_minimal_symbol_by_pc (pc
);
3557 && SYMBOL_LINKAGE_NAME (msym
) != NULL
3558 && strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) == 0)
3564 static const struct frame_unwind mips_stub_frame_unwind
=
3567 default_frame_unwind_stop_reason
,
3568 mips_stub_frame_this_id
,
3569 mips_stub_frame_prev_register
,
3571 mips_stub_frame_sniffer
3575 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3578 struct trad_frame_cache
*this_trad_cache
3579 = mips_stub_frame_cache (this_frame
, this_cache
);
3580 return trad_frame_get_this_base (this_trad_cache
);
3583 static const struct frame_base mips_stub_frame_base
=
3585 &mips_stub_frame_unwind
,
3586 mips_stub_frame_base_address
,
3587 mips_stub_frame_base_address
,
3588 mips_stub_frame_base_address
3591 static const struct frame_base
*
3592 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3594 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3595 return &mips_stub_frame_base
;
3600 /* mips_addr_bits_remove - remove useless address bits */
3603 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3605 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3607 if (is_compact_addr (addr
))
3608 addr
= unmake_compact_addr (addr
);
3610 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3611 /* This hack is a work-around for existing boards using PMON, the
3612 simulator, and any other 64-bit targets that doesn't have true
3613 64-bit addressing. On these targets, the upper 32 bits of
3614 addresses are ignored by the hardware. Thus, the PC or SP are
3615 likely to have been sign extended to all 1s by instruction
3616 sequences that load 32-bit addresses. For example, a typical
3617 piece of code that loads an address is this:
3619 lui $r2, <upper 16 bits>
3620 ori $r2, <lower 16 bits>
3622 But the lui sign-extends the value such that the upper 32 bits
3623 may be all 1s. The workaround is simply to mask off these
3624 bits. In the future, gcc may be changed to support true 64-bit
3625 addressing, and this masking will have to be disabled. */
3626 return addr
&= 0xffffffffUL
;
3632 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3633 instruction and ending with a SC/SCD instruction. If such a sequence
3634 is found, attempt to step through it. A breakpoint is placed at the end of
3637 /* Instructions used during single-stepping of atomic sequences, standard
3639 #define LL_OPCODE 0x30
3640 #define LLD_OPCODE 0x34
3641 #define SC_OPCODE 0x38
3642 #define SCD_OPCODE 0x3c
3645 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3646 struct address_space
*aspace
, CORE_ADDR pc
)
3648 CORE_ADDR breaks
[2] = {-1, -1};
3650 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3654 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3655 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3657 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3658 /* Assume all atomic sequences start with a ll/lld instruction. */
3659 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3662 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3664 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3667 loc
+= MIPS_INSN32_SIZE
;
3668 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3670 /* Assume that there is at most one branch in the atomic
3671 sequence. If a branch is found, put a breakpoint in its
3672 destination address. */
3673 switch (itype_op (insn
))
3675 case 0: /* SPECIAL */
3676 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3677 return 0; /* fallback to the standard single-step code. */
3679 case 1: /* REGIMM */
3680 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3681 || ((itype_rt (insn
) & 0x1e) == 0
3682 && itype_rs (insn
) == 0)); /* BPOSGE* */
3686 return 0; /* fallback to the standard single-step code. */
3693 case 22: /* BLEZL */
3694 case 23: /* BGTTL */
3698 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3699 && (itype_rt (insn
) & 0x2) == 0);
3700 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3705 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3710 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3711 if (last_breakpoint
>= 1)
3712 return 0; /* More than one branch found, fallback to the
3713 standard single-step code. */
3714 breaks
[1] = branch_bp
;
3718 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3722 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3723 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3726 loc
+= MIPS_INSN32_SIZE
;
3728 /* Insert a breakpoint right after the end of the atomic sequence. */
3731 /* Check for duplicated breakpoints. Check also for a breakpoint
3732 placed (branch instruction's destination) in the atomic sequence. */
3733 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3734 last_breakpoint
= 0;
3736 /* Effectively inserts the breakpoints. */
3737 for (index
= 0; index
<= last_breakpoint
; index
++)
3738 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3744 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3745 struct address_space
*aspace
,
3748 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3749 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3750 CORE_ADDR breaks
[2] = {-1, -1};
3751 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3758 /* Assume all atomic sequences start with a ll/lld instruction. */
3759 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3760 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
3762 loc
+= MIPS_INSN16_SIZE
;
3764 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3765 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
3767 loc
+= MIPS_INSN16_SIZE
;
3769 /* Assume all atomic sequences end with an sc/scd instruction. Assume
3770 that no atomic sequence is longer than "atomic_sequence_length"
3772 for (insn_count
= 0;
3773 !sc_found
&& insn_count
< atomic_sequence_length
;
3778 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
3779 loc
+= MIPS_INSN16_SIZE
;
3781 /* Assume that there is at most one conditional branch in the
3782 atomic sequence. If a branch is found, put a breakpoint in
3783 its destination address. */
3784 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3786 /* 48-bit instructions. */
3787 case 3 * MIPS_INSN16_SIZE
: /* POOL48A: bits 011111 */
3788 loc
+= 2 * MIPS_INSN16_SIZE
;
3791 /* 32-bit instructions. */
3792 case 2 * MIPS_INSN16_SIZE
:
3793 switch (micromips_op (insn
))
3795 case 0x10: /* POOL32I: bits 010000 */
3796 if ((b5s5_op (insn
) & 0x18) != 0x0
3797 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
3798 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
3799 && (b5s5_op (insn
) & 0x1d) != 0x11
3800 /* BLTZALS, BGEZALS: bits 010000 100x1 */
3801 && ((b5s5_op (insn
) & 0x1e) != 0x14
3802 || (insn
& 0x3) != 0x0)
3803 /* BC2F, BC2T: bits 010000 1010x xxx00 */
3804 && (b5s5_op (insn
) & 0x1e) != 0x1a
3805 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
3806 && ((b5s5_op (insn
) & 0x1e) != 0x1c
3807 || (insn
& 0x3) != 0x0)
3808 /* BC1F, BC1T: bits 010000 1110x xxx00 */
3809 && ((b5s5_op (insn
) & 0x1c) != 0x1c
3810 || (insn
& 0x3) != 0x1))
3811 /* BC1ANY*: bits 010000 111xx xxx01 */
3815 case 0x25: /* BEQ: bits 100101 */
3816 case 0x2d: /* BNE: bits 101101 */
3818 insn
|= mips_fetch_instruction (gdbarch
,
3819 ISA_MICROMIPS
, loc
, NULL
);
3820 branch_bp
= (loc
+ MIPS_INSN16_SIZE
3821 + micromips_relative_offset16 (insn
));
3825 case 0x00: /* POOL32A: bits 000000 */
3827 insn
|= mips_fetch_instruction (gdbarch
,
3828 ISA_MICROMIPS
, loc
, NULL
);
3829 if (b0s6_op (insn
) != 0x3c
3830 /* POOL32Axf: bits 000000 ... 111100 */
3831 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
3832 /* JALR, JALR.HB: 000000 000x111100 111100 */
3833 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
3837 case 0x1d: /* JALS: bits 011101 */
3838 case 0x35: /* J: bits 110101 */
3839 case 0x3d: /* JAL: bits 111101 */
3840 case 0x3c: /* JALX: bits 111100 */
3841 return 0; /* Fall back to the standard single-step code. */
3843 case 0x18: /* POOL32C: bits 011000 */
3844 if ((b12s4_op (insn
) & 0xb) == 0xb)
3845 /* SC, SCD: bits 011000 1x11 */
3849 loc
+= MIPS_INSN16_SIZE
;
3852 /* 16-bit instructions. */
3853 case MIPS_INSN16_SIZE
:
3854 switch (micromips_op (insn
))
3856 case 0x23: /* BEQZ16: bits 100011 */
3857 case 0x2b: /* BNEZ16: bits 101011 */
3858 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
3862 case 0x11: /* POOL16C: bits 010001 */
3863 if ((b5s5_op (insn
) & 0x1c) != 0xc
3864 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
3865 && b5s5_op (insn
) != 0x18)
3866 /* JRADDIUSP: bits 010001 11000 */
3868 return 0; /* Fall back to the standard single-step code. */
3870 case 0x33: /* B16: bits 110011 */
3871 return 0; /* Fall back to the standard single-step code. */
3877 if (last_breakpoint
>= 1)
3878 return 0; /* More than one branch found, fallback to the
3879 standard single-step code. */
3880 breaks
[1] = branch_bp
;
3887 /* Insert a breakpoint right after the end of the atomic sequence. */
3890 /* Check for duplicated breakpoints. Check also for a breakpoint
3891 placed (branch instruction's destination) in the atomic sequence */
3892 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3893 last_breakpoint
= 0;
3895 /* Effectively inserts the breakpoints. */
3896 for (index
= 0; index
<= last_breakpoint
; index
++)
3897 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
3903 deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
3904 struct address_space
*aspace
, CORE_ADDR pc
)
3906 if (mips_pc_is_mips (pc
))
3907 return mips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
3908 else if (mips_pc_is_micromips (gdbarch
, pc
))
3909 return micromips_deal_with_atomic_sequence (gdbarch
, aspace
, pc
);
3914 /* mips_software_single_step() is called just before we want to resume
3915 the inferior, if we want to single-step it but there is no hardware
3916 or kernel single-step support (MIPS on GNU/Linux for example). We find
3917 the target of the coming instruction and breakpoint it. */
3920 mips_software_single_step (struct frame_info
*frame
)
3922 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3923 struct address_space
*aspace
= get_frame_address_space (frame
);
3924 CORE_ADDR pc
, next_pc
;
3926 pc
= get_frame_pc (frame
);
3927 if (deal_with_atomic_sequence (gdbarch
, aspace
, pc
))
3930 next_pc
= mips_next_pc (frame
, pc
);
3932 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
3936 /* Test whether the PC points to the return instruction at the
3937 end of a function. */
3940 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3945 /* This used to check for MIPS16, but this piece of code is never
3946 called for MIPS16 functions. And likewise microMIPS ones. */
3947 gdb_assert (mips_pc_is_mips (pc
));
3949 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
3951 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
3955 /* This fencepost looks highly suspicious to me. Removing it also
3956 seems suspicious as it could affect remote debugging across serial
3960 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3966 struct inferior
*inf
;
3968 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
3970 fence
= start_pc
- heuristic_fence_post
;
3974 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
3975 fence
= VM_MIN_ADDRESS
;
3977 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
3979 inf
= current_inferior ();
3981 /* Search back for previous return. */
3982 for (start_pc
-= instlen
;; start_pc
-= instlen
)
3983 if (start_pc
< fence
)
3985 /* It's not clear to me why we reach this point when
3986 stop_soon, but with this test, at least we
3987 don't print out warnings for every child forked (eg, on
3988 decstation). 22apr93 rich@cygnus.com. */
3989 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
3991 static int blurb_printed
= 0;
3993 warning (_("GDB can't find the start of the function at %s."),
3994 paddress (gdbarch
, pc
));
3998 /* This actually happens frequently in embedded
3999 development, when you first connect to a board
4000 and your stack pointer and pc are nowhere in
4001 particular. This message needs to give people
4002 in that situation enough information to
4003 determine that it's no big deal. */
4004 printf_filtered ("\n\
4005 GDB is unable to find the start of the function at %s\n\
4006 and thus can't determine the size of that function's stack frame.\n\
4007 This means that GDB may be unable to access that stack frame, or\n\
4008 the frames below it.\n\
4009 This problem is most likely caused by an invalid program counter or\n\
4011 However, if you think GDB should simply search farther back\n\
4012 from %s for code which looks like the beginning of a\n\
4013 function, you can increase the range of the search using the `set\n\
4014 heuristic-fence-post' command.\n",
4015 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4022 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4024 unsigned short inst
;
4026 /* On MIPS16, any one of the following is likely to be the
4027 start of a function:
4033 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4034 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4035 if ((inst
& 0xff80) == 0x6480) /* save */
4037 if (start_pc
- instlen
>= fence
)
4039 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4040 start_pc
- instlen
, NULL
);
4041 if ((inst
& 0xf800) == 0xf000) /* extend */
4042 start_pc
-= instlen
;
4046 else if (((inst
& 0xf81f) == 0xe809
4047 && (inst
& 0x700) != 0x700) /* entry */
4048 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4049 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4050 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4052 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4053 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4058 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4066 /* On microMIPS, any one of the following is likely to be the
4067 start of a function:
4071 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4072 switch (micromips_op (insn
))
4074 case 0xc: /* ADDIU: bits 001100 */
4075 case 0x17: /* DADDIU: bits 010111 */
4076 sreg
= b0s5_reg (insn
);
4077 dreg
= b5s5_reg (insn
);
4079 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4080 pc
+ MIPS_INSN16_SIZE
, NULL
);
4081 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4082 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4083 /* (D)ADDIU $sp, imm */
4088 case 0x10: /* POOL32I: bits 010000 */
4089 if (b5s5_op (insn
) == 0xd
4090 /* LUI: bits 010000 001101 */
4091 && b0s5_reg (insn
>> 16) == 28)
4096 case 0x13: /* POOL16D: bits 010011 */
4097 if ((insn
& 0x1) == 0x1)
4098 /* ADDIUSP: bits 010011 1 */
4100 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4106 /* ADDIUS5: bits 010011 0 */
4108 dreg
= b5s5_reg (insn
);
4109 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4110 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4111 /* ADDIUS5 $sp, -imm */
4119 else if (mips_about_to_return (gdbarch
, start_pc
))
4121 /* Skip return and its delay slot. */
4122 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4129 struct mips_objfile_private
4135 /* According to the current ABI, should the type be passed in a
4136 floating-point register (assuming that there is space)? When there
4137 is no FPU, FP are not even considered as possible candidates for
4138 FP registers and, consequently this returns false - forces FP
4139 arguments into integer registers. */
4142 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4143 struct type
*arg_type
)
4145 return ((typecode
== TYPE_CODE_FLT
4146 || (MIPS_EABI (gdbarch
)
4147 && (typecode
== TYPE_CODE_STRUCT
4148 || typecode
== TYPE_CODE_UNION
)
4149 && TYPE_NFIELDS (arg_type
) == 1
4150 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
4152 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4155 /* On o32, argument passing in GPRs depends on the alignment of the type being
4156 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4159 mips_type_needs_double_align (struct type
*type
)
4161 enum type_code typecode
= TYPE_CODE (type
);
4163 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4165 else if (typecode
== TYPE_CODE_STRUCT
)
4167 if (TYPE_NFIELDS (type
) < 1)
4169 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
4171 else if (typecode
== TYPE_CODE_UNION
)
4175 n
= TYPE_NFIELDS (type
);
4176 for (i
= 0; i
< n
; i
++)
4177 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
4184 /* Adjust the address downward (direction of stack growth) so that it
4185 is correctly aligned for a new stack frame. */
4187 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4189 return align_down (addr
, 16);
4192 /* Implement the "push_dummy_code" gdbarch method. */
4195 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4196 CORE_ADDR funaddr
, struct value
**args
,
4197 int nargs
, struct type
*value_type
,
4198 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4199 struct regcache
*regcache
)
4202 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4204 /* Reserve enough room on the stack for our breakpoint instruction. */
4205 *bp_addr
= sp
- sizeof (nop_insn
);
4207 /* The breakpoint layer automatically adjusts the address of
4208 breakpoints inserted in a branch delay slot. With enough
4209 bad luck, the 4 bytes located just before our breakpoint
4210 instruction could look like a branch instruction, and thus
4211 trigger the adjustement, and break the function call entirely.
4212 So, we reserve those 4 bytes and write a nop instruction
4213 to prevent that from happening. */
4214 nop_addr
= *bp_addr
- sizeof (nop_insn
);
4215 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4216 sp
= mips_frame_align (gdbarch
, nop_addr
);
4218 /* Inferior resumes at the function entry point. */
4225 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4226 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4227 int nargs
, struct value
**args
, CORE_ADDR sp
,
4228 int struct_return
, CORE_ADDR struct_addr
)
4234 int stack_offset
= 0;
4235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4236 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4237 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4238 int regsize
= mips_abi_regsize (gdbarch
);
4240 /* For shared libraries, "t9" needs to point at the function
4242 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4244 /* Set the return address register to point to the entry point of
4245 the program, where a breakpoint lies in wait. */
4246 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4248 /* First ensure that the stack and structure return address (if any)
4249 are properly aligned. The stack has to be at least 64-bit
4250 aligned even on 32-bit machines, because doubles must be 64-bit
4251 aligned. For n32 and n64, stack frames need to be 128-bit
4252 aligned, so we round to this widest known alignment. */
4254 sp
= align_down (sp
, 16);
4255 struct_addr
= align_down (struct_addr
, 16);
4257 /* Now make space on the stack for the args. We allocate more
4258 than necessary for EABI, because the first few arguments are
4259 passed in registers, but that's OK. */
4260 for (argnum
= 0; argnum
< nargs
; argnum
++)
4261 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
4262 sp
-= align_up (len
, 16);
4265 fprintf_unfiltered (gdb_stdlog
,
4266 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4267 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4269 /* Initialize the integer and float register pointers. */
4270 argreg
= MIPS_A0_REGNUM
;
4271 float_argreg
= mips_fpa0_regnum (gdbarch
);
4273 /* The struct_return pointer occupies the first parameter-passing reg. */
4277 fprintf_unfiltered (gdb_stdlog
,
4278 "mips_eabi_push_dummy_call: "
4279 "struct_return reg=%d %s\n",
4280 argreg
, paddress (gdbarch
, struct_addr
));
4281 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4284 /* Now load as many as possible of the first arguments into
4285 registers, and push the rest onto the stack. Loop thru args
4286 from first to last. */
4287 for (argnum
= 0; argnum
< nargs
; argnum
++)
4289 const gdb_byte
*val
;
4290 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
4291 struct value
*arg
= args
[argnum
];
4292 struct type
*arg_type
= check_typedef (value_type (arg
));
4293 int len
= TYPE_LENGTH (arg_type
);
4294 enum type_code typecode
= TYPE_CODE (arg_type
);
4297 fprintf_unfiltered (gdb_stdlog
,
4298 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4299 argnum
+ 1, len
, (int) typecode
);
4301 /* Function pointer arguments to mips16 code need to be made into
4303 if (typecode
== TYPE_CODE_PTR
4304 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
4306 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
4308 if (mips_pc_is_mips (addr
))
4309 val
= value_contents (arg
);
4312 store_signed_integer (valbuf
, len
, byte_order
,
4313 make_compact_addr (addr
));
4317 /* The EABI passes structures that do not fit in a register by
4319 else if (len
> regsize
4320 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4322 store_unsigned_integer (valbuf
, regsize
, byte_order
,
4323 value_address (arg
));
4324 typecode
= TYPE_CODE_PTR
;
4328 fprintf_unfiltered (gdb_stdlog
, " push");
4331 val
= value_contents (arg
);
4333 /* 32-bit ABIs always start floating point arguments in an
4334 even-numbered floating point register. Round the FP register
4335 up before the check to see if there are any FP registers
4336 left. Non MIPS_EABI targets also pass the FP in the integer
4337 registers so also round up normal registers. */
4338 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4340 if ((float_argreg
& 1))
4344 /* Floating point arguments passed in registers have to be
4345 treated specially. On 32-bit architectures, doubles
4346 are passed in register pairs; the even register gets
4347 the low word, and the odd register gets the high word.
4348 On non-EABI processors, the first two floating point arguments are
4349 also copied to general registers, because MIPS16 functions
4350 don't use float registers for arguments. This duplication of
4351 arguments in general registers can't hurt non-MIPS16 functions
4352 because those registers are normally skipped. */
4353 /* MIPS_EABI squeezes a struct that contains a single floating
4354 point value into an FP register instead of pushing it onto the
4356 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4357 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4359 /* EABI32 will pass doubles in consecutive registers, even on
4360 64-bit cores. At one time, we used to check the size of
4361 `float_argreg' to determine whether or not to pass doubles
4362 in consecutive registers, but this is not sufficient for
4363 making the ABI determination. */
4364 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4366 int low_offset
= gdbarch_byte_order (gdbarch
)
4367 == BFD_ENDIAN_BIG
? 4 : 0;
4370 /* Write the low word of the double to the even register(s). */
4371 regval
= extract_signed_integer (val
+ low_offset
,
4374 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4375 float_argreg
, phex (regval
, 4));
4376 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4378 /* Write the high word of the double to the odd register(s). */
4379 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4382 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4383 float_argreg
, phex (regval
, 4));
4384 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4388 /* This is a floating point value that fits entirely
4389 in a single register. */
4390 /* On 32 bit ABI's the float_argreg is further adjusted
4391 above to ensure that it is even register aligned. */
4392 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4394 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4395 float_argreg
, phex (regval
, len
));
4396 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4401 /* Copy the argument to general registers or the stack in
4402 register-sized pieces. Large arguments are split between
4403 registers and stack. */
4404 /* Note: structs whose size is not a multiple of regsize
4405 are treated specially: Irix cc passes
4406 them in registers where gcc sometimes puts them on the
4407 stack. For maximum compatibility, we will put them in
4409 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
4411 /* Note: Floating-point values that didn't fit into an FP
4412 register are only written to memory. */
4415 /* Remember if the argument was written to the stack. */
4416 int stack_used_p
= 0;
4417 int partial_len
= (len
< regsize
? len
: regsize
);
4420 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4423 /* Write this portion of the argument to the stack. */
4424 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4426 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4428 /* Should shorter than int integer values be
4429 promoted to int before being stored? */
4430 int longword_offset
= 0;
4433 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4436 && (typecode
== TYPE_CODE_INT
4437 || typecode
== TYPE_CODE_PTR
4438 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4439 longword_offset
= regsize
- len
;
4440 else if ((typecode
== TYPE_CODE_STRUCT
4441 || typecode
== TYPE_CODE_UNION
)
4442 && TYPE_LENGTH (arg_type
) < regsize
)
4443 longword_offset
= regsize
- len
;
4448 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4449 paddress (gdbarch
, stack_offset
));
4450 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4451 paddress (gdbarch
, longword_offset
));
4454 addr
= sp
+ stack_offset
+ longword_offset
;
4459 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4460 paddress (gdbarch
, addr
));
4461 for (i
= 0; i
< partial_len
; i
++)
4463 fprintf_unfiltered (gdb_stdlog
, "%02x",
4467 write_memory (addr
, val
, partial_len
);
4470 /* Note!!! This is NOT an else clause. Odd sized
4471 structs may go thru BOTH paths. Floating point
4472 arguments will not. */
4473 /* Write this portion of the argument to a general
4474 purpose register. */
4475 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4476 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4479 extract_signed_integer (val
, partial_len
, byte_order
);
4482 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4484 phex (regval
, regsize
));
4485 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4492 /* Compute the offset into the stack at which we will
4493 copy the next parameter.
4495 In the new EABI (and the NABI32), the stack_offset
4496 only needs to be adjusted when it has been used. */
4499 stack_offset
+= align_up (partial_len
, regsize
);
4503 fprintf_unfiltered (gdb_stdlog
, "\n");
4506 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4508 /* Return adjusted stack pointer. */
4512 /* Determine the return value convention being used. */
4514 static enum return_value_convention
4515 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4516 struct type
*type
, struct regcache
*regcache
,
4517 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4519 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4520 int fp_return_type
= 0;
4521 int offset
, regnum
, xfer
;
4523 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4524 return RETURN_VALUE_STRUCT_CONVENTION
;
4526 /* Floating point type? */
4527 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4529 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
4531 /* Structs with a single field of float type
4532 are returned in a floating point register. */
4533 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
4534 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
4535 && TYPE_NFIELDS (type
) == 1)
4537 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
4539 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
4546 /* A floating-point value belongs in the least significant part
4549 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4550 regnum
= mips_regnum (gdbarch
)->fp0
;
4554 /* An integer value goes in V0/V1. */
4556 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4557 regnum
= MIPS_V0_REGNUM
;
4560 offset
< TYPE_LENGTH (type
);
4561 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4563 xfer
= mips_abi_regsize (gdbarch
);
4564 if (offset
+ xfer
> TYPE_LENGTH (type
))
4565 xfer
= TYPE_LENGTH (type
) - offset
;
4566 mips_xfer_register (gdbarch
, regcache
,
4567 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4568 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4572 return RETURN_VALUE_REGISTER_CONVENTION
;
4576 /* N32/N64 ABI stuff. */
4578 /* Search for a naturally aligned double at OFFSET inside a struct
4579 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4583 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4588 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
4591 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4594 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4597 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
4600 struct type
*field_type
;
4602 /* We're only looking at normal fields. */
4603 if (field_is_static (&TYPE_FIELD (arg_type
, i
))
4604 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4607 /* If we have gone past the offset, there is no double to pass. */
4608 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4612 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
4614 /* If this field is entirely before the requested offset, go
4615 on to the next one. */
4616 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4619 /* If this is our special aligned double, we can stop. */
4620 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
4621 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4624 /* This field starts at or before the requested offset, and
4625 overlaps it. If it is a structure, recurse inwards. */
4626 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4633 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4634 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4635 int nargs
, struct value
**args
, CORE_ADDR sp
,
4636 int struct_return
, CORE_ADDR struct_addr
)
4642 int stack_offset
= 0;
4643 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4644 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4645 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4647 /* For shared libraries, "t9" needs to point at the function
4649 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4651 /* Set the return address register to point to the entry point of
4652 the program, where a breakpoint lies in wait. */
4653 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4655 /* First ensure that the stack and structure return address (if any)
4656 are properly aligned. The stack has to be at least 64-bit
4657 aligned even on 32-bit machines, because doubles must be 64-bit
4658 aligned. For n32 and n64, stack frames need to be 128-bit
4659 aligned, so we round to this widest known alignment. */
4661 sp
= align_down (sp
, 16);
4662 struct_addr
= align_down (struct_addr
, 16);
4664 /* Now make space on the stack for the args. */
4665 for (argnum
= 0; argnum
< nargs
; argnum
++)
4666 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4667 sp
-= align_up (len
, 16);
4670 fprintf_unfiltered (gdb_stdlog
,
4671 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4672 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
4674 /* Initialize the integer and float register pointers. */
4675 argreg
= MIPS_A0_REGNUM
;
4676 float_argreg
= mips_fpa0_regnum (gdbarch
);
4678 /* The struct_return pointer occupies the first parameter-passing reg. */
4682 fprintf_unfiltered (gdb_stdlog
,
4683 "mips_n32n64_push_dummy_call: "
4684 "struct_return reg=%d %s\n",
4685 argreg
, paddress (gdbarch
, struct_addr
));
4686 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4689 /* Now load as many as possible of the first arguments into
4690 registers, and push the rest onto the stack. Loop thru args
4691 from first to last. */
4692 for (argnum
= 0; argnum
< nargs
; argnum
++)
4694 const gdb_byte
*val
;
4695 struct value
*arg
= args
[argnum
];
4696 struct type
*arg_type
= check_typedef (value_type (arg
));
4697 int len
= TYPE_LENGTH (arg_type
);
4698 enum type_code typecode
= TYPE_CODE (arg_type
);
4701 fprintf_unfiltered (gdb_stdlog
,
4702 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4703 argnum
+ 1, len
, (int) typecode
);
4705 val
= value_contents (arg
);
4707 /* A 128-bit long double value requires an even-odd pair of
4708 floating-point registers. */
4710 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4711 && (float_argreg
& 1))
4717 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4718 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4720 /* This is a floating point value that fits entirely
4721 in a single register or a pair of registers. */
4722 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4723 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4725 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4726 float_argreg
, phex (regval
, reglen
));
4727 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4730 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4731 argreg
, phex (regval
, reglen
));
4732 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4737 regval
= extract_unsigned_integer (val
+ reglen
,
4738 reglen
, byte_order
);
4740 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4741 float_argreg
, phex (regval
, reglen
));
4742 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4745 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4746 argreg
, phex (regval
, reglen
));
4747 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4754 /* Copy the argument to general registers or the stack in
4755 register-sized pieces. Large arguments are split between
4756 registers and stack. */
4757 /* For N32/N64, structs, unions, or other composite types are
4758 treated as a sequence of doublewords, and are passed in integer
4759 or floating point registers as though they were simple scalar
4760 parameters to the extent that they fit, with any excess on the
4761 stack packed according to the normal memory layout of the
4763 The caller does not reserve space for the register arguments;
4764 the callee is responsible for reserving it if required. */
4765 /* Note: Floating-point values that didn't fit into an FP
4766 register are only written to memory. */
4769 /* Remember if the argument was written to the stack. */
4770 int stack_used_p
= 0;
4771 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4774 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4777 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4778 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
4780 /* Write this portion of the argument to the stack. */
4781 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
4783 /* Should shorter than int integer values be
4784 promoted to int before being stored? */
4785 int longword_offset
= 0;
4788 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4790 if ((typecode
== TYPE_CODE_INT
4791 || typecode
== TYPE_CODE_PTR
)
4793 longword_offset
= MIPS64_REGSIZE
- len
;
4798 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4799 paddress (gdbarch
, stack_offset
));
4800 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4801 paddress (gdbarch
, longword_offset
));
4804 addr
= sp
+ stack_offset
+ longword_offset
;
4809 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4810 paddress (gdbarch
, addr
));
4811 for (i
= 0; i
< partial_len
; i
++)
4813 fprintf_unfiltered (gdb_stdlog
, "%02x",
4817 write_memory (addr
, val
, partial_len
);
4820 /* Note!!! This is NOT an else clause. Odd sized
4821 structs may go thru BOTH paths. */
4822 /* Write this portion of the argument to a general
4823 purpose register. */
4824 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4828 /* Sign extend pointers, 32-bit integers and signed
4829 16-bit and 8-bit integers; everything else is taken
4832 if ((partial_len
== 4
4833 && (typecode
== TYPE_CODE_PTR
4834 || typecode
== TYPE_CODE_INT
))
4836 && typecode
== TYPE_CODE_INT
4837 && !TYPE_UNSIGNED (arg_type
)))
4838 regval
= extract_signed_integer (val
, partial_len
,
4841 regval
= extract_unsigned_integer (val
, partial_len
,
4844 /* A non-floating-point argument being passed in a
4845 general register. If a struct or union, and if
4846 the remaining length is smaller than the register
4847 size, we have to adjust the register value on
4850 It does not seem to be necessary to do the
4851 same for integral types. */
4853 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4854 && partial_len
< MIPS64_REGSIZE
4855 && (typecode
== TYPE_CODE_STRUCT
4856 || typecode
== TYPE_CODE_UNION
))
4857 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4861 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4863 phex (regval
, MIPS64_REGSIZE
));
4864 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4866 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
4867 TYPE_LENGTH (arg_type
) - len
))
4870 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
4872 phex (regval
, MIPS64_REGSIZE
));
4873 regcache_cooked_write_unsigned (regcache
, float_argreg
,
4884 /* Compute the offset into the stack at which we will
4885 copy the next parameter.
4887 In N32 (N64?), the stack_offset only needs to be
4888 adjusted when it has been used. */
4891 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4895 fprintf_unfiltered (gdb_stdlog
, "\n");
4898 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4900 /* Return adjusted stack pointer. */
4904 static enum return_value_convention
4905 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4906 struct type
*type
, struct regcache
*regcache
,
4907 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4909 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4911 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
4913 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
4914 if needed), as appropriate for the type. Composite results (struct,
4915 union, or array) are returned in $2/$f0 and $3/$f2 according to the
4918 * A struct with only one or two floating point fields is returned in $f0
4919 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
4922 * Any other composite results of at most 128 bits are returned in
4923 $2 (first 64 bits) and $3 (remainder, if necessary).
4925 * Larger composite results are handled by converting the function to a
4926 procedure with an implicit first parameter, which is a pointer to an area
4927 reserved by the caller to receive the result. [The o32-bit ABI requires
4928 that all composite results be handled by conversion to implicit first
4929 parameters. The MIPS/SGI Fortran implementation has always made a
4930 specific exception to return COMPLEX results in the floating point
4933 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
4934 return RETURN_VALUE_STRUCT_CONVENTION
;
4935 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4936 && TYPE_LENGTH (type
) == 16
4937 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4939 /* A 128-bit floating-point value fills both $f0 and $f2. The
4940 two registers are used in the same as memory order, so the
4941 eight bytes with the lower memory address are in $f0. */
4943 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
4944 mips_xfer_register (gdbarch
, regcache
,
4945 (gdbarch_num_regs (gdbarch
)
4946 + mips_regnum (gdbarch
)->fp0
),
4947 8, gdbarch_byte_order (gdbarch
),
4948 readbuf
, writebuf
, 0);
4949 mips_xfer_register (gdbarch
, regcache
,
4950 (gdbarch_num_regs (gdbarch
)
4951 + mips_regnum (gdbarch
)->fp0
+ 2),
4952 8, gdbarch_byte_order (gdbarch
),
4953 readbuf
? readbuf
+ 8 : readbuf
,
4954 writebuf
? writebuf
+ 8 : writebuf
, 0);
4955 return RETURN_VALUE_REGISTER_CONVENTION
;
4957 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
4958 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4960 /* A single or double floating-point value that fits in FP0. */
4962 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4963 mips_xfer_register (gdbarch
, regcache
,
4964 (gdbarch_num_regs (gdbarch
)
4965 + mips_regnum (gdbarch
)->fp0
),
4967 gdbarch_byte_order (gdbarch
),
4968 readbuf
, writebuf
, 0);
4969 return RETURN_VALUE_REGISTER_CONVENTION
;
4971 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4972 && TYPE_NFIELDS (type
) <= 2
4973 && TYPE_NFIELDS (type
) >= 1
4974 && ((TYPE_NFIELDS (type
) == 1
4975 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
4977 || (TYPE_NFIELDS (type
) == 2
4978 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
4980 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
4981 == TYPE_CODE_FLT
))))
4983 /* A struct that contains one or two floats. Each value is part
4984 in the least significant part of their floating point
4985 register (or GPR, for soft float). */
4988 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
4989 ? mips_regnum (gdbarch
)->fp0
4991 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
4993 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
4996 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
4998 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
5000 /* A 16-byte long double field goes in two consecutive
5002 mips_xfer_register (gdbarch
, regcache
,
5003 gdbarch_num_regs (gdbarch
) + regnum
,
5005 gdbarch_byte_order (gdbarch
),
5006 readbuf
, writebuf
, offset
);
5007 mips_xfer_register (gdbarch
, regcache
,
5008 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5010 gdbarch_byte_order (gdbarch
),
5011 readbuf
, writebuf
, offset
+ 8);
5014 mips_xfer_register (gdbarch
, regcache
,
5015 gdbarch_num_regs (gdbarch
) + regnum
,
5016 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5017 gdbarch_byte_order (gdbarch
),
5018 readbuf
, writebuf
, offset
);
5020 return RETURN_VALUE_REGISTER_CONVENTION
;
5022 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5023 || TYPE_CODE (type
) == TYPE_CODE_UNION
5024 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5026 /* A composite type. Extract the left justified value,
5027 regardless of the byte order. I.e. DO NOT USE
5031 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5032 offset
< TYPE_LENGTH (type
);
5033 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5035 int xfer
= register_size (gdbarch
, regnum
);
5036 if (offset
+ xfer
> TYPE_LENGTH (type
))
5037 xfer
= TYPE_LENGTH (type
) - offset
;
5039 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5040 offset
, xfer
, regnum
);
5041 mips_xfer_register (gdbarch
, regcache
,
5042 gdbarch_num_regs (gdbarch
) + regnum
,
5043 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5046 return RETURN_VALUE_REGISTER_CONVENTION
;
5050 /* A scalar extract each part but least-significant-byte
5054 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5055 offset
< TYPE_LENGTH (type
);
5056 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5058 int xfer
= register_size (gdbarch
, regnum
);
5059 if (offset
+ xfer
> TYPE_LENGTH (type
))
5060 xfer
= TYPE_LENGTH (type
) - offset
;
5062 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5063 offset
, xfer
, regnum
);
5064 mips_xfer_register (gdbarch
, regcache
,
5065 gdbarch_num_regs (gdbarch
) + regnum
,
5066 xfer
, gdbarch_byte_order (gdbarch
),
5067 readbuf
, writebuf
, offset
);
5069 return RETURN_VALUE_REGISTER_CONVENTION
;
5073 /* Which registers to use for passing floating-point values between
5074 function calls, one of floating-point, general and both kinds of
5075 registers. O32 and O64 use different register kinds for standard
5076 MIPS and MIPS16 code; to make the handling of cases where we may
5077 not know what kind of code is being used (e.g. no debug information)
5078 easier we sometimes use both kinds. */
5087 /* O32 ABI stuff. */
5090 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5091 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5092 int nargs
, struct value
**args
, CORE_ADDR sp
,
5093 int struct_return
, CORE_ADDR struct_addr
)
5099 int stack_offset
= 0;
5100 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5101 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5102 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5104 /* For shared libraries, "t9" needs to point at the function
5106 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5108 /* Set the return address register to point to the entry point of
5109 the program, where a breakpoint lies in wait. */
5110 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5112 /* First ensure that the stack and structure return address (if any)
5113 are properly aligned. The stack has to be at least 64-bit
5114 aligned even on 32-bit machines, because doubles must be 64-bit
5115 aligned. For n32 and n64, stack frames need to be 128-bit
5116 aligned, so we round to this widest known alignment. */
5118 sp
= align_down (sp
, 16);
5119 struct_addr
= align_down (struct_addr
, 16);
5121 /* Now make space on the stack for the args. */
5122 for (argnum
= 0; argnum
< nargs
; argnum
++)
5124 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5125 int arglen
= TYPE_LENGTH (arg_type
);
5127 /* Align to double-word if necessary. */
5128 if (mips_type_needs_double_align (arg_type
))
5129 len
= align_up (len
, MIPS32_REGSIZE
* 2);
5130 /* Allocate space on the stack. */
5131 len
+= align_up (arglen
, MIPS32_REGSIZE
);
5133 sp
-= align_up (len
, 16);
5136 fprintf_unfiltered (gdb_stdlog
,
5137 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5138 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5140 /* Initialize the integer and float register pointers. */
5141 argreg
= MIPS_A0_REGNUM
;
5142 float_argreg
= mips_fpa0_regnum (gdbarch
);
5144 /* The struct_return pointer occupies the first parameter-passing reg. */
5148 fprintf_unfiltered (gdb_stdlog
,
5149 "mips_o32_push_dummy_call: "
5150 "struct_return reg=%d %s\n",
5151 argreg
, paddress (gdbarch
, struct_addr
));
5152 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5153 stack_offset
+= MIPS32_REGSIZE
;
5156 /* Now load as many as possible of the first arguments into
5157 registers, and push the rest onto the stack. Loop thru args
5158 from first to last. */
5159 for (argnum
= 0; argnum
< nargs
; argnum
++)
5161 const gdb_byte
*val
;
5162 struct value
*arg
= args
[argnum
];
5163 struct type
*arg_type
= check_typedef (value_type (arg
));
5164 int len
= TYPE_LENGTH (arg_type
);
5165 enum type_code typecode
= TYPE_CODE (arg_type
);
5168 fprintf_unfiltered (gdb_stdlog
,
5169 "mips_o32_push_dummy_call: %d len=%d type=%d",
5170 argnum
+ 1, len
, (int) typecode
);
5172 val
= value_contents (arg
);
5174 /* 32-bit ABIs always start floating point arguments in an
5175 even-numbered floating point register. Round the FP register
5176 up before the check to see if there are any FP registers
5177 left. O32 targets also pass the FP in the integer registers
5178 so also round up normal registers. */
5179 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5181 if ((float_argreg
& 1))
5185 /* Floating point arguments passed in registers have to be
5186 treated specially. On 32-bit architectures, doubles are
5187 passed in register pairs; the even FP register gets the
5188 low word, and the odd FP register gets the high word.
5189 On O32, the first two floating point arguments are also
5190 copied to general registers, following their memory order,
5191 because MIPS16 functions don't use float registers for
5192 arguments. This duplication of arguments in general
5193 registers can't hurt non-MIPS16 functions, because those
5194 registers are normally skipped. */
5196 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5197 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5199 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5201 int freg_offset
= gdbarch_byte_order (gdbarch
)
5202 == BFD_ENDIAN_BIG
? 1 : 0;
5203 unsigned long regval
;
5206 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5208 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5209 float_argreg
+ freg_offset
,
5211 regcache_cooked_write_unsigned (regcache
,
5212 float_argreg
++ + freg_offset
,
5215 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5216 argreg
, phex (regval
, 4));
5217 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5220 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5222 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5223 float_argreg
- freg_offset
,
5225 regcache_cooked_write_unsigned (regcache
,
5226 float_argreg
++ - freg_offset
,
5229 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5230 argreg
, phex (regval
, 4));
5231 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5235 /* This is a floating point value that fits entirely
5236 in a single register. */
5237 /* On 32 bit ABI's the float_argreg is further adjusted
5238 above to ensure that it is even register aligned. */
5239 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5241 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5242 float_argreg
, phex (regval
, len
));
5243 regcache_cooked_write_unsigned (regcache
,
5244 float_argreg
++, regval
);
5245 /* Although two FP registers are reserved for each
5246 argument, only one corresponding integer register is
5249 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5250 argreg
, phex (regval
, len
));
5251 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5253 /* Reserve space for the FP register. */
5254 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5258 /* Copy the argument to general registers or the stack in
5259 register-sized pieces. Large arguments are split between
5260 registers and stack. */
5261 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5262 are treated specially: Irix cc passes
5263 them in registers where gcc sometimes puts them on the
5264 stack. For maximum compatibility, we will put them in
5266 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5267 && len
% MIPS32_REGSIZE
!= 0);
5268 /* Structures should be aligned to eight bytes (even arg registers)
5269 on MIPS_ABI_O32, if their first member has double precision. */
5270 if (mips_type_needs_double_align (arg_type
))
5275 stack_offset
+= MIPS32_REGSIZE
;
5280 /* Remember if the argument was written to the stack. */
5281 int stack_used_p
= 0;
5282 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5285 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5288 /* Write this portion of the argument to the stack. */
5289 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5290 || odd_sized_struct
)
5292 /* Should shorter than int integer values be
5293 promoted to int before being stored? */
5294 int longword_offset
= 0;
5300 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5301 paddress (gdbarch
, stack_offset
));
5302 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5303 paddress (gdbarch
, longword_offset
));
5306 addr
= sp
+ stack_offset
+ longword_offset
;
5311 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5312 paddress (gdbarch
, addr
));
5313 for (i
= 0; i
< partial_len
; i
++)
5315 fprintf_unfiltered (gdb_stdlog
, "%02x",
5319 write_memory (addr
, val
, partial_len
);
5322 /* Note!!! This is NOT an else clause. Odd sized
5323 structs may go thru BOTH paths. */
5324 /* Write this portion of the argument to a general
5325 purpose register. */
5326 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5328 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5330 /* Value may need to be sign extended, because
5331 mips_isa_regsize() != mips_abi_regsize(). */
5333 /* A non-floating-point argument being passed in a
5334 general register. If a struct or union, and if
5335 the remaining length is smaller than the register
5336 size, we have to adjust the register value on
5339 It does not seem to be necessary to do the
5340 same for integral types.
5342 Also don't do this adjustment on O64 binaries.
5344 cagney/2001-07-23: gdb/179: Also, GCC, when
5345 outputting LE O32 with sizeof (struct) <
5346 mips_abi_regsize(), generates a left shift
5347 as part of storing the argument in a register
5348 (the left shift isn't generated when
5349 sizeof (struct) >= mips_abi_regsize()). Since
5350 it is quite possible that this is GCC
5351 contradicting the LE/O32 ABI, GDB has not been
5352 adjusted to accommodate this. Either someone
5353 needs to demonstrate that the LE/O32 ABI
5354 specifies such a left shift OR this new ABI gets
5355 identified as such and GDB gets tweaked
5358 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5359 && partial_len
< MIPS32_REGSIZE
5360 && (typecode
== TYPE_CODE_STRUCT
5361 || typecode
== TYPE_CODE_UNION
))
5362 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5366 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5368 phex (regval
, MIPS32_REGSIZE
));
5369 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5372 /* Prevent subsequent floating point arguments from
5373 being passed in floating point registers. */
5374 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5380 /* Compute the offset into the stack at which we will
5381 copy the next parameter.
5383 In older ABIs, the caller reserved space for
5384 registers that contained arguments. This was loosely
5385 refered to as their "home". Consequently, space is
5386 always allocated. */
5388 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5392 fprintf_unfiltered (gdb_stdlog
, "\n");
5395 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5397 /* Return adjusted stack pointer. */
5401 static enum return_value_convention
5402 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5403 struct type
*type
, struct regcache
*regcache
,
5404 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5406 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5407 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5408 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5409 enum mips_fval_reg fval_reg
;
5411 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5412 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5413 || TYPE_CODE (type
) == TYPE_CODE_UNION
5414 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5415 return RETURN_VALUE_STRUCT_CONVENTION
;
5416 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5417 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5419 /* A single-precision floating-point value. If reading in or copying,
5420 then we get it from/put it to FP0 for standard MIPS code or GPR2
5421 for MIPS16 code. If writing out only, then we put it to both FP0
5422 and GPR2. We do not support reading in with no function known, if
5423 this safety check ever triggers, then we'll have to try harder. */
5424 gdb_assert (function
|| !readbuf
);
5429 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5432 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5434 case mips_fval_both
:
5435 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5438 if (fval_reg
!= mips_fval_gpr
)
5439 mips_xfer_register (gdbarch
, regcache
,
5440 (gdbarch_num_regs (gdbarch
)
5441 + mips_regnum (gdbarch
)->fp0
),
5443 gdbarch_byte_order (gdbarch
),
5444 readbuf
, writebuf
, 0);
5445 if (fval_reg
!= mips_fval_fpr
)
5446 mips_xfer_register (gdbarch
, regcache
,
5447 gdbarch_num_regs (gdbarch
) + 2,
5449 gdbarch_byte_order (gdbarch
),
5450 readbuf
, writebuf
, 0);
5451 return RETURN_VALUE_REGISTER_CONVENTION
;
5453 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
5454 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5456 /* A double-precision floating-point value. If reading in or copying,
5457 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5458 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5459 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5460 no function known, if this safety check ever triggers, then we'll
5461 have to try harder. */
5462 gdb_assert (function
|| !readbuf
);
5467 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5470 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5472 case mips_fval_both
:
5473 fprintf_unfiltered (gdb_stderr
,
5474 "Return float in $fp1/$fp0 and $2/$3\n");
5477 if (fval_reg
!= mips_fval_gpr
)
5479 /* The most significant part goes in FP1, and the least significant
5481 switch (gdbarch_byte_order (gdbarch
))
5483 case BFD_ENDIAN_LITTLE
:
5484 mips_xfer_register (gdbarch
, regcache
,
5485 (gdbarch_num_regs (gdbarch
)
5486 + mips_regnum (gdbarch
)->fp0
+ 0),
5487 4, gdbarch_byte_order (gdbarch
),
5488 readbuf
, writebuf
, 0);
5489 mips_xfer_register (gdbarch
, regcache
,
5490 (gdbarch_num_regs (gdbarch
)
5491 + mips_regnum (gdbarch
)->fp0
+ 1),
5492 4, gdbarch_byte_order (gdbarch
),
5493 readbuf
, writebuf
, 4);
5495 case BFD_ENDIAN_BIG
:
5496 mips_xfer_register (gdbarch
, regcache
,
5497 (gdbarch_num_regs (gdbarch
)
5498 + mips_regnum (gdbarch
)->fp0
+ 1),
5499 4, gdbarch_byte_order (gdbarch
),
5500 readbuf
, writebuf
, 0);
5501 mips_xfer_register (gdbarch
, regcache
,
5502 (gdbarch_num_regs (gdbarch
)
5503 + mips_regnum (gdbarch
)->fp0
+ 0),
5504 4, gdbarch_byte_order (gdbarch
),
5505 readbuf
, writebuf
, 4);
5508 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5511 if (fval_reg
!= mips_fval_fpr
)
5513 /* The two 32-bit parts are always placed in GPR2 and GPR3
5514 following these registers' memory order. */
5515 mips_xfer_register (gdbarch
, regcache
,
5516 gdbarch_num_regs (gdbarch
) + 2,
5517 4, gdbarch_byte_order (gdbarch
),
5518 readbuf
, writebuf
, 0);
5519 mips_xfer_register (gdbarch
, regcache
,
5520 gdbarch_num_regs (gdbarch
) + 3,
5521 4, gdbarch_byte_order (gdbarch
),
5522 readbuf
, writebuf
, 4);
5524 return RETURN_VALUE_REGISTER_CONVENTION
;
5527 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5528 && TYPE_NFIELDS (type
) <= 2
5529 && TYPE_NFIELDS (type
) >= 1
5530 && ((TYPE_NFIELDS (type
) == 1
5531 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5533 || (TYPE_NFIELDS (type
) == 2
5534 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
5536 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
5538 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5540 /* A struct that contains one or two floats. Each value is part
5541 in the least significant part of their floating point
5543 gdb_byte reg
[MAX_REGISTER_SIZE
];
5546 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5547 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
5549 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
5552 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5554 mips_xfer_register (gdbarch
, regcache
,
5555 gdbarch_num_regs (gdbarch
) + regnum
,
5556 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
5557 gdbarch_byte_order (gdbarch
),
5558 readbuf
, writebuf
, offset
);
5560 return RETURN_VALUE_REGISTER_CONVENTION
;
5564 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5565 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
5567 /* A structure or union. Extract the left justified value,
5568 regardless of the byte order. I.e. DO NOT USE
5572 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5573 offset
< TYPE_LENGTH (type
);
5574 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5576 int xfer
= register_size (gdbarch
, regnum
);
5577 if (offset
+ xfer
> TYPE_LENGTH (type
))
5578 xfer
= TYPE_LENGTH (type
) - offset
;
5580 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5581 offset
, xfer
, regnum
);
5582 mips_xfer_register (gdbarch
, regcache
,
5583 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5584 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5586 return RETURN_VALUE_REGISTER_CONVENTION
;
5591 /* A scalar extract each part but least-significant-byte
5592 justified. o32 thinks registers are 4 byte, regardless of
5596 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5597 offset
< TYPE_LENGTH (type
);
5598 offset
+= MIPS32_REGSIZE
, regnum
++)
5600 int xfer
= MIPS32_REGSIZE
;
5601 if (offset
+ xfer
> TYPE_LENGTH (type
))
5602 xfer
= TYPE_LENGTH (type
) - offset
;
5604 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5605 offset
, xfer
, regnum
);
5606 mips_xfer_register (gdbarch
, regcache
,
5607 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5608 gdbarch_byte_order (gdbarch
),
5609 readbuf
, writebuf
, offset
);
5611 return RETURN_VALUE_REGISTER_CONVENTION
;
5615 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5619 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5620 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5622 struct value
**args
, CORE_ADDR sp
,
5623 int struct_return
, CORE_ADDR struct_addr
)
5629 int stack_offset
= 0;
5630 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5631 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5632 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5634 /* For shared libraries, "t9" needs to point at the function
5636 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5638 /* Set the return address register to point to the entry point of
5639 the program, where a breakpoint lies in wait. */
5640 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5642 /* First ensure that the stack and structure return address (if any)
5643 are properly aligned. The stack has to be at least 64-bit
5644 aligned even on 32-bit machines, because doubles must be 64-bit
5645 aligned. For n32 and n64, stack frames need to be 128-bit
5646 aligned, so we round to this widest known alignment. */
5648 sp
= align_down (sp
, 16);
5649 struct_addr
= align_down (struct_addr
, 16);
5651 /* Now make space on the stack for the args. */
5652 for (argnum
= 0; argnum
< nargs
; argnum
++)
5654 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5655 int arglen
= TYPE_LENGTH (arg_type
);
5657 /* Allocate space on the stack. */
5658 len
+= align_up (arglen
, MIPS64_REGSIZE
);
5660 sp
-= align_up (len
, 16);
5663 fprintf_unfiltered (gdb_stdlog
,
5664 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5665 paddress (gdbarch
, sp
), (long) align_up (len
, 16));
5667 /* Initialize the integer and float register pointers. */
5668 argreg
= MIPS_A0_REGNUM
;
5669 float_argreg
= mips_fpa0_regnum (gdbarch
);
5671 /* The struct_return pointer occupies the first parameter-passing reg. */
5675 fprintf_unfiltered (gdb_stdlog
,
5676 "mips_o64_push_dummy_call: "
5677 "struct_return reg=%d %s\n",
5678 argreg
, paddress (gdbarch
, struct_addr
));
5679 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5680 stack_offset
+= MIPS64_REGSIZE
;
5683 /* Now load as many as possible of the first arguments into
5684 registers, and push the rest onto the stack. Loop thru args
5685 from first to last. */
5686 for (argnum
= 0; argnum
< nargs
; argnum
++)
5688 const gdb_byte
*val
;
5689 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
5690 struct value
*arg
= args
[argnum
];
5691 struct type
*arg_type
= check_typedef (value_type (arg
));
5692 int len
= TYPE_LENGTH (arg_type
);
5693 enum type_code typecode
= TYPE_CODE (arg_type
);
5696 fprintf_unfiltered (gdb_stdlog
,
5697 "mips_o64_push_dummy_call: %d len=%d type=%d",
5698 argnum
+ 1, len
, (int) typecode
);
5700 val
= value_contents (arg
);
5702 /* Function pointer arguments to mips16 code need to be made into
5704 if (typecode
== TYPE_CODE_PTR
5705 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type
)) == TYPE_CODE_FUNC
)
5707 CORE_ADDR addr
= extract_signed_integer (value_contents (arg
),
5709 if (!mips_pc_is_mips (addr
))
5711 store_signed_integer (valbuf
, len
, byte_order
,
5712 make_compact_addr (addr
));
5717 /* Floating point arguments passed in registers have to be
5718 treated specially. On 32-bit architectures, doubles are
5719 passed in register pairs; the even FP register gets the
5720 low word, and the odd FP register gets the high word.
5721 On O64, the first two floating point arguments are also
5722 copied to general registers, because MIPS16 functions
5723 don't use float registers for arguments. This duplication
5724 of arguments in general registers can't hurt non-MIPS16
5725 functions because those registers are normally skipped. */
5727 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5728 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5730 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5732 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5733 float_argreg
, phex (regval
, len
));
5734 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5736 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5737 argreg
, phex (regval
, len
));
5738 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5740 /* Reserve space for the FP register. */
5741 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5745 /* Copy the argument to general registers or the stack in
5746 register-sized pieces. Large arguments are split between
5747 registers and stack. */
5748 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5749 are treated specially: Irix cc passes them in registers
5750 where gcc sometimes puts them on the stack. For maximum
5751 compatibility, we will put them in both places. */
5752 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5753 && len
% MIPS64_REGSIZE
!= 0);
5756 /* Remember if the argument was written to the stack. */
5757 int stack_used_p
= 0;
5758 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5761 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5764 /* Write this portion of the argument to the stack. */
5765 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5766 || odd_sized_struct
)
5768 /* Should shorter than int integer values be
5769 promoted to int before being stored? */
5770 int longword_offset
= 0;
5773 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5775 if ((typecode
== TYPE_CODE_INT
5776 || typecode
== TYPE_CODE_PTR
5777 || typecode
== TYPE_CODE_FLT
)
5779 longword_offset
= MIPS64_REGSIZE
- len
;
5784 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5785 paddress (gdbarch
, stack_offset
));
5786 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5787 paddress (gdbarch
, longword_offset
));
5790 addr
= sp
+ stack_offset
+ longword_offset
;
5795 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5796 paddress (gdbarch
, addr
));
5797 for (i
= 0; i
< partial_len
; i
++)
5799 fprintf_unfiltered (gdb_stdlog
, "%02x",
5803 write_memory (addr
, val
, partial_len
);
5806 /* Note!!! This is NOT an else clause. Odd sized
5807 structs may go thru BOTH paths. */
5808 /* Write this portion of the argument to a general
5809 purpose register. */
5810 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5812 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5814 /* Value may need to be sign extended, because
5815 mips_isa_regsize() != mips_abi_regsize(). */
5817 /* A non-floating-point argument being passed in a
5818 general register. If a struct or union, and if
5819 the remaining length is smaller than the register
5820 size, we have to adjust the register value on
5823 It does not seem to be necessary to do the
5824 same for integral types. */
5826 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5827 && partial_len
< MIPS64_REGSIZE
5828 && (typecode
== TYPE_CODE_STRUCT
5829 || typecode
== TYPE_CODE_UNION
))
5830 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5834 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5836 phex (regval
, MIPS64_REGSIZE
));
5837 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5840 /* Prevent subsequent floating point arguments from
5841 being passed in floating point registers. */
5842 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5848 /* Compute the offset into the stack at which we will
5849 copy the next parameter.
5851 In older ABIs, the caller reserved space for
5852 registers that contained arguments. This was loosely
5853 refered to as their "home". Consequently, space is
5854 always allocated. */
5856 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5860 fprintf_unfiltered (gdb_stdlog
, "\n");
5863 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5865 /* Return adjusted stack pointer. */
5869 static enum return_value_convention
5870 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5871 struct type
*type
, struct regcache
*regcache
,
5872 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5874 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5875 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5876 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5877 enum mips_fval_reg fval_reg
;
5879 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5880 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
5881 || TYPE_CODE (type
) == TYPE_CODE_UNION
5882 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
5883 return RETURN_VALUE_STRUCT_CONVENTION
;
5884 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
5886 /* A floating-point value. If reading in or copying, then we get it
5887 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
5888 If writing out only, then we put it to both FP0 and GPR2. We do
5889 not support reading in with no function known, if this safety
5890 check ever triggers, then we'll have to try harder. */
5891 gdb_assert (function
|| !readbuf
);
5896 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5899 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5901 case mips_fval_both
:
5902 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5905 if (fval_reg
!= mips_fval_gpr
)
5906 mips_xfer_register (gdbarch
, regcache
,
5907 (gdbarch_num_regs (gdbarch
)
5908 + mips_regnum (gdbarch
)->fp0
),
5910 gdbarch_byte_order (gdbarch
),
5911 readbuf
, writebuf
, 0);
5912 if (fval_reg
!= mips_fval_fpr
)
5913 mips_xfer_register (gdbarch
, regcache
,
5914 gdbarch_num_regs (gdbarch
) + 2,
5916 gdbarch_byte_order (gdbarch
),
5917 readbuf
, writebuf
, 0);
5918 return RETURN_VALUE_REGISTER_CONVENTION
;
5922 /* A scalar extract each part but least-significant-byte
5926 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5927 offset
< TYPE_LENGTH (type
);
5928 offset
+= MIPS64_REGSIZE
, regnum
++)
5930 int xfer
= MIPS64_REGSIZE
;
5931 if (offset
+ xfer
> TYPE_LENGTH (type
))
5932 xfer
= TYPE_LENGTH (type
) - offset
;
5934 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5935 offset
, xfer
, regnum
);
5936 mips_xfer_register (gdbarch
, regcache
,
5937 gdbarch_num_regs (gdbarch
) + regnum
,
5938 xfer
, gdbarch_byte_order (gdbarch
),
5939 readbuf
, writebuf
, offset
);
5941 return RETURN_VALUE_REGISTER_CONVENTION
;
5945 /* Floating point register management.
5947 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
5948 64bit operations, these early MIPS cpus treat fp register pairs
5949 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
5950 registers and offer a compatibility mode that emulates the MIPS2 fp
5951 model. When operating in MIPS2 fp compat mode, later cpu's split
5952 double precision floats into two 32-bit chunks and store them in
5953 consecutive fp regs. To display 64-bit floats stored in this
5954 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
5955 Throw in user-configurable endianness and you have a real mess.
5957 The way this works is:
5958 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
5959 double-precision value will be split across two logical registers.
5960 The lower-numbered logical register will hold the low-order bits,
5961 regardless of the processor's endianness.
5962 - If we are on a 64-bit processor, and we are looking for a
5963 single-precision value, it will be in the low ordered bits
5964 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
5965 save slot in memory.
5966 - If we are in 64-bit mode, everything is straightforward.
5968 Note that this code only deals with "live" registers at the top of the
5969 stack. We will attempt to deal with saved registers later, when
5970 the raw/cooked register interface is in place. (We need a general
5971 interface that can deal with dynamic saved register sizes -- fp
5972 regs could be 32 bits wide in one frame and 64 on the frame above
5975 /* Copy a 32-bit single-precision value from the current frame
5976 into rare_buffer. */
5979 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
5980 gdb_byte
*rare_buffer
)
5982 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
5983 int raw_size
= register_size (gdbarch
, regno
);
5984 gdb_byte
*raw_buffer
= alloca (raw_size
);
5986 if (!frame_register_read (frame
, regno
, raw_buffer
))
5987 error (_("can't read register %d (%s)"),
5988 regno
, gdbarch_register_name (gdbarch
, regno
));
5991 /* We have a 64-bit value for this register. Find the low-order
5995 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6000 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6004 memcpy (rare_buffer
, raw_buffer
, 4);
6008 /* Copy a 64-bit double-precision value from the current frame into
6009 rare_buffer. This may include getting half of it from the next
6013 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6014 gdb_byte
*rare_buffer
)
6016 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6017 int raw_size
= register_size (gdbarch
, regno
);
6019 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6021 /* We have a 64-bit value for this register, and we should use
6023 if (!frame_register_read (frame
, regno
, rare_buffer
))
6024 error (_("can't read register %d (%s)"),
6025 regno
, gdbarch_register_name (gdbarch
, regno
));
6029 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6031 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6032 internal_error (__FILE__
, __LINE__
,
6033 _("mips_read_fp_register_double: bad access to "
6034 "odd-numbered FP register"));
6036 /* mips_read_fp_register_single will find the correct 32 bits from
6038 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6040 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6041 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6045 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6046 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6052 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6054 { /* Do values for FP (float) regs. */
6055 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6056 gdb_byte
*raw_buffer
;
6057 double doub
, flt1
; /* Doubles extracted from raw hex data. */
6060 raw_buffer
= alloca (2 * register_size (gdbarch
,
6061 mips_regnum (gdbarch
)->fp0
));
6063 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6064 fprintf_filtered (file
, "%*s",
6065 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6068 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6070 struct value_print_options opts
;
6072 /* 4-byte registers: Print hex and floating. Also print even
6073 numbered registers as doubles. */
6074 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6075 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6078 get_formatted_print_options (&opts
, 'x');
6079 print_scalar_formatted (raw_buffer
,
6080 builtin_type (gdbarch
)->builtin_uint32
,
6083 fprintf_filtered (file
, " flt: ");
6085 fprintf_filtered (file
, " <invalid float> ");
6087 fprintf_filtered (file
, "%-17.9g", flt1
);
6089 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6091 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6092 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6095 fprintf_filtered (file
, " dbl: ");
6097 fprintf_filtered (file
, "<invalid double>");
6099 fprintf_filtered (file
, "%-24.17g", doub
);
6104 struct value_print_options opts
;
6106 /* Eight byte registers: print each one as hex, float and double. */
6107 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6108 flt1
= unpack_double (builtin_type (gdbarch
)->builtin_float
,
6111 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6112 doub
= unpack_double (builtin_type (gdbarch
)->builtin_double
,
6115 get_formatted_print_options (&opts
, 'x');
6116 print_scalar_formatted (raw_buffer
,
6117 builtin_type (gdbarch
)->builtin_uint64
,
6120 fprintf_filtered (file
, " flt: ");
6122 fprintf_filtered (file
, "<invalid float>");
6124 fprintf_filtered (file
, "%-17.9g", flt1
);
6126 fprintf_filtered (file
, " dbl: ");
6128 fprintf_filtered (file
, "<invalid double>");
6130 fprintf_filtered (file
, "%-24.17g", doub
);
6135 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6138 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6139 struct value_print_options opts
;
6142 if (mips_float_register_p (gdbarch
, regnum
))
6144 mips_print_fp_register (file
, frame
, regnum
);
6148 val
= get_frame_register_value (frame
, regnum
);
6149 if (value_optimized_out (val
))
6151 fprintf_filtered (file
, "%s: [Invalid]",
6152 gdbarch_register_name (gdbarch
, regnum
));
6156 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6158 /* The problem with printing numeric register names (r26, etc.) is that
6159 the user can't use them on input. Probably the best solution is to
6160 fix it so that either the numeric or the funky (a2, etc.) names
6161 are accepted on input. */
6162 if (regnum
< MIPS_NUMREGS
)
6163 fprintf_filtered (file
, "(r%d): ", regnum
);
6165 fprintf_filtered (file
, ": ");
6167 get_formatted_print_options (&opts
, 'x');
6168 val_print_scalar_formatted (value_type (val
),
6169 value_contents_for_printing (val
),
6170 value_embedded_offset (val
),
6175 /* Replacement for generic do_registers_info.
6176 Print regs in pretty columns. */
6179 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6182 fprintf_filtered (file
, " ");
6183 mips_print_fp_register (file
, frame
, regnum
);
6184 fprintf_filtered (file
, "\n");
6189 /* Print a row's worth of GP (int) registers, with name labels above. */
6192 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6195 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6196 /* Do values for GP (int) regs. */
6197 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
6198 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6203 /* For GP registers, we print a separate row of names above the vals. */
6204 for (col
= 0, regnum
= start_regnum
;
6205 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6206 + gdbarch_num_pseudo_regs (gdbarch
);
6209 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6210 continue; /* unused register */
6211 if (mips_float_register_p (gdbarch
, regnum
))
6212 break; /* End the row: reached FP register. */
6213 /* Large registers are handled separately. */
6214 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6217 break; /* End the row before this register. */
6219 /* Print this register on a row by itself. */
6220 mips_print_register (file
, frame
, regnum
);
6221 fprintf_filtered (file
, "\n");
6225 fprintf_filtered (file
, " ");
6226 fprintf_filtered (file
,
6227 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6228 gdbarch_register_name (gdbarch
, regnum
));
6235 /* Print the R0 to R31 names. */
6236 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6237 fprintf_filtered (file
, "\n R%-4d",
6238 start_regnum
% gdbarch_num_regs (gdbarch
));
6240 fprintf_filtered (file
, "\n ");
6242 /* Now print the values in hex, 4 or 8 to the row. */
6243 for (col
= 0, regnum
= start_regnum
;
6244 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
6245 + gdbarch_num_pseudo_regs (gdbarch
);
6248 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6249 continue; /* unused register */
6250 if (mips_float_register_p (gdbarch
, regnum
))
6251 break; /* End row: reached FP register. */
6252 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6253 break; /* End row: large register. */
6255 /* OK: get the data in raw format. */
6256 if (!frame_register_read (frame
, regnum
, raw_buffer
))
6257 error (_("can't read register %d (%s)"),
6258 regnum
, gdbarch_register_name (gdbarch
, regnum
));
6259 /* pad small registers */
6261 byte
< (mips_abi_regsize (gdbarch
)
6262 - register_size (gdbarch
, regnum
)); byte
++)
6263 printf_filtered (" ");
6264 /* Now print the register value in hex, endian order. */
6265 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6267 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6268 byte
< register_size (gdbarch
, regnum
); byte
++)
6269 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6271 for (byte
= register_size (gdbarch
, regnum
) - 1;
6273 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6274 fprintf_filtered (file
, " ");
6277 if (col
> 0) /* ie. if we actually printed anything... */
6278 fprintf_filtered (file
, "\n");
6283 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6286 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6287 struct frame_info
*frame
, int regnum
, int all
)
6289 if (regnum
!= -1) /* Do one specified register. */
6291 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6292 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6293 error (_("Not a valid register for the current processor type"));
6295 mips_print_register (file
, frame
, regnum
);
6296 fprintf_filtered (file
, "\n");
6299 /* Do all (or most) registers. */
6301 regnum
= gdbarch_num_regs (gdbarch
);
6302 while (regnum
< gdbarch_num_regs (gdbarch
)
6303 + gdbarch_num_pseudo_regs (gdbarch
))
6305 if (mips_float_register_p (gdbarch
, regnum
))
6307 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6308 regnum
= print_fp_register_row (file
, frame
, regnum
);
6310 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6313 regnum
= print_gp_register_row (file
, frame
, regnum
);
6319 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6320 struct frame_info
*frame
)
6322 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6323 CORE_ADDR pc
= get_frame_pc (frame
);
6324 struct address_space
*aspace
;
6330 if ((mips_pc_is_mips (pc
)
6331 && !mips32_instruction_has_delay_slot (gdbarch
, pc
))
6332 || (mips_pc_is_micromips (gdbarch
, pc
)
6333 && !micromips_instruction_has_delay_slot (gdbarch
, pc
, 0))
6334 || (mips_pc_is_mips16 (gdbarch
, pc
)
6335 && !mips16_instruction_has_delay_slot (gdbarch
, pc
, 0)))
6338 isa
= mips_pc_isa (gdbarch
, pc
);
6339 /* _has_delay_slot above will have validated the read. */
6340 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6341 size
= mips_insn_size (isa
, insn
);
6342 aspace
= get_frame_address_space (frame
);
6343 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6346 /* To skip prologues, I use this predicate. Returns either PC itself
6347 if the code at PC does not look like a function prologue; otherwise
6348 returns an address that (if we're lucky) follows the prologue. If
6349 LENIENT, then we must skip everything which is involved in setting
6350 up the frame (it's OK to skip more, just so long as we don't skip
6351 anything which might clobber the registers which are being saved.
6352 We must skip more in the case where part of the prologue is in the
6353 delay slot of a non-prologue instruction). */
6356 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6359 CORE_ADDR func_addr
;
6361 /* See if we can determine the end of the prologue via the symbol table.
6362 If so, then return either PC, or the PC after the prologue, whichever
6364 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6366 CORE_ADDR post_prologue_pc
6367 = skip_prologue_using_sal (gdbarch
, func_addr
);
6368 if (post_prologue_pc
!= 0)
6369 return max (pc
, post_prologue_pc
);
6372 /* Can't determine prologue from the symbol table, need to examine
6375 /* Find an upper limit on the function prologue using the debug
6376 information. If the debug information could not be used to provide
6377 that bound, then use an arbitrary large number as the upper bound. */
6378 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6380 limit_pc
= pc
+ 100; /* Magic. */
6382 if (mips_pc_is_mips16 (gdbarch
, pc
))
6383 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6384 else if (mips_pc_is_micromips (gdbarch
, pc
))
6385 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6387 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6390 /* Check whether the PC is in a function epilogue (32-bit version).
6391 This is a helper function for mips_in_function_epilogue_p. */
6393 mips32_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6395 CORE_ADDR func_addr
= 0, func_end
= 0;
6397 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6399 /* The MIPS epilogue is max. 12 bytes long. */
6400 CORE_ADDR addr
= func_end
- 12;
6402 if (addr
< func_addr
+ 4)
6403 addr
= func_addr
+ 4;
6407 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6409 unsigned long high_word
;
6412 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6413 high_word
= (inst
>> 16) & 0xffff;
6415 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6416 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6417 && inst
!= 0x03e00008 /* jr $ra */
6418 && inst
!= 0x00000000) /* nop */
6428 /* Check whether the PC is in a function epilogue (microMIPS version).
6429 This is a helper function for mips_in_function_epilogue_p. */
6432 micromips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6434 CORE_ADDR func_addr
= 0;
6435 CORE_ADDR func_end
= 0;
6443 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6446 /* The microMIPS epilogue is max. 12 bytes long. */
6447 addr
= func_end
- 12;
6449 if (addr
< func_addr
+ 2)
6450 addr
= func_addr
+ 2;
6454 for (; pc
< func_end
; pc
+= loc
)
6457 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6458 loc
+= MIPS_INSN16_SIZE
;
6459 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6461 /* 48-bit instructions. */
6462 case 3 * MIPS_INSN16_SIZE
:
6463 /* No epilogue instructions in this category. */
6466 /* 32-bit instructions. */
6467 case 2 * MIPS_INSN16_SIZE
:
6469 insn
|= mips_fetch_instruction (gdbarch
,
6470 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6471 loc
+= MIPS_INSN16_SIZE
;
6472 switch (micromips_op (insn
>> 16))
6474 case 0xc: /* ADDIU: bits 001100 */
6475 case 0x17: /* DADDIU: bits 010111 */
6476 sreg
= b0s5_reg (insn
>> 16);
6477 dreg
= b5s5_reg (insn
>> 16);
6478 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6479 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6480 /* (D)ADDIU $sp, imm */
6490 /* 16-bit instructions. */
6491 case MIPS_INSN16_SIZE
:
6492 switch (micromips_op (insn
))
6494 case 0x3: /* MOVE: bits 000011 */
6495 sreg
= b0s5_reg (insn
);
6496 dreg
= b5s5_reg (insn
);
6497 if (sreg
== 0 && dreg
== 0)
6498 /* MOVE $zero, $zero aka NOP */
6502 case 0x11: /* POOL16C: bits 010001 */
6503 if (b5s5_op (insn
) == 0x18
6504 /* JRADDIUSP: bits 010011 11000 */
6505 || (b5s5_op (insn
) == 0xd
6506 /* JRC: bits 010011 01101 */
6507 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6512 case 0x13: /* POOL16D: bits 010011 */
6513 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6514 if ((insn
& 0x1) == 0x1
6515 /* ADDIUSP: bits 010011 1 */
6529 /* Check whether the PC is in a function epilogue (16-bit version).
6530 This is a helper function for mips_in_function_epilogue_p. */
6532 mips16_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6534 CORE_ADDR func_addr
= 0, func_end
= 0;
6536 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6538 /* The MIPS epilogue is max. 12 bytes long. */
6539 CORE_ADDR addr
= func_end
- 12;
6541 if (addr
< func_addr
+ 4)
6542 addr
= func_addr
+ 4;
6546 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6548 unsigned short inst
;
6550 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6552 if ((inst
& 0xf800) == 0xf000) /* extend */
6555 if (inst
!= 0x6300 /* addiu $sp,offset */
6556 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6557 && inst
!= 0xe820 /* jr $ra */
6558 && inst
!= 0xe8a0 /* jrc $ra */
6559 && inst
!= 0x6500) /* nop */
6569 /* The epilogue is defined here as the area at the end of a function,
6570 after an instruction which destroys the function's stack frame. */
6572 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6574 if (mips_pc_is_mips16 (gdbarch
, pc
))
6575 return mips16_in_function_epilogue_p (gdbarch
, pc
);
6576 else if (mips_pc_is_micromips (gdbarch
, pc
))
6577 return micromips_in_function_epilogue_p (gdbarch
, pc
);
6579 return mips32_in_function_epilogue_p (gdbarch
, pc
);
6582 /* Root of all "set mips "/"show mips " commands. This will eventually be
6583 used for all MIPS-specific commands. */
6586 show_mips_command (char *args
, int from_tty
)
6588 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
6592 set_mips_command (char *args
, int from_tty
)
6595 ("\"set mips\" must be followed by an appropriate subcommand.\n");
6596 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
6599 /* Commands to show/set the MIPS FPU type. */
6602 show_mipsfpu_command (char *args
, int from_tty
)
6606 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
6609 ("The MIPS floating-point coprocessor is unknown "
6610 "because the current architecture is not MIPS.\n");
6614 switch (MIPS_FPU_TYPE (target_gdbarch
))
6616 case MIPS_FPU_SINGLE
:
6617 fpu
= "single-precision";
6619 case MIPS_FPU_DOUBLE
:
6620 fpu
= "double-precision";
6623 fpu
= "absent (none)";
6626 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6628 if (mips_fpu_type_auto
)
6629 printf_unfiltered ("The MIPS floating-point coprocessor "
6630 "is set automatically (currently %s)\n",
6634 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6639 set_mipsfpu_command (char *args
, int from_tty
)
6641 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", "
6642 "\"single\",\"none\" or \"auto\".\n");
6643 show_mipsfpu_command (args
, from_tty
);
6647 set_mipsfpu_single_command (char *args
, int from_tty
)
6649 struct gdbarch_info info
;
6650 gdbarch_info_init (&info
);
6651 mips_fpu_type
= MIPS_FPU_SINGLE
;
6652 mips_fpu_type_auto
= 0;
6653 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6654 instead of relying on globals. Doing that would let generic code
6655 handle the search for this specific architecture. */
6656 if (!gdbarch_update_p (info
))
6657 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6661 set_mipsfpu_double_command (char *args
, int from_tty
)
6663 struct gdbarch_info info
;
6664 gdbarch_info_init (&info
);
6665 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6666 mips_fpu_type_auto
= 0;
6667 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6668 instead of relying on globals. Doing that would let generic code
6669 handle the search for this specific architecture. */
6670 if (!gdbarch_update_p (info
))
6671 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6675 set_mipsfpu_none_command (char *args
, int from_tty
)
6677 struct gdbarch_info info
;
6678 gdbarch_info_init (&info
);
6679 mips_fpu_type
= MIPS_FPU_NONE
;
6680 mips_fpu_type_auto
= 0;
6681 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6682 instead of relying on globals. Doing that would let generic code
6683 handle the search for this specific architecture. */
6684 if (!gdbarch_update_p (info
))
6685 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6689 set_mipsfpu_auto_command (char *args
, int from_tty
)
6691 mips_fpu_type_auto
= 1;
6694 /* Attempt to identify the particular processor model by reading the
6695 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
6696 the relevant processor still exists (it dates back to '94) and
6697 secondly this is not the way to do this. The processor type should
6698 be set by forcing an architecture change. */
6701 deprecated_mips_set_processor_regs_hack (void)
6703 struct regcache
*regcache
= get_current_regcache ();
6704 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
6705 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6708 regcache_cooked_read_unsigned (regcache
, MIPS_PRID_REGNUM
, &prid
);
6709 if ((prid
& ~0xf) == 0x700)
6710 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
6713 /* Just like reinit_frame_cache, but with the right arguments to be
6714 callable as an sfunc. */
6717 reinit_frame_cache_sfunc (char *args
, int from_tty
,
6718 struct cmd_list_element
*c
)
6720 reinit_frame_cache ();
6724 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6726 struct gdbarch
*gdbarch
= info
->application_data
;
6728 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6729 disassembler needs to be able to locally determine the ISA, and
6730 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6732 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6733 info
->mach
= bfd_mach_mips16
;
6734 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6735 info
->mach
= bfd_mach_mips_micromips
;
6737 /* Round down the instruction address to the appropriate boundary. */
6738 memaddr
&= (info
->mach
== bfd_mach_mips16
6739 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6741 /* Set the disassembler options. */
6742 if (!info
->disassembler_options
)
6743 /* This string is not recognized explicitly by the disassembler,
6744 but it tells the disassembler to not try to guess the ABI from
6745 the bfd elf headers, such that, if the user overrides the ABI
6746 of a program linked as NewABI, the disassembly will follow the
6747 register naming conventions specified by the user. */
6748 info
->disassembler_options
= "gpr-names=32";
6750 /* Call the appropriate disassembler based on the target endian-ness. */
6751 if (info
->endian
== BFD_ENDIAN_BIG
)
6752 return print_insn_big_mips (memaddr
, info
);
6754 return print_insn_little_mips (memaddr
, info
);
6758 gdb_print_insn_mips_n32 (bfd_vma memaddr
, struct disassemble_info
*info
)
6760 /* Set up the disassembler info, so that we get the right
6761 register names from libopcodes. */
6762 info
->disassembler_options
= "gpr-names=n32";
6763 info
->flavour
= bfd_target_elf_flavour
;
6765 return gdb_print_insn_mips (memaddr
, info
);
6769 gdb_print_insn_mips_n64 (bfd_vma memaddr
, struct disassemble_info
*info
)
6771 /* Set up the disassembler info, so that we get the right
6772 register names from libopcodes. */
6773 info
->disassembler_options
= "gpr-names=64";
6774 info
->flavour
= bfd_target_elf_flavour
;
6776 return gdb_print_insn_mips (memaddr
, info
);
6779 /* This function implements gdbarch_breakpoint_from_pc. It uses the
6780 program counter value to determine whether a 16- or 32-bit breakpoint
6781 should be used. It returns a pointer to a string of bytes that encode a
6782 breakpoint instruction, stores the length of the string to *lenptr, and
6783 adjusts pc (if necessary) to point to the actual memory location where
6784 the breakpoint should be inserted. */
6786 static const gdb_byte
*
6787 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
,
6788 CORE_ADDR
*pcptr
, int *lenptr
)
6790 CORE_ADDR pc
= *pcptr
;
6792 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6794 if (mips_pc_is_mips16 (gdbarch
, pc
))
6796 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
6797 *pcptr
= unmake_compact_addr (pc
);
6798 *lenptr
= sizeof (mips16_big_breakpoint
);
6799 return mips16_big_breakpoint
;
6801 else if (mips_pc_is_micromips (gdbarch
, pc
))
6803 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
6804 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
6809 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6811 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6812 *pcptr
= unmake_compact_addr (pc
);
6814 return (size
== 2) ? micromips16_big_breakpoint
6815 : micromips32_big_breakpoint
;
6819 /* The IDT board uses an unusual breakpoint value, and
6820 sometimes gets confused when it sees the usual MIPS
6821 breakpoint instruction. */
6822 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
6823 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
6824 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
6825 /* Likewise, IRIX appears to expect a different breakpoint,
6826 although this is not apparent until you try to use pthreads. */
6827 static gdb_byte irix_big_breakpoint
[] = { 0, 0, 0, 0xd };
6829 *lenptr
= sizeof (big_breakpoint
);
6831 if (strcmp (target_shortname
, "mips") == 0)
6832 return idt_big_breakpoint
;
6833 else if (strcmp (target_shortname
, "ddb") == 0
6834 || strcmp (target_shortname
, "pmon") == 0
6835 || strcmp (target_shortname
, "lsi") == 0)
6836 return pmon_big_breakpoint
;
6837 else if (gdbarch_osabi (gdbarch
) == GDB_OSABI_IRIX
)
6838 return irix_big_breakpoint
;
6840 return big_breakpoint
;
6845 if (mips_pc_is_mips16 (gdbarch
, pc
))
6847 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
6848 *pcptr
= unmake_compact_addr (pc
);
6849 *lenptr
= sizeof (mips16_little_breakpoint
);
6850 return mips16_little_breakpoint
;
6852 else if (mips_pc_is_micromips (gdbarch
, pc
))
6854 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
6855 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
6860 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6862 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6863 *pcptr
= unmake_compact_addr (pc
);
6865 return (size
== 2) ? micromips16_little_breakpoint
6866 : micromips32_little_breakpoint
;
6870 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
6871 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
6872 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
6874 *lenptr
= sizeof (little_breakpoint
);
6876 if (strcmp (target_shortname
, "mips") == 0)
6877 return idt_little_breakpoint
;
6878 else if (strcmp (target_shortname
, "ddb") == 0
6879 || strcmp (target_shortname
, "pmon") == 0
6880 || strcmp (target_shortname
, "lsi") == 0)
6881 return pmon_little_breakpoint
;
6883 return little_breakpoint
;
6888 /* Determine the remote breakpoint kind suitable for the PC. The following
6891 * 2 -- 16-bit MIPS16 mode breakpoint,
6893 * 3 -- 16-bit microMIPS mode breakpoint,
6895 * 4 -- 32-bit standard MIPS mode breakpoint,
6897 * 5 -- 32-bit microMIPS mode breakpoint. */
6900 mips_remote_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
,
6903 CORE_ADDR pc
= *pcptr
;
6905 if (mips_pc_is_mips16 (gdbarch
, pc
))
6907 *pcptr
= unmake_compact_addr (pc
);
6910 else if (mips_pc_is_micromips (gdbarch
, pc
))
6916 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
6917 size
= status
? 2 : mips_insn_size (ISA_MICROMIPS
, insn
) == 2 ? 2 : 4;
6918 *pcptr
= unmake_compact_addr (pc
);
6919 *kindptr
= size
| 1;
6925 /* Return non-zero if the ADDR instruction has a branch delay slot
6926 (i.e. it is a jump or branch instruction). This function is based
6927 on mips32_next_pc. */
6930 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
6938 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
6942 op
= itype_op (inst
);
6943 if ((inst
& 0xe0000000) != 0)
6945 rs
= itype_rs (inst
);
6946 rt
= itype_rt (inst
);
6947 return (op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
6948 || op
== 29 /* JALX: bits 011101 */
6951 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
6952 || (rs
== 9 && (rt
& 0x2) == 0)
6953 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
6954 || (rs
== 10 && (rt
& 0x2) == 0))));
6955 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
6958 switch (op
& 0x07) /* extract bits 28,27,26 */
6960 case 0: /* SPECIAL */
6961 op
= rtype_funct (inst
);
6962 return (op
== 8 /* JR */
6963 || op
== 9); /* JALR */
6964 break; /* end SPECIAL */
6965 case 1: /* REGIMM */
6966 rs
= itype_rs (inst
);
6967 rt
= itype_rt (inst
); /* branch condition */
6968 return ((rt
& 0xc) == 0
6969 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
6970 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
6971 || ((rt
& 0x1e) == 0x1c && rs
== 0));
6972 /* BPOSGE32, BPOSGE64: bits 1110x */
6973 break; /* end REGIMM */
6974 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
6980 /* Return non-zero if the ADDR instruction, which must be a 32-bit
6981 instruction if MUSTBE32 is set or can be any instruction otherwise,
6982 has a branch delay slot (i.e. it is a non-compact jump instruction). */
6985 micromips_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
6986 CORE_ADDR addr
, int mustbe32
)
6991 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
6995 if (!mustbe32
) /* 16-bit instructions. */
6996 return (micromips_op (insn
) == 0x11
6997 /* POOL16C: bits 010001 */
6998 && (b5s5_op (insn
) == 0xc
6999 /* JR16: bits 010001 01100 */
7000 || (b5s5_op (insn
) & 0x1e) == 0xe))
7001 /* JALR16, JALRS16: bits 010001 0111x */
7002 || (micromips_op (insn
) & 0x37) == 0x23
7003 /* BEQZ16, BNEZ16: bits 10x011 */
7004 || micromips_op (insn
) == 0x33;
7005 /* B16: bits 110011 */
7007 /* 32-bit instructions. */
7008 if (micromips_op (insn
) == 0x0)
7009 /* POOL32A: bits 000000 */
7012 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7015 return b0s6_op (insn
) == 0x3c
7016 /* POOL32Axf: bits 000000 ... 111100 */
7017 && (b6s10_ext (insn
) & 0x2bf) == 0x3c;
7018 /* JALR, JALR.HB: 000000 000x111100 111100 */
7019 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7022 return (micromips_op (insn
) == 0x10
7023 /* POOL32I: bits 010000 */
7024 && ((b5s5_op (insn
) & 0x1c) == 0x0
7025 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7026 || (b5s5_op (insn
) & 0x1d) == 0x4
7027 /* BLEZ, BGTZ: bits 010000 001x0 */
7028 || (b5s5_op (insn
) & 0x1d) == 0x11
7029 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7030 || ((b5s5_op (insn
) & 0x1e) == 0x14
7031 && (insn
& 0x3) == 0x0)
7032 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7033 || (b5s5_op (insn
) & 0x1e) == 0x1a
7034 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7035 || ((b5s5_op (insn
) & 0x1e) == 0x1c
7036 && (insn
& 0x3) == 0x0)
7037 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7038 || ((b5s5_op (insn
) & 0x1c) == 0x1c
7039 && (insn
& 0x3) == 0x1)))
7040 /* BC1ANY*: bits 010000 111xx xxx01 */
7041 || (micromips_op (insn
) & 0x1f) == 0x1d
7042 /* JALS, JAL: bits x11101 */
7043 || (micromips_op (insn
) & 0x37) == 0x25
7044 /* BEQ, BNE: bits 10x101 */
7045 || micromips_op (insn
) == 0x35
7046 /* J: bits 110101 */
7047 || micromips_op (insn
) == 0x3c;
7048 /* JALX: bits 111100 */
7052 mips16_instruction_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
7055 unsigned short inst
;
7058 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7063 return (inst
& 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */
7064 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7067 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7068 This assumes KSSEG exists. */
7071 mips_segment_boundary (CORE_ADDR bpaddr
)
7073 CORE_ADDR mask
= CORE_ADDR_MAX
;
7076 if (sizeof (CORE_ADDR
) == 8)
7077 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7078 a compiler warning produced where CORE_ADDR is a 32-bit type even
7079 though in that case this is dead code). */
7080 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7083 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7084 segsize
= 29; /* 32-bit compatibility segment */
7086 segsize
= 62; /* xkseg */
7088 case 2: /* xkphys */
7091 default: /* xksseg (1), xkuseg/kuseg (0) */
7095 else if (bpaddr
& 0x80000000) /* kernel segment */
7098 segsize
= 31; /* user segment */
7100 return bpaddr
& mask
;
7103 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7104 it backwards if necessary. Return the address of the new location. */
7107 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7109 CORE_ADDR prev_addr
;
7111 CORE_ADDR func_addr
;
7113 /* If a breakpoint is set on the instruction in a branch delay slot,
7114 GDB gets confused. When the breakpoint is hit, the PC isn't on
7115 the instruction in the branch delay slot, the PC will point to
7116 the branch instruction. Since the PC doesn't match any known
7117 breakpoints, GDB reports a trap exception.
7119 There are two possible fixes for this problem.
7121 1) When the breakpoint gets hit, see if the BD bit is set in the
7122 Cause register (which indicates the last exception occurred in a
7123 branch delay slot). If the BD bit is set, fix the PC to point to
7124 the instruction in the branch delay slot.
7126 2) When the user sets the breakpoint, don't allow him to set the
7127 breakpoint on the instruction in the branch delay slot. Instead
7128 move the breakpoint to the branch instruction (which will have
7131 The problem with the first solution is that if the user then
7132 single-steps the processor, the branch instruction will get
7133 skipped (since GDB thinks the PC is on the instruction in the
7136 So, we'll use the second solution. To do this we need to know if
7137 the instruction we're trying to set the breakpoint on is in the
7138 branch delay slot. */
7140 boundary
= mips_segment_boundary (bpaddr
);
7142 /* Make sure we don't scan back before the beginning of the current
7143 function, since we may fetch constant data or insns that look like
7144 a jump. Of course we might do that anyway if the compiler has
7145 moved constants inline. :-( */
7146 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7147 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7148 boundary
= func_addr
;
7150 if (mips_pc_is_mips (bpaddr
))
7152 if (bpaddr
== boundary
)
7155 /* If the previous instruction has a branch delay slot, we have
7156 to move the breakpoint to the branch instruction. */
7157 prev_addr
= bpaddr
- 4;
7158 if (mips32_instruction_has_delay_slot (gdbarch
, prev_addr
))
7163 int (*instruction_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7164 CORE_ADDR addr
, jmpaddr
;
7167 boundary
= unmake_compact_addr (boundary
);
7169 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7170 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7171 so try for that first, then try the 2 byte JALR/JR.
7172 The microMIPS ASE has a whole range of jumps and branches
7173 with delay slots, some of which take 4 bytes and some take
7174 2 bytes, so the idea is the same.
7175 FIXME: We have to assume that bpaddr is not the second half
7176 of an extended instruction. */
7177 instruction_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7178 ? micromips_instruction_has_delay_slot
7179 : mips16_instruction_has_delay_slot
);
7183 for (i
= 1; i
< 4; i
++)
7185 if (unmake_compact_addr (addr
) == boundary
)
7187 addr
-= MIPS_INSN16_SIZE
;
7188 if (i
== 1 && instruction_has_delay_slot (gdbarch
, addr
, 0))
7189 /* Looks like a JR/JALR at [target-1], but it could be
7190 the second word of a previous JAL/JALX, so record it
7191 and check back one more. */
7193 else if (i
> 1 && instruction_has_delay_slot (gdbarch
, addr
, 1))
7196 /* Looks like a JAL/JALX at [target-2], but it could also
7197 be the second word of a previous JAL/JALX, record it,
7198 and check back one more. */
7201 /* Looks like a JAL/JALX at [target-3], so any previously
7202 recorded JAL/JALX or JR/JALR must be wrong, because:
7205 -2: JAL-ext (can't be JAL/JALX)
7206 -1: bdslot (can't be JR/JALR)
7209 Of course it could be another JAL-ext which looks
7210 like a JAL, but in that case we'd have broken out
7211 of this loop at [target-2]:
7215 -2: bdslot (can't be jmp)
7222 /* Not a jump instruction: if we're at [target-1] this
7223 could be the second word of a JAL/JALX, so continue;
7224 otherwise we're done. */
7237 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7238 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7241 mips_is_stub_suffix (const char *suffix
, int zero
)
7246 return zero
&& suffix
[1] == '\0';
7248 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7253 return suffix
[1] == '\0';
7259 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7260 call stubs, one of sf, df, sc, or dc. */
7263 mips_is_stub_mode (const char *mode
)
7265 return ((mode
[0] == 's' || mode
[0] == 'd')
7266 && (mode
[1] == 'f' || mode
[1] == 'c'));
7269 /* Code at PC is a compiler-generated stub. Such a stub for a function
7270 bar might have a name like __fn_stub_bar, and might look like this:
7277 followed by (or interspersed with):
7284 addiu $25, $25, %lo(bar)
7287 ($1 may be used in old code; for robustness we accept any register)
7290 lui $28, %hi(_gp_disp)
7291 addiu $28, $28, %lo(_gp_disp)
7294 addiu $25, $25, %lo(bar)
7297 In the case of a __call_stub_bar stub, the sequence to set up
7298 arguments might look like this:
7305 followed by (or interspersed with) one of the jump sequences above.
7307 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7308 of J or JR, respectively, followed by:
7314 We are at the beginning of the stub here, and scan down and extract
7315 the target address from the jump immediate instruction or, if a jump
7316 register instruction is used, from the register referred. Return
7317 the value of PC calculated or 0 if inconclusive.
7319 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7322 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7324 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7325 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7326 int addrreg
= MIPS_ZERO_REGNUM
;
7327 CORE_ADDR start_pc
= pc
;
7328 CORE_ADDR target_pc
= 0;
7335 status
== 0 && target_pc
== 0 && i
< 20;
7336 i
++, pc
+= MIPS_INSN32_SIZE
)
7338 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7344 switch (itype_op (inst
))
7346 case 0: /* SPECIAL */
7347 switch (rtype_funct (inst
))
7351 rs
= rtype_rs (inst
);
7352 if (rs
== MIPS_GP_REGNUM
)
7353 target_pc
= gp
; /* Hmm... */
7354 else if (rs
== addrreg
)
7358 case 0x21: /* ADDU */
7359 rt
= rtype_rt (inst
);
7360 rs
= rtype_rs (inst
);
7361 rd
= rtype_rd (inst
);
7362 if (rd
== MIPS_GP_REGNUM
7363 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7364 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7372 target_pc
= jtype_target (inst
) << 2;
7373 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7377 rt
= itype_rt (inst
);
7378 rs
= itype_rs (inst
);
7381 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7382 if (rt
== MIPS_GP_REGNUM
)
7384 else if (rt
== addrreg
)
7390 rt
= itype_rt (inst
);
7391 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7392 if (rt
== MIPS_GP_REGNUM
)
7394 else if (rt
!= MIPS_ZERO_REGNUM
)
7402 rt
= itype_rt (inst
);
7403 rs
= itype_rs (inst
);
7404 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7405 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7409 memset (buf
, 0, sizeof (buf
));
7410 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7412 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7421 /* If PC is in a MIPS16 call or return stub, return the address of the
7422 target PC, which is either the callee or the caller. There are several
7423 cases which must be handled:
7425 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7426 and the target PC is in $31 ($ra).
7427 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7428 and the target PC is in $2.
7429 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7430 i.e. before the JALR instruction, this is effectively a call stub
7431 and the target PC is in $2. Otherwise this is effectively
7432 a return stub and the target PC is in $18.
7433 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7434 JAL or JALR instruction, this is effectively a call stub and the
7435 target PC is buried in the instruction stream. Otherwise this
7436 is effectively a return stub and the target PC is in $18.
7437 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7438 stub and the target PC is buried in the instruction stream.
7440 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7441 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7445 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7447 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7448 CORE_ADDR start_addr
;
7452 /* Find the starting address and name of the function containing the PC. */
7453 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7456 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7457 and the target PC is in $31 ($ra). */
7458 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7459 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7460 && mips_is_stub_mode (name
+ prefixlen
)
7461 && name
[prefixlen
+ 2] == '\0')
7462 return get_frame_register_signed
7463 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7465 /* If the PC is in __mips16_call_stub_*, this is one of the call
7466 call/return stubs. */
7467 prefixlen
= strlen (mips_str_mips16_call_stub
);
7468 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7470 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7471 and the target PC is in $2. */
7472 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7473 return get_frame_register_signed
7474 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7476 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7477 i.e. before the JALR instruction, this is effectively a call stub
7478 and the target PC is in $2. Otherwise this is effectively
7479 a return stub and the target PC is in $18. */
7480 else if (mips_is_stub_mode (name
+ prefixlen
)
7481 && name
[prefixlen
+ 2] == '_'
7482 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7484 if (pc
== start_addr
)
7485 /* This is the 'call' part of a call stub. The return
7486 address is in $2. */
7487 return get_frame_register_signed
7488 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7490 /* This is the 'return' part of a call stub. The return
7491 address is in $18. */
7492 return get_frame_register_signed
7493 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7496 return 0; /* Not a stub. */
7499 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7500 compiler-generated call or call/return stubs. */
7501 if (strncmp (name
, mips_str_fn_stub
, strlen (mips_str_fn_stub
)) == 0
7502 || strncmp (name
, mips_str_call_stub
, strlen (mips_str_call_stub
)) == 0)
7504 if (pc
== start_addr
)
7505 /* This is the 'call' part of a call stub. Call this helper
7506 to scan through this code for interesting instructions
7507 and determine the final PC. */
7508 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7510 /* This is the 'return' part of a call stub. The return address
7512 return get_frame_register_signed
7513 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7516 return 0; /* Not a stub. */
7519 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7520 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7523 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7525 CORE_ADDR start_addr
;
7528 /* Find the starting address of the function containing the PC. */
7529 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7532 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7533 the start, i.e. after the JALR instruction, this is effectively
7535 prefixlen
= strlen (mips_str_mips16_call_stub
);
7536 if (pc
!= start_addr
7537 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7538 && mips_is_stub_mode (name
+ prefixlen
)
7539 && name
[prefixlen
+ 2] == '_'
7540 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7543 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7544 the JAL or JALR instruction, this is effectively a return stub. */
7545 prefixlen
= strlen (mips_str_call_fp_stub
);
7546 if (pc
!= start_addr
7547 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7550 /* Consume the .pic. prefix of any PIC stub, this function must return
7551 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7552 or the call stub path will trigger in handle_inferior_event causing
7554 prefixlen
= strlen (mips_str_pic
);
7555 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7558 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7559 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7560 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7561 && mips_is_stub_mode (name
+ prefixlen
)
7562 && name
[prefixlen
+ 2] == '\0')
7565 return 0; /* Not a stub. */
7568 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7569 PC of the stub target. The stub just loads $t9 and jumps to it,
7570 so that $t9 has the correct value at function entry. */
7573 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7575 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7576 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7577 struct minimal_symbol
*msym
;
7579 gdb_byte stub_code
[16];
7580 int32_t stub_words
[4];
7582 /* The stub for foo is named ".pic.foo", and is either two
7583 instructions inserted before foo or a three instruction sequence
7584 which jumps to foo. */
7585 msym
= lookup_minimal_symbol_by_pc (pc
);
7587 || SYMBOL_VALUE_ADDRESS (msym
) != pc
7588 || SYMBOL_LINKAGE_NAME (msym
) == NULL
7589 || strncmp (SYMBOL_LINKAGE_NAME (msym
), ".pic.", 5) != 0)
7592 /* A two-instruction header. */
7593 if (MSYMBOL_SIZE (msym
) == 8)
7596 /* A three-instruction (plus delay slot) trampoline. */
7597 if (MSYMBOL_SIZE (msym
) == 16)
7599 if (target_read_memory (pc
, stub_code
, 16) != 0)
7601 for (i
= 0; i
< 4; i
++)
7602 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7605 /* A stub contains these instructions:
7608 addiu t9, t9, %lo(target)
7611 This works even for N64, since stubs are only generated with
7613 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7614 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7615 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7616 && stub_words
[3] == 0x00000000)
7617 return ((((stub_words
[0] & 0x0000ffff) << 16)
7618 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7621 /* Not a recognized stub. */
7626 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7628 CORE_ADDR requested_pc
= pc
;
7629 CORE_ADDR target_pc
;
7636 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7640 if (is_compact_addr (pc
))
7641 pc
= unmake_compact_addr (pc
);
7644 new_pc
= find_solib_trampoline_target (frame
, pc
);
7648 if (is_compact_addr (pc
))
7649 pc
= unmake_compact_addr (pc
);
7652 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7656 if (is_compact_addr (pc
))
7657 pc
= unmake_compact_addr (pc
);
7660 while (pc
!= target_pc
);
7662 return pc
!= requested_pc
? pc
: 0;
7665 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7666 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7669 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7672 if (num
>= 0 && num
< 32)
7674 else if (num
>= 38 && num
< 70)
7675 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7677 regnum
= mips_regnum (gdbarch
)->hi
;
7679 regnum
= mips_regnum (gdbarch
)->lo
;
7680 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7681 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7683 /* This will hopefully (eventually) provoke a warning. Should
7684 we be calling complaint() here? */
7685 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7686 return gdbarch_num_regs (gdbarch
) + regnum
;
7690 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7691 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7694 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7697 if (num
>= 0 && num
< 32)
7699 else if (num
>= 32 && num
< 64)
7700 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7702 regnum
= mips_regnum (gdbarch
)->hi
;
7704 regnum
= mips_regnum (gdbarch
)->lo
;
7705 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7706 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7708 /* This will hopefully (eventually) provoke a warning. Should we
7709 be calling complaint() here? */
7710 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
7711 return gdbarch_num_regs (gdbarch
) + regnum
;
7715 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7717 /* Only makes sense to supply raw registers. */
7718 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7719 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7720 decide if it is valid. Should instead define a standard sim/gdb
7721 register numbering scheme. */
7722 if (gdbarch_register_name (gdbarch
,
7723 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7724 && gdbarch_register_name (gdbarch
,
7725 gdbarch_num_regs (gdbarch
)
7726 + regnum
)[0] != '\0')
7729 return LEGACY_SIM_REGNO_IGNORE
;
7733 /* Convert an integer into an address. Extracting the value signed
7734 guarantees a correctly sign extended address. */
7737 mips_integer_to_address (struct gdbarch
*gdbarch
,
7738 struct type
*type
, const gdb_byte
*buf
)
7740 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7741 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7744 /* Dummy virtual frame pointer method. This is no more or less accurate
7745 than most other architectures; we just need to be explicit about it,
7746 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7747 an assertion failure. */
7750 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7751 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7753 *reg
= MIPS_SP_REGNUM
;
7758 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7760 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7761 const char *name
= bfd_get_section_name (abfd
, sect
);
7763 if (*abip
!= MIPS_ABI_UNKNOWN
)
7766 if (strncmp (name
, ".mdebug.", 8) != 0)
7769 if (strcmp (name
, ".mdebug.abi32") == 0)
7770 *abip
= MIPS_ABI_O32
;
7771 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7772 *abip
= MIPS_ABI_N32
;
7773 else if (strcmp (name
, ".mdebug.abi64") == 0)
7774 *abip
= MIPS_ABI_N64
;
7775 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7776 *abip
= MIPS_ABI_O64
;
7777 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7778 *abip
= MIPS_ABI_EABI32
;
7779 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7780 *abip
= MIPS_ABI_EABI64
;
7782 warning (_("unsupported ABI %s."), name
+ 8);
7786 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
7788 int *lbp
= (int *) obj
;
7789 const char *name
= bfd_get_section_name (abfd
, sect
);
7791 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
7793 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
7795 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
7796 warning (_("unrecognized .gcc_compiled_longXX"));
7799 static enum mips_abi
7800 global_mips_abi (void)
7804 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
7805 if (mips_abi_strings
[i
] == mips_abi_string
)
7806 return (enum mips_abi
) i
;
7808 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
7811 /* Return the default compressed instruction set, either of MIPS16
7812 or microMIPS, selected when none could have been determined from
7813 the ELF header of the binary being executed (or no binary has been
7816 static enum mips_isa
7817 global_mips_compression (void)
7821 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
7822 if (mips_compression_strings
[i
] == mips_compression_string
)
7823 return (enum mips_isa
) i
;
7825 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
7829 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
7831 /* If the size matches the set of 32-bit or 64-bit integer registers,
7832 assume that's what we've got. */
7833 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
7834 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
7836 /* If the size matches the full set of registers GDB traditionally
7837 knows about, including floating point, for either 32-bit or
7838 64-bit, assume that's what we've got. */
7839 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
7840 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
7842 /* Otherwise we don't have a useful guess. */
7845 static struct value
*
7846 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
7848 const int *reg_p
= baton
;
7849 return value_of_register (*reg_p
, frame
);
7852 static struct gdbarch
*
7853 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
7855 struct gdbarch
*gdbarch
;
7856 struct gdbarch_tdep
*tdep
;
7858 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
7860 enum mips_fpu_type fpu_type
;
7861 struct tdesc_arch_data
*tdesc_data
= NULL
;
7862 int elf_fpu_type
= 0;
7863 const char **reg_names
;
7864 struct mips_regnum mips_regnum
, *regnum
;
7865 enum mips_isa mips_isa
;
7869 /* Fill in the OS dependent register numbers and names. */
7870 if (info
.osabi
== GDB_OSABI_IRIX
)
7872 mips_regnum
.fp0
= 32;
7873 mips_regnum
.pc
= 64;
7874 mips_regnum
.cause
= 65;
7875 mips_regnum
.badvaddr
= 66;
7876 mips_regnum
.hi
= 67;
7877 mips_regnum
.lo
= 68;
7878 mips_regnum
.fp_control_status
= 69;
7879 mips_regnum
.fp_implementation_revision
= 70;
7880 mips_regnum
.dspacc
= dspacc
= -1;
7881 mips_regnum
.dspctl
= dspctl
= -1;
7883 reg_names
= mips_irix_reg_names
;
7885 else if (info
.osabi
== GDB_OSABI_LINUX
)
7887 mips_regnum
.fp0
= 38;
7888 mips_regnum
.pc
= 37;
7889 mips_regnum
.cause
= 36;
7890 mips_regnum
.badvaddr
= 35;
7891 mips_regnum
.hi
= 34;
7892 mips_regnum
.lo
= 33;
7893 mips_regnum
.fp_control_status
= 70;
7894 mips_regnum
.fp_implementation_revision
= 71;
7895 mips_regnum
.dspacc
= -1;
7896 mips_regnum
.dspctl
= -1;
7900 reg_names
= mips_linux_reg_names
;
7904 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
7905 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
7906 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
7907 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
7908 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
7909 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
7910 mips_regnum
.fp_control_status
= 70;
7911 mips_regnum
.fp_implementation_revision
= 71;
7912 mips_regnum
.dspacc
= dspacc
= -1;
7913 mips_regnum
.dspctl
= dspctl
= -1;
7914 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
7915 if (info
.bfd_arch_info
!= NULL
7916 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
7917 reg_names
= mips_tx39_reg_names
;
7919 reg_names
= mips_generic_reg_names
;
7922 /* Check any target description for validity. */
7923 if (tdesc_has_registers (info
.target_desc
))
7925 static const char *const mips_gprs
[] = {
7926 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
7927 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
7928 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
7929 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
7931 static const char *const mips_fprs
[] = {
7932 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
7933 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
7934 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
7935 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
7938 const struct tdesc_feature
*feature
;
7941 feature
= tdesc_find_feature (info
.target_desc
,
7942 "org.gnu.gdb.mips.cpu");
7943 if (feature
== NULL
)
7946 tdesc_data
= tdesc_data_alloc ();
7949 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
7950 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
7954 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7955 mips_regnum
.lo
, "lo");
7956 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7957 mips_regnum
.hi
, "hi");
7958 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7959 mips_regnum
.pc
, "pc");
7963 tdesc_data_cleanup (tdesc_data
);
7967 feature
= tdesc_find_feature (info
.target_desc
,
7968 "org.gnu.gdb.mips.cp0");
7969 if (feature
== NULL
)
7971 tdesc_data_cleanup (tdesc_data
);
7976 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7977 mips_regnum
.badvaddr
, "badvaddr");
7978 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7979 MIPS_PS_REGNUM
, "status");
7980 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
7981 mips_regnum
.cause
, "cause");
7985 tdesc_data_cleanup (tdesc_data
);
7989 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
7990 backend is not prepared for that, though. */
7991 feature
= tdesc_find_feature (info
.target_desc
,
7992 "org.gnu.gdb.mips.fpu");
7993 if (feature
== NULL
)
7995 tdesc_data_cleanup (tdesc_data
);
8000 for (i
= 0; i
< 32; i
++)
8001 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8002 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8004 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8005 mips_regnum
.fp_control_status
,
8008 &= tdesc_numbered_register (feature
, tdesc_data
,
8009 mips_regnum
.fp_implementation_revision
,
8014 tdesc_data_cleanup (tdesc_data
);
8020 feature
= tdesc_find_feature (info
.target_desc
,
8021 "org.gnu.gdb.mips.dsp");
8022 /* The DSP registers are optional; it's OK if they are absent. */
8023 if (feature
!= NULL
)
8027 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8028 dspacc
+ i
++, "hi1");
8029 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8030 dspacc
+ i
++, "lo1");
8031 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8032 dspacc
+ i
++, "hi2");
8033 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8034 dspacc
+ i
++, "lo2");
8035 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8036 dspacc
+ i
++, "hi3");
8037 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8038 dspacc
+ i
++, "lo3");
8040 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
8045 tdesc_data_cleanup (tdesc_data
);
8049 mips_regnum
.dspacc
= dspacc
;
8050 mips_regnum
.dspctl
= dspctl
;
8054 /* It would be nice to detect an attempt to use a 64-bit ABI
8055 when only 32-bit registers are provided. */
8059 /* First of all, extract the elf_flags, if available. */
8060 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8061 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8062 else if (arches
!= NULL
)
8063 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8067 fprintf_unfiltered (gdb_stdlog
,
8068 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8070 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8071 switch ((elf_flags
& EF_MIPS_ABI
))
8073 case E_MIPS_ABI_O32
:
8074 found_abi
= MIPS_ABI_O32
;
8076 case E_MIPS_ABI_O64
:
8077 found_abi
= MIPS_ABI_O64
;
8079 case E_MIPS_ABI_EABI32
:
8080 found_abi
= MIPS_ABI_EABI32
;
8082 case E_MIPS_ABI_EABI64
:
8083 found_abi
= MIPS_ABI_EABI64
;
8086 if ((elf_flags
& EF_MIPS_ABI2
))
8087 found_abi
= MIPS_ABI_N32
;
8089 found_abi
= MIPS_ABI_UNKNOWN
;
8093 /* GCC creates a pseudo-section whose name describes the ABI. */
8094 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8095 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8097 /* If we have no useful BFD information, use the ABI from the last
8098 MIPS architecture (if there is one). */
8099 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8100 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8102 /* Try the architecture for any hint of the correct ABI. */
8103 if (found_abi
== MIPS_ABI_UNKNOWN
8104 && info
.bfd_arch_info
!= NULL
8105 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8107 switch (info
.bfd_arch_info
->mach
)
8109 case bfd_mach_mips3900
:
8110 found_abi
= MIPS_ABI_EABI32
;
8112 case bfd_mach_mips4100
:
8113 case bfd_mach_mips5000
:
8114 found_abi
= MIPS_ABI_EABI64
;
8116 case bfd_mach_mips8000
:
8117 case bfd_mach_mips10000
:
8118 /* On Irix, ELF64 executables use the N64 ABI. The
8119 pseudo-sections which describe the ABI aren't present
8120 on IRIX. (Even for executables created by gcc.) */
8121 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8122 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8123 found_abi
= MIPS_ABI_N64
;
8125 found_abi
= MIPS_ABI_N32
;
8130 /* Default 64-bit objects to N64 instead of O32. */
8131 if (found_abi
== MIPS_ABI_UNKNOWN
8132 && info
.abfd
!= NULL
8133 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8134 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8135 found_abi
= MIPS_ABI_N64
;
8138 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8141 /* What has the user specified from the command line? */
8142 wanted_abi
= global_mips_abi ();
8144 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8147 /* Now that we have found what the ABI for this binary would be,
8148 check whether the user is overriding it. */
8149 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8150 mips_abi
= wanted_abi
;
8151 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8152 mips_abi
= found_abi
;
8154 mips_abi
= MIPS_ABI_O32
;
8156 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8159 /* Determine the default compressed ISA. */
8160 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8161 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8162 mips_isa
= ISA_MICROMIPS
;
8163 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8164 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8165 mips_isa
= ISA_MIPS16
;
8167 mips_isa
= global_mips_compression ();
8168 mips_compression_string
= mips_compression_strings
[mips_isa
];
8170 /* Also used when doing an architecture lookup. */
8172 fprintf_unfiltered (gdb_stdlog
,
8173 "mips_gdbarch_init: "
8174 "mips64_transfers_32bit_regs_p = %d\n",
8175 mips64_transfers_32bit_regs_p
);
8177 /* Determine the MIPS FPU type. */
8180 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8181 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8182 Tag_GNU_MIPS_ABI_FP
);
8183 #endif /* HAVE_ELF */
8185 if (!mips_fpu_type_auto
)
8186 fpu_type
= mips_fpu_type
;
8187 else if (elf_fpu_type
!= 0)
8189 switch (elf_fpu_type
)
8192 fpu_type
= MIPS_FPU_DOUBLE
;
8195 fpu_type
= MIPS_FPU_SINGLE
;
8199 /* Soft float or unknown. */
8200 fpu_type
= MIPS_FPU_NONE
;
8204 else if (info
.bfd_arch_info
!= NULL
8205 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8206 switch (info
.bfd_arch_info
->mach
)
8208 case bfd_mach_mips3900
:
8209 case bfd_mach_mips4100
:
8210 case bfd_mach_mips4111
:
8211 case bfd_mach_mips4120
:
8212 fpu_type
= MIPS_FPU_NONE
;
8214 case bfd_mach_mips4650
:
8215 fpu_type
= MIPS_FPU_SINGLE
;
8218 fpu_type
= MIPS_FPU_DOUBLE
;
8221 else if (arches
!= NULL
)
8222 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
8224 fpu_type
= MIPS_FPU_DOUBLE
;
8226 fprintf_unfiltered (gdb_stdlog
,
8227 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8229 /* Check for blatant incompatibilities. */
8231 /* If we have only 32-bit registers, then we can't debug a 64-bit
8233 if (info
.target_desc
8234 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8235 && mips_abi
!= MIPS_ABI_EABI32
8236 && mips_abi
!= MIPS_ABI_O32
)
8238 if (tdesc_data
!= NULL
)
8239 tdesc_data_cleanup (tdesc_data
);
8243 /* Try to find a pre-existing architecture. */
8244 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8246 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8248 /* MIPS needs to be pedantic about which ABI the object is
8250 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8252 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8254 /* Need to be pedantic about which register virtual size is
8256 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8257 != mips64_transfers_32bit_regs_p
)
8259 /* Be pedantic about which FPU is selected. */
8260 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
8263 if (tdesc_data
!= NULL
)
8264 tdesc_data_cleanup (tdesc_data
);
8265 return arches
->gdbarch
;
8268 /* Need a new architecture. Fill in a target specific vector. */
8269 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
8270 gdbarch
= gdbarch_alloc (&info
, tdep
);
8271 tdep
->elf_flags
= elf_flags
;
8272 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8273 tdep
->found_abi
= found_abi
;
8274 tdep
->mips_abi
= mips_abi
;
8275 tdep
->mips_isa
= mips_isa
;
8276 tdep
->mips_fpu_type
= fpu_type
;
8277 tdep
->register_size_valid_p
= 0;
8278 tdep
->register_size
= 0;
8279 tdep
->gregset
= NULL
;
8280 tdep
->gregset64
= NULL
;
8281 tdep
->fpregset
= NULL
;
8282 tdep
->fpregset64
= NULL
;
8284 if (info
.target_desc
)
8286 /* Some useful properties can be inferred from the target. */
8287 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8289 tdep
->register_size_valid_p
= 1;
8290 tdep
->register_size
= 4;
8292 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8294 tdep
->register_size_valid_p
= 1;
8295 tdep
->register_size
= 8;
8299 /* Initially set everything according to the default ABI/ISA. */
8300 set_gdbarch_short_bit (gdbarch
, 16);
8301 set_gdbarch_int_bit (gdbarch
, 32);
8302 set_gdbarch_float_bit (gdbarch
, 32);
8303 set_gdbarch_double_bit (gdbarch
, 64);
8304 set_gdbarch_long_double_bit (gdbarch
, 64);
8305 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8306 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8307 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8309 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8310 mips_ax_pseudo_register_collect
);
8311 set_gdbarch_ax_pseudo_register_push_stack
8312 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8314 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8315 mips_elf_make_msymbol_special
);
8317 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8318 *regnum
= mips_regnum
;
8319 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8320 set_gdbarch_num_regs (gdbarch
, num_regs
);
8321 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8322 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8323 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8324 tdep
->mips_processor_reg_names
= reg_names
;
8325 tdep
->regnum
= regnum
;
8330 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8331 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8332 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8333 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8334 tdep
->default_mask_address_p
= 0;
8335 set_gdbarch_long_bit (gdbarch
, 32);
8336 set_gdbarch_ptr_bit (gdbarch
, 32);
8337 set_gdbarch_long_long_bit (gdbarch
, 64);
8340 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8341 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8342 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8343 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8344 tdep
->default_mask_address_p
= 0;
8345 set_gdbarch_long_bit (gdbarch
, 32);
8346 set_gdbarch_ptr_bit (gdbarch
, 32);
8347 set_gdbarch_long_long_bit (gdbarch
, 64);
8349 case MIPS_ABI_EABI32
:
8350 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8351 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8352 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8353 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8354 tdep
->default_mask_address_p
= 0;
8355 set_gdbarch_long_bit (gdbarch
, 32);
8356 set_gdbarch_ptr_bit (gdbarch
, 32);
8357 set_gdbarch_long_long_bit (gdbarch
, 64);
8359 case MIPS_ABI_EABI64
:
8360 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8361 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8362 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8363 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8364 tdep
->default_mask_address_p
= 0;
8365 set_gdbarch_long_bit (gdbarch
, 64);
8366 set_gdbarch_ptr_bit (gdbarch
, 64);
8367 set_gdbarch_long_long_bit (gdbarch
, 64);
8370 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8371 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8372 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8373 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8374 tdep
->default_mask_address_p
= 0;
8375 set_gdbarch_long_bit (gdbarch
, 32);
8376 set_gdbarch_ptr_bit (gdbarch
, 32);
8377 set_gdbarch_long_long_bit (gdbarch
, 64);
8378 set_gdbarch_long_double_bit (gdbarch
, 128);
8379 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8382 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8383 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8384 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8385 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8386 tdep
->default_mask_address_p
= 0;
8387 set_gdbarch_long_bit (gdbarch
, 64);
8388 set_gdbarch_ptr_bit (gdbarch
, 64);
8389 set_gdbarch_long_long_bit (gdbarch
, 64);
8390 set_gdbarch_long_double_bit (gdbarch
, 128);
8391 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8394 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8397 /* GCC creates a pseudo-section whose name specifies the size of
8398 longs, since -mlong32 or -mlong64 may be used independent of
8399 other options. How those options affect pointer sizes is ABI and
8400 architecture dependent, so use them to override the default sizes
8401 set by the ABI. This table shows the relationship between ABI,
8402 -mlongXX, and size of pointers:
8404 ABI -mlongXX ptr bits
8405 --- -------- --------
8419 Note that for o32 and eabi32, pointers are always 32 bits
8420 regardless of any -mlongXX option. For all others, pointers and
8421 longs are the same, as set by -mlongXX or set by defaults. */
8423 if (info
.abfd
!= NULL
)
8427 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8430 set_gdbarch_long_bit (gdbarch
, long_bit
);
8434 case MIPS_ABI_EABI32
:
8439 case MIPS_ABI_EABI64
:
8440 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8443 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8448 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8449 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8452 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8453 flag in object files because to do so would make it impossible to
8454 link with libraries compiled without "-gp32". This is
8455 unnecessarily restrictive.
8457 We could solve this problem by adding "-gp32" multilibs to gcc,
8458 but to set this flag before gcc is built with such multilibs will
8459 break too many systems.''
8461 But even more unhelpfully, the default linker output target for
8462 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8463 for 64-bit programs - you need to change the ABI to change this,
8464 and not all gcc targets support that currently. Therefore using
8465 this flag to detect 32-bit mode would do the wrong thing given
8466 the current gcc - it would make GDB treat these 64-bit programs
8467 as 32-bit programs by default. */
8469 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8470 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8472 /* Add/remove bits from an address. The MIPS needs be careful to
8473 ensure that all 32 bit addresses are sign extended to 64 bits. */
8474 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8476 /* Unwind the frame. */
8477 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8478 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8479 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8481 /* Map debug register numbers onto internal register numbers. */
8482 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8483 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8484 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8485 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8486 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8487 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8489 /* MIPS version of CALL_DUMMY. */
8491 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8492 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8493 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8495 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8496 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8497 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8499 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8500 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
8501 set_gdbarch_remote_breakpoint_from_pc (gdbarch
,
8502 mips_remote_breakpoint_from_pc
);
8503 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8504 mips_adjust_breakpoint_address
);
8506 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8508 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
8510 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8511 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8512 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8514 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8516 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8518 if (mips_abi
== MIPS_ABI_N32
)
8519 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n32
);
8520 else if (mips_abi
== MIPS_ABI_N64
)
8521 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips_n64
);
8523 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8525 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8526 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8527 need to all be folded into the target vector. Since they are
8528 being used as guards for target_stopped_by_watchpoint, why not have
8529 target_stopped_by_watchpoint return the type of watchpoint that the code
8531 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8533 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8535 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8536 to support MIPS16. This is a bad thing. Make sure not to do it
8537 if we have an OS ABI that actually supports shared libraries, since
8538 shared library support is more important. If we have an OS someday
8539 that supports both shared libraries and MIPS16, we'll have to find
8540 a better place for these.
8541 macro/2012-04-25: But that applies to return trampolines only and
8542 currently no MIPS OS ABI uses shared libraries that have them. */
8543 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8545 set_gdbarch_single_step_through_delay (gdbarch
,
8546 mips_single_step_through_delay
);
8548 /* Virtual tables. */
8549 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8551 mips_register_g_packet_guesses (gdbarch
);
8553 /* Hook in OS ABI-specific overrides, if they have been registered. */
8554 info
.tdep_info
= (void *) tdesc_data
;
8555 gdbarch_init_osabi (info
, gdbarch
);
8557 /* The hook may have adjusted num_regs, fetch the final value and
8558 set pc_regnum and sp_regnum now that it has been fixed. */
8559 num_regs
= gdbarch_num_regs (gdbarch
);
8560 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8561 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8563 /* Unwind the frame. */
8564 dwarf2_append_unwinders (gdbarch
);
8565 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8566 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8567 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8568 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8569 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8570 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8571 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8572 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8573 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8577 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8578 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
8580 /* Override the normal target description methods to handle our
8581 dual real and pseudo registers. */
8582 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8583 set_gdbarch_register_reggroup_p (gdbarch
,
8584 mips_tdesc_register_reggroup_p
);
8586 num_regs
= gdbarch_num_regs (gdbarch
);
8587 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8588 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8589 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8592 /* Add ABI-specific aliases for the registers. */
8593 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8594 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8595 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8596 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8598 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8599 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8600 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8602 /* Add some other standard aliases. */
8603 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8604 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8605 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8607 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8608 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8609 value_of_mips_user_reg
,
8610 &mips_numeric_register_aliases
[i
].regnum
);
8616 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
8618 struct gdbarch_info info
;
8620 /* Force the architecture to update, and (if it's a MIPS architecture)
8621 mips_gdbarch_init will take care of the rest. */
8622 gdbarch_info_init (&info
);
8623 gdbarch_update_p (info
);
8626 /* Print out which MIPS ABI is in use. */
8629 show_mips_abi (struct ui_file
*file
,
8631 struct cmd_list_element
*ignored_cmd
,
8632 const char *ignored_value
)
8634 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
8637 "The MIPS ABI is unknown because the current architecture "
8641 enum mips_abi global_abi
= global_mips_abi ();
8642 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
8643 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8645 if (global_abi
== MIPS_ABI_UNKNOWN
)
8648 "The MIPS ABI is set automatically (currently \"%s\").\n",
8650 else if (global_abi
== actual_abi
)
8653 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8657 /* Probably shouldn't happen... */
8658 fprintf_filtered (file
,
8659 "The (auto detected) MIPS ABI \"%s\" is in use "
8660 "even though the user setting was \"%s\".\n",
8661 actual_abi_str
, mips_abi_strings
[global_abi
]);
8666 /* Print out which MIPS compressed ISA encoding is used. */
8669 show_mips_compression (struct ui_file
*file
, int from_tty
,
8670 struct cmd_list_element
*c
, const char *value
)
8672 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8677 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8679 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8683 int ef_mips_32bitmode
;
8684 /* Determine the ISA. */
8685 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8703 /* Determine the size of a pointer. */
8704 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8705 fprintf_unfiltered (file
,
8706 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8708 fprintf_unfiltered (file
,
8709 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8711 fprintf_unfiltered (file
,
8712 "mips_dump_tdep: ef_mips_arch = %d\n",
8714 fprintf_unfiltered (file
,
8715 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8716 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8717 fprintf_unfiltered (file
,
8719 "mips_mask_address_p() %d (default %d)\n",
8720 mips_mask_address_p (tdep
),
8721 tdep
->default_mask_address_p
);
8723 fprintf_unfiltered (file
,
8724 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8725 MIPS_DEFAULT_FPU_TYPE
,
8726 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
8727 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
8728 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
8730 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8731 MIPS_EABI (gdbarch
));
8732 fprintf_unfiltered (file
,
8733 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8734 MIPS_FPU_TYPE (gdbarch
),
8735 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
8736 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
8737 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
8741 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
8744 _initialize_mips_tdep (void)
8746 static struct cmd_list_element
*mipsfpulist
= NULL
;
8747 struct cmd_list_element
*c
;
8749 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8750 if (MIPS_ABI_LAST
+ 1
8751 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8752 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8754 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8756 mips_pdr_data
= register_objfile_data ();
8758 /* Create feature sets with the appropriate properties. The values
8759 are not important. */
8760 mips_tdesc_gp32
= allocate_target_description ();
8761 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8763 mips_tdesc_gp64
= allocate_target_description ();
8764 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8766 /* Add root prefix command for all "set mips"/"show mips" commands. */
8767 add_prefix_cmd ("mips", no_class
, set_mips_command
,
8768 _("Various MIPS specific commands."),
8769 &setmipscmdlist
, "set mips ", 0, &setlist
);
8771 add_prefix_cmd ("mips", no_class
, show_mips_command
,
8772 _("Various MIPS specific commands."),
8773 &showmipscmdlist
, "show mips ", 0, &showlist
);
8775 /* Allow the user to override the ABI. */
8776 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8777 &mips_abi_string
, _("\
8778 Set the MIPS ABI used by this program."), _("\
8779 Show the MIPS ABI used by this program."), _("\
8780 This option can be set to one of:\n\
8781 auto - the default ABI associated with the current binary\n\
8790 &setmipscmdlist
, &showmipscmdlist
);
8792 /* Allow the user to set the ISA to assume for compressed code if ELF
8793 file flags don't tell or there is no program file selected. This
8794 setting is updated whenever unambiguous ELF file flags are interpreted,
8795 and carried over to subsequent sessions. */
8796 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
8797 &mips_compression_string
, _("\
8798 Set the compressed ISA encoding used by MIPS code."), _("\
8799 Show the compressed ISA encoding used by MIPS code."), _("\
8800 Select the compressed ISA encoding used in functions that have no symbol\n\
8801 information available. The encoding can be set to either of:\n\
8804 and is updated automatically from ELF file flags if available."),
8806 show_mips_compression
,
8807 &setmipscmdlist
, &showmipscmdlist
);
8809 /* Let the user turn off floating point and set the fence post for
8810 heuristic_proc_start. */
8812 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
8813 _("Set use of MIPS floating-point coprocessor."),
8814 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
8815 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
8816 _("Select single-precision MIPS floating-point coprocessor."),
8818 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
8819 _("Select double-precision MIPS floating-point coprocessor."),
8821 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
8822 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
8823 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
8824 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
8825 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
8826 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
8827 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
8828 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
8829 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
8830 _("Select MIPS floating-point coprocessor automatically."),
8832 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
8833 _("Show current use of MIPS floating-point coprocessor target."),
8836 /* We really would like to have both "0" and "unlimited" work, but
8837 command.c doesn't deal with that. So make it a var_zinteger
8838 because the user can always use "999999" or some such for unlimited. */
8839 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
8840 &heuristic_fence_post
, _("\
8841 Set the distance searched for the start of a function."), _("\
8842 Show the distance searched for the start of a function."), _("\
8843 If you are debugging a stripped executable, GDB needs to search through the\n\
8844 program for the start of a function. This command sets the distance of the\n\
8845 search. The only need to set it is when debugging a stripped executable."),
8846 reinit_frame_cache_sfunc
,
8847 NULL
, /* FIXME: i18n: The distance searched for
8848 the start of a function is %s. */
8849 &setlist
, &showlist
);
8851 /* Allow the user to control whether the upper bits of 64-bit
8852 addresses should be zeroed. */
8853 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
8854 &mask_address_var
, _("\
8855 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
8856 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
8857 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
8858 allow GDB to determine the correct value."),
8859 NULL
, show_mask_address
,
8860 &setmipscmdlist
, &showmipscmdlist
);
8862 /* Allow the user to control the size of 32 bit registers within the
8863 raw remote packet. */
8864 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
8865 &mips64_transfers_32bit_regs_p
, _("\
8866 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8868 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
8870 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
8871 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
8872 64 bits for others. Use \"off\" to disable compatibility mode"),
8873 set_mips64_transfers_32bit_regs
,
8874 NULL
, /* FIXME: i18n: Compatibility with 64-bit
8875 MIPS target that transfers 32-bit
8876 quantities is %s. */
8877 &setlist
, &showlist
);
8879 /* Debug this files internals. */
8880 add_setshow_zinteger_cmd ("mips", class_maintenance
,
8882 Set mips debugging."), _("\
8883 Show mips debugging."), _("\
8884 When non-zero, mips specific debugging is enabled."),
8886 NULL
, /* FIXME: i18n: Mips debugging is
8888 &setdebuglist
, &showdebuglist
);