1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 #ifndef MIPS_DEFAULT_FPU_TYPE
146 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
148 static int mips_fpu_type_auto
= 1;
149 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
151 static int mips_debug
= 0;
153 /* Properties (for struct target_desc) describing the g/G packet
155 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
156 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
158 struct target_desc
*mips_tdesc_gp32
;
159 struct target_desc
*mips_tdesc_gp64
;
161 const struct mips_regnum
*
162 mips_regnum (struct gdbarch
*gdbarch
)
164 return gdbarch_tdep (gdbarch
)->regnum
;
168 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
170 return mips_regnum (gdbarch
)->fp0
+ 12;
173 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
175 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
177 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
179 #define MIPS_LAST_ARG_REGNUM(gdbarch) (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
181 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
183 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
184 functions to test, set, or clear bit 0 of addresses. */
187 is_mips16_addr (CORE_ADDR addr
)
193 unmake_mips16_addr (CORE_ADDR addr
)
195 return ((addr
) & ~(CORE_ADDR
) 1);
198 /* Return the MIPS ABI associated with GDBARCH. */
200 mips_abi (struct gdbarch
*gdbarch
)
202 return gdbarch_tdep (gdbarch
)->mips_abi
;
206 mips_isa_regsize (struct gdbarch
*gdbarch
)
208 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
210 /* If we know how big the registers are, use that size. */
211 if (tdep
->register_size_valid_p
)
212 return tdep
->register_size
;
214 /* Fall back to the previous behavior. */
215 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
216 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
219 /* Return the currently configured (or set) saved register size. */
222 mips_abi_regsize (struct gdbarch
*gdbarch
)
224 switch (mips_abi (gdbarch
))
226 case MIPS_ABI_EABI32
:
232 case MIPS_ABI_EABI64
:
234 case MIPS_ABI_UNKNOWN
:
237 internal_error (__FILE__
, __LINE__
, _("bad switch"));
241 /* Functions for setting and testing a bit in a minimal symbol that
242 marks it as 16-bit function. The MSB of the minimal symbol's
243 "info" field is used for this purpose.
245 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
246 i.e. refers to a 16-bit function, and sets a "special" bit in a
247 minimal symbol to mark it as a 16-bit function
249 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
252 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
254 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
256 MSYMBOL_INFO (msym
) = (char *)
257 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
258 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
263 msymbol_is_special (struct minimal_symbol
*msym
)
265 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
268 /* XFER a value from the big/little/left end of the register.
269 Depending on the size of the value it might occupy the entire
270 register or just part of it. Make an allowance for this, aligning
271 things accordingly. */
274 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
275 int reg_num
, int length
,
276 enum bfd_endian endian
, gdb_byte
*in
,
277 const gdb_byte
*out
, int buf_offset
)
281 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
282 /* Need to transfer the left or right part of the register, based on
283 the targets byte order. */
287 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
289 case BFD_ENDIAN_LITTLE
:
292 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
296 internal_error (__FILE__
, __LINE__
, _("bad switch"));
299 fprintf_unfiltered (gdb_stderr
,
300 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
301 reg_num
, reg_offset
, buf_offset
, length
);
302 if (mips_debug
&& out
!= NULL
)
305 fprintf_unfiltered (gdb_stdlog
, "out ");
306 for (i
= 0; i
< length
; i
++)
307 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
310 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
313 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
315 if (mips_debug
&& in
!= NULL
)
318 fprintf_unfiltered (gdb_stdlog
, "in ");
319 for (i
= 0; i
< length
; i
++)
320 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
323 fprintf_unfiltered (gdb_stdlog
, "\n");
326 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
327 compatiblity mode. A return value of 1 means that we have
328 physical 64-bit registers, but should treat them as 32-bit registers. */
331 mips2_fp_compat (struct frame_info
*frame
)
333 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
334 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
336 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
340 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
341 in all the places we deal with FP registers. PR gdb/413. */
342 /* Otherwise check the FR bit in the status register - it controls
343 the FP compatiblity mode. If it is clear we are in compatibility
345 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
352 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
354 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
356 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
358 static struct type
*mips_float_register_type (void);
359 static struct type
*mips_double_register_type (void);
361 /* The list of available "set mips " and "show mips " commands */
363 static struct cmd_list_element
*setmipscmdlist
= NULL
;
364 static struct cmd_list_element
*showmipscmdlist
= NULL
;
366 /* Integer registers 0 thru 31 are handled explicitly by
367 mips_register_name(). Processor specific registers 32 and above
368 are listed in the following tables. */
371 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
375 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
376 "sr", "lo", "hi", "bad", "cause", "pc",
377 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
378 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
379 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
380 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
381 "fsr", "fir", "" /*"fp" */ , "",
382 "", "", "", "", "", "", "", "",
383 "", "", "", "", "", "", "", "",
386 /* Names of IDT R3041 registers. */
388 static const char *mips_r3041_reg_names
[] = {
389 "sr", "lo", "hi", "bad", "cause", "pc",
390 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
391 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
392 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
393 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
394 "fsr", "fir", "", /*"fp" */ "",
395 "", "", "bus", "ccfg", "", "", "", "",
396 "", "", "port", "cmp", "", "", "epc", "prid",
399 /* Names of tx39 registers. */
401 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
402 "sr", "lo", "hi", "bad", "cause", "pc",
403 "", "", "", "", "", "", "", "",
404 "", "", "", "", "", "", "", "",
405 "", "", "", "", "", "", "", "",
406 "", "", "", "", "", "", "", "",
408 "", "", "", "", "", "", "", "",
409 "", "", "config", "cache", "debug", "depc", "epc", ""
412 /* Names of IRIX registers. */
413 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
414 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
415 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
416 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
417 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
418 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
422 /* Return the name of the register corresponding to REGNO. */
424 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
426 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
427 /* GPR names for all ABIs other than n32/n64. */
428 static char *mips_gpr_names
[] = {
429 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
430 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
431 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
432 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
435 /* GPR names for n32 and n64 ABIs. */
436 static char *mips_n32_n64_gpr_names
[] = {
437 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
438 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
439 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
440 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
443 enum mips_abi abi
= mips_abi (gdbarch
);
445 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
446 but then don't make the raw register names visible. */
447 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
448 if (regno
< gdbarch_num_regs (gdbarch
))
451 /* The MIPS integer registers are always mapped from 0 to 31. The
452 names of the registers (which reflects the conventions regarding
453 register use) vary depending on the ABI. */
454 if (0 <= rawnum
&& rawnum
< 32)
456 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
457 return mips_n32_n64_gpr_names
[rawnum
];
459 return mips_gpr_names
[rawnum
];
461 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
462 return tdesc_register_name (gdbarch
, rawnum
);
463 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
465 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
466 return tdep
->mips_processor_reg_names
[rawnum
- 32];
469 internal_error (__FILE__
, __LINE__
,
470 _("mips_register_name: bad register number %d"), rawnum
);
473 /* Return the groups that a MIPS register can be categorised into. */
476 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
477 struct reggroup
*reggroup
)
482 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
483 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
484 if (reggroup
== all_reggroup
)
486 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
487 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
488 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
489 (gdbarch), as not all architectures are multi-arch. */
490 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
491 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
492 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
494 if (reggroup
== float_reggroup
)
495 return float_p
&& pseudo
;
496 if (reggroup
== vector_reggroup
)
497 return vector_p
&& pseudo
;
498 if (reggroup
== general_reggroup
)
499 return (!vector_p
&& !float_p
) && pseudo
;
500 /* Save the pseudo registers. Need to make certain that any code
501 extracting register values from a saved register cache also uses
503 if (reggroup
== save_reggroup
)
504 return raw_p
&& pseudo
;
505 /* Restore the same pseudo register. */
506 if (reggroup
== restore_reggroup
)
507 return raw_p
&& pseudo
;
511 /* Return the groups that a MIPS register can be categorised into.
512 This version is only used if we have a target description which
513 describes real registers (and their groups). */
516 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
517 struct reggroup
*reggroup
)
519 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
520 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
523 /* Only save, restore, and display the pseudo registers. Need to
524 make certain that any code extracting register values from a
525 saved register cache also uses pseudo registers.
527 Note: saving and restoring the pseudo registers is slightly
528 strange; if we have 64 bits, we should save and restore all
529 64 bits. But this is hard and has little benefit. */
533 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
537 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
540 /* Map the symbol table registers which live in the range [1 *
541 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
542 registers. Take care of alignment and size problems. */
545 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
546 int cookednum
, gdb_byte
*buf
)
548 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
549 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
550 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
551 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
552 regcache_raw_read (regcache
, rawnum
, buf
);
553 else if (register_size (gdbarch
, rawnum
) >
554 register_size (gdbarch
, cookednum
))
556 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
557 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
558 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
560 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
563 internal_error (__FILE__
, __LINE__
, _("bad register size"));
567 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
568 struct regcache
*regcache
, int cookednum
,
571 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
572 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
573 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
574 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
575 regcache_raw_write (regcache
, rawnum
, buf
);
576 else if (register_size (gdbarch
, rawnum
) >
577 register_size (gdbarch
, cookednum
))
579 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
580 || gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
581 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
583 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
586 internal_error (__FILE__
, __LINE__
, _("bad register size"));
589 /* Table to translate MIPS16 register field to actual register number. */
590 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
592 /* Heuristic_proc_start may hunt through the text section for a long
593 time across a 2400 baud serial line. Allows the user to limit this
596 static unsigned int heuristic_fence_post
= 0;
598 /* Number of bytes of storage in the actual machine representation for
599 register N. NOTE: This defines the pseudo register type so need to
600 rebuild the architecture vector. */
602 static int mips64_transfers_32bit_regs_p
= 0;
605 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
606 struct cmd_list_element
*c
)
608 struct gdbarch_info info
;
609 gdbarch_info_init (&info
);
610 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
611 instead of relying on globals. Doing that would let generic code
612 handle the search for this specific architecture. */
613 if (!gdbarch_update_p (info
))
615 mips64_transfers_32bit_regs_p
= 0;
616 error (_("32-bit compatibility mode not supported"));
620 /* Convert to/from a register and the corresponding memory value. */
623 mips_convert_register_p (struct gdbarch
*gdbarch
, int regnum
, struct type
*type
)
625 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
626 && register_size (gdbarch
, regnum
) == 4
627 && (regnum
% gdbarch_num_regs (gdbarch
))
628 >= mips_regnum (gdbarch
)->fp0
629 && (regnum
% gdbarch_num_regs (gdbarch
))
630 < mips_regnum (gdbarch
)->fp0
+ 32
631 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
635 mips_register_to_value (struct frame_info
*frame
, int regnum
,
636 struct type
*type
, gdb_byte
*to
)
638 get_frame_register (frame
, regnum
+ 0, to
+ 4);
639 get_frame_register (frame
, regnum
+ 1, to
+ 0);
643 mips_value_to_register (struct frame_info
*frame
, int regnum
,
644 struct type
*type
, const gdb_byte
*from
)
646 put_frame_register (frame
, regnum
+ 0, from
+ 4);
647 put_frame_register (frame
, regnum
+ 1, from
+ 0);
650 /* Return the GDB type object for the "standard" data type of data in
654 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
656 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
657 if ((regnum
% gdbarch_num_regs (gdbarch
)) >= mips_regnum (gdbarch
)->fp0
658 && (regnum
% gdbarch_num_regs (gdbarch
))
659 < mips_regnum (gdbarch
)->fp0
+ 32)
661 /* The floating-point registers raw, or cooked, always match
662 mips_isa_regsize(), and also map 1:1, byte for byte. */
663 if (mips_isa_regsize (gdbarch
) == 4)
664 return builtin_type_ieee_single
;
666 return builtin_type_ieee_double
;
668 else if (regnum
< gdbarch_num_regs (gdbarch
))
670 /* The raw or ISA registers. These are all sized according to
672 if (mips_isa_regsize (gdbarch
) == 4)
673 return builtin_type_int32
;
675 return builtin_type_int64
;
679 /* The cooked or ABI registers. These are sized according to
680 the ABI (with a few complications). */
681 if (regnum
>= (gdbarch_num_regs (gdbarch
)
682 + mips_regnum (gdbarch
)->fp_control_status
)
683 && regnum
<= gdbarch_num_regs (gdbarch
) + MIPS_LAST_EMBED_REGNUM
)
684 /* The pseudo/cooked view of the embedded registers is always
685 32-bit. The raw view is handled below. */
686 return builtin_type_int32
;
687 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
688 /* The target, while possibly using a 64-bit register buffer,
689 is only transfering 32-bits of each integer register.
690 Reflect this in the cooked/pseudo (ABI) register value. */
691 return builtin_type_int32
;
692 else if (mips_abi_regsize (gdbarch
) == 4)
693 /* The ABI is restricted to 32-bit registers (the ISA could be
695 return builtin_type_int32
;
698 return builtin_type_int64
;
702 /* Return the GDB type for the pseudo register REGNUM, which is the
703 ABI-level view. This function is only called if there is a target
704 description which includes registers, so we know precisely the
705 types of hardware registers. */
708 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
710 const int num_regs
= gdbarch_num_regs (gdbarch
);
711 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
712 int rawnum
= regnum
% num_regs
;
713 struct type
*rawtype
;
715 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
717 /* Absent registers are still absent. */
718 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
719 if (TYPE_LENGTH (rawtype
) == 0)
722 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
723 /* Present the floating point registers however the hardware did;
724 do not try to convert between FPU layouts. */
727 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
729 /* The pseudo/cooked view of embedded registers is always
730 32-bit, even if the target transfers 64-bit values for them.
731 New targets relying on XML descriptions should only transfer
732 the necessary 32 bits, but older versions of GDB expected 64,
733 so allow the target to provide 64 bits without interfering
734 with the displayed type. */
735 return builtin_type_int32
;
738 /* Use pointer types for registers if we can. For n32 we can not,
739 since we do not have a 64-bit pointer type. */
740 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
742 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
743 return builtin_type_void_data_ptr
;
744 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
745 return builtin_type_void_func_ptr
;
748 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
749 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
750 return builtin_type_int32
;
752 /* For all other registers, pass through the hardware type. */
756 /* Should the upper word of 64-bit addresses be zeroed? */
757 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
760 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
762 switch (mask_address_var
)
764 case AUTO_BOOLEAN_TRUE
:
766 case AUTO_BOOLEAN_FALSE
:
769 case AUTO_BOOLEAN_AUTO
:
770 return tdep
->default_mask_address_p
;
772 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
778 show_mask_address (struct ui_file
*file
, int from_tty
,
779 struct cmd_list_element
*c
, const char *value
)
781 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch
);
783 deprecated_show_value_hack (file
, from_tty
, c
, value
);
784 switch (mask_address_var
)
786 case AUTO_BOOLEAN_TRUE
:
787 printf_filtered ("The 32 bit mips address mask is enabled\n");
789 case AUTO_BOOLEAN_FALSE
:
790 printf_filtered ("The 32 bit mips address mask is disabled\n");
792 case AUTO_BOOLEAN_AUTO
:
794 ("The 32 bit address mask is set automatically. Currently %s\n",
795 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
798 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
803 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
806 mips_pc_is_mips16 (CORE_ADDR memaddr
)
808 struct minimal_symbol
*sym
;
810 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
811 if (is_mips16_addr (memaddr
))
814 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
815 the high bit of the info field. Use this to decide if the function is
816 MIPS16 or normal MIPS. */
817 sym
= lookup_minimal_symbol_by_pc (memaddr
);
819 return msymbol_is_special (sym
);
824 /* MIPS believes that the PC has a sign extended value. Perhaps the
825 all registers should be sign extended for simplicity? */
828 mips_read_pc (struct regcache
*regcache
)
831 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
832 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
837 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
839 return frame_unwind_register_signed
840 (next_frame
, gdbarch_num_regs (gdbarch
) + mips_regnum (gdbarch
)->pc
);
844 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
846 return frame_unwind_register_signed
847 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
850 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
851 dummy frame. The frame ID's base needs to match the TOS value
852 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
855 static struct frame_id
856 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
858 return frame_id_build
859 (get_frame_register_signed (this_frame
,
860 gdbarch_num_regs (gdbarch
)
862 get_frame_pc (this_frame
));
866 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
868 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
869 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
872 /* Fetch and return instruction from the specified location. If the PC
873 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
876 mips_fetch_instruction (CORE_ADDR addr
)
878 gdb_byte buf
[MIPS_INSN32_SIZE
];
882 if (mips_pc_is_mips16 (addr
))
884 instlen
= MIPS_INSN16_SIZE
;
885 addr
= unmake_mips16_addr (addr
);
888 instlen
= MIPS_INSN32_SIZE
;
889 status
= target_read_memory (addr
, buf
, instlen
);
891 memory_error (status
, addr
);
892 return extract_unsigned_integer (buf
, instlen
);
895 /* These the fields of 32 bit mips instructions */
896 #define mips32_op(x) (x >> 26)
897 #define itype_op(x) (x >> 26)
898 #define itype_rs(x) ((x >> 21) & 0x1f)
899 #define itype_rt(x) ((x >> 16) & 0x1f)
900 #define itype_immediate(x) (x & 0xffff)
902 #define jtype_op(x) (x >> 26)
903 #define jtype_target(x) (x & 0x03ffffff)
905 #define rtype_op(x) (x >> 26)
906 #define rtype_rs(x) ((x >> 21) & 0x1f)
907 #define rtype_rt(x) ((x >> 16) & 0x1f)
908 #define rtype_rd(x) ((x >> 11) & 0x1f)
909 #define rtype_shamt(x) ((x >> 6) & 0x1f)
910 #define rtype_funct(x) (x & 0x3f)
913 mips32_relative_offset (ULONGEST inst
)
915 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
918 /* Determine where to set a single step breakpoint while considering
919 branch prediction. */
921 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
925 inst
= mips_fetch_instruction (pc
);
926 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
928 if (itype_op (inst
) >> 2 == 5)
929 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
931 op
= (itype_op (inst
) & 0x03);
946 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
947 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
949 int tf
= itype_rt (inst
) & 0x01;
950 int cnum
= itype_rt (inst
) >> 2;
952 get_frame_register_signed (frame
,
953 mips_regnum (get_frame_arch (frame
))->
955 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
957 if (((cond
>> cnum
) & 0x01) == tf
)
958 pc
+= mips32_relative_offset (inst
) + 4;
963 pc
+= 4; /* Not a branch, next instruction is easy */
966 { /* This gets way messy */
968 /* Further subdivide into SPECIAL, REGIMM and other */
969 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
971 case 0: /* SPECIAL */
972 op
= rtype_funct (inst
);
977 /* Set PC to that address */
978 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
980 case 12: /* SYSCALL */
982 struct gdbarch_tdep
*tdep
;
984 tdep
= gdbarch_tdep (get_frame_arch (frame
));
985 if (tdep
->syscall_next_pc
!= NULL
)
986 pc
= tdep
->syscall_next_pc (frame
);
995 break; /* end SPECIAL */
998 op
= itype_rt (inst
); /* branch condition */
1003 case 16: /* BLTZAL */
1004 case 18: /* BLTZALL */
1006 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1007 pc
+= mips32_relative_offset (inst
) + 4;
1009 pc
+= 8; /* after the delay slot */
1013 case 17: /* BGEZAL */
1014 case 19: /* BGEZALL */
1015 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1016 pc
+= mips32_relative_offset (inst
) + 4;
1018 pc
+= 8; /* after the delay slot */
1020 /* All of the other instructions in the REGIMM category */
1025 break; /* end REGIMM */
1030 reg
= jtype_target (inst
) << 2;
1031 /* Upper four bits get never changed... */
1032 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1035 /* FIXME case JALX : */
1038 reg
= jtype_target (inst
) << 2;
1039 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1040 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1042 break; /* The new PC will be alternate mode */
1043 case 4: /* BEQ, BEQL */
1045 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1046 get_frame_register_signed (frame
, itype_rt (inst
)))
1047 pc
+= mips32_relative_offset (inst
) + 4;
1051 case 5: /* BNE, BNEL */
1053 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1054 get_frame_register_signed (frame
, itype_rt (inst
)))
1055 pc
+= mips32_relative_offset (inst
) + 4;
1059 case 6: /* BLEZ, BLEZL */
1060 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1061 pc
+= mips32_relative_offset (inst
) + 4;
1067 greater_branch
: /* BGTZ, BGTZL */
1068 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1069 pc
+= mips32_relative_offset (inst
) + 4;
1076 } /* mips32_next_pc */
1078 /* Decoding the next place to set a breakpoint is irregular for the
1079 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1080 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1081 We dont want to set a single step instruction on the extend instruction
1085 /* Lots of mips16 instruction formats */
1086 /* Predicting jumps requires itype,ritype,i8type
1087 and their extensions extItype,extritype,extI8type
1089 enum mips16_inst_fmts
1091 itype
, /* 0 immediate 5,10 */
1092 ritype
, /* 1 5,3,8 */
1093 rrtype
, /* 2 5,3,3,5 */
1094 rritype
, /* 3 5,3,3,5 */
1095 rrrtype
, /* 4 5,3,3,3,2 */
1096 rriatype
, /* 5 5,3,3,1,4 */
1097 shifttype
, /* 6 5,3,3,3,2 */
1098 i8type
, /* 7 5,3,8 */
1099 i8movtype
, /* 8 5,3,3,5 */
1100 i8mov32rtype
, /* 9 5,3,5,3 */
1101 i64type
, /* 10 5,3,8 */
1102 ri64type
, /* 11 5,3,3,5 */
1103 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1104 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1105 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1106 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1107 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1108 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1109 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1110 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1111 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1112 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1114 /* I am heaping all the fields of the formats into one structure and
1115 then, only the fields which are involved in instruction extension */
1119 unsigned int regx
; /* Function in i8 type */
1124 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1125 for the bits which make up the immediate extension. */
1128 extended_offset (unsigned int extension
)
1131 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1133 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1135 value
|= extension
& 0x01f; /* extract 4:0 */
1139 /* Only call this function if you know that this is an extendable
1140 instruction. It won't malfunction, but why make excess remote memory
1141 references? If the immediate operands get sign extended or something,
1142 do it after the extension is performed. */
1143 /* FIXME: Every one of these cases needs to worry about sign extension
1144 when the offset is to be used in relative addressing. */
1147 fetch_mips_16 (CORE_ADDR pc
)
1150 pc
&= 0xfffffffe; /* clear the low order bit */
1151 target_read_memory (pc
, buf
, 2);
1152 return extract_unsigned_integer (buf
, 2);
1156 unpack_mips16 (CORE_ADDR pc
,
1157 unsigned int extension
,
1159 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1164 switch (insn_format
)
1171 value
= extended_offset (extension
);
1172 value
= value
<< 11; /* rom for the original value */
1173 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1177 value
= inst
& 0x7ff;
1178 /* FIXME : Consider sign extension */
1187 { /* A register identifier and an offset */
1188 /* Most of the fields are the same as I type but the
1189 immediate value is of a different length */
1193 value
= extended_offset (extension
);
1194 value
= value
<< 8; /* from the original instruction */
1195 value
|= inst
& 0xff; /* eleven bits from instruction */
1196 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1197 if (value
& 0x4000) /* test the sign bit , bit 26 */
1199 value
&= ~0x3fff; /* remove the sign bit */
1205 value
= inst
& 0xff; /* 8 bits */
1206 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1207 /* FIXME: Do sign extension , this format needs it */
1208 if (value
& 0x80) /* THIS CONFUSES ME */
1210 value
&= 0xef; /* remove the sign bit */
1220 unsigned long value
;
1221 unsigned int nexthalf
;
1222 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1223 value
= value
<< 16;
1224 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1232 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1234 upk
->offset
= offset
;
1241 add_offset_16 (CORE_ADDR pc
, int offset
)
1243 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1247 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1248 unsigned int extension
, unsigned int insn
)
1250 int op
= (insn
>> 11);
1253 case 2: /* Branch */
1256 struct upk_mips16 upk
;
1257 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1258 offset
= upk
.offset
;
1264 pc
+= (offset
<< 1) + 2;
1267 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1269 struct upk_mips16 upk
;
1270 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1271 pc
= add_offset_16 (pc
, upk
.offset
);
1272 if ((insn
>> 10) & 0x01) /* Exchange mode */
1273 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1280 struct upk_mips16 upk
;
1282 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1283 reg
= get_frame_register_signed (frame
, upk
.regx
);
1285 pc
+= (upk
.offset
<< 1) + 2;
1292 struct upk_mips16 upk
;
1294 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1295 reg
= get_frame_register_signed (frame
, upk
.regx
);
1297 pc
+= (upk
.offset
<< 1) + 2;
1302 case 12: /* I8 Formats btez btnez */
1304 struct upk_mips16 upk
;
1306 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1307 /* upk.regx contains the opcode */
1308 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1309 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1310 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1311 /* pc = add_offset_16(pc,upk.offset) ; */
1312 pc
+= (upk
.offset
<< 1) + 2;
1317 case 29: /* RR Formats JR, JALR, JALR-RA */
1319 struct upk_mips16 upk
;
1320 /* upk.fmt = rrtype; */
1325 upk
.regx
= (insn
>> 8) & 0x07;
1326 upk
.regy
= (insn
>> 5) & 0x07;
1334 break; /* Function return instruction */
1340 break; /* BOGUS Guess */
1342 pc
= get_frame_register_signed (frame
, reg
);
1349 /* This is an instruction extension. Fetch the real instruction
1350 (which follows the extension) and decode things based on
1354 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1367 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1369 unsigned int insn
= fetch_mips_16 (pc
);
1370 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1373 /* The mips_next_pc function supports single_step when the remote
1374 target monitor or stub is not developed enough to do a single_step.
1375 It works by decoding the current instruction and predicting where a
1376 branch will go. This isnt hard because all the data is available.
1377 The MIPS32 and MIPS16 variants are quite different. */
1379 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1381 if (is_mips16_addr (pc
))
1382 return mips16_next_pc (frame
, pc
);
1384 return mips32_next_pc (frame
, pc
);
1387 struct mips_frame_cache
1390 struct trad_frame_saved_reg
*saved_regs
;
1393 /* Set a register's saved stack address in temp_saved_regs. If an
1394 address has already been set for this register, do nothing; this
1395 way we will only recognize the first save of a given register in a
1398 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1399 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1400 Strictly speaking, only the second range is used as it is only second
1401 range (the ABI instead of ISA registers) that comes into play when finding
1402 saved registers in a frame. */
1405 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
1406 int regnum
, CORE_ADDR offset
)
1408 if (this_cache
!= NULL
1409 && this_cache
->saved_regs
[regnum
].addr
== -1)
1411 this_cache
->saved_regs
[regnum
+ 0 * gdbarch_num_regs (gdbarch
)].addr
1413 this_cache
->saved_regs
[regnum
+ 1 * gdbarch_num_regs (gdbarch
)].addr
1419 /* Fetch the immediate value from a MIPS16 instruction.
1420 If the previous instruction was an EXTEND, use it to extend
1421 the upper bits of the immediate value. This is a helper function
1422 for mips16_scan_prologue. */
1425 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1426 unsigned short inst
, /* current instruction */
1427 int nbits
, /* number of bits in imm field */
1428 int scale
, /* scale factor to be applied to imm */
1429 int is_signed
) /* is the imm field signed? */
1433 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1435 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1436 if (offset
& 0x8000) /* check for negative extend */
1437 offset
= 0 - (0x10000 - (offset
& 0xffff));
1438 return offset
| (inst
& 0x1f);
1442 int max_imm
= 1 << nbits
;
1443 int mask
= max_imm
- 1;
1444 int sign_bit
= max_imm
>> 1;
1446 offset
= inst
& mask
;
1447 if (is_signed
&& (offset
& sign_bit
))
1448 offset
= 0 - (max_imm
- offset
);
1449 return offset
* scale
;
1454 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1455 the associated FRAME_CACHE if not null.
1456 Return the address of the first instruction past the prologue. */
1459 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1460 struct frame_info
*this_frame
,
1461 struct mips_frame_cache
*this_cache
)
1464 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1466 long frame_offset
= 0; /* Size of stack frame. */
1467 long frame_adjust
= 0; /* Offset of FP from SP. */
1468 int frame_reg
= MIPS_SP_REGNUM
;
1469 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1470 unsigned inst
= 0; /* current instruction */
1471 unsigned entry_inst
= 0; /* the entry instruction */
1472 unsigned save_inst
= 0; /* the save instruction */
1475 int extend_bytes
= 0;
1476 int prev_extend_bytes
;
1477 CORE_ADDR end_prologue_addr
= 0;
1478 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1480 /* Can be called when there's no process, and hence when there's no
1482 if (this_frame
!= NULL
)
1483 sp
= get_frame_register_signed (this_frame
,
1484 gdbarch_num_regs (gdbarch
)
1489 if (limit_pc
> start_pc
+ 200)
1490 limit_pc
= start_pc
+ 200;
1492 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1494 /* Save the previous instruction. If it's an EXTEND, we'll extract
1495 the immediate offset extension from it in mips16_get_imm. */
1498 /* Fetch and decode the instruction. */
1499 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1501 /* Normally we ignore extend instructions. However, if it is
1502 not followed by a valid prologue instruction, then this
1503 instruction is not part of the prologue either. We must
1504 remember in this case to adjust the end_prologue_addr back
1506 if ((inst
& 0xf800) == 0xf000) /* extend */
1508 extend_bytes
= MIPS_INSN16_SIZE
;
1512 prev_extend_bytes
= extend_bytes
;
1515 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1516 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1518 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1519 if (offset
< 0) /* negative stack adjustment? */
1520 frame_offset
-= offset
;
1522 /* Exit loop if a positive stack adjustment is found, which
1523 usually means that the stack cleanup code in the function
1524 epilogue is reached. */
1527 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1529 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1530 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1531 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1533 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1535 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1536 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1537 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1539 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1541 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1542 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1544 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1546 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1547 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1549 else if (inst
== 0x673d) /* move $s1, $sp */
1554 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1556 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1557 frame_addr
= sp
+ offset
;
1559 frame_adjust
= offset
;
1561 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1563 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1564 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1565 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1567 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1569 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1570 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1571 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
1573 else if ((inst
& 0xf81f) == 0xe809
1574 && (inst
& 0x700) != 0x700) /* entry */
1575 entry_inst
= inst
; /* save for later processing */
1576 else if ((inst
& 0xff80) == 0x6480) /* save */
1578 save_inst
= inst
; /* save for later processing */
1579 if (prev_extend_bytes
) /* extend */
1580 save_inst
|= prev_inst
<< 16;
1582 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1583 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1584 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1586 /* This instruction is part of the prologue, but we don't
1587 need to do anything special to handle it. */
1591 /* This instruction is not an instruction typically found
1592 in a prologue, so we must have reached the end of the
1594 if (end_prologue_addr
== 0)
1595 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1599 /* The entry instruction is typically the first instruction in a function,
1600 and it stores registers at offsets relative to the value of the old SP
1601 (before the prologue). But the value of the sp parameter to this
1602 function is the new SP (after the prologue has been executed). So we
1603 can't calculate those offsets until we've seen the entire prologue,
1604 and can calculate what the old SP must have been. */
1605 if (entry_inst
!= 0)
1607 int areg_count
= (entry_inst
>> 8) & 7;
1608 int sreg_count
= (entry_inst
>> 6) & 3;
1610 /* The entry instruction always subtracts 32 from the SP. */
1613 /* Now we can calculate what the SP must have been at the
1614 start of the function prologue. */
1617 /* Check if a0-a3 were saved in the caller's argument save area. */
1618 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1620 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1621 offset
+= mips_abi_regsize (gdbarch
);
1624 /* Check if the ra register was pushed on the stack. */
1626 if (entry_inst
& 0x20)
1628 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1629 offset
-= mips_abi_regsize (gdbarch
);
1632 /* Check if the s0 and s1 registers were pushed on the stack. */
1633 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1635 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1636 offset
-= mips_abi_regsize (gdbarch
);
1640 /* The SAVE instruction is similar to ENTRY, except that defined by the
1641 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
1642 size of the frame is specified as an immediate field of instruction
1643 and an extended variation exists which lets additional registers and
1644 frame space to be specified. The instruction always treats registers
1645 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
1646 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
1648 static int args_table
[16] = {
1649 0, 0, 0, 0, 1, 1, 1, 1,
1650 2, 2, 2, 0, 3, 3, 4, -1,
1652 static int astatic_table
[16] = {
1653 0, 1, 2, 3, 0, 1, 2, 3,
1654 0, 1, 2, 4, 0, 1, 0, -1,
1656 int aregs
= (save_inst
>> 16) & 0xf;
1657 int xsregs
= (save_inst
>> 24) & 0x7;
1658 int args
= args_table
[aregs
];
1659 int astatic
= astatic_table
[aregs
];
1664 warning (_("Invalid number of argument registers encoded in SAVE."));
1669 warning (_("Invalid number of static registers encoded in SAVE."));
1673 /* For standard SAVE the frame size of 0 means 128. */
1674 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
1675 if (frame_size
== 0 && (save_inst
>> 16) == 0)
1678 frame_offset
+= frame_size
;
1680 /* Now we can calculate what the SP must have been at the
1681 start of the function prologue. */
1684 /* Check if A0-A3 were saved in the caller's argument save area. */
1685 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
1687 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1688 offset
+= mips_abi_regsize (gdbarch
);
1693 /* Check if the RA register was pushed on the stack. */
1694 if (save_inst
& 0x40)
1696 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1697 offset
-= mips_abi_regsize (gdbarch
);
1700 /* Check if the S8 register was pushed on the stack. */
1703 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
1704 offset
-= mips_abi_regsize (gdbarch
);
1707 /* Check if S2-S7 were pushed on the stack. */
1708 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
1710 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1711 offset
-= mips_abi_regsize (gdbarch
);
1714 /* Check if the S1 register was pushed on the stack. */
1715 if (save_inst
& 0x10)
1717 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
1718 offset
-= mips_abi_regsize (gdbarch
);
1720 /* Check if the S0 register was pushed on the stack. */
1721 if (save_inst
& 0x20)
1723 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
1724 offset
-= mips_abi_regsize (gdbarch
);
1727 /* Check if A0-A3 were pushed on the stack. */
1728 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
1730 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
1731 offset
-= mips_abi_regsize (gdbarch
);
1735 if (this_cache
!= NULL
)
1738 (get_frame_register_signed (this_frame
,
1739 gdbarch_num_regs (gdbarch
) + frame_reg
)
1740 + frame_offset
- frame_adjust
);
1741 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1742 be able to get rid of the assignment below, evetually. But it's
1743 still needed for now. */
1744 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
1745 + mips_regnum (gdbarch
)->pc
]
1746 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
1749 /* If we didn't reach the end of the prologue when scanning the function
1750 instructions, then set end_prologue_addr to the address of the
1751 instruction immediately after the last one we scanned. */
1752 if (end_prologue_addr
== 0)
1753 end_prologue_addr
= cur_pc
;
1755 return end_prologue_addr
;
1758 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1759 Procedures that use the 32-bit instruction set are handled by the
1760 mips_insn32 unwinder. */
1762 static struct mips_frame_cache
*
1763 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1765 struct mips_frame_cache
*cache
;
1767 if ((*this_cache
) != NULL
)
1768 return (*this_cache
);
1769 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1770 (*this_cache
) = cache
;
1771 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1773 /* Analyze the function prologue. */
1775 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
1776 CORE_ADDR start_addr
;
1778 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1779 if (start_addr
== 0)
1780 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
1781 /* We can't analyze the prologue if we couldn't find the begining
1783 if (start_addr
== 0)
1786 mips16_scan_prologue (start_addr
, pc
, this_frame
, *this_cache
);
1789 /* gdbarch_sp_regnum contains the value and not the address. */
1790 trad_frame_set_value (cache
->saved_regs
,
1791 gdbarch_num_regs (get_frame_arch (this_frame
))
1795 return (*this_cache
);
1799 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1800 struct frame_id
*this_id
)
1802 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1804 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
1807 static struct value
*
1808 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
1809 void **this_cache
, int regnum
)
1811 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1813 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1817 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
1818 struct frame_info
*this_frame
, void **this_cache
)
1820 CORE_ADDR pc
= get_frame_pc (this_frame
);
1821 if (mips_pc_is_mips16 (pc
))
1826 static const struct frame_unwind mips_insn16_frame_unwind
=
1829 mips_insn16_frame_this_id
,
1830 mips_insn16_frame_prev_register
,
1832 mips_insn16_frame_sniffer
1836 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
1839 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
1844 static const struct frame_base mips_insn16_frame_base
=
1846 &mips_insn16_frame_unwind
,
1847 mips_insn16_frame_base_address
,
1848 mips_insn16_frame_base_address
,
1849 mips_insn16_frame_base_address
1852 static const struct frame_base
*
1853 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
1855 CORE_ADDR pc
= get_frame_pc (this_frame
);
1856 if (mips_pc_is_mips16 (pc
))
1857 return &mips_insn16_frame_base
;
1862 /* Mark all the registers as unset in the saved_regs array
1863 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1866 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
1868 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1872 const int num_regs
= gdbarch_num_regs (gdbarch
);
1875 for (i
= 0; i
< num_regs
; i
++)
1877 this_cache
->saved_regs
[i
].addr
= -1;
1882 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1883 the associated FRAME_CACHE if not null.
1884 Return the address of the first instruction past the prologue. */
1887 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1888 struct frame_info
*this_frame
,
1889 struct mips_frame_cache
*this_cache
)
1892 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1895 int frame_reg
= MIPS_SP_REGNUM
;
1897 CORE_ADDR end_prologue_addr
= 0;
1898 int seen_sp_adjust
= 0;
1899 int load_immediate_bytes
= 0;
1900 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1901 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
1903 /* Can be called when there's no process, and hence when there's no
1905 if (this_frame
!= NULL
)
1906 sp
= get_frame_register_signed (this_frame
,
1907 gdbarch_num_regs (gdbarch
)
1912 if (limit_pc
> start_pc
+ 200)
1913 limit_pc
= start_pc
+ 200;
1918 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1920 unsigned long inst
, high_word
, low_word
;
1923 /* Fetch the instruction. */
1924 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1926 /* Save some code by pre-extracting some useful fields. */
1927 high_word
= (inst
>> 16) & 0xffff;
1928 low_word
= inst
& 0xffff;
1929 reg
= high_word
& 0x1f;
1931 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1932 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1933 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1935 if (low_word
& 0x8000) /* negative stack adjustment? */
1936 frame_offset
+= 0x10000 - low_word
;
1938 /* Exit loop if a positive stack adjustment is found, which
1939 usually means that the stack cleanup code in the function
1940 epilogue is reached. */
1944 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1945 && !regsize_is_64_bits
)
1947 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1949 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1950 && regsize_is_64_bits
)
1952 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1953 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ low_word
);
1955 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1957 /* Old gcc frame, r30 is virtual frame pointer. */
1958 if ((long) low_word
!= frame_offset
)
1959 frame_addr
= sp
+ low_word
;
1960 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1962 unsigned alloca_adjust
;
1965 frame_addr
= get_frame_register_signed
1966 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
1968 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1969 if (alloca_adjust
> 0)
1971 /* FP > SP + frame_size. This may be because of
1972 an alloca or somethings similar. Fix sp to
1973 "pre-alloca" value, and try again. */
1974 sp
+= alloca_adjust
;
1975 /* Need to reset the status of all registers. Otherwise,
1976 we will hit a guard that prevents the new address
1977 for each register to be recomputed during the second
1979 reset_saved_regs (gdbarch
, this_cache
);
1984 /* move $30,$sp. With different versions of gas this will be either
1985 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1986 Accept any one of these. */
1987 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1989 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1990 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1992 unsigned alloca_adjust
;
1995 frame_addr
= get_frame_register_signed
1996 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
1998 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1999 if (alloca_adjust
> 0)
2001 /* FP > SP + frame_size. This may be because of
2002 an alloca or somethings similar. Fix sp to
2003 "pre-alloca" value, and try again. */
2005 /* Need to reset the status of all registers. Otherwise,
2006 we will hit a guard that prevents the new address
2007 for each register to be recomputed during the second
2009 reset_saved_regs (gdbarch
, this_cache
);
2014 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
2015 && !regsize_is_64_bits
)
2017 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ low_word
);
2019 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
2020 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
2021 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
2022 || high_word
== 0x3c1c /* lui $gp,n */
2023 || high_word
== 0x279c /* addiu $gp,$gp,n */
2024 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
2025 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
2028 /* These instructions are part of the prologue, but we don't
2029 need to do anything special to handle them. */
2031 /* The instructions below load $at or $t0 with an immediate
2032 value in preparation for a stack adjustment via
2033 subu $sp,$sp,[$at,$t0]. These instructions could also
2034 initialize a local variable, so we accept them only before
2035 a stack adjustment instruction was seen. */
2036 else if (!seen_sp_adjust
2037 && (high_word
== 0x3c01 /* lui $at,n */
2038 || high_word
== 0x3c08 /* lui $t0,n */
2039 || high_word
== 0x3421 /* ori $at,$at,n */
2040 || high_word
== 0x3508 /* ori $t0,$t0,n */
2041 || high_word
== 0x3401 /* ori $at,$zero,n */
2042 || high_word
== 0x3408 /* ori $t0,$zero,n */
2045 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2049 /* This instruction is not an instruction typically found
2050 in a prologue, so we must have reached the end of the
2052 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2053 loop now? Why would we need to continue scanning the function
2055 if (end_prologue_addr
== 0)
2056 end_prologue_addr
= cur_pc
;
2060 if (this_cache
!= NULL
)
2063 (get_frame_register_signed (this_frame
,
2064 gdbarch_num_regs (gdbarch
) + frame_reg
)
2066 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2067 this assignment below, eventually. But it's still needed
2069 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2070 + mips_regnum (gdbarch
)->pc
]
2071 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2075 /* If we didn't reach the end of the prologue when scanning the function
2076 instructions, then set end_prologue_addr to the address of the
2077 instruction immediately after the last one we scanned. */
2078 /* brobecker/2004-10-10: I don't think this would ever happen, but
2079 we may as well be careful and do our best if we have a null
2080 end_prologue_addr. */
2081 if (end_prologue_addr
== 0)
2082 end_prologue_addr
= cur_pc
;
2084 /* In a frameless function, we might have incorrectly
2085 skipped some load immediate instructions. Undo the skipping
2086 if the load immediate was not followed by a stack adjustment. */
2087 if (load_immediate_bytes
&& !seen_sp_adjust
)
2088 end_prologue_addr
-= load_immediate_bytes
;
2090 return end_prologue_addr
;
2093 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2094 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2095 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2098 static struct mips_frame_cache
*
2099 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2101 struct mips_frame_cache
*cache
;
2103 if ((*this_cache
) != NULL
)
2104 return (*this_cache
);
2106 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2107 (*this_cache
) = cache
;
2108 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2110 /* Analyze the function prologue. */
2112 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2113 CORE_ADDR start_addr
;
2115 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2116 if (start_addr
== 0)
2117 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
2118 /* We can't analyze the prologue if we couldn't find the begining
2120 if (start_addr
== 0)
2123 mips32_scan_prologue (start_addr
, pc
, this_frame
, *this_cache
);
2126 /* gdbarch_sp_regnum contains the value and not the address. */
2127 trad_frame_set_value (cache
->saved_regs
,
2128 gdbarch_num_regs (get_frame_arch (this_frame
))
2132 return (*this_cache
);
2136 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2137 struct frame_id
*this_id
)
2139 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2141 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2144 static struct value
*
2145 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
2146 void **this_cache
, int regnum
)
2148 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2150 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2154 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
2155 struct frame_info
*this_frame
, void **this_cache
)
2157 CORE_ADDR pc
= get_frame_pc (this_frame
);
2158 if (! mips_pc_is_mips16 (pc
))
2163 static const struct frame_unwind mips_insn32_frame_unwind
=
2166 mips_insn32_frame_this_id
,
2167 mips_insn32_frame_prev_register
,
2169 mips_insn32_frame_sniffer
2173 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
2176 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
2181 static const struct frame_base mips_insn32_frame_base
=
2183 &mips_insn32_frame_unwind
,
2184 mips_insn32_frame_base_address
,
2185 mips_insn32_frame_base_address
,
2186 mips_insn32_frame_base_address
2189 static const struct frame_base
*
2190 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
2192 CORE_ADDR pc
= get_frame_pc (this_frame
);
2193 if (! mips_pc_is_mips16 (pc
))
2194 return &mips_insn32_frame_base
;
2199 static struct trad_frame_cache
*
2200 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2203 CORE_ADDR start_addr
;
2204 CORE_ADDR stack_addr
;
2205 struct trad_frame_cache
*this_trad_cache
;
2206 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2207 int num_regs
= gdbarch_num_regs (gdbarch
);
2209 if ((*this_cache
) != NULL
)
2210 return (*this_cache
);
2211 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2212 (*this_cache
) = this_trad_cache
;
2214 /* The return address is in the link register. */
2215 trad_frame_set_reg_realreg (this_trad_cache
,
2216 gdbarch_pc_regnum (gdbarch
),
2217 num_regs
+ MIPS_RA_REGNUM
);
2219 /* Frame ID, since it's a frameless / stackless function, no stack
2220 space is allocated and SP on entry is the current SP. */
2221 pc
= get_frame_pc (this_frame
);
2222 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2223 stack_addr
= get_frame_register_signed (this_frame
,
2224 num_regs
+ MIPS_SP_REGNUM
);
2225 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2227 /* Assume that the frame's base is the same as the
2229 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2231 return this_trad_cache
;
2235 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2236 struct frame_id
*this_id
)
2238 struct trad_frame_cache
*this_trad_cache
2239 = mips_stub_frame_cache (this_frame
, this_cache
);
2240 trad_frame_get_id (this_trad_cache
, this_id
);
2243 static struct value
*
2244 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
2245 void **this_cache
, int regnum
)
2247 struct trad_frame_cache
*this_trad_cache
2248 = mips_stub_frame_cache (this_frame
, this_cache
);
2249 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2253 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
2254 struct frame_info
*this_frame
, void **this_cache
)
2257 struct obj_section
*s
;
2258 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2260 /* Use the stub unwinder for unreadable code. */
2261 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2264 if (in_plt_section (pc
, NULL
))
2267 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2268 s
= find_pc_section (pc
);
2271 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2272 ".MIPS.stubs") == 0)
2278 static const struct frame_unwind mips_stub_frame_unwind
=
2281 mips_stub_frame_this_id
,
2282 mips_stub_frame_prev_register
,
2284 mips_stub_frame_sniffer
2288 mips_stub_frame_base_address (struct frame_info
*this_frame
,
2291 struct trad_frame_cache
*this_trad_cache
2292 = mips_stub_frame_cache (this_frame
, this_cache
);
2293 return trad_frame_get_this_base (this_trad_cache
);
2296 static const struct frame_base mips_stub_frame_base
=
2298 &mips_stub_frame_unwind
,
2299 mips_stub_frame_base_address
,
2300 mips_stub_frame_base_address
,
2301 mips_stub_frame_base_address
2304 static const struct frame_base
*
2305 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
2307 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
2308 return &mips_stub_frame_base
;
2313 /* mips_addr_bits_remove - remove useless address bits */
2316 mips_addr_bits_remove (CORE_ADDR addr
)
2318 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2319 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2320 /* This hack is a work-around for existing boards using PMON, the
2321 simulator, and any other 64-bit targets that doesn't have true
2322 64-bit addressing. On these targets, the upper 32 bits of
2323 addresses are ignored by the hardware. Thus, the PC or SP are
2324 likely to have been sign extended to all 1s by instruction
2325 sequences that load 32-bit addresses. For example, a typical
2326 piece of code that loads an address is this:
2328 lui $r2, <upper 16 bits>
2329 ori $r2, <lower 16 bits>
2331 But the lui sign-extends the value such that the upper 32 bits
2332 may be all 1s. The workaround is simply to mask off these
2333 bits. In the future, gcc may be changed to support true 64-bit
2334 addressing, and this masking will have to be disabled. */
2335 return addr
&= 0xffffffffUL
;
2340 /* Instructions used during single-stepping of atomic sequences. */
2341 #define LL_OPCODE 0x30
2342 #define LLD_OPCODE 0x34
2343 #define SC_OPCODE 0x38
2344 #define SCD_OPCODE 0x3c
2346 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
2347 instruction and ending with a SC/SCD instruction. If such a sequence
2348 is found, attempt to step through it. A breakpoint is placed at the end of
2352 deal_with_atomic_sequence (CORE_ADDR pc
)
2354 CORE_ADDR breaks
[2] = {-1, -1};
2356 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
2360 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2361 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2366 insn
= mips_fetch_instruction (loc
);
2367 /* Assume all atomic sequences start with a ll/lld instruction. */
2368 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
2371 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
2373 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2376 loc
+= MIPS_INSN32_SIZE
;
2377 insn
= mips_fetch_instruction (loc
);
2379 /* Assume that there is at most one branch in the atomic
2380 sequence. If a branch is found, put a breakpoint in its
2381 destination address. */
2382 switch (itype_op (insn
))
2384 case 0: /* SPECIAL */
2385 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
2386 return 0; /* fallback to the standard single-step code. */
2388 case 1: /* REGIMM */
2389 is_branch
= ((itype_rt (insn
) & 0xc0) == 0); /* B{LT,GE}Z* */
2393 return 0; /* fallback to the standard single-step code. */
2400 case 22: /* BLEZL */
2401 case 23: /* BGTTL */
2407 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
2412 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
2413 if (last_breakpoint
>= 1)
2414 return 0; /* More than one branch found, fallback to the
2415 standard single-step code. */
2416 breaks
[1] = branch_bp
;
2420 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
2424 /* Assume that the atomic sequence ends with a sc/scd instruction. */
2425 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
2428 loc
+= MIPS_INSN32_SIZE
;
2430 /* Insert a breakpoint right after the end of the atomic sequence. */
2433 /* Check for duplicated breakpoints. Check also for a breakpoint
2434 placed (branch instruction's destination) in the atomic sequence */
2435 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
2436 last_breakpoint
= 0;
2438 /* Effectively inserts the breakpoints. */
2439 for (index
= 0; index
<= last_breakpoint
; index
++)
2440 insert_single_step_breakpoint (breaks
[index
]);
2445 /* mips_software_single_step() is called just before we want to resume
2446 the inferior, if we want to single-step it but there is no hardware
2447 or kernel single-step support (MIPS on GNU/Linux for example). We find
2448 the target of the coming instruction and breakpoint it. */
2451 mips_software_single_step (struct frame_info
*frame
)
2453 CORE_ADDR pc
, next_pc
;
2455 pc
= get_frame_pc (frame
);
2456 if (deal_with_atomic_sequence (pc
))
2459 next_pc
= mips_next_pc (frame
, pc
);
2461 insert_single_step_breakpoint (next_pc
);
2465 /* Test whether the PC points to the return instruction at the
2466 end of a function. */
2469 mips_about_to_return (CORE_ADDR pc
)
2471 if (mips_pc_is_mips16 (pc
))
2472 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2473 generates a "jr $ra"; other times it generates code to load
2474 the return address from the stack to an accessible register (such
2475 as $a3), then a "jr" using that register. This second case
2476 is almost impossible to distinguish from an indirect jump
2477 used for switch statements, so we don't even try. */
2478 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2480 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2484 /* This fencepost looks highly suspicious to me. Removing it also
2485 seems suspicious as it could affect remote debugging across serial
2489 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2496 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
2498 fence
= start_pc
- heuristic_fence_post
;
2502 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2503 fence
= VM_MIN_ADDRESS
;
2505 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2507 /* search back for previous return */
2508 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2509 if (start_pc
< fence
)
2511 /* It's not clear to me why we reach this point when
2512 stop_soon, but with this test, at least we
2513 don't print out warnings for every child forked (eg, on
2514 decstation). 22apr93 rich@cygnus.com. */
2515 if (stop_soon
== NO_STOP_QUIETLY
)
2517 static int blurb_printed
= 0;
2519 warning (_("GDB can't find the start of the function at 0x%s."),
2524 /* This actually happens frequently in embedded
2525 development, when you first connect to a board
2526 and your stack pointer and pc are nowhere in
2527 particular. This message needs to give people
2528 in that situation enough information to
2529 determine that it's no big deal. */
2530 printf_filtered ("\n\
2531 GDB is unable to find the start of the function at 0x%s\n\
2532 and thus can't determine the size of that function's stack frame.\n\
2533 This means that GDB may be unable to access that stack frame, or\n\
2534 the frames below it.\n\
2535 This problem is most likely caused by an invalid program counter or\n\
2537 However, if you think GDB should simply search farther back\n\
2538 from 0x%s for code which looks like the beginning of a\n\
2539 function, you can increase the range of the search using the `set\n\
2540 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2547 else if (mips_pc_is_mips16 (start_pc
))
2549 unsigned short inst
;
2551 /* On MIPS16, any one of the following is likely to be the
2552 start of a function:
2558 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2559 inst
= mips_fetch_instruction (start_pc
);
2560 if ((inst
& 0xff80) == 0x6480) /* save */
2562 if (start_pc
- instlen
>= fence
)
2564 inst
= mips_fetch_instruction (start_pc
- instlen
);
2565 if ((inst
& 0xf800) == 0xf000) /* extend */
2566 start_pc
-= instlen
;
2570 else if (((inst
& 0xf81f) == 0xe809
2571 && (inst
& 0x700) != 0x700) /* entry */
2572 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2573 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2574 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2576 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2577 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2582 else if (mips_about_to_return (start_pc
))
2584 /* Skip return and its delay slot. */
2585 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2592 struct mips_objfile_private
2598 /* According to the current ABI, should the type be passed in a
2599 floating-point register (assuming that there is space)? When there
2600 is no FPU, FP are not even considered as possible candidates for
2601 FP registers and, consequently this returns false - forces FP
2602 arguments into integer registers. */
2605 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
2606 struct type
*arg_type
)
2608 return ((typecode
== TYPE_CODE_FLT
2609 || (MIPS_EABI (gdbarch
)
2610 && (typecode
== TYPE_CODE_STRUCT
2611 || typecode
== TYPE_CODE_UNION
)
2612 && TYPE_NFIELDS (arg_type
) == 1
2613 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2615 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
2618 /* On o32, argument passing in GPRs depends on the alignment of the type being
2619 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2622 mips_type_needs_double_align (struct type
*type
)
2624 enum type_code typecode
= TYPE_CODE (type
);
2626 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2628 else if (typecode
== TYPE_CODE_STRUCT
)
2630 if (TYPE_NFIELDS (type
) < 1)
2632 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2634 else if (typecode
== TYPE_CODE_UNION
)
2638 n
= TYPE_NFIELDS (type
);
2639 for (i
= 0; i
< n
; i
++)
2640 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2647 /* Adjust the address downward (direction of stack growth) so that it
2648 is correctly aligned for a new stack frame. */
2650 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2652 return align_down (addr
, 16);
2656 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2657 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2658 int nargs
, struct value
**args
, CORE_ADDR sp
,
2659 int struct_return
, CORE_ADDR struct_addr
)
2665 int stack_offset
= 0;
2666 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2667 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2668 int regsize
= mips_abi_regsize (gdbarch
);
2670 /* For shared libraries, "t9" needs to point at the function
2672 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2674 /* Set the return address register to point to the entry point of
2675 the program, where a breakpoint lies in wait. */
2676 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2678 /* First ensure that the stack and structure return address (if any)
2679 are properly aligned. The stack has to be at least 64-bit
2680 aligned even on 32-bit machines, because doubles must be 64-bit
2681 aligned. For n32 and n64, stack frames need to be 128-bit
2682 aligned, so we round to this widest known alignment. */
2684 sp
= align_down (sp
, 16);
2685 struct_addr
= align_down (struct_addr
, 16);
2687 /* Now make space on the stack for the args. We allocate more
2688 than necessary for EABI, because the first few arguments are
2689 passed in registers, but that's OK. */
2690 for (argnum
= 0; argnum
< nargs
; argnum
++)
2691 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2692 sp
-= align_up (len
, 16);
2695 fprintf_unfiltered (gdb_stdlog
,
2696 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2697 paddr_nz (sp
), (long) align_up (len
, 16));
2699 /* Initialize the integer and float register pointers. */
2700 argreg
= MIPS_A0_REGNUM
;
2701 float_argreg
= mips_fpa0_regnum (gdbarch
);
2703 /* The struct_return pointer occupies the first parameter-passing reg. */
2707 fprintf_unfiltered (gdb_stdlog
,
2708 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2709 argreg
, paddr_nz (struct_addr
));
2710 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2713 /* Now load as many as possible of the first arguments into
2714 registers, and push the rest onto the stack. Loop thru args
2715 from first to last. */
2716 for (argnum
= 0; argnum
< nargs
; argnum
++)
2718 const gdb_byte
*val
;
2719 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2720 struct value
*arg
= args
[argnum
];
2721 struct type
*arg_type
= check_typedef (value_type (arg
));
2722 int len
= TYPE_LENGTH (arg_type
);
2723 enum type_code typecode
= TYPE_CODE (arg_type
);
2726 fprintf_unfiltered (gdb_stdlog
,
2727 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2728 argnum
+ 1, len
, (int) typecode
);
2730 /* The EABI passes structures that do not fit in a register by
2733 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2735 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2736 typecode
= TYPE_CODE_PTR
;
2740 fprintf_unfiltered (gdb_stdlog
, " push");
2743 val
= value_contents (arg
);
2745 /* 32-bit ABIs always start floating point arguments in an
2746 even-numbered floating point register. Round the FP register
2747 up before the check to see if there are any FP registers
2748 left. Non MIPS_EABI targets also pass the FP in the integer
2749 registers so also round up normal registers. */
2750 if (regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2752 if ((float_argreg
& 1))
2756 /* Floating point arguments passed in registers have to be
2757 treated specially. On 32-bit architectures, doubles
2758 are passed in register pairs; the even register gets
2759 the low word, and the odd register gets the high word.
2760 On non-EABI processors, the first two floating point arguments are
2761 also copied to general registers, because MIPS16 functions
2762 don't use float registers for arguments. This duplication of
2763 arguments in general registers can't hurt non-MIPS16 functions
2764 because those registers are normally skipped. */
2765 /* MIPS_EABI squeezes a struct that contains a single floating
2766 point value into an FP register instead of pushing it onto the
2768 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
2769 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
2771 /* EABI32 will pass doubles in consecutive registers, even on
2772 64-bit cores. At one time, we used to check the size of
2773 `float_argreg' to determine whether or not to pass doubles
2774 in consecutive registers, but this is not sufficient for
2775 making the ABI determination. */
2776 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2778 int low_offset
= gdbarch_byte_order (gdbarch
)
2779 == BFD_ENDIAN_BIG
? 4 : 0;
2780 unsigned long regval
;
2782 /* Write the low word of the double to the even register(s). */
2783 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2785 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2786 float_argreg
, phex (regval
, 4));
2787 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2789 /* Write the high word of the double to the odd register(s). */
2790 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2792 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2793 float_argreg
, phex (regval
, 4));
2794 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2798 /* This is a floating point value that fits entirely
2799 in a single register. */
2800 /* On 32 bit ABI's the float_argreg is further adjusted
2801 above to ensure that it is even register aligned. */
2802 LONGEST regval
= extract_unsigned_integer (val
, len
);
2804 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2805 float_argreg
, phex (regval
, len
));
2806 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2811 /* Copy the argument to general registers or the stack in
2812 register-sized pieces. Large arguments are split between
2813 registers and stack. */
2814 /* Note: structs whose size is not a multiple of regsize
2815 are treated specially: Irix cc passes
2816 them in registers where gcc sometimes puts them on the
2817 stack. For maximum compatibility, we will put them in
2819 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2821 /* Note: Floating-point values that didn't fit into an FP
2822 register are only written to memory. */
2825 /* Remember if the argument was written to the stack. */
2826 int stack_used_p
= 0;
2827 int partial_len
= (len
< regsize
? len
: regsize
);
2830 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2833 /* Write this portion of the argument to the stack. */
2834 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
2836 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2838 /* Should shorter than int integer values be
2839 promoted to int before being stored? */
2840 int longword_offset
= 0;
2843 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2846 && (typecode
== TYPE_CODE_INT
2847 || typecode
== TYPE_CODE_PTR
2848 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2849 longword_offset
= regsize
- len
;
2850 else if ((typecode
== TYPE_CODE_STRUCT
2851 || typecode
== TYPE_CODE_UNION
)
2852 && TYPE_LENGTH (arg_type
) < regsize
)
2853 longword_offset
= regsize
- len
;
2858 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2859 paddr_nz (stack_offset
));
2860 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2861 paddr_nz (longword_offset
));
2864 addr
= sp
+ stack_offset
+ longword_offset
;
2869 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2871 for (i
= 0; i
< partial_len
; i
++)
2873 fprintf_unfiltered (gdb_stdlog
, "%02x",
2877 write_memory (addr
, val
, partial_len
);
2880 /* Note!!! This is NOT an else clause. Odd sized
2881 structs may go thru BOTH paths. Floating point
2882 arguments will not. */
2883 /* Write this portion of the argument to a general
2884 purpose register. */
2885 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
2886 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
2889 extract_unsigned_integer (val
, partial_len
);
2892 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2894 phex (regval
, regsize
));
2895 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2902 /* Compute the the offset into the stack at which we
2903 will copy the next parameter.
2905 In the new EABI (and the NABI32), the stack_offset
2906 only needs to be adjusted when it has been used. */
2909 stack_offset
+= align_up (partial_len
, regsize
);
2913 fprintf_unfiltered (gdb_stdlog
, "\n");
2916 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2918 /* Return adjusted stack pointer. */
2922 /* Determine the return value convention being used. */
2924 static enum return_value_convention
2925 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
2926 struct type
*type
, struct regcache
*regcache
,
2927 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2929 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2930 int fp_return_type
= 0;
2931 int offset
, regnum
, xfer
;
2933 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2934 return RETURN_VALUE_STRUCT_CONVENTION
;
2936 /* Floating point type? */
2937 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
2939 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2941 /* Structs with a single field of float type
2942 are returned in a floating point register. */
2943 if ((TYPE_CODE (type
) == TYPE_CODE_STRUCT
2944 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
2945 && TYPE_NFIELDS (type
) == 1)
2947 struct type
*fieldtype
= TYPE_FIELD_TYPE (type
, 0);
2949 if (TYPE_CODE (check_typedef (fieldtype
)) == TYPE_CODE_FLT
)
2956 /* A floating-point value belongs in the least significant part
2959 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
2960 regnum
= mips_regnum (gdbarch
)->fp0
;
2964 /* An integer value goes in V0/V1. */
2966 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
2967 regnum
= MIPS_V0_REGNUM
;
2970 offset
< TYPE_LENGTH (type
);
2971 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
2973 xfer
= mips_abi_regsize (gdbarch
);
2974 if (offset
+ xfer
> TYPE_LENGTH (type
))
2975 xfer
= TYPE_LENGTH (type
) - offset
;
2976 mips_xfer_register (gdbarch
, regcache
,
2977 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
2978 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
2982 return RETURN_VALUE_REGISTER_CONVENTION
;
2986 /* N32/N64 ABI stuff. */
2988 /* Search for a naturally aligned double at OFFSET inside a struct
2989 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
2993 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
2998 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
3001 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
3004 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
3007 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
3010 struct type
*field_type
;
3012 /* We're only looking at normal fields. */
3013 if (TYPE_FIELD_STATIC (arg_type
, i
)
3014 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
3017 /* If we have gone past the offset, there is no double to pass. */
3018 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
3022 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
3024 /* If this field is entirely before the requested offset, go
3025 on to the next one. */
3026 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
3029 /* If this is our special aligned double, we can stop. */
3030 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
3031 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
3034 /* This field starts at or before the requested offset, and
3035 overlaps it. If it is a structure, recurse inwards. */
3036 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
3043 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3044 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3045 int nargs
, struct value
**args
, CORE_ADDR sp
,
3046 int struct_return
, CORE_ADDR struct_addr
)
3052 int stack_offset
= 0;
3053 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3054 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3056 /* For shared libraries, "t9" needs to point at the function
3058 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3060 /* Set the return address register to point to the entry point of
3061 the program, where a breakpoint lies in wait. */
3062 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3064 /* First ensure that the stack and structure return address (if any)
3065 are properly aligned. The stack has to be at least 64-bit
3066 aligned even on 32-bit machines, because doubles must be 64-bit
3067 aligned. For n32 and n64, stack frames need to be 128-bit
3068 aligned, so we round to this widest known alignment. */
3070 sp
= align_down (sp
, 16);
3071 struct_addr
= align_down (struct_addr
, 16);
3073 /* Now make space on the stack for the args. */
3074 for (argnum
= 0; argnum
< nargs
; argnum
++)
3075 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
3076 sp
-= align_up (len
, 16);
3079 fprintf_unfiltered (gdb_stdlog
,
3080 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
3081 paddr_nz (sp
), (long) align_up (len
, 16));
3083 /* Initialize the integer and float register pointers. */
3084 argreg
= MIPS_A0_REGNUM
;
3085 float_argreg
= mips_fpa0_regnum (gdbarch
);
3087 /* The struct_return pointer occupies the first parameter-passing reg. */
3091 fprintf_unfiltered (gdb_stdlog
,
3092 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
3093 argreg
, paddr_nz (struct_addr
));
3094 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3097 /* Now load as many as possible of the first arguments into
3098 registers, and push the rest onto the stack. Loop thru args
3099 from first to last. */
3100 for (argnum
= 0; argnum
< nargs
; argnum
++)
3102 const gdb_byte
*val
;
3103 struct value
*arg
= args
[argnum
];
3104 struct type
*arg_type
= check_typedef (value_type (arg
));
3105 int len
= TYPE_LENGTH (arg_type
);
3106 enum type_code typecode
= TYPE_CODE (arg_type
);
3109 fprintf_unfiltered (gdb_stdlog
,
3110 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
3111 argnum
+ 1, len
, (int) typecode
);
3113 val
= value_contents (arg
);
3115 /* A 128-bit long double value requires an even-odd pair of
3116 floating-point registers. */
3118 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3119 && (float_argreg
& 1))
3125 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3126 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3128 /* This is a floating point value that fits entirely
3129 in a single register or a pair of registers. */
3130 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3131 LONGEST regval
= extract_unsigned_integer (val
, reglen
);
3133 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3134 float_argreg
, phex (regval
, reglen
));
3135 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3138 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3139 argreg
, phex (regval
, reglen
));
3140 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3145 regval
= extract_unsigned_integer (val
+ reglen
, reglen
);
3147 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3148 float_argreg
, phex (regval
, reglen
));
3149 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
3152 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3153 argreg
, phex (regval
, reglen
));
3154 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3161 /* Copy the argument to general registers or the stack in
3162 register-sized pieces. Large arguments are split between
3163 registers and stack. */
3164 /* For N32/N64, structs, unions, or other composite types are
3165 treated as a sequence of doublewords, and are passed in integer
3166 or floating point registers as though they were simple scalar
3167 parameters to the extent that they fit, with any excess on the
3168 stack packed according to the normal memory layout of the
3170 The caller does not reserve space for the register arguments;
3171 the callee is responsible for reserving it if required. */
3172 /* Note: Floating-point values that didn't fit into an FP
3173 register are only written to memory. */
3176 /* Remember if the argument was written to the stack. */
3177 int stack_used_p
= 0;
3178 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3181 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3184 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3185 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
3187 /* Write this portion of the argument to the stack. */
3188 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
3190 /* Should shorter than int integer values be
3191 promoted to int before being stored? */
3192 int longword_offset
= 0;
3195 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
3197 if ((typecode
== TYPE_CODE_INT
3198 || typecode
== TYPE_CODE_PTR
)
3200 longword_offset
= MIPS64_REGSIZE
- len
;
3205 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3206 paddr_nz (stack_offset
));
3207 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3208 paddr_nz (longword_offset
));
3211 addr
= sp
+ stack_offset
+ longword_offset
;
3216 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3218 for (i
= 0; i
< partial_len
; i
++)
3220 fprintf_unfiltered (gdb_stdlog
, "%02x",
3224 write_memory (addr
, val
, partial_len
);
3227 /* Note!!! This is NOT an else clause. Odd sized
3228 structs may go thru BOTH paths. */
3229 /* Write this portion of the argument to a general
3230 purpose register. */
3231 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3235 /* Sign extend pointers, 32-bit integers and signed
3236 16-bit and 8-bit integers; everything else is taken
3239 if ((partial_len
== 4
3240 && (typecode
== TYPE_CODE_PTR
3241 || typecode
== TYPE_CODE_INT
))
3243 && typecode
== TYPE_CODE_INT
3244 && !TYPE_UNSIGNED (arg_type
)))
3245 regval
= extract_signed_integer (val
, partial_len
);
3247 regval
= extract_unsigned_integer (val
, partial_len
);
3249 /* A non-floating-point argument being passed in a
3250 general register. If a struct or union, and if
3251 the remaining length is smaller than the register
3252 size, we have to adjust the register value on
3255 It does not seem to be necessary to do the
3256 same for integral types. */
3258 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3259 && partial_len
< MIPS64_REGSIZE
3260 && (typecode
== TYPE_CODE_STRUCT
3261 || typecode
== TYPE_CODE_UNION
))
3262 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3266 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3268 phex (regval
, MIPS64_REGSIZE
));
3269 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3271 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
3272 TYPE_LENGTH (arg_type
) - len
))
3275 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3277 phex (regval
, MIPS64_REGSIZE
));
3278 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3289 /* Compute the the offset into the stack at which we
3290 will copy the next parameter.
3292 In N32 (N64?), the stack_offset only needs to be
3293 adjusted when it has been used. */
3296 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3300 fprintf_unfiltered (gdb_stdlog
, "\n");
3303 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3305 /* Return adjusted stack pointer. */
3309 static enum return_value_convention
3310 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3311 struct type
*type
, struct regcache
*regcache
,
3312 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3314 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3316 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3318 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3319 if needed), as appropriate for the type. Composite results (struct,
3320 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3323 * A struct with only one or two floating point fields is returned in $f0
3324 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3327 * Any other struct or union results of at most 128 bits are returned in
3328 $2 (first 64 bits) and $3 (remainder, if necessary).
3330 * Larger composite results are handled by converting the function to a
3331 procedure with an implicit first parameter, which is a pointer to an area
3332 reserved by the caller to receive the result. [The o32-bit ABI requires
3333 that all composite results be handled by conversion to implicit first
3334 parameters. The MIPS/SGI Fortran implementation has always made a
3335 specific exception to return COMPLEX results in the floating point
3338 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3339 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3340 return RETURN_VALUE_STRUCT_CONVENTION
;
3341 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3342 && TYPE_LENGTH (type
) == 16
3343 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3345 /* A 128-bit floating-point value fills both $f0 and $f2. The
3346 two registers are used in the same as memory order, so the
3347 eight bytes with the lower memory address are in $f0. */
3349 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3350 mips_xfer_register (gdbarch
, regcache
,
3351 gdbarch_num_regs (gdbarch
)
3352 + mips_regnum (gdbarch
)->fp0
,
3353 8, gdbarch_byte_order (gdbarch
),
3354 readbuf
, writebuf
, 0);
3355 mips_xfer_register (gdbarch
, regcache
,
3356 gdbarch_num_regs (gdbarch
)
3357 + mips_regnum (gdbarch
)->fp0
+ 2,
3358 8, gdbarch_byte_order (gdbarch
),
3359 readbuf
? readbuf
+ 8 : readbuf
,
3360 writebuf
? writebuf
+ 8 : writebuf
, 0);
3361 return RETURN_VALUE_REGISTER_CONVENTION
;
3363 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3364 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3366 /* A single or double floating-point value that fits in FP0. */
3368 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3369 mips_xfer_register (gdbarch
, regcache
,
3370 gdbarch_num_regs (gdbarch
)
3371 + mips_regnum (gdbarch
)->fp0
,
3373 gdbarch_byte_order (gdbarch
),
3374 readbuf
, writebuf
, 0);
3375 return RETURN_VALUE_REGISTER_CONVENTION
;
3377 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3378 && TYPE_NFIELDS (type
) <= 2
3379 && TYPE_NFIELDS (type
) >= 1
3380 && ((TYPE_NFIELDS (type
) == 1
3381 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3383 || (TYPE_NFIELDS (type
) == 2
3384 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3386 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3387 == TYPE_CODE_FLT
))))
3389 /* A struct that contains one or two floats. Each value is part
3390 in the least significant part of their floating point
3391 register (or GPR, for soft float). */
3394 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
3395 ? mips_regnum (gdbarch
)->fp0
3397 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3399 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3402 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3404 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)) == 16)
3406 /* A 16-byte long double field goes in two consecutive
3408 mips_xfer_register (gdbarch
, regcache
,
3409 gdbarch_num_regs (gdbarch
) + regnum
,
3411 gdbarch_byte_order (gdbarch
),
3412 readbuf
, writebuf
, offset
);
3413 mips_xfer_register (gdbarch
, regcache
,
3414 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
3416 gdbarch_byte_order (gdbarch
),
3417 readbuf
, writebuf
, offset
+ 8);
3420 mips_xfer_register (gdbarch
, regcache
,
3421 gdbarch_num_regs (gdbarch
) + regnum
,
3422 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3423 gdbarch_byte_order (gdbarch
),
3424 readbuf
, writebuf
, offset
);
3426 return RETURN_VALUE_REGISTER_CONVENTION
;
3428 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3429 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3431 /* A structure or union. Extract the left justified value,
3432 regardless of the byte order. I.e. DO NOT USE
3436 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3437 offset
< TYPE_LENGTH (type
);
3438 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3440 int xfer
= register_size (gdbarch
, regnum
);
3441 if (offset
+ xfer
> TYPE_LENGTH (type
))
3442 xfer
= TYPE_LENGTH (type
) - offset
;
3444 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3445 offset
, xfer
, regnum
);
3446 mips_xfer_register (gdbarch
, regcache
,
3447 gdbarch_num_regs (gdbarch
) + regnum
,
3448 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
3451 return RETURN_VALUE_REGISTER_CONVENTION
;
3455 /* A scalar extract each part but least-significant-byte
3459 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3460 offset
< TYPE_LENGTH (type
);
3461 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3463 int xfer
= register_size (gdbarch
, regnum
);
3464 if (offset
+ xfer
> TYPE_LENGTH (type
))
3465 xfer
= TYPE_LENGTH (type
) - offset
;
3467 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3468 offset
, xfer
, regnum
);
3469 mips_xfer_register (gdbarch
, regcache
,
3470 gdbarch_num_regs (gdbarch
) + regnum
,
3471 xfer
, gdbarch_byte_order (gdbarch
),
3472 readbuf
, writebuf
, offset
);
3474 return RETURN_VALUE_REGISTER_CONVENTION
;
3478 /* O32 ABI stuff. */
3481 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3482 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3483 int nargs
, struct value
**args
, CORE_ADDR sp
,
3484 int struct_return
, CORE_ADDR struct_addr
)
3490 int stack_offset
= 0;
3491 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3492 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3494 /* For shared libraries, "t9" needs to point at the function
3496 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3498 /* Set the return address register to point to the entry point of
3499 the program, where a breakpoint lies in wait. */
3500 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3502 /* First ensure that the stack and structure return address (if any)
3503 are properly aligned. The stack has to be at least 64-bit
3504 aligned even on 32-bit machines, because doubles must be 64-bit
3505 aligned. For n32 and n64, stack frames need to be 128-bit
3506 aligned, so we round to this widest known alignment. */
3508 sp
= align_down (sp
, 16);
3509 struct_addr
= align_down (struct_addr
, 16);
3511 /* Now make space on the stack for the args. */
3512 for (argnum
= 0; argnum
< nargs
; argnum
++)
3514 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3515 int arglen
= TYPE_LENGTH (arg_type
);
3517 /* Align to double-word if necessary. */
3518 if (mips_type_needs_double_align (arg_type
))
3519 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3520 /* Allocate space on the stack. */
3521 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3523 sp
-= align_up (len
, 16);
3526 fprintf_unfiltered (gdb_stdlog
,
3527 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3528 paddr_nz (sp
), (long) align_up (len
, 16));
3530 /* Initialize the integer and float register pointers. */
3531 argreg
= MIPS_A0_REGNUM
;
3532 float_argreg
= mips_fpa0_regnum (gdbarch
);
3534 /* The struct_return pointer occupies the first parameter-passing reg. */
3538 fprintf_unfiltered (gdb_stdlog
,
3539 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3540 argreg
, paddr_nz (struct_addr
));
3541 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3542 stack_offset
+= MIPS32_REGSIZE
;
3545 /* Now load as many as possible of the first arguments into
3546 registers, and push the rest onto the stack. Loop thru args
3547 from first to last. */
3548 for (argnum
= 0; argnum
< nargs
; argnum
++)
3550 const gdb_byte
*val
;
3551 struct value
*arg
= args
[argnum
];
3552 struct type
*arg_type
= check_typedef (value_type (arg
));
3553 int len
= TYPE_LENGTH (arg_type
);
3554 enum type_code typecode
= TYPE_CODE (arg_type
);
3557 fprintf_unfiltered (gdb_stdlog
,
3558 "mips_o32_push_dummy_call: %d len=%d type=%d",
3559 argnum
+ 1, len
, (int) typecode
);
3561 val
= value_contents (arg
);
3563 /* 32-bit ABIs always start floating point arguments in an
3564 even-numbered floating point register. Round the FP register
3565 up before the check to see if there are any FP registers
3566 left. O32/O64 targets also pass the FP in the integer
3567 registers so also round up normal registers. */
3568 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
3570 if ((float_argreg
& 1))
3574 /* Floating point arguments passed in registers have to be
3575 treated specially. On 32-bit architectures, doubles
3576 are passed in register pairs; the even register gets
3577 the low word, and the odd register gets the high word.
3578 On O32/O64, the first two floating point arguments are
3579 also copied to general registers, because MIPS16 functions
3580 don't use float registers for arguments. This duplication of
3581 arguments in general registers can't hurt non-MIPS16 functions
3582 because those registers are normally skipped. */
3584 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
3585 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
3587 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3589 int low_offset
= gdbarch_byte_order (gdbarch
)
3590 == BFD_ENDIAN_BIG
? 4 : 0;
3591 unsigned long regval
;
3593 /* Write the low word of the double to the even register(s). */
3594 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3596 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3597 float_argreg
, phex (regval
, 4));
3598 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3600 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3601 argreg
, phex (regval
, 4));
3602 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3604 /* Write the high word of the double to the odd register(s). */
3605 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3607 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3608 float_argreg
, phex (regval
, 4));
3609 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3612 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3613 argreg
, phex (regval
, 4));
3614 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3618 /* This is a floating point value that fits entirely
3619 in a single register. */
3620 /* On 32 bit ABI's the float_argreg is further adjusted
3621 above to ensure that it is even register aligned. */
3622 LONGEST regval
= extract_unsigned_integer (val
, len
);
3624 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3625 float_argreg
, phex (regval
, len
));
3626 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3627 /* Although two FP registers are reserved for each
3628 argument, only one corresponding integer register is
3631 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3632 argreg
, phex (regval
, len
));
3633 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3635 /* Reserve space for the FP register. */
3636 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3640 /* Copy the argument to general registers or the stack in
3641 register-sized pieces. Large arguments are split between
3642 registers and stack. */
3643 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3644 are treated specially: Irix cc passes
3645 them in registers where gcc sometimes puts them on the
3646 stack. For maximum compatibility, we will put them in
3648 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3649 && len
% MIPS32_REGSIZE
!= 0);
3650 /* Structures should be aligned to eight bytes (even arg registers)
3651 on MIPS_ABI_O32, if their first member has double precision. */
3652 if (mips_type_needs_double_align (arg_type
))
3657 stack_offset
+= MIPS32_REGSIZE
;
3662 /* Remember if the argument was written to the stack. */
3663 int stack_used_p
= 0;
3664 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3667 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3670 /* Write this portion of the argument to the stack. */
3671 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
3672 || odd_sized_struct
)
3674 /* Should shorter than int integer values be
3675 promoted to int before being stored? */
3676 int longword_offset
= 0;
3682 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3683 paddr_nz (stack_offset
));
3684 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3685 paddr_nz (longword_offset
));
3688 addr
= sp
+ stack_offset
+ longword_offset
;
3693 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3695 for (i
= 0; i
< partial_len
; i
++)
3697 fprintf_unfiltered (gdb_stdlog
, "%02x",
3701 write_memory (addr
, val
, partial_len
);
3704 /* Note!!! This is NOT an else clause. Odd sized
3705 structs may go thru BOTH paths. */
3706 /* Write this portion of the argument to a general
3707 purpose register. */
3708 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
3710 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3711 /* Value may need to be sign extended, because
3712 mips_isa_regsize() != mips_abi_regsize(). */
3714 /* A non-floating-point argument being passed in a
3715 general register. If a struct or union, and if
3716 the remaining length is smaller than the register
3717 size, we have to adjust the register value on
3720 It does not seem to be necessary to do the
3721 same for integral types.
3723 Also don't do this adjustment on O64 binaries.
3725 cagney/2001-07-23: gdb/179: Also, GCC, when
3726 outputting LE O32 with sizeof (struct) <
3727 mips_abi_regsize(), generates a left shift
3728 as part of storing the argument in a register
3729 (the left shift isn't generated when
3730 sizeof (struct) >= mips_abi_regsize()). Since
3731 it is quite possible that this is GCC
3732 contradicting the LE/O32 ABI, GDB has not been
3733 adjusted to accommodate this. Either someone
3734 needs to demonstrate that the LE/O32 ABI
3735 specifies such a left shift OR this new ABI gets
3736 identified as such and GDB gets tweaked
3739 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
3740 && partial_len
< MIPS32_REGSIZE
3741 && (typecode
== TYPE_CODE_STRUCT
3742 || typecode
== TYPE_CODE_UNION
))
3743 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3747 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3749 phex (regval
, MIPS32_REGSIZE
));
3750 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3753 /* Prevent subsequent floating point arguments from
3754 being passed in floating point registers. */
3755 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
3761 /* Compute the the offset into the stack at which we
3762 will copy the next parameter.
3764 In older ABIs, the caller reserved space for
3765 registers that contained arguments. This was loosely
3766 refered to as their "home". Consequently, space is
3767 always allocated. */
3769 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3773 fprintf_unfiltered (gdb_stdlog
, "\n");
3776 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3778 /* Return adjusted stack pointer. */
3782 static enum return_value_convention
3783 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
3784 struct type
*type
, struct regcache
*regcache
,
3785 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3787 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3789 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3790 || TYPE_CODE (type
) == TYPE_CODE_UNION
3791 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3792 return RETURN_VALUE_STRUCT_CONVENTION
;
3793 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3794 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3796 /* A single-precision floating-point value. It fits in the
3797 least significant part of FP0. */
3799 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3800 mips_xfer_register (gdbarch
, regcache
,
3801 gdbarch_num_regs (gdbarch
)
3802 + mips_regnum (gdbarch
)->fp0
,
3804 gdbarch_byte_order (gdbarch
),
3805 readbuf
, writebuf
, 0);
3806 return RETURN_VALUE_REGISTER_CONVENTION
;
3808 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3809 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3811 /* A double-precision floating-point value. The most
3812 significant part goes in FP1, and the least significant in
3815 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3816 switch (gdbarch_byte_order (gdbarch
))
3818 case BFD_ENDIAN_LITTLE
:
3819 mips_xfer_register (gdbarch
, regcache
,
3820 gdbarch_num_regs (gdbarch
)
3821 + mips_regnum (gdbarch
)->fp0
+
3822 0, 4, gdbarch_byte_order (gdbarch
),
3823 readbuf
, writebuf
, 0);
3824 mips_xfer_register (gdbarch
, regcache
,
3825 gdbarch_num_regs (gdbarch
)
3826 + mips_regnum (gdbarch
)->fp0
+ 1,
3827 4, gdbarch_byte_order (gdbarch
),
3828 readbuf
, writebuf
, 4);
3830 case BFD_ENDIAN_BIG
:
3831 mips_xfer_register (gdbarch
, regcache
,
3832 gdbarch_num_regs (gdbarch
)
3833 + mips_regnum (gdbarch
)->fp0
+ 1,
3834 4, gdbarch_byte_order (gdbarch
),
3835 readbuf
, writebuf
, 0);
3836 mips_xfer_register (gdbarch
, regcache
,
3837 gdbarch_num_regs (gdbarch
)
3838 + mips_regnum (gdbarch
)->fp0
+ 0,
3839 4, gdbarch_byte_order (gdbarch
),
3840 readbuf
, writebuf
, 4);
3843 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3845 return RETURN_VALUE_REGISTER_CONVENTION
;
3848 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3849 && TYPE_NFIELDS (type
) <= 2
3850 && TYPE_NFIELDS (type
) >= 1
3851 && ((TYPE_NFIELDS (type
) == 1
3852 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3854 || (TYPE_NFIELDS (type
) == 2
3855 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3857 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3859 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3861 /* A struct that contains one or two floats. Each value is part
3862 in the least significant part of their floating point
3864 gdb_byte reg
[MAX_REGISTER_SIZE
];
3867 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
3868 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3870 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3873 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3875 mips_xfer_register (gdbarch
, regcache
,
3876 gdbarch_num_regs (gdbarch
) + regnum
,
3877 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3878 gdbarch_byte_order (gdbarch
),
3879 readbuf
, writebuf
, offset
);
3881 return RETURN_VALUE_REGISTER_CONVENTION
;
3885 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3886 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3888 /* A structure or union. Extract the left justified value,
3889 regardless of the byte order. I.e. DO NOT USE
3893 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3894 offset
< TYPE_LENGTH (type
);
3895 offset
+= register_size (gdbarch
, regnum
), regnum
++)
3897 int xfer
= register_size (gdbarch
, regnum
);
3898 if (offset
+ xfer
> TYPE_LENGTH (type
))
3899 xfer
= TYPE_LENGTH (type
) - offset
;
3901 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3902 offset
, xfer
, regnum
);
3903 mips_xfer_register (gdbarch
, regcache
,
3904 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3905 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3907 return RETURN_VALUE_REGISTER_CONVENTION
;
3912 /* A scalar extract each part but least-significant-byte
3913 justified. o32 thinks registers are 4 byte, regardless of
3917 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3918 offset
< TYPE_LENGTH (type
);
3919 offset
+= MIPS32_REGSIZE
, regnum
++)
3921 int xfer
= MIPS32_REGSIZE
;
3922 if (offset
+ xfer
> TYPE_LENGTH (type
))
3923 xfer
= TYPE_LENGTH (type
) - offset
;
3925 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3926 offset
, xfer
, regnum
);
3927 mips_xfer_register (gdbarch
, regcache
,
3928 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
3929 gdbarch_byte_order (gdbarch
),
3930 readbuf
, writebuf
, offset
);
3932 return RETURN_VALUE_REGISTER_CONVENTION
;
3936 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3940 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3941 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3943 struct value
**args
, CORE_ADDR sp
,
3944 int struct_return
, CORE_ADDR struct_addr
)
3950 int stack_offset
= 0;
3951 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3952 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3954 /* For shared libraries, "t9" needs to point at the function
3956 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3958 /* Set the return address register to point to the entry point of
3959 the program, where a breakpoint lies in wait. */
3960 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3962 /* First ensure that the stack and structure return address (if any)
3963 are properly aligned. The stack has to be at least 64-bit
3964 aligned even on 32-bit machines, because doubles must be 64-bit
3965 aligned. For n32 and n64, stack frames need to be 128-bit
3966 aligned, so we round to this widest known alignment. */
3968 sp
= align_down (sp
, 16);
3969 struct_addr
= align_down (struct_addr
, 16);
3971 /* Now make space on the stack for the args. */
3972 for (argnum
= 0; argnum
< nargs
; argnum
++)
3974 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3975 int arglen
= TYPE_LENGTH (arg_type
);
3977 /* Allocate space on the stack. */
3978 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3980 sp
-= align_up (len
, 16);
3983 fprintf_unfiltered (gdb_stdlog
,
3984 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3985 paddr_nz (sp
), (long) align_up (len
, 16));
3987 /* Initialize the integer and float register pointers. */
3988 argreg
= MIPS_A0_REGNUM
;
3989 float_argreg
= mips_fpa0_regnum (gdbarch
);
3991 /* The struct_return pointer occupies the first parameter-passing reg. */
3995 fprintf_unfiltered (gdb_stdlog
,
3996 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3997 argreg
, paddr_nz (struct_addr
));
3998 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3999 stack_offset
+= MIPS64_REGSIZE
;
4002 /* Now load as many as possible of the first arguments into
4003 registers, and push the rest onto the stack. Loop thru args
4004 from first to last. */
4005 for (argnum
= 0; argnum
< nargs
; argnum
++)
4007 const gdb_byte
*val
;
4008 struct value
*arg
= args
[argnum
];
4009 struct type
*arg_type
= check_typedef (value_type (arg
));
4010 int len
= TYPE_LENGTH (arg_type
);
4011 enum type_code typecode
= TYPE_CODE (arg_type
);
4014 fprintf_unfiltered (gdb_stdlog
,
4015 "mips_o64_push_dummy_call: %d len=%d type=%d",
4016 argnum
+ 1, len
, (int) typecode
);
4018 val
= value_contents (arg
);
4020 /* Floating point arguments passed in registers have to be
4021 treated specially. On 32-bit architectures, doubles
4022 are passed in register pairs; the even register gets
4023 the low word, and the odd register gets the high word.
4024 On O32/O64, the first two floating point arguments are
4025 also copied to general registers, because MIPS16 functions
4026 don't use float registers for arguments. This duplication of
4027 arguments in general registers can't hurt non-MIPS16 functions
4028 because those registers are normally skipped. */
4030 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4031 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4033 LONGEST regval
= extract_unsigned_integer (val
, len
);
4035 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4036 float_argreg
, phex (regval
, len
));
4037 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
4039 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4040 argreg
, phex (regval
, len
));
4041 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4043 /* Reserve space for the FP register. */
4044 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
4048 /* Copy the argument to general registers or the stack in
4049 register-sized pieces. Large arguments are split between
4050 registers and stack. */
4051 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
4052 are treated specially: Irix cc passes them in registers
4053 where gcc sometimes puts them on the stack. For maximum
4054 compatibility, we will put them in both places. */
4055 int odd_sized_struct
= (len
> MIPS64_REGSIZE
4056 && len
% MIPS64_REGSIZE
!= 0);
4059 /* Remember if the argument was written to the stack. */
4060 int stack_used_p
= 0;
4061 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4064 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4067 /* Write this portion of the argument to the stack. */
4068 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4069 || odd_sized_struct
)
4071 /* Should shorter than int integer values be
4072 promoted to int before being stored? */
4073 int longword_offset
= 0;
4076 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4078 if ((typecode
== TYPE_CODE_INT
4079 || typecode
== TYPE_CODE_PTR
4080 || typecode
== TYPE_CODE_FLT
)
4082 longword_offset
= MIPS64_REGSIZE
- len
;
4087 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
4088 paddr_nz (stack_offset
));
4089 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
4090 paddr_nz (longword_offset
));
4093 addr
= sp
+ stack_offset
+ longword_offset
;
4098 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
4100 for (i
= 0; i
< partial_len
; i
++)
4102 fprintf_unfiltered (gdb_stdlog
, "%02x",
4106 write_memory (addr
, val
, partial_len
);
4109 /* Note!!! This is NOT an else clause. Odd sized
4110 structs may go thru BOTH paths. */
4111 /* Write this portion of the argument to a general
4112 purpose register. */
4113 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4115 LONGEST regval
= extract_signed_integer (val
, partial_len
);
4116 /* Value may need to be sign extended, because
4117 mips_isa_regsize() != mips_abi_regsize(). */
4119 /* A non-floating-point argument being passed in a
4120 general register. If a struct or union, and if
4121 the remaining length is smaller than the register
4122 size, we have to adjust the register value on
4125 It does not seem to be necessary to do the
4126 same for integral types. */
4128 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
4129 && partial_len
< MIPS64_REGSIZE
4130 && (typecode
== TYPE_CODE_STRUCT
4131 || typecode
== TYPE_CODE_UNION
))
4132 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
4136 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4138 phex (regval
, MIPS64_REGSIZE
));
4139 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4142 /* Prevent subsequent floating point arguments from
4143 being passed in floating point registers. */
4144 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
4150 /* Compute the the offset into the stack at which we
4151 will copy the next parameter.
4153 In older ABIs, the caller reserved space for
4154 registers that contained arguments. This was loosely
4155 refered to as their "home". Consequently, space is
4156 always allocated. */
4158 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
4162 fprintf_unfiltered (gdb_stdlog
, "\n");
4165 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4167 /* Return adjusted stack pointer. */
4171 static enum return_value_convention
4172 mips_o64_return_value (struct gdbarch
*gdbarch
, struct type
*func_type
,
4173 struct type
*type
, struct regcache
*regcache
,
4174 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4178 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
4179 || TYPE_CODE (type
) == TYPE_CODE_UNION
4180 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
4181 return RETURN_VALUE_STRUCT_CONVENTION
;
4182 else if (fp_register_arg_p (gdbarch
, TYPE_CODE (type
), type
))
4184 /* A floating-point value. It fits in the least significant
4187 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4188 mips_xfer_register (gdbarch
, regcache
,
4189 gdbarch_num_regs (gdbarch
)
4190 + mips_regnum (gdbarch
)->fp0
,
4192 gdbarch_byte_order (gdbarch
),
4193 readbuf
, writebuf
, 0);
4194 return RETURN_VALUE_REGISTER_CONVENTION
;
4198 /* A scalar extract each part but least-significant-byte
4202 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
4203 offset
< TYPE_LENGTH (type
);
4204 offset
+= MIPS64_REGSIZE
, regnum
++)
4206 int xfer
= MIPS64_REGSIZE
;
4207 if (offset
+ xfer
> TYPE_LENGTH (type
))
4208 xfer
= TYPE_LENGTH (type
) - offset
;
4210 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
4211 offset
, xfer
, regnum
);
4212 mips_xfer_register (gdbarch
, regcache
,
4213 gdbarch_num_regs (gdbarch
) + regnum
,
4214 xfer
, gdbarch_byte_order (gdbarch
),
4215 readbuf
, writebuf
, offset
);
4217 return RETURN_VALUE_REGISTER_CONVENTION
;
4221 /* Floating point register management.
4223 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
4224 64bit operations, these early MIPS cpus treat fp register pairs
4225 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
4226 registers and offer a compatibility mode that emulates the MIPS2 fp
4227 model. When operating in MIPS2 fp compat mode, later cpu's split
4228 double precision floats into two 32-bit chunks and store them in
4229 consecutive fp regs. To display 64-bit floats stored in this
4230 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
4231 Throw in user-configurable endianness and you have a real mess.
4233 The way this works is:
4234 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
4235 double-precision value will be split across two logical registers.
4236 The lower-numbered logical register will hold the low-order bits,
4237 regardless of the processor's endianness.
4238 - If we are on a 64-bit processor, and we are looking for a
4239 single-precision value, it will be in the low ordered bits
4240 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
4241 save slot in memory.
4242 - If we are in 64-bit mode, everything is straightforward.
4244 Note that this code only deals with "live" registers at the top of the
4245 stack. We will attempt to deal with saved registers later, when
4246 the raw/cooked register interface is in place. (We need a general
4247 interface that can deal with dynamic saved register sizes -- fp
4248 regs could be 32 bits wide in one frame and 64 on the frame above
4251 static struct type
*
4252 mips_float_register_type (void)
4254 return builtin_type_ieee_single
;
4257 static struct type
*
4258 mips_double_register_type (void)
4260 return builtin_type_ieee_double
;
4263 /* Copy a 32-bit single-precision value from the current frame
4264 into rare_buffer. */
4267 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4268 gdb_byte
*rare_buffer
)
4270 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4271 int raw_size
= register_size (gdbarch
, regno
);
4272 gdb_byte
*raw_buffer
= alloca (raw_size
);
4274 if (!frame_register_read (frame
, regno
, raw_buffer
))
4275 error (_("can't read register %d (%s)"),
4276 regno
, gdbarch_register_name (gdbarch
, regno
));
4279 /* We have a 64-bit value for this register. Find the low-order
4283 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4288 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4292 memcpy (rare_buffer
, raw_buffer
, 4);
4296 /* Copy a 64-bit double-precision value from the current frame into
4297 rare_buffer. This may include getting half of it from the next
4301 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4302 gdb_byte
*rare_buffer
)
4304 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4305 int raw_size
= register_size (gdbarch
, regno
);
4307 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4309 /* We have a 64-bit value for this register, and we should use
4311 if (!frame_register_read (frame
, regno
, rare_buffer
))
4312 error (_("can't read register %d (%s)"),
4313 regno
, gdbarch_register_name (gdbarch
, regno
));
4317 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
4319 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
4320 internal_error (__FILE__
, __LINE__
,
4321 _("mips_read_fp_register_double: bad access to "
4322 "odd-numbered FP register"));
4324 /* mips_read_fp_register_single will find the correct 32 bits from
4326 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4328 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4329 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4333 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4334 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4340 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4342 { /* do values for FP (float) regs */
4343 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4344 gdb_byte
*raw_buffer
;
4345 double doub
, flt1
; /* doubles extracted from raw hex data */
4348 raw_buffer
= alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
));
4350 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
4351 fprintf_filtered (file
, "%*s",
4352 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
4355 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4357 /* 4-byte registers: Print hex and floating. Also print even
4358 numbered registers as doubles. */
4359 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4360 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4362 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4365 fprintf_filtered (file
, " flt: ");
4367 fprintf_filtered (file
, " <invalid float> ");
4369 fprintf_filtered (file
, "%-17.9g", flt1
);
4371 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
4373 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4374 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4377 fprintf_filtered (file
, " dbl: ");
4379 fprintf_filtered (file
, "<invalid double>");
4381 fprintf_filtered (file
, "%-24.17g", doub
);
4386 /* Eight byte registers: print each one as hex, float and double. */
4387 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4388 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4390 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4391 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4394 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4397 fprintf_filtered (file
, " flt: ");
4399 fprintf_filtered (file
, "<invalid float>");
4401 fprintf_filtered (file
, "%-17.9g", flt1
);
4403 fprintf_filtered (file
, " dbl: ");
4405 fprintf_filtered (file
, "<invalid double>");
4407 fprintf_filtered (file
, "%-24.17g", doub
);
4412 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4415 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4416 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4419 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4421 mips_print_fp_register (file
, frame
, regnum
);
4425 /* Get the data in raw format. */
4426 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4428 fprintf_filtered (file
, "%s: [Invalid]",
4429 gdbarch_register_name (gdbarch
, regnum
));
4433 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
4435 /* The problem with printing numeric register names (r26, etc.) is that
4436 the user can't use them on input. Probably the best solution is to
4437 fix it so that either the numeric or the funky (a2, etc.) names
4438 are accepted on input. */
4439 if (regnum
< MIPS_NUMREGS
)
4440 fprintf_filtered (file
, "(r%d): ", regnum
);
4442 fprintf_filtered (file
, ": ");
4444 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4446 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4450 print_scalar_formatted (raw_buffer
+ offset
,
4451 register_type (gdbarch
, regnum
), 'x', 0,
4455 /* Replacement for generic do_registers_info.
4456 Print regs in pretty columns. */
4459 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4462 fprintf_filtered (file
, " ");
4463 mips_print_fp_register (file
, frame
, regnum
);
4464 fprintf_filtered (file
, "\n");
4469 /* Print a row's worth of GP (int) registers, with name labels above */
4472 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4475 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4476 /* do values for GP (int) regs */
4477 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4478 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4482 /* For GP registers, we print a separate row of names above the vals */
4483 for (col
= 0, regnum
= start_regnum
;
4484 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4485 + gdbarch_num_pseudo_regs (gdbarch
);
4488 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4489 continue; /* unused register */
4490 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4492 break; /* end the row: reached FP register */
4493 /* Large registers are handled separately. */
4494 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4497 break; /* End the row before this register. */
4499 /* Print this register on a row by itself. */
4500 mips_print_register (file
, frame
, regnum
);
4501 fprintf_filtered (file
, "\n");
4505 fprintf_filtered (file
, " ");
4506 fprintf_filtered (file
,
4507 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
4508 gdbarch_register_name (gdbarch
, regnum
));
4515 /* print the R0 to R31 names */
4516 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
4517 fprintf_filtered (file
, "\n R%-4d",
4518 start_regnum
% gdbarch_num_regs (gdbarch
));
4520 fprintf_filtered (file
, "\n ");
4522 /* now print the values in hex, 4 or 8 to the row */
4523 for (col
= 0, regnum
= start_regnum
;
4524 col
< ncols
&& regnum
< gdbarch_num_regs (gdbarch
)
4525 + gdbarch_num_pseudo_regs (gdbarch
);
4528 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
4529 continue; /* unused register */
4530 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4532 break; /* end row: reached FP register */
4533 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
4534 break; /* End row: large register. */
4536 /* OK: get the data in raw format. */
4537 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4538 error (_("can't read register %d (%s)"),
4539 regnum
, gdbarch_register_name (gdbarch
, regnum
));
4540 /* pad small registers */
4542 byte
< (mips_abi_regsize (gdbarch
)
4543 - register_size (gdbarch
, regnum
)); byte
++)
4544 printf_filtered (" ");
4545 /* Now print the register value in hex, endian order. */
4546 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4548 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
4549 byte
< register_size (gdbarch
, regnum
); byte
++)
4550 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4552 for (byte
= register_size (gdbarch
, regnum
) - 1;
4554 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4555 fprintf_filtered (file
, " ");
4558 if (col
> 0) /* ie. if we actually printed anything... */
4559 fprintf_filtered (file
, "\n");
4564 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4567 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4568 struct frame_info
*frame
, int regnum
, int all
)
4570 if (regnum
!= -1) /* do one specified register */
4572 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
4573 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
4574 error (_("Not a valid register for the current processor type"));
4576 mips_print_register (file
, frame
, regnum
);
4577 fprintf_filtered (file
, "\n");
4580 /* do all (or most) registers */
4582 regnum
= gdbarch_num_regs (gdbarch
);
4583 while (regnum
< gdbarch_num_regs (gdbarch
)
4584 + gdbarch_num_pseudo_regs (gdbarch
))
4586 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4589 if (all
) /* true for "INFO ALL-REGISTERS" command */
4590 regnum
= print_fp_register_row (file
, frame
, regnum
);
4592 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4595 regnum
= print_gp_register_row (file
, frame
, regnum
);
4600 /* Is this a branch with a delay slot? */
4603 is_delayed (unsigned long insn
)
4606 for (i
= 0; i
< NUMOPCODES
; ++i
)
4607 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4608 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4610 return (i
< NUMOPCODES
4611 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4612 | INSN_COND_BRANCH_DELAY
4613 | INSN_COND_BRANCH_LIKELY
)));
4617 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4618 struct frame_info
*frame
)
4620 CORE_ADDR pc
= get_frame_pc (frame
);
4621 gdb_byte buf
[MIPS_INSN32_SIZE
];
4623 /* There is no branch delay slot on MIPS16. */
4624 if (mips_pc_is_mips16 (pc
))
4627 if (!breakpoint_here_p (pc
+ 4))
4630 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4631 /* If error reading memory, guess that it is not a delayed
4634 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4637 /* To skip prologues, I use this predicate. Returns either PC itself
4638 if the code at PC does not look like a function prologue; otherwise
4639 returns an address that (if we're lucky) follows the prologue. If
4640 LENIENT, then we must skip everything which is involved in setting
4641 up the frame (it's OK to skip more, just so long as we don't skip
4642 anything which might clobber the registers which are being saved.
4643 We must skip more in the case where part of the prologue is in the
4644 delay slot of a non-prologue instruction). */
4647 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4650 CORE_ADDR func_addr
;
4652 /* See if we can determine the end of the prologue via the symbol table.
4653 If so, then return either PC, or the PC after the prologue, whichever
4655 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4657 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4658 if (post_prologue_pc
!= 0)
4659 return max (pc
, post_prologue_pc
);
4662 /* Can't determine prologue from the symbol table, need to examine
4665 /* Find an upper limit on the function prologue using the debug
4666 information. If the debug information could not be used to provide
4667 that bound, then use an arbitrary large number as the upper bound. */
4668 limit_pc
= skip_prologue_using_sal (pc
);
4670 limit_pc
= pc
+ 100; /* Magic. */
4672 if (mips_pc_is_mips16 (pc
))
4673 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4675 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4678 /* Check whether the PC is in a function epilogue (32-bit version).
4679 This is a helper function for mips_in_function_epilogue_p. */
4681 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4683 CORE_ADDR func_addr
= 0, func_end
= 0;
4685 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4687 /* The MIPS epilogue is max. 12 bytes long. */
4688 CORE_ADDR addr
= func_end
- 12;
4690 if (addr
< func_addr
+ 4)
4691 addr
= func_addr
+ 4;
4695 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4697 unsigned long high_word
;
4700 inst
= mips_fetch_instruction (pc
);
4701 high_word
= (inst
>> 16) & 0xffff;
4703 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4704 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4705 && inst
!= 0x03e00008 /* jr $ra */
4706 && inst
!= 0x00000000) /* nop */
4716 /* Check whether the PC is in a function epilogue (16-bit version).
4717 This is a helper function for mips_in_function_epilogue_p. */
4719 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4721 CORE_ADDR func_addr
= 0, func_end
= 0;
4723 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4725 /* The MIPS epilogue is max. 12 bytes long. */
4726 CORE_ADDR addr
= func_end
- 12;
4728 if (addr
< func_addr
+ 4)
4729 addr
= func_addr
+ 4;
4733 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4735 unsigned short inst
;
4737 inst
= mips_fetch_instruction (pc
);
4739 if ((inst
& 0xf800) == 0xf000) /* extend */
4742 if (inst
!= 0x6300 /* addiu $sp,offset */
4743 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4744 && inst
!= 0xe820 /* jr $ra */
4745 && inst
!= 0xe8a0 /* jrc $ra */
4746 && inst
!= 0x6500) /* nop */
4756 /* The epilogue is defined here as the area at the end of a function,
4757 after an instruction which destroys the function's stack frame. */
4759 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4761 if (mips_pc_is_mips16 (pc
))
4762 return mips16_in_function_epilogue_p (pc
);
4764 return mips32_in_function_epilogue_p (pc
);
4767 /* Root of all "set mips "/"show mips " commands. This will eventually be
4768 used for all MIPS-specific commands. */
4771 show_mips_command (char *args
, int from_tty
)
4773 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4777 set_mips_command (char *args
, int from_tty
)
4780 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4781 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4784 /* Commands to show/set the MIPS FPU type. */
4787 show_mipsfpu_command (char *args
, int from_tty
)
4791 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
4794 ("The MIPS floating-point coprocessor is unknown "
4795 "because the current architecture is not MIPS.\n");
4799 switch (MIPS_FPU_TYPE (target_gdbarch
))
4801 case MIPS_FPU_SINGLE
:
4802 fpu
= "single-precision";
4804 case MIPS_FPU_DOUBLE
:
4805 fpu
= "double-precision";
4808 fpu
= "absent (none)";
4811 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4813 if (mips_fpu_type_auto
)
4815 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4819 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4824 set_mipsfpu_command (char *args
, int from_tty
)
4827 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4828 show_mipsfpu_command (args
, from_tty
);
4832 set_mipsfpu_single_command (char *args
, int from_tty
)
4834 struct gdbarch_info info
;
4835 gdbarch_info_init (&info
);
4836 mips_fpu_type
= MIPS_FPU_SINGLE
;
4837 mips_fpu_type_auto
= 0;
4838 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4839 instead of relying on globals. Doing that would let generic code
4840 handle the search for this specific architecture. */
4841 if (!gdbarch_update_p (info
))
4842 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4846 set_mipsfpu_double_command (char *args
, int from_tty
)
4848 struct gdbarch_info info
;
4849 gdbarch_info_init (&info
);
4850 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4851 mips_fpu_type_auto
= 0;
4852 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4853 instead of relying on globals. Doing that would let generic code
4854 handle the search for this specific architecture. */
4855 if (!gdbarch_update_p (info
))
4856 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4860 set_mipsfpu_none_command (char *args
, int from_tty
)
4862 struct gdbarch_info info
;
4863 gdbarch_info_init (&info
);
4864 mips_fpu_type
= MIPS_FPU_NONE
;
4865 mips_fpu_type_auto
= 0;
4866 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4867 instead of relying on globals. Doing that would let generic code
4868 handle the search for this specific architecture. */
4869 if (!gdbarch_update_p (info
))
4870 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4874 set_mipsfpu_auto_command (char *args
, int from_tty
)
4876 mips_fpu_type_auto
= 1;
4879 /* Attempt to identify the particular processor model by reading the
4880 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4881 the relevant processor still exists (it dates back to '94) and
4882 secondly this is not the way to do this. The processor type should
4883 be set by forcing an architecture change. */
4886 deprecated_mips_set_processor_regs_hack (void)
4888 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4891 regcache_cooked_read_unsigned (get_current_regcache (),
4892 MIPS_PRID_REGNUM
, &prid
);
4893 if ((prid
& ~0xf) == 0x700)
4894 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4897 /* Just like reinit_frame_cache, but with the right arguments to be
4898 callable as an sfunc. */
4901 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4902 struct cmd_list_element
*c
)
4904 reinit_frame_cache ();
4908 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4910 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4912 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4913 disassembler needs to be able to locally determine the ISA, and
4914 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4916 if (mips_pc_is_mips16 (memaddr
))
4917 info
->mach
= bfd_mach_mips16
;
4919 /* Round down the instruction address to the appropriate boundary. */
4920 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4922 /* Set the disassembler options. */
4923 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4925 /* Set up the disassembler info, so that we get the right
4926 register names from libopcodes. */
4927 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4928 info
->disassembler_options
= "gpr-names=n32";
4930 info
->disassembler_options
= "gpr-names=64";
4931 info
->flavour
= bfd_target_elf_flavour
;
4934 /* This string is not recognized explicitly by the disassembler,
4935 but it tells the disassembler to not try to guess the ABI from
4936 the bfd elf headers, such that, if the user overrides the ABI
4937 of a program linked as NewABI, the disassembly will follow the
4938 register naming conventions specified by the user. */
4939 info
->disassembler_options
= "gpr-names=32";
4941 /* Call the appropriate disassembler based on the target endian-ness. */
4942 if (info
->endian
== BFD_ENDIAN_BIG
)
4943 return print_insn_big_mips (memaddr
, info
);
4945 return print_insn_little_mips (memaddr
, info
);
4948 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4949 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4950 It returns a pointer to a string of bytes that encode a breakpoint
4951 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4952 necessary) to point to the actual memory location where the breakpoint
4953 should be inserted. */
4955 static const gdb_byte
*
4956 mips_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
, int *lenptr
)
4958 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4960 if (mips_pc_is_mips16 (*pcptr
))
4962 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4963 *pcptr
= unmake_mips16_addr (*pcptr
);
4964 *lenptr
= sizeof (mips16_big_breakpoint
);
4965 return mips16_big_breakpoint
;
4969 /* The IDT board uses an unusual breakpoint value, and
4970 sometimes gets confused when it sees the usual MIPS
4971 breakpoint instruction. */
4972 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4973 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4974 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4976 *lenptr
= sizeof (big_breakpoint
);
4978 if (strcmp (target_shortname
, "mips") == 0)
4979 return idt_big_breakpoint
;
4980 else if (strcmp (target_shortname
, "ddb") == 0
4981 || strcmp (target_shortname
, "pmon") == 0
4982 || strcmp (target_shortname
, "lsi") == 0)
4983 return pmon_big_breakpoint
;
4985 return big_breakpoint
;
4990 if (mips_pc_is_mips16 (*pcptr
))
4992 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4993 *pcptr
= unmake_mips16_addr (*pcptr
);
4994 *lenptr
= sizeof (mips16_little_breakpoint
);
4995 return mips16_little_breakpoint
;
4999 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
5000 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
5001 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
5003 *lenptr
= sizeof (little_breakpoint
);
5005 if (strcmp (target_shortname
, "mips") == 0)
5006 return idt_little_breakpoint
;
5007 else if (strcmp (target_shortname
, "ddb") == 0
5008 || strcmp (target_shortname
, "pmon") == 0
5009 || strcmp (target_shortname
, "lsi") == 0)
5010 return pmon_little_breakpoint
;
5012 return little_breakpoint
;
5017 /* If PC is in a mips16 call or return stub, return the address of the target
5018 PC, which is either the callee or the caller. There are several
5019 cases which must be handled:
5021 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5022 target PC is in $31 ($ra).
5023 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5024 and the target PC is in $2.
5025 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5026 before the jal instruction, this is effectively a call stub
5027 and the the target PC is in $2. Otherwise this is effectively
5028 a return stub and the target PC is in $18.
5030 See the source code for the stubs in gcc/config/mips/mips16.S for
5034 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
5037 CORE_ADDR start_addr
;
5039 /* Find the starting address and name of the function containing the PC. */
5040 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
5043 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
5044 target PC is in $31 ($ra). */
5045 if (strcmp (name
, "__mips16_ret_sf") == 0
5046 || strcmp (name
, "__mips16_ret_df") == 0)
5047 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
5049 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
5051 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
5052 and the target PC is in $2. */
5053 if (name
[19] >= '0' && name
[19] <= '9')
5054 return get_frame_register_signed (frame
, 2);
5056 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
5057 before the jal instruction, this is effectively a call stub
5058 and the the target PC is in $2. Otherwise this is effectively
5059 a return stub and the target PC is in $18. */
5060 else if (name
[19] == 's' || name
[19] == 'd')
5062 if (pc
== start_addr
)
5064 /* Check if the target of the stub is a compiler-generated
5065 stub. Such a stub for a function bar might have a name
5066 like __fn_stub_bar, and might look like this:
5071 la $1,bar (becomes a lui/addiu pair)
5073 So scan down to the lui/addi and extract the target
5074 address from those two instructions. */
5076 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
5080 /* See if the name of the target function is __fn_stub_*. */
5081 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
5084 if (strncmp (name
, "__fn_stub_", 10) != 0
5085 && strcmp (name
, "etext") != 0
5086 && strcmp (name
, "_etext") != 0)
5089 /* Scan through this _fn_stub_ code for the lui/addiu pair.
5090 The limit on the search is arbitrarily set to 20
5091 instructions. FIXME. */
5092 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
5094 inst
= mips_fetch_instruction (target_pc
);
5095 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
5096 pc
= (inst
<< 16) & 0xffff0000; /* high word */
5097 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
5098 return pc
| (inst
& 0xffff); /* low word */
5101 /* Couldn't find the lui/addui pair, so return stub address. */
5105 /* This is the 'return' part of a call stub. The return
5106 address is in $r18. */
5107 return get_frame_register_signed (frame
, 18);
5110 return 0; /* not a stub */
5113 /* Convert a dbx stab register number (from `r' declaration) to a GDB
5114 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5117 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5120 if (num
>= 0 && num
< 32)
5122 else if (num
>= 38 && num
< 70)
5123 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
5125 regnum
= mips_regnum (gdbarch
)->hi
;
5127 regnum
= mips_regnum (gdbarch
)->lo
;
5129 /* This will hopefully (eventually) provoke a warning. Should
5130 we be calling complaint() here? */
5131 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5132 return gdbarch_num_regs (gdbarch
) + regnum
;
5136 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
5137 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
5140 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
5143 if (num
>= 0 && num
< 32)
5145 else if (num
>= 32 && num
< 64)
5146 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
5148 regnum
= mips_regnum (gdbarch
)->hi
;
5150 regnum
= mips_regnum (gdbarch
)->lo
;
5152 /* This will hopefully (eventually) provoke a warning. Should we
5153 be calling complaint() here? */
5154 return gdbarch_num_regs (gdbarch
) + gdbarch_num_pseudo_regs (gdbarch
);
5155 return gdbarch_num_regs (gdbarch
) + regnum
;
5159 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
5161 /* Only makes sense to supply raw registers. */
5162 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
5163 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
5164 decide if it is valid. Should instead define a standard sim/gdb
5165 register numbering scheme. */
5166 if (gdbarch_register_name (gdbarch
,
5167 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
5168 && gdbarch_register_name (gdbarch
,
5169 gdbarch_num_regs (gdbarch
) + regnum
)[0] != '\0')
5172 return LEGACY_SIM_REGNO_IGNORE
;
5176 /* Convert an integer into an address. Extracting the value signed
5177 guarantees a correctly sign extended address. */
5180 mips_integer_to_address (struct gdbarch
*gdbarch
,
5181 struct type
*type
, const gdb_byte
*buf
)
5183 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
5186 /* Dummy virtual frame pointer method. This is no more or less accurate
5187 than most other architectures; we just need to be explicit about it,
5188 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
5189 an assertion failure. */
5192 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
5193 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
5195 *reg
= MIPS_SP_REGNUM
;
5200 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
5202 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
5203 const char *name
= bfd_get_section_name (abfd
, sect
);
5205 if (*abip
!= MIPS_ABI_UNKNOWN
)
5208 if (strncmp (name
, ".mdebug.", 8) != 0)
5211 if (strcmp (name
, ".mdebug.abi32") == 0)
5212 *abip
= MIPS_ABI_O32
;
5213 else if (strcmp (name
, ".mdebug.abiN32") == 0)
5214 *abip
= MIPS_ABI_N32
;
5215 else if (strcmp (name
, ".mdebug.abi64") == 0)
5216 *abip
= MIPS_ABI_N64
;
5217 else if (strcmp (name
, ".mdebug.abiO64") == 0)
5218 *abip
= MIPS_ABI_O64
;
5219 else if (strcmp (name
, ".mdebug.eabi32") == 0)
5220 *abip
= MIPS_ABI_EABI32
;
5221 else if (strcmp (name
, ".mdebug.eabi64") == 0)
5222 *abip
= MIPS_ABI_EABI64
;
5224 warning (_("unsupported ABI %s."), name
+ 8);
5228 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
5230 int *lbp
= (int *) obj
;
5231 const char *name
= bfd_get_section_name (abfd
, sect
);
5233 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
5235 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
5237 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
5238 warning (_("unrecognized .gcc_compiled_longXX"));
5241 static enum mips_abi
5242 global_mips_abi (void)
5246 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
5247 if (mips_abi_strings
[i
] == mips_abi_string
)
5248 return (enum mips_abi
) i
;
5250 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
5254 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
5256 /* If the size matches the set of 32-bit or 64-bit integer registers,
5257 assume that's what we've got. */
5258 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
5259 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
5261 /* If the size matches the full set of registers GDB traditionally
5262 knows about, including floating point, for either 32-bit or
5263 64-bit, assume that's what we've got. */
5264 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
5265 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5267 /* Otherwise we don't have a useful guess. */
5270 static struct value
*
5271 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5273 const int *reg_p
= baton
;
5274 return value_of_register (*reg_p
, frame
);
5277 static struct gdbarch
*
5278 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5280 struct gdbarch
*gdbarch
;
5281 struct gdbarch_tdep
*tdep
;
5283 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5285 enum mips_fpu_type fpu_type
;
5286 struct tdesc_arch_data
*tdesc_data
= NULL
;
5287 int elf_fpu_type
= 0;
5289 /* Check any target description for validity. */
5290 if (tdesc_has_registers (info
.target_desc
))
5292 static const char *const mips_gprs
[] = {
5293 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5294 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5295 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5296 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5298 static const char *const mips_fprs
[] = {
5299 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5300 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5301 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5302 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5305 const struct tdesc_feature
*feature
;
5308 feature
= tdesc_find_feature (info
.target_desc
,
5309 "org.gnu.gdb.mips.cpu");
5310 if (feature
== NULL
)
5313 tdesc_data
= tdesc_data_alloc ();
5316 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5317 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5321 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5322 MIPS_EMBED_LO_REGNUM
, "lo");
5323 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5324 MIPS_EMBED_HI_REGNUM
, "hi");
5325 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5326 MIPS_EMBED_PC_REGNUM
, "pc");
5330 tdesc_data_cleanup (tdesc_data
);
5334 feature
= tdesc_find_feature (info
.target_desc
,
5335 "org.gnu.gdb.mips.cp0");
5336 if (feature
== NULL
)
5338 tdesc_data_cleanup (tdesc_data
);
5343 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5344 MIPS_EMBED_BADVADDR_REGNUM
,
5346 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5347 MIPS_PS_REGNUM
, "status");
5348 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5349 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5353 tdesc_data_cleanup (tdesc_data
);
5357 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5358 backend is not prepared for that, though. */
5359 feature
= tdesc_find_feature (info
.target_desc
,
5360 "org.gnu.gdb.mips.fpu");
5361 if (feature
== NULL
)
5363 tdesc_data_cleanup (tdesc_data
);
5368 for (i
= 0; i
< 32; i
++)
5369 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5370 i
+ MIPS_EMBED_FP0_REGNUM
,
5373 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5374 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5375 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5376 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5380 tdesc_data_cleanup (tdesc_data
);
5384 /* It would be nice to detect an attempt to use a 64-bit ABI
5385 when only 32-bit registers are provided. */
5388 /* First of all, extract the elf_flags, if available. */
5389 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5390 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5391 else if (arches
!= NULL
)
5392 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5396 fprintf_unfiltered (gdb_stdlog
,
5397 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5399 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5400 switch ((elf_flags
& EF_MIPS_ABI
))
5402 case E_MIPS_ABI_O32
:
5403 found_abi
= MIPS_ABI_O32
;
5405 case E_MIPS_ABI_O64
:
5406 found_abi
= MIPS_ABI_O64
;
5408 case E_MIPS_ABI_EABI32
:
5409 found_abi
= MIPS_ABI_EABI32
;
5411 case E_MIPS_ABI_EABI64
:
5412 found_abi
= MIPS_ABI_EABI64
;
5415 if ((elf_flags
& EF_MIPS_ABI2
))
5416 found_abi
= MIPS_ABI_N32
;
5418 found_abi
= MIPS_ABI_UNKNOWN
;
5422 /* GCC creates a pseudo-section whose name describes the ABI. */
5423 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5424 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5426 /* If we have no useful BFD information, use the ABI from the last
5427 MIPS architecture (if there is one). */
5428 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5429 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5431 /* Try the architecture for any hint of the correct ABI. */
5432 if (found_abi
== MIPS_ABI_UNKNOWN
5433 && info
.bfd_arch_info
!= NULL
5434 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5436 switch (info
.bfd_arch_info
->mach
)
5438 case bfd_mach_mips3900
:
5439 found_abi
= MIPS_ABI_EABI32
;
5441 case bfd_mach_mips4100
:
5442 case bfd_mach_mips5000
:
5443 found_abi
= MIPS_ABI_EABI64
;
5445 case bfd_mach_mips8000
:
5446 case bfd_mach_mips10000
:
5447 /* On Irix, ELF64 executables use the N64 ABI. The
5448 pseudo-sections which describe the ABI aren't present
5449 on IRIX. (Even for executables created by gcc.) */
5450 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5451 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5452 found_abi
= MIPS_ABI_N64
;
5454 found_abi
= MIPS_ABI_N32
;
5459 /* Default 64-bit objects to N64 instead of O32. */
5460 if (found_abi
== MIPS_ABI_UNKNOWN
5461 && info
.abfd
!= NULL
5462 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5463 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5464 found_abi
= MIPS_ABI_N64
;
5467 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5470 /* What has the user specified from the command line? */
5471 wanted_abi
= global_mips_abi ();
5473 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5476 /* Now that we have found what the ABI for this binary would be,
5477 check whether the user is overriding it. */
5478 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5479 mips_abi
= wanted_abi
;
5480 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5481 mips_abi
= found_abi
;
5483 mips_abi
= MIPS_ABI_O32
;
5485 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5488 /* Also used when doing an architecture lookup. */
5490 fprintf_unfiltered (gdb_stdlog
,
5491 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5492 mips64_transfers_32bit_regs_p
);
5494 /* Determine the MIPS FPU type. */
5497 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5498 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5499 Tag_GNU_MIPS_ABI_FP
);
5500 #endif /* HAVE_ELF */
5502 if (!mips_fpu_type_auto
)
5503 fpu_type
= mips_fpu_type
;
5504 else if (elf_fpu_type
!= 0)
5506 switch (elf_fpu_type
)
5509 fpu_type
= MIPS_FPU_DOUBLE
;
5512 fpu_type
= MIPS_FPU_SINGLE
;
5516 /* Soft float or unknown. */
5517 fpu_type
= MIPS_FPU_NONE
;
5521 else if (info
.bfd_arch_info
!= NULL
5522 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5523 switch (info
.bfd_arch_info
->mach
)
5525 case bfd_mach_mips3900
:
5526 case bfd_mach_mips4100
:
5527 case bfd_mach_mips4111
:
5528 case bfd_mach_mips4120
:
5529 fpu_type
= MIPS_FPU_NONE
;
5531 case bfd_mach_mips4650
:
5532 fpu_type
= MIPS_FPU_SINGLE
;
5535 fpu_type
= MIPS_FPU_DOUBLE
;
5538 else if (arches
!= NULL
)
5539 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5541 fpu_type
= MIPS_FPU_DOUBLE
;
5543 fprintf_unfiltered (gdb_stdlog
,
5544 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5546 /* Check for blatant incompatibilities. */
5548 /* If we have only 32-bit registers, then we can't debug a 64-bit
5550 if (info
.target_desc
5551 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5552 && mips_abi
!= MIPS_ABI_EABI32
5553 && mips_abi
!= MIPS_ABI_O32
)
5555 if (tdesc_data
!= NULL
)
5556 tdesc_data_cleanup (tdesc_data
);
5560 /* try to find a pre-existing architecture */
5561 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5563 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5565 /* MIPS needs to be pedantic about which ABI the object is
5567 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5569 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5571 /* Need to be pedantic about which register virtual size is
5573 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5574 != mips64_transfers_32bit_regs_p
)
5576 /* Be pedantic about which FPU is selected. */
5577 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5580 if (tdesc_data
!= NULL
)
5581 tdesc_data_cleanup (tdesc_data
);
5582 return arches
->gdbarch
;
5585 /* Need a new architecture. Fill in a target specific vector. */
5586 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5587 gdbarch
= gdbarch_alloc (&info
, tdep
);
5588 tdep
->elf_flags
= elf_flags
;
5589 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5590 tdep
->found_abi
= found_abi
;
5591 tdep
->mips_abi
= mips_abi
;
5592 tdep
->mips_fpu_type
= fpu_type
;
5593 tdep
->register_size_valid_p
= 0;
5594 tdep
->register_size
= 0;
5596 if (info
.target_desc
)
5598 /* Some useful properties can be inferred from the target. */
5599 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5601 tdep
->register_size_valid_p
= 1;
5602 tdep
->register_size
= 4;
5604 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5606 tdep
->register_size_valid_p
= 1;
5607 tdep
->register_size
= 8;
5611 /* Initially set everything according to the default ABI/ISA. */
5612 set_gdbarch_short_bit (gdbarch
, 16);
5613 set_gdbarch_int_bit (gdbarch
, 32);
5614 set_gdbarch_float_bit (gdbarch
, 32);
5615 set_gdbarch_double_bit (gdbarch
, 64);
5616 set_gdbarch_long_double_bit (gdbarch
, 64);
5617 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5618 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5619 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5621 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5622 mips_elf_make_msymbol_special
);
5624 /* Fill in the OS dependant register numbers and names. */
5626 const char **reg_names
;
5627 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5628 struct mips_regnum
);
5629 if (tdesc_has_registers (info
.target_desc
))
5631 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5632 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5633 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5634 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5635 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5636 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5637 regnum
->fp_control_status
= 70;
5638 regnum
->fp_implementation_revision
= 71;
5639 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5642 else if (info
.osabi
== GDB_OSABI_IRIX
)
5647 regnum
->badvaddr
= 66;
5650 regnum
->fp_control_status
= 69;
5651 regnum
->fp_implementation_revision
= 70;
5653 reg_names
= mips_irix_reg_names
;
5657 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5658 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5659 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5660 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5661 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5662 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5663 regnum
->fp_control_status
= 70;
5664 regnum
->fp_implementation_revision
= 71;
5666 if (info
.bfd_arch_info
!= NULL
5667 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5668 reg_names
= mips_tx39_reg_names
;
5670 reg_names
= mips_generic_reg_names
;
5672 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5673 replaced by read_pc? */
5674 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5675 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5676 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5677 set_gdbarch_num_regs (gdbarch
, num_regs
);
5678 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5679 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5680 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
5681 tdep
->mips_processor_reg_names
= reg_names
;
5682 tdep
->regnum
= regnum
;
5688 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5689 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5690 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5691 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5692 tdep
->default_mask_address_p
= 0;
5693 set_gdbarch_long_bit (gdbarch
, 32);
5694 set_gdbarch_ptr_bit (gdbarch
, 32);
5695 set_gdbarch_long_long_bit (gdbarch
, 64);
5698 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5699 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5700 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5701 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5702 tdep
->default_mask_address_p
= 0;
5703 set_gdbarch_long_bit (gdbarch
, 32);
5704 set_gdbarch_ptr_bit (gdbarch
, 32);
5705 set_gdbarch_long_long_bit (gdbarch
, 64);
5707 case MIPS_ABI_EABI32
:
5708 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5709 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5710 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5711 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5712 tdep
->default_mask_address_p
= 0;
5713 set_gdbarch_long_bit (gdbarch
, 32);
5714 set_gdbarch_ptr_bit (gdbarch
, 32);
5715 set_gdbarch_long_long_bit (gdbarch
, 64);
5717 case MIPS_ABI_EABI64
:
5718 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5719 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5720 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5721 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5722 tdep
->default_mask_address_p
= 0;
5723 set_gdbarch_long_bit (gdbarch
, 64);
5724 set_gdbarch_ptr_bit (gdbarch
, 64);
5725 set_gdbarch_long_long_bit (gdbarch
, 64);
5728 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5729 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5730 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5731 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5732 tdep
->default_mask_address_p
= 0;
5733 set_gdbarch_long_bit (gdbarch
, 32);
5734 set_gdbarch_ptr_bit (gdbarch
, 32);
5735 set_gdbarch_long_long_bit (gdbarch
, 64);
5736 set_gdbarch_long_double_bit (gdbarch
, 128);
5737 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5740 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5741 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5742 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5743 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5744 tdep
->default_mask_address_p
= 0;
5745 set_gdbarch_long_bit (gdbarch
, 64);
5746 set_gdbarch_ptr_bit (gdbarch
, 64);
5747 set_gdbarch_long_long_bit (gdbarch
, 64);
5748 set_gdbarch_long_double_bit (gdbarch
, 128);
5749 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
5752 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5755 /* GCC creates a pseudo-section whose name specifies the size of
5756 longs, since -mlong32 or -mlong64 may be used independent of
5757 other options. How those options affect pointer sizes is ABI and
5758 architecture dependent, so use them to override the default sizes
5759 set by the ABI. This table shows the relationship between ABI,
5760 -mlongXX, and size of pointers:
5762 ABI -mlongXX ptr bits
5763 --- -------- --------
5777 Note that for o32 and eabi32, pointers are always 32 bits
5778 regardless of any -mlongXX option. For all others, pointers and
5779 longs are the same, as set by -mlongXX or set by defaults.
5782 if (info
.abfd
!= NULL
)
5786 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5789 set_gdbarch_long_bit (gdbarch
, long_bit
);
5793 case MIPS_ABI_EABI32
:
5798 case MIPS_ABI_EABI64
:
5799 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5802 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5807 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5808 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5811 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5812 flag in object files because to do so would make it impossible to
5813 link with libraries compiled without "-gp32". This is
5814 unnecessarily restrictive.
5816 We could solve this problem by adding "-gp32" multilibs to gcc,
5817 but to set this flag before gcc is built with such multilibs will
5818 break too many systems.''
5820 But even more unhelpfully, the default linker output target for
5821 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5822 for 64-bit programs - you need to change the ABI to change this,
5823 and not all gcc targets support that currently. Therefore using
5824 this flag to detect 32-bit mode would do the wrong thing given
5825 the current gcc - it would make GDB treat these 64-bit programs
5826 as 32-bit programs by default. */
5828 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5829 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5831 /* Add/remove bits from an address. The MIPS needs be careful to
5832 ensure that all 32 bit addresses are sign extended to 64 bits. */
5833 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5835 /* Unwind the frame. */
5836 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5837 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5838 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
5840 /* Map debug register numbers onto internal register numbers. */
5841 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5842 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5843 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5844 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5845 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5846 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5848 /* MIPS version of CALL_DUMMY */
5850 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5851 replaced by a command, and all targets will default to on stack
5852 (regardless of the stack's execute status). */
5853 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5854 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5856 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5857 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5858 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5860 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5861 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5863 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5865 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5867 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5868 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5869 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5871 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5873 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5875 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5877 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5878 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5879 need to all be folded into the target vector. Since they are
5880 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5881 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5883 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5885 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5887 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5889 /* Virtual tables. */
5890 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5892 mips_register_g_packet_guesses (gdbarch
);
5894 /* Hook in OS ABI-specific overrides, if they have been registered. */
5895 info
.tdep_info
= (void *) tdesc_data
;
5896 gdbarch_init_osabi (info
, gdbarch
);
5898 /* Unwind the frame. */
5899 dwarf2_append_unwinders (gdbarch
);
5900 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
5901 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
5902 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
5903 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5904 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5905 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5906 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5910 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5911 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
5913 /* Override the normal target description methods to handle our
5914 dual real and pseudo registers. */
5915 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5916 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5918 num_regs
= gdbarch_num_regs (gdbarch
);
5919 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5920 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5921 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5924 /* Add ABI-specific aliases for the registers. */
5925 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5926 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5927 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5928 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5930 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5931 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5932 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5934 /* Add some other standard aliases. */
5935 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5936 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5937 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5943 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5945 struct gdbarch_info info
;
5947 /* Force the architecture to update, and (if it's a MIPS architecture)
5948 mips_gdbarch_init will take care of the rest. */
5949 gdbarch_info_init (&info
);
5950 gdbarch_update_p (info
);
5953 /* Print out which MIPS ABI is in use. */
5956 show_mips_abi (struct ui_file
*file
,
5958 struct cmd_list_element
*ignored_cmd
,
5959 const char *ignored_value
)
5961 if (gdbarch_bfd_arch_info (target_gdbarch
)->arch
!= bfd_arch_mips
)
5964 "The MIPS ABI is unknown because the current architecture "
5968 enum mips_abi global_abi
= global_mips_abi ();
5969 enum mips_abi actual_abi
= mips_abi (target_gdbarch
);
5970 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5972 if (global_abi
== MIPS_ABI_UNKNOWN
)
5975 "The MIPS ABI is set automatically (currently \"%s\").\n",
5977 else if (global_abi
== actual_abi
)
5980 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5984 /* Probably shouldn't happen... */
5987 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5988 actual_abi_str
, mips_abi_strings
[global_abi
]);
5994 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
5996 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6000 int ef_mips_32bitmode
;
6001 /* Determine the ISA. */
6002 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
6020 /* Determine the size of a pointer. */
6021 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
6022 fprintf_unfiltered (file
,
6023 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
6025 fprintf_unfiltered (file
,
6026 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
6028 fprintf_unfiltered (file
,
6029 "mips_dump_tdep: ef_mips_arch = %d\n",
6031 fprintf_unfiltered (file
,
6032 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
6033 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
6034 fprintf_unfiltered (file
,
6035 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
6036 mips_mask_address_p (tdep
),
6037 tdep
->default_mask_address_p
);
6039 fprintf_unfiltered (file
,
6040 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
6041 MIPS_DEFAULT_FPU_TYPE
,
6042 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
6043 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
6044 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
6046 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
6047 MIPS_EABI (gdbarch
));
6048 fprintf_unfiltered (file
,
6049 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
6050 MIPS_FPU_TYPE (gdbarch
),
6051 (MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_NONE
? "none"
6052 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_SINGLE
? "single"
6053 : MIPS_FPU_TYPE (gdbarch
) == MIPS_FPU_DOUBLE
? "double"
6057 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
6060 _initialize_mips_tdep (void)
6062 static struct cmd_list_element
*mipsfpulist
= NULL
;
6063 struct cmd_list_element
*c
;
6065 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
6066 if (MIPS_ABI_LAST
+ 1
6067 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
6068 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
6070 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
6072 mips_pdr_data
= register_objfile_data ();
6074 /* Create feature sets with the appropriate properties. The values
6075 are not important. */
6076 mips_tdesc_gp32
= allocate_target_description ();
6077 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
6079 mips_tdesc_gp64
= allocate_target_description ();
6080 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
6082 /* Add root prefix command for all "set mips"/"show mips" commands */
6083 add_prefix_cmd ("mips", no_class
, set_mips_command
,
6084 _("Various MIPS specific commands."),
6085 &setmipscmdlist
, "set mips ", 0, &setlist
);
6087 add_prefix_cmd ("mips", no_class
, show_mips_command
,
6088 _("Various MIPS specific commands."),
6089 &showmipscmdlist
, "show mips ", 0, &showlist
);
6091 /* Allow the user to override the ABI. */
6092 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
6093 &mips_abi_string
, _("\
6094 Set the MIPS ABI used by this program."), _("\
6095 Show the MIPS ABI used by this program."), _("\
6096 This option can be set to one of:\n\
6097 auto - the default ABI associated with the current binary\n\
6106 &setmipscmdlist
, &showmipscmdlist
);
6108 /* Let the user turn off floating point and set the fence post for
6109 heuristic_proc_start. */
6111 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
6112 _("Set use of MIPS floating-point coprocessor."),
6113 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
6114 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
6115 _("Select single-precision MIPS floating-point coprocessor."),
6117 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
6118 _("Select double-precision MIPS floating-point coprocessor."),
6120 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
6121 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
6122 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
6123 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
6124 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
6125 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
6126 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
6127 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
6128 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
6129 _("Select MIPS floating-point coprocessor automatically."),
6131 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
6132 _("Show current use of MIPS floating-point coprocessor target."),
6135 /* We really would like to have both "0" and "unlimited" work, but
6136 command.c doesn't deal with that. So make it a var_zinteger
6137 because the user can always use "999999" or some such for unlimited. */
6138 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
6139 &heuristic_fence_post
, _("\
6140 Set the distance searched for the start of a function."), _("\
6141 Show the distance searched for the start of a function."), _("\
6142 If you are debugging a stripped executable, GDB needs to search through the\n\
6143 program for the start of a function. This command sets the distance of the\n\
6144 search. The only need to set it is when debugging a stripped executable."),
6145 reinit_frame_cache_sfunc
,
6146 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
6147 &setlist
, &showlist
);
6149 /* Allow the user to control whether the upper bits of 64-bit
6150 addresses should be zeroed. */
6151 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
6152 &mask_address_var
, _("\
6153 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
6154 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
6155 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
6156 allow GDB to determine the correct value."),
6157 NULL
, show_mask_address
,
6158 &setmipscmdlist
, &showmipscmdlist
);
6160 /* Allow the user to control the size of 32 bit registers within the
6161 raw remote packet. */
6162 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
6163 &mips64_transfers_32bit_regs_p
, _("\
6164 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6166 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
6168 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
6169 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
6170 64 bits for others. Use \"off\" to disable compatibility mode"),
6171 set_mips64_transfers_32bit_regs
,
6172 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
6173 &setlist
, &showlist
);
6175 /* Debug this files internals. */
6176 add_setshow_zinteger_cmd ("mips", class_maintenance
,
6178 Set mips debugging."), _("\
6179 Show mips debugging."), _("\
6180 When non-zero, mips specific debugging is enabled."),
6182 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
6183 &setdebuglist
, &showdebuglist
);