gdb/mips-tdep.h

   1 /* Target-dependent header for the MIPS architecture, for GDB, the GNU Debugger.
   2
   3    Copyright (C) 2002-2003, 2007-2012 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef MIPS_TDEP_H
  21 #define MIPS_TDEP_H
  22
  23 struct gdbarch;
  24
  25 /* All the possible MIPS ABIs.  */
  26 enum mips_abi
  27   {
  28     MIPS_ABI_UNKNOWN = 0,
  29     MIPS_ABI_N32,
  30     MIPS_ABI_O32,
  31     MIPS_ABI_N64,
  32     MIPS_ABI_O64,
  33     MIPS_ABI_EABI32,
  34     MIPS_ABI_EABI64,
  35     MIPS_ABI_LAST
  36   };
  37
  38 /* Return the MIPS ABI associated with GDBARCH.  */
  39 enum mips_abi mips_abi (struct gdbarch *gdbarch);
  40
  41 /* Return the MIPS ISA's register size.  Just a short cut to the BFD
  42    architecture's word size.  */
  43 extern int mips_isa_regsize (struct gdbarch *gdbarch);
  44
  45 /* Return the current index for various MIPS registers.  */
  46 struct mips_regnum
  47 {
  48   int pc;
  49   int fp0;
  50   int fp_implementation_revision;
  51   int fp_control_status;
  52   int badvaddr;         /* Bad vaddr for addressing exception.  */
  53   int cause;            /* Describes last exception.  */
  54   int hi;               /* Multiply/divide temp.  */
  55   int lo;               /* ...  */
  56   int dspacc;           /* SmartMIPS/DSP accumulators.  */
  57   int dspctl;           /* DSP control.  */
  58 };
  59 extern const struct mips_regnum *mips_regnum (struct gdbarch *gdbarch);
  60
  61 /* Some MIPS boards don't support floating point while others only
  62    support single-precision floating-point operations.  */
  63
  64 enum mips_fpu_type
  65 {
  66   MIPS_FPU_DOUBLE,              /* Full double precision floating point.  */
  67   MIPS_FPU_SINGLE,              /* Single precision floating point (R4650).  */
  68   MIPS_FPU_NONE                 /* No floating point.  */
  69 };
  70
  71 /* MIPS specific per-architecture information.  */
  72 struct gdbarch_tdep
  73 {
  74   /* from the elf header */
  75   int elf_flags;
  76
  77   /* mips options */
  78   enum mips_abi mips_abi;
  79   enum mips_abi found_abi;
  80   enum mips_fpu_type mips_fpu_type;
  81   int mips_last_arg_regnum;
  82   int mips_last_fp_arg_regnum;
  83   int default_mask_address_p;
  84   /* Is the target using 64-bit raw integer registers but only
  85      storing a left-aligned 32-bit value in each?  */
  86   int mips64_transfers_32bit_regs_p;
  87   /* Indexes for various registers.  IRIX and embedded have
  88      different values.  This contains the "public" fields.  Don't
  89      add any that do not need to be public.  */
  90   const struct mips_regnum *regnum;
  91   /* Register names table for the current register set.  */
  92   const char **mips_processor_reg_names;
  93
  94   /* The size of register data available from the target, if known.
  95      This doesn't quite obsolete the manual
  96      mips64_transfers_32bit_regs_p, since that is documented to force
  97      left alignment even for big endian (very strange).  */
  98   int register_size_valid_p;
  99   int register_size;
 100
 101   /* General-purpose registers.  */
 102   struct regset *gregset;
 103   struct regset *gregset64;
 104
 105   /* Floating-point registers.  */
 106   struct regset *fpregset;
 107   struct regset *fpregset64;
 108
 109   /* Return the expected next PC if FRAME is stopped at a syscall
 110      instruction.  */
 111   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
 112 };
 113
 114 /* Register numbers of various important registers.  */
 115
 116 enum
 117 {
 118   MIPS_ZERO_REGNUM = 0,         /* Read-only register, always 0.  */
 119   MIPS_AT_REGNUM = 1,
 120   MIPS_V0_REGNUM = 2,           /* Function integer return value.  */
 121   MIPS_A0_REGNUM = 4,           /* Loc of first arg during a subr call.  */
 122   MIPS_S2_REGNUM = 18,          /* Contains return address in MIPS16 thunks. */
 123   MIPS_T9_REGNUM = 25,          /* Contains address of callee in PIC.  */
 124   MIPS_GP_REGNUM = 28,
 125   MIPS_SP_REGNUM = 29,
 126   MIPS_RA_REGNUM = 31,
 127   MIPS_PS_REGNUM = 32,          /* Contains processor status.  */
 128   MIPS_EMBED_LO_REGNUM = 33,
 129   MIPS_EMBED_HI_REGNUM = 34,
 130   MIPS_EMBED_BADVADDR_REGNUM = 35,
 131   MIPS_EMBED_CAUSE_REGNUM = 36,
 132   MIPS_EMBED_PC_REGNUM = 37,
 133   MIPS_EMBED_FP0_REGNUM = 38,
 134   MIPS_UNUSED_REGNUM = 73,      /* Never used, FIXME.  */
 135   MIPS_FIRST_EMBED_REGNUM = 74, /* First CP0 register for embedded use.  */
 136   MIPS_PRID_REGNUM = 89,        /* Processor ID.  */
 137   MIPS_LAST_EMBED_REGNUM = 89   /* Last one.  */
 138 };
 139
 140 /* Defined in mips-tdep.c and used in remote-mips.c.  */
 141 extern void deprecated_mips_set_processor_regs_hack (void);
 142
 143 /* Instruction sizes and other useful constants.  */
 144 enum
 145 {
 146   MIPS_INSN16_SIZE = 2,
 147   MIPS_INSN32_SIZE = 4,
 148   /* The number of floating-point or integer registers.  */
 149   MIPS_NUMREGS = 32
 150 };
 151
 152 /* Single step based on where the current instruction will take us.  */
 153 extern int mips_software_single_step (struct frame_info *frame);
 154
 155 /* Tell if the program counter value in MEMADDR is in a MIPS16
 156    function.  */
 157 extern int mips_pc_is_mips16 (bfd_vma memaddr);
 158
 159 /* Return the currently configured (or set) saved register size.  */
 160 extern unsigned int mips_abi_regsize (struct gdbarch *gdbarch);
 161
 162 /* Target descriptions which only indicate the size of general
 163    registers.  */
 164 extern struct target_desc *mips_tdesc_gp32;
 165 extern struct target_desc *mips_tdesc_gp64;
 166
 167 #endif /* MIPS_TDEP_H */