gdb/nat/aarch64-linux-hw-point.c

   1 /* Copyright (C) 2009-2015 Free Software Foundation, Inc.
   2    Contributed by ARM Ltd.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "common-defs.h"
  20 #include "break-common.h"
  21 #include "aarch64-linux-hw-point.h"
  22
  23 #include <sys/uio.h>
  24 #include <asm/ptrace.h>
  25 #include <sys/ptrace.h>
  26 #include <elf.h>
  27
  28 /* Number of hardware breakpoints/watchpoints the target supports.
  29    They are initialized with values obtained via the ptrace calls
  30    with NT_ARM_HW_BREAK and NT_ARM_HW_WATCH respectively.  */
  31
  32 int aarch64_num_bp_regs;
  33 int aarch64_num_wp_regs;
  34
  35 /* Utility function that returns the length in bytes of a watchpoint
  36    according to the content of a hardware debug control register CTRL.
  37    Note that the kernel currently only supports the following Byte
  38    Address Select (BAS) values: 0x1, 0x3, 0xf and 0xff, which means
  39    that for a hardware watchpoint, its valid length can only be 1
  40    byte, 2 bytes, 4 bytes or 8 bytes.  */
  41
  42 unsigned int
  43 aarch64_watchpoint_length (unsigned int ctrl)
  44 {
  45   switch (DR_CONTROL_LENGTH (ctrl))
  46     {
  47     case 0x01:
  48       return 1;
  49     case 0x03:
  50       return 2;
  51     case 0x0f:
  52       return 4;
  53     case 0xff:
  54       return 8;
  55     default:
  56       return 0;
  57     }
  58 }
  59
  60 /* Given the hardware breakpoint or watchpoint type TYPE and its
  61    length LEN, return the expected encoding for a hardware
  62    breakpoint/watchpoint control register.  */
  63
  64 static unsigned int
  65 aarch64_point_encode_ctrl_reg (enum target_hw_bp_type type, int len)
  66 {
  67   unsigned int ctrl, ttype;
  68
  69   /* type */
  70   switch (type)
  71     {
  72     case hw_write:
  73       ttype = 2;
  74       break;
  75     case hw_read:
  76       ttype = 1;
  77       break;
  78     case hw_access:
  79       ttype = 3;
  80       break;
  81     case hw_execute:
  82       ttype = 0;
  83       break;
  84     default:
  85       perror_with_name (_("Unrecognized breakpoint/watchpoint type"));
  86     }
  87
  88   ctrl = ttype << 3;
  89
  90   /* length bitmask */
  91   ctrl |= ((1 << len) - 1) << 5;
  92   /* enabled at el0 */
  93   ctrl |= (2 << 1) | 1;
  94
  95   return ctrl;
  96 }
  97
  98 /* Addresses to be written to the hardware breakpoint and watchpoint
  99    value registers need to be aligned; the alignment is 4-byte and
 100    8-type respectively.  Linux kernel rejects any non-aligned address
 101    it receives from the related ptrace call.  Furthermore, the kernel
 102    currently only supports the following Byte Address Select (BAS)
 103    values: 0x1, 0x3, 0xf and 0xff, which means that for a hardware
 104    watchpoint to be accepted by the kernel (via ptrace call), its
 105    valid length can only be 1 byte, 2 bytes, 4 bytes or 8 bytes.
 106    Despite these limitations, the unaligned watchpoint is supported in
 107    this port.
 108
 109    Return 0 for any non-compliant ADDR and/or LEN; return 1 otherwise.  */
 110
 111 static int
 112 aarch64_point_is_aligned (int is_watchpoint, CORE_ADDR addr, int len)
 113 {
 114   unsigned int alignment = is_watchpoint ? AARCH64_HWP_ALIGNMENT
 115     : AARCH64_HBP_ALIGNMENT;
 116
 117   if (addr & (alignment - 1))
 118     return 0;
 119
 120   if (len != 8 && len != 4 && len != 2 && len != 1)
 121     return 0;
 122
 123   return 1;
 124 }
 125
 126 /* Given the (potentially unaligned) watchpoint address in ADDR and
 127    length in LEN, return the aligned address and aligned length in
 128    *ALIGNED_ADDR_P and *ALIGNED_LEN_P, respectively.  The returned
 129    aligned address and length will be valid values to write to the
 130    hardware watchpoint value and control registers.
 131
 132    The given watchpoint may get truncated if more than one hardware
 133    register is needed to cover the watched region.  *NEXT_ADDR_P
 134    and *NEXT_LEN_P, if non-NULL, will return the address and length
 135    of the remaining part of the watchpoint (which can be processed
 136    by calling this routine again to generate another aligned address
 137    and length pair.
 138
 139    Essentially, unaligned watchpoint is achieved by minimally
 140    enlarging the watched area to meet the alignment requirement, and
 141    if necessary, splitting the watchpoint over several hardware
 142    watchpoint registers.  The trade-off is that there will be
 143    false-positive hits for the read-type or the access-type hardware
 144    watchpoints; for the write type, which is more commonly used, there
 145    will be no such issues, as the higher-level breakpoint management
 146    in gdb always examines the exact watched region for any content
 147    change, and transparently resumes a thread from a watchpoint trap
 148    if there is no change to the watched region.
 149
 150    Another limitation is that because the watched region is enlarged,
 151    the watchpoint fault address returned by
 152    aarch64_stopped_data_address may be outside of the original watched
 153    region, especially when the triggering instruction is accessing a
 154    larger region.  When the fault address is not within any known
 155    range, watchpoints_triggered in gdb will get confused, as the
 156    higher-level watchpoint management is only aware of original
 157    watched regions, and will think that some unknown watchpoint has
 158    been triggered.  In such a case, gdb may stop without displaying
 159    any detailed information.
 160
 161    Once the kernel provides the full support for Byte Address Select
 162    (BAS) in the hardware watchpoint control register, these
 163    limitations can be largely relaxed with some further work.  */
 164
 165 static void
 166 aarch64_align_watchpoint (CORE_ADDR addr, int len, CORE_ADDR *aligned_addr_p,
 167                           int *aligned_len_p, CORE_ADDR *next_addr_p,
 168                           int *next_len_p)
 169 {
 170   int aligned_len;
 171   unsigned int offset;
 172   CORE_ADDR aligned_addr;
 173   const unsigned int alignment = AARCH64_HWP_ALIGNMENT;
 174   const unsigned int max_wp_len = AARCH64_HWP_MAX_LEN_PER_REG;
 175
 176   /* As assumed by the algorithm.  */
 177   gdb_assert (alignment == max_wp_len);
 178
 179   if (len <= 0)
 180     return;
 181
 182   /* Address to be put into the hardware watchpoint value register
 183      must be aligned.  */
 184   offset = addr & (alignment - 1);
 185   aligned_addr = addr - offset;
 186
 187   gdb_assert (offset >= 0 && offset < alignment);
 188   gdb_assert (aligned_addr >= 0 && aligned_addr <= addr);
 189   gdb_assert (offset + len > 0);
 190
 191   if (offset + len >= max_wp_len)
 192     {
 193       /* Need more than one watchpoint registers; truncate it at the
 194          alignment boundary.  */
 195       aligned_len = max_wp_len;
 196       len -= (max_wp_len - offset);
 197       addr += (max_wp_len - offset);
 198       gdb_assert ((addr & (alignment - 1)) == 0);
 199     }
 200   else
 201     {
 202       /* Find the smallest valid length that is large enough to
 203          accommodate this watchpoint.  */
 204       static const unsigned char
 205         aligned_len_array[AARCH64_HWP_MAX_LEN_PER_REG] =
 206         { 1, 2, 4, 4, 8, 8, 8, 8 };
 207
 208       aligned_len = aligned_len_array[offset + len - 1];
 209       addr += len;
 210       len = 0;
 211     }
 212
 213   if (aligned_addr_p)
 214     *aligned_addr_p = aligned_addr;
 215   if (aligned_len_p)
 216     *aligned_len_p = aligned_len;
 217   if (next_addr_p)
 218     *next_addr_p = addr;
 219   if (next_len_p)
 220     *next_len_p = len;
 221 }
 222
 223 /* Record the insertion of one breakpoint/watchpoint, as represented
 224    by ADDR and CTRL, in the process' arch-specific data area *STATE.  */
 225
 226 static int
 227 aarch64_dr_state_insert_one_point (struct aarch64_debug_reg_state *state,
 228                                    enum target_hw_bp_type type,
 229                                    CORE_ADDR addr, int len)
 230 {
 231   int i, idx, num_regs, is_watchpoint;
 232   unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
 233   CORE_ADDR *dr_addr_p;
 234
 235   /* Set up state pointers.  */
 236   is_watchpoint = (type != hw_execute);
 237   gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
 238   if (is_watchpoint)
 239     {
 240       num_regs = aarch64_num_wp_regs;
 241       dr_addr_p = state->dr_addr_wp;
 242       dr_ctrl_p = state->dr_ctrl_wp;
 243       dr_ref_count = state->dr_ref_count_wp;
 244     }
 245   else
 246     {
 247       num_regs = aarch64_num_bp_regs;
 248       dr_addr_p = state->dr_addr_bp;
 249       dr_ctrl_p = state->dr_ctrl_bp;
 250       dr_ref_count = state->dr_ref_count_bp;
 251     }
 252
 253   ctrl = aarch64_point_encode_ctrl_reg (type, len);
 254
 255   /* Find an existing or free register in our cache.  */
 256   idx = -1;
 257   for (i = 0; i < num_regs; ++i)
 258     {
 259       if ((dr_ctrl_p[i] & 1) == 0)
 260         {
 261           gdb_assert (dr_ref_count[i] == 0);
 262           idx = i;
 263           /* no break; continue hunting for an exising one.  */
 264         }
 265       else if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
 266         {
 267           gdb_assert (dr_ref_count[i] != 0);
 268           idx = i;
 269           break;
 270         }
 271     }
 272
 273   /* No space.  */
 274   if (idx == -1)
 275     return -1;
 276
 277   /* Update our cache.  */
 278   if ((dr_ctrl_p[idx] & 1) == 0)
 279     {
 280       /* new entry */
 281       dr_addr_p[idx] = addr;
 282       dr_ctrl_p[idx] = ctrl;
 283       dr_ref_count[idx] = 1;
 284       /* Notify the change.  */
 285       aarch64_notify_debug_reg_change (state, is_watchpoint, idx);
 286     }
 287   else
 288     {
 289       /* existing entry */
 290       dr_ref_count[idx]++;
 291     }
 292
 293   return 0;
 294 }
 295
 296 /* Record the removal of one breakpoint/watchpoint, as represented by
 297    ADDR and CTRL, in the process' arch-specific data area *STATE.  */
 298
 299 static int
 300 aarch64_dr_state_remove_one_point (struct aarch64_debug_reg_state *state,
 301                                    enum target_hw_bp_type type,
 302                                    CORE_ADDR addr, int len)
 303 {
 304   int i, num_regs, is_watchpoint;
 305   unsigned int ctrl, *dr_ctrl_p, *dr_ref_count;
 306   CORE_ADDR *dr_addr_p;
 307
 308   /* Set up state pointers.  */
 309   is_watchpoint = (type != hw_execute);
 310   gdb_assert (aarch64_point_is_aligned (is_watchpoint, addr, len));
 311   if (is_watchpoint)
 312     {
 313       num_regs = aarch64_num_wp_regs;
 314       dr_addr_p = state->dr_addr_wp;
 315       dr_ctrl_p = state->dr_ctrl_wp;
 316       dr_ref_count = state->dr_ref_count_wp;
 317     }
 318   else
 319     {
 320       num_regs = aarch64_num_bp_regs;
 321       dr_addr_p = state->dr_addr_bp;
 322       dr_ctrl_p = state->dr_ctrl_bp;
 323       dr_ref_count = state->dr_ref_count_bp;
 324     }
 325
 326   ctrl = aarch64_point_encode_ctrl_reg (type, len);
 327
 328   /* Find the entry that matches the ADDR and CTRL.  */
 329   for (i = 0; i < num_regs; ++i)
 330     if (dr_addr_p[i] == addr && dr_ctrl_p[i] == ctrl)
 331       {
 332         gdb_assert (dr_ref_count[i] != 0);
 333         break;
 334       }
 335
 336   /* Not found.  */
 337   if (i == num_regs)
 338     return -1;
 339
 340   /* Clear our cache.  */
 341   if (--dr_ref_count[i] == 0)
 342     {
 343       /* Clear the enable bit.  */
 344       ctrl &= ~1;
 345       dr_addr_p[i] = 0;
 346       dr_ctrl_p[i] = ctrl;
 347       /* Notify the change.  */
 348       aarch64_notify_debug_reg_change (state, is_watchpoint, i);
 349     }
 350
 351   return 0;
 352 }
 353
 354 int
 355 aarch64_handle_breakpoint (enum target_hw_bp_type type, CORE_ADDR addr,
 356                            int len, int is_insert,
 357                            struct aarch64_debug_reg_state *state)
 358 {
 359   /* The hardware breakpoint on AArch64 should always be 4-byte
 360      aligned.  */
 361   if (!aarch64_point_is_aligned (0 /* is_watchpoint */ , addr, len))
 362     return -1;
 363
 364   if (is_insert)
 365     return aarch64_dr_state_insert_one_point (state, type, addr, len);
 366   else
 367     return aarch64_dr_state_remove_one_point (state, type, addr, len);
 368 }
 369
 370 /* This is essentially the same as aarch64_handle_breakpoint, apart
 371    from that it is an aligned watchpoint to be handled.  */
 372
 373 static int
 374 aarch64_handle_aligned_watchpoint (enum target_hw_bp_type type,
 375                                    CORE_ADDR addr, int len, int is_insert,
 376                                    struct aarch64_debug_reg_state *state)
 377 {
 378   if (is_insert)
 379     return aarch64_dr_state_insert_one_point (state, type, addr, len);
 380   else
 381     return aarch64_dr_state_remove_one_point (state, type, addr, len);
 382 }
 383
 384 /* Insert/remove unaligned watchpoint by calling
 385    aarch64_align_watchpoint repeatedly until the whole watched region,
 386    as represented by ADDR and LEN, has been properly aligned and ready
 387    to be written to one or more hardware watchpoint registers.
 388    IS_INSERT indicates whether this is an insertion or a deletion.
 389    Return 0 if succeed.  */
 390
 391 static int
 392 aarch64_handle_unaligned_watchpoint (enum target_hw_bp_type type,
 393                                      CORE_ADDR addr, int len, int is_insert,
 394                                      struct aarch64_debug_reg_state *state)
 395 {
 396   while (len > 0)
 397     {
 398       CORE_ADDR aligned_addr;
 399       int aligned_len, ret;
 400
 401       aarch64_align_watchpoint (addr, len, &aligned_addr, &aligned_len,
 402                                 &addr, &len);
 403
 404       if (is_insert)
 405         ret = aarch64_dr_state_insert_one_point (state, type, aligned_addr,
 406                                                  aligned_len);
 407       else
 408         ret = aarch64_dr_state_remove_one_point (state, type, aligned_addr,
 409                                                  aligned_len);
 410
 411       if (show_debug_regs)
 412         debug_printf ("handle_unaligned_watchpoint: is_insert: %d\n"
 413                       "                             "
 414                       "aligned_addr: %s, aligned_len: %d\n"
 415                       "                                "
 416                       "next_addr: %s,    next_len: %d\n",
 417                       is_insert, core_addr_to_string_nz (aligned_addr),
 418                       aligned_len, core_addr_to_string_nz (addr), len);
 419
 420       if (ret != 0)
 421         return ret;
 422     }
 423
 424   return 0;
 425 }
 426
 427 int
 428 aarch64_handle_watchpoint (enum target_hw_bp_type type, CORE_ADDR addr,
 429                            int len, int is_insert,
 430                            struct aarch64_debug_reg_state *state)
 431 {
 432   if (aarch64_point_is_aligned (1 /* is_watchpoint */ , addr, len))
 433     return aarch64_handle_aligned_watchpoint (type, addr, len, is_insert,
 434                                               state);
 435   else
 436     return aarch64_handle_unaligned_watchpoint (type, addr, len, is_insert,
 437                                                 state);
 438 }
 439
 440 /* Call ptrace to set the thread TID's hardware breakpoint/watchpoint
 441    registers with data from *STATE.  */
 442
 443 void
 444 aarch64_linux_set_debug_regs (const struct aarch64_debug_reg_state *state,
 445                               int tid, int watchpoint)
 446 {
 447   int i, count;
 448   struct iovec iov;
 449   struct user_hwdebug_state regs;
 450   const CORE_ADDR *addr;
 451   const unsigned int *ctrl;
 452
 453   memset (&regs, 0, sizeof (regs));
 454   iov.iov_base = &regs;
 455   count = watchpoint ? aarch64_num_wp_regs : aarch64_num_bp_regs;
 456   addr = watchpoint ? state->dr_addr_wp : state->dr_addr_bp;
 457   ctrl = watchpoint ? state->dr_ctrl_wp : state->dr_ctrl_bp;
 458   if (count == 0)
 459     return;
 460   iov.iov_len = (offsetof (struct user_hwdebug_state, dbg_regs[count - 1])
 461                  + sizeof (regs.dbg_regs [count - 1]));
 462
 463   for (i = 0; i < count; i++)
 464     {
 465       regs.dbg_regs[i].addr = addr[i];
 466       regs.dbg_regs[i].ctrl = ctrl[i];
 467     }
 468
 469   if (ptrace (PTRACE_SETREGSET, tid,
 470               watchpoint ? NT_ARM_HW_WATCH : NT_ARM_HW_BREAK,
 471               (void *) &iov))
 472     error (_("Unexpected error setting hardware debug registers"));
 473 }
 474
 475 /* Print the values of the cached breakpoint/watchpoint registers.  */
 476
 477 void
 478 aarch64_show_debug_reg_state (struct aarch64_debug_reg_state *state,
 479                               const char *func, CORE_ADDR addr,
 480                               int len, enum target_hw_bp_type type)
 481 {
 482   int i;
 483
 484   debug_printf ("%s", func);
 485   if (addr || len)
 486     debug_printf (" (addr=0x%08lx, len=%d, type=%s)",
 487                   (unsigned long) addr, len,
 488                   type == hw_write ? "hw-write-watchpoint"
 489                   : (type == hw_read ? "hw-read-watchpoint"
 490                      : (type == hw_access ? "hw-access-watchpoint"
 491                         : (type == hw_execute ? "hw-breakpoint"
 492                            : "??unknown??"))));
 493   debug_printf (":\n");
 494
 495   debug_printf ("\tBREAKPOINTs:\n");
 496   for (i = 0; i < aarch64_num_bp_regs; i++)
 497     debug_printf ("\tBP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
 498                   i, core_addr_to_string_nz (state->dr_addr_bp[i]),
 499                   state->dr_ctrl_bp[i], state->dr_ref_count_bp[i]);
 500
 501   debug_printf ("\tWATCHPOINTs:\n");
 502   for (i = 0; i < aarch64_num_wp_regs; i++)
 503     debug_printf ("\tWP%d: addr=%s, ctrl=0x%08x, ref.count=%d\n",
 504                   i, core_addr_to_string_nz (state->dr_addr_wp[i]),
 505                   state->dr_ctrl_wp[i], state->dr_ref_count_wp[i]);
 506 }
 507
 508 /* Get the hardware debug register capacity information from the
 509    process represented by TID.  */
 510
 511 void
 512 aarch64_linux_get_debug_reg_capacity (int tid)
 513 {
 514   struct iovec iov;
 515   struct user_hwdebug_state dreg_state;
 516
 517   iov.iov_base = &dreg_state;
 518   iov.iov_len = sizeof (dreg_state);
 519
 520   /* Get hardware watchpoint register info.  */
 521   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_WATCH, &iov) == 0
 522       && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
 523     {
 524       aarch64_num_wp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
 525       if (aarch64_num_wp_regs > AARCH64_HWP_MAX_NUM)
 526         {
 527           warning (_("Unexpected number of hardware watchpoint registers"
 528                      " reported by ptrace, got %d, expected %d."),
 529                    aarch64_num_wp_regs, AARCH64_HWP_MAX_NUM);
 530           aarch64_num_wp_regs = AARCH64_HWP_MAX_NUM;
 531         }
 532     }
 533   else
 534     {
 535       warning (_("Unable to determine the number of hardware watchpoints"
 536                  " available."));
 537       aarch64_num_wp_regs = 0;
 538     }
 539
 540   /* Get hardware breakpoint register info.  */
 541   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_HW_BREAK, &iov) == 0
 542       && AARCH64_DEBUG_ARCH (dreg_state.dbg_info) == AARCH64_DEBUG_ARCH_V8)
 543     {
 544       aarch64_num_bp_regs = AARCH64_DEBUG_NUM_SLOTS (dreg_state.dbg_info);
 545       if (aarch64_num_bp_regs > AARCH64_HBP_MAX_NUM)
 546         {
 547           warning (_("Unexpected number of hardware breakpoint registers"
 548                      " reported by ptrace, got %d, expected %d."),
 549                    aarch64_num_bp_regs, AARCH64_HBP_MAX_NUM);
 550           aarch64_num_bp_regs = AARCH64_HBP_MAX_NUM;
 551         }
 552     }
 553   else
 554     {
 555       warning (_("Unable to determine the number of hardware breakpoints"
 556                  " available."));
 557       aarch64_num_bp_regs = 0;
 558     }
 559 }