1 /* Target-machine dependent code for Nios II, for GDB.
2 Copyright (C) 2012-2015 Free Software Foundation, Inc.
3 Contributed by Peter Brookes (pbrookes@altera.com)
4 and Andrew Draper (adraper@altera.com).
5 Contributed by Mentor Graphics, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include "frame-unwind.h"
25 #include "frame-base.h"
26 #include "trad-frame.h"
27 #include "dwarf2-frame.h"
39 #include "arch-utils.h"
40 #include "floatformat.h"
43 #include "target-descriptions.h"
45 /* To get entry_point_address. */
48 /* Nios II specific header. */
49 #include "nios2-tdep.h"
51 #include "features/nios2.c"
53 /* Control debugging information emitted in this file. */
55 static int nios2_debug
= 0;
57 /* The following structures are used in the cache for prologue
58 analysis; see the reg_value and reg_saved tables in
59 struct nios2_unwind_cache, respectively. */
61 /* struct reg_value is used to record that a register has the same value
62 as reg at the given offset from the start of a function. */
70 /* struct reg_saved is used to record that a register value has been saved at
71 basereg + addr, for basereg >= 0. If basereg < 0, that indicates
72 that the register is not known to have been saved. Note that when
73 basereg == NIOS2_Z_REGNUM (that is, r0, which holds value 0),
74 addr is an absolute address. */
82 struct nios2_unwind_cache
84 /* The frame's base, optionally used by the high-level debug info. */
87 /* The previous frame's inner most stack address. Used as this
88 frame ID's stack_addr. */
91 /* The address of the first instruction in this function. */
94 /* Which register holds the return address for the frame. */
97 /* Table indicating what changes have been made to each register. */
98 struct reg_value reg_value
[NIOS2_NUM_REGS
];
100 /* Table indicating where each register has been saved. */
101 struct reg_saved reg_saved
[NIOS2_NUM_REGS
];
105 /* This array is a mapping from Dwarf-2 register numbering to GDB's. */
107 static int nios2_dwarf2gdb_regno_map
[] =
116 NIOS2_GP_REGNUM
, /* 26 */
117 NIOS2_SP_REGNUM
, /* 27 */
118 NIOS2_FP_REGNUM
, /* 28 */
119 NIOS2_EA_REGNUM
, /* 29 */
120 NIOS2_BA_REGNUM
, /* 30 */
121 NIOS2_RA_REGNUM
, /* 31 */
122 NIOS2_PC_REGNUM
, /* 32 */
123 NIOS2_STATUS_REGNUM
, /* 33 */
124 NIOS2_ESTATUS_REGNUM
, /* 34 */
125 NIOS2_BSTATUS_REGNUM
, /* 35 */
126 NIOS2_IENABLE_REGNUM
, /* 36 */
127 NIOS2_IPENDING_REGNUM
, /* 37 */
128 NIOS2_CPUID_REGNUM
, /* 38 */
129 39, /* CTL6 */ /* 39 */
130 NIOS2_EXCEPTION_REGNUM
, /* 40 */
131 NIOS2_PTEADDR_REGNUM
, /* 41 */
132 NIOS2_TLBACC_REGNUM
, /* 42 */
133 NIOS2_TLBMISC_REGNUM
, /* 43 */
134 NIOS2_ECCINJ_REGNUM
, /* 44 */
135 NIOS2_BADADDR_REGNUM
, /* 45 */
136 NIOS2_CONFIG_REGNUM
, /* 46 */
137 NIOS2_MPUBASE_REGNUM
, /* 47 */
138 NIOS2_MPUACC_REGNUM
/* 48 */
142 /* Implement the dwarf2_reg_to_regnum gdbarch method. */
145 nios2_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int dw_reg
)
147 if (dw_reg
< 0 || dw_reg
> NIOS2_NUM_REGS
)
149 warning (_("Dwarf-2 uses unmapped register #%d"), dw_reg
);
153 return nios2_dwarf2gdb_regno_map
[dw_reg
];
156 /* Canonical names for the 49 registers. */
158 static const char *const nios2_reg_names
[NIOS2_NUM_REGS
] =
160 "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7",
161 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
162 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
163 "et", "bt", "gp", "sp", "fp", "ea", "sstatus", "ra",
165 "status", "estatus", "bstatus", "ienable",
166 "ipending", "cpuid", "ctl6", "exception",
167 "pteaddr", "tlbacc", "tlbmisc", "eccinj",
168 "badaddr", "config", "mpubase", "mpuacc"
171 /* Implement the register_name gdbarch method. */
174 nios2_register_name (struct gdbarch
*gdbarch
, int regno
)
176 /* Use mnemonic aliases for GPRs. */
177 if (regno
>= 0 && regno
< NIOS2_NUM_REGS
)
178 return nios2_reg_names
[regno
];
180 return tdesc_register_name (gdbarch
, regno
);
183 /* Implement the register_type gdbarch method. */
186 nios2_register_type (struct gdbarch
*gdbarch
, int regno
)
188 /* If the XML description has register information, use that to
189 determine the register type. */
190 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
191 return tdesc_register_type (gdbarch
, regno
);
193 if (regno
== NIOS2_PC_REGNUM
)
194 return builtin_type (gdbarch
)->builtin_func_ptr
;
195 else if (regno
== NIOS2_SP_REGNUM
)
196 return builtin_type (gdbarch
)->builtin_data_ptr
;
198 return builtin_type (gdbarch
)->builtin_uint32
;
201 /* Given a return value in REGCACHE with a type VALTYPE,
202 extract and copy its value into VALBUF. */
205 nios2_extract_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
206 struct regcache
*regcache
, gdb_byte
*valbuf
)
208 int len
= TYPE_LENGTH (valtype
);
210 /* Return values of up to 8 bytes are returned in $r2 $r3. */
211 if (len
<= register_size (gdbarch
, NIOS2_R2_REGNUM
))
212 regcache_cooked_read (regcache
, NIOS2_R2_REGNUM
, valbuf
);
215 gdb_assert (len
<= (register_size (gdbarch
, NIOS2_R2_REGNUM
)
216 + register_size (gdbarch
, NIOS2_R3_REGNUM
)));
217 regcache_cooked_read (regcache
, NIOS2_R2_REGNUM
, valbuf
);
218 regcache_cooked_read (regcache
, NIOS2_R3_REGNUM
, valbuf
+ 4);
222 /* Write into appropriate registers a function return value
223 of type TYPE, given in virtual format. */
226 nios2_store_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
227 struct regcache
*regcache
, const gdb_byte
*valbuf
)
229 int len
= TYPE_LENGTH (valtype
);
231 /* Return values of up to 8 bytes are returned in $r2 $r3. */
232 if (len
<= register_size (gdbarch
, NIOS2_R2_REGNUM
))
233 regcache_cooked_write (regcache
, NIOS2_R2_REGNUM
, valbuf
);
236 gdb_assert (len
<= (register_size (gdbarch
, NIOS2_R2_REGNUM
)
237 + register_size (gdbarch
, NIOS2_R3_REGNUM
)));
238 regcache_cooked_write (regcache
, NIOS2_R2_REGNUM
, valbuf
);
239 regcache_cooked_write (regcache
, NIOS2_R3_REGNUM
, valbuf
+ 4);
244 /* Set up the default values of the registers. */
247 nios2_setup_default (struct nios2_unwind_cache
*cache
)
251 for (i
= 0; i
< NIOS2_NUM_REGS
; i
++)
253 /* All registers start off holding their previous values. */
254 cache
->reg_value
[i
].reg
= i
;
255 cache
->reg_value
[i
].offset
= 0;
257 /* All registers start off not saved. */
258 cache
->reg_saved
[i
].basereg
= -1;
259 cache
->reg_saved
[i
].addr
= 0;
263 /* Initialize the unwind cache. */
266 nios2_init_cache (struct nios2_unwind_cache
*cache
, CORE_ADDR pc
)
271 cache
->return_regnum
= NIOS2_RA_REGNUM
;
272 nios2_setup_default (cache
);
275 /* Read and identify an instruction at PC. If INSNP is non-null,
276 store the instruction word into that location. Return the opcode
277 pointer or NULL if the memory couldn't be read or disassembled. */
279 static const struct nios2_opcode
*
280 nios2_fetch_insn (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
284 unsigned long mach
= gdbarch_bfd_arch_info (gdbarch
)->mach
;
287 if (mach
== bfd_mach_nios2r2
)
289 if (!safe_read_memory_integer (pc
, NIOS2_OPCODE_SIZE
,
290 BFD_ENDIAN_LITTLE
, &memword
)
291 && !safe_read_memory_integer (pc
, NIOS2_CDX_OPCODE_SIZE
,
292 BFD_ENDIAN_LITTLE
, &memword
))
295 else if (!safe_read_memory_integer (pc
, NIOS2_OPCODE_SIZE
,
296 gdbarch_byte_order (gdbarch
), &memword
))
299 insn
= (unsigned int) memword
;
302 return nios2_find_opcode_hash (insn
, mach
);
306 /* Match and disassemble an ADD-type instruction, with 3 register operands.
307 Returns true on success, and fills in the operand pointers. */
310 nios2_match_add (uint32_t insn
, const struct nios2_opcode
*op
,
311 unsigned long mach
, int *ra
, int *rb
, int *rc
)
313 int is_r2
= (mach
== bfd_mach_nios2r2
);
315 if (!is_r2
&& (op
->match
== MATCH_R1_ADD
|| op
->match
== MATCH_R1_MOV
))
317 *ra
= GET_IW_R_A (insn
);
318 *rb
= GET_IW_R_B (insn
);
319 *rc
= GET_IW_R_C (insn
);
324 else if (op
->match
== MATCH_R2_ADD
|| op
->match
== MATCH_R2_MOV
)
326 *ra
= GET_IW_F3X6L5_A (insn
);
327 *rb
= GET_IW_F3X6L5_B (insn
);
328 *rc
= GET_IW_F3X6L5_C (insn
);
331 else if (op
->match
== MATCH_R2_ADD_N
)
333 *ra
= nios2_r2_reg3_mappings
[GET_IW_T3X1_A3 (insn
)];
334 *rb
= nios2_r2_reg3_mappings
[GET_IW_T3X1_B3 (insn
)];
335 *rc
= nios2_r2_reg3_mappings
[GET_IW_T3X1_C3 (insn
)];
338 else if (op
->match
== MATCH_R2_MOV_N
)
340 *ra
= GET_IW_F2_A (insn
);
342 *rc
= GET_IW_F2_B (insn
);
348 /* Match and disassemble a SUB-type instruction, with 3 register operands.
349 Returns true on success, and fills in the operand pointers. */
352 nios2_match_sub (uint32_t insn
, const struct nios2_opcode
*op
,
353 unsigned long mach
, int *ra
, int *rb
, int *rc
)
355 int is_r2
= (mach
== bfd_mach_nios2r2
);
357 if (!is_r2
&& op
->match
== MATCH_R1_SUB
)
359 *ra
= GET_IW_R_A (insn
);
360 *rb
= GET_IW_R_B (insn
);
361 *rc
= GET_IW_R_C (insn
);
366 else if (op
->match
== MATCH_R2_SUB
)
368 *ra
= GET_IW_F3X6L5_A (insn
);
369 *rb
= GET_IW_F3X6L5_B (insn
);
370 *rc
= GET_IW_F3X6L5_C (insn
);
373 else if (op
->match
== MATCH_R2_SUB_N
)
375 *ra
= nios2_r2_reg3_mappings
[GET_IW_T3X1_A3 (insn
)];
376 *rb
= nios2_r2_reg3_mappings
[GET_IW_T3X1_B3 (insn
)];
377 *rc
= nios2_r2_reg3_mappings
[GET_IW_T3X1_C3 (insn
)];
383 /* Match and disassemble an ADDI-type instruction, with 2 register operands
384 and one immediate operand.
385 Returns true on success, and fills in the operand pointers. */
388 nios2_match_addi (uint32_t insn
, const struct nios2_opcode
*op
,
389 unsigned long mach
, int *ra
, int *rb
, int *imm
)
391 int is_r2
= (mach
== bfd_mach_nios2r2
);
393 if (!is_r2
&& op
->match
== MATCH_R1_ADDI
)
395 *ra
= GET_IW_I_A (insn
);
396 *rb
= GET_IW_I_B (insn
);
397 *imm
= (signed) (GET_IW_I_IMM16 (insn
) << 16) >> 16;
402 else if (op
->match
== MATCH_R2_ADDI
)
404 *ra
= GET_IW_F2I16_A (insn
);
405 *rb
= GET_IW_F2I16_B (insn
);
406 *imm
= (signed) (GET_IW_F2I16_IMM16 (insn
) << 16) >> 16;
409 else if (op
->match
== MATCH_R2_ADDI_N
|| op
->match
== MATCH_R2_SUBI_N
)
411 *ra
= nios2_r2_reg3_mappings
[GET_IW_T2X1I3_A3 (insn
)];
412 *rb
= nios2_r2_reg3_mappings
[GET_IW_T2X1I3_B3 (insn
)];
413 *imm
= nios2_r2_asi_n_mappings
[GET_IW_T2X1I3_IMM3 (insn
)];
414 if (op
->match
== MATCH_R2_SUBI_N
)
418 else if (op
->match
== MATCH_R2_SPADDI_N
)
420 *ra
= nios2_r2_reg3_mappings
[GET_IW_T1I7_A3 (insn
)];
421 *rb
= NIOS2_SP_REGNUM
;
422 *imm
= GET_IW_T1I7_IMM7 (insn
) << 2;
425 else if (op
->match
== MATCH_R2_SPINCI_N
|| op
->match
== MATCH_R2_SPDECI_N
)
427 *ra
= NIOS2_SP_REGNUM
;
428 *rb
= NIOS2_SP_REGNUM
;
429 *imm
= GET_IW_X1I7_IMM7 (insn
) << 2;
430 if (op
->match
== MATCH_R2_SPDECI_N
)
437 /* Match and disassemble an ORHI-type instruction, with 2 register operands
438 and one unsigned immediate operand.
439 Returns true on success, and fills in the operand pointers. */
442 nios2_match_orhi (uint32_t insn
, const struct nios2_opcode
*op
,
443 unsigned long mach
, int *ra
, int *rb
, unsigned int *uimm
)
445 int is_r2
= (mach
== bfd_mach_nios2r2
);
447 if (!is_r2
&& op
->match
== MATCH_R1_ORHI
)
449 *ra
= GET_IW_I_A (insn
);
450 *rb
= GET_IW_I_B (insn
);
451 *uimm
= GET_IW_I_IMM16 (insn
);
456 else if (op
->match
== MATCH_R2_ORHI
)
458 *ra
= GET_IW_F2I16_A (insn
);
459 *rb
= GET_IW_F2I16_B (insn
);
460 *uimm
= GET_IW_F2I16_IMM16 (insn
);
466 /* Match and disassemble a STW-type instruction, with 2 register operands
467 and one immediate operand.
468 Returns true on success, and fills in the operand pointers. */
471 nios2_match_stw (uint32_t insn
, const struct nios2_opcode
*op
,
472 unsigned long mach
, int *ra
, int *rb
, int *imm
)
474 int is_r2
= (mach
== bfd_mach_nios2r2
);
476 if (!is_r2
&& (op
->match
== MATCH_R1_STW
|| op
->match
== MATCH_R1_STWIO
))
478 *ra
= GET_IW_I_A (insn
);
479 *rb
= GET_IW_I_B (insn
);
480 *imm
= (signed) (GET_IW_I_IMM16 (insn
) << 16) >> 16;
485 else if (op
->match
== MATCH_R2_STW
)
487 *ra
= GET_IW_F2I16_A (insn
);
488 *rb
= GET_IW_F2I16_B (insn
);
489 *imm
= (signed) (GET_IW_F2I16_IMM16 (insn
) << 16) >> 16;
492 else if (op
->match
== MATCH_R2_STWIO
)
494 *ra
= GET_IW_F2X4I12_A (insn
);
495 *rb
= GET_IW_F2X4I12_B (insn
);
496 *imm
= (signed) (GET_IW_F2X4I12_IMM12 (insn
) << 20) >> 20;
499 else if (op
->match
== MATCH_R2_STW_N
)
501 *ra
= nios2_r2_reg3_mappings
[GET_IW_T2I4_A3 (insn
)];
502 *rb
= nios2_r2_reg3_mappings
[GET_IW_T2I4_B3 (insn
)];
503 *imm
= GET_IW_T2I4_IMM4 (insn
) << 2;
506 else if (op
->match
== MATCH_R2_STWSP_N
)
508 *ra
= NIOS2_SP_REGNUM
;
509 *rb
= GET_IW_F1I5_B (insn
);
510 *imm
= GET_IW_F1I5_IMM5 (insn
) << 2;
513 else if (op
->match
== MATCH_R2_STWZ_N
)
515 *ra
= nios2_r2_reg3_mappings
[GET_IW_T1X1I6_A3 (insn
)];
517 *imm
= GET_IW_T1X1I6_IMM6 (insn
) << 2;
523 /* Match and disassemble a LDW-type instruction, with 2 register operands
524 and one immediate operand.
525 Returns true on success, and fills in the operand pointers. */
528 nios2_match_ldw (uint32_t insn
, const struct nios2_opcode
*op
,
529 unsigned long mach
, int *ra
, int *rb
, int *imm
)
531 int is_r2
= (mach
== bfd_mach_nios2r2
);
533 if (!is_r2
&& (op
->match
== MATCH_R1_LDW
|| op
->match
== MATCH_R1_LDWIO
))
535 *ra
= GET_IW_I_A (insn
);
536 *rb
= GET_IW_I_B (insn
);
537 *imm
= (signed) (GET_IW_I_IMM16 (insn
) << 16) >> 16;
542 else if (op
->match
== MATCH_R2_LDW
)
544 *ra
= GET_IW_F2I16_A (insn
);
545 *rb
= GET_IW_F2I16_B (insn
);
546 *imm
= (signed) (GET_IW_F2I16_IMM16 (insn
) << 16) >> 16;
549 else if (op
->match
== MATCH_R2_LDWIO
)
551 *ra
= GET_IW_F2X4I12_A (insn
);
552 *rb
= GET_IW_F2X4I12_B (insn
);
553 *imm
= (signed) (GET_IW_F2X4I12_IMM12 (insn
) << 20) >> 20;
556 else if (op
->match
== MATCH_R2_LDW_N
)
558 *ra
= nios2_r2_reg3_mappings
[GET_IW_T2I4_A3 (insn
)];
559 *rb
= nios2_r2_reg3_mappings
[GET_IW_T2I4_B3 (insn
)];
560 *imm
= GET_IW_T2I4_IMM4 (insn
) << 2;
563 else if (op
->match
== MATCH_R2_LDWSP_N
)
565 *ra
= NIOS2_SP_REGNUM
;
566 *rb
= GET_IW_F1I5_B (insn
);
567 *imm
= GET_IW_F1I5_IMM5 (insn
) << 2;
573 /* Match and disassemble a RDCTL instruction, with 2 register operands.
574 Returns true on success, and fills in the operand pointers. */
577 nios2_match_rdctl (uint32_t insn
, const struct nios2_opcode
*op
,
578 unsigned long mach
, int *ra
, int *rc
)
580 int is_r2
= (mach
== bfd_mach_nios2r2
);
582 if (!is_r2
&& (op
->match
== MATCH_R1_RDCTL
))
584 *ra
= GET_IW_R_IMM5 (insn
);
585 *rc
= GET_IW_R_C (insn
);
590 else if (op
->match
== MATCH_R2_RDCTL
)
592 *ra
= GET_IW_F3X6L5_IMM5 (insn
);
593 *rc
= GET_IW_F3X6L5_C (insn
);
599 /* Match and disassemble a PUSH.N or STWM instruction.
600 Returns true on success, and fills in the operand pointers. */
603 nios2_match_stwm (uint32_t insn
, const struct nios2_opcode
*op
,
604 unsigned long mach
, unsigned int *reglist
,
605 int *ra
, int *imm
, int *wb
, int *id
)
607 int is_r2
= (mach
== bfd_mach_nios2r2
);
611 else if (op
->match
== MATCH_R2_PUSH_N
)
614 if (GET_IW_L5I4X1_FP (insn
))
615 *reglist
|= (1 << 28);
616 if (GET_IW_L5I4X1_CS (insn
))
618 int val
= GET_IW_L5I4X1_REGRANGE (insn
);
619 *reglist
|= nios2_r2_reg_range_mappings
[val
];
621 *ra
= NIOS2_SP_REGNUM
;
622 *imm
= GET_IW_L5I4X1_IMM4 (insn
) << 2;
627 else if (op
->match
== MATCH_R2_STWM
)
629 unsigned int rawmask
= GET_IW_F1X4L17_REGMASK (insn
);
630 if (GET_IW_F1X4L17_RS (insn
))
632 *reglist
= ((rawmask
<< 14) & 0x00ffc000);
633 if (rawmask
& (1 << 10))
634 *reglist
|= (1 << 28);
635 if (rawmask
& (1 << 11))
636 *reglist
|= (1 << 31);
639 *reglist
= rawmask
<< 2;
640 *ra
= GET_IW_F1X4L17_A (insn
);
642 *wb
= GET_IW_F1X4L17_WB (insn
);
643 *id
= GET_IW_F1X4L17_ID (insn
);
649 /* Match and disassemble a POP.N or LDWM instruction.
650 Returns true on success, and fills in the operand pointers. */
653 nios2_match_ldwm (uint32_t insn
, const struct nios2_opcode
*op
,
654 unsigned long mach
, unsigned int *reglist
,
655 int *ra
, int *imm
, int *wb
, int *id
, int *ret
)
657 int is_r2
= (mach
== bfd_mach_nios2r2
);
661 else if (op
->match
== MATCH_R2_POP_N
)
664 if (GET_IW_L5I4X1_FP (insn
))
665 *reglist
|= (1 << 28);
666 if (GET_IW_L5I4X1_CS (insn
))
668 int val
= GET_IW_L5I4X1_REGRANGE (insn
);
669 *reglist
|= nios2_r2_reg_range_mappings
[val
];
671 *ra
= NIOS2_SP_REGNUM
;
672 *imm
= GET_IW_L5I4X1_IMM4 (insn
) << 2;
678 else if (op
->match
== MATCH_R2_LDWM
)
680 unsigned int rawmask
= GET_IW_F1X4L17_REGMASK (insn
);
681 if (GET_IW_F1X4L17_RS (insn
))
683 *reglist
= ((rawmask
<< 14) & 0x00ffc000);
684 if (rawmask
& (1 << 10))
685 *reglist
|= (1 << 28);
686 if (rawmask
& (1 << 11))
687 *reglist
|= (1 << 31);
690 *reglist
= rawmask
<< 2;
691 *ra
= GET_IW_F1X4L17_A (insn
);
693 *wb
= GET_IW_F1X4L17_WB (insn
);
694 *id
= GET_IW_F1X4L17_ID (insn
);
695 *ret
= GET_IW_F1X4L17_PC (insn
);
701 /* Match and disassemble a branch instruction, with (potentially)
702 2 register operands and one immediate operand.
703 Returns true on success, and fills in the operand pointers. */
705 enum branch_condition
{
716 nios2_match_branch (uint32_t insn
, const struct nios2_opcode
*op
,
717 unsigned long mach
, int *ra
, int *rb
, int *imm
,
718 enum branch_condition
*cond
)
720 int is_r2
= (mach
== bfd_mach_nios2r2
);
750 *imm
= (signed) (GET_IW_I_IMM16 (insn
) << 16) >> 16;
751 *ra
= GET_IW_I_A (insn
);
752 *rb
= GET_IW_I_B (insn
);
761 *ra
= NIOS2_Z_REGNUM
;
762 *rb
= NIOS2_Z_REGNUM
;
763 *imm
= (signed) ((GET_IW_I10_IMM10 (insn
) << 1) << 21) >> 21;
765 case MATCH_R2_BEQZ_N
:
767 *ra
= nios2_r2_reg3_mappings
[GET_IW_T1I7_A3 (insn
)];
768 *rb
= NIOS2_Z_REGNUM
;
769 *imm
= (signed) ((GET_IW_T1I7_IMM7 (insn
) << 1) << 24) >> 24;
771 case MATCH_R2_BNEZ_N
:
773 *ra
= nios2_r2_reg3_mappings
[GET_IW_T1I7_A3 (insn
)];
774 *rb
= NIOS2_Z_REGNUM
;
775 *imm
= (signed) ((GET_IW_T1I7_IMM7 (insn
) << 1) << 24) >> 24;
801 *ra
= GET_IW_F2I16_A (insn
);
802 *rb
= GET_IW_F2I16_B (insn
);
803 *imm
= (signed) (GET_IW_F2I16_IMM16 (insn
) << 16) >> 16;
809 /* Match and disassemble a direct jump instruction, with an
810 unsigned operand. Returns true on success, and fills in the operand
814 nios2_match_jmpi (uint32_t insn
, const struct nios2_opcode
*op
,
815 unsigned long mach
, unsigned int *uimm
)
817 int is_r2
= (mach
== bfd_mach_nios2r2
);
819 if (!is_r2
&& op
->match
== MATCH_R1_JMPI
)
821 *uimm
= GET_IW_J_IMM26 (insn
) << 2;
826 else if (op
->match
== MATCH_R2_JMPI
)
828 *uimm
= GET_IW_L26_IMM26 (insn
) << 2;
834 /* Match and disassemble a direct call instruction, with an
835 unsigned operand. Returns true on success, and fills in the operand
839 nios2_match_calli (uint32_t insn
, const struct nios2_opcode
*op
,
840 unsigned long mach
, unsigned int *uimm
)
842 int is_r2
= (mach
== bfd_mach_nios2r2
);
844 if (!is_r2
&& op
->match
== MATCH_R1_CALL
)
846 *uimm
= GET_IW_J_IMM26 (insn
) << 2;
851 else if (op
->match
== MATCH_R2_CALL
)
853 *uimm
= GET_IW_L26_IMM26 (insn
) << 2;
859 /* Match and disassemble an indirect jump instruction, with a
860 (possibly implicit) register operand. Returns true on success, and fills
861 in the operand pointer. */
864 nios2_match_jmpr (uint32_t insn
, const struct nios2_opcode
*op
,
865 unsigned long mach
, int *ra
)
867 int is_r2
= (mach
== bfd_mach_nios2r2
);
873 *ra
= GET_IW_I_A (insn
);
876 *ra
= NIOS2_RA_REGNUM
;
879 *ra
= NIOS2_EA_REGNUM
;
882 *ra
= NIOS2_BA_REGNUM
;
891 *ra
= GET_IW_F2I16_A (insn
);
893 case MATCH_R2_JMPR_N
:
894 *ra
= GET_IW_F1X1_A (insn
);
898 *ra
= NIOS2_RA_REGNUM
;
901 *ra
= NIOS2_EA_REGNUM
;
904 *ra
= NIOS2_BA_REGNUM
;
912 /* Match and disassemble an indirect call instruction, with a register
913 operand. Returns true on success, and fills in the operand pointer. */
916 nios2_match_callr (uint32_t insn
, const struct nios2_opcode
*op
,
917 unsigned long mach
, int *ra
)
919 int is_r2
= (mach
== bfd_mach_nios2r2
);
921 if (!is_r2
&& op
->match
== MATCH_R1_CALLR
)
923 *ra
= GET_IW_I_A (insn
);
928 else if (op
->match
== MATCH_R2_CALLR
)
930 *ra
= GET_IW_F2I16_A (insn
);
933 else if (op
->match
== MATCH_R2_CALLR_N
)
935 *ra
= GET_IW_F1X1_A (insn
);
941 /* Match and disassemble a break instruction, with an unsigned operand.
942 Returns true on success, and fills in the operand pointer. */
945 nios2_match_break (uint32_t insn
, const struct nios2_opcode
*op
,
946 unsigned long mach
, unsigned int *uimm
)
948 int is_r2
= (mach
== bfd_mach_nios2r2
);
950 if (!is_r2
&& op
->match
== MATCH_R1_BREAK
)
952 *uimm
= GET_IW_R_IMM5 (insn
);
957 else if (op
->match
== MATCH_R2_BREAK
)
959 *uimm
= GET_IW_F3X6L5_IMM5 (insn
);
962 else if (op
->match
== MATCH_R2_BREAK_N
)
964 *uimm
= GET_IW_X2L5_IMM5 (insn
);
970 /* Match and disassemble a trap instruction, with an unsigned operand.
971 Returns true on success, and fills in the operand pointer. */
974 nios2_match_trap (uint32_t insn
, const struct nios2_opcode
*op
,
975 unsigned long mach
, unsigned int *uimm
)
977 int is_r2
= (mach
== bfd_mach_nios2r2
);
979 if (!is_r2
&& op
->match
== MATCH_R1_TRAP
)
981 *uimm
= GET_IW_R_IMM5 (insn
);
986 else if (op
->match
== MATCH_R2_TRAP
)
988 *uimm
= GET_IW_F3X6L5_IMM5 (insn
);
991 else if (op
->match
== MATCH_R2_TRAP_N
)
993 *uimm
= GET_IW_X2L5_IMM5 (insn
);
999 /* Helper function to identify when we're in a function epilogue;
1000 that is, the part of the function from the point at which the
1001 stack adjustments are made, to the return or sibcall.
1002 Note that we may have several stack adjustment instructions, and
1003 this function needs to test whether the stack teardown has already
1004 started before current_pc, not whether it has completed. */
1007 nios2_in_epilogue_p (struct gdbarch
*gdbarch
,
1008 CORE_ADDR current_pc
,
1011 unsigned long mach
= gdbarch_bfd_arch_info (gdbarch
)->mach
;
1012 int is_r2
= (mach
== bfd_mach_nios2r2
);
1013 /* Maximum number of possibly-epilogue instructions to check.
1014 Note that this number should not be too large, else we can
1015 potentially end up iterating through unmapped memory. */
1016 int ninsns
, max_insns
= 5;
1018 const struct nios2_opcode
*op
= NULL
;
1023 enum branch_condition cond
;
1026 /* There has to be a previous instruction in the function. */
1027 if (current_pc
<= start_pc
)
1030 /* Find the previous instruction before current_pc. For R2, it might
1031 be either a 16-bit or 32-bit instruction; the only way to know for
1032 sure is to scan through from the beginning of the function,
1033 disassembling as we go. */
1035 for (pc
= start_pc
; ; )
1037 op
= nios2_fetch_insn (gdbarch
, pc
, &insn
);
1040 if (pc
+ op
->size
< current_pc
)
1044 /* We can skip over insns to a forward branch target. Since
1045 the branch offset is relative to the next instruction,
1046 it's correct to do this after incrementing the pc above. */
1047 if (nios2_match_branch (insn
, op
, mach
, &ra
, &rb
, &imm
, &cond
)
1049 && pc
+ imm
< current_pc
)
1052 /* Otherwise just go back to the previous 32-bit insn. */
1054 pc
= current_pc
- NIOS2_OPCODE_SIZE
;
1056 /* Beginning with the previous instruction we just located, check whether
1057 we are in a sequence of at least one stack adjustment instruction.
1058 Possible instructions here include:
1064 LDWM {reglist}, (sp)++, wb */
1065 for (ninsns
= 0; ninsns
< max_insns
; ninsns
++)
1069 /* Fetch the insn at pc. */
1070 op
= nios2_fetch_insn (gdbarch
, pc
, &insn
);
1075 /* Was it a stack adjustment? */
1076 if (nios2_match_addi (insn
, op
, mach
, &ra
, &rb
, &imm
))
1077 ok
= (rb
== NIOS2_SP_REGNUM
);
1078 else if (nios2_match_add (insn
, op
, mach
, &ra
, &rb
, &rc
))
1079 ok
= (rc
== NIOS2_SP_REGNUM
);
1080 else if (nios2_match_ldw (insn
, op
, mach
, &ra
, &rb
, &imm
))
1081 ok
= (rb
== NIOS2_SP_REGNUM
);
1082 else if (nios2_match_ldwm (insn
, op
, mach
, &uimm
, &ra
,
1083 &imm
, &wb
, &ret
, &id
))
1084 ok
= (ra
== NIOS2_SP_REGNUM
&& wb
&& id
);
1089 /* No stack adjustments found. */
1093 /* We found more stack adjustments than we expect GCC to be generating.
1094 Since it looks like a stack unwind might be in progress tell GDB to
1095 treat it as such. */
1096 if (ninsns
== max_insns
)
1099 /* The next instruction following the stack adjustments must be a
1100 return, jump, or unconditional branch, or a CDX pop.n or ldwm
1101 that does an implicit return. */
1102 if (nios2_match_jmpr (insn
, op
, mach
, &ra
)
1103 || nios2_match_jmpi (insn
, op
, mach
, &uimm
)
1104 || (nios2_match_ldwm (insn
, op
, mach
, &uimm
, &ra
, &imm
, &wb
, &id
, &ret
)
1106 || (nios2_match_branch (insn
, op
, mach
, &ra
, &rb
, &imm
, &cond
)
1107 && cond
== branch_none
))
1113 /* Implement the stack_frame_destroyed_p gdbarch method. */
1116 nios2_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1118 CORE_ADDR func_addr
;
1120 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1121 return nios2_in_epilogue_p (gdbarch
, pc
, func_addr
);
1126 /* Do prologue analysis, returning the PC of the first instruction
1127 after the function prologue. Assumes CACHE has already been
1128 initialized. THIS_FRAME can be null, in which case we are only
1129 interested in skipping the prologue. Otherwise CACHE is filled in
1130 from the frame information.
1132 The prologue may consist of the following parts:
1133 1) Profiling instrumentation. For non-PIC code it looks like:
1138 2) A stack adjustment and save of R4-R7 for varargs functions.
1139 For R2 CDX this is typically handled with a STWM, otherwise
1140 this is typically merged with item 3.
1142 3) A stack adjustment and save of the callee-saved registers.
1143 For R2 CDX these are typically handled with a PUSH.N or STWM,
1144 otherwise as an explicit SP decrement and individual register
1147 There may also be a stack switch here in an exception handler
1148 in place of a stack adjustment. It looks like:
1149 movhi rx, %hiadj(newstack)
1150 addhi rx, rx, %lo(newstack)
1151 stw sp, constant(rx)
1154 4) A frame pointer save, which can be either a MOV or ADDI.
1156 5) A further stack pointer adjustment. This is normally included
1157 adjustment in step 3 unless the total adjustment is too large
1158 to be done in one step.
1160 7) A stack overflow check, which can take either of these forms:
1164 bltu sp, rx, .Lstack_overflow
1169 Older versions of GCC emitted "break 3" instead of "trap 3" here,
1170 so we check for both cases.
1172 Older GCC versions emitted stack overflow checks after the SP
1173 adjustments in both steps 3 and 4. Starting with GCC 6, there is
1174 at most one overflow check, which is placed before the first
1175 stack adjustment for R2 CDX and after the first stack adjustment
1178 The prologue instructions may be combined or interleaved with other
1181 To cope with all this variability we decode all the instructions
1182 from the start of the prologue until we hit an instruction that
1183 cannot possibly be a prologue instruction, such as a branch, call,
1184 return, or epilogue instruction. The prologue is considered to end
1185 at the last instruction that can definitely be considered a
1186 prologue instruction. */
1189 nios2_analyze_prologue (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
,
1190 const CORE_ADDR current_pc
,
1191 struct nios2_unwind_cache
*cache
,
1192 struct frame_info
*this_frame
)
1194 /* Maximum number of possibly-prologue instructions to check.
1195 Note that this number should not be too large, else we can
1196 potentially end up iterating through unmapped memory. */
1197 int ninsns
, max_insns
= 50;
1199 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1200 unsigned long mach
= gdbarch_bfd_arch_info (gdbarch
)->mach
;
1201 int is_r2
= (mach
== bfd_mach_nios2r2
);
1203 /* Does the frame set up the FP register? */
1206 struct reg_value
*value
= cache
->reg_value
;
1207 struct reg_value temp_value
[NIOS2_NUM_REGS
];
1211 /* Save the starting PC so we can correct the pc after running
1212 through the prolog, using symbol info. */
1213 CORE_ADDR pc
= start_pc
;
1215 /* Is this an exception handler? */
1216 int exception_handler
= 0;
1218 /* What was the original value of SP (or fake original value for
1219 functions which switch stacks? */
1220 CORE_ADDR frame_high
;
1222 /* The last definitely-prologue instruction seen. */
1223 CORE_ADDR prologue_end
;
1225 /* Is this the innermost function? */
1226 int innermost
= (this_frame
? (frame_relative_level (this_frame
) == 0) : 1);
1229 fprintf_unfiltered (gdb_stdlog
,
1230 "{ nios2_analyze_prologue start=%s, current=%s ",
1231 paddress (gdbarch
, start_pc
),
1232 paddress (gdbarch
, current_pc
));
1234 /* Set up the default values of the registers. */
1235 nios2_setup_default (cache
);
1237 /* Find the prologue instructions. */
1238 prologue_end
= start_pc
;
1239 for (ninsns
= 0; ninsns
< max_insns
; ninsns
++)
1241 /* Present instruction. */
1243 const struct nios2_opcode
*op
;
1244 int ra
, rb
, rc
, imm
;
1246 unsigned int reglist
;
1248 enum branch_condition cond
;
1250 if (pc
== current_pc
)
1252 /* When we reach the current PC we must save the current
1253 register state (for the backtrace) but keep analysing
1254 because there might be more to find out (eg. is this an
1255 exception handler). */
1256 memcpy (temp_value
, value
, sizeof (temp_value
));
1259 fprintf_unfiltered (gdb_stdlog
, "*");
1262 op
= nios2_fetch_insn (gdbarch
, pc
, &insn
);
1264 /* Unknown opcode? Stop scanning. */
1272 fprintf_unfiltered (gdb_stdlog
, "[%04X]", insn
& 0xffff);
1274 fprintf_unfiltered (gdb_stdlog
, "[%08X]", insn
);
1277 /* The following instructions can appear in the prologue. */
1279 if (nios2_match_add (insn
, op
, mach
, &ra
, &rb
, &rc
))
1281 /* ADD rc, ra, rb (also used for MOV) */
1282 if (rc
== NIOS2_SP_REGNUM
1284 && value
[ra
].reg
== cache
->reg_saved
[NIOS2_SP_REGNUM
].basereg
)
1286 /* If the previous value of SP is available somewhere
1287 near the new stack pointer value then this is a
1290 /* If any registers were saved on the stack before then
1291 we can't backtrace into them now. */
1292 for (i
= 0 ; i
< NIOS2_NUM_REGS
; i
++)
1294 if (cache
->reg_saved
[i
].basereg
== NIOS2_SP_REGNUM
)
1295 cache
->reg_saved
[i
].basereg
= -1;
1296 if (value
[i
].reg
== NIOS2_SP_REGNUM
)
1300 /* Create a fake "high water mark" 4 bytes above where SP
1301 was stored and fake up the registers to be consistent
1303 value
[NIOS2_SP_REGNUM
].reg
= NIOS2_SP_REGNUM
;
1304 value
[NIOS2_SP_REGNUM
].offset
1306 - cache
->reg_saved
[NIOS2_SP_REGNUM
].addr
1308 cache
->reg_saved
[NIOS2_SP_REGNUM
].basereg
= NIOS2_SP_REGNUM
;
1309 cache
->reg_saved
[NIOS2_SP_REGNUM
].addr
= -4;
1312 else if (rc
== NIOS2_SP_REGNUM
&& ra
== NIOS2_FP_REGNUM
)
1313 /* This is setting SP from FP. This only happens in the
1314 function epilogue. */
1319 if (value
[rb
].reg
== 0)
1320 value
[rc
].reg
= value
[ra
].reg
;
1321 else if (value
[ra
].reg
== 0)
1322 value
[rc
].reg
= value
[rb
].reg
;
1325 value
[rc
].offset
= value
[ra
].offset
+ value
[rb
].offset
;
1328 /* The add/move is only considered a prologue instruction
1329 if the destination is SP or FP. */
1330 if (rc
== NIOS2_SP_REGNUM
|| rc
== NIOS2_FP_REGNUM
)
1334 else if (nios2_match_sub (insn
, op
, mach
, &ra
, &rb
, &rc
))
1336 /* SUB rc, ra, rb */
1337 if (rc
== NIOS2_SP_REGNUM
&& rb
== NIOS2_SP_REGNUM
1338 && value
[rc
].reg
!= 0)
1339 /* If we are decrementing the SP by a non-constant amount,
1340 this is alloca, not part of the prologue. */
1344 if (value
[rb
].reg
== 0)
1345 value
[rc
].reg
= value
[ra
].reg
;
1348 value
[rc
].offset
= value
[ra
].offset
- value
[rb
].offset
;
1352 else if (nios2_match_addi (insn
, op
, mach
, &ra
, &rb
, &imm
))
1354 /* ADDI rb, ra, imm */
1356 /* A positive stack adjustment has to be part of the epilogue. */
1357 if (rb
== NIOS2_SP_REGNUM
1358 && (imm
> 0 || value
[ra
].reg
!= NIOS2_SP_REGNUM
))
1361 /* Likewise restoring SP from FP. */
1362 else if (rb
== NIOS2_SP_REGNUM
&& ra
== NIOS2_FP_REGNUM
)
1367 value
[rb
].reg
= value
[ra
].reg
;
1368 value
[rb
].offset
= value
[ra
].offset
+ imm
;
1371 /* The add is only considered a prologue instruction
1372 if the destination is SP or FP. */
1373 if (rb
== NIOS2_SP_REGNUM
|| rb
== NIOS2_FP_REGNUM
)
1377 else if (nios2_match_orhi (insn
, op
, mach
, &ra
, &rb
, &uimm
))
1379 /* ORHI rb, ra, uimm (also used for MOVHI) */
1382 value
[rb
].reg
= (value
[ra
].reg
== 0) ? 0 : -1;
1383 value
[rb
].offset
= value
[ra
].offset
| (uimm
<< 16);
1387 else if (nios2_match_stw (insn
, op
, mach
, &ra
, &rb
, &imm
))
1389 /* STW rb, imm(ra) */
1391 /* Are we storing the original value of a register to the stack?
1392 For exception handlers the value of EA-4 (return
1393 address from interrupts etc) is sometimes stored. */
1394 int orig
= value
[rb
].reg
;
1396 && (value
[rb
].offset
== 0
1397 || (orig
== NIOS2_EA_REGNUM
&& value
[rb
].offset
== -4))
1398 && value
[ra
].reg
== NIOS2_SP_REGNUM
)
1400 if (pc
< current_pc
)
1402 /* Save off callee saved registers. */
1403 cache
->reg_saved
[orig
].basereg
= value
[ra
].reg
;
1404 cache
->reg_saved
[orig
].addr
= value
[ra
].offset
+ imm
;
1409 if (orig
== NIOS2_EA_REGNUM
|| orig
== NIOS2_ESTATUS_REGNUM
)
1410 exception_handler
= 1;
1413 /* Non-stack memory writes cannot appear in the prologue. */
1417 else if (nios2_match_stwm (insn
, op
, mach
,
1418 ®list
, &ra
, &imm
, &wb
, &id
))
1420 /* PUSH.N {reglist}, adjust
1422 STWM {reglist}, --(SP)[, writeback] */
1426 if (ra
!= NIOS2_SP_REGNUM
|| id
!= 0)
1427 /* This is a non-stack-push memory write and cannot be
1428 part of the prologue. */
1431 for (i
= 31; i
>= 0; i
--)
1432 if (reglist
& (1 << i
))
1434 int orig
= value
[i
].reg
;
1437 if (orig
> 0 && value
[i
].offset
== 0 && pc
< current_pc
)
1439 cache
->reg_saved
[orig
].basereg
1440 = value
[NIOS2_SP_REGNUM
].reg
;
1441 cache
->reg_saved
[orig
].addr
1442 = value
[NIOS2_SP_REGNUM
].offset
- off
;
1447 value
[NIOS2_SP_REGNUM
].offset
-= off
;
1448 value
[NIOS2_SP_REGNUM
].offset
-= imm
;
1453 else if (nios2_match_rdctl (insn
, op
, mach
, &ra
, &rc
))
1456 This can appear in exception handlers in combination with
1457 a subsequent save to the stack frame. */
1460 value
[rc
].reg
= NIOS2_STATUS_REGNUM
+ ra
;
1461 value
[rc
].offset
= 0;
1465 else if (nios2_match_calli (insn
, op
, mach
, &uimm
))
1467 if (value
[8].reg
== NIOS2_RA_REGNUM
1468 && value
[8].offset
== 0
1469 && value
[NIOS2_SP_REGNUM
].reg
== NIOS2_SP_REGNUM
1470 && value
[NIOS2_SP_REGNUM
].offset
== 0)
1472 /* A CALL instruction. This is treated as a call to mcount
1473 if ra has been stored into r8 beforehand and if it's
1474 before the stack adjust.
1475 Note mcount corrupts r2-r3, r9-r15 & ra. */
1476 for (i
= 2 ; i
<= 3 ; i
++)
1478 for (i
= 9 ; i
<= 15 ; i
++)
1480 value
[NIOS2_RA_REGNUM
].reg
= -1;
1485 /* Other calls are not part of the prologue. */
1490 else if (nios2_match_branch (insn
, op
, mach
, &ra
, &rb
, &imm
, &cond
))
1492 /* Branches not involving a stack overflow check aren't part of
1494 if (ra
!= NIOS2_SP_REGNUM
)
1496 else if (cond
== branch_geu
)
1500 This instruction sequence is used in stack checking;
1501 we can ignore it. */
1502 unsigned int next_insn
;
1503 const struct nios2_opcode
*next_op
1504 = nios2_fetch_insn (gdbarch
, pc
, &next_insn
);
1506 && (nios2_match_trap (next_insn
, op
, mach
, &uimm
)
1507 || nios2_match_break (next_insn
, op
, mach
, &uimm
)))
1508 pc
+= next_op
->size
;
1512 else if (cond
== branch_ltu
)
1514 /* BLTU sp, rx, .Lstackoverflow
1515 If the location branched to holds a TRAP or BREAK
1516 instruction then this is also stack overflow detection. */
1517 unsigned int next_insn
;
1518 const struct nios2_opcode
*next_op
1519 = nios2_fetch_insn (gdbarch
, pc
+ imm
, &next_insn
);
1521 && (nios2_match_trap (next_insn
, op
, mach
, &uimm
)
1522 || nios2_match_break (next_insn
, op
, mach
, &uimm
)))
1531 /* All other calls, jumps, returns, TRAPs, or BREAKs terminate
1533 else if (nios2_match_callr (insn
, op
, mach
, &ra
)
1534 || nios2_match_jmpr (insn
, op
, mach
, &ra
)
1535 || nios2_match_jmpi (insn
, op
, mach
, &uimm
)
1536 || (nios2_match_ldwm (insn
, op
, mach
, ®list
, &ra
,
1537 &imm
, &wb
, &id
, &ret
)
1539 || nios2_match_trap (insn
, op
, mach
, &uimm
)
1540 || nios2_match_break (insn
, op
, mach
, &uimm
))
1544 /* If THIS_FRAME is NULL, we are being called from skip_prologue
1545 and are only interested in the PROLOGUE_END value, so just
1546 return that now and skip over the cache updates, which depend
1547 on having frame information. */
1548 if (this_frame
== NULL
)
1549 return prologue_end
;
1551 /* If we are in the function epilogue and have already popped
1552 registers off the stack in preparation for returning, then we
1553 want to go back to the original register values. */
1554 if (innermost
&& nios2_in_epilogue_p (gdbarch
, current_pc
, start_pc
))
1555 nios2_setup_default (cache
);
1557 /* Exception handlers use a different return address register. */
1558 if (exception_handler
)
1559 cache
->return_regnum
= NIOS2_EA_REGNUM
;
1562 fprintf_unfiltered (gdb_stdlog
, "\n-> retreg=%d, ", cache
->return_regnum
);
1564 if (cache
->reg_value
[NIOS2_FP_REGNUM
].reg
== NIOS2_SP_REGNUM
)
1565 /* If the FP now holds an offset from the CFA then this is a
1566 normal frame which uses the frame pointer. */
1567 base_reg
= NIOS2_FP_REGNUM
;
1568 else if (cache
->reg_value
[NIOS2_SP_REGNUM
].reg
== NIOS2_SP_REGNUM
)
1569 /* FP doesn't hold an offset from the CFA. If SP still holds an
1570 offset from the CFA then we might be in a function which omits
1571 the frame pointer, or we might be partway through the prologue.
1572 In both cases we can find the CFA using SP. */
1573 base_reg
= NIOS2_SP_REGNUM
;
1576 /* Somehow the stack pointer has been corrupted.
1579 fprintf_unfiltered (gdb_stdlog
, "<can't reach cfa> }\n");
1583 if (cache
->reg_value
[base_reg
].offset
== 0
1584 || cache
->reg_saved
[NIOS2_RA_REGNUM
].basereg
!= NIOS2_SP_REGNUM
1585 || cache
->reg_saved
[cache
->return_regnum
].basereg
!= NIOS2_SP_REGNUM
)
1587 /* If the frame didn't adjust the stack, didn't save RA or
1588 didn't save EA in an exception handler then it must either
1589 be a leaf function (doesn't call any other functions) or it
1590 can't return. If it has called another function then it
1591 can't be a leaf, so set base == 0 to indicate that we can't
1592 backtrace past it. */
1596 /* If it isn't the innermost function then it can't be a
1597 leaf, unless it was interrupted. Check whether RA for
1598 this frame is the same as PC. If so then it probably
1599 wasn't interrupted. */
1601 = get_frame_register_unsigned (this_frame
, NIOS2_RA_REGNUM
);
1603 if (ra
== current_pc
)
1608 "<noreturn ADJUST %s, r31@r%d+?>, r%d@r%d+?> }\n",
1609 paddress (gdbarch
, cache
->reg_value
[base_reg
].offset
),
1610 cache
->reg_saved
[NIOS2_RA_REGNUM
].basereg
,
1611 cache
->return_regnum
,
1612 cache
->reg_saved
[cache
->return_regnum
].basereg
);
1618 /* Get the value of whichever register we are using for the
1620 cache
->base
= get_frame_register_unsigned (this_frame
, base_reg
);
1622 /* What was the value of SP at the start of this function (or just
1623 after the stack switch). */
1624 frame_high
= cache
->base
- cache
->reg_value
[base_reg
].offset
;
1626 /* Adjust all the saved registers such that they contain addresses
1627 instead of offsets. */
1628 for (i
= 0; i
< NIOS2_NUM_REGS
; i
++)
1629 if (cache
->reg_saved
[i
].basereg
== NIOS2_SP_REGNUM
)
1631 cache
->reg_saved
[i
].basereg
= NIOS2_Z_REGNUM
;
1632 cache
->reg_saved
[i
].addr
+= frame_high
;
1635 for (i
= 0; i
< NIOS2_NUM_REGS
; i
++)
1636 if (cache
->reg_saved
[i
].basereg
== NIOS2_GP_REGNUM
)
1638 CORE_ADDR gp
= get_frame_register_unsigned (this_frame
,
1641 for ( ; i
< NIOS2_NUM_REGS
; i
++)
1642 if (cache
->reg_saved
[i
].basereg
== NIOS2_GP_REGNUM
)
1644 cache
->reg_saved
[i
].basereg
= NIOS2_Z_REGNUM
;
1645 cache
->reg_saved
[i
].addr
+= gp
;
1649 /* Work out what the value of SP was on the first instruction of
1650 this function. If we didn't switch stacks then this can be
1651 trivially computed from the base address. */
1652 if (cache
->reg_saved
[NIOS2_SP_REGNUM
].basereg
== NIOS2_Z_REGNUM
)
1654 = read_memory_unsigned_integer (cache
->reg_saved
[NIOS2_SP_REGNUM
].addr
,
1657 cache
->cfa
= frame_high
;
1659 /* Exception handlers restore ESTATUS into STATUS. */
1660 if (exception_handler
)
1662 cache
->reg_saved
[NIOS2_STATUS_REGNUM
]
1663 = cache
->reg_saved
[NIOS2_ESTATUS_REGNUM
];
1664 cache
->reg_saved
[NIOS2_ESTATUS_REGNUM
].basereg
= -1;
1668 fprintf_unfiltered (gdb_stdlog
, "cfa=%s }\n",
1669 paddress (gdbarch
, cache
->cfa
));
1671 return prologue_end
;
1674 /* Implement the skip_prologue gdbarch hook. */
1677 nios2_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1679 CORE_ADDR func_addr
;
1681 struct nios2_unwind_cache cache
;
1683 /* See if we can determine the end of the prologue via the symbol
1684 table. If so, then return either PC, or the PC after the
1685 prologue, whichever is greater. */
1686 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1688 CORE_ADDR post_prologue_pc
1689 = skip_prologue_using_sal (gdbarch
, func_addr
);
1691 if (post_prologue_pc
!= 0)
1692 return max (start_pc
, post_prologue_pc
);
1695 /* Prologue analysis does the rest.... */
1696 nios2_init_cache (&cache
, start_pc
);
1697 return nios2_analyze_prologue (gdbarch
, start_pc
, start_pc
, &cache
, NULL
);
1700 /* Implement the breakpoint_from_pc gdbarch hook.
1702 The Nios II ABI for Linux says: "Userspace programs should not use
1703 the break instruction and userspace debuggers should not insert
1704 one." and "Userspace breakpoints are accomplished using the trap
1705 instruction with immediate operand 31 (all ones)."
1707 So, we use "trap 31" consistently as the breakpoint on bare-metal
1708 as well as Linux targets. */
1710 static const gdb_byte
*
1711 nios2_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
1714 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
1715 unsigned long mach
= gdbarch_bfd_arch_info (gdbarch
)->mach
;
1717 if (mach
== bfd_mach_nios2r2
)
1719 /* R2 trap encoding:
1720 ((0x2d << 26) | (0x1f << 21) | (0x1d << 16) | (0x20 << 0))
1722 CDX trap.n encoding:
1723 ((0xd << 12) | (0x1f << 6) | (0x9 << 0))
1725 Note that code is always little-endian on R2. */
1726 static const gdb_byte r2_breakpoint_le
[] = {0x20, 0x00, 0xfd, 0xb7};
1727 static const gdb_byte cdx_breakpoint_le
[] = {0xc9, 0xd7};
1729 const struct nios2_opcode
*op
1730 = nios2_fetch_insn (gdbarch
, *bp_addr
, &insn
);
1732 if (op
&& op
->size
== NIOS2_CDX_OPCODE_SIZE
)
1734 *bp_size
= NIOS2_CDX_OPCODE_SIZE
;
1735 return cdx_breakpoint_le
;
1739 *bp_size
= NIOS2_OPCODE_SIZE
;
1740 return r2_breakpoint_le
;
1745 /* R1 trap encoding:
1746 ((0x1d << 17) | (0x2d << 11) | (0x1f << 6) | (0x3a << 0))
1748 static const gdb_byte r1_breakpoint_le
[] = {0xfa, 0x6f, 0x3b, 0x0};
1749 static const gdb_byte r1_breakpoint_be
[] = {0x0, 0x3b, 0x6f, 0xfa};
1750 *bp_size
= NIOS2_OPCODE_SIZE
;
1751 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
1752 return r1_breakpoint_be
;
1754 return r1_breakpoint_le
;
1758 /* Implement the print_insn gdbarch method. */
1761 nios2_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
1763 if (info
->endian
== BFD_ENDIAN_BIG
)
1764 return print_insn_big_nios2 (memaddr
, info
);
1766 return print_insn_little_nios2 (memaddr
, info
);
1770 /* Implement the frame_align gdbarch method. */
1773 nios2_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1775 return align_down (addr
, 4);
1779 /* Implement the return_value gdbarch method. */
1781 static enum return_value_convention
1782 nios2_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1783 struct type
*type
, struct regcache
*regcache
,
1784 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1786 if (TYPE_LENGTH (type
) > 8)
1787 return RETURN_VALUE_STRUCT_CONVENTION
;
1790 nios2_extract_return_value (gdbarch
, type
, regcache
, readbuf
);
1792 nios2_store_return_value (gdbarch
, type
, regcache
, writebuf
);
1794 return RETURN_VALUE_REGISTER_CONVENTION
;
1797 /* Implement the dummy_id gdbarch method. */
1799 static struct frame_id
1800 nios2_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1802 return frame_id_build
1803 (get_frame_register_unsigned (this_frame
, NIOS2_SP_REGNUM
),
1804 get_frame_pc (this_frame
));
1807 /* Implement the push_dummy_call gdbarch method. */
1810 nios2_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1811 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1812 int nargs
, struct value
**args
, CORE_ADDR sp
,
1813 int struct_return
, CORE_ADDR struct_addr
)
1819 int stack_offset
= 0;
1820 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1821 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1823 /* Set the return address register to point to the entry point of
1824 the program, where a breakpoint lies in wait. */
1825 regcache_cooked_write_signed (regcache
, NIOS2_RA_REGNUM
, bp_addr
);
1827 /* Now make space on the stack for the args. */
1828 for (argnum
= 0; argnum
< nargs
; argnum
++)
1829 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), 4);
1832 /* Initialize the register pointer. */
1833 argreg
= NIOS2_FIRST_ARGREG
;
1835 /* The struct_return pointer occupies the first parameter-passing
1838 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
1840 /* Now load as many as possible of the first arguments into
1841 registers, and push the rest onto the stack. Loop through args
1842 from first to last. */
1843 for (argnum
= 0; argnum
< nargs
; argnum
++)
1845 const gdb_byte
*val
;
1846 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
1847 struct value
*arg
= args
[argnum
];
1848 struct type
*arg_type
= check_typedef (value_type (arg
));
1849 int len
= TYPE_LENGTH (arg_type
);
1850 enum type_code typecode
= TYPE_CODE (arg_type
);
1852 val
= value_contents (arg
);
1854 /* Copy the argument to general registers or the stack in
1855 register-sized pieces. Large arguments are split between
1856 registers and stack. */
1859 int partial_len
= (len
< 4 ? len
: 4);
1861 if (argreg
<= NIOS2_LAST_ARGREG
)
1863 /* The argument is being passed in a register. */
1864 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
,
1867 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1872 /* The argument is being passed on the stack. */
1873 CORE_ADDR addr
= sp
+ stack_offset
;
1875 write_memory (addr
, val
, partial_len
);
1876 stack_offset
+= align_up (partial_len
, 4);
1884 regcache_cooked_write_signed (regcache
, NIOS2_SP_REGNUM
, sp
);
1886 /* Return adjusted stack pointer. */
1890 /* Implement the unwind_pc gdbarch method. */
1893 nios2_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1897 frame_unwind_register (next_frame
, NIOS2_PC_REGNUM
, buf
);
1898 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1901 /* Implement the unwind_sp gdbarch method. */
1904 nios2_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1906 return frame_unwind_register_unsigned (this_frame
, NIOS2_SP_REGNUM
);
1909 /* Use prologue analysis to fill in the register cache
1910 *THIS_PROLOGUE_CACHE for THIS_FRAME. This function initializes
1911 *THIS_PROLOGUE_CACHE first. */
1913 static struct nios2_unwind_cache
*
1914 nios2_frame_unwind_cache (struct frame_info
*this_frame
,
1915 void **this_prologue_cache
)
1917 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1918 CORE_ADDR current_pc
;
1919 struct nios2_unwind_cache
*cache
;
1922 if (*this_prologue_cache
)
1923 return *this_prologue_cache
;
1925 cache
= FRAME_OBSTACK_ZALLOC (struct nios2_unwind_cache
);
1926 *this_prologue_cache
= cache
;
1928 /* Zero all fields. */
1929 nios2_init_cache (cache
, get_frame_func (this_frame
));
1931 /* Prologue analysis does the rest... */
1932 current_pc
= get_frame_pc (this_frame
);
1934 nios2_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, this_frame
);
1939 /* Implement the this_id function for the normal unwinder. */
1942 nios2_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1943 struct frame_id
*this_id
)
1945 struct nios2_unwind_cache
*cache
=
1946 nios2_frame_unwind_cache (this_frame
, this_cache
);
1948 /* This marks the outermost frame. */
1949 if (cache
->base
== 0)
1952 *this_id
= frame_id_build (cache
->cfa
, cache
->pc
);
1955 /* Implement the prev_register function for the normal unwinder. */
1957 static struct value
*
1958 nios2_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
1961 struct nios2_unwind_cache
*cache
=
1962 nios2_frame_unwind_cache (this_frame
, this_cache
);
1964 gdb_assert (regnum
>= 0 && regnum
< NIOS2_NUM_REGS
);
1966 /* The PC of the previous frame is stored in the RA register of
1967 the current frame. Frob regnum so that we pull the value from
1968 the correct place. */
1969 if (regnum
== NIOS2_PC_REGNUM
)
1970 regnum
= cache
->return_regnum
;
1972 if (regnum
== NIOS2_SP_REGNUM
&& cache
->cfa
)
1973 return frame_unwind_got_constant (this_frame
, regnum
, cache
->cfa
);
1975 /* If we've worked out where a register is stored then load it from
1977 if (cache
->reg_saved
[regnum
].basereg
== NIOS2_Z_REGNUM
)
1978 return frame_unwind_got_memory (this_frame
, regnum
,
1979 cache
->reg_saved
[regnum
].addr
);
1981 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1984 /* Implement the this_base, this_locals, and this_args hooks
1985 for the normal unwinder. */
1988 nios2_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1990 struct nios2_unwind_cache
*info
1991 = nios2_frame_unwind_cache (this_frame
, this_cache
);
1996 /* Data structures for the normal prologue-analysis-based
1999 static const struct frame_unwind nios2_frame_unwind
=
2002 default_frame_unwind_stop_reason
,
2003 nios2_frame_this_id
,
2004 nios2_frame_prev_register
,
2006 default_frame_sniffer
2009 static const struct frame_base nios2_frame_base
=
2011 &nios2_frame_unwind
,
2012 nios2_frame_base_address
,
2013 nios2_frame_base_address
,
2014 nios2_frame_base_address
2017 /* Fill in the register cache *THIS_CACHE for THIS_FRAME for use
2018 in the stub unwinder. */
2020 static struct trad_frame_cache
*
2021 nios2_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2024 CORE_ADDR start_addr
;
2025 CORE_ADDR stack_addr
;
2026 struct trad_frame_cache
*this_trad_cache
;
2027 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2028 int num_regs
= gdbarch_num_regs (gdbarch
);
2030 if (*this_cache
!= NULL
)
2032 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2033 *this_cache
= this_trad_cache
;
2035 /* The return address is in the link register. */
2036 trad_frame_set_reg_realreg (this_trad_cache
,
2037 gdbarch_pc_regnum (gdbarch
),
2040 /* Frame ID, since it's a frameless / stackless function, no stack
2041 space is allocated and SP on entry is the current SP. */
2042 pc
= get_frame_pc (this_frame
);
2043 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2044 stack_addr
= get_frame_register_unsigned (this_frame
, NIOS2_SP_REGNUM
);
2045 trad_frame_set_id (this_trad_cache
, frame_id_build (start_addr
, stack_addr
));
2046 /* Assume that the frame's base is the same as the stack pointer. */
2047 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2049 return this_trad_cache
;
2052 /* Implement the this_id function for the stub unwinder. */
2055 nios2_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2056 struct frame_id
*this_id
)
2058 struct trad_frame_cache
*this_trad_cache
2059 = nios2_stub_frame_cache (this_frame
, this_cache
);
2061 trad_frame_get_id (this_trad_cache
, this_id
);
2064 /* Implement the prev_register function for the stub unwinder. */
2066 static struct value
*
2067 nios2_stub_frame_prev_register (struct frame_info
*this_frame
,
2068 void **this_cache
, int regnum
)
2070 struct trad_frame_cache
*this_trad_cache
2071 = nios2_stub_frame_cache (this_frame
, this_cache
);
2073 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
2076 /* Implement the sniffer function for the stub unwinder.
2077 This unwinder is used for cases where the normal
2078 prologue-analysis-based unwinder can't work,
2079 such as PLT stubs. */
2082 nios2_stub_frame_sniffer (const struct frame_unwind
*self
,
2083 struct frame_info
*this_frame
, void **cache
)
2086 struct obj_section
*s
;
2087 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2089 /* Use the stub unwinder for unreadable code. */
2090 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
2093 if (in_plt_section (pc
))
2099 /* Define the data structures for the stub unwinder. */
2101 static const struct frame_unwind nios2_stub_frame_unwind
=
2104 default_frame_unwind_stop_reason
,
2105 nios2_stub_frame_this_id
,
2106 nios2_stub_frame_prev_register
,
2108 nios2_stub_frame_sniffer
2113 /* Determine where to set a single step breakpoint while considering
2114 branch prediction. */
2117 nios2_get_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
2119 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2120 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2121 unsigned long mach
= gdbarch_bfd_arch_info (gdbarch
)->mach
;
2123 const struct nios2_opcode
*op
= nios2_fetch_insn (gdbarch
, pc
, &insn
);
2129 enum branch_condition cond
;
2131 /* Do something stupid if we can't disassemble the insn at pc. */
2133 return pc
+ NIOS2_OPCODE_SIZE
;
2135 if (nios2_match_branch (insn
, op
, mach
, &ra
, &rb
, &imm
, &cond
))
2137 int ras
= get_frame_register_signed (frame
, ra
);
2138 int rbs
= get_frame_register_signed (frame
, rb
);
2139 unsigned int rau
= get_frame_register_unsigned (frame
, ra
);
2140 unsigned int rbu
= get_frame_register_unsigned (frame
, rb
);
2177 else if (nios2_match_jmpi (insn
, op
, mach
, &uimm
)
2178 || nios2_match_calli (insn
, op
, mach
, &uimm
))
2179 pc
= (pc
& 0xf0000000) | uimm
;
2181 else if (nios2_match_jmpr (insn
, op
, mach
, &ra
)
2182 || nios2_match_callr (insn
, op
, mach
, &ra
))
2183 pc
= get_frame_register_unsigned (frame
, ra
);
2185 else if (nios2_match_ldwm (insn
, op
, mach
, &uimm
, &ra
, &imm
, &wb
, &id
, &ret
)
2188 /* If ra is in the reglist, we have to use the value saved in the
2189 stack frame rather than the current value. */
2190 if (uimm
& (1 << NIOS2_RA_REGNUM
))
2191 pc
= nios2_unwind_pc (gdbarch
, frame
);
2193 pc
= get_frame_register_unsigned (frame
, NIOS2_RA_REGNUM
);
2196 else if (nios2_match_trap (insn
, op
, mach
, &uimm
) && uimm
== 0)
2198 if (tdep
->syscall_next_pc
!= NULL
)
2199 return tdep
->syscall_next_pc (frame
, op
);
2208 /* Implement the software_single_step gdbarch method. */
2211 nios2_software_single_step (struct frame_info
*frame
)
2213 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2214 struct address_space
*aspace
= get_frame_address_space (frame
);
2215 CORE_ADDR next_pc
= nios2_get_next_pc (frame
, get_frame_pc (frame
));
2217 insert_single_step_breakpoint (gdbarch
, aspace
, next_pc
);
2222 /* Implement the get_longjump_target gdbarch method. */
2225 nios2_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2227 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2229 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2230 CORE_ADDR jb_addr
= get_frame_register_unsigned (frame
, NIOS2_R4_REGNUM
);
2233 if (target_read_memory (jb_addr
+ (tdep
->jb_pc
* 4), buf
, 4))
2236 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2240 /* Initialize the Nios II gdbarch. */
2242 static struct gdbarch
*
2243 nios2_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2245 struct gdbarch
*gdbarch
;
2246 struct gdbarch_tdep
*tdep
;
2247 int register_bytes
, i
;
2248 struct tdesc_arch_data
*tdesc_data
= NULL
;
2249 const struct target_desc
*tdesc
= info
.target_desc
;
2251 if (!tdesc_has_registers (tdesc
))
2252 /* Pick a default target description. */
2253 tdesc
= tdesc_nios2
;
2255 /* Check any target description for validity. */
2256 if (tdesc_has_registers (tdesc
))
2258 const struct tdesc_feature
*feature
;
2261 feature
= tdesc_find_feature (tdesc
, "org.gnu.gdb.nios2.cpu");
2262 if (feature
== NULL
)
2265 tdesc_data
= tdesc_data_alloc ();
2269 for (i
= 0; i
< NIOS2_NUM_REGS
; i
++)
2270 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2271 nios2_reg_names
[i
]);
2275 tdesc_data_cleanup (tdesc_data
);
2280 /* Find a candidate among the list of pre-declared architectures. */
2281 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2283 return arches
->gdbarch
;
2285 /* None found, create a new architecture from the information
2287 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
2288 gdbarch
= gdbarch_alloc (&info
, tdep
);
2290 /* longjmp support not enabled by default. */
2293 /* Data type sizes. */
2294 set_gdbarch_ptr_bit (gdbarch
, 32);
2295 set_gdbarch_addr_bit (gdbarch
, 32);
2296 set_gdbarch_short_bit (gdbarch
, 16);
2297 set_gdbarch_int_bit (gdbarch
, 32);
2298 set_gdbarch_long_bit (gdbarch
, 32);
2299 set_gdbarch_long_long_bit (gdbarch
, 64);
2300 set_gdbarch_float_bit (gdbarch
, 32);
2301 set_gdbarch_double_bit (gdbarch
, 64);
2303 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
2304 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
2306 /* The register set. */
2307 set_gdbarch_num_regs (gdbarch
, NIOS2_NUM_REGS
);
2308 set_gdbarch_sp_regnum (gdbarch
, NIOS2_SP_REGNUM
);
2309 set_gdbarch_pc_regnum (gdbarch
, NIOS2_PC_REGNUM
); /* Pseudo register PC */
2311 set_gdbarch_register_name (gdbarch
, nios2_register_name
);
2312 set_gdbarch_register_type (gdbarch
, nios2_register_type
);
2314 /* Provide register mappings for stabs and dwarf2. */
2315 set_gdbarch_stab_reg_to_regnum (gdbarch
, nios2_dwarf_reg_to_regnum
);
2316 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, nios2_dwarf_reg_to_regnum
);
2318 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2320 /* Call dummy code. */
2321 set_gdbarch_frame_align (gdbarch
, nios2_frame_align
);
2323 set_gdbarch_return_value (gdbarch
, nios2_return_value
);
2325 set_gdbarch_skip_prologue (gdbarch
, nios2_skip_prologue
);
2326 set_gdbarch_stack_frame_destroyed_p (gdbarch
, nios2_stack_frame_destroyed_p
);
2327 set_gdbarch_breakpoint_from_pc (gdbarch
, nios2_breakpoint_from_pc
);
2329 set_gdbarch_dummy_id (gdbarch
, nios2_dummy_id
);
2330 set_gdbarch_unwind_pc (gdbarch
, nios2_unwind_pc
);
2331 set_gdbarch_unwind_sp (gdbarch
, nios2_unwind_sp
);
2333 /* The dwarf2 unwinder will normally produce the best results if
2334 the debug information is available, so register it first. */
2335 dwarf2_append_unwinders (gdbarch
);
2336 frame_unwind_append_unwinder (gdbarch
, &nios2_stub_frame_unwind
);
2337 frame_unwind_append_unwinder (gdbarch
, &nios2_frame_unwind
);
2339 /* Single stepping. */
2340 set_gdbarch_software_single_step (gdbarch
, nios2_software_single_step
);
2342 /* Hook in ABI-specific overrides, if they have been registered. */
2343 gdbarch_init_osabi (info
, gdbarch
);
2345 if (tdep
->jb_pc
>= 0)
2346 set_gdbarch_get_longjmp_target (gdbarch
, nios2_get_longjmp_target
);
2348 frame_base_set_default (gdbarch
, &nios2_frame_base
);
2350 set_gdbarch_print_insn (gdbarch
, nios2_print_insn
);
2352 /* Enable inferior call support. */
2353 set_gdbarch_push_dummy_call (gdbarch
, nios2_push_dummy_call
);
2356 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
2361 extern initialize_file_ftype _initialize_nios2_tdep
; /* -Wmissing-prototypes */
2364 _initialize_nios2_tdep (void)
2366 gdbarch_register (bfd_arch_nios2
, nios2_gdbarch_init
, NULL
);
2367 initialize_tdesc_nios2 ();
2369 /* Allow debugging this file's internals. */
2370 add_setshow_boolean_cmd ("nios2", class_maintenance
, &nios2_debug
,
2371 _("Set Nios II debugging."),
2372 _("Show Nios II debugging."),
2373 _("When on, Nios II specific debugging is enabled."),
2376 &setdebuglist
, &showdebuglist
);