gdb/ppc-linux-nat.c

   1 /* PPC GNU/Linux native support.
   2
   3    Copyright 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002,
   4    2003 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330,
  21    Boston, MA 02111-1307, USA.  */
  22
  23 #include "defs.h"
  24 #include "gdb_string.h"
  25 #include "frame.h"
  26 #include "inferior.h"
  27 #include "gdbcore.h"
  28 #include "regcache.h"
  29 #include "gdb_assert.h"
  30
  31 #include <sys/types.h>
  32 #include <sys/param.h>
  33 #include <signal.h>
  34 #include <sys/user.h>
  35 #include <sys/ioctl.h>
  36 #include "gdb_wait.h"
  37 #include <fcntl.h>
  38 #include <sys/procfs.h>
  39 #include <sys/ptrace.h>
  40
  41 /* Prototypes for supply_gregset etc. */
  42 #include "gregset.h"
  43 #include "ppc-tdep.h"
  44
  45 #ifndef PT_READ_U
  46 #define PT_READ_U PTRACE_PEEKUSR
  47 #endif
  48 #ifndef PT_WRITE_U
  49 #define PT_WRITE_U PTRACE_POKEUSR
  50 #endif
  51
  52 /* Default the type of the ptrace transfer to int.  */
  53 #ifndef PTRACE_XFER_TYPE
  54 #define PTRACE_XFER_TYPE int
  55 #endif
  56
  57 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
  58    configure time check.  Some older glibc's (for instance 2.2.1)
  59    don't have a specific powerpc version of ptrace.h, and fall back on
  60    a generic one.  In such cases, sys/ptrace.h defines
  61    PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
  62    ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
  63    PTRACE_SETVRREGS to be.  This also makes a configury check pretty
  64    much useless.  */
  65
  66 /* These definitions should really come from the glibc header files,
  67    but Glibc doesn't know about the vrregs yet.  */
  68 #ifndef PTRACE_GETVRREGS
  69 #define PTRACE_GETVRREGS 18
  70 #define PTRACE_SETVRREGS 19
  71 #endif
  72
  73
  74 /* Similarly for the ptrace requests for getting / setting the SPE
  75    registers (ev0 -- ev31, acc, and spefscr).  See the description of
  76    gdb_evrregset_t for details.  */
  77 #ifndef PTRACE_GETEVRREGS
  78 #define PTRACE_GETEVRREGS 20
  79 #define PTRACE_SETEVRREGS 21
  80 #endif
  81
  82
  83 /* This oddity is because the Linux kernel defines elf_vrregset_t as
  84    an array of 33 16 bytes long elements.  I.e. it leaves out vrsave.
  85    However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
  86    the vrsave as an extra 4 bytes at the end.  I opted for creating a
  87    flat array of chars, so that it is easier to manipulate for gdb.
  88
  89    There are 32 vector registers 16 bytes longs, plus a VSCR register
  90    which is only 4 bytes long, but is fetched as a 16 bytes
  91    quantity. Up to here we have the elf_vrregset_t structure.
  92    Appended to this there is space for the VRSAVE register: 4 bytes.
  93    Even though this vrsave register is not included in the regset
  94    typedef, it is handled by the ptrace requests.
  95
  96    Note that GNU/Linux doesn't support little endian PPC hardware,
  97    therefore the offset at which the real value of the VSCR register
  98    is located will be always 12 bytes.
  99
 100    The layout is like this (where x is the actual value of the vscr reg): */
 101
 102 /* *INDENT-OFF* */
 103 /*
 104    |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
 105    <------->     <-------><-------><->
 106      VR0           VR31     VSCR    VRSAVE
 107 */
 108 /* *INDENT-ON* */
 109
 110 #define SIZEOF_VRREGS 33*16+4
 111
 112 typedef char gdb_vrregset_t[SIZEOF_VRREGS];
 113
 114
 115 /* On PPC processors that support the the Signal Processing Extension
 116    (SPE) APU, the general-purpose registers are 64 bits long.
 117    However, the ordinary Linux kernel PTRACE_PEEKUSR / PTRACE_POKEUSR
 118    / PT_READ_U / PT_WRITE_U ptrace calls only access the lower half of
 119    each register, to allow them to behave the same way they do on
 120    non-SPE systems.  There's a separate pair of calls,
 121    PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that read and write the top
 122    halves of all the general-purpose registers at once, along with
 123    some SPE-specific registers.
 124
 125    GDB itself continues to claim the general-purpose registers are 32
 126    bits long.  It has unnamed raw registers that hold the upper halves
 127    of the gprs, and the the full 64-bit SIMD views of the registers,
 128    'ev0' -- 'ev31', are pseudo-registers that splice the top and
 129    bottom halves together.
 130
 131    This is the structure filled in by PTRACE_GETEVRREGS and written to
 132    the inferior's registers by PTRACE_SETEVRREGS.  */
 133 struct gdb_evrregset_t
 134 {
 135   unsigned long evr[32];
 136   unsigned long long acc;
 137   unsigned long spefscr;
 138 };
 139
 140
 141 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
 142    PTRACE_SETVRREGS requests, for reading and writing the Altivec
 143    registers.  Zero if we've tried one of them and gotten an
 144    error.  */
 145 int have_ptrace_getvrregs = 1;
 146
 147
 148 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
 149    PTRACE_SETEVRREGS requests, for reading and writing the SPE
 150    registers.  Zero if we've tried one of them and gotten an
 151    error.  */
 152 int have_ptrace_getsetevrregs = 1;
 153
 154
 155 int
 156 kernel_u_size (void)
 157 {
 158   return (sizeof (struct user));
 159 }
 160
 161 /* *INDENT-OFF* */
 162 /* registers layout, as presented by the ptrace interface:
 163 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
 164 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
 165 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
 166 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
 167 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
 168 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
 169 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
 170 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
 171 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
 172 /* *INDENT_ON * */
 173
 174 static int
 175 ppc_register_u_addr (int regno)
 176 {
 177   int u_addr = -1;
 178   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 179   /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
 180      interface, and not the wordsize of the program's ABI.  */
 181   int wordsize = sizeof (PTRACE_XFER_TYPE);
 182
 183   /* General purpose registers occupy 1 slot each in the buffer */
 184   if (regno >= tdep->ppc_gp0_regnum
 185       && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
 186     u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
 187
 188   /* Floating point regs: eight bytes each in both 32- and 64-bit
 189      ptrace interfaces.  Thus, two slots each in 32-bit interface, one
 190      slot each in 64-bit interface.  */
 191   if (tdep->ppc_fp0_regnum >= 0
 192       && regno >= tdep->ppc_fp0_regnum
 193       && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
 194     u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
 195
 196   /* UISA special purpose registers: 1 slot each */
 197   if (regno == PC_REGNUM)
 198     u_addr = PT_NIP * wordsize;
 199   if (regno == tdep->ppc_lr_regnum)
 200     u_addr = PT_LNK * wordsize;
 201   if (regno == tdep->ppc_cr_regnum)
 202     u_addr = PT_CCR * wordsize;
 203   if (regno == tdep->ppc_xer_regnum)
 204     u_addr = PT_XER * wordsize;
 205   if (regno == tdep->ppc_ctr_regnum)
 206     u_addr = PT_CTR * wordsize;
 207 #ifdef PT_MQ
 208   if (regno == tdep->ppc_mq_regnum)
 209     u_addr = PT_MQ * wordsize;
 210 #endif
 211   if (regno == tdep->ppc_ps_regnum)
 212     u_addr = PT_MSR * wordsize;
 213   if (tdep->ppc_fpscr_regnum >= 0
 214       && regno == tdep->ppc_fpscr_regnum)
 215     {
 216       /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
 217          kernel headers incorrectly contained the 32-bit definition of
 218          PT_FPSCR.  For the 32-bit definition, floating-point
 219          registers occupy two 32-bit "slots", and the FPSCR lives in
 220          the secondhalf of such a slot-pair (hence +1).  For 64-bit,
 221          the FPSCR instead occupies the full 64-bit 2-word-slot and
 222          hence no adjustment is necessary.  Hack around this.  */
 223       if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
 224         u_addr = (48 + 32) * wordsize;
 225       else
 226         u_addr = PT_FPSCR * wordsize;
 227     }
 228   return u_addr;
 229 }
 230
 231 /* The Linux kernel ptrace interface for AltiVec registers uses the
 232    registers set mechanism, as opposed to the interface for all the
 233    other registers, that stores/fetches each register individually.  */
 234 static void
 235 fetch_altivec_register (int tid, int regno)
 236 {
 237   int ret;
 238   int offset = 0;
 239   gdb_vrregset_t regs;
 240   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 241   int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
 242
 243   ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
 244   if (ret < 0)
 245     {
 246       if (errno == EIO)
 247         {
 248           have_ptrace_getvrregs = 0;
 249           return;
 250         }
 251       perror_with_name (_("Unable to fetch AltiVec register"));
 252     }
 253
 254   /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
 255      long on the hardware.  We deal only with the lower 4 bytes of the
 256      vector.  VRSAVE is at the end of the array in a 4 bytes slot, so
 257      there is no need to define an offset for it.  */
 258   if (regno == (tdep->ppc_vrsave_regnum - 1))
 259     offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
 260
 261   regcache_raw_supply (current_regcache, regno,
 262                        regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
 263 }
 264
 265 /* Fetch the top 32 bits of TID's general-purpose registers and the
 266    SPE-specific registers, and place the results in EVRREGSET.  If we
 267    don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
 268    zeros.
 269
 270    All the logic to deal with whether or not the PTRACE_GETEVRREGS and
 271    PTRACE_SETEVRREGS requests are supported is isolated here, and in
 272    set_spe_registers.  */
 273 static void
 274 get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
 275 {
 276   if (have_ptrace_getsetevrregs)
 277     {
 278       if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
 279         return;
 280       else
 281         {
 282           /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
 283              we just return zeros.  */
 284           if (errno == EIO)
 285             have_ptrace_getsetevrregs = 0;
 286           else
 287             /* Anything else needs to be reported.  */
 288             perror_with_name (_("Unable to fetch SPE registers"));
 289         }
 290     }
 291
 292   memset (evrregset, 0, sizeof (*evrregset));
 293 }
 294
 295 /* Supply values from TID for SPE-specific raw registers: the upper
 296    halves of the GPRs, the accumulator, and the spefscr.  REGNO must
 297    be the number of an upper half register, acc, spefscr, or -1 to
 298    supply the values of all registers.  */
 299 static void
 300 fetch_spe_register (int tid, int regno)
 301 {
 302   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 303   struct gdb_evrregset_t evrregs;
 304
 305   gdb_assert (sizeof (evrregs.evr[0])
 306               == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum));
 307   gdb_assert (sizeof (evrregs.acc)
 308               == register_size (current_gdbarch, tdep->ppc_acc_regnum));
 309   gdb_assert (sizeof (evrregs.spefscr)
 310               == register_size (current_gdbarch, tdep->ppc_spefscr_regnum));
 311
 312   get_spe_registers (tid, &evrregs);
 313
 314   if (regno == -1)
 315     {
 316       int i;
 317
 318       for (i = 0; i < ppc_num_gprs; i++)
 319         regcache_raw_supply (current_regcache, tdep->ppc_ev0_upper_regnum + i,
 320                              &evrregs.evr[i]);
 321     }
 322   else if (tdep->ppc_ev0_upper_regnum <= regno
 323            && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
 324     regcache_raw_supply (current_regcache, regno,
 325                          &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
 326
 327   if (regno == -1
 328       || regno == tdep->ppc_acc_regnum)
 329     regcache_raw_supply (current_regcache, tdep->ppc_acc_regnum, &evrregs.acc);
 330
 331   if (regno == -1
 332       || regno == tdep->ppc_spefscr_regnum)
 333     regcache_raw_supply (current_regcache, tdep->ppc_spefscr_regnum,
 334                          &evrregs.spefscr);
 335 }
 336
 337 static void
 338 fetch_register (int tid, int regno)
 339 {
 340   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 341   /* This isn't really an address.  But ptrace thinks of it as one.  */
 342   CORE_ADDR regaddr = ppc_register_u_addr (regno);
 343   int bytes_transferred;
 344   unsigned int offset;         /* Offset of registers within the u area. */
 345   char buf[MAX_REGISTER_SIZE];
 346
 347   if (altivec_register_p (regno))
 348     {
 349       /* If this is the first time through, or if it is not the first
 350          time through, and we have comfirmed that there is kernel
 351          support for such a ptrace request, then go and fetch the
 352          register.  */
 353       if (have_ptrace_getvrregs)
 354        {
 355          fetch_altivec_register (tid, regno);
 356          return;
 357        }
 358      /* If we have discovered that there is no ptrace support for
 359         AltiVec registers, fall through and return zeroes, because
 360         regaddr will be -1 in this case.  */
 361     }
 362   else if (spe_register_p (regno))
 363     {
 364       fetch_spe_register (tid, regno);
 365       return;
 366     }
 367
 368   if (regaddr == -1)
 369     {
 370       memset (buf, '\0', register_size (current_gdbarch, regno));   /* Supply zeroes */
 371       regcache_raw_supply (current_regcache, regno, buf);
 372       return;
 373     }
 374
 375   /* Read the raw register using PTRACE_XFER_TYPE sized chunks.  On a
 376      32-bit platform, 64-bit floating-point registers will require two
 377      transfers.  */
 378   for (bytes_transferred = 0;
 379        bytes_transferred < register_size (current_gdbarch, regno);
 380        bytes_transferred += sizeof (PTRACE_XFER_TYPE))
 381     {
 382       errno = 0;
 383       *(PTRACE_XFER_TYPE *) & buf[bytes_transferred]
 384         = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) regaddr, 0);
 385       regaddr += sizeof (PTRACE_XFER_TYPE);
 386       if (errno != 0)
 387         {
 388           char message[128];
 389           sprintf (message, "reading register %s (#%d)",
 390                    REGISTER_NAME (regno), regno);
 391           perror_with_name (message);
 392         }
 393     }
 394
 395   /* Now supply the register.  Keep in mind that the regcache's idea
 396      of the register's size may not be a multiple of sizeof
 397      (PTRACE_XFER_TYPE).  */
 398   if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
 399     {
 400       /* Little-endian values are always found at the left end of the
 401          bytes transferred.  */
 402       regcache_raw_supply (current_regcache, regno, buf);
 403     }
 404   else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
 405     {
 406       /* Big-endian values are found at the right end of the bytes
 407          transferred.  */
 408       size_t padding = (bytes_transferred
 409                         - register_size (current_gdbarch, regno));
 410       regcache_raw_supply (current_regcache, regno, buf + padding);
 411     }
 412   else
 413     internal_error (__FILE__, __LINE__,
 414                     _("fetch_register: unexpected byte order: %d"),
 415                     gdbarch_byte_order (current_gdbarch));
 416 }
 417
 418 static void
 419 supply_vrregset (gdb_vrregset_t *vrregsetp)
 420 {
 421   int i;
 422   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 423   int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
 424   int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
 425   int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
 426
 427   for (i = 0; i < num_of_vrregs; i++)
 428     {
 429       /* The last 2 registers of this set are only 32 bit long, not
 430          128.  However an offset is necessary only for VSCR because it
 431          occupies a whole vector, while VRSAVE occupies a full 4 bytes
 432          slot.  */
 433       if (i == (num_of_vrregs - 2))
 434         regcache_raw_supply (current_regcache, tdep->ppc_vr0_regnum + i,
 435                              *vrregsetp + i * vrregsize + offset);
 436       else
 437         regcache_raw_supply (current_regcache, tdep->ppc_vr0_regnum + i,
 438                              *vrregsetp + i * vrregsize);
 439     }
 440 }
 441
 442 static void
 443 fetch_altivec_registers (int tid)
 444 {
 445   int ret;
 446   gdb_vrregset_t regs;
 447
 448   ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
 449   if (ret < 0)
 450     {
 451       if (errno == EIO)
 452         {
 453           have_ptrace_getvrregs = 0;
 454           return;
 455         }
 456       perror_with_name (_("Unable to fetch AltiVec registers"));
 457     }
 458   supply_vrregset (&regs);
 459 }
 460
 461 static void
 462 fetch_ppc_registers (int tid)
 463 {
 464   int i;
 465   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 466
 467   for (i = 0; i < ppc_num_gprs; i++)
 468     fetch_register (tid, tdep->ppc_gp0_regnum + i);
 469   if (tdep->ppc_fp0_regnum >= 0)
 470     for (i = 0; i < ppc_num_fprs; i++)
 471       fetch_register (tid, tdep->ppc_fp0_regnum + i);
 472   fetch_register (tid, PC_REGNUM);
 473   if (tdep->ppc_ps_regnum != -1)
 474     fetch_register (tid, tdep->ppc_ps_regnum);
 475   if (tdep->ppc_cr_regnum != -1)
 476     fetch_register (tid, tdep->ppc_cr_regnum);
 477   if (tdep->ppc_lr_regnum != -1)
 478     fetch_register (tid, tdep->ppc_lr_regnum);
 479   if (tdep->ppc_ctr_regnum != -1)
 480     fetch_register (tid, tdep->ppc_ctr_regnum);
 481   if (tdep->ppc_xer_regnum != -1)
 482     fetch_register (tid, tdep->ppc_xer_regnum);
 483   if (tdep->ppc_mq_regnum != -1)
 484     fetch_register (tid, tdep->ppc_mq_regnum);
 485   if (tdep->ppc_fpscr_regnum != -1)
 486     fetch_register (tid, tdep->ppc_fpscr_regnum);
 487   if (have_ptrace_getvrregs)
 488     if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
 489       fetch_altivec_registers (tid);
 490   if (tdep->ppc_ev0_upper_regnum >= 0)
 491     fetch_spe_register (tid, -1);
 492 }
 493
 494 /* Fetch registers from the child process.  Fetch all registers if
 495    regno == -1, otherwise fetch all general registers or all floating
 496    point registers depending upon the value of regno.  */
 497 void
 498 fetch_inferior_registers (int regno)
 499 {
 500   /* Overload thread id onto process id */
 501   int tid = TIDGET (inferior_ptid);
 502
 503   /* No thread id, just use process id */
 504   if (tid == 0)
 505     tid = PIDGET (inferior_ptid);
 506
 507   if (regno == -1)
 508     fetch_ppc_registers (tid);
 509   else
 510     fetch_register (tid, regno);
 511 }
 512
 513 /* Store one register. */
 514 static void
 515 store_altivec_register (int tid, int regno)
 516 {
 517   int ret;
 518   int offset = 0;
 519   gdb_vrregset_t regs;
 520   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 521   int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
 522
 523   ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
 524   if (ret < 0)
 525     {
 526       if (errno == EIO)
 527         {
 528           have_ptrace_getvrregs = 0;
 529           return;
 530         }
 531       perror_with_name (_("Unable to fetch AltiVec register"));
 532     }
 533
 534   /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
 535      long on the hardware.  */
 536   if (regno == (tdep->ppc_vrsave_regnum - 1))
 537     offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
 538
 539   regcache_raw_collect (current_regcache, regno,
 540                         regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
 541
 542   ret = ptrace (PTRACE_SETVRREGS, tid, 0, &regs);
 543   if (ret < 0)
 544     perror_with_name (_("Unable to store AltiVec register"));
 545 }
 546
 547 /* Assuming TID referrs to an SPE process, set the top halves of TID's
 548    general-purpose registers and its SPE-specific registers to the
 549    values in EVRREGSET.  If we don't support PTRACE_SETEVRREGS, do
 550    nothing.
 551
 552    All the logic to deal with whether or not the PTRACE_GETEVRREGS and
 553    PTRACE_SETEVRREGS requests are supported is isolated here, and in
 554    get_spe_registers.  */
 555 static void
 556 set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
 557 {
 558   if (have_ptrace_getsetevrregs)
 559     {
 560       if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
 561         return;
 562       else
 563         {
 564           /* EIO means that the PTRACE_SETEVRREGS request isn't
 565              supported; we fail silently, and don't try the call
 566              again.  */
 567           if (errno == EIO)
 568             have_ptrace_getsetevrregs = 0;
 569           else
 570             /* Anything else needs to be reported.  */
 571             perror_with_name (_("Unable to set SPE registers"));
 572         }
 573     }
 574 }
 575
 576 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
 577    If REGNO is -1, write the values of all the SPE-specific
 578    registers.  */
 579 static void
 580 store_spe_register (int tid, int regno)
 581 {
 582   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 583   struct gdb_evrregset_t evrregs;
 584
 585   gdb_assert (sizeof (evrregs.evr[0])
 586               == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum));
 587   gdb_assert (sizeof (evrregs.acc)
 588               == register_size (current_gdbarch, tdep->ppc_acc_regnum));
 589   gdb_assert (sizeof (evrregs.spefscr)
 590               == register_size (current_gdbarch, tdep->ppc_spefscr_regnum));
 591
 592   if (regno == -1)
 593     /* Since we're going to write out every register, the code below
 594        should store to every field of evrregs; if that doesn't happen,
 595        make it obvious by initializing it with suspicious values.  */
 596     memset (&evrregs, 42, sizeof (evrregs));
 597   else
 598     /* We can only read and write the entire EVR register set at a
 599        time, so to write just a single register, we do a
 600        read-modify-write maneuver.  */
 601     get_spe_registers (tid, &evrregs);
 602
 603   if (regno == -1)
 604     {
 605       int i;
 606
 607       for (i = 0; i < ppc_num_gprs; i++)
 608         regcache_raw_collect (current_regcache,
 609                               tdep->ppc_ev0_upper_regnum + i,
 610                               &evrregs.evr[i]);
 611     }
 612   else if (tdep->ppc_ev0_upper_regnum <= regno
 613            && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
 614     regcache_raw_collect (current_regcache, regno,
 615                           &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
 616
 617   if (regno == -1
 618       || regno == tdep->ppc_acc_regnum)
 619     regcache_raw_collect (current_regcache,
 620                           tdep->ppc_acc_regnum,
 621                           &evrregs.acc);
 622
 623   if (regno == -1
 624       || regno == tdep->ppc_spefscr_regnum)
 625     regcache_raw_collect (current_regcache,
 626                           tdep->ppc_spefscr_regnum,
 627                           &evrregs.spefscr);
 628
 629   /* Write back the modified register set.  */
 630   set_spe_registers (tid, &evrregs);
 631 }
 632
 633 static void
 634 store_register (int tid, int regno)
 635 {
 636   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 637   /* This isn't really an address.  But ptrace thinks of it as one.  */
 638   CORE_ADDR regaddr = ppc_register_u_addr (regno);
 639   int i;
 640   size_t bytes_to_transfer;
 641   char buf[MAX_REGISTER_SIZE];
 642
 643   if (altivec_register_p (regno))
 644     {
 645       store_altivec_register (tid, regno);
 646       return;
 647     }
 648   else if (spe_register_p (regno))
 649     {
 650       store_spe_register (tid, regno);
 651       return;
 652     }
 653
 654   if (regaddr == -1)
 655     return;
 656
 657   /* First collect the register.  Keep in mind that the regcache's
 658      idea of the register's size may not be a multiple of sizeof
 659      (PTRACE_XFER_TYPE).  */
 660   memset (buf, 0, sizeof buf);
 661   bytes_to_transfer = align_up (register_size (current_gdbarch, regno),
 662                                 sizeof (PTRACE_XFER_TYPE));
 663   if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
 664     {
 665       /* Little-endian values always sit at the left end of the buffer.  */
 666       regcache_raw_collect (current_regcache, regno, buf);
 667     }
 668   else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 669     {
 670       /* Big-endian values sit at the right end of the buffer.  */
 671       size_t padding = (bytes_to_transfer
 672                         - register_size (current_gdbarch, regno));
 673       regcache_raw_collect (current_regcache, regno, buf + padding);
 674     }
 675
 676   for (i = 0; i < bytes_to_transfer; i += sizeof (PTRACE_XFER_TYPE))
 677     {
 678       errno = 0;
 679       ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) regaddr,
 680               *(PTRACE_XFER_TYPE *) & buf[i]);
 681       regaddr += sizeof (PTRACE_XFER_TYPE);
 682
 683       if (errno == EIO
 684           && regno == tdep->ppc_fpscr_regnum)
 685         {
 686           /* Some older kernel versions don't allow fpscr to be written.  */
 687           continue;
 688         }
 689
 690       if (errno != 0)
 691         {
 692           char message[128];
 693           sprintf (message, "writing register %s (#%d)",
 694                    REGISTER_NAME (regno), regno);
 695           perror_with_name (message);
 696         }
 697     }
 698 }
 699
 700 static void
 701 fill_vrregset (gdb_vrregset_t *vrregsetp)
 702 {
 703   int i;
 704   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 705   int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
 706   int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
 707   int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
 708
 709   for (i = 0; i < num_of_vrregs; i++)
 710     {
 711       /* The last 2 registers of this set are only 32 bit long, not
 712          128, but only VSCR is fetched as a 16 bytes quantity.  */
 713       if (i == (num_of_vrregs - 2))
 714         regcache_raw_collect (current_regcache, tdep->ppc_vr0_regnum + i,
 715                               *vrregsetp + i * vrregsize + offset);
 716       else
 717         regcache_raw_collect (current_regcache, tdep->ppc_vr0_regnum + i,
 718                               *vrregsetp + i * vrregsize);
 719     }
 720 }
 721
 722 static void
 723 store_altivec_registers (int tid)
 724 {
 725   int ret;
 726   gdb_vrregset_t regs;
 727
 728   ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
 729   if (ret < 0)
 730     {
 731       if (errno == EIO)
 732         {
 733           have_ptrace_getvrregs = 0;
 734           return;
 735         }
 736       perror_with_name (_("Couldn't get AltiVec registers"));
 737     }
 738
 739   fill_vrregset (&regs);
 740
 741   if (ptrace (PTRACE_SETVRREGS, tid, 0, &regs) < 0)
 742     perror_with_name (_("Couldn't write AltiVec registers"));
 743 }
 744
 745 static void
 746 store_ppc_registers (int tid)
 747 {
 748   int i;
 749   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 750
 751   for (i = 0; i < ppc_num_gprs; i++)
 752     store_register (tid, tdep->ppc_gp0_regnum + i);
 753   if (tdep->ppc_fp0_regnum >= 0)
 754     for (i = 0; i < ppc_num_fprs; i++)
 755       store_register (tid, tdep->ppc_fp0_regnum + i);
 756   store_register (tid, PC_REGNUM);
 757   if (tdep->ppc_ps_regnum != -1)
 758     store_register (tid, tdep->ppc_ps_regnum);
 759   if (tdep->ppc_cr_regnum != -1)
 760     store_register (tid, tdep->ppc_cr_regnum);
 761   if (tdep->ppc_lr_regnum != -1)
 762     store_register (tid, tdep->ppc_lr_regnum);
 763   if (tdep->ppc_ctr_regnum != -1)
 764     store_register (tid, tdep->ppc_ctr_regnum);
 765   if (tdep->ppc_xer_regnum != -1)
 766     store_register (tid, tdep->ppc_xer_regnum);
 767   if (tdep->ppc_mq_regnum != -1)
 768     store_register (tid, tdep->ppc_mq_regnum);
 769   if (tdep->ppc_fpscr_regnum != -1)
 770     store_register (tid, tdep->ppc_fpscr_regnum);
 771   if (have_ptrace_getvrregs)
 772     if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
 773       store_altivec_registers (tid);
 774   if (tdep->ppc_ev0_upper_regnum >= 0)
 775     store_spe_register (tid, -1);
 776 }
 777
 778 void
 779 store_inferior_registers (int regno)
 780 {
 781   /* Overload thread id onto process id */
 782   int tid = TIDGET (inferior_ptid);
 783
 784   /* No thread id, just use process id */
 785   if (tid == 0)
 786     tid = PIDGET (inferior_ptid);
 787
 788   if (regno >= 0)
 789     store_register (tid, regno);
 790   else
 791     store_ppc_registers (tid);
 792 }
 793
 794 void
 795 supply_gregset (gdb_gregset_t *gregsetp)
 796 {
 797   /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
 798      interface, and not the wordsize of the program's ABI.  */
 799   int wordsize = sizeof (PTRACE_XFER_TYPE);
 800   ppc_linux_supply_gregset (current_regcache, -1, gregsetp,
 801                             sizeof (gdb_gregset_t), wordsize);
 802 }
 803
 804 static void
 805 right_fill_reg (int regnum, void *reg)
 806 {
 807   /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
 808      interface, and not the wordsize of the program's ABI.  */
 809   int wordsize = sizeof (PTRACE_XFER_TYPE);
 810   /* Right fill the register.  */
 811   regcache_raw_collect (current_regcache, regnum,
 812                         ((bfd_byte *) reg
 813                          + wordsize
 814                          - register_size (current_gdbarch, regnum)));
 815 }
 816
 817 void
 818 fill_gregset (gdb_gregset_t *gregsetp, int regno)
 819 {
 820   int regi;
 821   elf_greg_t *regp = (elf_greg_t *) gregsetp;
 822   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 823   const int elf_ngreg = 48;
 824
 825
 826   /* Start with zeros.  */
 827   memset (regp, 0, elf_ngreg * sizeof (*regp));
 828
 829   for (regi = 0; regi < ppc_num_gprs; regi++)
 830     {
 831       if ((regno == -1) || regno == tdep->ppc_gp0_regnum + regi)
 832         right_fill_reg (tdep->ppc_gp0_regnum + regi, (regp + PT_R0 + regi));
 833     }
 834
 835   if ((regno == -1) || regno == PC_REGNUM)
 836     right_fill_reg (PC_REGNUM, regp + PT_NIP);
 837   if ((regno == -1) || regno == tdep->ppc_lr_regnum)
 838     right_fill_reg (tdep->ppc_lr_regnum, regp + PT_LNK);
 839   if ((regno == -1) || regno == tdep->ppc_cr_regnum)
 840     regcache_raw_collect (current_regcache, tdep->ppc_cr_regnum,
 841                           regp + PT_CCR);
 842   if ((regno == -1) || regno == tdep->ppc_xer_regnum)
 843     regcache_raw_collect (current_regcache, tdep->ppc_xer_regnum,
 844                           regp + PT_XER);
 845   if ((regno == -1) || regno == tdep->ppc_ctr_regnum)
 846     right_fill_reg (tdep->ppc_ctr_regnum, regp + PT_CTR);
 847 #ifdef PT_MQ
 848   if (((regno == -1) || regno == tdep->ppc_mq_regnum)
 849       && (tdep->ppc_mq_regnum != -1))
 850     right_fill_reg (tdep->ppc_mq_regnum, regp + PT_MQ);
 851 #endif
 852   if ((regno == -1) || regno == tdep->ppc_ps_regnum)
 853     right_fill_reg (tdep->ppc_ps_regnum, regp + PT_MSR);
 854 }
 855
 856 void
 857 supply_fpregset (gdb_fpregset_t * fpregsetp)
 858 {
 859   ppc_linux_supply_fpregset (NULL, current_regcache, -1, fpregsetp,
 860                              sizeof (gdb_fpregset_t));
 861 }
 862
 863 /* Given a pointer to a floating point register set in /proc format
 864    (fpregset_t *), update the register specified by REGNO from gdb's
 865    idea of the current floating point register set.  If REGNO is -1,
 866    update them all.  */
 867 void
 868 fill_fpregset (gdb_fpregset_t *fpregsetp, int regno)
 869 {
 870   int regi;
 871   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 872   bfd_byte *fpp = (void *) fpregsetp;
 873
 874   if (ppc_floating_point_unit_p (current_gdbarch))
 875     {
 876       for (regi = 0; regi < ppc_num_fprs; regi++)
 877         {
 878           if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi))
 879             regcache_raw_collect (current_regcache, tdep->ppc_fp0_regnum + regi,
 880                                   fpp + 8 * regi);
 881         }
 882       if (regno == -1 || regno == tdep->ppc_fpscr_regnum)
 883         right_fill_reg (tdep->ppc_fpscr_regnum, (fpp + 8 * 32));
 884     }
 885 }