2011-01-10 Michael Snyder <msnyder@vmware.com>
[deliverable/binutils-gdb.git] / gdb / ppc-linux-nat.c
1 /* PPC GNU/Linux native support.
2
3 Copyright (C) 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002, 2003,
4 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
5 Free Software Foundation, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22 #include "defs.h"
23 #include "gdb_string.h"
24 #include "observer.h"
25 #include "frame.h"
26 #include "inferior.h"
27 #include "gdbthread.h"
28 #include "gdbcore.h"
29 #include "regcache.h"
30 #include "gdb_assert.h"
31 #include "target.h"
32 #include "linux-nat.h"
33
34 #include <stdint.h>
35 #include <sys/types.h>
36 #include <sys/param.h>
37 #include <signal.h>
38 #include <sys/user.h>
39 #include <sys/ioctl.h>
40 #include "gdb_wait.h"
41 #include <fcntl.h>
42 #include <sys/procfs.h>
43 #include <sys/ptrace.h>
44
45 /* Prototypes for supply_gregset etc. */
46 #include "gregset.h"
47 #include "ppc-tdep.h"
48 #include "ppc-linux-tdep.h"
49
50 /* Required when using the AUXV. */
51 #include "elf/common.h"
52 #include "auxv.h"
53
54 /* This sometimes isn't defined. */
55 #ifndef PT_ORIG_R3
56 #define PT_ORIG_R3 34
57 #endif
58 #ifndef PT_TRAP
59 #define PT_TRAP 40
60 #endif
61
62 /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
63 If they aren't, we can provide them ourselves (their values are fixed
64 because they are part of the kernel ABI). They are used in the AT_HWCAP
65 entry of the AUXV. */
66 #ifndef PPC_FEATURE_CELL
67 #define PPC_FEATURE_CELL 0x00010000
68 #endif
69 #ifndef PPC_FEATURE_BOOKE
70 #define PPC_FEATURE_BOOKE 0x00008000
71 #endif
72 #ifndef PPC_FEATURE_HAS_DFP
73 #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */
74 #endif
75
76 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
77 configure time check. Some older glibc's (for instance 2.2.1)
78 don't have a specific powerpc version of ptrace.h, and fall back on
79 a generic one. In such cases, sys/ptrace.h defines
80 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
81 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
82 PTRACE_SETVRREGS to be. This also makes a configury check pretty
83 much useless. */
84
85 /* These definitions should really come from the glibc header files,
86 but Glibc doesn't know about the vrregs yet. */
87 #ifndef PTRACE_GETVRREGS
88 #define PTRACE_GETVRREGS 18
89 #define PTRACE_SETVRREGS 19
90 #endif
91
92 /* PTRACE requests for POWER7 VSX registers. */
93 #ifndef PTRACE_GETVSXREGS
94 #define PTRACE_GETVSXREGS 27
95 #define PTRACE_SETVSXREGS 28
96 #endif
97
98 /* Similarly for the ptrace requests for getting / setting the SPE
99 registers (ev0 -- ev31, acc, and spefscr). See the description of
100 gdb_evrregset_t for details. */
101 #ifndef PTRACE_GETEVRREGS
102 #define PTRACE_GETEVRREGS 20
103 #define PTRACE_SETEVRREGS 21
104 #endif
105
106 /* Similarly for the hardware watchpoint support. These requests are used
107 when the BookE kernel interface is not available. */
108 #ifndef PTRACE_GET_DEBUGREG
109 #define PTRACE_GET_DEBUGREG 25
110 #endif
111 #ifndef PTRACE_SET_DEBUGREG
112 #define PTRACE_SET_DEBUGREG 26
113 #endif
114 #ifndef PTRACE_GETSIGINFO
115 #define PTRACE_GETSIGINFO 0x4202
116 #endif
117
118 /* These requests are used when the BookE kernel interface is available.
119 It exposes the additional debug features of BookE processors, such as
120 ranged breakpoints and watchpoints and hardware-accelerated condition
121 evaluation. */
122 #ifndef PPC_PTRACE_GETHWDBGINFO
123
124 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the new BookE
125 interface is not present in ptrace.h, so we'll have to pretty much include
126 it all here so that the code at least compiles on older systems. */
127 #define PPC_PTRACE_GETHWDBGINFO 0x89
128 #define PPC_PTRACE_SETHWDEBUG 0x88
129 #define PPC_PTRACE_DELHWDEBUG 0x87
130
131 struct ppc_debug_info
132 {
133 uint32_t version; /* Only version 1 exists to date. */
134 uint32_t num_instruction_bps;
135 uint32_t num_data_bps;
136 uint32_t num_condition_regs;
137 uint32_t data_bp_alignment;
138 uint32_t sizeof_condition; /* size of the DVC register. */
139 uint64_t features;
140 };
141
142 /* Features will have bits indicating whether there is support for: */
143 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
144 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
145 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
146 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
147
148 struct ppc_hw_breakpoint
149 {
150 uint32_t version; /* currently, version must be 1 */
151 uint32_t trigger_type; /* only some combinations allowed */
152 uint32_t addr_mode; /* address match mode */
153 uint32_t condition_mode; /* break/watchpoint condition flags */
154 uint64_t addr; /* break/watchpoint address */
155 uint64_t addr2; /* range end or mask */
156 uint64_t condition_value; /* contents of the DVC register */
157 };
158
159 /* Trigger type. */
160 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
161 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
162 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
163 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
164
165 /* Address mode. */
166 #define PPC_BREAKPOINT_MODE_EXACT 0x0
167 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
168 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
169 #define PPC_BREAKPOINT_MODE_MASK 0x3
170
171 /* Condition mode. */
172 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
173 #define PPC_BREAKPOINT_CONDITION_AND 0x1
174 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
175 #define PPC_BREAKPOINT_CONDITION_OR 0x2
176 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
177 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
178 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
179 #define PPC_BREAKPOINT_CONDITION_BE(n) \
180 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
181 #endif /* PPC_PTRACE_GETHWDBGINFO */
182
183
184
185 /* Similarly for the general-purpose (gp0 -- gp31)
186 and floating-point registers (fp0 -- fp31). */
187 #ifndef PTRACE_GETREGS
188 #define PTRACE_GETREGS 12
189 #endif
190 #ifndef PTRACE_SETREGS
191 #define PTRACE_SETREGS 13
192 #endif
193 #ifndef PTRACE_GETFPREGS
194 #define PTRACE_GETFPREGS 14
195 #endif
196 #ifndef PTRACE_SETFPREGS
197 #define PTRACE_SETFPREGS 15
198 #endif
199
200 /* This oddity is because the Linux kernel defines elf_vrregset_t as
201 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
202 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
203 the vrsave as an extra 4 bytes at the end. I opted for creating a
204 flat array of chars, so that it is easier to manipulate for gdb.
205
206 There are 32 vector registers 16 bytes longs, plus a VSCR register
207 which is only 4 bytes long, but is fetched as a 16 bytes
208 quantity. Up to here we have the elf_vrregset_t structure.
209 Appended to this there is space for the VRSAVE register: 4 bytes.
210 Even though this vrsave register is not included in the regset
211 typedef, it is handled by the ptrace requests.
212
213 Note that GNU/Linux doesn't support little endian PPC hardware,
214 therefore the offset at which the real value of the VSCR register
215 is located will be always 12 bytes.
216
217 The layout is like this (where x is the actual value of the vscr reg): */
218
219 /* *INDENT-OFF* */
220 /*
221 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
222 <-------> <-------><-------><->
223 VR0 VR31 VSCR VRSAVE
224 */
225 /* *INDENT-ON* */
226
227 #define SIZEOF_VRREGS 33*16+4
228
229 typedef char gdb_vrregset_t[SIZEOF_VRREGS];
230
231 /* This is the layout of the POWER7 VSX registers and the way they overlap
232 with the existing FPR and VMX registers.
233
234 VSR doubleword 0 VSR doubleword 1
235 ----------------------------------------------------------------
236 VSR[0] | FPR[0] | |
237 ----------------------------------------------------------------
238 VSR[1] | FPR[1] | |
239 ----------------------------------------------------------------
240 | ... | |
241 | ... | |
242 ----------------------------------------------------------------
243 VSR[30] | FPR[30] | |
244 ----------------------------------------------------------------
245 VSR[31] | FPR[31] | |
246 ----------------------------------------------------------------
247 VSR[32] | VR[0] |
248 ----------------------------------------------------------------
249 VSR[33] | VR[1] |
250 ----------------------------------------------------------------
251 | ... |
252 | ... |
253 ----------------------------------------------------------------
254 VSR[62] | VR[30] |
255 ----------------------------------------------------------------
256 VSR[63] | VR[31] |
257 ----------------------------------------------------------------
258
259 VSX has 64 128bit registers. The first 32 registers overlap with
260 the FP registers (doubleword 0) and hence extend them with additional
261 64 bits (doubleword 1). The other 32 regs overlap with the VMX
262 registers. */
263 #define SIZEOF_VSXREGS 32*8
264
265 typedef char gdb_vsxregset_t[SIZEOF_VSXREGS];
266
267 /* On PPC processors that support the the Signal Processing Extension
268 (SPE) APU, the general-purpose registers are 64 bits long.
269 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
270 ptrace calls only access the lower half of each register, to allow
271 them to behave the same way they do on non-SPE systems. There's a
272 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
273 read and write the top halves of all the general-purpose registers
274 at once, along with some SPE-specific registers.
275
276 GDB itself continues to claim the general-purpose registers are 32
277 bits long. It has unnamed raw registers that hold the upper halves
278 of the gprs, and the the full 64-bit SIMD views of the registers,
279 'ev0' -- 'ev31', are pseudo-registers that splice the top and
280 bottom halves together.
281
282 This is the structure filled in by PTRACE_GETEVRREGS and written to
283 the inferior's registers by PTRACE_SETEVRREGS. */
284 struct gdb_evrregset_t
285 {
286 unsigned long evr[32];
287 unsigned long long acc;
288 unsigned long spefscr;
289 };
290
291 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
292 PTRACE_SETVSXREGS requests, for reading and writing the VSX
293 POWER7 registers 0 through 31. Zero if we've tried one of them and
294 gotten an error. Note that VSX registers 32 through 63 overlap
295 with VR registers 0 through 31. */
296 int have_ptrace_getsetvsxregs = 1;
297
298 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
299 PTRACE_SETVRREGS requests, for reading and writing the Altivec
300 registers. Zero if we've tried one of them and gotten an
301 error. */
302 int have_ptrace_getvrregs = 1;
303
304 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
305 PTRACE_SETEVRREGS requests, for reading and writing the SPE
306 registers. Zero if we've tried one of them and gotten an
307 error. */
308 int have_ptrace_getsetevrregs = 1;
309
310 /* Non-zero if our kernel may support the PTRACE_GETREGS and
311 PTRACE_SETREGS requests, for reading and writing the
312 general-purpose registers. Zero if we've tried one of
313 them and gotten an error. */
314 int have_ptrace_getsetregs = 1;
315
316 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
317 PTRACE_SETFPREGS requests, for reading and writing the
318 floating-pointers registers. Zero if we've tried one of
319 them and gotten an error. */
320 int have_ptrace_getsetfpregs = 1;
321
322 /* *INDENT-OFF* */
323 /* registers layout, as presented by the ptrace interface:
324 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
325 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
326 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
327 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
328 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
329 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
330 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
331 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
332 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
333 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
334 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
335 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
336 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
337 /* *INDENT_ON * */
338
339 static int
340 ppc_register_u_addr (struct gdbarch *gdbarch, int regno)
341 {
342 int u_addr = -1;
343 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
344 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
345 interface, and not the wordsize of the program's ABI. */
346 int wordsize = sizeof (long);
347
348 /* General purpose registers occupy 1 slot each in the buffer. */
349 if (regno >= tdep->ppc_gp0_regnum
350 && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
351 u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
352
353 /* Floating point regs: eight bytes each in both 32- and 64-bit
354 ptrace interfaces. Thus, two slots each in 32-bit interface, one
355 slot each in 64-bit interface. */
356 if (tdep->ppc_fp0_regnum >= 0
357 && regno >= tdep->ppc_fp0_regnum
358 && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
359 u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
360
361 /* UISA special purpose registers: 1 slot each. */
362 if (regno == gdbarch_pc_regnum (gdbarch))
363 u_addr = PT_NIP * wordsize;
364 if (regno == tdep->ppc_lr_regnum)
365 u_addr = PT_LNK * wordsize;
366 if (regno == tdep->ppc_cr_regnum)
367 u_addr = PT_CCR * wordsize;
368 if (regno == tdep->ppc_xer_regnum)
369 u_addr = PT_XER * wordsize;
370 if (regno == tdep->ppc_ctr_regnum)
371 u_addr = PT_CTR * wordsize;
372 #ifdef PT_MQ
373 if (regno == tdep->ppc_mq_regnum)
374 u_addr = PT_MQ * wordsize;
375 #endif
376 if (regno == tdep->ppc_ps_regnum)
377 u_addr = PT_MSR * wordsize;
378 if (regno == PPC_ORIG_R3_REGNUM)
379 u_addr = PT_ORIG_R3 * wordsize;
380 if (regno == PPC_TRAP_REGNUM)
381 u_addr = PT_TRAP * wordsize;
382 if (tdep->ppc_fpscr_regnum >= 0
383 && regno == tdep->ppc_fpscr_regnum)
384 {
385 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
386 kernel headers incorrectly contained the 32-bit definition of
387 PT_FPSCR. For the 32-bit definition, floating-point
388 registers occupy two 32-bit "slots", and the FPSCR lives in
389 the second half of such a slot-pair (hence +1). For 64-bit,
390 the FPSCR instead occupies the full 64-bit 2-word-slot and
391 hence no adjustment is necessary. Hack around this. */
392 if (wordsize == 8 && PT_FPSCR == (48 + 32 + 1))
393 u_addr = (48 + 32) * wordsize;
394 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
395 slot and not just its second word. The PT_FPSCR supplied when
396 GDB is compiled as a 32-bit app doesn't reflect this. */
397 else if (wordsize == 4 && register_size (gdbarch, regno) == 8
398 && PT_FPSCR == (48 + 2*32 + 1))
399 u_addr = (48 + 2*32) * wordsize;
400 else
401 u_addr = PT_FPSCR * wordsize;
402 }
403 return u_addr;
404 }
405
406 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
407 registers set mechanism, as opposed to the interface for all the
408 other registers, that stores/fetches each register individually. */
409 static void
410 fetch_vsx_register (struct regcache *regcache, int tid, int regno)
411 {
412 int ret;
413 gdb_vsxregset_t regs;
414 struct gdbarch *gdbarch = get_regcache_arch (regcache);
415 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
416 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
417
418 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
419 if (ret < 0)
420 {
421 if (errno == EIO)
422 {
423 have_ptrace_getsetvsxregs = 0;
424 return;
425 }
426 perror_with_name (_("Unable to fetch VSX register"));
427 }
428
429 regcache_raw_supply (regcache, regno,
430 regs + (regno - tdep->ppc_vsr0_upper_regnum)
431 * vsxregsize);
432 }
433
434 /* The Linux kernel ptrace interface for AltiVec registers uses the
435 registers set mechanism, as opposed to the interface for all the
436 other registers, that stores/fetches each register individually. */
437 static void
438 fetch_altivec_register (struct regcache *regcache, int tid, int regno)
439 {
440 int ret;
441 int offset = 0;
442 gdb_vrregset_t regs;
443 struct gdbarch *gdbarch = get_regcache_arch (regcache);
444 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
445 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
446
447 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
448 if (ret < 0)
449 {
450 if (errno == EIO)
451 {
452 have_ptrace_getvrregs = 0;
453 return;
454 }
455 perror_with_name (_("Unable to fetch AltiVec register"));
456 }
457
458 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
459 long on the hardware. We deal only with the lower 4 bytes of the
460 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
461 there is no need to define an offset for it. */
462 if (regno == (tdep->ppc_vrsave_regnum - 1))
463 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
464
465 regcache_raw_supply (regcache, regno,
466 regs + (regno
467 - tdep->ppc_vr0_regnum) * vrregsize + offset);
468 }
469
470 /* Fetch the top 32 bits of TID's general-purpose registers and the
471 SPE-specific registers, and place the results in EVRREGSET. If we
472 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
473 zeros.
474
475 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
476 PTRACE_SETEVRREGS requests are supported is isolated here, and in
477 set_spe_registers. */
478 static void
479 get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
480 {
481 if (have_ptrace_getsetevrregs)
482 {
483 if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
484 return;
485 else
486 {
487 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
488 we just return zeros. */
489 if (errno == EIO)
490 have_ptrace_getsetevrregs = 0;
491 else
492 /* Anything else needs to be reported. */
493 perror_with_name (_("Unable to fetch SPE registers"));
494 }
495 }
496
497 memset (evrregset, 0, sizeof (*evrregset));
498 }
499
500 /* Supply values from TID for SPE-specific raw registers: the upper
501 halves of the GPRs, the accumulator, and the spefscr. REGNO must
502 be the number of an upper half register, acc, spefscr, or -1 to
503 supply the values of all registers. */
504 static void
505 fetch_spe_register (struct regcache *regcache, int tid, int regno)
506 {
507 struct gdbarch *gdbarch = get_regcache_arch (regcache);
508 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
509 struct gdb_evrregset_t evrregs;
510
511 gdb_assert (sizeof (evrregs.evr[0])
512 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
513 gdb_assert (sizeof (evrregs.acc)
514 == register_size (gdbarch, tdep->ppc_acc_regnum));
515 gdb_assert (sizeof (evrregs.spefscr)
516 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
517
518 get_spe_registers (tid, &evrregs);
519
520 if (regno == -1)
521 {
522 int i;
523
524 for (i = 0; i < ppc_num_gprs; i++)
525 regcache_raw_supply (regcache, tdep->ppc_ev0_upper_regnum + i,
526 &evrregs.evr[i]);
527 }
528 else if (tdep->ppc_ev0_upper_regnum <= regno
529 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
530 regcache_raw_supply (regcache, regno,
531 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
532
533 if (regno == -1
534 || regno == tdep->ppc_acc_regnum)
535 regcache_raw_supply (regcache, tdep->ppc_acc_regnum, &evrregs.acc);
536
537 if (regno == -1
538 || regno == tdep->ppc_spefscr_regnum)
539 regcache_raw_supply (regcache, tdep->ppc_spefscr_regnum,
540 &evrregs.spefscr);
541 }
542
543 static void
544 fetch_register (struct regcache *regcache, int tid, int regno)
545 {
546 struct gdbarch *gdbarch = get_regcache_arch (regcache);
547 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
548 /* This isn't really an address. But ptrace thinks of it as one. */
549 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
550 int bytes_transferred;
551 unsigned int offset; /* Offset of registers within the u area. */
552 char buf[MAX_REGISTER_SIZE];
553
554 if (altivec_register_p (gdbarch, regno))
555 {
556 /* If this is the first time through, or if it is not the first
557 time through, and we have comfirmed that there is kernel
558 support for such a ptrace request, then go and fetch the
559 register. */
560 if (have_ptrace_getvrregs)
561 {
562 fetch_altivec_register (regcache, tid, regno);
563 return;
564 }
565 /* If we have discovered that there is no ptrace support for
566 AltiVec registers, fall through and return zeroes, because
567 regaddr will be -1 in this case. */
568 }
569 if (vsx_register_p (gdbarch, regno))
570 {
571 if (have_ptrace_getsetvsxregs)
572 {
573 fetch_vsx_register (regcache, tid, regno);
574 return;
575 }
576 }
577 else if (spe_register_p (gdbarch, regno))
578 {
579 fetch_spe_register (regcache, tid, regno);
580 return;
581 }
582
583 if (regaddr == -1)
584 {
585 memset (buf, '\0', register_size (gdbarch, regno)); /* Supply zeroes */
586 regcache_raw_supply (regcache, regno, buf);
587 return;
588 }
589
590 /* Read the raw register using sizeof(long) sized chunks. On a
591 32-bit platform, 64-bit floating-point registers will require two
592 transfers. */
593 for (bytes_transferred = 0;
594 bytes_transferred < register_size (gdbarch, regno);
595 bytes_transferred += sizeof (long))
596 {
597 errno = 0;
598 *(long *) &buf[bytes_transferred]
599 = ptrace (PTRACE_PEEKUSER, tid, (PTRACE_TYPE_ARG3) regaddr, 0);
600 regaddr += sizeof (long);
601 if (errno != 0)
602 {
603 char message[128];
604 sprintf (message, "reading register %s (#%d)",
605 gdbarch_register_name (gdbarch, regno), regno);
606 perror_with_name (message);
607 }
608 }
609
610 /* Now supply the register. Keep in mind that the regcache's idea
611 of the register's size may not be a multiple of sizeof
612 (long). */
613 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
614 {
615 /* Little-endian values are always found at the left end of the
616 bytes transferred. */
617 regcache_raw_supply (regcache, regno, buf);
618 }
619 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
620 {
621 /* Big-endian values are found at the right end of the bytes
622 transferred. */
623 size_t padding = (bytes_transferred - register_size (gdbarch, regno));
624 regcache_raw_supply (regcache, regno, buf + padding);
625 }
626 else
627 internal_error (__FILE__, __LINE__,
628 _("fetch_register: unexpected byte order: %d"),
629 gdbarch_byte_order (gdbarch));
630 }
631
632 static void
633 supply_vsxregset (struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
634 {
635 int i;
636 struct gdbarch *gdbarch = get_regcache_arch (regcache);
637 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
638 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
639
640 for (i = 0; i < ppc_num_vshrs; i++)
641 {
642 regcache_raw_supply (regcache, tdep->ppc_vsr0_upper_regnum + i,
643 *vsxregsetp + i * vsxregsize);
644 }
645 }
646
647 static void
648 supply_vrregset (struct regcache *regcache, gdb_vrregset_t *vrregsetp)
649 {
650 int i;
651 struct gdbarch *gdbarch = get_regcache_arch (regcache);
652 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
653 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
654 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
655 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
656
657 for (i = 0; i < num_of_vrregs; i++)
658 {
659 /* The last 2 registers of this set are only 32 bit long, not
660 128. However an offset is necessary only for VSCR because it
661 occupies a whole vector, while VRSAVE occupies a full 4 bytes
662 slot. */
663 if (i == (num_of_vrregs - 2))
664 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
665 *vrregsetp + i * vrregsize + offset);
666 else
667 regcache_raw_supply (regcache, tdep->ppc_vr0_regnum + i,
668 *vrregsetp + i * vrregsize);
669 }
670 }
671
672 static void
673 fetch_vsx_registers (struct regcache *regcache, int tid)
674 {
675 int ret;
676 gdb_vsxregset_t regs;
677
678 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
679 if (ret < 0)
680 {
681 if (errno == EIO)
682 {
683 have_ptrace_getsetvsxregs = 0;
684 return;
685 }
686 perror_with_name (_("Unable to fetch VSX registers"));
687 }
688 supply_vsxregset (regcache, &regs);
689 }
690
691 static void
692 fetch_altivec_registers (struct regcache *regcache, int tid)
693 {
694 int ret;
695 gdb_vrregset_t regs;
696
697 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
698 if (ret < 0)
699 {
700 if (errno == EIO)
701 {
702 have_ptrace_getvrregs = 0;
703 return;
704 }
705 perror_with_name (_("Unable to fetch AltiVec registers"));
706 }
707 supply_vrregset (regcache, &regs);
708 }
709
710 /* This function actually issues the request to ptrace, telling
711 it to get all general-purpose registers and put them into the
712 specified regset.
713
714 If the ptrace request does not exist, this function returns 0
715 and properly sets the have_ptrace_* flag. If the request fails,
716 this function calls perror_with_name. Otherwise, if the request
717 succeeds, then the regcache gets filled and 1 is returned. */
718 static int
719 fetch_all_gp_regs (struct regcache *regcache, int tid)
720 {
721 struct gdbarch *gdbarch = get_regcache_arch (regcache);
722 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
723 gdb_gregset_t gregset;
724
725 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
726 {
727 if (errno == EIO)
728 {
729 have_ptrace_getsetregs = 0;
730 return 0;
731 }
732 perror_with_name (_("Couldn't get general-purpose registers."));
733 }
734
735 supply_gregset (regcache, (const gdb_gregset_t *) &gregset);
736
737 return 1;
738 }
739
740 /* This is a wrapper for the fetch_all_gp_regs function. It is
741 responsible for verifying if this target has the ptrace request
742 that can be used to fetch all general-purpose registers at one
743 shot. If it doesn't, then we should fetch them using the
744 old-fashioned way, which is to iterate over the registers and
745 request them one by one. */
746 static void
747 fetch_gp_regs (struct regcache *regcache, int tid)
748 {
749 struct gdbarch *gdbarch = get_regcache_arch (regcache);
750 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
751 int i;
752
753 if (have_ptrace_getsetregs)
754 if (fetch_all_gp_regs (regcache, tid))
755 return;
756
757 /* If we've hit this point, it doesn't really matter which
758 architecture we are using. We just need to read the
759 registers in the "old-fashioned way". */
760 for (i = 0; i < ppc_num_gprs; i++)
761 fetch_register (regcache, tid, tdep->ppc_gp0_regnum + i);
762 }
763
764 /* This function actually issues the request to ptrace, telling
765 it to get all floating-point registers and put them into the
766 specified regset.
767
768 If the ptrace request does not exist, this function returns 0
769 and properly sets the have_ptrace_* flag. If the request fails,
770 this function calls perror_with_name. Otherwise, if the request
771 succeeds, then the regcache gets filled and 1 is returned. */
772 static int
773 fetch_all_fp_regs (struct regcache *regcache, int tid)
774 {
775 gdb_fpregset_t fpregs;
776
777 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
778 {
779 if (errno == EIO)
780 {
781 have_ptrace_getsetfpregs = 0;
782 return 0;
783 }
784 perror_with_name (_("Couldn't get floating-point registers."));
785 }
786
787 supply_fpregset (regcache, (const gdb_fpregset_t *) &fpregs);
788
789 return 1;
790 }
791
792 /* This is a wrapper for the fetch_all_fp_regs function. It is
793 responsible for verifying if this target has the ptrace request
794 that can be used to fetch all floating-point registers at one
795 shot. If it doesn't, then we should fetch them using the
796 old-fashioned way, which is to iterate over the registers and
797 request them one by one. */
798 static void
799 fetch_fp_regs (struct regcache *regcache, int tid)
800 {
801 struct gdbarch *gdbarch = get_regcache_arch (regcache);
802 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
803 int i;
804
805 if (have_ptrace_getsetfpregs)
806 if (fetch_all_fp_regs (regcache, tid))
807 return;
808
809 /* If we've hit this point, it doesn't really matter which
810 architecture we are using. We just need to read the
811 registers in the "old-fashioned way". */
812 for (i = 0; i < ppc_num_fprs; i++)
813 fetch_register (regcache, tid, tdep->ppc_fp0_regnum + i);
814 }
815
816 static void
817 fetch_ppc_registers (struct regcache *regcache, int tid)
818 {
819 int i;
820 struct gdbarch *gdbarch = get_regcache_arch (regcache);
821 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
822
823 fetch_gp_regs (regcache, tid);
824 if (tdep->ppc_fp0_regnum >= 0)
825 fetch_fp_regs (regcache, tid);
826 fetch_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
827 if (tdep->ppc_ps_regnum != -1)
828 fetch_register (regcache, tid, tdep->ppc_ps_regnum);
829 if (tdep->ppc_cr_regnum != -1)
830 fetch_register (regcache, tid, tdep->ppc_cr_regnum);
831 if (tdep->ppc_lr_regnum != -1)
832 fetch_register (regcache, tid, tdep->ppc_lr_regnum);
833 if (tdep->ppc_ctr_regnum != -1)
834 fetch_register (regcache, tid, tdep->ppc_ctr_regnum);
835 if (tdep->ppc_xer_regnum != -1)
836 fetch_register (regcache, tid, tdep->ppc_xer_regnum);
837 if (tdep->ppc_mq_regnum != -1)
838 fetch_register (regcache, tid, tdep->ppc_mq_regnum);
839 if (ppc_linux_trap_reg_p (gdbarch))
840 {
841 fetch_register (regcache, tid, PPC_ORIG_R3_REGNUM);
842 fetch_register (regcache, tid, PPC_TRAP_REGNUM);
843 }
844 if (tdep->ppc_fpscr_regnum != -1)
845 fetch_register (regcache, tid, tdep->ppc_fpscr_regnum);
846 if (have_ptrace_getvrregs)
847 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
848 fetch_altivec_registers (regcache, tid);
849 if (have_ptrace_getsetvsxregs)
850 if (tdep->ppc_vsr0_upper_regnum != -1)
851 fetch_vsx_registers (regcache, tid);
852 if (tdep->ppc_ev0_upper_regnum >= 0)
853 fetch_spe_register (regcache, tid, -1);
854 }
855
856 /* Fetch registers from the child process. Fetch all registers if
857 regno == -1, otherwise fetch all general registers or all floating
858 point registers depending upon the value of regno. */
859 static void
860 ppc_linux_fetch_inferior_registers (struct target_ops *ops,
861 struct regcache *regcache, int regno)
862 {
863 /* Overload thread id onto process id. */
864 int tid = TIDGET (inferior_ptid);
865
866 /* No thread id, just use process id. */
867 if (tid == 0)
868 tid = PIDGET (inferior_ptid);
869
870 if (regno == -1)
871 fetch_ppc_registers (regcache, tid);
872 else
873 fetch_register (regcache, tid, regno);
874 }
875
876 /* Store one VSX register. */
877 static void
878 store_vsx_register (const struct regcache *regcache, int tid, int regno)
879 {
880 int ret;
881 gdb_vsxregset_t regs;
882 struct gdbarch *gdbarch = get_regcache_arch (regcache);
883 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
884 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
885
886 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
887 if (ret < 0)
888 {
889 if (errno == EIO)
890 {
891 have_ptrace_getsetvsxregs = 0;
892 return;
893 }
894 perror_with_name (_("Unable to fetch VSX register"));
895 }
896
897 regcache_raw_collect (regcache, regno, regs +
898 (regno - tdep->ppc_vsr0_upper_regnum) * vsxregsize);
899
900 ret = ptrace (PTRACE_SETVSXREGS, tid, 0, &regs);
901 if (ret < 0)
902 perror_with_name (_("Unable to store VSX register"));
903 }
904
905 /* Store one register. */
906 static void
907 store_altivec_register (const struct regcache *regcache, int tid, int regno)
908 {
909 int ret;
910 int offset = 0;
911 gdb_vrregset_t regs;
912 struct gdbarch *gdbarch = get_regcache_arch (regcache);
913 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
914 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
915
916 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
917 if (ret < 0)
918 {
919 if (errno == EIO)
920 {
921 have_ptrace_getvrregs = 0;
922 return;
923 }
924 perror_with_name (_("Unable to fetch AltiVec register"));
925 }
926
927 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
928 long on the hardware. */
929 if (regno == (tdep->ppc_vrsave_regnum - 1))
930 offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
931
932 regcache_raw_collect (regcache, regno,
933 regs + (regno
934 - tdep->ppc_vr0_regnum) * vrregsize + offset);
935
936 ret = ptrace (PTRACE_SETVRREGS, tid, 0, &regs);
937 if (ret < 0)
938 perror_with_name (_("Unable to store AltiVec register"));
939 }
940
941 /* Assuming TID referrs to an SPE process, set the top halves of TID's
942 general-purpose registers and its SPE-specific registers to the
943 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
944 nothing.
945
946 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
947 PTRACE_SETEVRREGS requests are supported is isolated here, and in
948 get_spe_registers. */
949 static void
950 set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
951 {
952 if (have_ptrace_getsetevrregs)
953 {
954 if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
955 return;
956 else
957 {
958 /* EIO means that the PTRACE_SETEVRREGS request isn't
959 supported; we fail silently, and don't try the call
960 again. */
961 if (errno == EIO)
962 have_ptrace_getsetevrregs = 0;
963 else
964 /* Anything else needs to be reported. */
965 perror_with_name (_("Unable to set SPE registers"));
966 }
967 }
968 }
969
970 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
971 If REGNO is -1, write the values of all the SPE-specific
972 registers. */
973 static void
974 store_spe_register (const struct regcache *regcache, int tid, int regno)
975 {
976 struct gdbarch *gdbarch = get_regcache_arch (regcache);
977 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
978 struct gdb_evrregset_t evrregs;
979
980 gdb_assert (sizeof (evrregs.evr[0])
981 == register_size (gdbarch, tdep->ppc_ev0_upper_regnum));
982 gdb_assert (sizeof (evrregs.acc)
983 == register_size (gdbarch, tdep->ppc_acc_regnum));
984 gdb_assert (sizeof (evrregs.spefscr)
985 == register_size (gdbarch, tdep->ppc_spefscr_regnum));
986
987 if (regno == -1)
988 /* Since we're going to write out every register, the code below
989 should store to every field of evrregs; if that doesn't happen,
990 make it obvious by initializing it with suspicious values. */
991 memset (&evrregs, 42, sizeof (evrregs));
992 else
993 /* We can only read and write the entire EVR register set at a
994 time, so to write just a single register, we do a
995 read-modify-write maneuver. */
996 get_spe_registers (tid, &evrregs);
997
998 if (regno == -1)
999 {
1000 int i;
1001
1002 for (i = 0; i < ppc_num_gprs; i++)
1003 regcache_raw_collect (regcache,
1004 tdep->ppc_ev0_upper_regnum + i,
1005 &evrregs.evr[i]);
1006 }
1007 else if (tdep->ppc_ev0_upper_regnum <= regno
1008 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
1009 regcache_raw_collect (regcache, regno,
1010 &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
1011
1012 if (regno == -1
1013 || regno == tdep->ppc_acc_regnum)
1014 regcache_raw_collect (regcache,
1015 tdep->ppc_acc_regnum,
1016 &evrregs.acc);
1017
1018 if (regno == -1
1019 || regno == tdep->ppc_spefscr_regnum)
1020 regcache_raw_collect (regcache,
1021 tdep->ppc_spefscr_regnum,
1022 &evrregs.spefscr);
1023
1024 /* Write back the modified register set. */
1025 set_spe_registers (tid, &evrregs);
1026 }
1027
1028 static void
1029 store_register (const struct regcache *regcache, int tid, int regno)
1030 {
1031 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1032 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1033 /* This isn't really an address. But ptrace thinks of it as one. */
1034 CORE_ADDR regaddr = ppc_register_u_addr (gdbarch, regno);
1035 int i;
1036 size_t bytes_to_transfer;
1037 char buf[MAX_REGISTER_SIZE];
1038
1039 if (altivec_register_p (gdbarch, regno))
1040 {
1041 store_altivec_register (regcache, tid, regno);
1042 return;
1043 }
1044 if (vsx_register_p (gdbarch, regno))
1045 {
1046 store_vsx_register (regcache, tid, regno);
1047 return;
1048 }
1049 else if (spe_register_p (gdbarch, regno))
1050 {
1051 store_spe_register (regcache, tid, regno);
1052 return;
1053 }
1054
1055 if (regaddr == -1)
1056 return;
1057
1058 /* First collect the register. Keep in mind that the regcache's
1059 idea of the register's size may not be a multiple of sizeof
1060 (long). */
1061 memset (buf, 0, sizeof buf);
1062 bytes_to_transfer = align_up (register_size (gdbarch, regno), sizeof (long));
1063 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1064 {
1065 /* Little-endian values always sit at the left end of the buffer. */
1066 regcache_raw_collect (regcache, regno, buf);
1067 }
1068 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1069 {
1070 /* Big-endian values sit at the right end of the buffer. */
1071 size_t padding = (bytes_to_transfer - register_size (gdbarch, regno));
1072 regcache_raw_collect (regcache, regno, buf + padding);
1073 }
1074
1075 for (i = 0; i < bytes_to_transfer; i += sizeof (long))
1076 {
1077 errno = 0;
1078 ptrace (PTRACE_POKEUSER, tid, (PTRACE_TYPE_ARG3) regaddr,
1079 *(long *) &buf[i]);
1080 regaddr += sizeof (long);
1081
1082 if (errno == EIO
1083 && (regno == tdep->ppc_fpscr_regnum
1084 || regno == PPC_ORIG_R3_REGNUM
1085 || regno == PPC_TRAP_REGNUM))
1086 {
1087 /* Some older kernel versions don't allow fpscr, orig_r3
1088 or trap to be written. */
1089 continue;
1090 }
1091
1092 if (errno != 0)
1093 {
1094 char message[128];
1095 sprintf (message, "writing register %s (#%d)",
1096 gdbarch_register_name (gdbarch, regno), regno);
1097 perror_with_name (message);
1098 }
1099 }
1100 }
1101
1102 static void
1103 fill_vsxregset (const struct regcache *regcache, gdb_vsxregset_t *vsxregsetp)
1104 {
1105 int i;
1106 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1107 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1108 int vsxregsize = register_size (gdbarch, tdep->ppc_vsr0_upper_regnum);
1109
1110 for (i = 0; i < ppc_num_vshrs; i++)
1111 regcache_raw_collect (regcache, tdep->ppc_vsr0_upper_regnum + i,
1112 *vsxregsetp + i * vsxregsize);
1113 }
1114
1115 static void
1116 fill_vrregset (const struct regcache *regcache, gdb_vrregset_t *vrregsetp)
1117 {
1118 int i;
1119 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1120 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1121 int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
1122 int vrregsize = register_size (gdbarch, tdep->ppc_vr0_regnum);
1123 int offset = vrregsize - register_size (gdbarch, tdep->ppc_vrsave_regnum);
1124
1125 for (i = 0; i < num_of_vrregs; i++)
1126 {
1127 /* The last 2 registers of this set are only 32 bit long, not
1128 128, but only VSCR is fetched as a 16 bytes quantity. */
1129 if (i == (num_of_vrregs - 2))
1130 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1131 *vrregsetp + i * vrregsize + offset);
1132 else
1133 regcache_raw_collect (regcache, tdep->ppc_vr0_regnum + i,
1134 *vrregsetp + i * vrregsize);
1135 }
1136 }
1137
1138 static void
1139 store_vsx_registers (const struct regcache *regcache, int tid)
1140 {
1141 int ret;
1142 gdb_vsxregset_t regs;
1143
1144 ret = ptrace (PTRACE_GETVSXREGS, tid, 0, &regs);
1145 if (ret < 0)
1146 {
1147 if (errno == EIO)
1148 {
1149 have_ptrace_getsetvsxregs = 0;
1150 return;
1151 }
1152 perror_with_name (_("Couldn't get VSX registers"));
1153 }
1154
1155 fill_vsxregset (regcache, &regs);
1156
1157 if (ptrace (PTRACE_SETVSXREGS, tid, 0, &regs) < 0)
1158 perror_with_name (_("Couldn't write VSX registers"));
1159 }
1160
1161 static void
1162 store_altivec_registers (const struct regcache *regcache, int tid)
1163 {
1164 int ret;
1165 gdb_vrregset_t regs;
1166
1167 ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
1168 if (ret < 0)
1169 {
1170 if (errno == EIO)
1171 {
1172 have_ptrace_getvrregs = 0;
1173 return;
1174 }
1175 perror_with_name (_("Couldn't get AltiVec registers"));
1176 }
1177
1178 fill_vrregset (regcache, &regs);
1179
1180 if (ptrace (PTRACE_SETVRREGS, tid, 0, &regs) < 0)
1181 perror_with_name (_("Couldn't write AltiVec registers"));
1182 }
1183
1184 /* This function actually issues the request to ptrace, telling
1185 it to store all general-purpose registers present in the specified
1186 regset.
1187
1188 If the ptrace request does not exist, this function returns 0
1189 and properly sets the have_ptrace_* flag. If the request fails,
1190 this function calls perror_with_name. Otherwise, if the request
1191 succeeds, then the regcache is stored and 1 is returned. */
1192 static int
1193 store_all_gp_regs (const struct regcache *regcache, int tid, int regno)
1194 {
1195 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1196 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1197 gdb_gregset_t gregset;
1198
1199 if (ptrace (PTRACE_GETREGS, tid, 0, (void *) &gregset) < 0)
1200 {
1201 if (errno == EIO)
1202 {
1203 have_ptrace_getsetregs = 0;
1204 return 0;
1205 }
1206 perror_with_name (_("Couldn't get general-purpose registers."));
1207 }
1208
1209 fill_gregset (regcache, &gregset, regno);
1210
1211 if (ptrace (PTRACE_SETREGS, tid, 0, (void *) &gregset) < 0)
1212 {
1213 if (errno == EIO)
1214 {
1215 have_ptrace_getsetregs = 0;
1216 return 0;
1217 }
1218 perror_with_name (_("Couldn't set general-purpose registers."));
1219 }
1220
1221 return 1;
1222 }
1223
1224 /* This is a wrapper for the store_all_gp_regs function. It is
1225 responsible for verifying if this target has the ptrace request
1226 that can be used to store all general-purpose registers at one
1227 shot. If it doesn't, then we should store them using the
1228 old-fashioned way, which is to iterate over the registers and
1229 store them one by one. */
1230 static void
1231 store_gp_regs (const struct regcache *regcache, int tid, int regno)
1232 {
1233 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1234 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1235 int i;
1236
1237 if (have_ptrace_getsetregs)
1238 if (store_all_gp_regs (regcache, tid, regno))
1239 return;
1240
1241 /* If we hit this point, it doesn't really matter which
1242 architecture we are using. We just need to store the
1243 registers in the "old-fashioned way". */
1244 for (i = 0; i < ppc_num_gprs; i++)
1245 store_register (regcache, tid, tdep->ppc_gp0_regnum + i);
1246 }
1247
1248 /* This function actually issues the request to ptrace, telling
1249 it to store all floating-point registers present in the specified
1250 regset.
1251
1252 If the ptrace request does not exist, this function returns 0
1253 and properly sets the have_ptrace_* flag. If the request fails,
1254 this function calls perror_with_name. Otherwise, if the request
1255 succeeds, then the regcache is stored and 1 is returned. */
1256 static int
1257 store_all_fp_regs (const struct regcache *regcache, int tid, int regno)
1258 {
1259 gdb_fpregset_t fpregs;
1260
1261 if (ptrace (PTRACE_GETFPREGS, tid, 0, (void *) &fpregs) < 0)
1262 {
1263 if (errno == EIO)
1264 {
1265 have_ptrace_getsetfpregs = 0;
1266 return 0;
1267 }
1268 perror_with_name (_("Couldn't get floating-point registers."));
1269 }
1270
1271 fill_fpregset (regcache, &fpregs, regno);
1272
1273 if (ptrace (PTRACE_SETFPREGS, tid, 0, (void *) &fpregs) < 0)
1274 {
1275 if (errno == EIO)
1276 {
1277 have_ptrace_getsetfpregs = 0;
1278 return 0;
1279 }
1280 perror_with_name (_("Couldn't set floating-point registers."));
1281 }
1282
1283 return 1;
1284 }
1285
1286 /* This is a wrapper for the store_all_fp_regs function. It is
1287 responsible for verifying if this target has the ptrace request
1288 that can be used to store all floating-point registers at one
1289 shot. If it doesn't, then we should store them using the
1290 old-fashioned way, which is to iterate over the registers and
1291 store them one by one. */
1292 static void
1293 store_fp_regs (const struct regcache *regcache, int tid, int regno)
1294 {
1295 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1296 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1297 int i;
1298
1299 if (have_ptrace_getsetfpregs)
1300 if (store_all_fp_regs (regcache, tid, regno))
1301 return;
1302
1303 /* If we hit this point, it doesn't really matter which
1304 architecture we are using. We just need to store the
1305 registers in the "old-fashioned way". */
1306 for (i = 0; i < ppc_num_fprs; i++)
1307 store_register (regcache, tid, tdep->ppc_fp0_regnum + i);
1308 }
1309
1310 static void
1311 store_ppc_registers (const struct regcache *regcache, int tid)
1312 {
1313 int i;
1314 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1315 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1316
1317 store_gp_regs (regcache, tid, -1);
1318 if (tdep->ppc_fp0_regnum >= 0)
1319 store_fp_regs (regcache, tid, -1);
1320 store_register (regcache, tid, gdbarch_pc_regnum (gdbarch));
1321 if (tdep->ppc_ps_regnum != -1)
1322 store_register (regcache, tid, tdep->ppc_ps_regnum);
1323 if (tdep->ppc_cr_regnum != -1)
1324 store_register (regcache, tid, tdep->ppc_cr_regnum);
1325 if (tdep->ppc_lr_regnum != -1)
1326 store_register (regcache, tid, tdep->ppc_lr_regnum);
1327 if (tdep->ppc_ctr_regnum != -1)
1328 store_register (regcache, tid, tdep->ppc_ctr_regnum);
1329 if (tdep->ppc_xer_regnum != -1)
1330 store_register (regcache, tid, tdep->ppc_xer_regnum);
1331 if (tdep->ppc_mq_regnum != -1)
1332 store_register (regcache, tid, tdep->ppc_mq_regnum);
1333 if (tdep->ppc_fpscr_regnum != -1)
1334 store_register (regcache, tid, tdep->ppc_fpscr_regnum);
1335 if (ppc_linux_trap_reg_p (gdbarch))
1336 {
1337 store_register (regcache, tid, PPC_ORIG_R3_REGNUM);
1338 store_register (regcache, tid, PPC_TRAP_REGNUM);
1339 }
1340 if (have_ptrace_getvrregs)
1341 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
1342 store_altivec_registers (regcache, tid);
1343 if (have_ptrace_getsetvsxregs)
1344 if (tdep->ppc_vsr0_upper_regnum != -1)
1345 store_vsx_registers (regcache, tid);
1346 if (tdep->ppc_ev0_upper_regnum >= 0)
1347 store_spe_register (regcache, tid, -1);
1348 }
1349
1350 /* Fetch the AT_HWCAP entry from the aux vector. */
1351 unsigned long ppc_linux_get_hwcap (void)
1352 {
1353 CORE_ADDR field;
1354
1355 if (target_auxv_search (&current_target, AT_HWCAP, &field))
1356 return (unsigned long) field;
1357
1358 return 0;
1359 }
1360
1361 /* The cached DABR value, to install in new threads.
1362 This variable is used when we are dealing with non-BookE
1363 processors. */
1364 static long saved_dabr_value;
1365
1366 /* Global structure that will store information about the available
1367 features on this BookE processor. */
1368 static struct ppc_debug_info booke_debug_info;
1369
1370 /* Global variable that holds the maximum number of slots that the
1371 kernel will use. This is only used when the processor is BookE. */
1372 static size_t max_slots_number = 0;
1373
1374 struct hw_break_tuple
1375 {
1376 long slot;
1377 struct ppc_hw_breakpoint *hw_break;
1378 };
1379
1380 /* This is an internal VEC created to store information about *points inserted
1381 for each thread. This is used for BookE processors. */
1382 typedef struct thread_points
1383 {
1384 /* The TID to which this *point relates. */
1385 int tid;
1386 /* Information about the *point, such as its address, type, etc.
1387
1388 Each element inside this vector corresponds to a hardware
1389 breakpoint or watchpoint in the thread represented by TID. The maximum
1390 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1391 the tuple is NULL, then the position in the vector is free. */
1392 struct hw_break_tuple *hw_breaks;
1393 } *thread_points_p;
1394 DEF_VEC_P (thread_points_p);
1395
1396 VEC(thread_points_p) *ppc_threads = NULL;
1397
1398 /* The version of the kernel interface that we will use if the processor is
1399 BookE. */
1400 #define PPC_DEBUG_CURRENT_VERSION 1
1401
1402 /* Returns non-zero if we support the ptrace interface which enables
1403 booke debugging resources. */
1404 static int
1405 have_ptrace_booke_interface (void)
1406 {
1407 static int have_ptrace_booke_interface = -1;
1408
1409 if (have_ptrace_booke_interface == -1)
1410 {
1411 int tid;
1412
1413 tid = TIDGET (inferior_ptid);
1414 if (tid == 0)
1415 tid = PIDGET (inferior_ptid);
1416
1417 /* Check for kernel support for BOOKE debug registers. */
1418 if (ptrace (PPC_PTRACE_GETHWDBGINFO, tid, 0, &booke_debug_info) >= 0)
1419 {
1420 have_ptrace_booke_interface = 1;
1421 max_slots_number = booke_debug_info.num_instruction_bps
1422 + booke_debug_info.num_data_bps
1423 + booke_debug_info.num_condition_regs;
1424 }
1425 else
1426 {
1427 /* Old school interface and no BOOKE debug registers support. */
1428 have_ptrace_booke_interface = 0;
1429 memset (&booke_debug_info, 0, sizeof (struct ppc_debug_info));
1430 }
1431 }
1432
1433 return have_ptrace_booke_interface;
1434 }
1435
1436 static int
1437 ppc_linux_can_use_hw_breakpoint (int type, int cnt, int ot)
1438 {
1439 int total_hw_wp, total_hw_bp;
1440
1441 if (have_ptrace_booke_interface ())
1442 {
1443 /* For PPC BookE processors, the number of available hardware
1444 watchpoints and breakpoints is stored at the booke_debug_info
1445 struct. */
1446 total_hw_bp = booke_debug_info.num_instruction_bps;
1447 total_hw_wp = booke_debug_info.num_data_bps;
1448 }
1449 else
1450 {
1451 /* For PPC server processors, we accept 1 hardware watchpoint and 0
1452 hardware breakpoints. */
1453 total_hw_bp = 0;
1454 total_hw_wp = 1;
1455 }
1456
1457 if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
1458 || type == bp_access_watchpoint || type == bp_watchpoint)
1459 {
1460 if (cnt > total_hw_wp)
1461 return -1;
1462 }
1463 else if (type == bp_hardware_breakpoint)
1464 {
1465 if (cnt > total_hw_bp)
1466 return -1;
1467 }
1468
1469 if (!have_ptrace_booke_interface ())
1470 {
1471 int tid;
1472 ptid_t ptid = inferior_ptid;
1473
1474 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1475 and whether the target has DABR. If either answer is no, the
1476 ptrace call will return -1. Fail in that case. */
1477 tid = TIDGET (ptid);
1478 if (tid == 0)
1479 tid = PIDGET (ptid);
1480
1481 if (ptrace (PTRACE_SET_DEBUGREG, tid, 0, 0) == -1)
1482 return 0;
1483 }
1484
1485 return 1;
1486 }
1487
1488 static int
1489 ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
1490 {
1491 /* Handle sub-8-byte quantities. */
1492 if (len <= 0)
1493 return 0;
1494
1495 /* The new BookE ptrace interface tells if there are alignment restrictions
1496 for watchpoints in the processors. In that case, we use that information
1497 to determine the hardcoded watchable region for watchpoints. */
1498 if (have_ptrace_booke_interface ())
1499 {
1500 if (booke_debug_info.data_bp_alignment
1501 && (addr + len > (addr & ~(booke_debug_info.data_bp_alignment - 1))
1502 + booke_debug_info.data_bp_alignment))
1503 return 0;
1504 }
1505 /* addr+len must fall in the 8 byte watchable region for DABR-based
1506 processors (i.e., server processors). Without the new BookE ptrace
1507 interface, DAC-based processors (i.e., embedded processors) will use
1508 addresses aligned to 4-bytes due to the way the read/write flags are
1509 passed in the old ptrace interface. */
1510 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1511 && (addr + len) > (addr & ~3) + 4)
1512 || (addr + len) > (addr & ~7) + 8)
1513 return 0;
1514
1515 return 1;
1516 }
1517
1518 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1519 static int
1520 booke_cmp_hw_point (struct ppc_hw_breakpoint *a, struct ppc_hw_breakpoint *b)
1521 {
1522 return (a->trigger_type == b->trigger_type
1523 && a->addr_mode == b->addr_mode
1524 && a->condition_mode == b->condition_mode
1525 && a->addr == b->addr
1526 && a->addr2 == b->addr2
1527 && a->condition_value == b->condition_value);
1528 }
1529
1530 /* This function can be used to retrieve a thread_points by the TID of the
1531 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1532 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1533 provided TID will be created and returned. */
1534 static struct thread_points *
1535 booke_find_thread_points_by_tid (int tid, int alloc_new)
1536 {
1537 int i;
1538 struct thread_points *t;
1539
1540 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, t); i++)
1541 if (t->tid == tid)
1542 return t;
1543
1544 t = NULL;
1545
1546 /* Do we need to allocate a new point_item
1547 if the wanted one does not exist? */
1548 if (alloc_new)
1549 {
1550 t = xmalloc (sizeof (struct thread_points));
1551 t->hw_breaks
1552 = xzalloc (max_slots_number * sizeof (struct hw_break_tuple));
1553 t->tid = tid;
1554 VEC_safe_push (thread_points_p, ppc_threads, t);
1555 }
1556
1557 return t;
1558 }
1559
1560 /* This function is a generic wrapper that is responsible for inserting a
1561 *point (i.e., calling `ptrace' in order to issue the request to the
1562 kernel) and registering it internally in GDB. */
1563 static void
1564 booke_insert_point (struct ppc_hw_breakpoint *b, int tid)
1565 {
1566 int i;
1567 long slot;
1568 struct ppc_hw_breakpoint *p = xmalloc (sizeof (struct ppc_hw_breakpoint));
1569 struct hw_break_tuple *hw_breaks;
1570 struct cleanup *c = make_cleanup (xfree, p);
1571 struct thread_points *t;
1572 struct hw_break_tuple *tuple;
1573
1574 memcpy (p, b, sizeof (struct ppc_hw_breakpoint));
1575
1576 errno = 0;
1577 slot = ptrace (PPC_PTRACE_SETHWDEBUG, tid, 0, p);
1578 if (slot < 0)
1579 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1580
1581 /* Everything went fine, so we have to register this *point. */
1582 t = booke_find_thread_points_by_tid (tid, 1);
1583 gdb_assert (t != NULL);
1584 hw_breaks = t->hw_breaks;
1585
1586 /* Find a free element in the hw_breaks vector. */
1587 for (i = 0; i < max_slots_number; i++)
1588 if (hw_breaks[i].hw_break == NULL)
1589 {
1590 hw_breaks[i].slot = slot;
1591 hw_breaks[i].hw_break = p;
1592 break;
1593 }
1594
1595 gdb_assert (i != max_slots_number);
1596
1597 discard_cleanups (c);
1598 }
1599
1600 /* This function is a generic wrapper that is responsible for removing a
1601 *point (i.e., calling `ptrace' in order to issue the request to the
1602 kernel), and unregistering it internally at GDB. */
1603 static void
1604 booke_remove_point (struct ppc_hw_breakpoint *b, int tid)
1605 {
1606 int i;
1607 struct hw_break_tuple *hw_breaks;
1608 struct thread_points *t;
1609
1610 t = booke_find_thread_points_by_tid (tid, 0);
1611 gdb_assert (t != NULL);
1612 hw_breaks = t->hw_breaks;
1613
1614 for (i = 0; i < max_slots_number; i++)
1615 if (hw_breaks[i].hw_break && booke_cmp_hw_point (hw_breaks[i].hw_break, b))
1616 break;
1617
1618 gdb_assert (i != max_slots_number);
1619
1620 /* We have to ignore ENOENT errors because the kernel implements hardware
1621 breakpoints/watchpoints as "one-shot", that is, they are automatically
1622 deleted when hit. */
1623 errno = 0;
1624 if (ptrace (PPC_PTRACE_DELHWDEBUG, tid, 0, hw_breaks[i].slot) < 0)
1625 if (errno != ENOENT)
1626 perror_with_name (_("Unexpected error deleting "
1627 "breakpoint or watchpoint"));
1628
1629 xfree (hw_breaks[i].hw_break);
1630 hw_breaks[i].hw_break = NULL;
1631 }
1632
1633 static int
1634 ppc_linux_insert_hw_breakpoint (struct gdbarch *gdbarch,
1635 struct bp_target_info *bp_tgt)
1636 {
1637 ptid_t ptid;
1638 struct lwp_info *lp;
1639 struct ppc_hw_breakpoint p;
1640
1641 if (!have_ptrace_booke_interface ())
1642 return -1;
1643
1644 p.version = PPC_DEBUG_CURRENT_VERSION;
1645 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1646 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1647 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1648 p.addr = (uint64_t) bp_tgt->placed_address;
1649 p.addr2 = 0;
1650 p.condition_value = 0;
1651
1652 ALL_LWPS (lp, ptid)
1653 booke_insert_point (&p, TIDGET (ptid));
1654
1655 return 0;
1656 }
1657
1658 static int
1659 ppc_linux_remove_hw_breakpoint (struct gdbarch *gdbarch,
1660 struct bp_target_info *bp_tgt)
1661 {
1662 ptid_t ptid;
1663 struct lwp_info *lp;
1664 struct ppc_hw_breakpoint p;
1665
1666 if (!have_ptrace_booke_interface ())
1667 return -1;
1668
1669 p.version = PPC_DEBUG_CURRENT_VERSION;
1670 p.trigger_type = PPC_BREAKPOINT_TRIGGER_EXECUTE;
1671 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1672 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1673 p.addr = (uint64_t) bp_tgt->placed_address;
1674 p.addr2 = 0;
1675 p.condition_value = 0;
1676
1677 ALL_LWPS (lp, ptid)
1678 booke_remove_point (&p, TIDGET (ptid));
1679
1680 return 0;
1681 }
1682
1683 static int
1684 get_trigger_type (int rw)
1685 {
1686 int t;
1687
1688 if (rw == hw_read)
1689 t = PPC_BREAKPOINT_TRIGGER_READ;
1690 else if (rw == hw_write)
1691 t = PPC_BREAKPOINT_TRIGGER_WRITE;
1692 else
1693 t = PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE;
1694
1695 return t;
1696 }
1697
1698 /* Check whether we have at least one free DVC register. */
1699 static int
1700 can_use_watchpoint_cond_accel (void)
1701 {
1702 struct thread_points *p;
1703 int tid = TIDGET (inferior_ptid);
1704 int cnt = booke_debug_info.num_condition_regs, i;
1705 CORE_ADDR tmp_value;
1706
1707 if (!have_ptrace_booke_interface () || cnt == 0)
1708 return 0;
1709
1710 p = booke_find_thread_points_by_tid (tid, 0);
1711
1712 if (p)
1713 {
1714 for (i = 0; i < max_slots_number; i++)
1715 if (p->hw_breaks[i].hw_break != NULL
1716 && (p->hw_breaks[i].hw_break->condition_mode
1717 != PPC_BREAKPOINT_CONDITION_NONE))
1718 cnt--;
1719
1720 /* There are no available slots now. */
1721 if (cnt <= 0)
1722 return 0;
1723 }
1724
1725 return 1;
1726 }
1727
1728 /* Calculate the enable bits and the contents of the Data Value Compare
1729 debug register present in BookE processors.
1730
1731 ADDR is the address to be watched, LEN is the length of watched data
1732 and DATA_VALUE is the value which will trigger the watchpoint.
1733 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1734 CONDITION_VALUE will hold the value which should be put in the
1735 DVC register. */
1736 static void
1737 calculate_dvc (CORE_ADDR addr, int len, CORE_ADDR data_value,
1738 uint32_t *condition_mode, uint64_t *condition_value)
1739 {
1740 int i, num_byte_enable, align_offset, num_bytes_off_dvc,
1741 rightmost_enabled_byte;
1742 CORE_ADDR addr_end_data, addr_end_dvc;
1743
1744 /* The DVC register compares bytes within fixed-length windows which
1745 are word-aligned, with length equal to that of the DVC register.
1746 We need to calculate where our watch region is relative to that
1747 window and enable comparison of the bytes which fall within it. */
1748
1749 align_offset = addr % booke_debug_info.sizeof_condition;
1750 addr_end_data = addr + len;
1751 addr_end_dvc = (addr - align_offset
1752 + booke_debug_info.sizeof_condition);
1753 num_bytes_off_dvc = (addr_end_data > addr_end_dvc)?
1754 addr_end_data - addr_end_dvc : 0;
1755 num_byte_enable = len - num_bytes_off_dvc;
1756 /* Here, bytes are numbered from right to left. */
1757 rightmost_enabled_byte = (addr_end_data < addr_end_dvc)?
1758 addr_end_dvc - addr_end_data : 0;
1759
1760 *condition_mode = PPC_BREAKPOINT_CONDITION_AND;
1761 for (i = 0; i < num_byte_enable; i++)
1762 *condition_mode
1763 |= PPC_BREAKPOINT_CONDITION_BE (i + rightmost_enabled_byte);
1764
1765 /* Now we need to match the position within the DVC of the comparison
1766 value with where the watch region is relative to the window
1767 (i.e., the ALIGN_OFFSET). */
1768
1769 *condition_value = ((uint64_t) data_value >> num_bytes_off_dvc * 8
1770 << rightmost_enabled_byte * 8);
1771 }
1772
1773 /* Return the number of memory locations that need to be accessed to
1774 evaluate the expression which generated the given value chain.
1775 Returns -1 if there's any register access involved, or if there are
1776 other kinds of values which are not acceptable in a condition
1777 expression (e.g., lval_computed or lval_internalvar). */
1778 static int
1779 num_memory_accesses (struct value *v)
1780 {
1781 int found_memory_cnt = 0;
1782 struct value *head = v;
1783
1784 /* The idea here is that evaluating an expression generates a series
1785 of values, one holding the value of every subexpression. (The
1786 expression a*b+c has five subexpressions: a, b, a*b, c, and
1787 a*b+c.) GDB's values hold almost enough information to establish
1788 the criteria given above --- they identify memory lvalues,
1789 register lvalues, computed values, etcetera. So we can evaluate
1790 the expression, and then scan the chain of values that leaves
1791 behind to determine the memory locations involved in the evaluation
1792 of an expression.
1793
1794 However, I don't think that the values returned by inferior
1795 function calls are special in any way. So this function may not
1796 notice that an expression contains an inferior function call.
1797 FIXME. */
1798
1799 for (; v; v = value_next (v))
1800 {
1801 /* Constants and values from the history are fine. */
1802 if (VALUE_LVAL (v) == not_lval || deprecated_value_modifiable (v) == 0)
1803 continue;
1804 else if (VALUE_LVAL (v) == lval_memory)
1805 {
1806 /* A lazy memory lvalue is one that GDB never needed to fetch;
1807 we either just used its address (e.g., `a' in `a.b') or
1808 we never needed it at all (e.g., `a' in `a,b'). */
1809 if (!value_lazy (v))
1810 found_memory_cnt++;
1811 }
1812 /* Other kinds of values are not fine. */
1813 else
1814 return -1;
1815 }
1816
1817 return found_memory_cnt;
1818 }
1819
1820 /* Verifies whether the expression COND can be implemented using the
1821 DVC (Data Value Compare) register in BookE processors. The expression
1822 must test the watch value for equality with a constant expression.
1823 If the function returns 1, DATA_VALUE will contain the constant against
1824 which the watch value should be compared. */
1825 static int
1826 check_condition (CORE_ADDR watch_addr, struct expression *cond,
1827 CORE_ADDR *data_value)
1828 {
1829 int pc = 1, num_accesses_left, num_accesses_right;
1830 struct value *left_val, *right_val, *left_chain, *right_chain;
1831
1832 if (cond->elts[0].opcode != BINOP_EQUAL)
1833 return 0;
1834
1835 fetch_subexp_value (cond, &pc, &left_val, NULL, &left_chain);
1836 num_accesses_left = num_memory_accesses (left_chain);
1837
1838 if (left_val == NULL || num_accesses_left < 0)
1839 {
1840 free_value_chain (left_chain);
1841
1842 return 0;
1843 }
1844
1845 fetch_subexp_value (cond, &pc, &right_val, NULL, &right_chain);
1846 num_accesses_right = num_memory_accesses (right_chain);
1847
1848 if (right_val == NULL || num_accesses_right < 0)
1849 {
1850 free_value_chain (left_chain);
1851 free_value_chain (right_chain);
1852
1853 return 0;
1854 }
1855
1856 if (num_accesses_left == 1 && num_accesses_right == 0
1857 && VALUE_LVAL (left_val) == lval_memory
1858 && value_address (left_val) == watch_addr)
1859 *data_value = value_as_long (right_val);
1860 else if (num_accesses_left == 0 && num_accesses_right == 1
1861 && VALUE_LVAL (right_val) == lval_memory
1862 && value_address (right_val) == watch_addr)
1863 *data_value = value_as_long (left_val);
1864 else
1865 {
1866 free_value_chain (left_chain);
1867 free_value_chain (right_chain);
1868
1869 return 0;
1870 }
1871
1872 free_value_chain (left_chain);
1873 free_value_chain (right_chain);
1874
1875 return 1;
1876 }
1877
1878 /* Return non-zero if the target is capable of using hardware to evaluate
1879 the condition expression, thus only triggering the watchpoint when it is
1880 true. */
1881 static int
1882 ppc_linux_can_accel_watchpoint_condition (CORE_ADDR addr, int len, int rw,
1883 struct expression *cond)
1884 {
1885 CORE_ADDR data_value;
1886
1887 return (have_ptrace_booke_interface ()
1888 && booke_debug_info.num_condition_regs > 0
1889 && check_condition (addr, cond, &data_value));
1890 }
1891
1892 static int
1893 ppc_linux_insert_watchpoint (CORE_ADDR addr, int len, int rw,
1894 struct expression *cond)
1895 {
1896 struct lwp_info *lp;
1897 ptid_t ptid;
1898 int ret = -1;
1899
1900 if (have_ptrace_booke_interface ())
1901 {
1902 struct ppc_hw_breakpoint p;
1903 CORE_ADDR data_value;
1904
1905 if (cond && can_use_watchpoint_cond_accel ()
1906 && check_condition (addr, cond, &data_value))
1907 calculate_dvc (addr, len, data_value, &p.condition_mode,
1908 &p.condition_value);
1909 else
1910 {
1911 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1912 p.condition_value = 0;
1913 }
1914
1915 p.version = PPC_DEBUG_CURRENT_VERSION;
1916 p.trigger_type = get_trigger_type (rw);
1917 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
1918 p.addr = (uint64_t) addr;
1919 p.addr2 = 0;
1920
1921 ALL_LWPS (lp, ptid)
1922 booke_insert_point (&p, TIDGET (ptid));
1923
1924 ret = 0;
1925 }
1926 else
1927 {
1928 long dabr_value;
1929 long read_mode, write_mode;
1930
1931 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
1932 {
1933 /* PowerPC 440 requires only the read/write flags to be passed
1934 to the kernel. */
1935 read_mode = 1;
1936 write_mode = 2;
1937 }
1938 else
1939 {
1940 /* PowerPC 970 and other DABR-based processors are required to pass
1941 the Breakpoint Translation bit together with the flags. */
1942 read_mode = 5;
1943 write_mode = 6;
1944 }
1945
1946 dabr_value = addr & ~(read_mode | write_mode);
1947 switch (rw)
1948 {
1949 case hw_read:
1950 /* Set read and translate bits. */
1951 dabr_value |= read_mode;
1952 break;
1953 case hw_write:
1954 /* Set write and translate bits. */
1955 dabr_value |= write_mode;
1956 break;
1957 case hw_access:
1958 /* Set read, write and translate bits. */
1959 dabr_value |= read_mode | write_mode;
1960 break;
1961 }
1962
1963 saved_dabr_value = dabr_value;
1964
1965 ALL_LWPS (lp, ptid)
1966 if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0,
1967 saved_dabr_value) < 0)
1968 return -1;
1969
1970 ret = 0;
1971 }
1972
1973 return ret;
1974 }
1975
1976 static int
1977 ppc_linux_remove_watchpoint (CORE_ADDR addr, int len, int rw,
1978 struct expression *cond)
1979 {
1980 struct lwp_info *lp;
1981 ptid_t ptid;
1982 int ret = -1;
1983
1984 if (have_ptrace_booke_interface ())
1985 {
1986 struct ppc_hw_breakpoint p;
1987 CORE_ADDR data_value;
1988
1989 if (cond && booke_debug_info.num_condition_regs > 0
1990 && check_condition (addr, cond, &data_value))
1991 calculate_dvc (addr, len, data_value, &p.condition_mode,
1992 &p.condition_value);
1993 else
1994 {
1995 p.condition_mode = PPC_BREAKPOINT_CONDITION_NONE;
1996 p.condition_value = 0;
1997 }
1998
1999 p.version = PPC_DEBUG_CURRENT_VERSION;
2000 p.trigger_type = get_trigger_type (rw);
2001 p.addr_mode = PPC_BREAKPOINT_MODE_EXACT;
2002 p.addr = (uint64_t) addr;
2003 p.addr2 = 0;
2004
2005 ALL_LWPS (lp, ptid)
2006 booke_remove_point (&p, TIDGET (ptid));
2007
2008 ret = 0;
2009 }
2010 else
2011 {
2012 saved_dabr_value = 0;
2013 ALL_LWPS (lp, ptid)
2014 if (ptrace (PTRACE_SET_DEBUGREG, TIDGET (ptid), 0,
2015 saved_dabr_value) < 0)
2016 return -1;
2017
2018 ret = 0;
2019 }
2020
2021 return ret;
2022 }
2023
2024 static void
2025 ppc_linux_new_thread (ptid_t ptid)
2026 {
2027 int tid = TIDGET (ptid);
2028
2029 if (have_ptrace_booke_interface ())
2030 {
2031 int i;
2032 struct thread_points *p;
2033 struct hw_break_tuple *hw_breaks;
2034
2035 if (VEC_empty (thread_points_p, ppc_threads))
2036 return;
2037
2038 /* Get a list of breakpoints from any thread. */
2039 p = VEC_last (thread_points_p, ppc_threads);
2040 hw_breaks = p->hw_breaks;
2041
2042 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2043 for (i = 0; i < max_slots_number; i++)
2044 if (hw_breaks[i].hw_break)
2045 booke_insert_point (hw_breaks[i].hw_break, tid);
2046 }
2047 else
2048 ptrace (PTRACE_SET_DEBUGREG, tid, 0, saved_dabr_value);
2049 }
2050
2051 static void
2052 ppc_linux_thread_exit (struct thread_info *tp, int silent)
2053 {
2054 int i;
2055 int tid = TIDGET (tp->ptid);
2056 struct hw_break_tuple *hw_breaks;
2057 struct thread_points *t = NULL, *p;
2058
2059 if (!have_ptrace_booke_interface ())
2060 return;
2061
2062 for (i = 0; VEC_iterate (thread_points_p, ppc_threads, i, p); i++)
2063 if (p->tid == tid)
2064 {
2065 t = p;
2066 break;
2067 }
2068
2069 if (t == NULL)
2070 return;
2071
2072 VEC_unordered_remove (thread_points_p, ppc_threads, i);
2073
2074 hw_breaks = t->hw_breaks;
2075
2076 for (i = 0; i < max_slots_number; i++)
2077 if (hw_breaks[i].hw_break)
2078 xfree (hw_breaks[i].hw_break);
2079
2080 xfree (t->hw_breaks);
2081 xfree (t);
2082 }
2083
2084 static int
2085 ppc_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p)
2086 {
2087 struct siginfo *siginfo_p;
2088
2089 siginfo_p = linux_nat_get_siginfo (inferior_ptid);
2090
2091 if (siginfo_p->si_signo != SIGTRAP
2092 || (siginfo_p->si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2093 return 0;
2094
2095 if (have_ptrace_booke_interface ())
2096 {
2097 int i;
2098 struct thread_points *t;
2099 struct hw_break_tuple *hw_breaks;
2100 /* The index (or slot) of the *point is passed in the si_errno field. */
2101 int slot = siginfo_p->si_errno;
2102
2103 t = booke_find_thread_points_by_tid (TIDGET (inferior_ptid), 0);
2104
2105 /* Find out if this *point is a hardware breakpoint.
2106 If so, we should return 0. */
2107 if (t)
2108 {
2109 hw_breaks = t->hw_breaks;
2110 for (i = 0; i < max_slots_number; i++)
2111 if (hw_breaks[i].hw_break && hw_breaks[i].slot == slot
2112 && hw_breaks[i].hw_break->trigger_type
2113 == PPC_BREAKPOINT_TRIGGER_EXECUTE)
2114 return 0;
2115 }
2116 }
2117
2118 *addr_p = (CORE_ADDR) (uintptr_t) siginfo_p->si_addr;
2119 return 1;
2120 }
2121
2122 static int
2123 ppc_linux_stopped_by_watchpoint (void)
2124 {
2125 CORE_ADDR addr;
2126 return ppc_linux_stopped_data_address (&current_target, &addr);
2127 }
2128
2129 static int
2130 ppc_linux_watchpoint_addr_within_range (struct target_ops *target,
2131 CORE_ADDR addr,
2132 CORE_ADDR start, int length)
2133 {
2134 int mask;
2135
2136 if (have_ptrace_booke_interface ()
2137 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2138 return start <= addr && start + length >= addr;
2139 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE)
2140 mask = 3;
2141 else
2142 mask = 7;
2143
2144 addr &= ~mask;
2145
2146 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2147 return start <= addr + mask && start + length - 1 >= addr;
2148 }
2149
2150 static void
2151 ppc_linux_store_inferior_registers (struct target_ops *ops,
2152 struct regcache *regcache, int regno)
2153 {
2154 /* Overload thread id onto process id. */
2155 int tid = TIDGET (inferior_ptid);
2156
2157 /* No thread id, just use process id. */
2158 if (tid == 0)
2159 tid = PIDGET (inferior_ptid);
2160
2161 if (regno >= 0)
2162 store_register (regcache, tid, regno);
2163 else
2164 store_ppc_registers (regcache, tid);
2165 }
2166
2167 /* Functions for transferring registers between a gregset_t or fpregset_t
2168 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2169 by the ptrace interface, not the current program's ABI. Eg. if a
2170 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2171 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2172
2173 void
2174 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
2175 {
2176 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2177
2178 ppc_supply_gregset (regset, regcache, -1, gregsetp, sizeof (*gregsetp));
2179 }
2180
2181 void
2182 fill_gregset (const struct regcache *regcache,
2183 gdb_gregset_t *gregsetp, int regno)
2184 {
2185 const struct regset *regset = ppc_linux_gregset (sizeof (long));
2186
2187 if (regno == -1)
2188 memset (gregsetp, 0, sizeof (*gregsetp));
2189 ppc_collect_gregset (regset, regcache, regno, gregsetp, sizeof (*gregsetp));
2190 }
2191
2192 void
2193 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t * fpregsetp)
2194 {
2195 const struct regset *regset = ppc_linux_fpregset ();
2196
2197 ppc_supply_fpregset (regset, regcache, -1,
2198 fpregsetp, sizeof (*fpregsetp));
2199 }
2200
2201 void
2202 fill_fpregset (const struct regcache *regcache,
2203 gdb_fpregset_t *fpregsetp, int regno)
2204 {
2205 const struct regset *regset = ppc_linux_fpregset ();
2206
2207 ppc_collect_fpregset (regset, regcache, regno,
2208 fpregsetp, sizeof (*fpregsetp));
2209 }
2210
2211 static int
2212 ppc_linux_target_wordsize (void)
2213 {
2214 int wordsize = 4;
2215
2216 /* Check for 64-bit inferior process. This is the case when the host is
2217 64-bit, and in addition the top bit of the MSR register is set. */
2218 #ifdef __powerpc64__
2219 long msr;
2220
2221 int tid = TIDGET (inferior_ptid);
2222 if (tid == 0)
2223 tid = PIDGET (inferior_ptid);
2224
2225 errno = 0;
2226 msr = (long) ptrace (PTRACE_PEEKUSER, tid, PT_MSR * 8, 0);
2227 if (errno == 0 && msr < 0)
2228 wordsize = 8;
2229 #endif
2230
2231 return wordsize;
2232 }
2233
2234 static int
2235 ppc_linux_auxv_parse (struct target_ops *ops, gdb_byte **readptr,
2236 gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp)
2237 {
2238 int sizeof_auxv_field = ppc_linux_target_wordsize ();
2239 enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch);
2240 gdb_byte *ptr = *readptr;
2241
2242 if (endptr == ptr)
2243 return 0;
2244
2245 if (endptr - ptr < sizeof_auxv_field * 2)
2246 return -1;
2247
2248 *typep = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2249 ptr += sizeof_auxv_field;
2250 *valp = extract_unsigned_integer (ptr, sizeof_auxv_field, byte_order);
2251 ptr += sizeof_auxv_field;
2252
2253 *readptr = ptr;
2254 return 1;
2255 }
2256
2257 static const struct target_desc *
2258 ppc_linux_read_description (struct target_ops *ops)
2259 {
2260 int altivec = 0;
2261 int vsx = 0;
2262 int isa205 = 0;
2263 int cell = 0;
2264
2265 int tid = TIDGET (inferior_ptid);
2266 if (tid == 0)
2267 tid = PIDGET (inferior_ptid);
2268
2269 if (have_ptrace_getsetevrregs)
2270 {
2271 struct gdb_evrregset_t evrregset;
2272
2273 if (ptrace (PTRACE_GETEVRREGS, tid, 0, &evrregset) >= 0)
2274 return tdesc_powerpc_e500l;
2275
2276 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2277 Anything else needs to be reported. */
2278 else if (errno != EIO)
2279 perror_with_name (_("Unable to fetch SPE registers"));
2280 }
2281
2282 if (have_ptrace_getsetvsxregs)
2283 {
2284 gdb_vsxregset_t vsxregset;
2285
2286 if (ptrace (PTRACE_GETVSXREGS, tid, 0, &vsxregset) >= 0)
2287 vsx = 1;
2288
2289 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2290 Anything else needs to be reported. */
2291 else if (errno != EIO)
2292 perror_with_name (_("Unable to fetch VSX registers"));
2293 }
2294
2295 if (have_ptrace_getvrregs)
2296 {
2297 gdb_vrregset_t vrregset;
2298
2299 if (ptrace (PTRACE_GETVRREGS, tid, 0, &vrregset) >= 0)
2300 altivec = 1;
2301
2302 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2303 Anything else needs to be reported. */
2304 else if (errno != EIO)
2305 perror_with_name (_("Unable to fetch AltiVec registers"));
2306 }
2307
2308 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2309 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2310 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2311 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2312 half of the register are for Decimal Floating Point, we check if that
2313 feature is available to decide the size of the FPSCR. */
2314 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP)
2315 isa205 = 1;
2316
2317 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL)
2318 cell = 1;
2319
2320 if (ppc_linux_target_wordsize () == 8)
2321 {
2322 if (cell)
2323 return tdesc_powerpc_cell64l;
2324 else if (vsx)
2325 return isa205? tdesc_powerpc_isa205_vsx64l : tdesc_powerpc_vsx64l;
2326 else if (altivec)
2327 return isa205
2328 ? tdesc_powerpc_isa205_altivec64l : tdesc_powerpc_altivec64l;
2329
2330 return isa205? tdesc_powerpc_isa205_64l : tdesc_powerpc_64l;
2331 }
2332
2333 if (cell)
2334 return tdesc_powerpc_cell32l;
2335 else if (vsx)
2336 return isa205? tdesc_powerpc_isa205_vsx32l : tdesc_powerpc_vsx32l;
2337 else if (altivec)
2338 return isa205? tdesc_powerpc_isa205_altivec32l : tdesc_powerpc_altivec32l;
2339
2340 return isa205? tdesc_powerpc_isa205_32l : tdesc_powerpc_32l;
2341 }
2342
2343 void _initialize_ppc_linux_nat (void);
2344
2345 void
2346 _initialize_ppc_linux_nat (void)
2347 {
2348 struct target_ops *t;
2349
2350 /* Fill in the generic GNU/Linux methods. */
2351 t = linux_target ();
2352
2353 /* Add our register access methods. */
2354 t->to_fetch_registers = ppc_linux_fetch_inferior_registers;
2355 t->to_store_registers = ppc_linux_store_inferior_registers;
2356
2357 /* Add our breakpoint/watchpoint methods. */
2358 t->to_can_use_hw_breakpoint = ppc_linux_can_use_hw_breakpoint;
2359 t->to_insert_hw_breakpoint = ppc_linux_insert_hw_breakpoint;
2360 t->to_remove_hw_breakpoint = ppc_linux_remove_hw_breakpoint;
2361 t->to_region_ok_for_hw_watchpoint = ppc_linux_region_ok_for_hw_watchpoint;
2362 t->to_insert_watchpoint = ppc_linux_insert_watchpoint;
2363 t->to_remove_watchpoint = ppc_linux_remove_watchpoint;
2364 t->to_stopped_by_watchpoint = ppc_linux_stopped_by_watchpoint;
2365 t->to_stopped_data_address = ppc_linux_stopped_data_address;
2366 t->to_watchpoint_addr_within_range = ppc_linux_watchpoint_addr_within_range;
2367 t->to_can_accel_watchpoint_condition
2368 = ppc_linux_can_accel_watchpoint_condition;
2369
2370 t->to_read_description = ppc_linux_read_description;
2371 t->to_auxv_parse = ppc_linux_auxv_parse;
2372
2373 observer_attach_thread_exit (ppc_linux_thread_exit);
2374
2375 /* Register the target. */
2376 linux_nat_add_target (t);
2377 linux_nat_set_new_thread (t, ppc_linux_new_thread);
2378 }
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