gdb/ppc-linux-nat.c

   1 /* PPC GNU/Linux native support.
   2
   3    Copyright 1988, 1989, 1991, 1992, 1994, 1996, 2000, 2001, 2002,
   4    2003 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 59 Temple Place - Suite 330,
  21    Boston, MA 02111-1307, USA.  */
  22
  23 #include "defs.h"
  24 #include "gdb_string.h"
  25 #include "frame.h"
  26 #include "inferior.h"
  27 #include "gdbcore.h"
  28 #include "regcache.h"
  29 #include "gdb_assert.h"
  30
  31 #include <sys/types.h>
  32 #include <sys/param.h>
  33 #include <signal.h>
  34 #include <sys/user.h>
  35 #include <sys/ioctl.h>
  36 #include "gdb_wait.h"
  37 #include <fcntl.h>
  38 #include <sys/procfs.h>
  39 #include <sys/ptrace.h>
  40
  41 /* Prototypes for supply_gregset etc. */
  42 #include "gregset.h"
  43 #include "ppc-tdep.h"
  44
  45 #ifndef PT_READ_U
  46 #define PT_READ_U PTRACE_PEEKUSR
  47 #endif
  48 #ifndef PT_WRITE_U
  49 #define PT_WRITE_U PTRACE_POKEUSR
  50 #endif
  51
  52 /* Default the type of the ptrace transfer to int.  */
  53 #ifndef PTRACE_XFER_TYPE
  54 #define PTRACE_XFER_TYPE int
  55 #endif
  56
  57 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
  58    configure time check.  Some older glibc's (for instance 2.2.1)
  59    don't have a specific powerpc version of ptrace.h, and fall back on
  60    a generic one.  In such cases, sys/ptrace.h defines
  61    PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
  62    ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
  63    PTRACE_SETVRREGS to be.  This also makes a configury check pretty
  64    much useless.  */
  65
  66 /* These definitions should really come from the glibc header files,
  67    but Glibc doesn't know about the vrregs yet.  */
  68 #ifndef PTRACE_GETVRREGS
  69 #define PTRACE_GETVRREGS 18
  70 #define PTRACE_SETVRREGS 19
  71 #endif
  72
  73
  74 /* Similarly for the ptrace requests for getting / setting the SPE
  75    registers (ev0 -- ev31, acc, and spefscr).  See the description of
  76    gdb_evrregset_t for details.  */
  77 #ifndef PTRACE_GETEVRREGS
  78 #define PTRACE_GETEVRREGS 20
  79 #define PTRACE_SETEVRREGS 21
  80 #endif
  81
  82
  83 /* This oddity is because the Linux kernel defines elf_vrregset_t as
  84    an array of 33 16 bytes long elements.  I.e. it leaves out vrsave.
  85    However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
  86    the vrsave as an extra 4 bytes at the end.  I opted for creating a
  87    flat array of chars, so that it is easier to manipulate for gdb.
  88
  89    There are 32 vector registers 16 bytes longs, plus a VSCR register
  90    which is only 4 bytes long, but is fetched as a 16 bytes
  91    quantity. Up to here we have the elf_vrregset_t structure.
  92    Appended to this there is space for the VRSAVE register: 4 bytes.
  93    Even though this vrsave register is not included in the regset
  94    typedef, it is handled by the ptrace requests.
  95
  96    Note that GNU/Linux doesn't support little endian PPC hardware,
  97    therefore the offset at which the real value of the VSCR register
  98    is located will be always 12 bytes.
  99
 100    The layout is like this (where x is the actual value of the vscr reg): */
 101
 102 /* *INDENT-OFF* */
 103 /*
 104    |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
 105    <------->     <-------><-------><->
 106      VR0           VR31     VSCR    VRSAVE
 107 */
 108 /* *INDENT-ON* */
 109
 110 #define SIZEOF_VRREGS 33*16+4
 111
 112 typedef char gdb_vrregset_t[SIZEOF_VRREGS];
 113
 114
 115 /* On PPC processors that support the the Signal Processing Extension
 116    (SPE) APU, the general-purpose registers are 64 bits long.
 117    However, the ordinary Linux kernel PTRACE_PEEKUSR / PTRACE_POKEUSR
 118    / PT_READ_U / PT_WRITE_U ptrace calls only access the lower half of
 119    each register, to allow them to behave the same way they do on
 120    non-SPE systems.  There's a separate pair of calls,
 121    PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that read and write the top
 122    halves of all the general-purpose registers at once, along with
 123    some SPE-specific registers.
 124
 125    GDB itself continues to claim the general-purpose registers are 32
 126    bits long.  It has unnamed raw registers that hold the upper halves
 127    of the gprs, and the the full 64-bit SIMD views of the registers,
 128    'ev0' -- 'ev31', are pseudo-registers that splice the top and
 129    bottom halves together.
 130
 131    This is the structure filled in by PTRACE_GETEVRREGS and written to
 132    the inferior's registers by PTRACE_SETEVRREGS.  */
 133 struct gdb_evrregset_t
 134 {
 135   unsigned long evr[32];
 136   unsigned long long acc;
 137   unsigned long spefscr;
 138 };
 139
 140
 141 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
 142    PTRACE_SETVRREGS requests, for reading and writing the Altivec
 143    registers.  Zero if we've tried one of them and gotten an
 144    error.  */
 145 int have_ptrace_getvrregs = 1;
 146
 147
 148 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
 149    PTRACE_SETEVRREGS requests, for reading and writing the SPE
 150    registers.  Zero if we've tried one of them and gotten an
 151    error.  */
 152 int have_ptrace_getsetevrregs = 1;
 153
 154
 155 int
 156 kernel_u_size (void)
 157 {
 158   return (sizeof (struct user));
 159 }
 160
 161 /* *INDENT-OFF* */
 162 /* registers layout, as presented by the ptrace interface:
 163 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
 164 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
 165 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
 166 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
 167 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6, PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
 168 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22, PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
 169 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38, PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
 170 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54, PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
 171 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
 172 /* *INDENT_ON * */
 173
 174 static int
 175 ppc_register_u_addr (int regno)
 176 {
 177   int u_addr = -1;
 178   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 179   /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
 180      interface, and not the wordsize of the program's ABI.  */
 181   int wordsize = sizeof (PTRACE_XFER_TYPE);
 182
 183   /* General purpose registers occupy 1 slot each in the buffer */
 184   if (regno >= tdep->ppc_gp0_regnum
 185       && regno < tdep->ppc_gp0_regnum + ppc_num_gprs)
 186     u_addr = ((regno - tdep->ppc_gp0_regnum + PT_R0) * wordsize);
 187
 188   /* Floating point regs: eight bytes each in both 32- and 64-bit
 189      ptrace interfaces.  Thus, two slots each in 32-bit interface, one
 190      slot each in 64-bit interface.  */
 191   if (tdep->ppc_fp0_regnum >= 0
 192       && regno >= tdep->ppc_fp0_regnum
 193       && regno < tdep->ppc_fp0_regnum + ppc_num_fprs)
 194     u_addr = (PT_FPR0 * wordsize) + ((regno - tdep->ppc_fp0_regnum) * 8);
 195
 196   /* UISA special purpose registers: 1 slot each */
 197   if (regno == PC_REGNUM)
 198     u_addr = PT_NIP * wordsize;
 199   if (regno == tdep->ppc_lr_regnum)
 200     u_addr = PT_LNK * wordsize;
 201   if (regno == tdep->ppc_cr_regnum)
 202     u_addr = PT_CCR * wordsize;
 203   if (regno == tdep->ppc_xer_regnum)
 204     u_addr = PT_XER * wordsize;
 205   if (regno == tdep->ppc_ctr_regnum)
 206     u_addr = PT_CTR * wordsize;
 207 #ifdef PT_MQ
 208   if (regno == tdep->ppc_mq_regnum)
 209     u_addr = PT_MQ * wordsize;
 210 #endif
 211   if (regno == tdep->ppc_ps_regnum)
 212     u_addr = PT_MSR * wordsize;
 213   if (tdep->ppc_fpscr_regnum >= 0
 214       && regno == tdep->ppc_fpscr_regnum)
 215     u_addr = PT_FPSCR * wordsize;
 216
 217   return u_addr;
 218 }
 219
 220 /* The Linux kernel ptrace interface for AltiVec registers uses the
 221    registers set mechanism, as opposed to the interface for all the
 222    other registers, that stores/fetches each register individually.  */
 223 static void
 224 fetch_altivec_register (int tid, int regno)
 225 {
 226   int ret;
 227   int offset = 0;
 228   gdb_vrregset_t regs;
 229   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 230   int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
 231
 232   ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
 233   if (ret < 0)
 234     {
 235       if (errno == EIO)
 236         {
 237           have_ptrace_getvrregs = 0;
 238           return;
 239         }
 240       perror_with_name ("Unable to fetch AltiVec register");
 241     }
 242
 243   /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
 244      long on the hardware.  We deal only with the lower 4 bytes of the
 245      vector.  VRSAVE is at the end of the array in a 4 bytes slot, so
 246      there is no need to define an offset for it.  */
 247   if (regno == (tdep->ppc_vrsave_regnum - 1))
 248     offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
 249
 250   regcache_raw_supply (current_regcache, regno,
 251                        regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
 252 }
 253
 254 /* Fetch the top 32 bits of TID's general-purpose registers and the
 255    SPE-specific registers, and place the results in EVRREGSET.  If we
 256    don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
 257    zeros.
 258
 259    All the logic to deal with whether or not the PTRACE_GETEVRREGS and
 260    PTRACE_SETEVRREGS requests are supported is isolated here, and in
 261    set_spe_registers.  */
 262 static void
 263 get_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
 264 {
 265   if (have_ptrace_getsetevrregs)
 266     {
 267       if (ptrace (PTRACE_GETEVRREGS, tid, 0, evrregset) >= 0)
 268         return;
 269       else
 270         {
 271           /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
 272              we just return zeros.  */
 273           if (errno == EIO)
 274             have_ptrace_getsetevrregs = 0;
 275           else
 276             /* Anything else needs to be reported.  */
 277             perror_with_name ("Unable to fetch SPE registers");
 278         }
 279     }
 280
 281   memset (evrregset, 0, sizeof (*evrregset));
 282 }
 283
 284 /* Supply values from TID for SPE-specific raw registers: the upper
 285    halves of the GPRs, the accumulator, and the spefscr.  REGNO must
 286    be the number of an upper half register, acc, spefscr, or -1 to
 287    supply the values of all registers.  */
 288 static void
 289 fetch_spe_register (int tid, int regno)
 290 {
 291   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 292   struct gdb_evrregset_t evrregs;
 293
 294   gdb_assert (sizeof (evrregs.evr[0])
 295               == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum));
 296   gdb_assert (sizeof (evrregs.acc)
 297               == register_size (current_gdbarch, tdep->ppc_acc_regnum));
 298   gdb_assert (sizeof (evrregs.spefscr)
 299               == register_size (current_gdbarch, tdep->ppc_spefscr_regnum));
 300
 301   get_spe_registers (tid, &evrregs);
 302
 303   if (regno == -1)
 304     {
 305       int i;
 306
 307       for (i = 0; i < ppc_num_gprs; i++)
 308         regcache_raw_supply (current_regcache, tdep->ppc_ev0_upper_regnum + i,
 309                              &evrregs.evr[i]);
 310     }
 311   else if (tdep->ppc_ev0_upper_regnum <= regno
 312            && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
 313     regcache_raw_supply (current_regcache, regno,
 314                          &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
 315
 316   if (regno == -1
 317       || regno == tdep->ppc_acc_regnum)
 318     regcache_raw_supply (current_regcache, tdep->ppc_acc_regnum, &evrregs.acc);
 319
 320   if (regno == -1
 321       || regno == tdep->ppc_spefscr_regnum)
 322     regcache_raw_supply (current_regcache, tdep->ppc_spefscr_regnum,
 323                          &evrregs.spefscr);
 324 }
 325
 326 static void
 327 fetch_register (int tid, int regno)
 328 {
 329   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 330   /* This isn't really an address.  But ptrace thinks of it as one.  */
 331   CORE_ADDR regaddr = ppc_register_u_addr (regno);
 332   int bytes_transferred;
 333   unsigned int offset;         /* Offset of registers within the u area. */
 334   char buf[MAX_REGISTER_SIZE];
 335
 336   if (altivec_register_p (regno))
 337     {
 338       /* If this is the first time through, or if it is not the first
 339          time through, and we have comfirmed that there is kernel
 340          support for such a ptrace request, then go and fetch the
 341          register.  */
 342       if (have_ptrace_getvrregs)
 343        {
 344          fetch_altivec_register (tid, regno);
 345          return;
 346        }
 347      /* If we have discovered that there is no ptrace support for
 348         AltiVec registers, fall through and return zeroes, because
 349         regaddr will be -1 in this case.  */
 350     }
 351   else if (spe_register_p (regno))
 352     {
 353       fetch_spe_register (tid, regno);
 354       return;
 355     }
 356
 357   if (regaddr == -1)
 358     {
 359       memset (buf, '\0', register_size (current_gdbarch, regno));   /* Supply zeroes */
 360       regcache_raw_supply (current_regcache, regno, buf);
 361       return;
 362     }
 363
 364   /* Read the raw register using PTRACE_XFER_TYPE sized chunks.  On a
 365      32-bit platform, 64-bit floating-point registers will require two
 366      transfers.  */
 367   for (bytes_transferred = 0;
 368        bytes_transferred < register_size (current_gdbarch, regno);
 369        bytes_transferred += sizeof (PTRACE_XFER_TYPE))
 370     {
 371       errno = 0;
 372       *(PTRACE_XFER_TYPE *) & buf[bytes_transferred]
 373         = ptrace (PT_READ_U, tid, (PTRACE_ARG3_TYPE) regaddr, 0);
 374       regaddr += sizeof (PTRACE_XFER_TYPE);
 375       if (errno != 0)
 376         {
 377           char message[128];
 378           sprintf (message, "reading register %s (#%d)",
 379                    REGISTER_NAME (regno), regno);
 380           perror_with_name (message);
 381         }
 382     }
 383
 384   /* Now supply the register.  Keep in mind that the regcache's idea
 385      of the register's size may not be a multiple of sizeof
 386      (PTRACE_XFER_TYPE).  */
 387   if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
 388     {
 389       /* Little-endian values are always found at the left end of the
 390          bytes transferred.  */
 391       regcache_raw_supply (current_regcache, regno, buf);
 392     }
 393   else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
 394     {
 395       /* Big-endian values are found at the right end of the bytes
 396          transferred.  */
 397       size_t padding = (bytes_transferred
 398                         - register_size (current_gdbarch, regno));
 399       regcache_raw_supply (current_regcache, regno, buf + padding);
 400     }
 401   else
 402     internal_error (__FILE__, __LINE__,
 403                     "fetch_register: unexpected byte order: %d",
 404                     gdbarch_byte_order (current_gdbarch));
 405 }
 406
 407 static void
 408 supply_vrregset (gdb_vrregset_t *vrregsetp)
 409 {
 410   int i;
 411   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 412   int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
 413   int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
 414   int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
 415
 416   for (i = 0; i < num_of_vrregs; i++)
 417     {
 418       /* The last 2 registers of this set are only 32 bit long, not
 419          128.  However an offset is necessary only for VSCR because it
 420          occupies a whole vector, while VRSAVE occupies a full 4 bytes
 421          slot.  */
 422       if (i == (num_of_vrregs - 2))
 423         regcache_raw_supply (current_regcache, tdep->ppc_vr0_regnum + i,
 424                              *vrregsetp + i * vrregsize + offset);
 425       else
 426         regcache_raw_supply (current_regcache, tdep->ppc_vr0_regnum + i,
 427                              *vrregsetp + i * vrregsize);
 428     }
 429 }
 430
 431 static void
 432 fetch_altivec_registers (int tid)
 433 {
 434   int ret;
 435   gdb_vrregset_t regs;
 436
 437   ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
 438   if (ret < 0)
 439     {
 440       if (errno == EIO)
 441         {
 442           have_ptrace_getvrregs = 0;
 443           return;
 444         }
 445       perror_with_name ("Unable to fetch AltiVec registers");
 446     }
 447   supply_vrregset (&regs);
 448 }
 449
 450 static void
 451 fetch_ppc_registers (int tid)
 452 {
 453   int i;
 454   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 455
 456   for (i = 0; i < ppc_num_gprs; i++)
 457     fetch_register (tid, tdep->ppc_gp0_regnum + i);
 458   if (tdep->ppc_fp0_regnum >= 0)
 459     for (i = 0; i < ppc_num_fprs; i++)
 460       fetch_register (tid, tdep->ppc_fp0_regnum + i);
 461   fetch_register (tid, PC_REGNUM);
 462   if (tdep->ppc_ps_regnum != -1)
 463     fetch_register (tid, tdep->ppc_ps_regnum);
 464   if (tdep->ppc_cr_regnum != -1)
 465     fetch_register (tid, tdep->ppc_cr_regnum);
 466   if (tdep->ppc_lr_regnum != -1)
 467     fetch_register (tid, tdep->ppc_lr_regnum);
 468   if (tdep->ppc_ctr_regnum != -1)
 469     fetch_register (tid, tdep->ppc_ctr_regnum);
 470   if (tdep->ppc_xer_regnum != -1)
 471     fetch_register (tid, tdep->ppc_xer_regnum);
 472   if (tdep->ppc_mq_regnum != -1)
 473     fetch_register (tid, tdep->ppc_mq_regnum);
 474   if (tdep->ppc_fpscr_regnum != -1)
 475     fetch_register (tid, tdep->ppc_fpscr_regnum);
 476   if (have_ptrace_getvrregs)
 477     if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
 478       fetch_altivec_registers (tid);
 479   if (tdep->ppc_ev0_upper_regnum >= 0)
 480     fetch_spe_register (tid, -1);
 481 }
 482
 483 /* Fetch registers from the child process.  Fetch all registers if
 484    regno == -1, otherwise fetch all general registers or all floating
 485    point registers depending upon the value of regno.  */
 486 void
 487 fetch_inferior_registers (int regno)
 488 {
 489   /* Overload thread id onto process id */
 490   int tid = TIDGET (inferior_ptid);
 491
 492   /* No thread id, just use process id */
 493   if (tid == 0)
 494     tid = PIDGET (inferior_ptid);
 495
 496   if (regno == -1)
 497     fetch_ppc_registers (tid);
 498   else
 499     fetch_register (tid, regno);
 500 }
 501
 502 /* Store one register. */
 503 static void
 504 store_altivec_register (int tid, int regno)
 505 {
 506   int ret;
 507   int offset = 0;
 508   gdb_vrregset_t regs;
 509   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 510   int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
 511
 512   ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
 513   if (ret < 0)
 514     {
 515       if (errno == EIO)
 516         {
 517           have_ptrace_getvrregs = 0;
 518           return;
 519         }
 520       perror_with_name ("Unable to fetch AltiVec register");
 521     }
 522
 523   /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
 524      long on the hardware.  */
 525   if (regno == (tdep->ppc_vrsave_regnum - 1))
 526     offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
 527
 528   regcache_raw_collect (current_regcache, regno,
 529                         regs + (regno - tdep->ppc_vr0_regnum) * vrregsize + offset);
 530
 531   ret = ptrace (PTRACE_SETVRREGS, tid, 0, &regs);
 532   if (ret < 0)
 533     perror_with_name ("Unable to store AltiVec register");
 534 }
 535
 536 /* Assuming TID referrs to an SPE process, set the top halves of TID's
 537    general-purpose registers and its SPE-specific registers to the
 538    values in EVRREGSET.  If we don't support PTRACE_SETEVRREGS, do
 539    nothing.
 540
 541    All the logic to deal with whether or not the PTRACE_GETEVRREGS and
 542    PTRACE_SETEVRREGS requests are supported is isolated here, and in
 543    get_spe_registers.  */
 544 static void
 545 set_spe_registers (int tid, struct gdb_evrregset_t *evrregset)
 546 {
 547   if (have_ptrace_getsetevrregs)
 548     {
 549       if (ptrace (PTRACE_SETEVRREGS, tid, 0, evrregset) >= 0)
 550         return;
 551       else
 552         {
 553           /* EIO means that the PTRACE_SETEVRREGS request isn't
 554              supported; we fail silently, and don't try the call
 555              again.  */
 556           if (errno == EIO)
 557             have_ptrace_getsetevrregs = 0;
 558           else
 559             /* Anything else needs to be reported.  */
 560             perror_with_name ("Unable to set SPE registers");
 561         }
 562     }
 563 }
 564
 565 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
 566    If REGNO is -1, write the values of all the SPE-specific
 567    registers.  */
 568 static void
 569 store_spe_register (int tid, int regno)
 570 {
 571   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 572   struct gdb_evrregset_t evrregs;
 573
 574   gdb_assert (sizeof (evrregs.evr[0])
 575               == register_size (current_gdbarch, tdep->ppc_ev0_upper_regnum));
 576   gdb_assert (sizeof (evrregs.acc)
 577               == register_size (current_gdbarch, tdep->ppc_acc_regnum));
 578   gdb_assert (sizeof (evrregs.spefscr)
 579               == register_size (current_gdbarch, tdep->ppc_spefscr_regnum));
 580
 581   if (regno == -1)
 582     /* Since we're going to write out every register, the code below
 583        should store to every field of evrregs; if that doesn't happen,
 584        make it obvious by initializing it with suspicious values.  */
 585     memset (&evrregs, 42, sizeof (evrregs));
 586   else
 587     /* We can only read and write the entire EVR register set at a
 588        time, so to write just a single register, we do a
 589        read-modify-write maneuver.  */
 590     get_spe_registers (tid, &evrregs);
 591
 592   if (regno == -1)
 593     {
 594       int i;
 595
 596       for (i = 0; i < ppc_num_gprs; i++)
 597         regcache_raw_collect (current_regcache,
 598                               tdep->ppc_ev0_upper_regnum + i,
 599                               &evrregs.evr[i]);
 600     }
 601   else if (tdep->ppc_ev0_upper_regnum <= regno
 602            && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
 603     regcache_raw_collect (current_regcache, regno,
 604                           &evrregs.evr[regno - tdep->ppc_ev0_upper_regnum]);
 605
 606   if (regno == -1
 607       || regno == tdep->ppc_acc_regnum)
 608     regcache_raw_collect (current_regcache,
 609                           tdep->ppc_acc_regnum,
 610                           &evrregs.acc);
 611
 612   if (regno == -1
 613       || regno == tdep->ppc_spefscr_regnum)
 614     regcache_raw_collect (current_regcache,
 615                           tdep->ppc_spefscr_regnum,
 616                           &evrregs.spefscr);
 617
 618   /* Write back the modified register set.  */
 619   set_spe_registers (tid, &evrregs);
 620 }
 621
 622 static void
 623 store_register (int tid, int regno)
 624 {
 625   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 626   /* This isn't really an address.  But ptrace thinks of it as one.  */
 627   CORE_ADDR regaddr = ppc_register_u_addr (regno);
 628   int i;
 629   size_t bytes_to_transfer;
 630   char buf[MAX_REGISTER_SIZE];
 631
 632   if (altivec_register_p (regno))
 633     {
 634       store_altivec_register (tid, regno);
 635       return;
 636     }
 637   else if (spe_register_p (regno))
 638     {
 639       store_spe_register (tid, regno);
 640       return;
 641     }
 642
 643   if (regaddr == -1)
 644     return;
 645
 646   /* First collect the register.  Keep in mind that the regcache's
 647      idea of the register's size may not be a multiple of sizeof
 648      (PTRACE_XFER_TYPE).  */
 649   memset (buf, 0, sizeof buf);
 650   bytes_to_transfer = align_up (register_size (current_gdbarch, regno),
 651                                 sizeof (PTRACE_XFER_TYPE));
 652   if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
 653     {
 654       /* Little-endian values always sit at the left end of the buffer.  */
 655       regcache_raw_collect (current_regcache, regno, buf);
 656     }
 657   else if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
 658     {
 659       /* Big-endian values sit at the right end of the buffer.  */
 660       size_t padding = (bytes_to_transfer
 661                         - register_size (current_gdbarch, regno));
 662       regcache_raw_collect (current_regcache, regno, buf + padding);
 663     }
 664
 665   for (i = 0; i < bytes_to_transfer; i += sizeof (PTRACE_XFER_TYPE))
 666     {
 667       errno = 0;
 668       ptrace (PT_WRITE_U, tid, (PTRACE_ARG3_TYPE) regaddr,
 669               *(PTRACE_XFER_TYPE *) & buf[i]);
 670       regaddr += sizeof (PTRACE_XFER_TYPE);
 671
 672       if (errno == EIO
 673           && regno == tdep->ppc_fpscr_regnum)
 674         {
 675           /* Some older kernel versions don't allow fpscr to be written.  */
 676           continue;
 677         }
 678
 679       if (errno != 0)
 680         {
 681           char message[128];
 682           sprintf (message, "writing register %s (#%d)",
 683                    REGISTER_NAME (regno), regno);
 684           perror_with_name (message);
 685         }
 686     }
 687 }
 688
 689 static void
 690 fill_vrregset (gdb_vrregset_t *vrregsetp)
 691 {
 692   int i;
 693   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 694   int num_of_vrregs = tdep->ppc_vrsave_regnum - tdep->ppc_vr0_regnum + 1;
 695   int vrregsize = register_size (current_gdbarch, tdep->ppc_vr0_regnum);
 696   int offset = vrregsize - register_size (current_gdbarch, tdep->ppc_vrsave_regnum);
 697
 698   for (i = 0; i < num_of_vrregs; i++)
 699     {
 700       /* The last 2 registers of this set are only 32 bit long, not
 701          128, but only VSCR is fetched as a 16 bytes quantity.  */
 702       if (i == (num_of_vrregs - 2))
 703         regcache_raw_collect (current_regcache, tdep->ppc_vr0_regnum + i,
 704                               *vrregsetp + i * vrregsize + offset);
 705       else
 706         regcache_raw_collect (current_regcache, tdep->ppc_vr0_regnum + i,
 707                               *vrregsetp + i * vrregsize);
 708     }
 709 }
 710
 711 static void
 712 store_altivec_registers (int tid)
 713 {
 714   int ret;
 715   gdb_vrregset_t regs;
 716
 717   ret = ptrace (PTRACE_GETVRREGS, tid, 0, &regs);
 718   if (ret < 0)
 719     {
 720       if (errno == EIO)
 721         {
 722           have_ptrace_getvrregs = 0;
 723           return;
 724         }
 725       perror_with_name ("Couldn't get AltiVec registers");
 726     }
 727
 728   fill_vrregset (&regs);
 729
 730   if (ptrace (PTRACE_SETVRREGS, tid, 0, &regs) < 0)
 731     perror_with_name ("Couldn't write AltiVec registers");
 732 }
 733
 734 static void
 735 store_ppc_registers (int tid)
 736 {
 737   int i;
 738   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 739
 740   for (i = 0; i < ppc_num_gprs; i++)
 741     store_register (tid, tdep->ppc_gp0_regnum + i);
 742   if (tdep->ppc_fp0_regnum >= 0)
 743     for (i = 0; i < ppc_num_fprs; i++)
 744       store_register (tid, tdep->ppc_fp0_regnum + i);
 745   store_register (tid, PC_REGNUM);
 746   if (tdep->ppc_ps_regnum != -1)
 747     store_register (tid, tdep->ppc_ps_regnum);
 748   if (tdep->ppc_cr_regnum != -1)
 749     store_register (tid, tdep->ppc_cr_regnum);
 750   if (tdep->ppc_lr_regnum != -1)
 751     store_register (tid, tdep->ppc_lr_regnum);
 752   if (tdep->ppc_ctr_regnum != -1)
 753     store_register (tid, tdep->ppc_ctr_regnum);
 754   if (tdep->ppc_xer_regnum != -1)
 755     store_register (tid, tdep->ppc_xer_regnum);
 756   if (tdep->ppc_mq_regnum != -1)
 757     store_register (tid, tdep->ppc_mq_regnum);
 758   if (tdep->ppc_fpscr_regnum != -1)
 759     store_register (tid, tdep->ppc_fpscr_regnum);
 760   if (have_ptrace_getvrregs)
 761     if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
 762       store_altivec_registers (tid);
 763   if (tdep->ppc_ev0_upper_regnum >= 0)
 764     store_spe_register (tid, -1);
 765 }
 766
 767 void
 768 store_inferior_registers (int regno)
 769 {
 770   /* Overload thread id onto process id */
 771   int tid = TIDGET (inferior_ptid);
 772
 773   /* No thread id, just use process id */
 774   if (tid == 0)
 775     tid = PIDGET (inferior_ptid);
 776
 777   if (regno >= 0)
 778     store_register (tid, regno);
 779   else
 780     store_ppc_registers (tid);
 781 }
 782
 783 void
 784 supply_gregset (gdb_gregset_t *gregsetp)
 785 {
 786   /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
 787      interface, and not the wordsize of the program's ABI.  */
 788   int wordsize = sizeof (PTRACE_XFER_TYPE);
 789   ppc_linux_supply_gregset (current_regcache, -1, gregsetp,
 790                             sizeof (gdb_gregset_t), wordsize);
 791 }
 792
 793 static void
 794 right_fill_reg (int regnum, void *reg)
 795 {
 796   /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
 797      interface, and not the wordsize of the program's ABI.  */
 798   int wordsize = sizeof (PTRACE_XFER_TYPE);
 799   /* Right fill the register.  */
 800   regcache_raw_collect (current_regcache, regnum,
 801                         ((bfd_byte *) reg
 802                          + wordsize
 803                          - register_size (current_gdbarch, regnum)));
 804 }
 805
 806 void
 807 fill_gregset (gdb_gregset_t *gregsetp, int regno)
 808 {
 809   int regi;
 810   elf_greg_t *regp = (elf_greg_t *) gregsetp;
 811   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 812   const int elf_ngreg = 48;
 813
 814
 815   /* Start with zeros.  */
 816   memset (regp, 0, elf_ngreg * sizeof (*regp));
 817
 818   for (regi = 0; regi < ppc_num_gprs; regi++)
 819     {
 820       if ((regno == -1) || regno == tdep->ppc_gp0_regnum + regi)
 821         right_fill_reg (tdep->ppc_gp0_regnum + regi, (regp + PT_R0 + regi));
 822     }
 823
 824   if ((regno == -1) || regno == PC_REGNUM)
 825     right_fill_reg (PC_REGNUM, regp + PT_NIP);
 826   if ((regno == -1) || regno == tdep->ppc_lr_regnum)
 827     right_fill_reg (tdep->ppc_lr_regnum, regp + PT_LNK);
 828   if ((regno == -1) || regno == tdep->ppc_cr_regnum)
 829     regcache_raw_collect (current_regcache, tdep->ppc_cr_regnum,
 830                           regp + PT_CCR);
 831   if ((regno == -1) || regno == tdep->ppc_xer_regnum)
 832     regcache_raw_collect (current_regcache, tdep->ppc_xer_regnum,
 833                           regp + PT_XER);
 834   if ((regno == -1) || regno == tdep->ppc_ctr_regnum)
 835     right_fill_reg (tdep->ppc_ctr_regnum, regp + PT_CTR);
 836 #ifdef PT_MQ
 837   if (((regno == -1) || regno == tdep->ppc_mq_regnum)
 838       && (tdep->ppc_mq_regnum != -1))
 839     right_fill_reg (tdep->ppc_mq_regnum, regp + PT_MQ);
 840 #endif
 841   if ((regno == -1) || regno == tdep->ppc_ps_regnum)
 842     right_fill_reg (tdep->ppc_ps_regnum, regp + PT_MSR);
 843 }
 844
 845 void
 846 supply_fpregset (gdb_fpregset_t * fpregsetp)
 847 {
 848   ppc_linux_supply_fpregset (NULL, current_regcache, -1, fpregsetp,
 849                              sizeof (gdb_fpregset_t));
 850 }
 851
 852 /* Given a pointer to a floating point register set in /proc format
 853    (fpregset_t *), update the register specified by REGNO from gdb's
 854    idea of the current floating point register set.  If REGNO is -1,
 855    update them all.  */
 856 void
 857 fill_fpregset (gdb_fpregset_t *fpregsetp, int regno)
 858 {
 859   int regi;
 860   struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
 861   bfd_byte *fpp = (void *) fpregsetp;
 862
 863   if (ppc_floating_point_unit_p (current_gdbarch))
 864     {
 865       for (regi = 0; regi < ppc_num_fprs; regi++)
 866         {
 867           if ((regno == -1) || (regno == tdep->ppc_fp0_regnum + regi))
 868             regcache_raw_collect (current_regcache, tdep->ppc_fp0_regnum + regi,
 869                                   fpp + 8 * regi);
 870         }
 871       if (regno == -1 || regno == tdep->ppc_fpscr_regnum)
 872         right_fill_reg (tdep->ppc_fpscr_regnum, (fpp + 8 * 32));
 873     }
 874 }