1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "observable.h"
24 #include "gdbthread.h"
28 #include "linux-nat.h"
29 #include <sys/types.h>
32 #include <sys/ioctl.h>
35 #include <sys/procfs.h>
36 #include "nat/gdb_ptrace.h"
37 #include "inf-ptrace.h"
39 /* Prototypes for supply_gregset etc. */
42 #include "ppc-linux-tdep.h"
44 /* Required when using the AUXV. */
45 #include "elf/common.h"
48 #include "arch/ppc-linux-common.h"
49 #include "arch/ppc-linux-tdesc.h"
50 #include "nat/ppc-linux.h"
52 /* Similarly for the hardware watchpoint support. These requests are used
53 when the PowerPC HWDEBUG ptrace interface is not available. */
54 #ifndef PTRACE_GET_DEBUGREG
55 #define PTRACE_GET_DEBUGREG 25
57 #ifndef PTRACE_SET_DEBUGREG
58 #define PTRACE_SET_DEBUGREG 26
60 #ifndef PTRACE_GETSIGINFO
61 #define PTRACE_GETSIGINFO 0x4202
64 /* These requests are used when the PowerPC HWDEBUG ptrace interface is
65 available. It exposes the debug facilities of PowerPC processors, as well
66 as additional features of BookE processors, such as ranged breakpoints and
67 watchpoints and hardware-accelerated condition evaluation. */
68 #ifndef PPC_PTRACE_GETHWDBGINFO
70 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the PowerPC HWDEBUG
71 ptrace interface is not present in ptrace.h, so we'll have to pretty much
72 include it all here so that the code at least compiles on older systems. */
73 #define PPC_PTRACE_GETHWDBGINFO 0x89
74 #define PPC_PTRACE_SETHWDEBUG 0x88
75 #define PPC_PTRACE_DELHWDEBUG 0x87
79 uint32_t version
; /* Only version 1 exists to date. */
80 uint32_t num_instruction_bps
;
81 uint32_t num_data_bps
;
82 uint32_t num_condition_regs
;
83 uint32_t data_bp_alignment
;
84 uint32_t sizeof_condition
; /* size of the DVC register. */
88 /* Features will have bits indicating whether there is support for: */
89 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
90 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
91 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
92 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
94 struct ppc_hw_breakpoint
96 uint32_t version
; /* currently, version must be 1 */
97 uint32_t trigger_type
; /* only some combinations allowed */
98 uint32_t addr_mode
; /* address match mode */
99 uint32_t condition_mode
; /* break/watchpoint condition flags */
100 uint64_t addr
; /* break/watchpoint address */
101 uint64_t addr2
; /* range end or mask */
102 uint64_t condition_value
; /* contents of the DVC register */
106 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
107 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
108 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
109 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
112 #define PPC_BREAKPOINT_MODE_EXACT 0x0
113 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
114 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
115 #define PPC_BREAKPOINT_MODE_MASK 0x3
117 /* Condition mode. */
118 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
119 #define PPC_BREAKPOINT_CONDITION_AND 0x1
120 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
121 #define PPC_BREAKPOINT_CONDITION_OR 0x2
122 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
123 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
124 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
125 #define PPC_BREAKPOINT_CONDITION_BE(n) \
126 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
127 #endif /* PPC_PTRACE_GETHWDBGINFO */
129 /* Feature defined on Linux kernel v3.9: DAWR interface, that enables wider
130 watchpoint (up to 512 bytes). */
131 #ifndef PPC_DEBUG_FEATURE_DATA_BP_DAWR
132 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x10
133 #endif /* PPC_DEBUG_FEATURE_DATA_BP_DAWR */
135 /* Similarly for the general-purpose (gp0 -- gp31)
136 and floating-point registers (fp0 -- fp31). */
137 #ifndef PTRACE_GETREGS
138 #define PTRACE_GETREGS 12
140 #ifndef PTRACE_SETREGS
141 #define PTRACE_SETREGS 13
143 #ifndef PTRACE_GETFPREGS
144 #define PTRACE_GETFPREGS 14
146 #ifndef PTRACE_SETFPREGS
147 #define PTRACE_SETFPREGS 15
150 /* This oddity is because the Linux kernel defines elf_vrregset_t as
151 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
152 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
153 the vrsave as an extra 4 bytes at the end. I opted for creating a
154 flat array of chars, so that it is easier to manipulate for gdb.
156 There are 32 vector registers 16 bytes longs, plus a VSCR register
157 which is only 4 bytes long, but is fetched as a 16 bytes
158 quantity. Up to here we have the elf_vrregset_t structure.
159 Appended to this there is space for the VRSAVE register: 4 bytes.
160 Even though this vrsave register is not included in the regset
161 typedef, it is handled by the ptrace requests.
163 Note that GNU/Linux doesn't support little endian PPC hardware,
164 therefore the offset at which the real value of the VSCR register
165 is located will be always 12 bytes.
167 The layout is like this (where x is the actual value of the vscr reg): */
171 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
172 <-------> <-------><-------><->
177 #define SIZEOF_VRREGS 33*16+4
179 typedef char gdb_vrregset_t
[SIZEOF_VRREGS
];
181 /* This is the layout of the POWER7 VSX registers and the way they overlap
182 with the existing FPR and VMX registers.
184 VSR doubleword 0 VSR doubleword 1
185 ----------------------------------------------------------------
187 ----------------------------------------------------------------
189 ----------------------------------------------------------------
192 ----------------------------------------------------------------
193 VSR[30] | FPR[30] | |
194 ----------------------------------------------------------------
195 VSR[31] | FPR[31] | |
196 ----------------------------------------------------------------
198 ----------------------------------------------------------------
200 ----------------------------------------------------------------
203 ----------------------------------------------------------------
205 ----------------------------------------------------------------
207 ----------------------------------------------------------------
209 VSX has 64 128bit registers. The first 32 registers overlap with
210 the FP registers (doubleword 0) and hence extend them with additional
211 64 bits (doubleword 1). The other 32 regs overlap with the VMX
213 #define SIZEOF_VSXREGS 32*8
215 typedef char gdb_vsxregset_t
[SIZEOF_VSXREGS
];
217 /* On PPC processors that support the Signal Processing Extension
218 (SPE) APU, the general-purpose registers are 64 bits long.
219 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
220 ptrace calls only access the lower half of each register, to allow
221 them to behave the same way they do on non-SPE systems. There's a
222 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
223 read and write the top halves of all the general-purpose registers
224 at once, along with some SPE-specific registers.
226 GDB itself continues to claim the general-purpose registers are 32
227 bits long. It has unnamed raw registers that hold the upper halves
228 of the gprs, and the full 64-bit SIMD views of the registers,
229 'ev0' -- 'ev31', are pseudo-registers that splice the top and
230 bottom halves together.
232 This is the structure filled in by PTRACE_GETEVRREGS and written to
233 the inferior's registers by PTRACE_SETEVRREGS. */
234 struct gdb_evrregset_t
236 unsigned long evr
[32];
237 unsigned long long acc
;
238 unsigned long spefscr
;
241 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
242 PTRACE_SETVSXREGS requests, for reading and writing the VSX
243 POWER7 registers 0 through 31. Zero if we've tried one of them and
244 gotten an error. Note that VSX registers 32 through 63 overlap
245 with VR registers 0 through 31. */
246 int have_ptrace_getsetvsxregs
= 1;
248 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
249 PTRACE_SETVRREGS requests, for reading and writing the Altivec
250 registers. Zero if we've tried one of them and gotten an
252 int have_ptrace_getvrregs
= 1;
254 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
255 PTRACE_SETEVRREGS requests, for reading and writing the SPE
256 registers. Zero if we've tried one of them and gotten an
258 int have_ptrace_getsetevrregs
= 1;
260 /* Non-zero if our kernel may support the PTRACE_GETREGS and
261 PTRACE_SETREGS requests, for reading and writing the
262 general-purpose registers. Zero if we've tried one of
263 them and gotten an error. */
264 int have_ptrace_getsetregs
= 1;
266 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
267 PTRACE_SETFPREGS requests, for reading and writing the
268 floating-pointers registers. Zero if we've tried one of
269 them and gotten an error. */
270 int have_ptrace_getsetfpregs
= 1;
272 struct ppc_linux_nat_target final
: public linux_nat_target
274 /* Add our register access methods. */
275 void fetch_registers (struct regcache
*, int) override
;
276 void store_registers (struct regcache
*, int) override
;
278 /* Add our breakpoint/watchpoint methods. */
279 int can_use_hw_breakpoint (enum bptype
, int, int) override
;
281 int insert_hw_breakpoint (struct gdbarch
*, struct bp_target_info
*)
284 int remove_hw_breakpoint (struct gdbarch
*, struct bp_target_info
*)
287 int region_ok_for_hw_watchpoint (CORE_ADDR
, int) override
;
289 int insert_watchpoint (CORE_ADDR
, int, enum target_hw_bp_type
,
290 struct expression
*) override
;
292 int remove_watchpoint (CORE_ADDR
, int, enum target_hw_bp_type
,
293 struct expression
*) override
;
295 int insert_mask_watchpoint (CORE_ADDR
, CORE_ADDR
, enum target_hw_bp_type
)
298 int remove_mask_watchpoint (CORE_ADDR
, CORE_ADDR
, enum target_hw_bp_type
)
301 bool stopped_by_watchpoint () override
;
303 bool stopped_data_address (CORE_ADDR
*) override
;
305 bool watchpoint_addr_within_range (CORE_ADDR
, CORE_ADDR
, int) override
;
307 bool can_accel_watchpoint_condition (CORE_ADDR
, int, int, struct expression
*)
310 int masked_watch_num_registers (CORE_ADDR
, CORE_ADDR
) override
;
312 int ranged_break_num_registers () override
;
314 const struct target_desc
*read_description () override
;
316 int auxv_parse (gdb_byte
**readptr
,
317 gdb_byte
*endptr
, CORE_ADDR
*typep
, CORE_ADDR
*valp
)
320 /* Override linux_nat_target low methods. */
321 void low_new_thread (struct lwp_info
*lp
) override
;
324 static ppc_linux_nat_target the_ppc_linux_nat_target
;
327 /* registers layout, as presented by the ptrace interface:
328 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
329 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
330 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
331 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
332 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
333 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
334 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
335 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
336 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
337 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
338 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
339 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
340 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
344 ppc_register_u_addr (struct gdbarch
*gdbarch
, int regno
)
347 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
348 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
349 interface, and not the wordsize of the program's ABI. */
350 int wordsize
= sizeof (long);
352 /* General purpose registers occupy 1 slot each in the buffer. */
353 if (regno
>= tdep
->ppc_gp0_regnum
354 && regno
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
355 u_addr
= ((regno
- tdep
->ppc_gp0_regnum
+ PT_R0
) * wordsize
);
357 /* Floating point regs: eight bytes each in both 32- and 64-bit
358 ptrace interfaces. Thus, two slots each in 32-bit interface, one
359 slot each in 64-bit interface. */
360 if (tdep
->ppc_fp0_regnum
>= 0
361 && regno
>= tdep
->ppc_fp0_regnum
362 && regno
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
363 u_addr
= (PT_FPR0
* wordsize
) + ((regno
- tdep
->ppc_fp0_regnum
) * 8);
365 /* UISA special purpose registers: 1 slot each. */
366 if (regno
== gdbarch_pc_regnum (gdbarch
))
367 u_addr
= PT_NIP
* wordsize
;
368 if (regno
== tdep
->ppc_lr_regnum
)
369 u_addr
= PT_LNK
* wordsize
;
370 if (regno
== tdep
->ppc_cr_regnum
)
371 u_addr
= PT_CCR
* wordsize
;
372 if (regno
== tdep
->ppc_xer_regnum
)
373 u_addr
= PT_XER
* wordsize
;
374 if (regno
== tdep
->ppc_ctr_regnum
)
375 u_addr
= PT_CTR
* wordsize
;
377 if (regno
== tdep
->ppc_mq_regnum
)
378 u_addr
= PT_MQ
* wordsize
;
380 if (regno
== tdep
->ppc_ps_regnum
)
381 u_addr
= PT_MSR
* wordsize
;
382 if (regno
== PPC_ORIG_R3_REGNUM
)
383 u_addr
= PT_ORIG_R3
* wordsize
;
384 if (regno
== PPC_TRAP_REGNUM
)
385 u_addr
= PT_TRAP
* wordsize
;
386 if (tdep
->ppc_fpscr_regnum
>= 0
387 && regno
== tdep
->ppc_fpscr_regnum
)
389 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
390 kernel headers incorrectly contained the 32-bit definition of
391 PT_FPSCR. For the 32-bit definition, floating-point
392 registers occupy two 32-bit "slots", and the FPSCR lives in
393 the second half of such a slot-pair (hence +1). For 64-bit,
394 the FPSCR instead occupies the full 64-bit 2-word-slot and
395 hence no adjustment is necessary. Hack around this. */
396 if (wordsize
== 8 && PT_FPSCR
== (48 + 32 + 1))
397 u_addr
= (48 + 32) * wordsize
;
398 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
399 slot and not just its second word. The PT_FPSCR supplied when
400 GDB is compiled as a 32-bit app doesn't reflect this. */
401 else if (wordsize
== 4 && register_size (gdbarch
, regno
) == 8
402 && PT_FPSCR
== (48 + 2*32 + 1))
403 u_addr
= (48 + 2*32) * wordsize
;
405 u_addr
= PT_FPSCR
* wordsize
;
410 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
411 registers set mechanism, as opposed to the interface for all the
412 other registers, that stores/fetches each register individually. */
414 fetch_vsx_register (struct regcache
*regcache
, int tid
, int regno
)
417 gdb_vsxregset_t regs
;
418 struct gdbarch
*gdbarch
= regcache
->arch ();
419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
420 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
422 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
427 have_ptrace_getsetvsxregs
= 0;
430 perror_with_name (_("Unable to fetch VSX register"));
433 regcache_raw_supply (regcache
, regno
,
434 regs
+ (regno
- tdep
->ppc_vsr0_upper_regnum
)
438 /* The Linux kernel ptrace interface for AltiVec registers uses the
439 registers set mechanism, as opposed to the interface for all the
440 other registers, that stores/fetches each register individually. */
442 fetch_altivec_register (struct regcache
*regcache
, int tid
, int regno
)
447 struct gdbarch
*gdbarch
= regcache
->arch ();
448 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
449 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
451 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
456 have_ptrace_getvrregs
= 0;
459 perror_with_name (_("Unable to fetch AltiVec register"));
462 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
463 long on the hardware. We deal only with the lower 4 bytes of the
464 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
465 there is no need to define an offset for it. */
466 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
467 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
469 regcache_raw_supply (regcache
, regno
,
471 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
474 /* Fetch the top 32 bits of TID's general-purpose registers and the
475 SPE-specific registers, and place the results in EVRREGSET. If we
476 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
479 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
480 PTRACE_SETEVRREGS requests are supported is isolated here, and in
481 set_spe_registers. */
483 get_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
485 if (have_ptrace_getsetevrregs
)
487 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, evrregset
) >= 0)
491 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
492 we just return zeros. */
494 have_ptrace_getsetevrregs
= 0;
496 /* Anything else needs to be reported. */
497 perror_with_name (_("Unable to fetch SPE registers"));
501 memset (evrregset
, 0, sizeof (*evrregset
));
504 /* Supply values from TID for SPE-specific raw registers: the upper
505 halves of the GPRs, the accumulator, and the spefscr. REGNO must
506 be the number of an upper half register, acc, spefscr, or -1 to
507 supply the values of all registers. */
509 fetch_spe_register (struct regcache
*regcache
, int tid
, int regno
)
511 struct gdbarch
*gdbarch
= regcache
->arch ();
512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
513 struct gdb_evrregset_t evrregs
;
515 gdb_assert (sizeof (evrregs
.evr
[0])
516 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
517 gdb_assert (sizeof (evrregs
.acc
)
518 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
519 gdb_assert (sizeof (evrregs
.spefscr
)
520 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
522 get_spe_registers (tid
, &evrregs
);
528 for (i
= 0; i
< ppc_num_gprs
; i
++)
529 regcache_raw_supply (regcache
, tdep
->ppc_ev0_upper_regnum
+ i
,
532 else if (tdep
->ppc_ev0_upper_regnum
<= regno
533 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
534 regcache_raw_supply (regcache
, regno
,
535 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
538 || regno
== tdep
->ppc_acc_regnum
)
539 regcache_raw_supply (regcache
, tdep
->ppc_acc_regnum
, &evrregs
.acc
);
542 || regno
== tdep
->ppc_spefscr_regnum
)
543 regcache_raw_supply (regcache
, tdep
->ppc_spefscr_regnum
,
548 fetch_register (struct regcache
*regcache
, int tid
, int regno
)
550 struct gdbarch
*gdbarch
= regcache
->arch ();
551 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
552 /* This isn't really an address. But ptrace thinks of it as one. */
553 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
554 int bytes_transferred
;
555 unsigned int offset
; /* Offset of registers within the u area. */
556 gdb_byte buf
[PPC_MAX_REGISTER_SIZE
];
558 if (altivec_register_p (gdbarch
, regno
))
560 /* If this is the first time through, or if it is not the first
561 time through, and we have comfirmed that there is kernel
562 support for such a ptrace request, then go and fetch the
564 if (have_ptrace_getvrregs
)
566 fetch_altivec_register (regcache
, tid
, regno
);
569 /* If we have discovered that there is no ptrace support for
570 AltiVec registers, fall through and return zeroes, because
571 regaddr will be -1 in this case. */
573 if (vsx_register_p (gdbarch
, regno
))
575 if (have_ptrace_getsetvsxregs
)
577 fetch_vsx_register (regcache
, tid
, regno
);
581 else if (spe_register_p (gdbarch
, regno
))
583 fetch_spe_register (regcache
, tid
, regno
);
589 memset (buf
, '\0', register_size (gdbarch
, regno
)); /* Supply zeroes */
590 regcache_raw_supply (regcache
, regno
, buf
);
594 /* Read the raw register using sizeof(long) sized chunks. On a
595 32-bit platform, 64-bit floating-point registers will require two
597 for (bytes_transferred
= 0;
598 bytes_transferred
< register_size (gdbarch
, regno
);
599 bytes_transferred
+= sizeof (long))
604 l
= ptrace (PTRACE_PEEKUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, 0);
605 regaddr
+= sizeof (long);
609 xsnprintf (message
, sizeof (message
), "reading register %s (#%d)",
610 gdbarch_register_name (gdbarch
, regno
), regno
);
611 perror_with_name (message
);
613 memcpy (&buf
[bytes_transferred
], &l
, sizeof (l
));
616 /* Now supply the register. Keep in mind that the regcache's idea
617 of the register's size may not be a multiple of sizeof
619 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
621 /* Little-endian values are always found at the left end of the
622 bytes transferred. */
623 regcache_raw_supply (regcache
, regno
, buf
);
625 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
627 /* Big-endian values are found at the right end of the bytes
629 size_t padding
= (bytes_transferred
- register_size (gdbarch
, regno
));
630 regcache_raw_supply (regcache
, regno
, buf
+ padding
);
633 internal_error (__FILE__
, __LINE__
,
634 _("fetch_register: unexpected byte order: %d"),
635 gdbarch_byte_order (gdbarch
));
639 supply_vsxregset (struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
642 struct gdbarch
*gdbarch
= regcache
->arch ();
643 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
644 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
646 for (i
= 0; i
< ppc_num_vshrs
; i
++)
648 regcache_raw_supply (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
649 *vsxregsetp
+ i
* vsxregsize
);
654 supply_vrregset (struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
657 struct gdbarch
*gdbarch
= regcache
->arch ();
658 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
659 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
660 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
661 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
663 for (i
= 0; i
< num_of_vrregs
; i
++)
665 /* The last 2 registers of this set are only 32 bit long, not
666 128. However an offset is necessary only for VSCR because it
667 occupies a whole vector, while VRSAVE occupies a full 4 bytes
669 if (i
== (num_of_vrregs
- 2))
670 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
671 *vrregsetp
+ i
* vrregsize
+ offset
);
673 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
674 *vrregsetp
+ i
* vrregsize
);
679 fetch_vsx_registers (struct regcache
*regcache
, int tid
)
682 gdb_vsxregset_t regs
;
684 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
689 have_ptrace_getsetvsxregs
= 0;
692 perror_with_name (_("Unable to fetch VSX registers"));
694 supply_vsxregset (regcache
, ®s
);
698 fetch_altivec_registers (struct regcache
*regcache
, int tid
)
703 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
708 have_ptrace_getvrregs
= 0;
711 perror_with_name (_("Unable to fetch AltiVec registers"));
713 supply_vrregset (regcache
, ®s
);
716 /* This function actually issues the request to ptrace, telling
717 it to get all general-purpose registers and put them into the
720 If the ptrace request does not exist, this function returns 0
721 and properly sets the have_ptrace_* flag. If the request fails,
722 this function calls perror_with_name. Otherwise, if the request
723 succeeds, then the regcache gets filled and 1 is returned. */
725 fetch_all_gp_regs (struct regcache
*regcache
, int tid
)
727 struct gdbarch
*gdbarch
= regcache
->arch ();
728 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
729 gdb_gregset_t gregset
;
731 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
735 have_ptrace_getsetregs
= 0;
738 perror_with_name (_("Couldn't get general-purpose registers."));
741 supply_gregset (regcache
, (const gdb_gregset_t
*) &gregset
);
746 /* This is a wrapper for the fetch_all_gp_regs function. It is
747 responsible for verifying if this target has the ptrace request
748 that can be used to fetch all general-purpose registers at one
749 shot. If it doesn't, then we should fetch them using the
750 old-fashioned way, which is to iterate over the registers and
751 request them one by one. */
753 fetch_gp_regs (struct regcache
*regcache
, int tid
)
755 struct gdbarch
*gdbarch
= regcache
->arch ();
756 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
759 if (have_ptrace_getsetregs
)
760 if (fetch_all_gp_regs (regcache
, tid
))
763 /* If we've hit this point, it doesn't really matter which
764 architecture we are using. We just need to read the
765 registers in the "old-fashioned way". */
766 for (i
= 0; i
< ppc_num_gprs
; i
++)
767 fetch_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
770 /* This function actually issues the request to ptrace, telling
771 it to get all floating-point registers and put them into the
774 If the ptrace request does not exist, this function returns 0
775 and properly sets the have_ptrace_* flag. If the request fails,
776 this function calls perror_with_name. Otherwise, if the request
777 succeeds, then the regcache gets filled and 1 is returned. */
779 fetch_all_fp_regs (struct regcache
*regcache
, int tid
)
781 gdb_fpregset_t fpregs
;
783 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
787 have_ptrace_getsetfpregs
= 0;
790 perror_with_name (_("Couldn't get floating-point registers."));
793 supply_fpregset (regcache
, (const gdb_fpregset_t
*) &fpregs
);
798 /* This is a wrapper for the fetch_all_fp_regs function. It is
799 responsible for verifying if this target has the ptrace request
800 that can be used to fetch all floating-point registers at one
801 shot. If it doesn't, then we should fetch them using the
802 old-fashioned way, which is to iterate over the registers and
803 request them one by one. */
805 fetch_fp_regs (struct regcache
*regcache
, int tid
)
807 struct gdbarch
*gdbarch
= regcache
->arch ();
808 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
811 if (have_ptrace_getsetfpregs
)
812 if (fetch_all_fp_regs (regcache
, tid
))
815 /* If we've hit this point, it doesn't really matter which
816 architecture we are using. We just need to read the
817 registers in the "old-fashioned way". */
818 for (i
= 0; i
< ppc_num_fprs
; i
++)
819 fetch_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
823 fetch_ppc_registers (struct regcache
*regcache
, int tid
)
826 struct gdbarch
*gdbarch
= regcache
->arch ();
827 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
829 fetch_gp_regs (regcache
, tid
);
830 if (tdep
->ppc_fp0_regnum
>= 0)
831 fetch_fp_regs (regcache
, tid
);
832 fetch_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
833 if (tdep
->ppc_ps_regnum
!= -1)
834 fetch_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
835 if (tdep
->ppc_cr_regnum
!= -1)
836 fetch_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
837 if (tdep
->ppc_lr_regnum
!= -1)
838 fetch_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
839 if (tdep
->ppc_ctr_regnum
!= -1)
840 fetch_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
841 if (tdep
->ppc_xer_regnum
!= -1)
842 fetch_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
843 if (tdep
->ppc_mq_regnum
!= -1)
844 fetch_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
845 if (ppc_linux_trap_reg_p (gdbarch
))
847 fetch_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
848 fetch_register (regcache
, tid
, PPC_TRAP_REGNUM
);
850 if (tdep
->ppc_fpscr_regnum
!= -1)
851 fetch_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
852 if (have_ptrace_getvrregs
)
853 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
854 fetch_altivec_registers (regcache
, tid
);
855 if (have_ptrace_getsetvsxregs
)
856 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
857 fetch_vsx_registers (regcache
, tid
);
858 if (tdep
->ppc_ev0_upper_regnum
>= 0)
859 fetch_spe_register (regcache
, tid
, -1);
862 /* Fetch registers from the child process. Fetch all registers if
863 regno == -1, otherwise fetch all general registers or all floating
864 point registers depending upon the value of regno. */
866 ppc_linux_nat_target::fetch_registers (struct regcache
*regcache
, int regno
)
868 pid_t tid
= get_ptrace_pid (regcache_get_ptid (regcache
));
871 fetch_ppc_registers (regcache
, tid
);
873 fetch_register (regcache
, tid
, regno
);
876 /* Store one VSX register. */
878 store_vsx_register (const struct regcache
*regcache
, int tid
, int regno
)
881 gdb_vsxregset_t regs
;
882 struct gdbarch
*gdbarch
= regcache
->arch ();
883 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
884 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
886 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
891 have_ptrace_getsetvsxregs
= 0;
894 perror_with_name (_("Unable to fetch VSX register"));
897 regcache_raw_collect (regcache
, regno
, regs
+
898 (regno
- tdep
->ppc_vsr0_upper_regnum
) * vsxregsize
);
900 ret
= ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
);
902 perror_with_name (_("Unable to store VSX register"));
905 /* Store one register. */
907 store_altivec_register (const struct regcache
*regcache
, int tid
, int regno
)
912 struct gdbarch
*gdbarch
= regcache
->arch ();
913 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
914 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
916 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
921 have_ptrace_getvrregs
= 0;
924 perror_with_name (_("Unable to fetch AltiVec register"));
927 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
928 long on the hardware. */
929 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
930 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
932 regcache_raw_collect (regcache
, regno
,
934 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
936 ret
= ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
);
938 perror_with_name (_("Unable to store AltiVec register"));
941 /* Assuming TID referrs to an SPE process, set the top halves of TID's
942 general-purpose registers and its SPE-specific registers to the
943 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
946 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
947 PTRACE_SETEVRREGS requests are supported is isolated here, and in
948 get_spe_registers. */
950 set_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
952 if (have_ptrace_getsetevrregs
)
954 if (ptrace (PTRACE_SETEVRREGS
, tid
, 0, evrregset
) >= 0)
958 /* EIO means that the PTRACE_SETEVRREGS request isn't
959 supported; we fail silently, and don't try the call
962 have_ptrace_getsetevrregs
= 0;
964 /* Anything else needs to be reported. */
965 perror_with_name (_("Unable to set SPE registers"));
970 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
971 If REGNO is -1, write the values of all the SPE-specific
974 store_spe_register (const struct regcache
*regcache
, int tid
, int regno
)
976 struct gdbarch
*gdbarch
= regcache
->arch ();
977 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
978 struct gdb_evrregset_t evrregs
;
980 gdb_assert (sizeof (evrregs
.evr
[0])
981 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
982 gdb_assert (sizeof (evrregs
.acc
)
983 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
984 gdb_assert (sizeof (evrregs
.spefscr
)
985 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
988 /* Since we're going to write out every register, the code below
989 should store to every field of evrregs; if that doesn't happen,
990 make it obvious by initializing it with suspicious values. */
991 memset (&evrregs
, 42, sizeof (evrregs
));
993 /* We can only read and write the entire EVR register set at a
994 time, so to write just a single register, we do a
995 read-modify-write maneuver. */
996 get_spe_registers (tid
, &evrregs
);
1002 for (i
= 0; i
< ppc_num_gprs
; i
++)
1003 regcache_raw_collect (regcache
,
1004 tdep
->ppc_ev0_upper_regnum
+ i
,
1007 else if (tdep
->ppc_ev0_upper_regnum
<= regno
1008 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
1009 regcache_raw_collect (regcache
, regno
,
1010 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
1013 || regno
== tdep
->ppc_acc_regnum
)
1014 regcache_raw_collect (regcache
,
1015 tdep
->ppc_acc_regnum
,
1019 || regno
== tdep
->ppc_spefscr_regnum
)
1020 regcache_raw_collect (regcache
,
1021 tdep
->ppc_spefscr_regnum
,
1024 /* Write back the modified register set. */
1025 set_spe_registers (tid
, &evrregs
);
1029 store_register (const struct regcache
*regcache
, int tid
, int regno
)
1031 struct gdbarch
*gdbarch
= regcache
->arch ();
1032 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1033 /* This isn't really an address. But ptrace thinks of it as one. */
1034 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
1036 size_t bytes_to_transfer
;
1037 gdb_byte buf
[PPC_MAX_REGISTER_SIZE
];
1039 if (altivec_register_p (gdbarch
, regno
))
1041 store_altivec_register (regcache
, tid
, regno
);
1044 if (vsx_register_p (gdbarch
, regno
))
1046 store_vsx_register (regcache
, tid
, regno
);
1049 else if (spe_register_p (gdbarch
, regno
))
1051 store_spe_register (regcache
, tid
, regno
);
1058 /* First collect the register. Keep in mind that the regcache's
1059 idea of the register's size may not be a multiple of sizeof
1061 memset (buf
, 0, sizeof buf
);
1062 bytes_to_transfer
= align_up (register_size (gdbarch
, regno
), sizeof (long));
1063 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1065 /* Little-endian values always sit at the left end of the buffer. */
1066 regcache_raw_collect (regcache
, regno
, buf
);
1068 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1070 /* Big-endian values sit at the right end of the buffer. */
1071 size_t padding
= (bytes_to_transfer
- register_size (gdbarch
, regno
));
1072 regcache_raw_collect (regcache
, regno
, buf
+ padding
);
1075 for (i
= 0; i
< bytes_to_transfer
; i
+= sizeof (long))
1079 memcpy (&l
, &buf
[i
], sizeof (l
));
1081 ptrace (PTRACE_POKEUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, l
);
1082 regaddr
+= sizeof (long);
1085 && (regno
== tdep
->ppc_fpscr_regnum
1086 || regno
== PPC_ORIG_R3_REGNUM
1087 || regno
== PPC_TRAP_REGNUM
))
1089 /* Some older kernel versions don't allow fpscr, orig_r3
1090 or trap to be written. */
1097 xsnprintf (message
, sizeof (message
), "writing register %s (#%d)",
1098 gdbarch_register_name (gdbarch
, regno
), regno
);
1099 perror_with_name (message
);
1105 fill_vsxregset (const struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
1108 struct gdbarch
*gdbarch
= regcache
->arch ();
1109 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1110 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
1112 for (i
= 0; i
< ppc_num_vshrs
; i
++)
1113 regcache_raw_collect (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
1114 *vsxregsetp
+ i
* vsxregsize
);
1118 fill_vrregset (const struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
1121 struct gdbarch
*gdbarch
= regcache
->arch ();
1122 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1123 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
1124 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
1125 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
1127 for (i
= 0; i
< num_of_vrregs
; i
++)
1129 /* The last 2 registers of this set are only 32 bit long, not
1130 128, but only VSCR is fetched as a 16 bytes quantity. */
1131 if (i
== (num_of_vrregs
- 2))
1132 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1133 *vrregsetp
+ i
* vrregsize
+ offset
);
1135 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1136 *vrregsetp
+ i
* vrregsize
);
1141 store_vsx_registers (const struct regcache
*regcache
, int tid
)
1144 gdb_vsxregset_t regs
;
1146 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
1151 have_ptrace_getsetvsxregs
= 0;
1154 perror_with_name (_("Couldn't get VSX registers"));
1157 fill_vsxregset (regcache
, ®s
);
1159 if (ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
) < 0)
1160 perror_with_name (_("Couldn't write VSX registers"));
1164 store_altivec_registers (const struct regcache
*regcache
, int tid
)
1167 gdb_vrregset_t regs
;
1169 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
1174 have_ptrace_getvrregs
= 0;
1177 perror_with_name (_("Couldn't get AltiVec registers"));
1180 fill_vrregset (regcache
, ®s
);
1182 if (ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
) < 0)
1183 perror_with_name (_("Couldn't write AltiVec registers"));
1186 /* This function actually issues the request to ptrace, telling
1187 it to store all general-purpose registers present in the specified
1190 If the ptrace request does not exist, this function returns 0
1191 and properly sets the have_ptrace_* flag. If the request fails,
1192 this function calls perror_with_name. Otherwise, if the request
1193 succeeds, then the regcache is stored and 1 is returned. */
1195 store_all_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1197 struct gdbarch
*gdbarch
= regcache
->arch ();
1198 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1199 gdb_gregset_t gregset
;
1201 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
1205 have_ptrace_getsetregs
= 0;
1208 perror_with_name (_("Couldn't get general-purpose registers."));
1211 fill_gregset (regcache
, &gregset
, regno
);
1213 if (ptrace (PTRACE_SETREGS
, tid
, 0, (void *) &gregset
) < 0)
1217 have_ptrace_getsetregs
= 0;
1220 perror_with_name (_("Couldn't set general-purpose registers."));
1226 /* This is a wrapper for the store_all_gp_regs function. It is
1227 responsible for verifying if this target has the ptrace request
1228 that can be used to store all general-purpose registers at one
1229 shot. If it doesn't, then we should store them using the
1230 old-fashioned way, which is to iterate over the registers and
1231 store them one by one. */
1233 store_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1235 struct gdbarch
*gdbarch
= regcache
->arch ();
1236 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1239 if (have_ptrace_getsetregs
)
1240 if (store_all_gp_regs (regcache
, tid
, regno
))
1243 /* If we hit this point, it doesn't really matter which
1244 architecture we are using. We just need to store the
1245 registers in the "old-fashioned way". */
1246 for (i
= 0; i
< ppc_num_gprs
; i
++)
1247 store_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
1250 /* This function actually issues the request to ptrace, telling
1251 it to store all floating-point registers present in the specified
1254 If the ptrace request does not exist, this function returns 0
1255 and properly sets the have_ptrace_* flag. If the request fails,
1256 this function calls perror_with_name. Otherwise, if the request
1257 succeeds, then the regcache is stored and 1 is returned. */
1259 store_all_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1261 gdb_fpregset_t fpregs
;
1263 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1267 have_ptrace_getsetfpregs
= 0;
1270 perror_with_name (_("Couldn't get floating-point registers."));
1273 fill_fpregset (regcache
, &fpregs
, regno
);
1275 if (ptrace (PTRACE_SETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1279 have_ptrace_getsetfpregs
= 0;
1282 perror_with_name (_("Couldn't set floating-point registers."));
1288 /* This is a wrapper for the store_all_fp_regs function. It is
1289 responsible for verifying if this target has the ptrace request
1290 that can be used to store all floating-point registers at one
1291 shot. If it doesn't, then we should store them using the
1292 old-fashioned way, which is to iterate over the registers and
1293 store them one by one. */
1295 store_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1297 struct gdbarch
*gdbarch
= regcache
->arch ();
1298 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1301 if (have_ptrace_getsetfpregs
)
1302 if (store_all_fp_regs (regcache
, tid
, regno
))
1305 /* If we hit this point, it doesn't really matter which
1306 architecture we are using. We just need to store the
1307 registers in the "old-fashioned way". */
1308 for (i
= 0; i
< ppc_num_fprs
; i
++)
1309 store_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
1313 store_ppc_registers (const struct regcache
*regcache
, int tid
)
1316 struct gdbarch
*gdbarch
= regcache
->arch ();
1317 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1319 store_gp_regs (regcache
, tid
, -1);
1320 if (tdep
->ppc_fp0_regnum
>= 0)
1321 store_fp_regs (regcache
, tid
, -1);
1322 store_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
1323 if (tdep
->ppc_ps_regnum
!= -1)
1324 store_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
1325 if (tdep
->ppc_cr_regnum
!= -1)
1326 store_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
1327 if (tdep
->ppc_lr_regnum
!= -1)
1328 store_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
1329 if (tdep
->ppc_ctr_regnum
!= -1)
1330 store_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
1331 if (tdep
->ppc_xer_regnum
!= -1)
1332 store_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
1333 if (tdep
->ppc_mq_regnum
!= -1)
1334 store_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
1335 if (tdep
->ppc_fpscr_regnum
!= -1)
1336 store_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
1337 if (ppc_linux_trap_reg_p (gdbarch
))
1339 store_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
1340 store_register (regcache
, tid
, PPC_TRAP_REGNUM
);
1342 if (have_ptrace_getvrregs
)
1343 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
1344 store_altivec_registers (regcache
, tid
);
1345 if (have_ptrace_getsetvsxregs
)
1346 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
1347 store_vsx_registers (regcache
, tid
);
1348 if (tdep
->ppc_ev0_upper_regnum
>= 0)
1349 store_spe_register (regcache
, tid
, -1);
1352 /* Fetch the AT_HWCAP entry from the aux vector. */
1353 static unsigned long
1354 ppc_linux_get_hwcap (void)
1358 if (target_auxv_search (target_stack
, AT_HWCAP
, &field
))
1359 return (unsigned long) field
;
1364 /* The cached DABR value, to install in new threads.
1365 This variable is used when the PowerPC HWDEBUG ptrace
1366 interface is not available. */
1367 static long saved_dabr_value
;
1369 /* Global structure that will store information about the available
1370 features provided by the PowerPC HWDEBUG ptrace interface. */
1371 static struct ppc_debug_info hwdebug_info
;
1373 /* Global variable that holds the maximum number of slots that the
1374 kernel will use. This is only used when PowerPC HWDEBUG ptrace interface
1376 static size_t max_slots_number
= 0;
1378 struct hw_break_tuple
1381 struct ppc_hw_breakpoint
*hw_break
;
1384 /* This is an internal VEC created to store information about *points inserted
1385 for each thread. This is used when PowerPC HWDEBUG ptrace interface is
1387 typedef struct thread_points
1389 /* The TID to which this *point relates. */
1391 /* Information about the *point, such as its address, type, etc.
1393 Each element inside this vector corresponds to a hardware
1394 breakpoint or watchpoint in the thread represented by TID. The maximum
1395 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1396 the tuple is NULL, then the position in the vector is free. */
1397 struct hw_break_tuple
*hw_breaks
;
1399 DEF_VEC_P (thread_points_p
);
1401 VEC(thread_points_p
) *ppc_threads
= NULL
;
1403 /* The version of the PowerPC HWDEBUG kernel interface that we will use, if
1405 #define PPC_DEBUG_CURRENT_VERSION 1
1407 /* Returns non-zero if we support the PowerPC HWDEBUG ptrace interface. */
1409 have_ptrace_hwdebug_interface (void)
1411 static int have_ptrace_hwdebug_interface
= -1;
1413 if (have_ptrace_hwdebug_interface
== -1)
1417 tid
= ptid_get_lwp (inferior_ptid
);
1419 tid
= ptid_get_pid (inferior_ptid
);
1421 /* Check for kernel support for PowerPC HWDEBUG ptrace interface. */
1422 if (ptrace (PPC_PTRACE_GETHWDBGINFO
, tid
, 0, &hwdebug_info
) >= 0)
1424 /* Check whether PowerPC HWDEBUG ptrace interface is functional and
1425 provides any supported feature. */
1426 if (hwdebug_info
.features
!= 0)
1428 have_ptrace_hwdebug_interface
= 1;
1429 max_slots_number
= hwdebug_info
.num_instruction_bps
1430 + hwdebug_info
.num_data_bps
1431 + hwdebug_info
.num_condition_regs
;
1432 return have_ptrace_hwdebug_interface
;
1435 /* Old school interface and no PowerPC HWDEBUG ptrace support. */
1436 have_ptrace_hwdebug_interface
= 0;
1437 memset (&hwdebug_info
, 0, sizeof (struct ppc_debug_info
));
1440 return have_ptrace_hwdebug_interface
;
1444 ppc_linux_nat_target::can_use_hw_breakpoint (enum bptype type
, int cnt
, int ot
)
1446 int total_hw_wp
, total_hw_bp
;
1448 if (have_ptrace_hwdebug_interface ())
1450 /* When PowerPC HWDEBUG ptrace interface is available, the number of
1451 available hardware watchpoints and breakpoints is stored at the
1452 hwdebug_info struct. */
1453 total_hw_bp
= hwdebug_info
.num_instruction_bps
;
1454 total_hw_wp
= hwdebug_info
.num_data_bps
;
1458 /* When we do not have PowerPC HWDEBUG ptrace interface, we should
1459 consider having 1 hardware watchpoint and no hardware breakpoints. */
1464 if (type
== bp_hardware_watchpoint
|| type
== bp_read_watchpoint
1465 || type
== bp_access_watchpoint
|| type
== bp_watchpoint
)
1467 if (cnt
+ ot
> total_hw_wp
)
1470 else if (type
== bp_hardware_breakpoint
)
1472 if (total_hw_bp
== 0)
1474 /* No hardware breakpoint support. */
1477 if (cnt
> total_hw_bp
)
1481 if (!have_ptrace_hwdebug_interface ())
1484 ptid_t ptid
= inferior_ptid
;
1486 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1487 and whether the target has DABR. If either answer is no, the
1488 ptrace call will return -1. Fail in that case. */
1489 tid
= ptid_get_lwp (ptid
);
1491 tid
= ptid_get_pid (ptid
);
1493 if (ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, 0) == -1)
1501 ppc_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
1503 /* Handle sub-8-byte quantities. */
1507 /* The PowerPC HWDEBUG ptrace interface tells if there are alignment
1508 restrictions for watchpoints in the processors. In that case, we use that
1509 information to determine the hardcoded watchable region for
1511 if (have_ptrace_hwdebug_interface ())
1514 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1515 watchpoints and can watch any access within an arbitrary memory
1516 region. This is useful to watch arrays and structs, for instance. It
1517 takes two hardware watchpoints though. */
1519 && hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
1520 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1522 /* Check if the processor provides DAWR interface. */
1523 if (hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_DAWR
)
1524 /* DAWR interface allows to watch up to 512 byte wide ranges which
1525 can't cross a 512 byte boundary. */
1528 region_size
= hwdebug_info
.data_bp_alignment
;
1529 /* Server processors provide one hardware watchpoint and addr+len should
1530 fall in the watchable region provided by the ptrace interface. */
1532 && (addr
+ len
> (addr
& ~(region_size
- 1)) + region_size
))
1535 /* addr+len must fall in the 8 byte watchable region for DABR-based
1536 processors (i.e., server processors). Without the new PowerPC HWDEBUG
1537 ptrace interface, DAC-based processors (i.e., embedded processors) will
1538 use addresses aligned to 4-bytes due to the way the read/write flags are
1539 passed in the old ptrace interface. */
1540 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1541 && (addr
+ len
) > (addr
& ~3) + 4)
1542 || (addr
+ len
) > (addr
& ~7) + 8)
1548 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1550 hwdebug_point_cmp (struct ppc_hw_breakpoint
*a
, struct ppc_hw_breakpoint
*b
)
1552 return (a
->trigger_type
== b
->trigger_type
1553 && a
->addr_mode
== b
->addr_mode
1554 && a
->condition_mode
== b
->condition_mode
1555 && a
->addr
== b
->addr
1556 && a
->addr2
== b
->addr2
1557 && a
->condition_value
== b
->condition_value
);
1560 /* This function can be used to retrieve a thread_points by the TID of the
1561 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1562 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1563 provided TID will be created and returned. */
1564 static struct thread_points
*
1565 hwdebug_find_thread_points_by_tid (int tid
, int alloc_new
)
1568 struct thread_points
*t
;
1570 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, t
); i
++)
1576 /* Do we need to allocate a new point_item
1577 if the wanted one does not exist? */
1580 t
= XNEW (struct thread_points
);
1581 t
->hw_breaks
= XCNEWVEC (struct hw_break_tuple
, max_slots_number
);
1583 VEC_safe_push (thread_points_p
, ppc_threads
, t
);
1589 /* This function is a generic wrapper that is responsible for inserting a
1590 *point (i.e., calling `ptrace' in order to issue the request to the
1591 kernel) and registering it internally in GDB. */
1593 hwdebug_insert_point (struct ppc_hw_breakpoint
*b
, int tid
)
1597 gdb::unique_xmalloc_ptr
<ppc_hw_breakpoint
> p (XDUP (ppc_hw_breakpoint
, b
));
1598 struct hw_break_tuple
*hw_breaks
;
1599 struct thread_points
*t
;
1600 struct hw_break_tuple
*tuple
;
1603 slot
= ptrace (PPC_PTRACE_SETHWDEBUG
, tid
, 0, p
.get ());
1605 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1607 /* Everything went fine, so we have to register this *point. */
1608 t
= hwdebug_find_thread_points_by_tid (tid
, 1);
1609 gdb_assert (t
!= NULL
);
1610 hw_breaks
= t
->hw_breaks
;
1612 /* Find a free element in the hw_breaks vector. */
1613 for (i
= 0; i
< max_slots_number
; i
++)
1614 if (hw_breaks
[i
].hw_break
== NULL
)
1616 hw_breaks
[i
].slot
= slot
;
1617 hw_breaks
[i
].hw_break
= p
.release ();
1621 gdb_assert (i
!= max_slots_number
);
1624 /* This function is a generic wrapper that is responsible for removing a
1625 *point (i.e., calling `ptrace' in order to issue the request to the
1626 kernel), and unregistering it internally at GDB. */
1628 hwdebug_remove_point (struct ppc_hw_breakpoint
*b
, int tid
)
1631 struct hw_break_tuple
*hw_breaks
;
1632 struct thread_points
*t
;
1634 t
= hwdebug_find_thread_points_by_tid (tid
, 0);
1635 gdb_assert (t
!= NULL
);
1636 hw_breaks
= t
->hw_breaks
;
1638 for (i
= 0; i
< max_slots_number
; i
++)
1639 if (hw_breaks
[i
].hw_break
&& hwdebug_point_cmp (hw_breaks
[i
].hw_break
, b
))
1642 gdb_assert (i
!= max_slots_number
);
1644 /* We have to ignore ENOENT errors because the kernel implements hardware
1645 breakpoints/watchpoints as "one-shot", that is, they are automatically
1646 deleted when hit. */
1648 if (ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
) < 0)
1649 if (errno
!= ENOENT
)
1650 perror_with_name (_("Unexpected error deleting "
1651 "breakpoint or watchpoint"));
1653 xfree (hw_breaks
[i
].hw_break
);
1654 hw_breaks
[i
].hw_break
= NULL
;
1657 /* Return the number of registers needed for a ranged breakpoint. */
1660 ppc_linux_nat_target::ranged_break_num_registers ()
1662 return ((have_ptrace_hwdebug_interface ()
1663 && hwdebug_info
.features
& PPC_DEBUG_FEATURE_INSN_BP_RANGE
)?
1667 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1668 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1671 ppc_linux_nat_target::insert_hw_breakpoint (struct gdbarch
*gdbarch
,
1672 struct bp_target_info
*bp_tgt
)
1674 struct lwp_info
*lp
;
1675 struct ppc_hw_breakpoint p
;
1677 if (!have_ptrace_hwdebug_interface ())
1680 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1681 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1682 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1683 p
.addr
= (uint64_t) (bp_tgt
->placed_address
= bp_tgt
->reqstd_address
);
1684 p
.condition_value
= 0;
1688 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1690 /* The breakpoint will trigger if the address of the instruction is
1691 within the defined range, as follows: p.addr <= address < p.addr2. */
1692 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1696 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1701 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
1707 ppc_linux_nat_target::remove_hw_breakpoint (struct gdbarch
*gdbarch
,
1708 struct bp_target_info
*bp_tgt
)
1710 struct lwp_info
*lp
;
1711 struct ppc_hw_breakpoint p
;
1713 if (!have_ptrace_hwdebug_interface ())
1716 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1717 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1718 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1719 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1720 p
.condition_value
= 0;
1724 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1726 /* The breakpoint will trigger if the address of the instruction is within
1727 the defined range, as follows: p.addr <= address < p.addr2. */
1728 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1732 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1737 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
1743 get_trigger_type (enum target_hw_bp_type type
)
1747 if (type
== hw_read
)
1748 t
= PPC_BREAKPOINT_TRIGGER_READ
;
1749 else if (type
== hw_write
)
1750 t
= PPC_BREAKPOINT_TRIGGER_WRITE
;
1752 t
= PPC_BREAKPOINT_TRIGGER_READ
| PPC_BREAKPOINT_TRIGGER_WRITE
;
1757 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1758 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1759 or hw_access for an access watchpoint. Returns 0 on success and throws
1760 an error on failure. */
1763 ppc_linux_nat_target::insert_mask_watchpoint (CORE_ADDR addr
, CORE_ADDR mask
,
1764 target_hw_bp_type rw
)
1766 struct lwp_info
*lp
;
1767 struct ppc_hw_breakpoint p
;
1769 gdb_assert (have_ptrace_hwdebug_interface ());
1771 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1772 p
.trigger_type
= get_trigger_type (rw
);
1773 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1774 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1777 p
.condition_value
= 0;
1780 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
1785 /* Remove a masked watchpoint at ADDR with the mask MASK.
1786 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1787 or hw_access for an access watchpoint. Returns 0 on success and throws
1788 an error on failure. */
1791 ppc_linux_nat_target::remove_mask_watchpoint (CORE_ADDR addr
, CORE_ADDR mask
,
1792 target_hw_bp_type rw
)
1794 struct lwp_info
*lp
;
1795 struct ppc_hw_breakpoint p
;
1797 gdb_assert (have_ptrace_hwdebug_interface ());
1799 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1800 p
.trigger_type
= get_trigger_type (rw
);
1801 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1802 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1805 p
.condition_value
= 0;
1808 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
1813 /* Check whether we have at least one free DVC register. */
1815 can_use_watchpoint_cond_accel (void)
1817 struct thread_points
*p
;
1818 int tid
= ptid_get_lwp (inferior_ptid
);
1819 int cnt
= hwdebug_info
.num_condition_regs
, i
;
1820 CORE_ADDR tmp_value
;
1822 if (!have_ptrace_hwdebug_interface () || cnt
== 0)
1825 p
= hwdebug_find_thread_points_by_tid (tid
, 0);
1829 for (i
= 0; i
< max_slots_number
; i
++)
1830 if (p
->hw_breaks
[i
].hw_break
!= NULL
1831 && (p
->hw_breaks
[i
].hw_break
->condition_mode
1832 != PPC_BREAKPOINT_CONDITION_NONE
))
1835 /* There are no available slots now. */
1843 /* Calculate the enable bits and the contents of the Data Value Compare
1844 debug register present in BookE processors.
1846 ADDR is the address to be watched, LEN is the length of watched data
1847 and DATA_VALUE is the value which will trigger the watchpoint.
1848 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1849 CONDITION_VALUE will hold the value which should be put in the
1852 calculate_dvc (CORE_ADDR addr
, int len
, CORE_ADDR data_value
,
1853 uint32_t *condition_mode
, uint64_t *condition_value
)
1855 int i
, num_byte_enable
, align_offset
, num_bytes_off_dvc
,
1856 rightmost_enabled_byte
;
1857 CORE_ADDR addr_end_data
, addr_end_dvc
;
1859 /* The DVC register compares bytes within fixed-length windows which
1860 are word-aligned, with length equal to that of the DVC register.
1861 We need to calculate where our watch region is relative to that
1862 window and enable comparison of the bytes which fall within it. */
1864 align_offset
= addr
% hwdebug_info
.sizeof_condition
;
1865 addr_end_data
= addr
+ len
;
1866 addr_end_dvc
= (addr
- align_offset
1867 + hwdebug_info
.sizeof_condition
);
1868 num_bytes_off_dvc
= (addr_end_data
> addr_end_dvc
)?
1869 addr_end_data
- addr_end_dvc
: 0;
1870 num_byte_enable
= len
- num_bytes_off_dvc
;
1871 /* Here, bytes are numbered from right to left. */
1872 rightmost_enabled_byte
= (addr_end_data
< addr_end_dvc
)?
1873 addr_end_dvc
- addr_end_data
: 0;
1875 *condition_mode
= PPC_BREAKPOINT_CONDITION_AND
;
1876 for (i
= 0; i
< num_byte_enable
; i
++)
1878 |= PPC_BREAKPOINT_CONDITION_BE (i
+ rightmost_enabled_byte
);
1880 /* Now we need to match the position within the DVC of the comparison
1881 value with where the watch region is relative to the window
1882 (i.e., the ALIGN_OFFSET). */
1884 *condition_value
= ((uint64_t) data_value
>> num_bytes_off_dvc
* 8
1885 << rightmost_enabled_byte
* 8);
1888 /* Return the number of memory locations that need to be accessed to
1889 evaluate the expression which generated the given value chain.
1890 Returns -1 if there's any register access involved, or if there are
1891 other kinds of values which are not acceptable in a condition
1892 expression (e.g., lval_computed or lval_internalvar). */
1894 num_memory_accesses (const std::vector
<value_ref_ptr
> &chain
)
1896 int found_memory_cnt
= 0;
1898 /* The idea here is that evaluating an expression generates a series
1899 of values, one holding the value of every subexpression. (The
1900 expression a*b+c has five subexpressions: a, b, a*b, c, and
1901 a*b+c.) GDB's values hold almost enough information to establish
1902 the criteria given above --- they identify memory lvalues,
1903 register lvalues, computed values, etcetera. So we can evaluate
1904 the expression, and then scan the chain of values that leaves
1905 behind to determine the memory locations involved in the evaluation
1908 However, I don't think that the values returned by inferior
1909 function calls are special in any way. So this function may not
1910 notice that an expression contains an inferior function call.
1913 for (const value_ref_ptr
&iter
: chain
)
1915 struct value
*v
= iter
.get ();
1917 /* Constants and values from the history are fine. */
1918 if (VALUE_LVAL (v
) == not_lval
|| deprecated_value_modifiable (v
) == 0)
1920 else if (VALUE_LVAL (v
) == lval_memory
)
1922 /* A lazy memory lvalue is one that GDB never needed to fetch;
1923 we either just used its address (e.g., `a' in `a.b') or
1924 we never needed it at all (e.g., `a' in `a,b'). */
1925 if (!value_lazy (v
))
1928 /* Other kinds of values are not fine. */
1933 return found_memory_cnt
;
1936 /* Verifies whether the expression COND can be implemented using the
1937 DVC (Data Value Compare) register in BookE processors. The expression
1938 must test the watch value for equality with a constant expression.
1939 If the function returns 1, DATA_VALUE will contain the constant against
1940 which the watch value should be compared and LEN will contain the size
1943 check_condition (CORE_ADDR watch_addr
, struct expression
*cond
,
1944 CORE_ADDR
*data_value
, int *len
)
1946 int pc
= 1, num_accesses_left
, num_accesses_right
;
1947 struct value
*left_val
, *right_val
;
1948 std::vector
<value_ref_ptr
> left_chain
, right_chain
;
1950 if (cond
->elts
[0].opcode
!= BINOP_EQUAL
)
1953 fetch_subexp_value (cond
, &pc
, &left_val
, NULL
, &left_chain
, 0);
1954 num_accesses_left
= num_memory_accesses (left_chain
);
1956 if (left_val
== NULL
|| num_accesses_left
< 0)
1959 fetch_subexp_value (cond
, &pc
, &right_val
, NULL
, &right_chain
, 0);
1960 num_accesses_right
= num_memory_accesses (right_chain
);
1962 if (right_val
== NULL
|| num_accesses_right
< 0)
1965 if (num_accesses_left
== 1 && num_accesses_right
== 0
1966 && VALUE_LVAL (left_val
) == lval_memory
1967 && value_address (left_val
) == watch_addr
)
1969 *data_value
= value_as_long (right_val
);
1971 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1972 the same type as the memory region referenced by LEFT_VAL. */
1973 *len
= TYPE_LENGTH (check_typedef (value_type (left_val
)));
1975 else if (num_accesses_left
== 0 && num_accesses_right
== 1
1976 && VALUE_LVAL (right_val
) == lval_memory
1977 && value_address (right_val
) == watch_addr
)
1979 *data_value
= value_as_long (left_val
);
1981 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1982 the same type as the memory region referenced by RIGHT_VAL. */
1983 *len
= TYPE_LENGTH (check_typedef (value_type (right_val
)));
1991 /* Return non-zero if the target is capable of using hardware to evaluate
1992 the condition expression, thus only triggering the watchpoint when it is
1995 ppc_linux_nat_target::can_accel_watchpoint_condition (CORE_ADDR addr
, int len
,
1997 struct expression
*cond
)
1999 CORE_ADDR data_value
;
2001 return (have_ptrace_hwdebug_interface ()
2002 && hwdebug_info
.num_condition_regs
> 0
2003 && check_condition (addr
, cond
, &data_value
, &len
));
2006 /* Set up P with the parameters necessary to request a watchpoint covering
2007 LEN bytes starting at ADDR and if possible with condition expression COND
2008 evaluated by hardware. INSERT tells if we are creating a request for
2009 inserting or removing the watchpoint. */
2012 create_watchpoint_request (struct ppc_hw_breakpoint
*p
, CORE_ADDR addr
,
2013 int len
, enum target_hw_bp_type type
,
2014 struct expression
*cond
, int insert
)
2017 || !(hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
))
2020 CORE_ADDR data_value
;
2022 use_condition
= (insert
? can_use_watchpoint_cond_accel ()
2023 : hwdebug_info
.num_condition_regs
> 0);
2024 if (cond
&& use_condition
&& check_condition (addr
, cond
,
2026 calculate_dvc (addr
, len
, data_value
, &p
->condition_mode
,
2027 &p
->condition_value
);
2030 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2031 p
->condition_value
= 0;
2034 p
->addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
2039 p
->addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
2040 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2041 p
->condition_value
= 0;
2043 /* The watchpoint will trigger if the address of the memory access is
2044 within the defined range, as follows: p->addr <= address < p->addr2.
2046 Note that the above sentence just documents how ptrace interprets
2047 its arguments; the watchpoint is set to watch the range defined by
2048 the user _inclusively_, as specified by the user interface. */
2049 p
->addr2
= (uint64_t) addr
+ len
;
2052 p
->version
= PPC_DEBUG_CURRENT_VERSION
;
2053 p
->trigger_type
= get_trigger_type (type
);
2054 p
->addr
= (uint64_t) addr
;
2058 ppc_linux_nat_target::insert_watchpoint (CORE_ADDR addr
, int len
,
2059 enum target_hw_bp_type type
,
2060 struct expression
*cond
)
2062 struct lwp_info
*lp
;
2065 if (have_ptrace_hwdebug_interface ())
2067 struct ppc_hw_breakpoint p
;
2069 create_watchpoint_request (&p
, addr
, len
, type
, cond
, 1);
2072 hwdebug_insert_point (&p
, ptid_get_lwp (lp
->ptid
));
2079 long read_mode
, write_mode
;
2081 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2083 /* PowerPC 440 requires only the read/write flags to be passed
2090 /* PowerPC 970 and other DABR-based processors are required to pass
2091 the Breakpoint Translation bit together with the flags. */
2096 dabr_value
= addr
& ~(read_mode
| write_mode
);
2100 /* Set read and translate bits. */
2101 dabr_value
|= read_mode
;
2104 /* Set write and translate bits. */
2105 dabr_value
|= write_mode
;
2108 /* Set read, write and translate bits. */
2109 dabr_value
|= read_mode
| write_mode
;
2113 saved_dabr_value
= dabr_value
;
2116 if (ptrace (PTRACE_SET_DEBUGREG
, ptid_get_lwp (lp
->ptid
), 0,
2117 saved_dabr_value
) < 0)
2127 ppc_linux_nat_target::remove_watchpoint (CORE_ADDR addr
, int len
,
2128 enum target_hw_bp_type type
,
2129 struct expression
*cond
)
2131 struct lwp_info
*lp
;
2134 if (have_ptrace_hwdebug_interface ())
2136 struct ppc_hw_breakpoint p
;
2138 create_watchpoint_request (&p
, addr
, len
, type
, cond
, 0);
2141 hwdebug_remove_point (&p
, ptid_get_lwp (lp
->ptid
));
2147 saved_dabr_value
= 0;
2149 if (ptrace (PTRACE_SET_DEBUGREG
, ptid_get_lwp (lp
->ptid
), 0,
2150 saved_dabr_value
) < 0)
2160 ppc_linux_nat_target::low_new_thread (struct lwp_info
*lp
)
2162 int tid
= ptid_get_lwp (lp
->ptid
);
2164 if (have_ptrace_hwdebug_interface ())
2167 struct thread_points
*p
;
2168 struct hw_break_tuple
*hw_breaks
;
2170 if (VEC_empty (thread_points_p
, ppc_threads
))
2173 /* Get a list of breakpoints from any thread. */
2174 p
= VEC_last (thread_points_p
, ppc_threads
);
2175 hw_breaks
= p
->hw_breaks
;
2177 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2178 for (i
= 0; i
< max_slots_number
; i
++)
2179 if (hw_breaks
[i
].hw_break
)
2181 /* Older kernels did not make new threads inherit their parent
2182 thread's debug state, so we always clear the slot and replicate
2183 the debug state ourselves, ensuring compatibility with all
2186 /* The ppc debug resource accounting is done through "slots".
2187 Ask the kernel the deallocate this specific *point's slot. */
2188 ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
);
2190 hwdebug_insert_point (hw_breaks
[i
].hw_break
, tid
);
2194 ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, saved_dabr_value
);
2198 ppc_linux_thread_exit (struct thread_info
*tp
, int silent
)
2201 int tid
= ptid_get_lwp (tp
->ptid
);
2202 struct hw_break_tuple
*hw_breaks
;
2203 struct thread_points
*t
= NULL
, *p
;
2205 if (!have_ptrace_hwdebug_interface ())
2208 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, p
); i
++)
2218 VEC_unordered_remove (thread_points_p
, ppc_threads
, i
);
2220 hw_breaks
= t
->hw_breaks
;
2222 for (i
= 0; i
< max_slots_number
; i
++)
2223 if (hw_breaks
[i
].hw_break
)
2224 xfree (hw_breaks
[i
].hw_break
);
2226 xfree (t
->hw_breaks
);
2231 ppc_linux_nat_target::stopped_data_address (CORE_ADDR
*addr_p
)
2235 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
2238 if (siginfo
.si_signo
!= SIGTRAP
2239 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2242 if (have_ptrace_hwdebug_interface ())
2245 struct thread_points
*t
;
2246 struct hw_break_tuple
*hw_breaks
;
2247 /* The index (or slot) of the *point is passed in the si_errno field. */
2248 int slot
= siginfo
.si_errno
;
2250 t
= hwdebug_find_thread_points_by_tid (ptid_get_lwp (inferior_ptid
), 0);
2252 /* Find out if this *point is a hardware breakpoint.
2253 If so, we should return 0. */
2256 hw_breaks
= t
->hw_breaks
;
2257 for (i
= 0; i
< max_slots_number
; i
++)
2258 if (hw_breaks
[i
].hw_break
&& hw_breaks
[i
].slot
== slot
2259 && hw_breaks
[i
].hw_break
->trigger_type
2260 == PPC_BREAKPOINT_TRIGGER_EXECUTE
)
2265 *addr_p
= (CORE_ADDR
) (uintptr_t) siginfo
.si_addr
;
2270 ppc_linux_nat_target::stopped_by_watchpoint ()
2273 return stopped_data_address (&addr
);
2277 ppc_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr
,
2283 if (have_ptrace_hwdebug_interface ()
2284 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2285 return start
<= addr
&& start
+ length
>= addr
;
2286 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2293 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2294 return start
<= addr
+ mask
&& start
+ length
- 1 >= addr
;
2297 /* Return the number of registers needed for a masked hardware watchpoint. */
2300 ppc_linux_nat_target::masked_watch_num_registers (CORE_ADDR addr
, CORE_ADDR mask
)
2302 if (!have_ptrace_hwdebug_interface ()
2303 || (hwdebug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_MASK
) == 0)
2305 else if ((mask
& 0xC0000000) != 0xC0000000)
2307 warning (_("The given mask covers kernel address space "
2308 "and cannot be used.\n"));
2317 ppc_linux_nat_target::store_registers (struct regcache
*regcache
, int regno
)
2319 pid_t tid
= get_ptrace_pid (regcache_get_ptid (regcache
));
2322 store_register (regcache
, tid
, regno
);
2324 store_ppc_registers (regcache
, tid
);
2327 /* Functions for transferring registers between a gregset_t or fpregset_t
2328 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2329 by the ptrace interface, not the current program's ABI. Eg. if a
2330 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2331 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2334 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
2336 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2338 ppc_supply_gregset (regset
, regcache
, -1, gregsetp
, sizeof (*gregsetp
));
2342 fill_gregset (const struct regcache
*regcache
,
2343 gdb_gregset_t
*gregsetp
, int regno
)
2345 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2348 memset (gregsetp
, 0, sizeof (*gregsetp
));
2349 ppc_collect_gregset (regset
, regcache
, regno
, gregsetp
, sizeof (*gregsetp
));
2353 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
* fpregsetp
)
2355 const struct regset
*regset
= ppc_linux_fpregset ();
2357 ppc_supply_fpregset (regset
, regcache
, -1,
2358 fpregsetp
, sizeof (*fpregsetp
));
2362 fill_fpregset (const struct regcache
*regcache
,
2363 gdb_fpregset_t
*fpregsetp
, int regno
)
2365 const struct regset
*regset
= ppc_linux_fpregset ();
2367 ppc_collect_fpregset (regset
, regcache
, regno
,
2368 fpregsetp
, sizeof (*fpregsetp
));
2372 ppc_linux_target_wordsize (void)
2376 /* Check for 64-bit inferior process. This is the case when the host is
2377 64-bit, and in addition the top bit of the MSR register is set. */
2378 #ifdef __powerpc64__
2381 int tid
= ptid_get_lwp (inferior_ptid
);
2383 tid
= ptid_get_pid (inferior_ptid
);
2386 msr
= (long) ptrace (PTRACE_PEEKUSER
, tid
, PT_MSR
* 8, 0);
2387 if (errno
== 0 && ppc64_64bit_inferior_p (msr
))
2395 ppc_linux_nat_target::auxv_parse (gdb_byte
**readptr
,
2396 gdb_byte
*endptr
, CORE_ADDR
*typep
,
2399 int sizeof_auxv_field
= ppc_linux_target_wordsize ();
2400 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
2401 gdb_byte
*ptr
= *readptr
;
2406 if (endptr
- ptr
< sizeof_auxv_field
* 2)
2409 *typep
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2410 ptr
+= sizeof_auxv_field
;
2411 *valp
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2412 ptr
+= sizeof_auxv_field
;
2418 const struct target_desc
*
2419 ppc_linux_nat_target::read_description ()
2421 int tid
= ptid_get_lwp (inferior_ptid
);
2423 tid
= ptid_get_pid (inferior_ptid
);
2425 if (have_ptrace_getsetevrregs
)
2427 struct gdb_evrregset_t evrregset
;
2429 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, &evrregset
) >= 0)
2430 return tdesc_powerpc_e500l
;
2432 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2433 Anything else needs to be reported. */
2434 else if (errno
!= EIO
)
2435 perror_with_name (_("Unable to fetch SPE registers"));
2438 struct ppc_linux_features features
= ppc_linux_no_features
;
2440 features
.wordsize
= ppc_linux_target_wordsize ();
2442 unsigned long hwcap
= ppc_linux_get_hwcap ();
2444 if (have_ptrace_getsetvsxregs
2445 && (hwcap
& PPC_FEATURE_HAS_VSX
))
2447 gdb_vsxregset_t vsxregset
;
2449 if (ptrace (PTRACE_GETVSXREGS
, tid
, 0, &vsxregset
) >= 0)
2450 features
.vsx
= true;
2452 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2453 Anything else needs to be reported. */
2454 else if (errno
!= EIO
)
2455 perror_with_name (_("Unable to fetch VSX registers"));
2458 if (have_ptrace_getvrregs
2459 && (hwcap
& PPC_FEATURE_HAS_ALTIVEC
))
2461 gdb_vrregset_t vrregset
;
2463 if (ptrace (PTRACE_GETVRREGS
, tid
, 0, &vrregset
) >= 0)
2464 features
.altivec
= true;
2466 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2467 Anything else needs to be reported. */
2468 else if (errno
!= EIO
)
2469 perror_with_name (_("Unable to fetch AltiVec registers"));
2472 if (hwcap
& PPC_FEATURE_CELL
)
2473 features
.cell
= true;
2475 features
.isa205
= ppc_linux_has_isa205 (hwcap
);
2477 return ppc_linux_match_description (features
);
2481 _initialize_ppc_linux_nat (void)
2483 linux_target
= &the_ppc_linux_nat_target
;
2485 gdb::observers::thread_exit
.attach (ppc_linux_thread_exit
);
2487 /* Register the target. */
2488 add_inf_child_target (linux_target
);