1 /* PPC GNU/Linux native support.
3 Copyright (C) 1988-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "gdb_string.h"
25 #include "gdbthread.h"
28 #include "gdb_assert.h"
30 #include "linux-nat.h"
33 #include <sys/types.h>
36 #include <sys/ioctl.h>
39 #include <sys/procfs.h>
40 #include <sys/ptrace.h>
42 /* Prototypes for supply_gregset etc. */
45 #include "ppc-linux-tdep.h"
47 /* Required when using the AUXV. */
48 #include "elf/common.h"
51 /* This sometimes isn't defined. */
59 /* The PPC_FEATURE_* defines should be provided by <asm/cputable.h>.
60 If they aren't, we can provide them ourselves (their values are fixed
61 because they are part of the kernel ABI). They are used in the AT_HWCAP
63 #ifndef PPC_FEATURE_CELL
64 #define PPC_FEATURE_CELL 0x00010000
66 #ifndef PPC_FEATURE_BOOKE
67 #define PPC_FEATURE_BOOKE 0x00008000
69 #ifndef PPC_FEATURE_HAS_DFP
70 #define PPC_FEATURE_HAS_DFP 0x00000400 /* Decimal Floating Point. */
73 /* Glibc's headers don't define PTRACE_GETVRREGS so we cannot use a
74 configure time check. Some older glibc's (for instance 2.2.1)
75 don't have a specific powerpc version of ptrace.h, and fall back on
76 a generic one. In such cases, sys/ptrace.h defines
77 PTRACE_GETFPXREGS and PTRACE_SETFPXREGS to the same numbers that
78 ppc kernel's asm/ptrace.h defines PTRACE_GETVRREGS and
79 PTRACE_SETVRREGS to be. This also makes a configury check pretty
82 /* These definitions should really come from the glibc header files,
83 but Glibc doesn't know about the vrregs yet. */
84 #ifndef PTRACE_GETVRREGS
85 #define PTRACE_GETVRREGS 18
86 #define PTRACE_SETVRREGS 19
89 /* PTRACE requests for POWER7 VSX registers. */
90 #ifndef PTRACE_GETVSXREGS
91 #define PTRACE_GETVSXREGS 27
92 #define PTRACE_SETVSXREGS 28
95 /* Similarly for the ptrace requests for getting / setting the SPE
96 registers (ev0 -- ev31, acc, and spefscr). See the description of
97 gdb_evrregset_t for details. */
98 #ifndef PTRACE_GETEVRREGS
99 #define PTRACE_GETEVRREGS 20
100 #define PTRACE_SETEVRREGS 21
103 /* Similarly for the hardware watchpoint support. These requests are used
104 when the BookE kernel interface is not available. */
105 #ifndef PTRACE_GET_DEBUGREG
106 #define PTRACE_GET_DEBUGREG 25
108 #ifndef PTRACE_SET_DEBUGREG
109 #define PTRACE_SET_DEBUGREG 26
111 #ifndef PTRACE_GETSIGINFO
112 #define PTRACE_GETSIGINFO 0x4202
115 /* These requests are used when the BookE kernel interface is available.
116 It exposes the additional debug features of BookE processors, such as
117 ranged breakpoints and watchpoints and hardware-accelerated condition
119 #ifndef PPC_PTRACE_GETHWDBGINFO
121 /* Not having PPC_PTRACE_GETHWDBGINFO defined means that the new BookE
122 interface is not present in ptrace.h, so we'll have to pretty much include
123 it all here so that the code at least compiles on older systems. */
124 #define PPC_PTRACE_GETHWDBGINFO 0x89
125 #define PPC_PTRACE_SETHWDEBUG 0x88
126 #define PPC_PTRACE_DELHWDEBUG 0x87
128 struct ppc_debug_info
130 uint32_t version
; /* Only version 1 exists to date. */
131 uint32_t num_instruction_bps
;
132 uint32_t num_data_bps
;
133 uint32_t num_condition_regs
;
134 uint32_t data_bp_alignment
;
135 uint32_t sizeof_condition
; /* size of the DVC register. */
139 /* Features will have bits indicating whether there is support for: */
140 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x1
141 #define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x2
142 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x4
143 #define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x8
145 struct ppc_hw_breakpoint
147 uint32_t version
; /* currently, version must be 1 */
148 uint32_t trigger_type
; /* only some combinations allowed */
149 uint32_t addr_mode
; /* address match mode */
150 uint32_t condition_mode
; /* break/watchpoint condition flags */
151 uint64_t addr
; /* break/watchpoint address */
152 uint64_t addr2
; /* range end or mask */
153 uint64_t condition_value
; /* contents of the DVC register */
157 #define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x1
158 #define PPC_BREAKPOINT_TRIGGER_READ 0x2
159 #define PPC_BREAKPOINT_TRIGGER_WRITE 0x4
160 #define PPC_BREAKPOINT_TRIGGER_RW 0x6
163 #define PPC_BREAKPOINT_MODE_EXACT 0x0
164 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x1
165 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x2
166 #define PPC_BREAKPOINT_MODE_MASK 0x3
168 /* Condition mode. */
169 #define PPC_BREAKPOINT_CONDITION_NONE 0x0
170 #define PPC_BREAKPOINT_CONDITION_AND 0x1
171 #define PPC_BREAKPOINT_CONDITION_EXACT 0x1
172 #define PPC_BREAKPOINT_CONDITION_OR 0x2
173 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
174 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
175 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
176 #define PPC_BREAKPOINT_CONDITION_BE(n) \
177 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
178 #endif /* PPC_PTRACE_GETHWDBGINFO */
182 /* Similarly for the general-purpose (gp0 -- gp31)
183 and floating-point registers (fp0 -- fp31). */
184 #ifndef PTRACE_GETREGS
185 #define PTRACE_GETREGS 12
187 #ifndef PTRACE_SETREGS
188 #define PTRACE_SETREGS 13
190 #ifndef PTRACE_GETFPREGS
191 #define PTRACE_GETFPREGS 14
193 #ifndef PTRACE_SETFPREGS
194 #define PTRACE_SETFPREGS 15
197 /* This oddity is because the Linux kernel defines elf_vrregset_t as
198 an array of 33 16 bytes long elements. I.e. it leaves out vrsave.
199 However the PTRACE_GETVRREGS and PTRACE_SETVRREGS requests return
200 the vrsave as an extra 4 bytes at the end. I opted for creating a
201 flat array of chars, so that it is easier to manipulate for gdb.
203 There are 32 vector registers 16 bytes longs, plus a VSCR register
204 which is only 4 bytes long, but is fetched as a 16 bytes
205 quantity. Up to here we have the elf_vrregset_t structure.
206 Appended to this there is space for the VRSAVE register: 4 bytes.
207 Even though this vrsave register is not included in the regset
208 typedef, it is handled by the ptrace requests.
210 Note that GNU/Linux doesn't support little endian PPC hardware,
211 therefore the offset at which the real value of the VSCR register
212 is located will be always 12 bytes.
214 The layout is like this (where x is the actual value of the vscr reg): */
218 |.|.|.|.|.....|.|.|.|.||.|.|.|x||.|
219 <-------> <-------><-------><->
224 #define SIZEOF_VRREGS 33*16+4
226 typedef char gdb_vrregset_t
[SIZEOF_VRREGS
];
228 /* This is the layout of the POWER7 VSX registers and the way they overlap
229 with the existing FPR and VMX registers.
231 VSR doubleword 0 VSR doubleword 1
232 ----------------------------------------------------------------
234 ----------------------------------------------------------------
236 ----------------------------------------------------------------
239 ----------------------------------------------------------------
240 VSR[30] | FPR[30] | |
241 ----------------------------------------------------------------
242 VSR[31] | FPR[31] | |
243 ----------------------------------------------------------------
245 ----------------------------------------------------------------
247 ----------------------------------------------------------------
250 ----------------------------------------------------------------
252 ----------------------------------------------------------------
254 ----------------------------------------------------------------
256 VSX has 64 128bit registers. The first 32 registers overlap with
257 the FP registers (doubleword 0) and hence extend them with additional
258 64 bits (doubleword 1). The other 32 regs overlap with the VMX
260 #define SIZEOF_VSXREGS 32*8
262 typedef char gdb_vsxregset_t
[SIZEOF_VSXREGS
];
264 /* On PPC processors that support the Signal Processing Extension
265 (SPE) APU, the general-purpose registers are 64 bits long.
266 However, the ordinary Linux kernel PTRACE_PEEKUSER / PTRACE_POKEUSER
267 ptrace calls only access the lower half of each register, to allow
268 them to behave the same way they do on non-SPE systems. There's a
269 separate pair of calls, PTRACE_GETEVRREGS / PTRACE_SETEVRREGS, that
270 read and write the top halves of all the general-purpose registers
271 at once, along with some SPE-specific registers.
273 GDB itself continues to claim the general-purpose registers are 32
274 bits long. It has unnamed raw registers that hold the upper halves
275 of the gprs, and the full 64-bit SIMD views of the registers,
276 'ev0' -- 'ev31', are pseudo-registers that splice the top and
277 bottom halves together.
279 This is the structure filled in by PTRACE_GETEVRREGS and written to
280 the inferior's registers by PTRACE_SETEVRREGS. */
281 struct gdb_evrregset_t
283 unsigned long evr
[32];
284 unsigned long long acc
;
285 unsigned long spefscr
;
288 /* Non-zero if our kernel may support the PTRACE_GETVSXREGS and
289 PTRACE_SETVSXREGS requests, for reading and writing the VSX
290 POWER7 registers 0 through 31. Zero if we've tried one of them and
291 gotten an error. Note that VSX registers 32 through 63 overlap
292 with VR registers 0 through 31. */
293 int have_ptrace_getsetvsxregs
= 1;
295 /* Non-zero if our kernel may support the PTRACE_GETVRREGS and
296 PTRACE_SETVRREGS requests, for reading and writing the Altivec
297 registers. Zero if we've tried one of them and gotten an
299 int have_ptrace_getvrregs
= 1;
301 /* Non-zero if our kernel may support the PTRACE_GETEVRREGS and
302 PTRACE_SETEVRREGS requests, for reading and writing the SPE
303 registers. Zero if we've tried one of them and gotten an
305 int have_ptrace_getsetevrregs
= 1;
307 /* Non-zero if our kernel may support the PTRACE_GETREGS and
308 PTRACE_SETREGS requests, for reading and writing the
309 general-purpose registers. Zero if we've tried one of
310 them and gotten an error. */
311 int have_ptrace_getsetregs
= 1;
313 /* Non-zero if our kernel may support the PTRACE_GETFPREGS and
314 PTRACE_SETFPREGS requests, for reading and writing the
315 floating-pointers registers. Zero if we've tried one of
316 them and gotten an error. */
317 int have_ptrace_getsetfpregs
= 1;
320 /* registers layout, as presented by the ptrace interface:
321 PT_R0, PT_R1, PT_R2, PT_R3, PT_R4, PT_R5, PT_R6, PT_R7,
322 PT_R8, PT_R9, PT_R10, PT_R11, PT_R12, PT_R13, PT_R14, PT_R15,
323 PT_R16, PT_R17, PT_R18, PT_R19, PT_R20, PT_R21, PT_R22, PT_R23,
324 PT_R24, PT_R25, PT_R26, PT_R27, PT_R28, PT_R29, PT_R30, PT_R31,
325 PT_FPR0, PT_FPR0 + 2, PT_FPR0 + 4, PT_FPR0 + 6,
326 PT_FPR0 + 8, PT_FPR0 + 10, PT_FPR0 + 12, PT_FPR0 + 14,
327 PT_FPR0 + 16, PT_FPR0 + 18, PT_FPR0 + 20, PT_FPR0 + 22,
328 PT_FPR0 + 24, PT_FPR0 + 26, PT_FPR0 + 28, PT_FPR0 + 30,
329 PT_FPR0 + 32, PT_FPR0 + 34, PT_FPR0 + 36, PT_FPR0 + 38,
330 PT_FPR0 + 40, PT_FPR0 + 42, PT_FPR0 + 44, PT_FPR0 + 46,
331 PT_FPR0 + 48, PT_FPR0 + 50, PT_FPR0 + 52, PT_FPR0 + 54,
332 PT_FPR0 + 56, PT_FPR0 + 58, PT_FPR0 + 60, PT_FPR0 + 62,
333 PT_NIP, PT_MSR, PT_CCR, PT_LNK, PT_CTR, PT_XER, PT_MQ */
337 ppc_register_u_addr (struct gdbarch
*gdbarch
, int regno
)
340 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
341 /* NOTE: cagney/2003-11-25: This is the word size used by the ptrace
342 interface, and not the wordsize of the program's ABI. */
343 int wordsize
= sizeof (long);
345 /* General purpose registers occupy 1 slot each in the buffer. */
346 if (regno
>= tdep
->ppc_gp0_regnum
347 && regno
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
348 u_addr
= ((regno
- tdep
->ppc_gp0_regnum
+ PT_R0
) * wordsize
);
350 /* Floating point regs: eight bytes each in both 32- and 64-bit
351 ptrace interfaces. Thus, two slots each in 32-bit interface, one
352 slot each in 64-bit interface. */
353 if (tdep
->ppc_fp0_regnum
>= 0
354 && regno
>= tdep
->ppc_fp0_regnum
355 && regno
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
356 u_addr
= (PT_FPR0
* wordsize
) + ((regno
- tdep
->ppc_fp0_regnum
) * 8);
358 /* UISA special purpose registers: 1 slot each. */
359 if (regno
== gdbarch_pc_regnum (gdbarch
))
360 u_addr
= PT_NIP
* wordsize
;
361 if (regno
== tdep
->ppc_lr_regnum
)
362 u_addr
= PT_LNK
* wordsize
;
363 if (regno
== tdep
->ppc_cr_regnum
)
364 u_addr
= PT_CCR
* wordsize
;
365 if (regno
== tdep
->ppc_xer_regnum
)
366 u_addr
= PT_XER
* wordsize
;
367 if (regno
== tdep
->ppc_ctr_regnum
)
368 u_addr
= PT_CTR
* wordsize
;
370 if (regno
== tdep
->ppc_mq_regnum
)
371 u_addr
= PT_MQ
* wordsize
;
373 if (regno
== tdep
->ppc_ps_regnum
)
374 u_addr
= PT_MSR
* wordsize
;
375 if (regno
== PPC_ORIG_R3_REGNUM
)
376 u_addr
= PT_ORIG_R3
* wordsize
;
377 if (regno
== PPC_TRAP_REGNUM
)
378 u_addr
= PT_TRAP
* wordsize
;
379 if (tdep
->ppc_fpscr_regnum
>= 0
380 && regno
== tdep
->ppc_fpscr_regnum
)
382 /* NOTE: cagney/2005-02-08: On some 64-bit GNU/Linux systems the
383 kernel headers incorrectly contained the 32-bit definition of
384 PT_FPSCR. For the 32-bit definition, floating-point
385 registers occupy two 32-bit "slots", and the FPSCR lives in
386 the second half of such a slot-pair (hence +1). For 64-bit,
387 the FPSCR instead occupies the full 64-bit 2-word-slot and
388 hence no adjustment is necessary. Hack around this. */
389 if (wordsize
== 8 && PT_FPSCR
== (48 + 32 + 1))
390 u_addr
= (48 + 32) * wordsize
;
391 /* If the FPSCR is 64-bit wide, we need to fetch the whole 64-bit
392 slot and not just its second word. The PT_FPSCR supplied when
393 GDB is compiled as a 32-bit app doesn't reflect this. */
394 else if (wordsize
== 4 && register_size (gdbarch
, regno
) == 8
395 && PT_FPSCR
== (48 + 2*32 + 1))
396 u_addr
= (48 + 2*32) * wordsize
;
398 u_addr
= PT_FPSCR
* wordsize
;
403 /* The Linux kernel ptrace interface for POWER7 VSX registers uses the
404 registers set mechanism, as opposed to the interface for all the
405 other registers, that stores/fetches each register individually. */
407 fetch_vsx_register (struct regcache
*regcache
, int tid
, int regno
)
410 gdb_vsxregset_t regs
;
411 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
412 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
413 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
415 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
420 have_ptrace_getsetvsxregs
= 0;
423 perror_with_name (_("Unable to fetch VSX register"));
426 regcache_raw_supply (regcache
, regno
,
427 regs
+ (regno
- tdep
->ppc_vsr0_upper_regnum
)
431 /* The Linux kernel ptrace interface for AltiVec registers uses the
432 registers set mechanism, as opposed to the interface for all the
433 other registers, that stores/fetches each register individually. */
435 fetch_altivec_register (struct regcache
*regcache
, int tid
, int regno
)
440 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
441 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
442 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
444 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
449 have_ptrace_getvrregs
= 0;
452 perror_with_name (_("Unable to fetch AltiVec register"));
455 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
456 long on the hardware. We deal only with the lower 4 bytes of the
457 vector. VRSAVE is at the end of the array in a 4 bytes slot, so
458 there is no need to define an offset for it. */
459 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
460 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
462 regcache_raw_supply (regcache
, regno
,
464 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
467 /* Fetch the top 32 bits of TID's general-purpose registers and the
468 SPE-specific registers, and place the results in EVRREGSET. If we
469 don't support PTRACE_GETEVRREGS, then just fill EVRREGSET with
472 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
473 PTRACE_SETEVRREGS requests are supported is isolated here, and in
474 set_spe_registers. */
476 get_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
478 if (have_ptrace_getsetevrregs
)
480 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, evrregset
) >= 0)
484 /* EIO means that the PTRACE_GETEVRREGS request isn't supported;
485 we just return zeros. */
487 have_ptrace_getsetevrregs
= 0;
489 /* Anything else needs to be reported. */
490 perror_with_name (_("Unable to fetch SPE registers"));
494 memset (evrregset
, 0, sizeof (*evrregset
));
497 /* Supply values from TID for SPE-specific raw registers: the upper
498 halves of the GPRs, the accumulator, and the spefscr. REGNO must
499 be the number of an upper half register, acc, spefscr, or -1 to
500 supply the values of all registers. */
502 fetch_spe_register (struct regcache
*regcache
, int tid
, int regno
)
504 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
505 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
506 struct gdb_evrregset_t evrregs
;
508 gdb_assert (sizeof (evrregs
.evr
[0])
509 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
510 gdb_assert (sizeof (evrregs
.acc
)
511 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
512 gdb_assert (sizeof (evrregs
.spefscr
)
513 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
515 get_spe_registers (tid
, &evrregs
);
521 for (i
= 0; i
< ppc_num_gprs
; i
++)
522 regcache_raw_supply (regcache
, tdep
->ppc_ev0_upper_regnum
+ i
,
525 else if (tdep
->ppc_ev0_upper_regnum
<= regno
526 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
527 regcache_raw_supply (regcache
, regno
,
528 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
531 || regno
== tdep
->ppc_acc_regnum
)
532 regcache_raw_supply (regcache
, tdep
->ppc_acc_regnum
, &evrregs
.acc
);
535 || regno
== tdep
->ppc_spefscr_regnum
)
536 regcache_raw_supply (regcache
, tdep
->ppc_spefscr_regnum
,
541 fetch_register (struct regcache
*regcache
, int tid
, int regno
)
543 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
544 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
545 /* This isn't really an address. But ptrace thinks of it as one. */
546 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
547 int bytes_transferred
;
548 unsigned int offset
; /* Offset of registers within the u area. */
549 gdb_byte buf
[MAX_REGISTER_SIZE
];
551 if (altivec_register_p (gdbarch
, regno
))
553 /* If this is the first time through, or if it is not the first
554 time through, and we have comfirmed that there is kernel
555 support for such a ptrace request, then go and fetch the
557 if (have_ptrace_getvrregs
)
559 fetch_altivec_register (regcache
, tid
, regno
);
562 /* If we have discovered that there is no ptrace support for
563 AltiVec registers, fall through and return zeroes, because
564 regaddr will be -1 in this case. */
566 if (vsx_register_p (gdbarch
, regno
))
568 if (have_ptrace_getsetvsxregs
)
570 fetch_vsx_register (regcache
, tid
, regno
);
574 else if (spe_register_p (gdbarch
, regno
))
576 fetch_spe_register (regcache
, tid
, regno
);
582 memset (buf
, '\0', register_size (gdbarch
, regno
)); /* Supply zeroes */
583 regcache_raw_supply (regcache
, regno
, buf
);
587 /* Read the raw register using sizeof(long) sized chunks. On a
588 32-bit platform, 64-bit floating-point registers will require two
590 for (bytes_transferred
= 0;
591 bytes_transferred
< register_size (gdbarch
, regno
);
592 bytes_transferred
+= sizeof (long))
597 l
= ptrace (PTRACE_PEEKUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, 0);
598 regaddr
+= sizeof (long);
602 xsnprintf (message
, sizeof (message
), "reading register %s (#%d)",
603 gdbarch_register_name (gdbarch
, regno
), regno
);
604 perror_with_name (message
);
606 memcpy (&buf
[bytes_transferred
], &l
, sizeof (l
));
609 /* Now supply the register. Keep in mind that the regcache's idea
610 of the register's size may not be a multiple of sizeof
612 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
614 /* Little-endian values are always found at the left end of the
615 bytes transferred. */
616 regcache_raw_supply (regcache
, regno
, buf
);
618 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
620 /* Big-endian values are found at the right end of the bytes
622 size_t padding
= (bytes_transferred
- register_size (gdbarch
, regno
));
623 regcache_raw_supply (regcache
, regno
, buf
+ padding
);
626 internal_error (__FILE__
, __LINE__
,
627 _("fetch_register: unexpected byte order: %d"),
628 gdbarch_byte_order (gdbarch
));
632 supply_vsxregset (struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
635 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
636 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
637 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
639 for (i
= 0; i
< ppc_num_vshrs
; i
++)
641 regcache_raw_supply (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
642 *vsxregsetp
+ i
* vsxregsize
);
647 supply_vrregset (struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
650 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
651 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
652 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
653 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
654 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
656 for (i
= 0; i
< num_of_vrregs
; i
++)
658 /* The last 2 registers of this set are only 32 bit long, not
659 128. However an offset is necessary only for VSCR because it
660 occupies a whole vector, while VRSAVE occupies a full 4 bytes
662 if (i
== (num_of_vrregs
- 2))
663 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
664 *vrregsetp
+ i
* vrregsize
+ offset
);
666 regcache_raw_supply (regcache
, tdep
->ppc_vr0_regnum
+ i
,
667 *vrregsetp
+ i
* vrregsize
);
672 fetch_vsx_registers (struct regcache
*regcache
, int tid
)
675 gdb_vsxregset_t regs
;
677 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
682 have_ptrace_getsetvsxregs
= 0;
685 perror_with_name (_("Unable to fetch VSX registers"));
687 supply_vsxregset (regcache
, ®s
);
691 fetch_altivec_registers (struct regcache
*regcache
, int tid
)
696 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
701 have_ptrace_getvrregs
= 0;
704 perror_with_name (_("Unable to fetch AltiVec registers"));
706 supply_vrregset (regcache
, ®s
);
709 /* This function actually issues the request to ptrace, telling
710 it to get all general-purpose registers and put them into the
713 If the ptrace request does not exist, this function returns 0
714 and properly sets the have_ptrace_* flag. If the request fails,
715 this function calls perror_with_name. Otherwise, if the request
716 succeeds, then the regcache gets filled and 1 is returned. */
718 fetch_all_gp_regs (struct regcache
*regcache
, int tid
)
720 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
721 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
722 gdb_gregset_t gregset
;
724 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
728 have_ptrace_getsetregs
= 0;
731 perror_with_name (_("Couldn't get general-purpose registers."));
734 supply_gregset (regcache
, (const gdb_gregset_t
*) &gregset
);
739 /* This is a wrapper for the fetch_all_gp_regs function. It is
740 responsible for verifying if this target has the ptrace request
741 that can be used to fetch all general-purpose registers at one
742 shot. If it doesn't, then we should fetch them using the
743 old-fashioned way, which is to iterate over the registers and
744 request them one by one. */
746 fetch_gp_regs (struct regcache
*regcache
, int tid
)
748 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
749 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
752 if (have_ptrace_getsetregs
)
753 if (fetch_all_gp_regs (regcache
, tid
))
756 /* If we've hit this point, it doesn't really matter which
757 architecture we are using. We just need to read the
758 registers in the "old-fashioned way". */
759 for (i
= 0; i
< ppc_num_gprs
; i
++)
760 fetch_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
763 /* This function actually issues the request to ptrace, telling
764 it to get all floating-point registers and put them into the
767 If the ptrace request does not exist, this function returns 0
768 and properly sets the have_ptrace_* flag. If the request fails,
769 this function calls perror_with_name. Otherwise, if the request
770 succeeds, then the regcache gets filled and 1 is returned. */
772 fetch_all_fp_regs (struct regcache
*regcache
, int tid
)
774 gdb_fpregset_t fpregs
;
776 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
780 have_ptrace_getsetfpregs
= 0;
783 perror_with_name (_("Couldn't get floating-point registers."));
786 supply_fpregset (regcache
, (const gdb_fpregset_t
*) &fpregs
);
791 /* This is a wrapper for the fetch_all_fp_regs function. It is
792 responsible for verifying if this target has the ptrace request
793 that can be used to fetch all floating-point registers at one
794 shot. If it doesn't, then we should fetch them using the
795 old-fashioned way, which is to iterate over the registers and
796 request them one by one. */
798 fetch_fp_regs (struct regcache
*regcache
, int tid
)
800 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
801 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
804 if (have_ptrace_getsetfpregs
)
805 if (fetch_all_fp_regs (regcache
, tid
))
808 /* If we've hit this point, it doesn't really matter which
809 architecture we are using. We just need to read the
810 registers in the "old-fashioned way". */
811 for (i
= 0; i
< ppc_num_fprs
; i
++)
812 fetch_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
816 fetch_ppc_registers (struct regcache
*regcache
, int tid
)
819 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
820 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
822 fetch_gp_regs (regcache
, tid
);
823 if (tdep
->ppc_fp0_regnum
>= 0)
824 fetch_fp_regs (regcache
, tid
);
825 fetch_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
826 if (tdep
->ppc_ps_regnum
!= -1)
827 fetch_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
828 if (tdep
->ppc_cr_regnum
!= -1)
829 fetch_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
830 if (tdep
->ppc_lr_regnum
!= -1)
831 fetch_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
832 if (tdep
->ppc_ctr_regnum
!= -1)
833 fetch_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
834 if (tdep
->ppc_xer_regnum
!= -1)
835 fetch_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
836 if (tdep
->ppc_mq_regnum
!= -1)
837 fetch_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
838 if (ppc_linux_trap_reg_p (gdbarch
))
840 fetch_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
841 fetch_register (regcache
, tid
, PPC_TRAP_REGNUM
);
843 if (tdep
->ppc_fpscr_regnum
!= -1)
844 fetch_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
845 if (have_ptrace_getvrregs
)
846 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
847 fetch_altivec_registers (regcache
, tid
);
848 if (have_ptrace_getsetvsxregs
)
849 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
850 fetch_vsx_registers (regcache
, tid
);
851 if (tdep
->ppc_ev0_upper_regnum
>= 0)
852 fetch_spe_register (regcache
, tid
, -1);
855 /* Fetch registers from the child process. Fetch all registers if
856 regno == -1, otherwise fetch all general registers or all floating
857 point registers depending upon the value of regno. */
859 ppc_linux_fetch_inferior_registers (struct target_ops
*ops
,
860 struct regcache
*regcache
, int regno
)
862 /* Overload thread id onto process id. */
863 int tid
= TIDGET (inferior_ptid
);
865 /* No thread id, just use process id. */
867 tid
= PIDGET (inferior_ptid
);
870 fetch_ppc_registers (regcache
, tid
);
872 fetch_register (regcache
, tid
, regno
);
875 /* Store one VSX register. */
877 store_vsx_register (const struct regcache
*regcache
, int tid
, int regno
)
880 gdb_vsxregset_t regs
;
881 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
882 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
883 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
885 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
890 have_ptrace_getsetvsxregs
= 0;
893 perror_with_name (_("Unable to fetch VSX register"));
896 regcache_raw_collect (regcache
, regno
, regs
+
897 (regno
- tdep
->ppc_vsr0_upper_regnum
) * vsxregsize
);
899 ret
= ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
);
901 perror_with_name (_("Unable to store VSX register"));
904 /* Store one register. */
906 store_altivec_register (const struct regcache
*regcache
, int tid
, int regno
)
911 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
912 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
913 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
915 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
920 have_ptrace_getvrregs
= 0;
923 perror_with_name (_("Unable to fetch AltiVec register"));
926 /* VSCR is fetched as a 16 bytes quantity, but it is really 4 bytes
927 long on the hardware. */
928 if (regno
== (tdep
->ppc_vrsave_regnum
- 1))
929 offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
931 regcache_raw_collect (regcache
, regno
,
933 - tdep
->ppc_vr0_regnum
) * vrregsize
+ offset
);
935 ret
= ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
);
937 perror_with_name (_("Unable to store AltiVec register"));
940 /* Assuming TID referrs to an SPE process, set the top halves of TID's
941 general-purpose registers and its SPE-specific registers to the
942 values in EVRREGSET. If we don't support PTRACE_SETEVRREGS, do
945 All the logic to deal with whether or not the PTRACE_GETEVRREGS and
946 PTRACE_SETEVRREGS requests are supported is isolated here, and in
947 get_spe_registers. */
949 set_spe_registers (int tid
, struct gdb_evrregset_t
*evrregset
)
951 if (have_ptrace_getsetevrregs
)
953 if (ptrace (PTRACE_SETEVRREGS
, tid
, 0, evrregset
) >= 0)
957 /* EIO means that the PTRACE_SETEVRREGS request isn't
958 supported; we fail silently, and don't try the call
961 have_ptrace_getsetevrregs
= 0;
963 /* Anything else needs to be reported. */
964 perror_with_name (_("Unable to set SPE registers"));
969 /* Write GDB's value for the SPE-specific raw register REGNO to TID.
970 If REGNO is -1, write the values of all the SPE-specific
973 store_spe_register (const struct regcache
*regcache
, int tid
, int regno
)
975 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
976 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
977 struct gdb_evrregset_t evrregs
;
979 gdb_assert (sizeof (evrregs
.evr
[0])
980 == register_size (gdbarch
, tdep
->ppc_ev0_upper_regnum
));
981 gdb_assert (sizeof (evrregs
.acc
)
982 == register_size (gdbarch
, tdep
->ppc_acc_regnum
));
983 gdb_assert (sizeof (evrregs
.spefscr
)
984 == register_size (gdbarch
, tdep
->ppc_spefscr_regnum
));
987 /* Since we're going to write out every register, the code below
988 should store to every field of evrregs; if that doesn't happen,
989 make it obvious by initializing it with suspicious values. */
990 memset (&evrregs
, 42, sizeof (evrregs
));
992 /* We can only read and write the entire EVR register set at a
993 time, so to write just a single register, we do a
994 read-modify-write maneuver. */
995 get_spe_registers (tid
, &evrregs
);
1001 for (i
= 0; i
< ppc_num_gprs
; i
++)
1002 regcache_raw_collect (regcache
,
1003 tdep
->ppc_ev0_upper_regnum
+ i
,
1006 else if (tdep
->ppc_ev0_upper_regnum
<= regno
1007 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
1008 regcache_raw_collect (regcache
, regno
,
1009 &evrregs
.evr
[regno
- tdep
->ppc_ev0_upper_regnum
]);
1012 || regno
== tdep
->ppc_acc_regnum
)
1013 regcache_raw_collect (regcache
,
1014 tdep
->ppc_acc_regnum
,
1018 || regno
== tdep
->ppc_spefscr_regnum
)
1019 regcache_raw_collect (regcache
,
1020 tdep
->ppc_spefscr_regnum
,
1023 /* Write back the modified register set. */
1024 set_spe_registers (tid
, &evrregs
);
1028 store_register (const struct regcache
*regcache
, int tid
, int regno
)
1030 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1031 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1032 /* This isn't really an address. But ptrace thinks of it as one. */
1033 CORE_ADDR regaddr
= ppc_register_u_addr (gdbarch
, regno
);
1035 size_t bytes_to_transfer
;
1036 gdb_byte buf
[MAX_REGISTER_SIZE
];
1038 if (altivec_register_p (gdbarch
, regno
))
1040 store_altivec_register (regcache
, tid
, regno
);
1043 if (vsx_register_p (gdbarch
, regno
))
1045 store_vsx_register (regcache
, tid
, regno
);
1048 else if (spe_register_p (gdbarch
, regno
))
1050 store_spe_register (regcache
, tid
, regno
);
1057 /* First collect the register. Keep in mind that the regcache's
1058 idea of the register's size may not be a multiple of sizeof
1060 memset (buf
, 0, sizeof buf
);
1061 bytes_to_transfer
= align_up (register_size (gdbarch
, regno
), sizeof (long));
1062 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1064 /* Little-endian values always sit at the left end of the buffer. */
1065 regcache_raw_collect (regcache
, regno
, buf
);
1067 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
1069 /* Big-endian values sit at the right end of the buffer. */
1070 size_t padding
= (bytes_to_transfer
- register_size (gdbarch
, regno
));
1071 regcache_raw_collect (regcache
, regno
, buf
+ padding
);
1074 for (i
= 0; i
< bytes_to_transfer
; i
+= sizeof (long))
1078 memcpy (&l
, &buf
[i
], sizeof (l
));
1080 ptrace (PTRACE_POKEUSER
, tid
, (PTRACE_TYPE_ARG3
) regaddr
, l
);
1081 regaddr
+= sizeof (long);
1084 && (regno
== tdep
->ppc_fpscr_regnum
1085 || regno
== PPC_ORIG_R3_REGNUM
1086 || regno
== PPC_TRAP_REGNUM
))
1088 /* Some older kernel versions don't allow fpscr, orig_r3
1089 or trap to be written. */
1096 xsnprintf (message
, sizeof (message
), "writing register %s (#%d)",
1097 gdbarch_register_name (gdbarch
, regno
), regno
);
1098 perror_with_name (message
);
1104 fill_vsxregset (const struct regcache
*regcache
, gdb_vsxregset_t
*vsxregsetp
)
1107 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1108 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1109 int vsxregsize
= register_size (gdbarch
, tdep
->ppc_vsr0_upper_regnum
);
1111 for (i
= 0; i
< ppc_num_vshrs
; i
++)
1112 regcache_raw_collect (regcache
, tdep
->ppc_vsr0_upper_regnum
+ i
,
1113 *vsxregsetp
+ i
* vsxregsize
);
1117 fill_vrregset (const struct regcache
*regcache
, gdb_vrregset_t
*vrregsetp
)
1120 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1121 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1122 int num_of_vrregs
= tdep
->ppc_vrsave_regnum
- tdep
->ppc_vr0_regnum
+ 1;
1123 int vrregsize
= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
1124 int offset
= vrregsize
- register_size (gdbarch
, tdep
->ppc_vrsave_regnum
);
1126 for (i
= 0; i
< num_of_vrregs
; i
++)
1128 /* The last 2 registers of this set are only 32 bit long, not
1129 128, but only VSCR is fetched as a 16 bytes quantity. */
1130 if (i
== (num_of_vrregs
- 2))
1131 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1132 *vrregsetp
+ i
* vrregsize
+ offset
);
1134 regcache_raw_collect (regcache
, tdep
->ppc_vr0_regnum
+ i
,
1135 *vrregsetp
+ i
* vrregsize
);
1140 store_vsx_registers (const struct regcache
*regcache
, int tid
)
1143 gdb_vsxregset_t regs
;
1145 ret
= ptrace (PTRACE_GETVSXREGS
, tid
, 0, ®s
);
1150 have_ptrace_getsetvsxregs
= 0;
1153 perror_with_name (_("Couldn't get VSX registers"));
1156 fill_vsxregset (regcache
, ®s
);
1158 if (ptrace (PTRACE_SETVSXREGS
, tid
, 0, ®s
) < 0)
1159 perror_with_name (_("Couldn't write VSX registers"));
1163 store_altivec_registers (const struct regcache
*regcache
, int tid
)
1166 gdb_vrregset_t regs
;
1168 ret
= ptrace (PTRACE_GETVRREGS
, tid
, 0, ®s
);
1173 have_ptrace_getvrregs
= 0;
1176 perror_with_name (_("Couldn't get AltiVec registers"));
1179 fill_vrregset (regcache
, ®s
);
1181 if (ptrace (PTRACE_SETVRREGS
, tid
, 0, ®s
) < 0)
1182 perror_with_name (_("Couldn't write AltiVec registers"));
1185 /* This function actually issues the request to ptrace, telling
1186 it to store all general-purpose registers present in the specified
1189 If the ptrace request does not exist, this function returns 0
1190 and properly sets the have_ptrace_* flag. If the request fails,
1191 this function calls perror_with_name. Otherwise, if the request
1192 succeeds, then the regcache is stored and 1 is returned. */
1194 store_all_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1196 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1197 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1198 gdb_gregset_t gregset
;
1200 if (ptrace (PTRACE_GETREGS
, tid
, 0, (void *) &gregset
) < 0)
1204 have_ptrace_getsetregs
= 0;
1207 perror_with_name (_("Couldn't get general-purpose registers."));
1210 fill_gregset (regcache
, &gregset
, regno
);
1212 if (ptrace (PTRACE_SETREGS
, tid
, 0, (void *) &gregset
) < 0)
1216 have_ptrace_getsetregs
= 0;
1219 perror_with_name (_("Couldn't set general-purpose registers."));
1225 /* This is a wrapper for the store_all_gp_regs function. It is
1226 responsible for verifying if this target has the ptrace request
1227 that can be used to store all general-purpose registers at one
1228 shot. If it doesn't, then we should store them using the
1229 old-fashioned way, which is to iterate over the registers and
1230 store them one by one. */
1232 store_gp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1234 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1238 if (have_ptrace_getsetregs
)
1239 if (store_all_gp_regs (regcache
, tid
, regno
))
1242 /* If we hit this point, it doesn't really matter which
1243 architecture we are using. We just need to store the
1244 registers in the "old-fashioned way". */
1245 for (i
= 0; i
< ppc_num_gprs
; i
++)
1246 store_register (regcache
, tid
, tdep
->ppc_gp0_regnum
+ i
);
1249 /* This function actually issues the request to ptrace, telling
1250 it to store all floating-point registers present in the specified
1253 If the ptrace request does not exist, this function returns 0
1254 and properly sets the have_ptrace_* flag. If the request fails,
1255 this function calls perror_with_name. Otherwise, if the request
1256 succeeds, then the regcache is stored and 1 is returned. */
1258 store_all_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1260 gdb_fpregset_t fpregs
;
1262 if (ptrace (PTRACE_GETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1266 have_ptrace_getsetfpregs
= 0;
1269 perror_with_name (_("Couldn't get floating-point registers."));
1272 fill_fpregset (regcache
, &fpregs
, regno
);
1274 if (ptrace (PTRACE_SETFPREGS
, tid
, 0, (void *) &fpregs
) < 0)
1278 have_ptrace_getsetfpregs
= 0;
1281 perror_with_name (_("Couldn't set floating-point registers."));
1287 /* This is a wrapper for the store_all_fp_regs function. It is
1288 responsible for verifying if this target has the ptrace request
1289 that can be used to store all floating-point registers at one
1290 shot. If it doesn't, then we should store them using the
1291 old-fashioned way, which is to iterate over the registers and
1292 store them one by one. */
1294 store_fp_regs (const struct regcache
*regcache
, int tid
, int regno
)
1296 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1297 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1300 if (have_ptrace_getsetfpregs
)
1301 if (store_all_fp_regs (regcache
, tid
, regno
))
1304 /* If we hit this point, it doesn't really matter which
1305 architecture we are using. We just need to store the
1306 registers in the "old-fashioned way". */
1307 for (i
= 0; i
< ppc_num_fprs
; i
++)
1308 store_register (regcache
, tid
, tdep
->ppc_fp0_regnum
+ i
);
1312 store_ppc_registers (const struct regcache
*regcache
, int tid
)
1315 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1316 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1318 store_gp_regs (regcache
, tid
, -1);
1319 if (tdep
->ppc_fp0_regnum
>= 0)
1320 store_fp_regs (regcache
, tid
, -1);
1321 store_register (regcache
, tid
, gdbarch_pc_regnum (gdbarch
));
1322 if (tdep
->ppc_ps_regnum
!= -1)
1323 store_register (regcache
, tid
, tdep
->ppc_ps_regnum
);
1324 if (tdep
->ppc_cr_regnum
!= -1)
1325 store_register (regcache
, tid
, tdep
->ppc_cr_regnum
);
1326 if (tdep
->ppc_lr_regnum
!= -1)
1327 store_register (regcache
, tid
, tdep
->ppc_lr_regnum
);
1328 if (tdep
->ppc_ctr_regnum
!= -1)
1329 store_register (regcache
, tid
, tdep
->ppc_ctr_regnum
);
1330 if (tdep
->ppc_xer_regnum
!= -1)
1331 store_register (regcache
, tid
, tdep
->ppc_xer_regnum
);
1332 if (tdep
->ppc_mq_regnum
!= -1)
1333 store_register (regcache
, tid
, tdep
->ppc_mq_regnum
);
1334 if (tdep
->ppc_fpscr_regnum
!= -1)
1335 store_register (regcache
, tid
, tdep
->ppc_fpscr_regnum
);
1336 if (ppc_linux_trap_reg_p (gdbarch
))
1338 store_register (regcache
, tid
, PPC_ORIG_R3_REGNUM
);
1339 store_register (regcache
, tid
, PPC_TRAP_REGNUM
);
1341 if (have_ptrace_getvrregs
)
1342 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
1343 store_altivec_registers (regcache
, tid
);
1344 if (have_ptrace_getsetvsxregs
)
1345 if (tdep
->ppc_vsr0_upper_regnum
!= -1)
1346 store_vsx_registers (regcache
, tid
);
1347 if (tdep
->ppc_ev0_upper_regnum
>= 0)
1348 store_spe_register (regcache
, tid
, -1);
1351 /* Fetch the AT_HWCAP entry from the aux vector. */
1352 static unsigned long
1353 ppc_linux_get_hwcap (void)
1357 if (target_auxv_search (¤t_target
, AT_HWCAP
, &field
))
1358 return (unsigned long) field
;
1363 /* The cached DABR value, to install in new threads.
1364 This variable is used when we are dealing with non-BookE
1366 static long saved_dabr_value
;
1368 /* Global structure that will store information about the available
1369 features on this BookE processor. */
1370 static struct ppc_debug_info booke_debug_info
;
1372 /* Global variable that holds the maximum number of slots that the
1373 kernel will use. This is only used when the processor is BookE. */
1374 static size_t max_slots_number
= 0;
1376 struct hw_break_tuple
1379 struct ppc_hw_breakpoint
*hw_break
;
1382 /* This is an internal VEC created to store information about *points inserted
1383 for each thread. This is used for BookE processors. */
1384 typedef struct thread_points
1386 /* The TID to which this *point relates. */
1388 /* Information about the *point, such as its address, type, etc.
1390 Each element inside this vector corresponds to a hardware
1391 breakpoint or watchpoint in the thread represented by TID. The maximum
1392 size of these vector is MAX_SLOTS_NUMBER. If the hw_break element of
1393 the tuple is NULL, then the position in the vector is free. */
1394 struct hw_break_tuple
*hw_breaks
;
1396 DEF_VEC_P (thread_points_p
);
1398 VEC(thread_points_p
) *ppc_threads
= NULL
;
1400 /* The version of the kernel interface that we will use if the processor is
1402 #define PPC_DEBUG_CURRENT_VERSION 1
1404 /* Returns non-zero if we support the ptrace interface which enables
1405 booke debugging resources. */
1407 have_ptrace_booke_interface (void)
1409 static int have_ptrace_booke_interface
= -1;
1411 if (have_ptrace_booke_interface
== -1)
1415 tid
= TIDGET (inferior_ptid
);
1417 tid
= PIDGET (inferior_ptid
);
1419 /* Check for kernel support for BOOKE debug registers. */
1420 if (ptrace (PPC_PTRACE_GETHWDBGINFO
, tid
, 0, &booke_debug_info
) >= 0)
1422 /* Check whether ptrace BOOKE interface is functional and
1423 provides any supported feature. */
1424 if (booke_debug_info
.features
!= 0)
1426 have_ptrace_booke_interface
= 1;
1427 max_slots_number
= booke_debug_info
.num_instruction_bps
1428 + booke_debug_info
.num_data_bps
1429 + booke_debug_info
.num_condition_regs
;
1430 return have_ptrace_booke_interface
;
1433 /* Old school interface and no BOOKE debug registers support. */
1434 have_ptrace_booke_interface
= 0;
1435 memset (&booke_debug_info
, 0, sizeof (struct ppc_debug_info
));
1438 return have_ptrace_booke_interface
;
1442 ppc_linux_can_use_hw_breakpoint (int type
, int cnt
, int ot
)
1444 int total_hw_wp
, total_hw_bp
;
1446 if (have_ptrace_booke_interface ())
1448 /* For PPC BookE processors, the number of available hardware
1449 watchpoints and breakpoints is stored at the booke_debug_info
1451 total_hw_bp
= booke_debug_info
.num_instruction_bps
;
1452 total_hw_wp
= booke_debug_info
.num_data_bps
;
1456 /* For PPC server processors, we accept 1 hardware watchpoint and 0
1457 hardware breakpoints. */
1462 if (type
== bp_hardware_watchpoint
|| type
== bp_read_watchpoint
1463 || type
== bp_access_watchpoint
|| type
== bp_watchpoint
)
1465 if (cnt
+ ot
> total_hw_wp
)
1468 else if (type
== bp_hardware_breakpoint
)
1470 if (cnt
> total_hw_bp
)
1474 if (!have_ptrace_booke_interface ())
1477 ptid_t ptid
= inferior_ptid
;
1479 /* We need to know whether ptrace supports PTRACE_SET_DEBUGREG
1480 and whether the target has DABR. If either answer is no, the
1481 ptrace call will return -1. Fail in that case. */
1482 tid
= TIDGET (ptid
);
1484 tid
= PIDGET (ptid
);
1486 if (ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, 0) == -1)
1494 ppc_linux_region_ok_for_hw_watchpoint (CORE_ADDR addr
, int len
)
1496 /* Handle sub-8-byte quantities. */
1500 /* The new BookE ptrace interface tells if there are alignment restrictions
1501 for watchpoints in the processors. In that case, we use that information
1502 to determine the hardcoded watchable region for watchpoints. */
1503 if (have_ptrace_booke_interface ())
1505 /* Embedded DAC-based processors, like the PowerPC 440 have ranged
1506 watchpoints and can watch any access within an arbitrary memory
1507 region. This is useful to watch arrays and structs, for instance. It
1508 takes two hardware watchpoints though. */
1510 && booke_debug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
1511 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1513 /* Server processors provide one hardware watchpoint and addr+len should
1514 fall in the watchable region provided by the ptrace interface. */
1515 if (booke_debug_info
.data_bp_alignment
1516 && (addr
+ len
> (addr
& ~(booke_debug_info
.data_bp_alignment
- 1))
1517 + booke_debug_info
.data_bp_alignment
))
1520 /* addr+len must fall in the 8 byte watchable region for DABR-based
1521 processors (i.e., server processors). Without the new BookE ptrace
1522 interface, DAC-based processors (i.e., embedded processors) will use
1523 addresses aligned to 4-bytes due to the way the read/write flags are
1524 passed in the old ptrace interface. */
1525 else if (((ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
1526 && (addr
+ len
) > (addr
& ~3) + 4)
1527 || (addr
+ len
) > (addr
& ~7) + 8)
1533 /* This function compares two ppc_hw_breakpoint structs field-by-field. */
1535 booke_cmp_hw_point (struct ppc_hw_breakpoint
*a
, struct ppc_hw_breakpoint
*b
)
1537 return (a
->trigger_type
== b
->trigger_type
1538 && a
->addr_mode
== b
->addr_mode
1539 && a
->condition_mode
== b
->condition_mode
1540 && a
->addr
== b
->addr
1541 && a
->addr2
== b
->addr2
1542 && a
->condition_value
== b
->condition_value
);
1545 /* This function can be used to retrieve a thread_points by the TID of the
1546 related process/thread. If nothing has been found, and ALLOC_NEW is 0,
1547 it returns NULL. If ALLOC_NEW is non-zero, a new thread_points for the
1548 provided TID will be created and returned. */
1549 static struct thread_points
*
1550 booke_find_thread_points_by_tid (int tid
, int alloc_new
)
1553 struct thread_points
*t
;
1555 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, t
); i
++)
1561 /* Do we need to allocate a new point_item
1562 if the wanted one does not exist? */
1565 t
= xmalloc (sizeof (struct thread_points
));
1567 = xzalloc (max_slots_number
* sizeof (struct hw_break_tuple
));
1569 VEC_safe_push (thread_points_p
, ppc_threads
, t
);
1575 /* This function is a generic wrapper that is responsible for inserting a
1576 *point (i.e., calling `ptrace' in order to issue the request to the
1577 kernel) and registering it internally in GDB. */
1579 booke_insert_point (struct ppc_hw_breakpoint
*b
, int tid
)
1583 struct ppc_hw_breakpoint
*p
= xmalloc (sizeof (struct ppc_hw_breakpoint
));
1584 struct hw_break_tuple
*hw_breaks
;
1585 struct cleanup
*c
= make_cleanup (xfree
, p
);
1586 struct thread_points
*t
;
1587 struct hw_break_tuple
*tuple
;
1589 memcpy (p
, b
, sizeof (struct ppc_hw_breakpoint
));
1592 slot
= ptrace (PPC_PTRACE_SETHWDEBUG
, tid
, 0, p
);
1594 perror_with_name (_("Unexpected error setting breakpoint or watchpoint"));
1596 /* Everything went fine, so we have to register this *point. */
1597 t
= booke_find_thread_points_by_tid (tid
, 1);
1598 gdb_assert (t
!= NULL
);
1599 hw_breaks
= t
->hw_breaks
;
1601 /* Find a free element in the hw_breaks vector. */
1602 for (i
= 0; i
< max_slots_number
; i
++)
1603 if (hw_breaks
[i
].hw_break
== NULL
)
1605 hw_breaks
[i
].slot
= slot
;
1606 hw_breaks
[i
].hw_break
= p
;
1610 gdb_assert (i
!= max_slots_number
);
1612 discard_cleanups (c
);
1615 /* This function is a generic wrapper that is responsible for removing a
1616 *point (i.e., calling `ptrace' in order to issue the request to the
1617 kernel), and unregistering it internally at GDB. */
1619 booke_remove_point (struct ppc_hw_breakpoint
*b
, int tid
)
1622 struct hw_break_tuple
*hw_breaks
;
1623 struct thread_points
*t
;
1625 t
= booke_find_thread_points_by_tid (tid
, 0);
1626 gdb_assert (t
!= NULL
);
1627 hw_breaks
= t
->hw_breaks
;
1629 for (i
= 0; i
< max_slots_number
; i
++)
1630 if (hw_breaks
[i
].hw_break
&& booke_cmp_hw_point (hw_breaks
[i
].hw_break
, b
))
1633 gdb_assert (i
!= max_slots_number
);
1635 /* We have to ignore ENOENT errors because the kernel implements hardware
1636 breakpoints/watchpoints as "one-shot", that is, they are automatically
1637 deleted when hit. */
1639 if (ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
) < 0)
1640 if (errno
!= ENOENT
)
1641 perror_with_name (_("Unexpected error deleting "
1642 "breakpoint or watchpoint"));
1644 xfree (hw_breaks
[i
].hw_break
);
1645 hw_breaks
[i
].hw_break
= NULL
;
1648 /* Return the number of registers needed for a ranged breakpoint. */
1651 ppc_linux_ranged_break_num_registers (struct target_ops
*target
)
1653 return ((have_ptrace_booke_interface ()
1654 && booke_debug_info
.features
& PPC_DEBUG_FEATURE_INSN_BP_RANGE
)?
1658 /* Insert the hardware breakpoint described by BP_TGT. Returns 0 for
1659 success, 1 if hardware breakpoints are not supported or -1 for failure. */
1662 ppc_linux_insert_hw_breakpoint (struct gdbarch
*gdbarch
,
1663 struct bp_target_info
*bp_tgt
)
1665 struct lwp_info
*lp
;
1666 struct ppc_hw_breakpoint p
;
1668 if (!have_ptrace_booke_interface ())
1671 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1672 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1673 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1674 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1675 p
.condition_value
= 0;
1679 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1681 /* The breakpoint will trigger if the address of the instruction is
1682 within the defined range, as follows: p.addr <= address < p.addr2. */
1683 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1687 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1692 booke_insert_point (&p
, TIDGET (lp
->ptid
));
1698 ppc_linux_remove_hw_breakpoint (struct gdbarch
*gdbarch
,
1699 struct bp_target_info
*bp_tgt
)
1701 struct lwp_info
*lp
;
1702 struct ppc_hw_breakpoint p
;
1704 if (!have_ptrace_booke_interface ())
1707 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1708 p
.trigger_type
= PPC_BREAKPOINT_TRIGGER_EXECUTE
;
1709 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1710 p
.addr
= (uint64_t) bp_tgt
->placed_address
;
1711 p
.condition_value
= 0;
1715 p
.addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
1717 /* The breakpoint will trigger if the address of the instruction is within
1718 the defined range, as follows: p.addr <= address < p.addr2. */
1719 p
.addr2
= (uint64_t) bp_tgt
->placed_address
+ bp_tgt
->length
;
1723 p
.addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
1728 booke_remove_point (&p
, TIDGET (lp
->ptid
));
1734 get_trigger_type (int rw
)
1739 t
= PPC_BREAKPOINT_TRIGGER_READ
;
1740 else if (rw
== hw_write
)
1741 t
= PPC_BREAKPOINT_TRIGGER_WRITE
;
1743 t
= PPC_BREAKPOINT_TRIGGER_READ
| PPC_BREAKPOINT_TRIGGER_WRITE
;
1748 /* Insert a new masked watchpoint at ADDR using the mask MASK.
1749 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1750 or hw_access for an access watchpoint. Returns 0 on success and throws
1751 an error on failure. */
1754 ppc_linux_insert_mask_watchpoint (struct target_ops
*ops
, CORE_ADDR addr
,
1755 CORE_ADDR mask
, int rw
)
1757 struct lwp_info
*lp
;
1758 struct ppc_hw_breakpoint p
;
1760 gdb_assert (have_ptrace_booke_interface ());
1762 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1763 p
.trigger_type
= get_trigger_type (rw
);
1764 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1765 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1768 p
.condition_value
= 0;
1771 booke_insert_point (&p
, TIDGET (lp
->ptid
));
1776 /* Remove a masked watchpoint at ADDR with the mask MASK.
1777 RW may be hw_read for a read watchpoint, hw_write for a write watchpoint
1778 or hw_access for an access watchpoint. Returns 0 on success and throws
1779 an error on failure. */
1782 ppc_linux_remove_mask_watchpoint (struct target_ops
*ops
, CORE_ADDR addr
,
1783 CORE_ADDR mask
, int rw
)
1785 struct lwp_info
*lp
;
1786 struct ppc_hw_breakpoint p
;
1788 gdb_assert (have_ptrace_booke_interface ());
1790 p
.version
= PPC_DEBUG_CURRENT_VERSION
;
1791 p
.trigger_type
= get_trigger_type (rw
);
1792 p
.addr_mode
= PPC_BREAKPOINT_MODE_MASK
;
1793 p
.condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
1796 p
.condition_value
= 0;
1799 booke_remove_point (&p
, TIDGET (lp
->ptid
));
1804 /* Check whether we have at least one free DVC register. */
1806 can_use_watchpoint_cond_accel (void)
1808 struct thread_points
*p
;
1809 int tid
= TIDGET (inferior_ptid
);
1810 int cnt
= booke_debug_info
.num_condition_regs
, i
;
1811 CORE_ADDR tmp_value
;
1813 if (!have_ptrace_booke_interface () || cnt
== 0)
1816 p
= booke_find_thread_points_by_tid (tid
, 0);
1820 for (i
= 0; i
< max_slots_number
; i
++)
1821 if (p
->hw_breaks
[i
].hw_break
!= NULL
1822 && (p
->hw_breaks
[i
].hw_break
->condition_mode
1823 != PPC_BREAKPOINT_CONDITION_NONE
))
1826 /* There are no available slots now. */
1834 /* Calculate the enable bits and the contents of the Data Value Compare
1835 debug register present in BookE processors.
1837 ADDR is the address to be watched, LEN is the length of watched data
1838 and DATA_VALUE is the value which will trigger the watchpoint.
1839 On exit, CONDITION_MODE will hold the enable bits for the DVC, and
1840 CONDITION_VALUE will hold the value which should be put in the
1843 calculate_dvc (CORE_ADDR addr
, int len
, CORE_ADDR data_value
,
1844 uint32_t *condition_mode
, uint64_t *condition_value
)
1846 int i
, num_byte_enable
, align_offset
, num_bytes_off_dvc
,
1847 rightmost_enabled_byte
;
1848 CORE_ADDR addr_end_data
, addr_end_dvc
;
1850 /* The DVC register compares bytes within fixed-length windows which
1851 are word-aligned, with length equal to that of the DVC register.
1852 We need to calculate where our watch region is relative to that
1853 window and enable comparison of the bytes which fall within it. */
1855 align_offset
= addr
% booke_debug_info
.sizeof_condition
;
1856 addr_end_data
= addr
+ len
;
1857 addr_end_dvc
= (addr
- align_offset
1858 + booke_debug_info
.sizeof_condition
);
1859 num_bytes_off_dvc
= (addr_end_data
> addr_end_dvc
)?
1860 addr_end_data
- addr_end_dvc
: 0;
1861 num_byte_enable
= len
- num_bytes_off_dvc
;
1862 /* Here, bytes are numbered from right to left. */
1863 rightmost_enabled_byte
= (addr_end_data
< addr_end_dvc
)?
1864 addr_end_dvc
- addr_end_data
: 0;
1866 *condition_mode
= PPC_BREAKPOINT_CONDITION_AND
;
1867 for (i
= 0; i
< num_byte_enable
; i
++)
1869 |= PPC_BREAKPOINT_CONDITION_BE (i
+ rightmost_enabled_byte
);
1871 /* Now we need to match the position within the DVC of the comparison
1872 value with where the watch region is relative to the window
1873 (i.e., the ALIGN_OFFSET). */
1875 *condition_value
= ((uint64_t) data_value
>> num_bytes_off_dvc
* 8
1876 << rightmost_enabled_byte
* 8);
1879 /* Return the number of memory locations that need to be accessed to
1880 evaluate the expression which generated the given value chain.
1881 Returns -1 if there's any register access involved, or if there are
1882 other kinds of values which are not acceptable in a condition
1883 expression (e.g., lval_computed or lval_internalvar). */
1885 num_memory_accesses (struct value
*v
)
1887 int found_memory_cnt
= 0;
1888 struct value
*head
= v
;
1890 /* The idea here is that evaluating an expression generates a series
1891 of values, one holding the value of every subexpression. (The
1892 expression a*b+c has five subexpressions: a, b, a*b, c, and
1893 a*b+c.) GDB's values hold almost enough information to establish
1894 the criteria given above --- they identify memory lvalues,
1895 register lvalues, computed values, etcetera. So we can evaluate
1896 the expression, and then scan the chain of values that leaves
1897 behind to determine the memory locations involved in the evaluation
1900 However, I don't think that the values returned by inferior
1901 function calls are special in any way. So this function may not
1902 notice that an expression contains an inferior function call.
1905 for (; v
; v
= value_next (v
))
1907 /* Constants and values from the history are fine. */
1908 if (VALUE_LVAL (v
) == not_lval
|| deprecated_value_modifiable (v
) == 0)
1910 else if (VALUE_LVAL (v
) == lval_memory
)
1912 /* A lazy memory lvalue is one that GDB never needed to fetch;
1913 we either just used its address (e.g., `a' in `a.b') or
1914 we never needed it at all (e.g., `a' in `a,b'). */
1915 if (!value_lazy (v
))
1918 /* Other kinds of values are not fine. */
1923 return found_memory_cnt
;
1926 /* Verifies whether the expression COND can be implemented using the
1927 DVC (Data Value Compare) register in BookE processors. The expression
1928 must test the watch value for equality with a constant expression.
1929 If the function returns 1, DATA_VALUE will contain the constant against
1930 which the watch value should be compared and LEN will contain the size
1933 check_condition (CORE_ADDR watch_addr
, struct expression
*cond
,
1934 CORE_ADDR
*data_value
, int *len
)
1936 int pc
= 1, num_accesses_left
, num_accesses_right
;
1937 struct value
*left_val
, *right_val
, *left_chain
, *right_chain
;
1939 if (cond
->elts
[0].opcode
!= BINOP_EQUAL
)
1942 fetch_subexp_value (cond
, &pc
, &left_val
, NULL
, &left_chain
);
1943 num_accesses_left
= num_memory_accesses (left_chain
);
1945 if (left_val
== NULL
|| num_accesses_left
< 0)
1947 free_value_chain (left_chain
);
1952 fetch_subexp_value (cond
, &pc
, &right_val
, NULL
, &right_chain
);
1953 num_accesses_right
= num_memory_accesses (right_chain
);
1955 if (right_val
== NULL
|| num_accesses_right
< 0)
1957 free_value_chain (left_chain
);
1958 free_value_chain (right_chain
);
1963 if (num_accesses_left
== 1 && num_accesses_right
== 0
1964 && VALUE_LVAL (left_val
) == lval_memory
1965 && value_address (left_val
) == watch_addr
)
1967 *data_value
= value_as_long (right_val
);
1969 /* DATA_VALUE is the constant in RIGHT_VAL, but actually has
1970 the same type as the memory region referenced by LEFT_VAL. */
1971 *len
= TYPE_LENGTH (check_typedef (value_type (left_val
)));
1973 else if (num_accesses_left
== 0 && num_accesses_right
== 1
1974 && VALUE_LVAL (right_val
) == lval_memory
1975 && value_address (right_val
) == watch_addr
)
1977 *data_value
= value_as_long (left_val
);
1979 /* DATA_VALUE is the constant in LEFT_VAL, but actually has
1980 the same type as the memory region referenced by RIGHT_VAL. */
1981 *len
= TYPE_LENGTH (check_typedef (value_type (right_val
)));
1985 free_value_chain (left_chain
);
1986 free_value_chain (right_chain
);
1991 free_value_chain (left_chain
);
1992 free_value_chain (right_chain
);
1997 /* Return non-zero if the target is capable of using hardware to evaluate
1998 the condition expression, thus only triggering the watchpoint when it is
2001 ppc_linux_can_accel_watchpoint_condition (CORE_ADDR addr
, int len
, int rw
,
2002 struct expression
*cond
)
2004 CORE_ADDR data_value
;
2006 return (have_ptrace_booke_interface ()
2007 && booke_debug_info
.num_condition_regs
> 0
2008 && check_condition (addr
, cond
, &data_value
, &len
));
2011 /* Set up P with the parameters necessary to request a watchpoint covering
2012 LEN bytes starting at ADDR and if possible with condition expression COND
2013 evaluated by hardware. INSERT tells if we are creating a request for
2014 inserting or removing the watchpoint. */
2017 create_watchpoint_request (struct ppc_hw_breakpoint
*p
, CORE_ADDR addr
,
2018 int len
, int rw
, struct expression
*cond
,
2022 || !(booke_debug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_RANGE
))
2025 CORE_ADDR data_value
;
2027 use_condition
= (insert
? can_use_watchpoint_cond_accel ()
2028 : booke_debug_info
.num_condition_regs
> 0);
2029 if (cond
&& use_condition
&& check_condition (addr
, cond
,
2031 calculate_dvc (addr
, len
, data_value
, &p
->condition_mode
,
2032 &p
->condition_value
);
2035 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2036 p
->condition_value
= 0;
2039 p
->addr_mode
= PPC_BREAKPOINT_MODE_EXACT
;
2044 p
->addr_mode
= PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE
;
2045 p
->condition_mode
= PPC_BREAKPOINT_CONDITION_NONE
;
2046 p
->condition_value
= 0;
2048 /* The watchpoint will trigger if the address of the memory access is
2049 within the defined range, as follows: p->addr <= address < p->addr2.
2051 Note that the above sentence just documents how ptrace interprets
2052 its arguments; the watchpoint is set to watch the range defined by
2053 the user _inclusively_, as specified by the user interface. */
2054 p
->addr2
= (uint64_t) addr
+ len
;
2057 p
->version
= PPC_DEBUG_CURRENT_VERSION
;
2058 p
->trigger_type
= get_trigger_type (rw
);
2059 p
->addr
= (uint64_t) addr
;
2063 ppc_linux_insert_watchpoint (CORE_ADDR addr
, int len
, int rw
,
2064 struct expression
*cond
)
2066 struct lwp_info
*lp
;
2069 if (have_ptrace_booke_interface ())
2071 struct ppc_hw_breakpoint p
;
2073 create_watchpoint_request (&p
, addr
, len
, rw
, cond
, 1);
2076 booke_insert_point (&p
, TIDGET (lp
->ptid
));
2083 long read_mode
, write_mode
;
2085 if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2087 /* PowerPC 440 requires only the read/write flags to be passed
2094 /* PowerPC 970 and other DABR-based processors are required to pass
2095 the Breakpoint Translation bit together with the flags. */
2100 dabr_value
= addr
& ~(read_mode
| write_mode
);
2104 /* Set read and translate bits. */
2105 dabr_value
|= read_mode
;
2108 /* Set write and translate bits. */
2109 dabr_value
|= write_mode
;
2112 /* Set read, write and translate bits. */
2113 dabr_value
|= read_mode
| write_mode
;
2117 saved_dabr_value
= dabr_value
;
2120 if (ptrace (PTRACE_SET_DEBUGREG
, TIDGET (lp
->ptid
), 0,
2121 saved_dabr_value
) < 0)
2131 ppc_linux_remove_watchpoint (CORE_ADDR addr
, int len
, int rw
,
2132 struct expression
*cond
)
2134 struct lwp_info
*lp
;
2137 if (have_ptrace_booke_interface ())
2139 struct ppc_hw_breakpoint p
;
2141 create_watchpoint_request (&p
, addr
, len
, rw
, cond
, 0);
2144 booke_remove_point (&p
, TIDGET (lp
->ptid
));
2150 saved_dabr_value
= 0;
2152 if (ptrace (PTRACE_SET_DEBUGREG
, TIDGET (lp
->ptid
), 0,
2153 saved_dabr_value
) < 0)
2163 ppc_linux_new_thread (struct lwp_info
*lp
)
2165 int tid
= TIDGET (lp
->ptid
);
2167 if (have_ptrace_booke_interface ())
2170 struct thread_points
*p
;
2171 struct hw_break_tuple
*hw_breaks
;
2173 if (VEC_empty (thread_points_p
, ppc_threads
))
2176 /* Get a list of breakpoints from any thread. */
2177 p
= VEC_last (thread_points_p
, ppc_threads
);
2178 hw_breaks
= p
->hw_breaks
;
2180 /* Copy that thread's breakpoints and watchpoints to the new thread. */
2181 for (i
= 0; i
< max_slots_number
; i
++)
2182 if (hw_breaks
[i
].hw_break
)
2184 /* Older kernels did not make new threads inherit their parent
2185 thread's debug state, so we always clear the slot and replicate
2186 the debug state ourselves, ensuring compatibility with all
2189 /* The ppc debug resource accounting is done through "slots".
2190 Ask the kernel the deallocate this specific *point's slot. */
2191 ptrace (PPC_PTRACE_DELHWDEBUG
, tid
, 0, hw_breaks
[i
].slot
);
2193 booke_insert_point (hw_breaks
[i
].hw_break
, tid
);
2197 ptrace (PTRACE_SET_DEBUGREG
, tid
, 0, saved_dabr_value
);
2201 ppc_linux_thread_exit (struct thread_info
*tp
, int silent
)
2204 int tid
= TIDGET (tp
->ptid
);
2205 struct hw_break_tuple
*hw_breaks
;
2206 struct thread_points
*t
= NULL
, *p
;
2208 if (!have_ptrace_booke_interface ())
2211 for (i
= 0; VEC_iterate (thread_points_p
, ppc_threads
, i
, p
); i
++)
2221 VEC_unordered_remove (thread_points_p
, ppc_threads
, i
);
2223 hw_breaks
= t
->hw_breaks
;
2225 for (i
= 0; i
< max_slots_number
; i
++)
2226 if (hw_breaks
[i
].hw_break
)
2227 xfree (hw_breaks
[i
].hw_break
);
2229 xfree (t
->hw_breaks
);
2234 ppc_linux_stopped_data_address (struct target_ops
*target
, CORE_ADDR
*addr_p
)
2238 if (!linux_nat_get_siginfo (inferior_ptid
, &siginfo
))
2241 if (siginfo
.si_signo
!= SIGTRAP
2242 || (siginfo
.si_code
& 0xffff) != 0x0004 /* TRAP_HWBKPT */)
2245 if (have_ptrace_booke_interface ())
2248 struct thread_points
*t
;
2249 struct hw_break_tuple
*hw_breaks
;
2250 /* The index (or slot) of the *point is passed in the si_errno field. */
2251 int slot
= siginfo
.si_errno
;
2253 t
= booke_find_thread_points_by_tid (TIDGET (inferior_ptid
), 0);
2255 /* Find out if this *point is a hardware breakpoint.
2256 If so, we should return 0. */
2259 hw_breaks
= t
->hw_breaks
;
2260 for (i
= 0; i
< max_slots_number
; i
++)
2261 if (hw_breaks
[i
].hw_break
&& hw_breaks
[i
].slot
== slot
2262 && hw_breaks
[i
].hw_break
->trigger_type
2263 == PPC_BREAKPOINT_TRIGGER_EXECUTE
)
2268 *addr_p
= (CORE_ADDR
) (uintptr_t) siginfo
.si_addr
;
2273 ppc_linux_stopped_by_watchpoint (void)
2276 return ppc_linux_stopped_data_address (¤t_target
, &addr
);
2280 ppc_linux_watchpoint_addr_within_range (struct target_ops
*target
,
2282 CORE_ADDR start
, int length
)
2286 if (have_ptrace_booke_interface ()
2287 && ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2288 return start
<= addr
&& start
+ length
>= addr
;
2289 else if (ppc_linux_get_hwcap () & PPC_FEATURE_BOOKE
)
2296 /* Check whether [start, start+length-1] intersects [addr, addr+mask]. */
2297 return start
<= addr
+ mask
&& start
+ length
- 1 >= addr
;
2300 /* Return the number of registers needed for a masked hardware watchpoint. */
2303 ppc_linux_masked_watch_num_registers (struct target_ops
*target
,
2304 CORE_ADDR addr
, CORE_ADDR mask
)
2306 if (!have_ptrace_booke_interface ()
2307 || (booke_debug_info
.features
& PPC_DEBUG_FEATURE_DATA_BP_MASK
) == 0)
2309 else if ((mask
& 0xC0000000) != 0xC0000000)
2311 warning (_("The given mask covers kernel address space "
2312 "and cannot be used.\n"));
2321 ppc_linux_store_inferior_registers (struct target_ops
*ops
,
2322 struct regcache
*regcache
, int regno
)
2324 /* Overload thread id onto process id. */
2325 int tid
= TIDGET (inferior_ptid
);
2327 /* No thread id, just use process id. */
2329 tid
= PIDGET (inferior_ptid
);
2332 store_register (regcache
, tid
, regno
);
2334 store_ppc_registers (regcache
, tid
);
2337 /* Functions for transferring registers between a gregset_t or fpregset_t
2338 (see sys/ucontext.h) and gdb's regcache. The word size is that used
2339 by the ptrace interface, not the current program's ABI. Eg. if a
2340 powerpc64-linux gdb is being used to debug a powerpc32-linux app, we
2341 read or write 64-bit gregsets. This is to suit the host libthread_db. */
2344 supply_gregset (struct regcache
*regcache
, const gdb_gregset_t
*gregsetp
)
2346 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2348 ppc_supply_gregset (regset
, regcache
, -1, gregsetp
, sizeof (*gregsetp
));
2352 fill_gregset (const struct regcache
*regcache
,
2353 gdb_gregset_t
*gregsetp
, int regno
)
2355 const struct regset
*regset
= ppc_linux_gregset (sizeof (long));
2358 memset (gregsetp
, 0, sizeof (*gregsetp
));
2359 ppc_collect_gregset (regset
, regcache
, regno
, gregsetp
, sizeof (*gregsetp
));
2363 supply_fpregset (struct regcache
*regcache
, const gdb_fpregset_t
* fpregsetp
)
2365 const struct regset
*regset
= ppc_linux_fpregset ();
2367 ppc_supply_fpregset (regset
, regcache
, -1,
2368 fpregsetp
, sizeof (*fpregsetp
));
2372 fill_fpregset (const struct regcache
*regcache
,
2373 gdb_fpregset_t
*fpregsetp
, int regno
)
2375 const struct regset
*regset
= ppc_linux_fpregset ();
2377 ppc_collect_fpregset (regset
, regcache
, regno
,
2378 fpregsetp
, sizeof (*fpregsetp
));
2382 ppc_linux_target_wordsize (void)
2386 /* Check for 64-bit inferior process. This is the case when the host is
2387 64-bit, and in addition the top bit of the MSR register is set. */
2388 #ifdef __powerpc64__
2391 int tid
= TIDGET (inferior_ptid
);
2393 tid
= PIDGET (inferior_ptid
);
2396 msr
= (long) ptrace (PTRACE_PEEKUSER
, tid
, PT_MSR
* 8, 0);
2397 if (errno
== 0 && msr
< 0)
2405 ppc_linux_auxv_parse (struct target_ops
*ops
, gdb_byte
**readptr
,
2406 gdb_byte
*endptr
, CORE_ADDR
*typep
, CORE_ADDR
*valp
)
2408 int sizeof_auxv_field
= ppc_linux_target_wordsize ();
2409 enum bfd_endian byte_order
= gdbarch_byte_order (target_gdbarch ());
2410 gdb_byte
*ptr
= *readptr
;
2415 if (endptr
- ptr
< sizeof_auxv_field
* 2)
2418 *typep
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2419 ptr
+= sizeof_auxv_field
;
2420 *valp
= extract_unsigned_integer (ptr
, sizeof_auxv_field
, byte_order
);
2421 ptr
+= sizeof_auxv_field
;
2427 static const struct target_desc
*
2428 ppc_linux_read_description (struct target_ops
*ops
)
2435 int tid
= TIDGET (inferior_ptid
);
2437 tid
= PIDGET (inferior_ptid
);
2439 if (have_ptrace_getsetevrregs
)
2441 struct gdb_evrregset_t evrregset
;
2443 if (ptrace (PTRACE_GETEVRREGS
, tid
, 0, &evrregset
) >= 0)
2444 return tdesc_powerpc_e500l
;
2446 /* EIO means that the PTRACE_GETEVRREGS request isn't supported.
2447 Anything else needs to be reported. */
2448 else if (errno
!= EIO
)
2449 perror_with_name (_("Unable to fetch SPE registers"));
2452 if (have_ptrace_getsetvsxregs
)
2454 gdb_vsxregset_t vsxregset
;
2456 if (ptrace (PTRACE_GETVSXREGS
, tid
, 0, &vsxregset
) >= 0)
2459 /* EIO means that the PTRACE_GETVSXREGS request isn't supported.
2460 Anything else needs to be reported. */
2461 else if (errno
!= EIO
)
2462 perror_with_name (_("Unable to fetch VSX registers"));
2465 if (have_ptrace_getvrregs
)
2467 gdb_vrregset_t vrregset
;
2469 if (ptrace (PTRACE_GETVRREGS
, tid
, 0, &vrregset
) >= 0)
2472 /* EIO means that the PTRACE_GETVRREGS request isn't supported.
2473 Anything else needs to be reported. */
2474 else if (errno
!= EIO
)
2475 perror_with_name (_("Unable to fetch AltiVec registers"));
2478 /* Power ISA 2.05 (implemented by Power 6 and newer processors) increases
2479 the FPSCR from 32 bits to 64 bits. Even though Power 7 supports this
2480 ISA version, it doesn't have PPC_FEATURE_ARCH_2_05 set, only
2481 PPC_FEATURE_ARCH_2_06. Since for now the only bits used in the higher
2482 half of the register are for Decimal Floating Point, we check if that
2483 feature is available to decide the size of the FPSCR. */
2484 if (ppc_linux_get_hwcap () & PPC_FEATURE_HAS_DFP
)
2487 if (ppc_linux_get_hwcap () & PPC_FEATURE_CELL
)
2490 if (ppc_linux_target_wordsize () == 8)
2493 return tdesc_powerpc_cell64l
;
2495 return isa205
? tdesc_powerpc_isa205_vsx64l
: tdesc_powerpc_vsx64l
;
2498 ? tdesc_powerpc_isa205_altivec64l
: tdesc_powerpc_altivec64l
;
2500 return isa205
? tdesc_powerpc_isa205_64l
: tdesc_powerpc_64l
;
2504 return tdesc_powerpc_cell32l
;
2506 return isa205
? tdesc_powerpc_isa205_vsx32l
: tdesc_powerpc_vsx32l
;
2508 return isa205
? tdesc_powerpc_isa205_altivec32l
: tdesc_powerpc_altivec32l
;
2510 return isa205
? tdesc_powerpc_isa205_32l
: tdesc_powerpc_32l
;
2513 void _initialize_ppc_linux_nat (void);
2516 _initialize_ppc_linux_nat (void)
2518 struct target_ops
*t
;
2520 /* Fill in the generic GNU/Linux methods. */
2521 t
= linux_target ();
2523 /* Add our register access methods. */
2524 t
->to_fetch_registers
= ppc_linux_fetch_inferior_registers
;
2525 t
->to_store_registers
= ppc_linux_store_inferior_registers
;
2527 /* Add our breakpoint/watchpoint methods. */
2528 t
->to_can_use_hw_breakpoint
= ppc_linux_can_use_hw_breakpoint
;
2529 t
->to_insert_hw_breakpoint
= ppc_linux_insert_hw_breakpoint
;
2530 t
->to_remove_hw_breakpoint
= ppc_linux_remove_hw_breakpoint
;
2531 t
->to_region_ok_for_hw_watchpoint
= ppc_linux_region_ok_for_hw_watchpoint
;
2532 t
->to_insert_watchpoint
= ppc_linux_insert_watchpoint
;
2533 t
->to_remove_watchpoint
= ppc_linux_remove_watchpoint
;
2534 t
->to_insert_mask_watchpoint
= ppc_linux_insert_mask_watchpoint
;
2535 t
->to_remove_mask_watchpoint
= ppc_linux_remove_mask_watchpoint
;
2536 t
->to_stopped_by_watchpoint
= ppc_linux_stopped_by_watchpoint
;
2537 t
->to_stopped_data_address
= ppc_linux_stopped_data_address
;
2538 t
->to_watchpoint_addr_within_range
= ppc_linux_watchpoint_addr_within_range
;
2539 t
->to_can_accel_watchpoint_condition
2540 = ppc_linux_can_accel_watchpoint_condition
;
2541 t
->to_masked_watch_num_registers
= ppc_linux_masked_watch_num_registers
;
2542 t
->to_ranged_break_num_registers
= ppc_linux_ranged_break_num_registers
;
2544 t
->to_read_description
= ppc_linux_read_description
;
2545 t
->to_auxv_parse
= ppc_linux_auxv_parse
;
2547 observer_attach_thread_exit (ppc_linux_thread_exit
);
2549 /* Register the target. */
2550 linux_nat_add_target (t
);
2551 linux_nat_set_new_thread (t
, ppc_linux_new_thread
);