include:
[deliverable/binutils-gdb.git] / gdb / ppc-sysv-tdep.c
1 /* Target-dependent code for PowerPC systems using the SVR4 ABI
2 for GDB, the GNU debugger.
3
4 Copyright (C) 2000, 2001, 2002, 2003, 2005, 2007
5 Free Software Foundation, Inc.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22 #include "defs.h"
23 #include "gdbcore.h"
24 #include "inferior.h"
25 #include "regcache.h"
26 #include "value.h"
27 #include "gdb_string.h"
28 #include "gdb_assert.h"
29 #include "ppc-tdep.h"
30 #include "target.h"
31 #include "objfiles.h"
32 #include "infcall.h"
33
34 /* Pass the arguments in either registers, or in the stack. Using the
35 ppc sysv ABI, the first eight words of the argument list (that might
36 be less than eight parameters if some parameters occupy more than one
37 word) are passed in r3..r10 registers. float and double parameters are
38 passed in fpr's, in addition to that. Rest of the parameters if any
39 are passed in user stack.
40
41 If the function is returning a structure, then the return address is passed
42 in r3, then the first 7 words of the parametes can be passed in registers,
43 starting from r4. */
44
45 CORE_ADDR
46 ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
47 struct regcache *regcache, CORE_ADDR bp_addr,
48 int nargs, struct value **args, CORE_ADDR sp,
49 int struct_return, CORE_ADDR struct_addr)
50 {
51 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
52 ULONGEST saved_sp;
53 int argspace = 0; /* 0 is an initial wrong guess. */
54 int write_pass;
55
56 gdb_assert (tdep->wordsize == 4);
57
58 regcache_cooked_read_unsigned (regcache,
59 gdbarch_sp_regnum (current_gdbarch),
60 &saved_sp);
61
62 /* Go through the argument list twice.
63
64 Pass 1: Figure out how much new stack space is required for
65 arguments and pushed values. Unlike the PowerOpen ABI, the SysV
66 ABI doesn't reserve any extra space for parameters which are put
67 in registers, but does always push structures and then pass their
68 address.
69
70 Pass 2: Replay the same computation but this time also write the
71 values out to the target. */
72
73 for (write_pass = 0; write_pass < 2; write_pass++)
74 {
75 int argno;
76 /* Next available floating point register for float and double
77 arguments. */
78 int freg = 1;
79 /* Next available general register for non-float, non-vector
80 arguments. */
81 int greg = 3;
82 /* Next available vector register for vector arguments. */
83 int vreg = 2;
84 /* Arguments start above the "LR save word" and "Back chain". */
85 int argoffset = 2 * tdep->wordsize;
86 /* Structures start after the arguments. */
87 int structoffset = argoffset + argspace;
88
89 /* If the function is returning a `struct', then the first word
90 (which will be passed in r3) is used for struct return
91 address. In that case we should advance one word and start
92 from r4 register to copy parameters. */
93 if (struct_return)
94 {
95 if (write_pass)
96 regcache_cooked_write_signed (regcache,
97 tdep->ppc_gp0_regnum + greg,
98 struct_addr);
99 greg++;
100 }
101
102 for (argno = 0; argno < nargs; argno++)
103 {
104 struct value *arg = args[argno];
105 struct type *type = check_typedef (value_type (arg));
106 int len = TYPE_LENGTH (type);
107 const bfd_byte *val = value_contents (arg);
108
109 if (TYPE_CODE (type) == TYPE_CODE_FLT && len <= 8
110 && !tdep->soft_float)
111 {
112 /* Floating point value converted to "double" then
113 passed in an FP register, when the registers run out,
114 8 byte aligned stack is used. */
115 if (freg <= 8)
116 {
117 if (write_pass)
118 {
119 /* Always store the floating point value using
120 the register's floating-point format. */
121 gdb_byte regval[MAX_REGISTER_SIZE];
122 struct type *regtype
123 = register_type (gdbarch, tdep->ppc_fp0_regnum + freg);
124 convert_typed_floating (val, type, regval, regtype);
125 regcache_cooked_write (regcache,
126 tdep->ppc_fp0_regnum + freg,
127 regval);
128 }
129 freg++;
130 }
131 else
132 {
133 /* SysV ABI converts floats to doubles before
134 writing them to an 8 byte aligned stack location. */
135 argoffset = align_up (argoffset, 8);
136 if (write_pass)
137 {
138 char memval[8];
139 convert_typed_floating (val, type, memval,
140 builtin_type_ieee_double);
141 write_memory (sp + argoffset, val, len);
142 }
143 argoffset += 8;
144 }
145 }
146 else if (TYPE_CODE (type) == TYPE_CODE_FLT
147 && len == 16
148 && !tdep->soft_float
149 && (gdbarch_long_double_format (current_gdbarch)
150 == floatformats_ibm_long_double))
151 {
152 /* IBM long double passed in two FP registers if
153 available, otherwise 8-byte aligned stack. */
154 if (freg <= 7)
155 {
156 if (write_pass)
157 {
158 regcache_cooked_write (regcache,
159 tdep->ppc_fp0_regnum + freg,
160 val);
161 regcache_cooked_write (regcache,
162 tdep->ppc_fp0_regnum + freg + 1,
163 val + 8);
164 }
165 freg += 2;
166 }
167 else
168 {
169 argoffset = align_up (argoffset, 8);
170 if (write_pass)
171 write_memory (sp + argoffset, val, len);
172 argoffset += 16;
173 }
174 }
175 else if (len == 8
176 && (TYPE_CODE (type) == TYPE_CODE_INT /* long long */
177 || TYPE_CODE (type) == TYPE_CODE_FLT)) /* double */
178 {
179 /* "long long" or soft-float "double" passed in an odd/even
180 register pair with the low addressed word in the odd
181 register and the high addressed word in the even
182 register, or when the registers run out an 8 byte
183 aligned stack location. */
184 if (greg > 9)
185 {
186 /* Just in case GREG was 10. */
187 greg = 11;
188 argoffset = align_up (argoffset, 8);
189 if (write_pass)
190 write_memory (sp + argoffset, val, len);
191 argoffset += 8;
192 }
193 else
194 {
195 /* Must start on an odd register - r3/r4 etc. */
196 if ((greg & 1) == 0)
197 greg++;
198 if (write_pass)
199 {
200 regcache_cooked_write (regcache,
201 tdep->ppc_gp0_regnum + greg + 0,
202 val + 0);
203 regcache_cooked_write (regcache,
204 tdep->ppc_gp0_regnum + greg + 1,
205 val + 4);
206 }
207 greg += 2;
208 }
209 }
210 else if (len == 16 && TYPE_CODE (type) == TYPE_CODE_FLT
211 && (gdbarch_long_double_format (current_gdbarch)
212 == floatformats_ibm_long_double))
213 {
214 /* Soft-float IBM long double passed in four consecutive
215 registers, or on the stack. The registers are not
216 necessarily odd/even pairs. */
217 if (greg > 7)
218 {
219 greg = 11;
220 argoffset = align_up (argoffset, 8);
221 if (write_pass)
222 write_memory (sp + argoffset, val, len);
223 argoffset += 16;
224 }
225 else
226 {
227 if (write_pass)
228 {
229 regcache_cooked_write (regcache,
230 tdep->ppc_gp0_regnum + greg + 0,
231 val + 0);
232 regcache_cooked_write (regcache,
233 tdep->ppc_gp0_regnum + greg + 1,
234 val + 4);
235 regcache_cooked_write (regcache,
236 tdep->ppc_gp0_regnum + greg + 2,
237 val + 8);
238 regcache_cooked_write (regcache,
239 tdep->ppc_gp0_regnum + greg + 3,
240 val + 12);
241 }
242 greg += 4;
243 }
244 }
245 else if (len == 16
246 && TYPE_CODE (type) == TYPE_CODE_ARRAY
247 && TYPE_VECTOR (type)
248 && tdep->vector_abi == POWERPC_VEC_ALTIVEC)
249 {
250 /* Vector parameter passed in an Altivec register, or
251 when that runs out, 16 byte aligned stack location. */
252 if (vreg <= 13)
253 {
254 if (write_pass)
255 regcache_cooked_write (regcache,
256 tdep->ppc_vr0_regnum + vreg, val);
257 vreg++;
258 }
259 else
260 {
261 argoffset = align_up (argoffset, 16);
262 if (write_pass)
263 write_memory (sp + argoffset, val, 16);
264 argoffset += 16;
265 }
266 }
267 else if (len == 8
268 && TYPE_CODE (type) == TYPE_CODE_ARRAY
269 && TYPE_VECTOR (type)
270 && tdep->vector_abi == POWERPC_VEC_SPE)
271 {
272 /* Vector parameter passed in an e500 register, or when
273 that runs out, 8 byte aligned stack location. Note
274 that since e500 vector and general purpose registers
275 both map onto the same underlying register set, a
276 "greg" and not a "vreg" is consumed here. A cooked
277 write stores the value in the correct locations
278 within the raw register cache. */
279 if (greg <= 10)
280 {
281 if (write_pass)
282 regcache_cooked_write (regcache,
283 tdep->ppc_ev0_regnum + greg, val);
284 greg++;
285 }
286 else
287 {
288 argoffset = align_up (argoffset, 8);
289 if (write_pass)
290 write_memory (sp + argoffset, val, 8);
291 argoffset += 8;
292 }
293 }
294 else
295 {
296 /* Reduce the parameter down to something that fits in a
297 "word". */
298 gdb_byte word[MAX_REGISTER_SIZE];
299 memset (word, 0, MAX_REGISTER_SIZE);
300 if (len > tdep->wordsize
301 || TYPE_CODE (type) == TYPE_CODE_STRUCT
302 || TYPE_CODE (type) == TYPE_CODE_UNION)
303 {
304 /* Structs and large values are put in an
305 aligned stack slot ... */
306 if (TYPE_CODE (type) == TYPE_CODE_ARRAY
307 && TYPE_VECTOR (type)
308 && len >= 16)
309 structoffset = align_up (structoffset, 16);
310 else
311 structoffset = align_up (structoffset, 8);
312
313 if (write_pass)
314 write_memory (sp + structoffset, val, len);
315 /* ... and then a "word" pointing to that address is
316 passed as the parameter. */
317 store_unsigned_integer (word, tdep->wordsize,
318 sp + structoffset);
319 structoffset += len;
320 }
321 else if (TYPE_CODE (type) == TYPE_CODE_INT)
322 /* Sign or zero extend the "int" into a "word". */
323 store_unsigned_integer (word, tdep->wordsize,
324 unpack_long (type, val));
325 else
326 /* Always goes in the low address. */
327 memcpy (word, val, len);
328 /* Store that "word" in a register, or on the stack.
329 The words have "4" byte alignment. */
330 if (greg <= 10)
331 {
332 if (write_pass)
333 regcache_cooked_write (regcache,
334 tdep->ppc_gp0_regnum + greg, word);
335 greg++;
336 }
337 else
338 {
339 argoffset = align_up (argoffset, tdep->wordsize);
340 if (write_pass)
341 write_memory (sp + argoffset, word, tdep->wordsize);
342 argoffset += tdep->wordsize;
343 }
344 }
345 }
346
347 /* Compute the actual stack space requirements. */
348 if (!write_pass)
349 {
350 /* Remember the amount of space needed by the arguments. */
351 argspace = argoffset;
352 /* Allocate space for both the arguments and the structures. */
353 sp -= (argoffset + structoffset);
354 /* Ensure that the stack is still 16 byte aligned. */
355 sp = align_down (sp, 16);
356 }
357
358 /* The psABI says that "A caller of a function that takes a
359 variable argument list shall set condition register bit 6 to
360 1 if it passes one or more arguments in the floating-point
361 registers. It is strongly recommended that the caller set the
362 bit to 0 otherwise..." Doing this for normal functions too
363 shouldn't hurt. */
364 if (write_pass)
365 {
366 ULONGEST cr;
367
368 regcache_cooked_read_unsigned (regcache, tdep->ppc_cr_regnum, &cr);
369 if (freg > 1)
370 cr |= 0x02000000;
371 else
372 cr &= ~0x02000000;
373 regcache_cooked_write_unsigned (regcache, tdep->ppc_cr_regnum, cr);
374 }
375 }
376
377 /* Update %sp. */
378 regcache_cooked_write_signed (regcache,
379 gdbarch_sp_regnum (current_gdbarch), sp);
380
381 /* Write the backchain (it occupies WORDSIZED bytes). */
382 write_memory_signed_integer (sp, tdep->wordsize, saved_sp);
383
384 /* Point the inferior function call's return address at the dummy's
385 breakpoint. */
386 regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
387
388 return sp;
389 }
390
391 /* Handle the return-value conventions specified by the SysV 32-bit
392 PowerPC ABI (including all the supplements):
393
394 no floating-point: floating-point values returned using 32-bit
395 general-purpose registers.
396
397 Altivec: 128-bit vectors returned using vector registers.
398
399 e500: 64-bit vectors returned using the full full 64 bit EV
400 register, floating-point values returned using 32-bit
401 general-purpose registers.
402
403 GCC (broken): Small struct values right (instead of left) aligned
404 when returned in general-purpose registers. */
405
406 static enum return_value_convention
407 do_ppc_sysv_return_value (struct gdbarch *gdbarch, struct type *type,
408 struct regcache *regcache, gdb_byte *readbuf,
409 const gdb_byte *writebuf, int broken_gcc)
410 {
411 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
412 gdb_assert (tdep->wordsize == 4);
413 if (TYPE_CODE (type) == TYPE_CODE_FLT
414 && TYPE_LENGTH (type) <= 8
415 && !tdep->soft_float)
416 {
417 if (readbuf)
418 {
419 /* Floats and doubles stored in "f1". Convert the value to
420 the required type. */
421 gdb_byte regval[MAX_REGISTER_SIZE];
422 struct type *regtype = register_type (gdbarch,
423 tdep->ppc_fp0_regnum + 1);
424 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
425 convert_typed_floating (regval, regtype, readbuf, type);
426 }
427 if (writebuf)
428 {
429 /* Floats and doubles stored in "f1". Convert the value to
430 the register's "double" type. */
431 gdb_byte regval[MAX_REGISTER_SIZE];
432 struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
433 convert_typed_floating (writebuf, type, regval, regtype);
434 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
435 }
436 return RETURN_VALUE_REGISTER_CONVENTION;
437 }
438 if (TYPE_CODE (type) == TYPE_CODE_FLT
439 && TYPE_LENGTH (type) == 16
440 && !tdep->soft_float
441 && (gdbarch_long_double_format (current_gdbarch)
442 == floatformats_ibm_long_double))
443 {
444 /* IBM long double stored in f1 and f2. */
445 if (readbuf)
446 {
447 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, readbuf);
448 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 2,
449 readbuf + 8);
450 }
451 if (writebuf)
452 {
453 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, writebuf);
454 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 2,
455 writebuf + 8);
456 }
457 return RETURN_VALUE_REGISTER_CONVENTION;
458 }
459 if (TYPE_CODE (type) == TYPE_CODE_FLT
460 && TYPE_LENGTH (type) == 16
461 && (gdbarch_long_double_format (current_gdbarch)
462 == floatformats_ibm_long_double))
463 {
464 /* Soft-float IBM long double stored in r3, r4, r5, r6. */
465 if (readbuf)
466 {
467 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, readbuf);
468 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
469 readbuf + 4);
470 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 5,
471 readbuf + 8);
472 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 6,
473 readbuf + 12);
474 }
475 if (writebuf)
476 {
477 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
478 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
479 writebuf + 4);
480 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 5,
481 writebuf + 8);
482 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 6,
483 writebuf + 12);
484 }
485 return RETURN_VALUE_REGISTER_CONVENTION;
486 }
487 if ((TYPE_CODE (type) == TYPE_CODE_INT && TYPE_LENGTH (type) == 8)
488 || (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8))
489 {
490 if (readbuf)
491 {
492 /* A long long, or a double stored in the 32 bit r3/r4. */
493 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3,
494 readbuf + 0);
495 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
496 readbuf + 4);
497 }
498 if (writebuf)
499 {
500 /* A long long, or a double stored in the 32 bit r3/r4. */
501 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3,
502 writebuf + 0);
503 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
504 writebuf + 4);
505 }
506 return RETURN_VALUE_REGISTER_CONVENTION;
507 }
508 else if ((TYPE_CODE (type) == TYPE_CODE_INT
509 || TYPE_CODE (type) == TYPE_CODE_CHAR
510 || TYPE_CODE (type) == TYPE_CODE_BOOL
511 || TYPE_CODE (type) == TYPE_CODE_PTR
512 || TYPE_CODE (type) == TYPE_CODE_REF
513 || TYPE_CODE (type) == TYPE_CODE_ENUM)
514 && TYPE_LENGTH (type) <= tdep->wordsize)
515 {
516 if (readbuf)
517 {
518 /* Some sort of integer stored in r3. Since TYPE isn't
519 bigger than the register, sign extension isn't a problem
520 - just do everything unsigned. */
521 ULONGEST regval;
522 regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
523 &regval);
524 store_unsigned_integer (readbuf, TYPE_LENGTH (type), regval);
525 }
526 if (writebuf)
527 {
528 /* Some sort of integer stored in r3. Use unpack_long since
529 that should handle any required sign extension. */
530 regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
531 unpack_long (type, writebuf));
532 }
533 return RETURN_VALUE_REGISTER_CONVENTION;
534 }
535 if (TYPE_LENGTH (type) == 16
536 && TYPE_CODE (type) == TYPE_CODE_ARRAY
537 && TYPE_VECTOR (type)
538 && tdep->vector_abi == POWERPC_VEC_ALTIVEC)
539 {
540 if (readbuf)
541 {
542 /* Altivec places the return value in "v2". */
543 regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
544 }
545 if (writebuf)
546 {
547 /* Altivec places the return value in "v2". */
548 regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
549 }
550 return RETURN_VALUE_REGISTER_CONVENTION;
551 }
552 if (TYPE_LENGTH (type) == 16
553 && TYPE_CODE (type) == TYPE_CODE_ARRAY
554 && TYPE_VECTOR (type)
555 && tdep->vector_abi == POWERPC_VEC_GENERIC)
556 {
557 /* GCC -maltivec -mabi=no-altivec returns vectors in r3/r4/r5/r6.
558 GCC without AltiVec returns them in memory, but it warns about
559 ABI risks in that case; we don't try to support it. */
560 if (readbuf)
561 {
562 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3,
563 readbuf + 0);
564 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
565 readbuf + 4);
566 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 5,
567 readbuf + 8);
568 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 6,
569 readbuf + 12);
570 }
571 if (writebuf)
572 {
573 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3,
574 writebuf + 0);
575 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
576 writebuf + 4);
577 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 5,
578 writebuf + 8);
579 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 6,
580 writebuf + 12);
581 }
582 return RETURN_VALUE_REGISTER_CONVENTION;
583 }
584 if (TYPE_LENGTH (type) == 8
585 && TYPE_CODE (type) == TYPE_CODE_ARRAY
586 && TYPE_VECTOR (type)
587 && tdep->vector_abi == POWERPC_VEC_SPE)
588 {
589 /* The e500 ABI places return values for the 64-bit DSP types
590 (__ev64_opaque__) in r3. However, in GDB-speak, ev3
591 corresponds to the entire r3 value for e500, whereas GDB's r3
592 only corresponds to the least significant 32-bits. So place
593 the 64-bit DSP type's value in ev3. */
594 if (readbuf)
595 regcache_cooked_read (regcache, tdep->ppc_ev0_regnum + 3, readbuf);
596 if (writebuf)
597 regcache_cooked_write (regcache, tdep->ppc_ev0_regnum + 3, writebuf);
598 return RETURN_VALUE_REGISTER_CONVENTION;
599 }
600 if (broken_gcc && TYPE_LENGTH (type) <= 8)
601 {
602 /* GCC screwed up for structures or unions whose size is less
603 than or equal to 8 bytes.. Instead of left-aligning, it
604 right-aligns the data into the buffer formed by r3, r4. */
605 gdb_byte regvals[MAX_REGISTER_SIZE * 2];
606 int len = TYPE_LENGTH (type);
607 int offset = (2 * tdep->wordsize - len) % tdep->wordsize;
608
609 if (readbuf)
610 {
611 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3,
612 regvals + 0 * tdep->wordsize);
613 if (len > tdep->wordsize)
614 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
615 regvals + 1 * tdep->wordsize);
616 memcpy (readbuf, regvals + offset, len);
617 }
618 if (writebuf)
619 {
620 memset (regvals, 0, sizeof regvals);
621 memcpy (regvals + offset, writebuf, len);
622 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3,
623 regvals + 0 * tdep->wordsize);
624 if (len > tdep->wordsize)
625 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
626 regvals + 1 * tdep->wordsize);
627 }
628
629 return RETURN_VALUE_REGISTER_CONVENTION;
630 }
631 if (TYPE_LENGTH (type) <= 8)
632 {
633 if (readbuf)
634 {
635 /* This matches SVr4 PPC, it does not match GCC. */
636 /* The value is right-padded to 8 bytes and then loaded, as
637 two "words", into r3/r4. */
638 gdb_byte regvals[MAX_REGISTER_SIZE * 2];
639 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3,
640 regvals + 0 * tdep->wordsize);
641 if (TYPE_LENGTH (type) > tdep->wordsize)
642 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
643 regvals + 1 * tdep->wordsize);
644 memcpy (readbuf, regvals, TYPE_LENGTH (type));
645 }
646 if (writebuf)
647 {
648 /* This matches SVr4 PPC, it does not match GCC. */
649 /* The value is padded out to 8 bytes and then loaded, as
650 two "words" into r3/r4. */
651 gdb_byte regvals[MAX_REGISTER_SIZE * 2];
652 memset (regvals, 0, sizeof regvals);
653 memcpy (regvals, writebuf, TYPE_LENGTH (type));
654 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3,
655 regvals + 0 * tdep->wordsize);
656 if (TYPE_LENGTH (type) > tdep->wordsize)
657 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
658 regvals + 1 * tdep->wordsize);
659 }
660 return RETURN_VALUE_REGISTER_CONVENTION;
661 }
662 return RETURN_VALUE_STRUCT_CONVENTION;
663 }
664
665 enum return_value_convention
666 ppc_sysv_abi_return_value (struct gdbarch *gdbarch, struct type *valtype,
667 struct regcache *regcache, gdb_byte *readbuf,
668 const gdb_byte *writebuf)
669 {
670 return do_ppc_sysv_return_value (gdbarch, valtype, regcache, readbuf,
671 writebuf, 0);
672 }
673
674 enum return_value_convention
675 ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
676 struct type *valtype,
677 struct regcache *regcache,
678 gdb_byte *readbuf, const gdb_byte *writebuf)
679 {
680 return do_ppc_sysv_return_value (gdbarch, valtype, regcache, readbuf,
681 writebuf, 1);
682 }
683
684 /* The helper function for 64-bit SYSV push_dummy_call. Converts the
685 function's code address back into the function's descriptor
686 address.
687
688 Find a value for the TOC register. Every symbol should have both
689 ".FN" and "FN" in the minimal symbol table. "FN" points at the
690 FN's descriptor, while ".FN" points at the entry point (which
691 matches FUNC_ADDR). Need to reverse from FUNC_ADDR back to the
692 FN's descriptor address (while at the same time being careful to
693 find "FN" in the same object file as ".FN"). */
694
695 static int
696 convert_code_addr_to_desc_addr (CORE_ADDR code_addr, CORE_ADDR *desc_addr)
697 {
698 struct obj_section *dot_fn_section;
699 struct minimal_symbol *dot_fn;
700 struct minimal_symbol *fn;
701 CORE_ADDR toc;
702 /* Find the minimal symbol that corresponds to CODE_ADDR (should
703 have a name of the form ".FN"). */
704 dot_fn = lookup_minimal_symbol_by_pc (code_addr);
705 if (dot_fn == NULL || SYMBOL_LINKAGE_NAME (dot_fn)[0] != '.')
706 return 0;
707 /* Get the section that contains CODE_ADDR. Need this for the
708 "objfile" that it contains. */
709 dot_fn_section = find_pc_section (code_addr);
710 if (dot_fn_section == NULL || dot_fn_section->objfile == NULL)
711 return 0;
712 /* Now find the corresponding "FN" (dropping ".") minimal symbol's
713 address. Only look for the minimal symbol in ".FN"'s object file
714 - avoids problems when two object files (i.e., shared libraries)
715 contain a minimal symbol with the same name. */
716 fn = lookup_minimal_symbol (SYMBOL_LINKAGE_NAME (dot_fn) + 1, NULL,
717 dot_fn_section->objfile);
718 if (fn == NULL)
719 return 0;
720 /* Found a descriptor. */
721 (*desc_addr) = SYMBOL_VALUE_ADDRESS (fn);
722 return 1;
723 }
724
725 /* Pass the arguments in either registers, or in the stack. Using the
726 ppc 64 bit SysV ABI.
727
728 This implements a dumbed down version of the ABI. It always writes
729 values to memory, GPR and FPR, even when not necessary. Doing this
730 greatly simplifies the logic. */
731
732 CORE_ADDR
733 ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
734 struct regcache *regcache, CORE_ADDR bp_addr,
735 int nargs, struct value **args, CORE_ADDR sp,
736 int struct_return, CORE_ADDR struct_addr)
737 {
738 CORE_ADDR func_addr = find_function_addr (function, NULL);
739 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
740 ULONGEST back_chain;
741 /* See for-loop comment below. */
742 int write_pass;
743 /* Size of the Altivec's vector parameter region, the final value is
744 computed in the for-loop below. */
745 LONGEST vparam_size = 0;
746 /* Size of the general parameter region, the final value is computed
747 in the for-loop below. */
748 LONGEST gparam_size = 0;
749 /* Kevin writes ... I don't mind seeing tdep->wordsize used in the
750 calls to align_up(), align_down(), etc. because this makes it
751 easier to reuse this code (in a copy/paste sense) in the future,
752 but it is a 64-bit ABI and asserting that the wordsize is 8 bytes
753 at some point makes it easier to verify that this function is
754 correct without having to do a non-local analysis to figure out
755 the possible values of tdep->wordsize. */
756 gdb_assert (tdep->wordsize == 8);
757
758 /* This function exists to support a calling convention that
759 requires floating-point registers. It shouldn't be used on
760 processors that lack them. */
761 gdb_assert (ppc_floating_point_unit_p (gdbarch));
762
763 /* By this stage in the proceedings, SP has been decremented by "red
764 zone size" + "struct return size". Fetch the stack-pointer from
765 before this and use that as the BACK_CHAIN. */
766 regcache_cooked_read_unsigned (regcache,
767 gdbarch_sp_regnum (current_gdbarch),
768 &back_chain);
769
770 /* Go through the argument list twice.
771
772 Pass 1: Compute the function call's stack space and register
773 requirements.
774
775 Pass 2: Replay the same computation but this time also write the
776 values out to the target. */
777
778 for (write_pass = 0; write_pass < 2; write_pass++)
779 {
780 int argno;
781 /* Next available floating point register for float and double
782 arguments. */
783 int freg = 1;
784 /* Next available general register for non-vector (but possibly
785 float) arguments. */
786 int greg = 3;
787 /* Next available vector register for vector arguments. */
788 int vreg = 2;
789 /* The address, at which the next general purpose parameter
790 (integer, struct, float, ...) should be saved. */
791 CORE_ADDR gparam;
792 /* Address, at which the next Altivec vector parameter should be
793 saved. */
794 CORE_ADDR vparam;
795
796 if (!write_pass)
797 {
798 /* During the first pass, GPARAM and VPARAM are more like
799 offsets (start address zero) than addresses. That way
800 the accumulate the total stack space each region
801 requires. */
802 gparam = 0;
803 vparam = 0;
804 }
805 else
806 {
807 /* Decrement the stack pointer making space for the Altivec
808 and general on-stack parameters. Set vparam and gparam
809 to their corresponding regions. */
810 vparam = align_down (sp - vparam_size, 16);
811 gparam = align_down (vparam - gparam_size, 16);
812 /* Add in space for the TOC, link editor double word,
813 compiler double word, LR save area, CR save area. */
814 sp = align_down (gparam - 48, 16);
815 }
816
817 /* If the function is returning a `struct', then there is an
818 extra hidden parameter (which will be passed in r3)
819 containing the address of that struct.. In that case we
820 should advance one word and start from r4 register to copy
821 parameters. This also consumes one on-stack parameter slot. */
822 if (struct_return)
823 {
824 if (write_pass)
825 regcache_cooked_write_signed (regcache,
826 tdep->ppc_gp0_regnum + greg,
827 struct_addr);
828 greg++;
829 gparam = align_up (gparam + tdep->wordsize, tdep->wordsize);
830 }
831
832 for (argno = 0; argno < nargs; argno++)
833 {
834 struct value *arg = args[argno];
835 struct type *type = check_typedef (value_type (arg));
836 const bfd_byte *val = value_contents (arg);
837 if (TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) <= 8)
838 {
839 /* Floats and Doubles go in f1 .. f13. They also
840 consume a left aligned GREG,, and can end up in
841 memory. */
842 if (write_pass)
843 {
844 if (freg <= 13)
845 {
846 gdb_byte regval[MAX_REGISTER_SIZE];
847 struct type *regtype
848 = register_type (gdbarch, tdep->ppc_fp0_regnum);
849 convert_typed_floating (val, type, regval, regtype);
850 regcache_cooked_write (regcache,
851 tdep->ppc_fp0_regnum + freg,
852 regval);
853 }
854 if (greg <= 10)
855 {
856 /* The ABI states "Single precision floating
857 point values are mapped to the first word in
858 a single doubleword" and "... floating point
859 values mapped to the first eight doublewords
860 of the parameter save area are also passed in
861 general registers").
862
863 This code interprets that to mean: store it,
864 left aligned, in the general register. */
865 gdb_byte regval[MAX_REGISTER_SIZE];
866 memset (regval, 0, sizeof regval);
867 memcpy (regval, val, TYPE_LENGTH (type));
868 regcache_cooked_write (regcache,
869 tdep->ppc_gp0_regnum + greg,
870 regval);
871 }
872 write_memory (gparam, val, TYPE_LENGTH (type));
873 }
874 /* Always consume parameter stack space. */
875 freg++;
876 greg++;
877 gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
878 }
879 else if (TYPE_CODE (type) == TYPE_CODE_FLT
880 && TYPE_LENGTH (type) == 16
881 && (gdbarch_long_double_format (current_gdbarch)
882 == floatformats_ibm_long_double))
883 {
884 /* IBM long double stored in two doublewords of the
885 parameter save area and corresponding registers. */
886 if (write_pass)
887 {
888 if (!tdep->soft_float && freg <= 13)
889 {
890 regcache_cooked_write (regcache,
891 tdep->ppc_fp0_regnum + freg,
892 val);
893 if (freg <= 12)
894 regcache_cooked_write (regcache,
895 tdep->ppc_fp0_regnum + freg + 1,
896 val + 8);
897 }
898 if (greg <= 10)
899 {
900 regcache_cooked_write (regcache,
901 tdep->ppc_gp0_regnum + greg,
902 val);
903 if (greg <= 9)
904 regcache_cooked_write (regcache,
905 tdep->ppc_gp0_regnum + greg + 1,
906 val + 8);
907 }
908 write_memory (gparam, val, TYPE_LENGTH (type));
909 }
910 freg += 2;
911 greg += 2;
912 gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
913 }
914 else if (TYPE_LENGTH (type) == 16 && TYPE_VECTOR (type)
915 && TYPE_CODE (type) == TYPE_CODE_ARRAY
916 && tdep->ppc_vr0_regnum >= 0)
917 {
918 /* In the Altivec ABI, vectors go in the vector
919 registers v2 .. v13, or when that runs out, a vector
920 annex which goes above all the normal parameters.
921 NOTE: cagney/2003-09-21: This is a guess based on the
922 PowerOpen Altivec ABI. */
923 if (vreg <= 13)
924 {
925 if (write_pass)
926 regcache_cooked_write (regcache,
927 tdep->ppc_vr0_regnum + vreg, val);
928 vreg++;
929 }
930 else
931 {
932 if (write_pass)
933 write_memory (vparam, val, TYPE_LENGTH (type));
934 vparam = align_up (vparam + TYPE_LENGTH (type), 16);
935 }
936 }
937 else if ((TYPE_CODE (type) == TYPE_CODE_INT
938 || TYPE_CODE (type) == TYPE_CODE_ENUM
939 || TYPE_CODE (type) == TYPE_CODE_PTR)
940 && TYPE_LENGTH (type) <= 8)
941 {
942 /* Scalars and Pointers get sign[un]extended and go in
943 gpr3 .. gpr10. They can also end up in memory. */
944 if (write_pass)
945 {
946 /* Sign extend the value, then store it unsigned. */
947 ULONGEST word = unpack_long (type, val);
948 /* Convert any function code addresses into
949 descriptors. */
950 if (TYPE_CODE (type) == TYPE_CODE_PTR
951 && TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)
952 {
953 CORE_ADDR desc = word;
954 convert_code_addr_to_desc_addr (word, &desc);
955 word = desc;
956 }
957 if (greg <= 10)
958 regcache_cooked_write_unsigned (regcache,
959 tdep->ppc_gp0_regnum +
960 greg, word);
961 write_memory_unsigned_integer (gparam, tdep->wordsize,
962 word);
963 }
964 greg++;
965 gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
966 }
967 else
968 {
969 int byte;
970 for (byte = 0; byte < TYPE_LENGTH (type);
971 byte += tdep->wordsize)
972 {
973 if (write_pass && greg <= 10)
974 {
975 gdb_byte regval[MAX_REGISTER_SIZE];
976 int len = TYPE_LENGTH (type) - byte;
977 if (len > tdep->wordsize)
978 len = tdep->wordsize;
979 memset (regval, 0, sizeof regval);
980 /* WARNING: cagney/2003-09-21: As best I can
981 tell, the ABI specifies that the value should
982 be left aligned. Unfortunately, GCC doesn't
983 do this - it instead right aligns even sized
984 values and puts odd sized values on the
985 stack. Work around that by putting both a
986 left and right aligned value into the
987 register (hopefully no one notices :-^).
988 Arrrgh! */
989 /* Left aligned (8 byte values such as pointers
990 fill the buffer). */
991 memcpy (regval, val + byte, len);
992 /* Right aligned (but only if even). */
993 if (len == 1 || len == 2 || len == 4)
994 memcpy (regval + tdep->wordsize - len,
995 val + byte, len);
996 regcache_cooked_write (regcache, greg, regval);
997 }
998 greg++;
999 }
1000 if (write_pass)
1001 /* WARNING: cagney/2003-09-21: Strictly speaking, this
1002 isn't necessary, unfortunately, GCC appears to get
1003 "struct convention" parameter passing wrong putting
1004 odd sized structures in memory instead of in a
1005 register. Work around this by always writing the
1006 value to memory. Fortunately, doing this
1007 simplifies the code. */
1008 write_memory (gparam, val, TYPE_LENGTH (type));
1009 if (write_pass)
1010 /* WARNING: cagney/2004-06-20: It appears that GCC
1011 likes to put structures containing a single
1012 floating-point member in an FP register instead of
1013 general general purpose. */
1014 /* Always consume parameter stack space. */
1015 gparam = align_up (gparam + TYPE_LENGTH (type), tdep->wordsize);
1016 }
1017 }
1018
1019 if (!write_pass)
1020 {
1021 /* Save the true region sizes ready for the second pass. */
1022 vparam_size = vparam;
1023 /* Make certain that the general parameter save area is at
1024 least the minimum 8 registers (or doublewords) in size. */
1025 if (greg < 8)
1026 gparam_size = 8 * tdep->wordsize;
1027 else
1028 gparam_size = gparam;
1029 }
1030 }
1031
1032 /* Update %sp. */
1033 regcache_cooked_write_signed (regcache,
1034 gdbarch_sp_regnum (current_gdbarch), sp);
1035
1036 /* Write the backchain (it occupies WORDSIZED bytes). */
1037 write_memory_signed_integer (sp, tdep->wordsize, back_chain);
1038
1039 /* Point the inferior function call's return address at the dummy's
1040 breakpoint. */
1041 regcache_cooked_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1042
1043 /* Use the func_addr to find the descriptor, and use that to find
1044 the TOC. */
1045 {
1046 CORE_ADDR desc_addr;
1047 if (convert_code_addr_to_desc_addr (func_addr, &desc_addr))
1048 {
1049 /* The TOC is the second double word in the descriptor. */
1050 CORE_ADDR toc =
1051 read_memory_unsigned_integer (desc_addr + tdep->wordsize,
1052 tdep->wordsize);
1053 regcache_cooked_write_unsigned (regcache,
1054 tdep->ppc_gp0_regnum + 2, toc);
1055 }
1056 }
1057
1058 return sp;
1059 }
1060
1061
1062 /* The 64 bit ABI return value convention.
1063
1064 Return non-zero if the return-value is stored in a register, return
1065 0 if the return-value is instead stored on the stack (a.k.a.,
1066 struct return convention).
1067
1068 For a return-value stored in a register: when WRITEBUF is non-NULL,
1069 copy the buffer to the corresponding register return-value location
1070 location; when READBUF is non-NULL, fill the buffer from the
1071 corresponding register return-value location. */
1072 enum return_value_convention
1073 ppc64_sysv_abi_return_value (struct gdbarch *gdbarch, struct type *valtype,
1074 struct regcache *regcache, gdb_byte *readbuf,
1075 const gdb_byte *writebuf)
1076 {
1077 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1078
1079 /* This function exists to support a calling convention that
1080 requires floating-point registers. It shouldn't be used on
1081 processors that lack them. */
1082 gdb_assert (ppc_floating_point_unit_p (gdbarch));
1083
1084 /* Floats and doubles in F1. */
1085 if (TYPE_CODE (valtype) == TYPE_CODE_FLT && TYPE_LENGTH (valtype) <= 8)
1086 {
1087 gdb_byte regval[MAX_REGISTER_SIZE];
1088 struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
1089 if (writebuf != NULL)
1090 {
1091 convert_typed_floating (writebuf, valtype, regval, regtype);
1092 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
1093 }
1094 if (readbuf != NULL)
1095 {
1096 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
1097 convert_typed_floating (regval, regtype, readbuf, valtype);
1098 }
1099 return RETURN_VALUE_REGISTER_CONVENTION;
1100 }
1101 /* Integers in r3. */
1102 if ((TYPE_CODE (valtype) == TYPE_CODE_INT
1103 || TYPE_CODE (valtype) == TYPE_CODE_ENUM)
1104 && TYPE_LENGTH (valtype) <= 8)
1105 {
1106 if (writebuf != NULL)
1107 {
1108 /* Be careful to sign extend the value. */
1109 regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1110 unpack_long (valtype, writebuf));
1111 }
1112 if (readbuf != NULL)
1113 {
1114 /* Extract the integer from r3. Since this is truncating the
1115 value, there isn't a sign extension problem. */
1116 ULONGEST regval;
1117 regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1118 &regval);
1119 store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval);
1120 }
1121 return RETURN_VALUE_REGISTER_CONVENTION;
1122 }
1123 /* All pointers live in r3. */
1124 if (TYPE_CODE (valtype) == TYPE_CODE_PTR)
1125 {
1126 /* All pointers live in r3. */
1127 if (writebuf != NULL)
1128 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
1129 if (readbuf != NULL)
1130 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, readbuf);
1131 return RETURN_VALUE_REGISTER_CONVENTION;
1132 }
1133 /* Array type has more than one use. */
1134 if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1135 {
1136 /* Small character arrays are returned, right justified, in r3. */
1137 if (TYPE_LENGTH (valtype) <= 8
1138 && TYPE_CODE (TYPE_TARGET_TYPE (valtype)) == TYPE_CODE_INT
1139 && TYPE_LENGTH (TYPE_TARGET_TYPE (valtype)) == 1)
1140 {
1141 int offset = (register_size (gdbarch, tdep->ppc_gp0_regnum + 3)
1142 - TYPE_LENGTH (valtype));
1143 if (writebuf != NULL)
1144 regcache_cooked_write_part (regcache, tdep->ppc_gp0_regnum + 3,
1145 offset, TYPE_LENGTH (valtype), writebuf);
1146 if (readbuf != NULL)
1147 regcache_cooked_read_part (regcache, tdep->ppc_gp0_regnum + 3,
1148 offset, TYPE_LENGTH (valtype), readbuf);
1149 return RETURN_VALUE_REGISTER_CONVENTION;
1150 }
1151 /* A VMX vector is returned in v2. */
1152 if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1153 && TYPE_VECTOR (valtype) && tdep->ppc_vr0_regnum >= 0)
1154 {
1155 if (readbuf)
1156 regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
1157 if (writebuf)
1158 regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
1159 return RETURN_VALUE_REGISTER_CONVENTION;
1160 }
1161 }
1162 /* Big floating point values get stored in adjacent floating
1163 point registers, starting with F1. */
1164 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
1165 && (TYPE_LENGTH (valtype) == 16 || TYPE_LENGTH (valtype) == 32))
1166 {
1167 if (writebuf || readbuf != NULL)
1168 {
1169 int i;
1170 for (i = 0; i < TYPE_LENGTH (valtype) / 8; i++)
1171 {
1172 if (writebuf != NULL)
1173 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1 + i,
1174 (const bfd_byte *) writebuf + i * 8);
1175 if (readbuf != NULL)
1176 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1 + i,
1177 (bfd_byte *) readbuf + i * 8);
1178 }
1179 }
1180 return RETURN_VALUE_REGISTER_CONVENTION;
1181 }
1182 /* Complex values get returned in f1:f2, need to convert. */
1183 if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX
1184 && (TYPE_LENGTH (valtype) == 8 || TYPE_LENGTH (valtype) == 16))
1185 {
1186 if (regcache != NULL)
1187 {
1188 int i;
1189 for (i = 0; i < 2; i++)
1190 {
1191 gdb_byte regval[MAX_REGISTER_SIZE];
1192 struct type *regtype =
1193 register_type (current_gdbarch, tdep->ppc_fp0_regnum);
1194 if (writebuf != NULL)
1195 {
1196 convert_typed_floating ((const bfd_byte *) writebuf +
1197 i * (TYPE_LENGTH (valtype) / 2),
1198 valtype, regval, regtype);
1199 regcache_cooked_write (regcache,
1200 tdep->ppc_fp0_regnum + 1 + i,
1201 regval);
1202 }
1203 if (readbuf != NULL)
1204 {
1205 regcache_cooked_read (regcache,
1206 tdep->ppc_fp0_regnum + 1 + i,
1207 regval);
1208 convert_typed_floating (regval, regtype,
1209 (bfd_byte *) readbuf +
1210 i * (TYPE_LENGTH (valtype) / 2),
1211 valtype);
1212 }
1213 }
1214 }
1215 return RETURN_VALUE_REGISTER_CONVENTION;
1216 }
1217 /* Big complex values get stored in f1:f4. */
1218 if (TYPE_CODE (valtype) == TYPE_CODE_COMPLEX && TYPE_LENGTH (valtype) == 32)
1219 {
1220 if (regcache != NULL)
1221 {
1222 int i;
1223 for (i = 0; i < 4; i++)
1224 {
1225 if (writebuf != NULL)
1226 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1 + i,
1227 (const bfd_byte *) writebuf + i * 8);
1228 if (readbuf != NULL)
1229 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1 + i,
1230 (bfd_byte *) readbuf + i * 8);
1231 }
1232 }
1233 return RETURN_VALUE_REGISTER_CONVENTION;
1234 }
1235 return RETURN_VALUE_STRUCT_CONVENTION;
1236 }
1237
1238 CORE_ADDR
1239 ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
1240 CORE_ADDR bpaddr)
1241 {
1242 /* PPC64 SYSV specifies that the minimal-symbol "FN" should point at
1243 a function-descriptor while the corresponding minimal-symbol
1244 ".FN" should point at the entry point. Consequently, a command
1245 like "break FN" applied to an object file with only minimal
1246 symbols, will insert the breakpoint into the descriptor at "FN"
1247 and not the function at ".FN". Avoid this confusion by adjusting
1248 any attempt to set a descriptor breakpoint into a corresponding
1249 function breakpoint. Note that GDB warns the user when this
1250 adjustment is applied - that's ok as otherwise the user will have
1251 no way of knowing why their breakpoint at "FN" resulted in the
1252 program stopping at ".FN". */
1253 return gdbarch_convert_from_func_ptr_addr (gdbarch, bpaddr, &current_target);
1254 }
This page took 0.056318 seconds and 4 git commands to generate.