[PowerPC] Add support for PPR and DSCR
[deliverable/binutils-gdb.git] / gdb / ppc-tdep.h
1 /* Target-dependent code for GDB, the GNU debugger.
2
3 Copyright (C) 2000-2018 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #ifndef PPC_TDEP_H
21 #define PPC_TDEP_H
22
23 struct gdbarch;
24 struct frame_info;
25 struct value;
26 struct regcache;
27 struct type;
28
29 /* From ppc-sysv-tdep.c ... */
30 enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
31 struct value *function,
32 struct type *valtype,
33 struct regcache *regcache,
34 gdb_byte *readbuf,
35 const gdb_byte *writebuf);
36 enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
37 struct value *function,
38 struct type *valtype,
39 struct regcache *regcache,
40 gdb_byte *readbuf,
41 const gdb_byte *writebuf);
42 CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
43 struct value *function,
44 struct regcache *regcache,
45 CORE_ADDR bp_addr, int nargs,
46 struct value **args, CORE_ADDR sp,
47 int struct_return,
48 CORE_ADDR struct_addr);
49 CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
50 struct value *function,
51 struct regcache *regcache,
52 CORE_ADDR bp_addr, int nargs,
53 struct value **args, CORE_ADDR sp,
54 int struct_return,
55 CORE_ADDR struct_addr);
56 enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
57 struct value *function,
58 struct type *valtype,
59 struct regcache *regcache,
60 gdb_byte *readbuf,
61 const gdb_byte *writebuf);
62
63 /* From rs6000-tdep.c... */
64 int altivec_register_p (struct gdbarch *gdbarch, int regno);
65 int vsx_register_p (struct gdbarch *gdbarch, int regno);
66 int spe_register_p (struct gdbarch *gdbarch, int regno);
67
68 /* Return non-zero if the architecture described by GDBARCH has
69 floating-point registers (f0 --- f31 and fpscr). */
70 int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
71
72 /* Return non-zero if the architecture described by GDBARCH has
73 Altivec registers (vr0 --- vr31, vrsave and vscr). */
74 int ppc_altivec_support_p (struct gdbarch *gdbarch);
75
76 /* Return non-zero if the architecture described by GDBARCH has
77 VSX registers (vsr0 --- vsr63). */
78 int vsx_support_p (struct gdbarch *gdbarch);
79 std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
80 (struct regcache *regcache);
81
82
83 /* Register set description. */
84
85 struct ppc_reg_offsets
86 {
87 /* General-purpose registers. */
88 int r0_offset;
89 int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
90 int xr_size; /* size for cr, xer, mq. */
91 int pc_offset;
92 int ps_offset;
93 int cr_offset;
94 int lr_offset;
95 int ctr_offset;
96 int xer_offset;
97 int mq_offset;
98
99 /* Floating-point registers. */
100 int f0_offset;
101 int fpscr_offset;
102 int fpscr_size;
103 };
104
105 extern void ppc_supply_reg (struct regcache *regcache, int regnum,
106 const gdb_byte *regs, size_t offset, int regsize);
107
108 extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
109 gdb_byte *regs, size_t offset, int regsize);
110
111 /* Supply register REGNUM in the general-purpose register set REGSET
112 from the buffer specified by GREGS and LEN to register cache
113 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
114
115 extern void ppc_supply_gregset (const struct regset *regset,
116 struct regcache *regcache,
117 int regnum, const void *gregs, size_t len);
118
119 /* Supply register REGNUM in the floating-point register set REGSET
120 from the buffer specified by FPREGS and LEN to register cache
121 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
122
123 extern void ppc_supply_fpregset (const struct regset *regset,
124 struct regcache *regcache,
125 int regnum, const void *fpregs, size_t len);
126
127 /* Supply register REGNUM in the Altivec register set REGSET
128 from the buffer specified by VRREGS and LEN to register cache
129 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
130
131 extern void ppc_supply_vrregset (const struct regset *regset,
132 struct regcache *regcache,
133 int regnum, const void *vrregs, size_t len);
134
135 /* Supply register REGNUM in the VSX register set REGSET
136 from the buffer specified by VSXREGS and LEN to register cache
137 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
138
139 extern void ppc_supply_vsxregset (const struct regset *regset,
140 struct regcache *regcache,
141 int regnum, const void *vsxregs, size_t len);
142
143 /* Collect register REGNUM in the general-purpose register set
144 REGSET, from register cache REGCACHE into the buffer specified by
145 GREGS and LEN. If REGNUM is -1, do this for all registers in
146 REGSET. */
147
148 extern void ppc_collect_gregset (const struct regset *regset,
149 const struct regcache *regcache,
150 int regnum, void *gregs, size_t len);
151
152 /* Collect register REGNUM in the floating-point register set
153 REGSET, from register cache REGCACHE into the buffer specified by
154 FPREGS and LEN. If REGNUM is -1, do this for all registers in
155 REGSET. */
156
157 extern void ppc_collect_fpregset (const struct regset *regset,
158 const struct regcache *regcache,
159 int regnum, void *fpregs, size_t len);
160
161 /* Collect register REGNUM in the Altivec register set
162 REGSET from register cache REGCACHE into the buffer specified by
163 VRREGS and LEN. If REGNUM is -1, do this for all registers in
164 REGSET. */
165
166 extern void ppc_collect_vrregset (const struct regset *regset,
167 const struct regcache *regcache,
168 int regnum, void *vrregs, size_t len);
169
170 /* Collect register REGNUM in the VSX register set
171 REGSET from register cache REGCACHE into the buffer specified by
172 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
173 REGSET. */
174
175 extern void ppc_collect_vsxregset (const struct regset *regset,
176 const struct regcache *regcache,
177 int regnum, void *vsxregs, size_t len);
178
179 /* Private data that this module attaches to struct gdbarch. */
180
181 /* ELF ABI version used by the inferior. */
182 enum powerpc_elf_abi
183 {
184 POWERPC_ELF_AUTO,
185 POWERPC_ELF_V1,
186 POWERPC_ELF_V2,
187 POWERPC_ELF_LAST
188 };
189
190 /* Vector ABI used by the inferior. */
191 enum powerpc_vector_abi
192 {
193 POWERPC_VEC_AUTO,
194 POWERPC_VEC_GENERIC,
195 POWERPC_VEC_ALTIVEC,
196 POWERPC_VEC_SPE,
197 POWERPC_VEC_LAST
198 };
199
200 /* long double ABI version used by the inferior. */
201 enum powerpc_long_double_abi
202 {
203 POWERPC_LONG_DOUBLE_AUTO,
204 POWERPC_LONG_DOUBLE_IBM128,
205 POWERPC_LONG_DOUBLE_IEEE128,
206 POWERPC_LONG_DOUBLE_LAST
207 };
208
209 struct gdbarch_tdep
210 {
211 int wordsize; /* Size in bytes of fixed-point word. */
212 int soft_float; /* Avoid FP registers for arguments? */
213
214 enum powerpc_elf_abi elf_abi; /* ELF ABI version. */
215
216 /* Format to use for the "long double" data type. */
217 enum powerpc_long_double_abi long_double_abi;
218
219 /* How to pass vector arguments. Never set to AUTO or LAST. */
220 enum powerpc_vector_abi vector_abi;
221
222 int ppc_gp0_regnum; /* GPR register 0 */
223 int ppc_toc_regnum; /* TOC register */
224 int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
225 int ppc_cr_regnum; /* Condition register */
226 int ppc_lr_regnum; /* Link register */
227 int ppc_ctr_regnum; /* Count register */
228 int ppc_xer_regnum; /* Integer exception register */
229
230 /* Not all PPC and RS6000 variants will have the registers
231 represented below. A -1 is used to indicate that the register
232 is not present in this variant. */
233
234 /* Floating-point registers. */
235 int ppc_fp0_regnum; /* Floating-point register 0. */
236 int ppc_fpscr_regnum; /* fp status and condition register. */
237
238 /* Multiplier-Quotient Register (older POWER architectures only). */
239 int ppc_mq_regnum;
240
241 /* POWER7 VSX registers. */
242 int ppc_vsr0_regnum; /* First VSX register. */
243 int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */
244 int ppc_efpr0_regnum; /* First Extended FP register. */
245
246 /* Altivec registers. */
247 int ppc_vr0_regnum; /* First AltiVec register. */
248 int ppc_vrsave_regnum; /* Last AltiVec register. */
249
250 /* SPE registers. */
251 int ppc_ev0_upper_regnum; /* First GPR upper half register. */
252 int ppc_ev0_regnum; /* First ev register. */
253 int ppc_acc_regnum; /* SPE 'acc' register. */
254 int ppc_spefscr_regnum; /* SPE 'spefscr' register. */
255
256 /* Program Priority Register. */
257 int ppc_ppr_regnum;
258
259 /* Data Stream Control Register. */
260 int ppc_dscr_regnum;
261
262 /* Decimal 128 registers. */
263 int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
264
265 /* Offset to ABI specific location where link register is saved. */
266 int lr_frame_offset;
267
268 /* An array of integers, such that sim_regno[I] is the simulator
269 register number for GDB register number I, or -1 if the
270 simulator does not implement that register. */
271 int *sim_regno;
272
273 /* ISA-specific types. */
274 struct type *ppc_builtin_type_vec64;
275 struct type *ppc_builtin_type_vec128;
276
277 int (*ppc_syscall_record) (struct regcache *regcache);
278 };
279
280
281 /* Constants for register set sizes. */
282 enum
283 {
284 ppc_num_gprs = 32, /* 32 general-purpose registers. */
285 ppc_num_fprs = 32, /* 32 floating-point registers. */
286 ppc_num_srs = 16, /* 16 segment registers. */
287 ppc_num_vrs = 32, /* 32 Altivec vector registers. */
288 ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */
289 ppc_num_vsrs = 64, /* 64 VSX vector registers. */
290 ppc_num_efprs = 32 /* 32 Extended FP registers. */
291 };
292
293
294 /* Register number constants. These are GDB internal register
295 numbers; they are not used for the simulator or remote targets.
296 Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
297 numbers above PPC_NUM_REGS. So are segment registers and other
298 target-defined registers. */
299 enum {
300 PPC_R0_REGNUM = 0,
301 PPC_F0_REGNUM = 32,
302 PPC_PC_REGNUM = 64,
303 PPC_MSR_REGNUM = 65,
304 PPC_CR_REGNUM = 66,
305 PPC_LR_REGNUM = 67,
306 PPC_CTR_REGNUM = 68,
307 PPC_XER_REGNUM = 69,
308 PPC_FPSCR_REGNUM = 70,
309 PPC_MQ_REGNUM = 71,
310 PPC_SPE_UPPER_GP0_REGNUM = 72,
311 PPC_SPE_ACC_REGNUM = 104,
312 PPC_SPE_FSCR_REGNUM = 105,
313 PPC_VR0_REGNUM = 106,
314 PPC_VSCR_REGNUM = 138,
315 PPC_VRSAVE_REGNUM = 139,
316 PPC_VSR0_UPPER_REGNUM = 140,
317 PPC_VSR31_UPPER_REGNUM = 171,
318 PPC_PPR_REGNUM = 172,
319 PPC_DSCR_REGNUM = 173,
320 PPC_NUM_REGS
321 };
322
323 /* Big enough to hold the size of the largest register in bytes. */
324 #define PPC_MAX_REGISTER_SIZE 64
325
326 /* An instruction to match. */
327
328 struct ppc_insn_pattern
329 {
330 unsigned int mask; /* mask the insn with this... */
331 unsigned int data; /* ...and see if it matches this. */
332 int optional; /* If non-zero, this insn may be absent. */
333 };
334
335 extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
336 const struct ppc_insn_pattern *pattern,
337 unsigned int *insns);
338 extern CORE_ADDR ppc_insn_d_field (unsigned int insn);
339
340 extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);
341
342 extern int ppc_process_record (struct gdbarch *gdbarch,
343 struct regcache *regcache, CORE_ADDR addr);
344
345 /* Instruction size. */
346 #define PPC_INSN_SIZE 4
347
348 /* Estimate for the maximum number of instrctions in a function epilogue. */
349 #define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
350
351 #endif /* ppc-tdep.h */
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