gdb/pyr-opcode.h

   1 /* pyramid.opcode.h -- gdb initial attempt. */
   2
   3 /* pyramid opcode table: wot to do with this
   4    particular opcode */
   5
   6 struct pyr_datum
   7 {
   8   char              nargs;
   9   char *            args;       /* how to compile said opcode */
  10   unsigned long     mask;       /* Bit vector: which operand modes are valid
  11                                    for this opcode */
  12   unsigned char     code;       /* op-code (always 6(?) bits */
  13 };
  14
  15 typedef struct pyr_insn_format {
  16     unsigned int mode :4;
  17     unsigned int operator :8;
  18     unsigned int index_scale :2;
  19     unsigned int index_reg :6;
  20     unsigned int operand_1 :6;
  21     unsigned int operand_2:6;
  22 } pyr_insn_format;
  23
  24
  25 /* We store four bytes of opcode for all opcodes.
  26    Pyramid is sufficiently RISCy that:
  27       - insns are always an integral number of words;
  28       - the length of any insn can be told from the first word of
  29         the insn. (ie, if there are zero, one, or two words of
  30         immediate operand/offset).
  31
  32
  33    The args component is a string containing two characters for each
  34    operand of the instruction.  The first specifies the kind of operand;
  35    the second, the place it is stored. */
  36
  37 /* Kinds of operands:
  38    mask  assembler syntax       description
  39    0x0001:  movw Rn,Rn          register to register
  40    0x0002:  movw K,Rn           quick immediate to register
  41    0x0004:  movw I,Rn           long immediate to register
  42    0x0008:  movw (Rn),Rn        register indirect to register
  43             movw (Rn)[x],Rn     register indirect to register
  44    0x0010:  movw I(Rn),Rn       offset register indirect to register
  45             movw I(Rn)[x],Rn    offset register indirect, indexed, to register
  46
  47    0x0020:  movw Rn,(Rn)        register to register indirect
  48    0x0040:  movw K,(Rn)         quick immediate to register indirect
  49    0x0080:  movw I,(Rn)         long immediate to register indirect
  50    0x0100:  movw (Rn),(Rn)      register indirect to-register indirect
  51    0x0100:  movw (Rn),(Rn)      register indirect to-register indirect
  52    0x0200:  movw I(Rn),(Rn)     register indirect+offset to register indirect
  53    0x0200:  movw I(Rn),(Rn)     register indirect+offset to register indirect
  54
  55    0x0400:  movw Rn,I(Rn)       register to register indirect+offset
  56    0x0800:  movw K,I(Rn)        quick immediate to register indirect+offset
  57    0x1000:  movw I,I(Rn)        long immediate to register indirect+offset
  58    0x1000:  movw (Rn),I(Rn)     register indirect to-register indirect+offset
  59    0x1000:  movw I(Rn),I(Rn)    register indirect+offset to register indirect
  60                                         +offset
  61    0x0000:  (irregular)         ???
  62
  63
  64    Each insn has a four-bit field encoding the type(s) of its operands.
  65 */
  66
  67 /* Some common combinations
  68    */
  69
  70 /* the first 5,(0x1|0x2|0x4|0x8|0x10) ie (1|2|4|8|16), ie ( 32 -1)*/
  71 #define GEN_TO_REG (31)
  72
  73 #define UNKNOWN ((unsigned long)-1)
  74 #define ANY (GEN_TO_REG | (GEN_TO_REG << 5) | (GEN_TO_REG << 15))
  75
  76 #define CONVERT (1|8|0x10|0x20|0x200)
  77
  78 #define K_TO_REG (2)
  79 #define I_TO_REG (4)
  80 #define NOTK_TO_REG (GEN_TO_REG & ~K_TO_REG)
  81 #define NOTI_TO_REG (GEN_TO_REG & ~I_TO_REG)
  82
  83 /* The assembler requires that this array be sorted as follows:
  84    all instances of the same mnemonic must be consecutive.
  85    All instances of the same mnemonic with the same number of operands
  86    must be consecutive.
  87  */
  88
  89 struct pyr_opcode               /* pyr opcode text */
  90 {
  91   char *            name;       /* opcode name: lowercase string  [key]  */
  92   struct pyr_datum  datum;      /* rest of opcode table          [datum] */
  93 };
  94
  95 #define pyr_how args
  96 #define pyr_nargs nargs
  97 #define pyr_mask mask
  98 #define pyr_name name
  99
 100 struct pyr_opcode pyr_opcodes[] =
 101 {
 102   {"movb",      { 2, "", UNKNOWN,               0x11}, },
 103   {"movh",      { 2, "", UNKNOWN,               0x12} },
 104   {"movw",      { 2, "", ANY,                   0x10} },
 105   {"movl",      { 2, "", ANY,                   0x13} },
 106   {"mnegw",     { 2, "", (0x1|0x8|0x10),        0x14} },
 107   {"mnegf",     { 2, "", 0x1,                   0x15} },
 108   {"mnegd",     { 2, "", 0x1,                   0x16} },
 109   {"mcomw",     { 2, "", (0x1|0x8|0x10),        0x17} },
 110   {"mabsw",     { 2, "", (0x1|0x8|0x10),        0x18} },
 111   {"mabsf",     { 2, "", 0x1,                   0x19} },
 112   {"mabsd",     { 2, "", 0x1,                   0x1a} },
 113   {"mtstw",     { 2, "", (0x1|0x8|0x10),        0x1c} },
 114   {"mtstf",     { 2, "", 0x1,                   0x1d} },
 115   {"mtstd",     { 2, "", 0x1,                   0x1e} },
 116   {"mova",      { 2, "", 0x8|0x10,              0x1f} },
 117   {"movzbw",    { 2, "", (0x1|0x8|0x10),        0x20} },
 118   {"movzhw",    { 2, "", (0x1|0x8|0x10),        0x21} },
 119                                 /* 2 insns out of order here */
 120   {"movbl",     { 2, "", 1,                     0x4f} },
 121   {"filbl",     { 2, "", 1,                     0x4e} },
 122
 123   {"cvtbw",     { 2, "", CONVERT,               0x22} },
 124   {"cvthw",     { 2, "", CONVERT,               0x23} },
 125   {"cvtwb",     { 2, "", CONVERT,               0x24} },
 126   {"cvtwh",     { 2, "", CONVERT,               0x25} },
 127   {"cvtwf",     { 2, "", CONVERT,               0x26} },
 128   {"cvtwd",     { 2, "", CONVERT,               0x27} },
 129   {"cvtfw",     { 2, "", CONVERT,               0x28} },
 130   {"cvtfd",     { 2, "", CONVERT,               0x29} },
 131   {"cvtdw",     { 2, "", CONVERT,               0x2a} },
 132   {"cvtdf",     { 2, "", CONVERT,               0x2b} },
 133
 134   {"addw",      { 2, "", GEN_TO_REG,            0x40} },
 135   {"addwc",     { 2, "", GEN_TO_REG,            0x41} },
 136   {"subw",      { 2, "", GEN_TO_REG,            0x42} },
 137   {"subwb",     { 2, "", GEN_TO_REG,            0x43} },
 138   {"rsubw",     { 2, "", GEN_TO_REG,            0x44} },
 139   {"mulw",      { 2, "", GEN_TO_REG,            0x45} },
 140   {"emul",      { 2, "", GEN_TO_REG,            0x47} },
 141   {"umulw",     { 2, "", GEN_TO_REG,            0x46} },
 142   {"divw",      { 2, "", GEN_TO_REG,            0x48} },
 143   {"ediv",      { 2, "", GEN_TO_REG,            0x4a} },
 144   {"rdivw",     { 2, "", GEN_TO_REG,            0x4b} },
 145   {"udivw",     { 2, "", GEN_TO_REG,            0x49} },
 146   {"modw",      { 2, "", GEN_TO_REG,            0x4c} },
 147   {"umodw",     { 2, "", GEN_TO_REG,            0x4d} },
 148
 149
 150   {"addf",      { 2, "", 1,                     0x50} },
 151   {"addd",      { 2, "", 1,                     0x51} },
 152   {"subf",      { 2, "", 1,                     0x52} },
 153   {"subd",      { 2, "", 1,                     0x53} },
 154   {"mulf",      { 2, "", 1,                     0x56} },
 155   {"muld",      { 2, "", 1,                     0x57} },
 156   {"divf",      { 2, "", 1,                     0x58} },
 157   {"divd",      { 2, "", 1,                     0x59} },
 158
 159
 160   {"cmpb",      { 2, "", UNKNOWN,               0x61} },
 161   {"cmph",      { 2, "", UNKNOWN,               0x62} },
 162   {"cmpw",      { 2, "", UNKNOWN,               0x60} },
 163   {"ucmpb",     { 2, "", UNKNOWN,               0x66} },
 164   /* WHY no "ucmph"??? */
 165   {"ucmpw",     { 2, "", UNKNOWN,               0x65} },
 166   {"xchw",      { 2, "", UNKNOWN,               0x0f} },
 167
 168
 169   {"andw",      { 2, "", GEN_TO_REG,            0x30} },
 170   {"orw",       { 2, "", GEN_TO_REG,            0x31} },
 171   {"xorw",      { 2, "", GEN_TO_REG,            0x32} },
 172   {"bicw",      { 2, "", GEN_TO_REG,            0x33} },
 173   {"lshlw",     { 2, "", GEN_TO_REG,            0x38} },
 174   {"ashlw",     { 2, "", GEN_TO_REG,            0x3a} },
 175   {"ashll",     { 2, "", GEN_TO_REG,            0x3c} },
 176   {"ashrw",     { 2, "", GEN_TO_REG,            0x3b} },
 177   {"ashrl",     { 2, "", GEN_TO_REG,            0x3d} },
 178   {"rotlw",     { 2, "", GEN_TO_REG,            0x3e} },
 179   {"rotrw",     { 2, "", GEN_TO_REG,            0x3f} },
 180
 181   /* push and pop insns are "going away next release". */
 182   {"pushw",     { 2, "", GEN_TO_REG,            0x0c} },
 183   {"popw",      { 2, "", (0x1|0x8|0x10),        0x0d} },
 184   {"pusha",     { 2, "", (0x8|0x10),            0x0e} },
 185
 186   {"bitsw",     { 2, "", UNKNOWN,               0x35} },
 187   {"bitcw",     { 2, "", UNKNOWN,               0x36} },
 188   /* some kind of ibra/dbra insns??*/
 189   {"icmpw",     { 2, "", UNKNOWN,               0x67} },
 190   {"dcmpw",     { 2, "", (1|4|0x20|0x80|0x400|0x1000),  0x69} },/*FIXME*/
 191   {"acmpw",     { 2, "", 1,                     0x6b} },
 192
 193   /* Call is written as a 1-op insn, but is always (dis)assembled as a 2-op
 194      insn with a 2nd op of tr14.   The assembler will have to grok this.  */
 195   {"call",      { 2, "", GEN_TO_REG,            0x04} },
 196   {"call",      { 1, "", GEN_TO_REG,            0x04} },
 197
 198   {"callk",     { 1, "", UNKNOWN,               0x06} },/* system call?*/
 199   /* Ret is usually written as a 0-op insn, but gets disassembled as a
 200      1-op insn. The operand is always tr15. */
 201   {"ret",       { 0, "", UNKNOWN,               0x09} },
 202   {"ret",       { 1, "", UNKNOWN,               0x09} },
 203   {"adsf",      { 2, "", (1|2|4),               0x08} },
 204   {"retd",      { 2, "", UNKNOWN,               0x0a} },
 205   {"btc",       { 2, "", UNKNOWN,               0x01} },
 206   {"bfc",       { 2, "", UNKNOWN,               0x02} },
 207   /* Careful: halt is 0x00000000. Jump must have some other (mode?)bit set?? */
 208   {"jump",      { 1, "", UNKNOWN,               0x00} },
 209   {"btp",       { 2, "", UNKNOWN,               0xf00} },
 210   /* read control-stack pointer is another 1-or-2 operand insn. */
 211   {"rcsp",      { 2, "", UNKNOWN,               0x01f} },
 212   {"rcsp",      { 1, "", UNKNOWN,               0x01f} }
 213 };
 214
 215 /* end: pyramid.opcode.h */
 216 /* One day I will have to take the time to find out what operands
 217    are valid for these insns, and guess at what they mean.
 218
 219    I can't imagine what the "I???" insns (iglob, etc) do.
 220
 221    the arithmetic-sounding insns ending in "p" sound awfully like BCD
 222    arithmetic insns:
 223         dshlp -> Decimal SHift Left Packed
 224         dshrp -> Decimal SHift Right Packed
 225    and cvtlp would be convert long to packed.
 226    I have no idea how the operands are interpreted; but having them be
 227    a long register with (address, length) of an in-memory packed BCD operand
 228    would not be surprising.
 229    They are unlikely to be a packed bcd string: 64 bits of long give
 230    is only 15 digits+sign, which isn't enough for COBOL.
 231  */
 232 #if 0
 233   {"wcsp",      { 2, "", UNKNOWN,               0x00} }, /*write csp?*/
 234   /* The OSx Operating System Porting Guide claims SSL does things
 235      with tr12 (a register reserved to it) to do with static block-structure
 236      references.  SSL=Set Static Link?  It's "Going away next release". */
 237   {"ssl",       { 2, "", UNKNOWN,               0x00} },
 238   {"ccmps",     { 2, "", UNKNOWN,               0x00} },
 239   {"lcd",       { 2, "", UNKNOWN,               0x00} },
 240   {"uemul",     { 2, "", UNKNOWN,               0x00} }, /*unsigned emul*/
 241   {"srf",       { 2, "", UNKNOWN,               0x00} }, /*Gidget time???*/
 242   {"mnegp",     { 2, "", UNKNOWN,               0x00} }, /move-neg phys?*/
 243   {"ldp",       { 2, "", UNKNOWN,               0x00} }, /*load phys?*/
 244   {"ldti",      { 2, "", UNKNOWN,               0x00} },
 245   {"ldb",       { 2, "", UNKNOWN,               0x00} },
 246   {"stp",       { 2, "", UNKNOWN,               0x00} },
 247   {"stti",      { 2, "", UNKNOWN,               0x00} },
 248   {"stb",       { 2, "", UNKNOWN,               0x00} },
 249   {"stu",       { 2, "", UNKNOWN,               0x00} },
 250   {"addp",      { 2, "", UNKNOWN,               0x00} },
 251   {"subp",      { 2, "", UNKNOWN,               0x00} },
 252   {"mulp",      { 2, "", UNKNOWN,               0x00} },
 253   {"divp",      { 2, "", UNKNOWN,               0x00} },
 254   {"dshlp",     { 2, "", UNKNOWN,               0x00} },  /* dec shl packed? */
 255   {"dshrp",     { 2, "", UNKNOWN,               0x00} }, /* dec shr packed? */
 256   {"movs",      { 2, "", UNKNOWN,               0x00} }, /*move (string?)?*/
 257   {"cmpp",      { 2, "", UNKNOWN,               0x00} }, /* cmp phys?*/
 258   {"cmps",      { 2, "", UNKNOWN,               0x00} }, /* cmp (string?)?*/
 259   {"cvtlp",     { 2, "", UNKNOWN,               0x00} }, /* cvt long to p??*/
 260   {"cvtpl",     { 2, "", UNKNOWN,               0x00} }, /* cvt p to l??*/
 261   {"dintr",     { 2, "", UNKNOWN,               0x00} }, /* ?? intr ?*/
 262   {"rphysw",    { 2, "", UNKNOWN,               0x00} }, /* read phys word?*/
 263   {"wphysw",    { 2, "", UNKNOWN,               0x00} }, /* write phys word?*/
 264   {"cmovs",     { 2, "", UNKNOWN,               0x00} },
 265   {"rsubw",     { 2, "", UNKNOWN,               0x00} },
 266   {"bicpsw",    { 2, "", UNKNOWN,               0x00} }, /* clr bit in psw? */
 267   {"bispsw",    { 2, "", UNKNOWN,               0x00} }, /* set bit in psw? */
 268   {"eio",       { 2, "", UNKNOWN,               0x00} }, /* ?? ?io ? */
 269   {"callp",     { 2, "", UNKNOWN,               0x00} }, /* call phys?*/
 270   {"callr",     { 2, "", UNKNOWN,               0x00} },
 271   {"lpcxt",     { 2, "", UNKNOWN,               0x00} }, /*load proc context*/
 272   {"rei",       { 2, "", UNKNOWN,               0x00} }, /*ret from intrpt*/
 273   {"rport",     { 2, "", UNKNOWN,               0x00} }, /*read-port?*/
 274   {"rtod",      { 2, "", UNKNOWN,               0x00} }, /*read-time-of-day?*/
 275   {"ssi",       { 2, "", UNKNOWN,               0x00} },
 276   {"vtpa",      { 2, "", UNKNOWN,               0x00} }, /*virt-to-phys-addr?*/
 277   {"wicl",      { 2, "", UNKNOWN,               0x00} }, /* write icl ? */
 278   {"wport",     { 2, "", UNKNOWN,               0x00} }, /*write-port?*/
 279   {"wtod",      { 2, "", UNKNOWN,               0x00} }, /*write-time-of-day?*/
 280   {"flic",      { 2, "", UNKNOWN,               0x00} },
 281   {"iglob",     { 2, "", UNKNOWN,               0x00} }, /* I global? */
 282   {"iphys",     { 2, "", UNKNOWN,               0x00} }, /* I physical? */
 283   {"ipid",      { 2, "", UNKNOWN,               0x00} }, /* I pid? */
 284   {"ivect",     { 2, "", UNKNOWN,               0x00} }, /* I vector? */
 285   {"lamst",     { 2, "", UNKNOWN,               0x00} },
 286   {"tio",       { 2, "", UNKNOWN,               0x00} },
 287 #endif