gdb/riscv-linux-nat.c

   1 /* Native-dependent code for GNU/Linux RISC-V.
   2    Copyright (C) 2018-2020 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #include "defs.h"
  20 #include "regcache.h"
  21 #include "gregset.h"
  22 #include "linux-nat.h"
  23 #include "riscv-tdep.h"
  24 #include "inferior.h"
  25 #include "target-descriptions.h"
  26
  27 #include "elf/common.h"
  28
  29 #include <sys/ptrace.h>
  30
  31 /* Work around glibc header breakage causing ELF_NFPREG not to be usable.  */
  32 #ifndef NFPREG
  33 # define NFPREG 33
  34 #endif
  35
  36 /* RISC-V Linux native additions to the default linux support.  */
  37
  38 class riscv_linux_nat_target final : public linux_nat_target
  39 {
  40 public:
  41   /* Add our register access methods.  */
  42   void fetch_registers (struct regcache *regcache, int regnum) override;
  43   void store_registers (struct regcache *regcache, int regnum) override;
  44
  45   /* Read suitable target description.  */
  46   const struct target_desc *read_description () override;
  47 };
  48
  49 static riscv_linux_nat_target the_riscv_linux_nat_target;
  50
  51 /* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)
  52    from regset GREGS into REGCACHE.  */
  53
  54 static void
  55 supply_gregset_regnum (struct regcache *regcache, const prgregset_t *gregs,
  56                        int regnum)
  57 {
  58   int i;
  59   const elf_greg_t *regp = *gregs;
  60
  61   if (regnum == -1)
  62     {
  63       /* We only support the integer registers and PC here.  */
  64       for (i = RISCV_ZERO_REGNUM + 1; i < RISCV_PC_REGNUM; i++)
  65         regcache->raw_supply (i, regp + i);
  66
  67       /* GDB stores PC in reg 32.  Linux kernel stores it in reg 0.  */
  68       regcache->raw_supply (32, regp + 0);
  69
  70       /* Fill the inaccessible zero register with zero.  */
  71       regcache->raw_supply_zeroed (0);
  72     }
  73   else if (regnum == RISCV_ZERO_REGNUM)
  74     regcache->raw_supply_zeroed (0);
  75   else if (regnum > RISCV_ZERO_REGNUM && regnum < RISCV_PC_REGNUM)
  76     regcache->raw_supply (regnum, regp + regnum);
  77   else if (regnum == RISCV_PC_REGNUM)
  78     regcache->raw_supply (32, regp + 0);
  79 }
  80
  81 /* Copy all general purpose registers from regset GREGS into REGCACHE.  */
  82
  83 void
  84 supply_gregset (struct regcache *regcache, const prgregset_t *gregs)
  85 {
  86   supply_gregset_regnum (regcache, gregs, -1);
  87 }
  88
  89 /* Copy floating point register REGNUM (or all fp regs if REGNUM == -1)
  90    from regset FPREGS into REGCACHE.  */
  91
  92 static void
  93 supply_fpregset_regnum (struct regcache *regcache, const prfpregset_t *fpregs,
  94                         int regnum)
  95 {
  96   int flen = register_size (regcache->arch (), RISCV_FIRST_FP_REGNUM);
  97   union
  98     {
  99       const prfpregset_t *fpregs;
 100       const gdb_byte *buf;
 101     }
 102   fpbuf = { .fpregs = fpregs };
 103   int i;
 104
 105   if (regnum == -1)
 106     {
 107       /* We only support the FP registers and FCSR here.  */
 108       for (i = RISCV_FIRST_FP_REGNUM;
 109            i <= RISCV_LAST_FP_REGNUM;
 110            i++, fpbuf.buf += flen)
 111         regcache->raw_supply (i, fpbuf.buf);
 112
 113       regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
 114     }
 115   else if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
 116     {
 117       fpbuf.buf += flen * (regnum - RISCV_FIRST_FP_REGNUM);
 118       regcache->raw_supply (regnum, fpbuf.buf);
 119     }
 120   else if (regnum == RISCV_CSR_FCSR_REGNUM)
 121     {
 122       fpbuf.buf += flen * (RISCV_LAST_FP_REGNUM - RISCV_FIRST_FP_REGNUM + 1);
 123       regcache->raw_supply (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
 124     }
 125 }
 126
 127 /* Copy all floating point registers from regset FPREGS into REGCACHE.  */
 128
 129 void
 130 supply_fpregset (struct regcache *regcache, const prfpregset_t *fpregs)
 131 {
 132   supply_fpregset_regnum (regcache, fpregs, -1);
 133 }
 134
 135 /* Copy general purpose register REGNUM (or all gp regs if REGNUM == -1)
 136    from REGCACHE into regset GREGS.  */
 137
 138 void
 139 fill_gregset (const struct regcache *regcache, prgregset_t *gregs, int regnum)
 140 {
 141   elf_greg_t *regp = *gregs;
 142
 143   if (regnum == -1)
 144     {
 145       /* We only support the integer registers and PC here.  */
 146       for (int i = RISCV_ZERO_REGNUM + 1; i < RISCV_PC_REGNUM; i++)
 147         regcache->raw_collect (i, regp + i);
 148
 149       regcache->raw_collect (32, regp + 0);
 150     }
 151   else if (regnum == RISCV_ZERO_REGNUM)
 152     /* Nothing to do here.  */
 153     ;
 154   else if (regnum > RISCV_ZERO_REGNUM && regnum < RISCV_PC_REGNUM)
 155     regcache->raw_collect (regnum, regp + regnum);
 156   else if (regnum == RISCV_PC_REGNUM)
 157     regcache->raw_collect (32, regp + 0);
 158 }
 159
 160 /* Copy floating point register REGNUM (or all fp regs if REGNUM == -1)
 161    from REGCACHE into regset FPREGS.  */
 162
 163 void
 164 fill_fpregset (const struct regcache *regcache, prfpregset_t *fpregs,
 165                int regnum)
 166 {
 167   int flen = register_size (regcache->arch (), RISCV_FIRST_FP_REGNUM);
 168   union
 169     {
 170       prfpregset_t *fpregs;
 171       gdb_byte *buf;
 172     }
 173   fpbuf = { .fpregs = fpregs };
 174   int i;
 175
 176   if (regnum == -1)
 177     {
 178       /* We only support the FP registers and FCSR here.  */
 179       for (i = RISCV_FIRST_FP_REGNUM;
 180            i <= RISCV_LAST_FP_REGNUM;
 181            i++, fpbuf.buf += flen)
 182         regcache->raw_collect (i, fpbuf.buf);
 183
 184       regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
 185     }
 186   else if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
 187     {
 188       fpbuf.buf += flen * (regnum - RISCV_FIRST_FP_REGNUM);
 189       regcache->raw_collect (regnum, fpbuf.buf);
 190     }
 191   else if (regnum == RISCV_CSR_FCSR_REGNUM)
 192     {
 193       fpbuf.buf += flen * (RISCV_LAST_FP_REGNUM - RISCV_FIRST_FP_REGNUM + 1);
 194       regcache->raw_collect (RISCV_CSR_FCSR_REGNUM, fpbuf.buf);
 195     }
 196 }
 197
 198 /* Return a target description for the current target.  */
 199
 200 const struct target_desc *
 201 riscv_linux_nat_target::read_description ()
 202 {
 203   struct riscv_gdbarch_features features;
 204   elf_fpregset_t regs;
 205   int flen;
 206   int tid;
 207
 208   /* Figuring out xlen is easy.  */
 209   features.xlen = sizeof (elf_greg_t);
 210
 211   tid = inferior_ptid.lwp ();
 212
 213   /* Start with no f-registers.  */
 214   features.flen = 0;
 215
 216   /* How much worth of f-registers can we fetch if any?  */
 217   for (flen = sizeof (regs.__f.__f[0]); ; flen *= 2)
 218     {
 219       size_t regset_size;
 220       struct iovec iov;
 221
 222       /* Regsets have a uniform slot size, so we count FSCR like
 223          an FP data register.  */
 224       regset_size = ELF_NFPREG * flen;
 225       if (regset_size > sizeof (regs))
 226         break;
 227
 228       iov.iov_base = &regs;
 229       iov.iov_len = regset_size;
 230       if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET,
 231                   (PTRACE_TYPE_ARG3) &iov) == -1)
 232         {
 233           switch (errno)
 234             {
 235             case EINVAL:
 236               continue;
 237             case EIO:
 238               break;
 239             default:
 240               perror_with_name (_("Couldn't get registers"));
 241               break;
 242             }
 243         }
 244       else
 245         features.flen = flen;
 246       break;
 247     }
 248
 249   return riscv_create_target_description (features);
 250 }
 251
 252 /* Fetch REGNUM (or all registers if REGNUM == -1) from the target
 253    into REGCACHE using PTRACE_GETREGSET.  */
 254
 255 void
 256 riscv_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
 257 {
 258   int tid;
 259
 260   tid = get_ptrace_pid (regcache->ptid());
 261
 262   if ((regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_PC_REGNUM)
 263       || (regnum == -1))
 264     {
 265       struct iovec iov;
 266       elf_gregset_t regs;
 267
 268       iov.iov_base = &regs;
 269       iov.iov_len = sizeof (regs);
 270
 271       if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS,
 272                   (PTRACE_TYPE_ARG3) &iov) == -1)
 273         perror_with_name (_("Couldn't get registers"));
 274       else
 275         supply_gregset_regnum (regcache, &regs, regnum);
 276     }
 277
 278   if ((regnum >= RISCV_FIRST_FP_REGNUM
 279        && regnum <= RISCV_LAST_FP_REGNUM)
 280       || (regnum == RISCV_CSR_FCSR_REGNUM)
 281       || (regnum == -1))
 282     {
 283       struct iovec iov;
 284       elf_fpregset_t regs;
 285
 286       iov.iov_base = &regs;
 287       iov.iov_len = ELF_NFPREG * register_size (regcache->arch (),
 288                                                 RISCV_FIRST_FP_REGNUM);
 289       gdb_assert (iov.iov_len <= sizeof (regs));
 290
 291       if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET,
 292                   (PTRACE_TYPE_ARG3) &iov) == -1)
 293         perror_with_name (_("Couldn't get registers"));
 294       else
 295         supply_fpregset_regnum (regcache, &regs, regnum);
 296     }
 297
 298   if ((regnum == RISCV_CSR_MISA_REGNUM)
 299       || (regnum == -1))
 300     {
 301       /* TODO: Need to add a ptrace call for this.  */
 302       regcache->raw_supply_zeroed (RISCV_CSR_MISA_REGNUM);
 303     }
 304
 305   /* Access to other CSRs has potential security issues, don't support them for
 306      now.  */
 307 }
 308
 309 /* Store REGNUM (or all registers if REGNUM == -1) to the target
 310    from REGCACHE using PTRACE_SETREGSET.  */
 311
 312 void
 313 riscv_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
 314 {
 315   int tid;
 316
 317   tid = get_ptrace_pid (regcache->ptid ());
 318
 319   if ((regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_PC_REGNUM)
 320       || (regnum == -1))
 321     {
 322       struct iovec iov;
 323       elf_gregset_t regs;
 324
 325       iov.iov_base = &regs;
 326       iov.iov_len = sizeof (regs);
 327
 328       if (ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS,
 329                   (PTRACE_TYPE_ARG3) &iov) == -1)
 330         perror_with_name (_("Couldn't get registers"));
 331       else
 332         {
 333           fill_gregset (regcache, &regs, regnum);
 334
 335           if (ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS,
 336                       (PTRACE_TYPE_ARG3) &iov) == -1)
 337             perror_with_name (_("Couldn't set registers"));
 338         }
 339     }
 340
 341   if ((regnum >= RISCV_FIRST_FP_REGNUM
 342        && regnum <= RISCV_LAST_FP_REGNUM)
 343       || (regnum == RISCV_CSR_FCSR_REGNUM)
 344       || (regnum == -1))
 345     {
 346       struct iovec iov;
 347       elf_fpregset_t regs;
 348
 349       iov.iov_base = &regs;
 350       iov.iov_len = ELF_NFPREG * register_size (regcache->arch (),
 351                                                 RISCV_FIRST_FP_REGNUM);
 352       gdb_assert (iov.iov_len <= sizeof (regs));
 353
 354       if (ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET,
 355                   (PTRACE_TYPE_ARG3) &iov) == -1)
 356         perror_with_name (_("Couldn't get registers"));
 357       else
 358         {
 359           fill_fpregset (regcache, &regs, regnum);
 360
 361           if (ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET,
 362                       (PTRACE_TYPE_ARG3) &iov) == -1)
 363             perror_with_name (_("Couldn't set registers"));
 364         }
 365     }
 366
 367   /* Access to CSRs has potential security issues, don't support them for
 368      now.  */
 369 }
 370
 371 /* Initialize RISC-V Linux native support.  */
 372
 373 void _initialize_riscv_linux_nat ();
 374 void
 375 _initialize_riscv_linux_nat ()
 376 {
 377   /* Register the target.  */
 378   linux_target = &the_riscv_linux_nat_target;
 379   add_inf_child_target (&the_riscv_linux_nat_target);
 380 }