1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
58 /* The stack must be 16-byte aligned. */
59 #define SP_ALIGNMENT 16
61 /* Forward declarations. */
62 static bool riscv_has_feature (struct gdbarch
*gdbarch
, char feature
);
63 struct riscv_inferior_data
;
64 struct riscv_inferior_data
* riscv_inferior_data (struct inferior
*const inf
);
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Per inferior information for RiscV. */
78 struct riscv_inferior_data
80 /* True when MISA_VALUE is valid, otherwise false. */
83 /* If MISA_READ is true then MISA_VALUE holds the value of the MISA
84 register read from the target. */
88 /* Key created when the RiscV per-inferior data is registered. */
90 static const struct inferior_data
*riscv_inferior_data_reg
;
92 /* Architectural name for core registers. */
94 static const char * const riscv_gdb_reg_names
[RISCV_LAST_FP_REGNUM
+ 1] =
96 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
97 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
98 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
99 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
101 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
102 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
103 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
104 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
107 /* Maps "pretty" register names onto their GDB register number. */
109 struct register_alias
111 /* The register alias. Usually more descriptive than the
112 architectural name of the register. */
115 /* The GDB register number. */
119 /* Table of register aliases. */
121 static const struct register_alias riscv_register_aliases
[] =
189 #define DECLARE_CSR(name, num) { #name, (num) + 65 },
190 #include "opcode/riscv-opc.h"
194 /* Controls whether we place compressed breakpoints or not. When in auto
195 mode GDB tries to determine if the target supports compressed
196 breakpoints, and uses them if it does. */
198 static enum auto_boolean use_compressed_breakpoints
;
200 /* The show callback for 'show riscv use-compressed-breakpoints'. */
203 show_use_compressed_breakpoints (struct ui_file
*file
, int from_tty
,
204 struct cmd_list_element
*c
,
207 const char *additional_info
;
208 struct gdbarch
*gdbarch
= target_gdbarch ();
210 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
211 if (riscv_has_feature (gdbarch
, 'C'))
212 additional_info
= _(" (currently on)");
214 additional_info
= _(" (currently off)");
216 additional_info
= "";
218 fprintf_filtered (file
,
219 _("Debugger's use of compressed breakpoints is set "
220 "to %s%s.\n"), value
, additional_info
);
223 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
225 static struct cmd_list_element
*setriscvcmdlist
= NULL
;
226 static struct cmd_list_element
*showriscvcmdlist
= NULL
;
228 /* The show callback for the 'show riscv' prefix command. */
231 show_riscv_command (const char *args
, int from_tty
)
233 help_list (showriscvcmdlist
, "show riscv ", all_commands
, gdb_stdout
);
236 /* The set callback for the 'set riscv' prefix command. */
239 set_riscv_command (const char *args
, int from_tty
)
242 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
243 help_list (setriscvcmdlist
, "set riscv ", all_commands
, gdb_stdout
);
246 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
248 static struct cmd_list_element
*setdebugriscvcmdlist
= NULL
;
249 static struct cmd_list_element
*showdebugriscvcmdlist
= NULL
;
251 /* The show callback for the 'show debug riscv' prefix command. */
254 show_debug_riscv_command (const char *args
, int from_tty
)
256 help_list (showdebugriscvcmdlist
, "show debug riscv ", all_commands
, gdb_stdout
);
259 /* The set callback for the 'set debug riscv' prefix command. */
262 set_debug_riscv_command (const char *args
, int from_tty
)
265 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
266 help_list (setdebugriscvcmdlist
, "set debug riscv ", all_commands
, gdb_stdout
);
269 /* The show callback for all 'show debug riscv VARNAME' variables. */
272 show_riscv_debug_variable (struct ui_file
*file
, int from_tty
,
273 struct cmd_list_element
*c
,
276 fprintf_filtered (file
,
277 _("RiscV debug variable `%s' is set to: %s\n"),
281 /* When this is set to non-zero debugging information about inferior calls
284 static unsigned int riscv_debug_infcall
= 0;
286 /* Read the MISA register from the target. The register will only be read
287 once, and the value read will be cached. If the register can't be read
288 from the target then a default value (0) will be returned. If the
289 pointer READ_P is not null, then the bool pointed to is updated to
290 indicate if the value returned was read from the target (true) or is the
294 riscv_read_misa_reg (bool *read_p
)
296 struct riscv_inferior_data
*inf_data
297 = riscv_inferior_data (current_inferior ());
299 if (!inf_data
->misa_read
&& target_has_registers
)
302 struct frame_info
*frame
= get_current_frame ();
306 value
= get_frame_register_unsigned (frame
, RISCV_CSR_MISA_REGNUM
);
308 CATCH (ex
, RETURN_MASK_ERROR
)
310 /* Old cores might have MISA located at a different offset. */
311 value
= get_frame_register_unsigned (frame
,
312 RISCV_CSR_LEGACY_MISA_REGNUM
);
316 inf_data
->misa_read
= true;
317 inf_data
->misa_value
= value
;
320 if (read_p
!= nullptr)
321 *read_p
= inf_data
->misa_read
;
323 return inf_data
->misa_value
;
326 /* Return true if FEATURE is available for the architecture GDBARCH. The
327 FEATURE should be one of the single character feature codes described in
328 the RiscV ISA manual, these are between 'A' and 'Z'. */
331 riscv_has_feature (struct gdbarch
*gdbarch
, char feature
)
333 bool have_read_misa
= false;
336 gdb_assert (feature
>= 'A' && feature
<= 'Z');
338 /* It would be nice to always check with the real target where possible,
339 however, for compressed instructions this is a bad idea.
341 The call to `set_gdbarch_decr_pc_after_break' is made just once per
342 GDBARCH and we decide at that point if we should decrement by 2 or 4
343 bytes based on whether the BFD has compressed instruction support or
346 If the BFD was not compiled with compressed instruction support, but we
347 are running on a target with compressed instructions then we might
348 place a 4-byte breakpoint, then decrement the $pc by 2 bytes leading to
351 It's safer if we just make decisions about compressed instruction
352 support based on the BFD. */
354 misa
= riscv_read_misa_reg (&have_read_misa
);
355 if (!have_read_misa
|| misa
== 0)
356 misa
= gdbarch_tdep (gdbarch
)->core_features
;
358 return (misa
& (1 << (feature
- 'A'))) != 0;
361 /* Return the width in bytes of the general purpose registers for GDBARCH.
362 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
366 riscv_isa_xlen (struct gdbarch
*gdbarch
)
368 switch (gdbarch_tdep (gdbarch
)->abi
.fields
.base_len
)
371 warning (_("unknown xlen size, assuming 4 bytes"));
381 /* Return the width in bytes of the floating point registers for GDBARCH.
382 If this architecture has no floating point registers, then return 0.
383 Possible values are 4, 8, or 16 for depending on which of single, double
384 or quad floating point support is available. */
387 riscv_isa_flen (struct gdbarch
*gdbarch
)
389 if (riscv_has_feature (gdbarch
, 'Q'))
391 else if (riscv_has_feature (gdbarch
, 'D'))
393 else if (riscv_has_feature (gdbarch
, 'F'))
399 /* Return true if the target for GDBARCH has floating point hardware. */
402 riscv_has_fp_regs (struct gdbarch
*gdbarch
)
404 return (riscv_isa_flen (gdbarch
) > 0);
407 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
410 riscv_has_fp_abi (struct gdbarch
*gdbarch
)
412 return (gdbarch_tdep (gdbarch
)->abi
.fields
.float_abi
!= 0);
415 /* Implement the breakpoint_kind_from_pc gdbarch method. */
418 riscv_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
420 if (use_compressed_breakpoints
== AUTO_BOOLEAN_AUTO
)
422 if (riscv_has_feature (gdbarch
, 'C'))
427 else if (use_compressed_breakpoints
== AUTO_BOOLEAN_TRUE
)
433 /* Implement the sw_breakpoint_from_kind gdbarch method. */
435 static const gdb_byte
*
436 riscv_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
438 static const gdb_byte ebreak
[] = { 0x73, 0x00, 0x10, 0x00, };
439 static const gdb_byte c_ebreak
[] = { 0x02, 0x90 };
449 gdb_assert_not_reached ("unhandled breakpoint kind");
453 /* Callback function for user_reg_add. */
455 static struct value
*
456 value_of_riscv_user_reg (struct frame_info
*frame
, const void *baton
)
458 const int *reg_p
= (const int *) baton
;
459 return value_of_register (*reg_p
, frame
);
462 /* Implement the register_name gdbarch method. */
465 riscv_register_name (struct gdbarch
*gdbarch
, int regnum
)
467 if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
468 return tdesc_register_name (gdbarch
, regnum
);
470 /* Prefer to use the alias. */
471 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_REGNUM
)
475 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
476 if (regnum
== riscv_register_aliases
[i
].regnum
)
477 return riscv_register_aliases
[i
].name
;
480 if (regnum
>= RISCV_ZERO_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
481 return riscv_gdb_reg_names
[regnum
];
483 if (regnum
>= RISCV_FIRST_CSR_REGNUM
&& regnum
<= RISCV_LAST_CSR_REGNUM
)
487 sprintf (buf
, "csr%d", regnum
- RISCV_FIRST_CSR_REGNUM
);
491 if (regnum
== RISCV_PRIV_REGNUM
)
497 /* Implement the register_type gdbarch method. */
500 riscv_register_type (struct gdbarch
*gdbarch
, int regnum
)
504 if (regnum
< RISCV_FIRST_FP_REGNUM
)
506 if (regnum
== gdbarch_pc_regnum (gdbarch
)
507 || regnum
== RISCV_RA_REGNUM
)
508 return builtin_type (gdbarch
)->builtin_func_ptr
;
510 if (regnum
== RISCV_FP_REGNUM
511 || regnum
== RISCV_SP_REGNUM
512 || regnum
== RISCV_GP_REGNUM
513 || regnum
== RISCV_TP_REGNUM
)
514 return builtin_type (gdbarch
)->builtin_data_ptr
;
516 /* Remaining GPRs vary in size based on the current ISA. */
517 regsize
= riscv_isa_xlen (gdbarch
);
521 return builtin_type (gdbarch
)->builtin_uint32
;
523 return builtin_type (gdbarch
)->builtin_uint64
;
525 return builtin_type (gdbarch
)->builtin_uint128
;
527 internal_error (__FILE__
, __LINE__
,
528 _("unknown isa regsize %i"), regsize
);
531 else if (regnum
<= RISCV_LAST_FP_REGNUM
)
533 regsize
= riscv_isa_xlen (gdbarch
);
537 return builtin_type (gdbarch
)->builtin_float
;
539 return builtin_type (gdbarch
)->builtin_double
;
541 return builtin_type (gdbarch
)->builtin_long_double
;
543 internal_error (__FILE__
, __LINE__
,
544 _("unknown isa regsize %i"), regsize
);
547 else if (regnum
== RISCV_PRIV_REGNUM
)
548 return builtin_type (gdbarch
)->builtin_int8
;
551 if (regnum
== RISCV_CSR_FFLAGS_REGNUM
552 || regnum
== RISCV_CSR_FRM_REGNUM
553 || regnum
== RISCV_CSR_FCSR_REGNUM
)
554 return builtin_type (gdbarch
)->builtin_int32
;
556 regsize
= riscv_isa_xlen (gdbarch
);
560 return builtin_type (gdbarch
)->builtin_int32
;
562 return builtin_type (gdbarch
)->builtin_int64
;
564 return builtin_type (gdbarch
)->builtin_int128
;
566 internal_error (__FILE__
, __LINE__
,
567 _("unknown isa regsize %i"), regsize
);
572 /* Helper for riscv_print_registers_info, prints info for a single register
576 riscv_print_one_register_info (struct gdbarch
*gdbarch
,
577 struct ui_file
*file
,
578 struct frame_info
*frame
,
581 const char *name
= gdbarch_register_name (gdbarch
, regnum
);
582 struct value
*val
= value_of_register (regnum
, frame
);
583 struct type
*regtype
= value_type (val
);
584 int print_raw_format
;
585 enum tab_stops
{ value_column_1
= 15 };
587 fputs_filtered (name
, file
);
588 print_spaces_filtered (value_column_1
- strlen (name
), file
);
590 print_raw_format
= (value_entirely_available (val
)
591 && !value_optimized_out (val
));
593 if (TYPE_CODE (regtype
) == TYPE_CODE_FLT
)
595 struct value_print_options opts
;
596 const gdb_byte
*valaddr
= value_contents_for_printing (val
);
597 enum bfd_endian byte_order
= gdbarch_byte_order (get_type_arch (regtype
));
599 get_user_print_options (&opts
);
603 value_embedded_offset (val
), 0,
604 file
, 0, val
, &opts
, current_language
);
606 if (print_raw_format
)
608 fprintf_filtered (file
, "\t(raw ");
609 print_hex_chars (file
, valaddr
, TYPE_LENGTH (regtype
), byte_order
,
611 fprintf_filtered (file
, ")");
616 struct value_print_options opts
;
618 /* Print the register in hex. */
619 get_formatted_print_options (&opts
, 'x');
622 value_embedded_offset (val
), 0,
623 file
, 0, val
, &opts
, current_language
);
625 if (print_raw_format
)
627 if (regnum
== RISCV_CSR_MSTATUS_REGNUM
)
630 int size
= register_size (gdbarch
, regnum
);
633 d
= value_as_long (val
);
635 fprintf_filtered (file
,
636 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
637 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
638 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
639 (int) ((d
>> (xlen
- 1)) & 0x1),
640 (int) ((d
>> 24) & 0x1f),
641 (int) ((d
>> 19) & 0x1),
642 (int) ((d
>> 18) & 0x1),
643 (int) ((d
>> 17) & 0x1),
644 (int) ((d
>> 15) & 0x3),
645 (int) ((d
>> 13) & 0x3),
646 (int) ((d
>> 11) & 0x3),
647 (int) ((d
>> 9) & 0x3),
648 (int) ((d
>> 8) & 0x1),
649 (int) ((d
>> 7) & 0x1),
650 (int) ((d
>> 6) & 0x1),
651 (int) ((d
>> 5) & 0x1),
652 (int) ((d
>> 4) & 0x1),
653 (int) ((d
>> 3) & 0x1),
654 (int) ((d
>> 2) & 0x1),
655 (int) ((d
>> 1) & 0x1),
656 (int) ((d
>> 0) & 0x1));
658 else if (regnum
== RISCV_CSR_MISA_REGNUM
)
664 d
= value_as_long (val
);
668 for (; base
> 0; base
--)
670 fprintf_filtered (file
, "\tRV%d", xlen
);
672 for (i
= 0; i
< 26; i
++)
675 fprintf_filtered (file
, "%c", 'A' + i
);
678 else if (regnum
== RISCV_CSR_FCSR_REGNUM
679 || regnum
== RISCV_CSR_FFLAGS_REGNUM
680 || regnum
== RISCV_CSR_FRM_REGNUM
)
684 d
= value_as_long (val
);
686 fprintf_filtered (file
, "\t");
687 if (regnum
!= RISCV_CSR_FRM_REGNUM
)
688 fprintf_filtered (file
,
689 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
690 (int) ((d
>> 5) & 0x7),
691 (int) ((d
>> 4) & 0x1),
692 (int) ((d
>> 3) & 0x1),
693 (int) ((d
>> 2) & 0x1),
694 (int) ((d
>> 1) & 0x1),
695 (int) ((d
>> 0) & 0x1));
697 if (regnum
!= RISCV_CSR_FFLAGS_REGNUM
)
699 static const char * const sfrm
[] =
701 "RNE (round to nearest; ties to even)",
702 "RTZ (Round towards zero)",
703 "RDN (Round down towards -INF)",
704 "RUP (Round up towards +INF)",
705 "RMM (Round to nearest; ties to max magnitude)",
708 "dynamic rounding mode",
710 int frm
= ((regnum
== RISCV_CSR_FCSR_REGNUM
)
711 ? (d
>> 5) : d
) & 0x3;
713 fprintf_filtered (file
, "%sFRM:%i [%s]",
714 (regnum
== RISCV_CSR_FCSR_REGNUM
719 else if (regnum
== RISCV_PRIV_REGNUM
)
724 d
= value_as_long (val
);
729 static const char * const sprv
[] =
736 fprintf_filtered (file
, "\tprv:%d [%s]",
740 fprintf_filtered (file
, "\tprv:%d [INVALID]", priv
);
744 /* If not a vector register, print it also according to its
746 if (TYPE_VECTOR (regtype
) == 0)
748 get_user_print_options (&opts
);
750 fprintf_filtered (file
, "\t");
752 value_embedded_offset (val
), 0,
753 file
, 0, val
, &opts
, current_language
);
758 fprintf_filtered (file
, "\n");
761 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
765 riscv_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
766 struct reggroup
*reggroup
)
772 /* Used by 'info registers' and 'info registers <groupname>'. */
774 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
775 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
778 if (reggroup
== all_reggroup
)
780 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
== RISCV_PRIV_REGNUM
)
782 /* Only include CSRs that have aliases. */
783 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
785 if (regnum
== riscv_register_aliases
[i
].regnum
)
790 else if (reggroup
== float_reggroup
)
791 return ((regnum
>= RISCV_FIRST_FP_REGNUM
&& regnum
<= RISCV_LAST_FP_REGNUM
)
792 || (regnum
== RISCV_CSR_FCSR_REGNUM
793 || regnum
== RISCV_CSR_FFLAGS_REGNUM
794 || regnum
== RISCV_CSR_FRM_REGNUM
));
795 else if (reggroup
== general_reggroup
)
796 return regnum
< RISCV_FIRST_FP_REGNUM
;
797 else if (reggroup
== restore_reggroup
|| reggroup
== save_reggroup
)
799 if (riscv_has_fp_regs (gdbarch
))
800 return regnum
<= RISCV_LAST_FP_REGNUM
;
802 return regnum
< RISCV_FIRST_FP_REGNUM
;
804 else if (reggroup
== system_reggroup
)
806 if (regnum
== RISCV_PRIV_REGNUM
)
808 if (regnum
< RISCV_FIRST_CSR_REGNUM
|| regnum
> RISCV_LAST_CSR_REGNUM
)
810 /* Only include CSRs that have aliases. */
811 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
813 if (regnum
== riscv_register_aliases
[i
].regnum
)
818 else if (reggroup
== vector_reggroup
)
824 /* Implement the print_registers_info gdbarch method. This is used by
825 'info registers' and 'info all-registers'. */
828 riscv_print_registers_info (struct gdbarch
*gdbarch
,
829 struct ui_file
*file
,
830 struct frame_info
*frame
,
831 int regnum
, int print_all
)
835 /* Print one specified register. */
836 gdb_assert (regnum
<= RISCV_LAST_REGNUM
);
837 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
838 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
839 error (_("Not a valid register for the current processor type"));
840 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
844 struct reggroup
*reggroup
;
847 reggroup
= all_reggroup
;
849 reggroup
= general_reggroup
;
851 for (regnum
= 0; regnum
<= RISCV_LAST_REGNUM
; ++regnum
)
853 /* Zero never changes, so might as well hide by default. */
854 if (regnum
== RISCV_ZERO_REGNUM
&& !print_all
)
857 /* Registers with no name are not valid on this ISA. */
858 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
859 || *(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
862 /* Is the register in the group we're interested in? */
863 if (!riscv_register_reggroup_p (gdbarch
, regnum
, reggroup
))
866 riscv_print_one_register_info (gdbarch
, file
, frame
, regnum
);
871 /* Class that handles one decoded RiscV instruction. */
877 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
880 /* Unknown value is used at initialisation time. */
883 /* These instructions are all the ones we are interested in during the
894 /* Other instructions are not interesting during the prologue scan, and
909 void decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
);
911 /* Get the length of the instruction in bytes. */
915 /* Get the opcode for this instruction. */
916 enum opcode
opcode () const
919 /* Get destination register field for this instruction. This is only
920 valid if the OPCODE implies there is such a field for this
925 /* Get the RS1 register field for this instruction. This is only valid
926 if the OPCODE implies there is such a field for this instruction. */
930 /* Get the RS2 register field for this instruction. This is only valid
931 if the OPCODE implies there is such a field for this instruction. */
935 /* Get the immediate for this instruction in signed form. This is only
936 valid if the OPCODE implies there is such a field for this
938 int imm_signed () const
943 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
944 int decode_register_index (unsigned long opcode
, int offset
)
946 return (opcode
>> offset
) & 0x1F;
949 /* Helper for DECODE, decode 32-bit R-type instruction. */
950 void decode_r_type_insn (enum opcode opcode
, ULONGEST ival
)
953 m_rd
= decode_register_index (ival
, OP_SH_RD
);
954 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
955 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
958 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
959 void decode_cr_type_insn (enum opcode opcode
, ULONGEST ival
)
962 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
963 m_rs2
= decode_register_index (ival
, OP_SH_CRS2
);
966 /* Helper for DECODE, decode 32-bit I-type instruction. */
967 void decode_i_type_insn (enum opcode opcode
, ULONGEST ival
)
970 m_rd
= decode_register_index (ival
, OP_SH_RD
);
971 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
972 m_imm
.s
= EXTRACT_ITYPE_IMM (ival
);
975 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
976 void decode_ci_type_insn (enum opcode opcode
, ULONGEST ival
)
979 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_CRS1S
);
980 m_imm
.s
= EXTRACT_RVC_IMM (ival
);
983 /* Helper for DECODE, decode 32-bit S-type instruction. */
984 void decode_s_type_insn (enum opcode opcode
, ULONGEST ival
)
987 m_rs1
= decode_register_index (ival
, OP_SH_RS1
);
988 m_rs2
= decode_register_index (ival
, OP_SH_RS2
);
989 m_imm
.s
= EXTRACT_STYPE_IMM (ival
);
992 /* Helper for DECODE, decode 32-bit U-type instruction. */
993 void decode_u_type_insn (enum opcode opcode
, ULONGEST ival
)
996 m_rd
= decode_register_index (ival
, OP_SH_RD
);
997 m_imm
.s
= EXTRACT_UTYPE_IMM (ival
);
1000 /* Fetch instruction from target memory at ADDR, return the content of
1001 the instruction, and update LEN with the instruction length. */
1002 static ULONGEST
fetch_instruction (struct gdbarch
*gdbarch
,
1003 CORE_ADDR addr
, int *len
);
1005 /* The length of the instruction in bytes. Should be 2 or 4. */
1008 /* The instruction opcode. */
1009 enum opcode m_opcode
;
1011 /* The three possible registers an instruction might reference. Not
1012 every instruction fills in all of these registers. Which fields are
1013 valid depends on the opcode. The naming of these fields matches the
1014 naming in the riscv isa manual. */
1019 /* Possible instruction immediate. This is only valid if the instruction
1020 format contains an immediate, not all instruction, whether this is
1021 valid depends on the opcode. Despite only having one format for now
1022 the immediate is packed into a union, later instructions might require
1023 an unsigned formatted immediate, having the union in place now will
1024 reduce the need for code churn later. */
1025 union riscv_insn_immediate
1027 riscv_insn_immediate ()
1037 /* Fetch instruction from target memory at ADDR, return the content of the
1038 instruction, and update LEN with the instruction length. */
1041 riscv_insn::fetch_instruction (struct gdbarch
*gdbarch
,
1042 CORE_ADDR addr
, int *len
)
1044 enum bfd_endian byte_order
= gdbarch_byte_order_for_code (gdbarch
);
1046 int instlen
, status
;
1048 /* All insns are at least 16 bits. */
1049 status
= target_read_memory (addr
, buf
, 2);
1051 memory_error (TARGET_XFER_E_IO
, addr
);
1053 /* If we need more, grab it now. */
1054 instlen
= riscv_insn_length (buf
[0]);
1056 if (instlen
> sizeof (buf
))
1057 internal_error (__FILE__
, __LINE__
,
1058 _("%s: riscv_insn_length returned %i"),
1060 else if (instlen
> 2)
1062 status
= target_read_memory (addr
+ 2, buf
+ 2, instlen
- 2);
1064 memory_error (TARGET_XFER_E_IO
, addr
+ 2);
1067 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1070 /* Fetch from target memory an instruction at PC and decode it. */
1073 riscv_insn::decode (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1077 /* Fetch the instruction, and the instructions length. */
1078 ival
= fetch_instruction (gdbarch
, pc
, &m_length
);
1082 if (is_add_insn (ival
))
1083 decode_r_type_insn (ADD
, ival
);
1084 else if (is_addw_insn (ival
))
1085 decode_r_type_insn (ADDW
, ival
);
1086 else if (is_addi_insn (ival
))
1087 decode_i_type_insn (ADDI
, ival
);
1088 else if (is_addiw_insn (ival
))
1089 decode_i_type_insn (ADDIW
, ival
);
1090 else if (is_auipc_insn (ival
))
1091 decode_u_type_insn (AUIPC
, ival
);
1092 else if (is_lui_insn (ival
))
1093 decode_u_type_insn (LUI
, ival
);
1094 else if (is_sd_insn (ival
))
1095 decode_s_type_insn (SD
, ival
);
1096 else if (is_sw_insn (ival
))
1097 decode_s_type_insn (SW
, ival
);
1099 /* None of the other fields are valid in this case. */
1102 else if (m_length
== 2)
1104 if (is_c_add_insn (ival
))
1105 decode_cr_type_insn (ADD
, ival
);
1106 else if (is_c_addw_insn (ival
))
1107 decode_cr_type_insn (ADDW
, ival
);
1108 else if (is_c_addi_insn (ival
))
1109 decode_ci_type_insn (ADDI
, ival
);
1110 else if (is_c_addiw_insn (ival
))
1111 decode_ci_type_insn (ADDIW
, ival
);
1112 else if (is_c_addi16sp_insn (ival
))
1115 m_rd
= m_rs1
= decode_register_index (ival
, OP_SH_RD
);
1116 m_imm
.s
= EXTRACT_RVC_ADDI16SP_IMM (ival
);
1118 else if (is_lui_insn (ival
))
1120 else if (is_c_sd_insn (ival
))
1122 else if (is_sw_insn (ival
))
1125 /* None of the other fields of INSN are valid in this case. */
1129 internal_error (__FILE__
, __LINE__
,
1130 _("unable to decode %d byte instructions in "
1131 "prologue at %s"), m_length
,
1132 core_addr_to_string (pc
));
1135 /* The prologue scanner. This is currently only used for skipping the
1136 prologue of a function when the DWARF information is not sufficient.
1137 However, it is written with filling of the frame cache in mind, which
1138 is why different groups of stack setup instructions are split apart
1139 during the core of the inner loop. In the future, the intention is to
1140 extend this function to fully support building up a frame cache that
1141 can unwind register values when there is no DWARF information. */
1144 riscv_scan_prologue (struct gdbarch
*gdbarch
,
1145 CORE_ADDR start_pc
, CORE_ADDR limit_pc
)
1147 CORE_ADDR cur_pc
, next_pc
;
1148 long frame_offset
= 0;
1149 CORE_ADDR end_prologue_addr
= 0;
1151 if (limit_pc
> start_pc
+ 200)
1152 limit_pc
= start_pc
+ 200;
1154 for (next_pc
= cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
= next_pc
)
1156 struct riscv_insn insn
;
1158 /* Decode the current instruction, and decide where the next
1159 instruction lives based on the size of this instruction. */
1160 insn
.decode (gdbarch
, cur_pc
);
1161 gdb_assert (insn
.length () > 0);
1162 next_pc
= cur_pc
+ insn
.length ();
1164 /* Look for common stack adjustment insns. */
1165 if ((insn
.opcode () == riscv_insn::ADDI
1166 || insn
.opcode () == riscv_insn::ADDIW
)
1167 && insn
.rd () == RISCV_SP_REGNUM
1168 && insn
.rs1 () == RISCV_SP_REGNUM
)
1170 /* Handle: addi sp, sp, -i
1171 or: addiw sp, sp, -i */
1172 if (insn
.imm_signed () < 0)
1173 frame_offset
+= insn
.imm_signed ();
1177 else if ((insn
.opcode () == riscv_insn::SW
1178 || insn
.opcode () == riscv_insn::SD
)
1179 && (insn
.rs1 () == RISCV_SP_REGNUM
1180 || insn
.rs1 () == RISCV_FP_REGNUM
))
1182 /* Handle: sw reg, offset(sp)
1183 or: sd reg, offset(sp)
1184 or: sw reg, offset(s0)
1185 or: sd reg, offset(s0) */
1186 /* Instruction storing a register onto the stack. */
1188 else if (insn
.opcode () == riscv_insn::ADDI
1189 && insn
.rd () == RISCV_FP_REGNUM
1190 && insn
.rs1 () == RISCV_SP_REGNUM
)
1192 /* Handle: addi s0, sp, size */
1193 /* Instructions setting up the frame pointer. */
1195 else if ((insn
.opcode () == riscv_insn::ADD
1196 || insn
.opcode () == riscv_insn::ADDW
)
1197 && insn
.rd () == RISCV_FP_REGNUM
1198 && insn
.rs1 () == RISCV_SP_REGNUM
1199 && insn
.rs2 () == RISCV_ZERO_REGNUM
)
1201 /* Handle: add s0, sp, 0
1202 or: addw s0, sp, 0 */
1203 /* Instructions setting up the frame pointer. */
1205 else if ((insn
.rd () == RISCV_GP_REGNUM
1206 && (insn
.opcode () == riscv_insn::AUIPC
1207 || insn
.opcode () == riscv_insn::LUI
1208 || (insn
.opcode () == riscv_insn::ADDI
1209 && insn
.rs1 () == RISCV_GP_REGNUM
)
1210 || (insn
.opcode () == riscv_insn::ADD
1211 && (insn
.rs1 () == RISCV_GP_REGNUM
1212 || insn
.rs2 () == RISCV_GP_REGNUM
))))
1213 || (insn
.opcode () == riscv_insn::ADDI
1214 && insn
.rd () == RISCV_ZERO_REGNUM
1215 && insn
.rs1 () == RISCV_ZERO_REGNUM
1216 && insn
.imm_signed () == 0))
1218 /* Handle: auipc gp, n
1223 or: add x0, x0, 0 (NOP) */
1224 /* These instructions are part of the prologue, but we don't need
1225 to do anything special to handle them. */
1229 if (end_prologue_addr
== 0)
1230 end_prologue_addr
= cur_pc
;
1234 if (end_prologue_addr
== 0)
1235 end_prologue_addr
= cur_pc
;
1237 return end_prologue_addr
;
1240 /* Implement the riscv_skip_prologue gdbarch method. */
1243 riscv_skip_prologue (struct gdbarch
*gdbarch
,
1247 CORE_ADDR func_addr
;
1249 /* See if we can determine the end of the prologue via the symbol
1250 table. If so, then return either PC, or the PC after the
1251 prologue, whichever is greater. */
1252 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1254 CORE_ADDR post_prologue_pc
1255 = skip_prologue_using_sal (gdbarch
, func_addr
);
1257 if (post_prologue_pc
!= 0)
1258 return std::max (pc
, post_prologue_pc
);
1261 /* Can't determine prologue from the symbol table, need to examine
1264 /* Find an upper limit on the function prologue using the debug
1265 information. If the debug information could not be used to provide
1266 that bound, then use an arbitrary large number as the upper bound. */
1267 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
1269 limit_pc
= pc
+ 100; /* MAGIC! */
1271 return riscv_scan_prologue (gdbarch
, pc
, limit_pc
);
1274 /* Implement the gdbarch push dummy code callback. */
1277 riscv_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
1278 CORE_ADDR funaddr
, struct value
**args
, int nargs
,
1279 struct type
*value_type
, CORE_ADDR
*real_pc
,
1280 CORE_ADDR
*bp_addr
, struct regcache
*regcache
)
1282 /* Allocate space for a breakpoint, and keep the stack correctly
1290 /* Compute the alignment of the type T. Used while setting up the
1291 arguments for a dummy call. */
1294 riscv_type_alignment (struct type
*t
)
1296 t
= check_typedef (t
);
1297 switch (TYPE_CODE (t
))
1300 error (_("Could not compute alignment of type"));
1302 case TYPE_CODE_RVALUE_REF
:
1304 case TYPE_CODE_ENUM
:
1308 case TYPE_CODE_CHAR
:
1309 case TYPE_CODE_BOOL
:
1310 return TYPE_LENGTH (t
);
1312 case TYPE_CODE_ARRAY
:
1313 case TYPE_CODE_COMPLEX
:
1314 return riscv_type_alignment (TYPE_TARGET_TYPE (t
));
1316 case TYPE_CODE_STRUCT
:
1317 case TYPE_CODE_UNION
:
1322 for (i
= 0; i
< TYPE_NFIELDS (t
); ++i
)
1324 if (TYPE_FIELD_LOC_KIND (t
, i
) == FIELD_LOC_KIND_BITPOS
)
1326 int a
= riscv_type_alignment (TYPE_FIELD_TYPE (t
, i
));
1336 /* Holds information about a single argument either being passed to an
1337 inferior function, or returned from an inferior function. This includes
1338 information about the size, type, etc of the argument, and also
1339 information about how the argument will be passed (or returned). */
1341 struct riscv_arg_info
1343 /* Contents of the argument. */
1344 const gdb_byte
*contents
;
1346 /* Length of argument. */
1349 /* Alignment required for an argument of this type. */
1352 /* The type for this argument. */
1355 /* Each argument can have either 1 or 2 locations assigned to it. Each
1356 location describes where part of the argument will be placed. The
1357 second location is valid based on the LOC_TYPE and C_LENGTH fields
1358 of the first location (which is always valid). */
1361 /* What type of location this is. */
1364 /* Argument passed in a register. */
1367 /* Argument passed as an on stack argument. */
1370 /* Argument passed by reference. The second location is always
1371 valid for a BY_REF argument, and describes where the address
1372 of the BY_REF argument should be placed. */
1376 /* Information that depends on the location type. */
1379 /* Which register number to use. */
1382 /* The offset into the stack region. */
1386 /* The length of contents covered by this location. If this is less
1387 than the total length of the argument, then the second location
1388 will be valid, and will describe where the rest of the argument
1392 /* The offset within CONTENTS for this part of the argument. Will
1393 always be 0 for the first part. For the second part of the
1394 argument, this might be the C_LENGTH value of the first part,
1395 however, if we are passing a structure in two registers, and there's
1396 is padding between the first and second field, then this offset
1397 might be greater than the length of the first argument part. When
1398 the second argument location is not holding part of the argument
1399 value, but is instead holding the address of a reference argument,
1400 then this offset will be set to 0. */
1405 /* Information about a set of registers being used for passing arguments as
1406 part of a function call. The register set must be numerically
1407 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1408 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1410 struct riscv_arg_reg
1412 riscv_arg_reg (int first
, int last
)
1413 : next_regnum (first
),
1419 /* The GDB register number to use in this set. */
1422 /* The last GDB register number to use in this set. */
1426 /* Arguments can be passed as on stack arguments, or by reference. The
1427 on stack arguments must be in a continuous region starting from $sp,
1428 while the by reference arguments can be anywhere, but we'll put them
1429 on the stack after (at higher address) the on stack arguments.
1431 This might not be the right approach to take. The ABI is clear that
1432 an argument passed by reference can be modified by the callee, which
1433 us placing the argument (temporarily) onto the stack will not achieve
1434 (changes will be lost). There's also the possibility that very large
1435 arguments could overflow the stack.
1437 This struct is used to track offset into these two areas for where
1438 arguments are to be placed. */
1439 struct riscv_memory_offsets
1441 riscv_memory_offsets ()
1448 /* Offset into on stack argument area. */
1451 /* Offset into the pass by reference area. */
1455 /* Holds information about where arguments to a call will be placed. This
1456 is updated as arguments are added onto the call, and can be used to
1457 figure out where the next argument should be placed. */
1459 struct riscv_call_info
1461 riscv_call_info (struct gdbarch
*gdbarch
)
1462 : int_regs (RISCV_A0_REGNUM
, RISCV_A0_REGNUM
+ 7),
1463 float_regs (RISCV_FA0_REGNUM
, RISCV_FA0_REGNUM
+ 7)
1465 xlen
= riscv_isa_xlen (gdbarch
);
1466 flen
= riscv_isa_flen (gdbarch
);
1468 /* Disable use of floating point registers if needed. */
1469 if (!riscv_has_fp_abi (gdbarch
))
1470 float_regs
.next_regnum
= float_regs
.last_regnum
+ 1;
1473 /* Track the memory areas used for holding in-memory arguments to a
1475 struct riscv_memory_offsets memory
;
1477 /* Holds information about the next integer register to use for passing
1479 struct riscv_arg_reg int_regs
;
1481 /* Holds information about the next floating point register to use for
1482 passing an argument. */
1483 struct riscv_arg_reg float_regs
;
1485 /* The XLEN and FLEN are copied in to this structure for convenience, and
1486 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1491 /* Return the number of registers available for use as parameters in the
1492 register set REG. Returned value can be 0 or more. */
1495 riscv_arg_regs_available (struct riscv_arg_reg
*reg
)
1497 if (reg
->next_regnum
> reg
->last_regnum
)
1500 return (reg
->last_regnum
- reg
->next_regnum
+ 1);
1503 /* If there is at least one register available in the register set REG then
1504 the next register from REG is assigned to LOC and the length field of
1505 LOC is updated to LENGTH. The register set REG is updated to indicate
1506 that the assigned register is no longer available and the function
1509 If there are no registers available in REG then the function returns
1510 false, and LOC and REG are unchanged. */
1513 riscv_assign_reg_location (struct riscv_arg_info::location
*loc
,
1514 struct riscv_arg_reg
*reg
,
1515 int length
, int offset
)
1517 if (reg
->next_regnum
<= reg
->last_regnum
)
1519 loc
->loc_type
= riscv_arg_info::location::in_reg
;
1520 loc
->loc_data
.regno
= reg
->next_regnum
;
1522 loc
->c_length
= length
;
1523 loc
->c_offset
= offset
;
1530 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1531 record that an area of stack has been used to hold the parameter
1534 The length field of LOC is updated to LENGTH, the length of the
1535 parameter being stored, and ALIGN is the alignment required by the
1536 parameter, which will affect how memory is allocated out of MEMORY. */
1539 riscv_assign_stack_location (struct riscv_arg_info::location
*loc
,
1540 struct riscv_memory_offsets
*memory
,
1541 int length
, int align
)
1543 loc
->loc_type
= riscv_arg_info::location::on_stack
;
1545 = align_up (memory
->arg_offset
, align
);
1546 loc
->loc_data
.offset
= memory
->arg_offset
;
1547 memory
->arg_offset
+= length
;
1548 loc
->c_length
= length
;
1550 /* Offset is always 0, either we're the first location part, in which
1551 case we're reading content from the start of the argument, or we're
1552 passing the address of a reference argument, so 0. */
1556 /* Update AINFO, which describes an argument that should be passed or
1557 returned using the integer ABI. The argloc fields within AINFO are
1558 updated to describe the location in which the argument will be passed to
1559 a function, or returned from a function.
1561 The CINFO structure contains the ongoing call information, the holds
1562 information such as which argument registers are remaining to be
1563 assigned to parameter, and how much memory has been used by parameters
1566 By examining the state of CINFO a suitable location can be selected,
1567 and assigned to AINFO. */
1570 riscv_call_arg_scalar_int (struct riscv_arg_info
*ainfo
,
1571 struct riscv_call_info
*cinfo
)
1573 if (ainfo
->length
> (2 * cinfo
->xlen
))
1575 /* Argument is going to be passed by reference. */
1576 ainfo
->argloc
[0].loc_type
1577 = riscv_arg_info::location::by_ref
;
1578 cinfo
->memory
.ref_offset
1579 = align_up (cinfo
->memory
.ref_offset
, ainfo
->align
);
1580 ainfo
->argloc
[0].loc_data
.offset
= cinfo
->memory
.ref_offset
;
1581 cinfo
->memory
.ref_offset
+= ainfo
->length
;
1582 ainfo
->argloc
[0].c_length
= ainfo
->length
;
1584 /* The second location for this argument is given over to holding the
1585 address of the by-reference data. Pass 0 for the offset as this
1586 is not part of the actual argument value. */
1587 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1590 riscv_assign_stack_location (&ainfo
->argloc
[1],
1591 &cinfo
->memory
, cinfo
->xlen
,
1596 int len
= (ainfo
->length
> cinfo
->xlen
) ? cinfo
->xlen
: ainfo
->length
;
1598 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1599 &cinfo
->int_regs
, len
, 0))
1600 riscv_assign_stack_location (&ainfo
->argloc
[0],
1601 &cinfo
->memory
, len
, ainfo
->align
);
1603 if (len
< ainfo
->length
)
1605 len
= ainfo
->length
- len
;
1606 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1607 &cinfo
->int_regs
, len
,
1609 riscv_assign_stack_location (&ainfo
->argloc
[1],
1610 &cinfo
->memory
, len
, cinfo
->xlen
);
1615 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1616 is being passed with the floating point ABI. */
1619 riscv_call_arg_scalar_float (struct riscv_arg_info
*ainfo
,
1620 struct riscv_call_info
*cinfo
)
1622 if (ainfo
->length
> cinfo
->flen
)
1623 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1626 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1629 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1633 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1634 is a complex floating point argument, and is therefore handled
1635 differently to other argument types. */
1638 riscv_call_arg_complex_float (struct riscv_arg_info
*ainfo
,
1639 struct riscv_call_info
*cinfo
)
1641 if (ainfo
->length
<= (2 * cinfo
->flen
)
1642 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1645 int len
= ainfo
->length
/ 2;
1647 result
= riscv_assign_reg_location (&ainfo
->argloc
[0],
1648 &cinfo
->float_regs
, len
, len
);
1649 gdb_assert (result
);
1651 result
= riscv_assign_reg_location (&ainfo
->argloc
[1],
1652 &cinfo
->float_regs
, len
, len
);
1653 gdb_assert (result
);
1656 return riscv_call_arg_scalar_int (ainfo
, cinfo
);
1659 /* A structure used for holding information about a structure type within
1660 the inferior program. The RiscV ABI has special rules for handling some
1661 structures with a single field or with two fields. The counting of
1662 fields here is done after flattening out all nested structures. */
1664 class riscv_struct_info
1667 riscv_struct_info ()
1668 : m_number_of_fields (0),
1669 m_types
{ nullptr, nullptr }
1674 /* Analyse TYPE descending into nested structures, count the number of
1675 scalar fields and record the types of the first two fields found. */
1676 void analyse (struct type
*type
);
1678 /* The number of scalar fields found in the analysed type. This is
1679 currently only accurate if the value returned is 0, 1, or 2 as the
1680 analysis stops counting when the number of fields is 3. This is
1681 because the RiscV ABI only has special cases for 1 or 2 fields,
1682 anything else we just don't care about. */
1683 int number_of_fields () const
1684 { return m_number_of_fields
; }
1686 /* Return the type for scalar field INDEX within the analysed type. Will
1687 return nullptr if there is no field at that index. Only INDEX values
1688 0 and 1 can be requested as the RiscV ABI only has special cases for
1689 structures with 1 or 2 fields. */
1690 struct type
*field_type (int index
) const
1692 gdb_assert (index
< (sizeof (m_types
) / sizeof (m_types
[0])));
1693 return m_types
[index
];
1697 /* The number of scalar fields found within the structure after recursing
1698 into nested structures. */
1699 int m_number_of_fields
;
1701 /* The types of the first two scalar fields found within the structure
1702 after recursing into nested structures. */
1703 struct type
*m_types
[2];
1706 /* Analyse TYPE descending into nested structures, count the number of
1707 scalar fields and record the types of the first two fields found. */
1710 riscv_struct_info::analyse (struct type
*type
)
1712 unsigned int count
= TYPE_NFIELDS (type
);
1715 for (i
= 0; i
< count
; ++i
)
1717 if (TYPE_FIELD_LOC_KIND (type
, i
) != FIELD_LOC_KIND_BITPOS
)
1720 struct type
*field_type
= TYPE_FIELD_TYPE (type
, i
);
1721 field_type
= check_typedef (field_type
);
1723 switch (TYPE_CODE (field_type
))
1725 case TYPE_CODE_STRUCT
:
1726 analyse (field_type
);
1730 /* RiscV only flattens out structures. Anything else does not
1731 need to be flattened, we just record the type, and when we
1732 look at the analysis results we'll realise this is not a
1733 structure we can special case, and pass the structure in
1735 if (m_number_of_fields
< 2)
1736 m_types
[m_number_of_fields
] = field_type
;
1737 m_number_of_fields
++;
1741 /* RiscV only has special handling for structures with 1 or 2 scalar
1742 fields, any more than that and the structure is just passed in
1743 memory. We can safely drop out early when we find 3 or more
1746 if (m_number_of_fields
> 2)
1751 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1752 is a structure. Small structures on RiscV have some special case
1753 handling in order that the structure might be passed in register.
1754 Larger structures are passed in memory. After assigning location
1755 information to AINFO, CINFO will have been updated. */
1758 riscv_call_arg_struct (struct riscv_arg_info
*ainfo
,
1759 struct riscv_call_info
*cinfo
)
1761 if (riscv_arg_regs_available (&cinfo
->float_regs
) >= 1)
1763 struct riscv_struct_info sinfo
;
1765 sinfo
.analyse (ainfo
->type
);
1766 if (sinfo
.number_of_fields () == 1
1767 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_COMPLEX
)
1769 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1770 == TYPE_LENGTH (sinfo
.field_type (0)));
1771 return riscv_call_arg_complex_float (ainfo
, cinfo
);
1774 if (sinfo
.number_of_fields () == 1
1775 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
)
1777 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1778 == TYPE_LENGTH (sinfo
.field_type (0)));
1779 return riscv_call_arg_scalar_float (ainfo
, cinfo
);
1782 if (sinfo
.number_of_fields () == 2
1783 && TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1784 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1785 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1786 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
1787 && riscv_arg_regs_available (&cinfo
->float_regs
) >= 2)
1789 int len0
, len1
, offset
;
1791 gdb_assert (TYPE_LENGTH (ainfo
->type
) <= (2 * cinfo
->flen
));
1793 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1794 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1795 &cinfo
->float_regs
, len0
, 0))
1796 error (_("failed during argument setup"));
1798 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1799 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1800 gdb_assert (len1
<= (TYPE_LENGTH (ainfo
->type
)
1801 - TYPE_LENGTH (sinfo
.field_type (0))));
1803 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1806 error (_("failed during argument setup"));
1810 if (sinfo
.number_of_fields () == 2
1811 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1812 && (TYPE_CODE (sinfo
.field_type (0)) == TYPE_CODE_FLT
1813 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->flen
1814 && is_integral_type (sinfo
.field_type (1))
1815 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->xlen
))
1817 int len0
, len1
, offset
;
1819 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1820 <= (cinfo
->flen
+ cinfo
->xlen
));
1822 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1823 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1824 &cinfo
->float_regs
, len0
, 0))
1825 error (_("failed during argument setup"));
1827 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1828 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1829 gdb_assert (len1
<= cinfo
->xlen
);
1830 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1831 &cinfo
->int_regs
, len1
, offset
))
1832 error (_("failed during argument setup"));
1836 if (sinfo
.number_of_fields () == 2
1837 && riscv_arg_regs_available (&cinfo
->int_regs
) >= 1
1838 && (is_integral_type (sinfo
.field_type (0))
1839 && TYPE_LENGTH (sinfo
.field_type (0)) <= cinfo
->xlen
1840 && TYPE_CODE (sinfo
.field_type (1)) == TYPE_CODE_FLT
1841 && TYPE_LENGTH (sinfo
.field_type (1)) <= cinfo
->flen
))
1843 int len0
, len1
, offset
;
1845 gdb_assert (TYPE_LENGTH (ainfo
->type
)
1846 <= (cinfo
->flen
+ cinfo
->xlen
));
1848 len0
= TYPE_LENGTH (sinfo
.field_type (0));
1849 len1
= TYPE_LENGTH (sinfo
.field_type (1));
1850 offset
= align_up (len0
, riscv_type_alignment (sinfo
.field_type (1)));
1852 gdb_assert (len0
<= cinfo
->xlen
);
1853 gdb_assert (len1
<= cinfo
->flen
);
1855 if (!riscv_assign_reg_location (&ainfo
->argloc
[0],
1856 &cinfo
->int_regs
, len0
, 0))
1857 error (_("failed during argument setup"));
1859 if (!riscv_assign_reg_location (&ainfo
->argloc
[1],
1862 error (_("failed during argument setup"));
1868 /* Non of the structure flattening cases apply, so we just pass using
1870 ainfo
->length
= align_up (ainfo
->length
, cinfo
->xlen
);
1871 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1874 /* Assign a location to call (or return) argument AINFO, the location is
1875 selected from CINFO which holds information about what call argument
1876 locations are available for use next. The TYPE is the type of the
1877 argument being passed, this information is recorded into AINFO (along
1878 with some additional information derived from the type).
1880 After assigning a location to AINFO, CINFO will have been updated. */
1883 riscv_arg_location (struct gdbarch
*gdbarch
,
1884 struct riscv_arg_info
*ainfo
,
1885 struct riscv_call_info
*cinfo
,
1889 ainfo
->length
= TYPE_LENGTH (ainfo
->type
);
1890 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1891 ainfo
->contents
= nullptr;
1893 switch (TYPE_CODE (ainfo
->type
))
1896 case TYPE_CODE_BOOL
:
1897 case TYPE_CODE_CHAR
:
1898 case TYPE_CODE_RANGE
:
1899 case TYPE_CODE_ENUM
:
1901 if (ainfo
->length
<= cinfo
->xlen
)
1903 ainfo
->type
= builtin_type (gdbarch
)->builtin_long
;
1904 ainfo
->length
= cinfo
->xlen
;
1906 else if (ainfo
->length
<= (2 * cinfo
->xlen
))
1908 ainfo
->type
= builtin_type (gdbarch
)->builtin_long_long
;
1909 ainfo
->length
= 2 * cinfo
->xlen
;
1912 /* Recalculate the alignment requirement. */
1913 ainfo
->align
= riscv_type_alignment (ainfo
->type
);
1914 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1918 riscv_call_arg_scalar_float (ainfo
, cinfo
);
1921 case TYPE_CODE_COMPLEX
:
1922 riscv_call_arg_complex_float (ainfo
, cinfo
);
1925 case TYPE_CODE_STRUCT
:
1926 riscv_call_arg_struct (ainfo
, cinfo
);
1930 riscv_call_arg_scalar_int (ainfo
, cinfo
);
1935 /* Used for printing debug information about the call argument location in
1936 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
1937 addresses for the location of pass-by-reference and
1938 arguments-on-the-stack memory areas. */
1941 riscv_print_arg_location (ui_file
*stream
, struct gdbarch
*gdbarch
,
1942 struct riscv_arg_info
*info
,
1943 CORE_ADDR sp_refs
, CORE_ADDR sp_args
)
1945 const char* type_name
= TYPE_NAME (info
->type
);
1946 if (type_name
== nullptr)
1949 fprintf_unfiltered (stream
, "type: '%s', length: 0x%x, alignment: 0x%x",
1950 type_name
, info
->length
, info
->align
);
1951 switch (info
->argloc
[0].loc_type
)
1953 case riscv_arg_info::location::in_reg
:
1955 (stream
, ", register %s",
1956 gdbarch_register_name (gdbarch
, info
->argloc
[0].loc_data
.regno
));
1957 if (info
->argloc
[0].c_length
< info
->length
)
1959 switch (info
->argloc
[1].loc_type
)
1961 case riscv_arg_info::location::in_reg
:
1963 (stream
, ", register %s",
1964 gdbarch_register_name (gdbarch
,
1965 info
->argloc
[1].loc_data
.regno
));
1968 case riscv_arg_info::location::on_stack
:
1969 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
1970 info
->argloc
[1].loc_data
.offset
);
1973 case riscv_arg_info::location::by_ref
:
1975 /* The second location should never be a reference, any
1976 argument being passed by reference just places its address
1977 in the first location and is done. */
1978 error (_("invalid argument location"));
1982 if (info
->argloc
[1].c_offset
> info
->argloc
[0].c_length
)
1983 fprintf_unfiltered (stream
, " (offset 0x%x)",
1984 info
->argloc
[1].c_offset
);
1988 case riscv_arg_info::location::on_stack
:
1989 fprintf_unfiltered (stream
, ", on stack at offset 0x%x",
1990 info
->argloc
[0].loc_data
.offset
);
1993 case riscv_arg_info::location::by_ref
:
1995 (stream
, ", by reference, data at offset 0x%x (%s)",
1996 info
->argloc
[0].loc_data
.offset
,
1997 core_addr_to_string (sp_refs
+ info
->argloc
[0].loc_data
.offset
));
1998 if (info
->argloc
[1].loc_type
1999 == riscv_arg_info::location::in_reg
)
2001 (stream
, ", address in register %s",
2002 gdbarch_register_name (gdbarch
, info
->argloc
[1].loc_data
.regno
));
2005 gdb_assert (info
->argloc
[1].loc_type
2006 == riscv_arg_info::location::on_stack
);
2008 (stream
, ", address on stack at offset 0x%x (%s)",
2009 info
->argloc
[1].loc_data
.offset
,
2010 core_addr_to_string (sp_args
+ info
->argloc
[1].loc_data
.offset
));
2015 error ("unknown argument location type");
2019 /* Implement the push dummy call gdbarch callback. */
2022 riscv_push_dummy_call (struct gdbarch
*gdbarch
,
2023 struct value
*function
,
2024 struct regcache
*regcache
,
2027 struct value
**args
,
2030 CORE_ADDR struct_addr
)
2033 CORE_ADDR sp_args
, sp_refs
;
2034 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2035 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2037 struct riscv_arg_info
*arg_info
=
2038 (struct riscv_arg_info
*) alloca (nargs
* sizeof (struct riscv_arg_info
));
2039 struct riscv_arg_info
*info
;
2041 struct riscv_call_info
call_info (gdbarch
);
2045 /* We'll use register $a0 if we're returning a struct. */
2047 ++call_info
.int_regs
.next_regnum
;
2049 for (i
= 0, info
= &arg_info
[0];
2053 struct value
*arg_value
;
2054 struct type
*arg_type
;
2056 arg_value
= args
[i
];
2057 arg_type
= check_typedef (value_type (arg_value
));
2059 riscv_arg_location (gdbarch
, info
, &call_info
, arg_type
);
2061 if (info
->type
!= arg_type
)
2062 arg_value
= value_cast (info
->type
, arg_value
);
2063 info
->contents
= value_contents (arg_value
);
2066 /* Adjust the stack pointer and align it. */
2067 sp
= sp_refs
= align_down (sp
- call_info
.memory
.ref_offset
, SP_ALIGNMENT
);
2068 sp
= sp_args
= align_down (sp
- call_info
.memory
.arg_offset
, SP_ALIGNMENT
);
2070 if (riscv_debug_infcall
> 0)
2072 fprintf_unfiltered (gdb_stdlog
, "dummy call args:\n");
2073 fprintf_unfiltered (gdb_stdlog
, ": floating point ABI %s in use\n",
2074 (riscv_has_fp_abi (gdbarch
) ? "is" : "is not"));
2075 fprintf_unfiltered (gdb_stdlog
, ": xlen: %d\n: flen: %d\n",
2076 call_info
.xlen
, call_info
.flen
);
2078 fprintf_unfiltered (gdb_stdlog
,
2079 "[*] struct return pointer in register $A0\n");
2080 for (i
= 0; i
< nargs
; ++i
)
2082 struct riscv_arg_info
*info
= &arg_info
[i
];
2084 fprintf_unfiltered (gdb_stdlog
, "[%2d] ", i
);
2085 riscv_print_arg_location (gdb_stdlog
, gdbarch
, info
, sp_refs
, sp_args
);
2086 fprintf_unfiltered (gdb_stdlog
, "\n");
2088 if (call_info
.memory
.arg_offset
> 0
2089 || call_info
.memory
.ref_offset
> 0)
2091 fprintf_unfiltered (gdb_stdlog
, " Original sp: %s\n",
2092 core_addr_to_string (osp
));
2093 fprintf_unfiltered (gdb_stdlog
, "Stack required (for args): 0x%x\n",
2094 call_info
.memory
.arg_offset
);
2095 fprintf_unfiltered (gdb_stdlog
, "Stack required (for refs): 0x%x\n",
2096 call_info
.memory
.ref_offset
);
2097 fprintf_unfiltered (gdb_stdlog
, " Stack allocated: %s\n",
2098 core_addr_to_string_nz (osp
- sp
));
2102 /* Now load the argument into registers, or onto the stack. */
2106 gdb_byte buf
[sizeof (LONGEST
)];
2108 store_unsigned_integer (buf
, call_info
.xlen
, byte_order
, struct_addr
);
2109 regcache_cooked_write (regcache
, RISCV_A0_REGNUM
, buf
);
2112 for (i
= 0; i
< nargs
; ++i
)
2115 int second_arg_length
= 0;
2116 const gdb_byte
*second_arg_data
;
2117 struct riscv_arg_info
*info
= &arg_info
[i
];
2119 gdb_assert (info
->length
> 0);
2121 switch (info
->argloc
[0].loc_type
)
2123 case riscv_arg_info::location::in_reg
:
2125 gdb_byte tmp
[sizeof (ULONGEST
)];
2127 gdb_assert (info
->argloc
[0].c_length
<= info
->length
);
2128 memset (tmp
, 0, sizeof (tmp
));
2129 memcpy (tmp
, info
->contents
, info
->argloc
[0].c_length
);
2130 regcache_cooked_write (regcache
,
2131 info
->argloc
[0].loc_data
.regno
,
2134 ((info
->argloc
[0].c_length
< info
->length
)
2135 ? info
->argloc
[1].c_length
: 0);
2136 second_arg_data
= info
->contents
+ info
->argloc
[1].c_offset
;
2140 case riscv_arg_info::location::on_stack
:
2141 dst
= sp_args
+ info
->argloc
[0].loc_data
.offset
;
2142 write_memory (dst
, info
->contents
, info
->length
);
2143 second_arg_length
= 0;
2146 case riscv_arg_info::location::by_ref
:
2147 dst
= sp_refs
+ info
->argloc
[0].loc_data
.offset
;
2148 write_memory (dst
, info
->contents
, info
->length
);
2150 second_arg_length
= call_info
.xlen
;
2151 second_arg_data
= (gdb_byte
*) &dst
;
2155 error ("unknown argument location type");
2158 if (second_arg_length
> 0)
2160 switch (info
->argloc
[1].loc_type
)
2162 case riscv_arg_info::location::in_reg
:
2164 gdb_byte tmp
[sizeof (ULONGEST
)];
2166 gdb_assert (second_arg_length
<= call_info
.xlen
);
2167 memset (tmp
, 0, sizeof (tmp
));
2168 memcpy (tmp
, second_arg_data
, second_arg_length
);
2169 regcache_cooked_write (regcache
,
2170 info
->argloc
[1].loc_data
.regno
,
2175 case riscv_arg_info::location::on_stack
:
2179 arg_addr
= sp_args
+ info
->argloc
[1].loc_data
.offset
;
2180 write_memory (arg_addr
, second_arg_data
, second_arg_length
);
2184 case riscv_arg_info::location::by_ref
:
2186 /* The second location should never be a reference, any
2187 argument being passed by reference just places its address
2188 in the first location and is done. */
2189 error (_("invalid argument location"));
2195 /* Set the dummy return value to bp_addr.
2196 A dummy breakpoint will be setup to execute the call. */
2198 if (riscv_debug_infcall
> 0)
2199 fprintf_unfiltered (gdb_stdlog
, ": writing $ra = %s\n",
2200 core_addr_to_string (bp_addr
));
2201 regcache_cooked_write_unsigned (regcache
, RISCV_RA_REGNUM
, bp_addr
);
2203 /* Finally, update the stack pointer. */
2205 if (riscv_debug_infcall
> 0)
2206 fprintf_unfiltered (gdb_stdlog
, ": writing $sp = %s\n",
2207 core_addr_to_string (sp
));
2208 regcache_cooked_write_unsigned (regcache
, RISCV_SP_REGNUM
, sp
);
2213 /* Implement the return_value gdbarch method. */
2215 static enum return_value_convention
2216 riscv_return_value (struct gdbarch
*gdbarch
,
2217 struct value
*function
,
2219 struct regcache
*regcache
,
2221 const gdb_byte
*writebuf
)
2223 enum type_code rv_type
= TYPE_CODE (type
);
2224 unsigned int rv_size
= TYPE_LENGTH (type
);
2225 int fp
, regnum
, flen
;
2227 struct riscv_call_info
call_info (gdbarch
);
2228 struct riscv_arg_info info
;
2229 struct type
*arg_type
;
2231 arg_type
= check_typedef (type
);
2232 riscv_arg_location (gdbarch
, &info
, &call_info
, arg_type
);
2234 if (riscv_debug_infcall
> 0)
2236 fprintf_unfiltered (gdb_stdlog
, "riscv return value:\n");
2237 fprintf_unfiltered (gdb_stdlog
, "[R] ");
2238 riscv_print_arg_location (gdb_stdlog
, gdbarch
, &info
, 0, 0);
2239 fprintf_unfiltered (gdb_stdlog
, "\n");
2242 if (readbuf
!= nullptr || writebuf
!= nullptr)
2246 switch (info
.argloc
[0].loc_type
)
2248 /* Return value in register(s). */
2249 case riscv_arg_info::location::in_reg
:
2251 regnum
= info
.argloc
[0].loc_data
.regno
;
2254 regcache_cooked_read (regcache
, regnum
, readbuf
);
2257 regcache_cooked_write (regcache
, regnum
, writebuf
);
2259 /* A return value in register can have a second part in a
2261 if (info
.argloc
[0].c_length
< info
.length
)
2263 switch (info
.argloc
[1].loc_type
)
2265 case riscv_arg_info::location::in_reg
:
2266 regnum
= info
.argloc
[1].loc_data
.regno
;
2270 readbuf
+= info
.argloc
[1].c_offset
;
2271 regcache_cooked_read (regcache
, regnum
, readbuf
);
2276 writebuf
+= info
.argloc
[1].c_offset
;
2277 regcache_cooked_write (regcache
, regnum
, writebuf
);
2281 case riscv_arg_info::location::by_ref
:
2282 case riscv_arg_info::location::on_stack
:
2284 error (_("invalid argument location"));
2291 /* Return value by reference will have its address in A0. */
2292 case riscv_arg_info::location::by_ref
:
2296 regcache_cooked_read_unsigned (regcache
, RISCV_A0_REGNUM
,
2298 if (readbuf
!= nullptr)
2299 read_memory (addr
, readbuf
, info
.length
);
2300 if (writebuf
!= nullptr)
2301 write_memory (addr
, writebuf
, info
.length
);
2305 case riscv_arg_info::location::on_stack
:
2307 error (_("invalid argument location"));
2312 switch (info
.argloc
[0].loc_type
)
2314 case riscv_arg_info::location::in_reg
:
2315 return RETURN_VALUE_REGISTER_CONVENTION
;
2316 case riscv_arg_info::location::by_ref
:
2317 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
2318 case riscv_arg_info::location::on_stack
:
2320 error (_("invalid argument location"));
2324 /* Implement the frame_align gdbarch method. */
2327 riscv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2329 return align_down (addr
, 16);
2332 /* Implement the unwind_pc gdbarch method. */
2335 riscv_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2337 return frame_unwind_register_unsigned (next_frame
, RISCV_PC_REGNUM
);
2340 /* Implement the unwind_sp gdbarch method. */
2343 riscv_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2345 return frame_unwind_register_unsigned (next_frame
, RISCV_SP_REGNUM
);
2348 /* Implement the dummy_id gdbarch method. */
2350 static struct frame_id
2351 riscv_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2353 return frame_id_build (get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
),
2354 get_frame_pc (this_frame
));
2357 /* Generate, or return the cached frame cache for the RiscV frame
2360 static struct trad_frame_cache
*
2361 riscv_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2364 CORE_ADDR start_addr
;
2365 CORE_ADDR stack_addr
;
2366 struct trad_frame_cache
*this_trad_cache
;
2367 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2369 if ((*this_cache
) != NULL
)
2370 return (struct trad_frame_cache
*) *this_cache
;
2371 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
2372 (*this_cache
) = this_trad_cache
;
2374 trad_frame_set_reg_realreg (this_trad_cache
, gdbarch_pc_regnum (gdbarch
),
2377 pc
= get_frame_pc (this_frame
);
2378 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2379 stack_addr
= get_frame_register_signed (this_frame
, RISCV_SP_REGNUM
);
2380 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2382 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2384 return this_trad_cache
;
2387 /* Implement the this_id callback for RiscV frame unwinder. */
2390 riscv_frame_this_id (struct frame_info
*this_frame
,
2391 void **prologue_cache
,
2392 struct frame_id
*this_id
)
2394 struct trad_frame_cache
*info
;
2396 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2397 trad_frame_get_id (info
, this_id
);
2400 /* Implement the prev_register callback for RiscV frame unwinder. */
2402 static struct value
*
2403 riscv_frame_prev_register (struct frame_info
*this_frame
,
2404 void **prologue_cache
,
2407 struct trad_frame_cache
*info
;
2409 info
= riscv_frame_cache (this_frame
, prologue_cache
);
2410 return trad_frame_get_register (info
, this_frame
, regnum
);
2413 /* Structure defining the RiscV normal frame unwind functions. Since we
2414 are the fallback unwinder (DWARF unwinder is used first), we use the
2415 default frame sniffer, which always accepts the frame. */
2417 static const struct frame_unwind riscv_frame_unwind
=
2419 /*.type =*/ NORMAL_FRAME
,
2420 /*.stop_reason =*/ default_frame_unwind_stop_reason
,
2421 /*.this_id =*/ riscv_frame_this_id
,
2422 /*.prev_register =*/ riscv_frame_prev_register
,
2423 /*.unwind_data =*/ NULL
,
2424 /*.sniffer =*/ default_frame_sniffer
,
2425 /*.dealloc_cache =*/ NULL
,
2426 /*.prev_arch =*/ NULL
,
2429 /* Initialize the current architecture based on INFO. If possible,
2430 re-use an architecture from ARCHES, which is a list of
2431 architectures already created during this debugging session.
2433 Called e.g. at program startup, when reading a core file, and when
2434 reading a binary file. */
2436 static struct gdbarch
*
2437 riscv_gdbarch_init (struct gdbarch_info info
,
2438 struct gdbarch_list
*arches
)
2440 struct gdbarch
*gdbarch
;
2441 struct gdbarch_tdep
*tdep
;
2442 struct gdbarch_tdep tmp_tdep
;
2443 bool has_compressed_isa
= false;
2446 /* Ideally, we'd like to get as much information from the target for
2447 things like register size, and whether the target has floating point
2448 hardware. However, there are some things that the target can't tell
2449 us, like, what ABI is being used.
2451 So, for now, we take as much information as possible from the ELF,
2452 including things like register size, and FP hardware support, along
2453 with information about the ABI.
2455 Information about this target is built up in TMP_TDEP, and then we
2456 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2457 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2458 memset (&tmp_tdep
, 0, sizeof (tmp_tdep
));
2460 if (info
.abfd
!= NULL
2461 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
2463 unsigned char eclass
= elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
];
2464 int e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2466 if (eclass
== ELFCLASS32
)
2467 tmp_tdep
.abi
.fields
.base_len
= 1;
2468 else if (eclass
== ELFCLASS64
)
2469 tmp_tdep
.abi
.fields
.base_len
= 2;
2471 internal_error (__FILE__
, __LINE__
,
2472 _("unknown ELF header class %d"), eclass
);
2474 if (e_flags
& EF_RISCV_RVC
)
2476 has_compressed_isa
= true;
2477 tmp_tdep
.core_features
|= (1 << ('C' - 'A'));
2480 if (e_flags
& EF_RISCV_FLOAT_ABI_DOUBLE
)
2482 tmp_tdep
.abi
.fields
.float_abi
= 2;
2483 tmp_tdep
.core_features
|= (1 << ('D' - 'A'));
2484 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2486 else if (e_flags
& EF_RISCV_FLOAT_ABI_SINGLE
)
2488 tmp_tdep
.abi
.fields
.float_abi
= 1;
2489 tmp_tdep
.core_features
|= (1 << ('F' - 'A'));
2494 const struct bfd_arch_info
*binfo
= info
.bfd_arch_info
;
2496 if (binfo
->bits_per_word
== 32)
2497 tmp_tdep
.abi
.fields
.base_len
= 1;
2498 else if (binfo
->bits_per_word
== 64)
2499 tmp_tdep
.abi
.fields
.base_len
= 2;
2501 internal_error (__FILE__
, __LINE__
, _("unknown bits_per_word %d"),
2502 binfo
->bits_per_word
);
2505 /* Find a candidate among the list of pre-declared architectures. */
2506 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2508 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2509 if (gdbarch_tdep (arches
->gdbarch
)->abi
.value
== tmp_tdep
.abi
.value
)
2510 return arches
->gdbarch
;
2512 /* None found, so create a new architecture from the information provided. */
2513 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof *tdep
);
2514 gdbarch
= gdbarch_alloc (&info
, tdep
);
2515 memcpy (tdep
, &tmp_tdep
, sizeof (tmp_tdep
));
2517 /* Target data types. */
2518 set_gdbarch_short_bit (gdbarch
, 16);
2519 set_gdbarch_int_bit (gdbarch
, 32);
2520 set_gdbarch_long_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2521 set_gdbarch_long_long_bit (gdbarch
, 64);
2522 set_gdbarch_float_bit (gdbarch
, 32);
2523 set_gdbarch_double_bit (gdbarch
, 64);
2524 set_gdbarch_long_double_bit (gdbarch
, 128);
2525 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
2526 set_gdbarch_ptr_bit (gdbarch
, riscv_isa_xlen (gdbarch
) * 8);
2527 set_gdbarch_char_signed (gdbarch
, 0);
2529 /* Information about the target architecture. */
2530 set_gdbarch_return_value (gdbarch
, riscv_return_value
);
2531 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, riscv_breakpoint_kind_from_pc
);
2532 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, riscv_sw_breakpoint_from_kind
);
2534 /* Register architecture. */
2535 set_gdbarch_num_regs (gdbarch
, RISCV_LAST_REGNUM
+ 1);
2536 set_gdbarch_sp_regnum (gdbarch
, RISCV_SP_REGNUM
);
2537 set_gdbarch_pc_regnum (gdbarch
, RISCV_PC_REGNUM
);
2538 set_gdbarch_ps_regnum (gdbarch
, RISCV_FP_REGNUM
);
2539 set_gdbarch_deprecated_fp_regnum (gdbarch
, RISCV_FP_REGNUM
);
2541 /* Functions to supply register information. */
2542 set_gdbarch_register_name (gdbarch
, riscv_register_name
);
2543 set_gdbarch_register_type (gdbarch
, riscv_register_type
);
2544 set_gdbarch_print_registers_info (gdbarch
, riscv_print_registers_info
);
2545 set_gdbarch_register_reggroup_p (gdbarch
, riscv_register_reggroup_p
);
2547 /* Functions to analyze frames. */
2548 set_gdbarch_decr_pc_after_break (gdbarch
, (has_compressed_isa
? 2 : 4));
2549 set_gdbarch_skip_prologue (gdbarch
, riscv_skip_prologue
);
2550 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2551 set_gdbarch_frame_align (gdbarch
, riscv_frame_align
);
2553 /* Functions to access frame data. */
2554 set_gdbarch_unwind_pc (gdbarch
, riscv_unwind_pc
);
2555 set_gdbarch_unwind_sp (gdbarch
, riscv_unwind_sp
);
2557 /* Functions handling dummy frames. */
2558 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
2559 set_gdbarch_push_dummy_code (gdbarch
, riscv_push_dummy_code
);
2560 set_gdbarch_push_dummy_call (gdbarch
, riscv_push_dummy_call
);
2561 set_gdbarch_dummy_id (gdbarch
, riscv_dummy_id
);
2563 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2565 dwarf2_append_unwinders (gdbarch
);
2566 frame_unwind_append_unwinder (gdbarch
, &riscv_frame_unwind
);
2568 /* Check any target description for validity. */
2569 if (tdesc_has_registers (info
.target_desc
))
2571 const struct tdesc_feature
*feature
;
2572 struct tdesc_arch_data
*tdesc_data
;
2575 feature
= tdesc_find_feature (info
.target_desc
, "org.gnu.gdb.riscv.cpu");
2576 if (feature
== NULL
)
2579 tdesc_data
= tdesc_data_alloc ();
2582 for (i
= RISCV_ZERO_REGNUM
; i
<= RISCV_LAST_FP_REGNUM
; ++i
)
2583 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
2584 riscv_gdb_reg_names
[i
]);
2585 for (i
= RISCV_FIRST_CSR_REGNUM
; i
<= RISCV_LAST_CSR_REGNUM
; ++i
)
2589 sprintf (buf
, "csr%d", i
- RISCV_FIRST_CSR_REGNUM
);
2590 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, buf
);
2593 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
++, "priv");
2596 tdesc_data_cleanup (tdesc_data
);
2598 tdesc_use_registers (gdbarch
, info
.target_desc
, tdesc_data
);
2602 for (i
= 0; i
< ARRAY_SIZE (riscv_register_aliases
); ++i
)
2603 user_reg_add (gdbarch
, riscv_register_aliases
[i
].name
,
2604 value_of_riscv_user_reg
, &riscv_register_aliases
[i
].regnum
);
2610 /* Allocate new riscv_inferior_data object. */
2612 static struct riscv_inferior_data
*
2613 riscv_new_inferior_data (void)
2615 struct riscv_inferior_data
*inf_data
2616 = new (struct riscv_inferior_data
);
2617 inf_data
->misa_read
= false;
2621 /* Free inferior data. */
2624 riscv_inferior_data_cleanup (struct inferior
*inf
, void *data
)
2626 struct riscv_inferior_data
*inf_data
=
2627 static_cast <struct riscv_inferior_data
*> (data
);
2631 /* Return riscv_inferior_data for the given INFERIOR. If not yet created,
2634 struct riscv_inferior_data
*
2635 riscv_inferior_data (struct inferior
*const inf
)
2637 struct riscv_inferior_data
*inf_data
;
2639 gdb_assert (inf
!= NULL
);
2642 = (struct riscv_inferior_data
*) inferior_data (inf
, riscv_inferior_data_reg
);
2643 if (inf_data
== NULL
)
2645 inf_data
= riscv_new_inferior_data ();
2646 set_inferior_data (inf
, riscv_inferior_data_reg
, inf_data
);
2652 /* Free the inferior data when an inferior exits. */
2655 riscv_invalidate_inferior_data (struct inferior
*inf
)
2657 struct riscv_inferior_data
*inf_data
;
2659 gdb_assert (inf
!= NULL
);
2661 /* Don't call RISCV_INFERIOR_DATA as we don't want to create the data if
2662 we've not already created it by this point. */
2664 = (struct riscv_inferior_data
*) inferior_data (inf
, riscv_inferior_data_reg
);
2665 if (inf_data
!= NULL
)
2668 set_inferior_data (inf
, riscv_inferior_data_reg
, NULL
);
2673 _initialize_riscv_tdep (void)
2675 gdbarch_register (bfd_arch_riscv
, riscv_gdbarch_init
, NULL
);
2677 /* Register per-inferior data. */
2678 riscv_inferior_data_reg
2679 = register_inferior_data_with_cleanup (NULL
, riscv_inferior_data_cleanup
);
2681 /* Observers used to invalidate the inferior data when needed. */
2682 observer_attach_inferior_exit (riscv_invalidate_inferior_data
);
2683 observer_attach_inferior_appeared (riscv_invalidate_inferior_data
);
2685 /* Add root prefix command for all "set debug riscv" and "show debug
2687 add_prefix_cmd ("riscv", no_class
, set_debug_riscv_command
,
2688 _("RISC-V specific debug commands."),
2689 &setdebugriscvcmdlist
, "set debug riscv ", 0,
2692 add_prefix_cmd ("riscv", no_class
, show_debug_riscv_command
,
2693 _("RISC-V specific debug commands."),
2694 &showdebugriscvcmdlist
, "show debug riscv ", 0,
2697 add_setshow_zuinteger_cmd ("infcall", class_maintenance
,
2698 &riscv_debug_infcall
, _("\
2699 Set riscv inferior call debugging."), _("\
2700 Show riscv inferior call debugging."), _("\
2701 When non-zero, print debugging information for the riscv specific parts\n\
2702 of the inferior call mechanism."),
2704 show_riscv_debug_variable
,
2705 &setdebugriscvcmdlist
, &showdebugriscvcmdlist
);
2707 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2708 add_prefix_cmd ("riscv", no_class
, set_riscv_command
,
2709 _("RISC-V specific commands."),
2710 &setriscvcmdlist
, "set riscv ", 0, &setlist
);
2712 add_prefix_cmd ("riscv", no_class
, show_riscv_command
,
2713 _("RISC-V specific commands."),
2714 &showriscvcmdlist
, "show riscv ", 0, &showlist
);
2717 use_compressed_breakpoints
= AUTO_BOOLEAN_AUTO
;
2718 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class
,
2719 &use_compressed_breakpoints
,
2721 Set debugger's use of compressed breakpoints."), _(" \
2722 Show debugger's use of compressed breakpoints."), _("\
2723 Debugging compressed code requires compressed breakpoints to be used. If\n \
2724 left to 'auto' then gdb will use them if $misa indicates the C extension\n \
2725 is supported. If that doesn't give the correct behavior, then this option\n\
2728 show_use_compressed_breakpoints
,