1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* Holds the current set of options to be passed to the disassembler. */
110 static char *powerpc_disassembler_options
;
112 /* The list of available "set powerpc ..." and "show powerpc ..."
114 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
115 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
117 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
119 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
120 static const char *const powerpc_vector_strings
[] =
129 /* A variable that can be configured by the user. */
130 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
131 static const char *powerpc_vector_abi_string
= "auto";
133 /* To be used by skip_prologue. */
135 struct rs6000_framedata
137 int offset
; /* total size of frame --- the distance
138 by which we decrement sp to allocate
140 int saved_gpr
; /* smallest # of saved gpr */
141 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
142 int saved_fpr
; /* smallest # of saved fpr */
143 int saved_vr
; /* smallest # of saved vr */
144 int saved_ev
; /* smallest # of saved ev */
145 int alloca_reg
; /* alloca register number (frame ptr) */
146 char frameless
; /* true if frameless functions. */
147 char nosavedpc
; /* true if pc not saved. */
148 char used_bl
; /* true if link register clobbered */
149 int gpr_offset
; /* offset of saved gprs from prev sp */
150 int fpr_offset
; /* offset of saved fprs from prev sp */
151 int vr_offset
; /* offset of saved vrs from prev sp */
152 int ev_offset
; /* offset of saved evs from prev sp */
153 int lr_offset
; /* offset of saved lr */
154 int lr_register
; /* register of saved lr, if trustworthy */
155 int cr_offset
; /* offset of saved cr */
156 int vrsave_offset
; /* offset of saved vrsave register */
160 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
162 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
165 if (tdep
->ppc_vsr0_regnum
< 0)
168 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
169 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
172 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
174 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
177 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
180 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
184 /* Return true if REGNO is an SPE register, false otherwise. */
186 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
190 /* Is it a reference to EV0 -- EV31, and do we have those? */
191 if (IS_SPE_PSEUDOREG (tdep
, regno
))
194 /* Is it a reference to one of the raw upper GPR halves? */
195 if (tdep
->ppc_ev0_upper_regnum
>= 0
196 && tdep
->ppc_ev0_upper_regnum
<= regno
197 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
200 /* Is it a reference to the 64-bit accumulator, and do we have that? */
201 if (tdep
->ppc_acc_regnum
>= 0
202 && tdep
->ppc_acc_regnum
== regno
)
205 /* Is it a reference to the SPE floating-point status and control register,
206 and do we have that? */
207 if (tdep
->ppc_spefscr_regnum
>= 0
208 && tdep
->ppc_spefscr_regnum
== regno
)
215 /* Return non-zero if the architecture described by GDBARCH has
216 floating-point registers (f0 --- f31 and fpscr). */
218 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 return (tdep
->ppc_fp0_regnum
>= 0
223 && tdep
->ppc_fpscr_regnum
>= 0);
226 /* Return non-zero if the architecture described by GDBARCH has
227 Altivec registers (vr0 --- vr31, vrsave and vscr). */
229 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
233 return (tdep
->ppc_vr0_regnum
>= 0
234 && tdep
->ppc_vrsave_regnum
>= 0);
237 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
240 This is a helper function for init_sim_regno_table, constructing
241 the table mapping GDB register numbers to sim register numbers; we
242 initialize every element in that table to -1 before we start
245 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
247 /* Make sure we don't try to assign any given GDB register a sim
248 register number more than once. */
249 gdb_assert (table
[gdb_regno
] == -1);
250 table
[gdb_regno
] = sim_regno
;
254 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
255 numbers to simulator register numbers, based on the values placed
256 in the ARCH->tdep->ppc_foo_regnum members. */
258 init_sim_regno_table (struct gdbarch
*arch
)
260 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
261 int total_regs
= gdbarch_num_regs (arch
);
262 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
264 static const char *const segment_regs
[] = {
265 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
266 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
269 /* Presume that all registers not explicitly mentioned below are
270 unavailable from the sim. */
271 for (i
= 0; i
< total_regs
; i
++)
274 /* General-purpose registers. */
275 for (i
= 0; i
< ppc_num_gprs
; i
++)
276 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
278 /* Floating-point registers. */
279 if (tdep
->ppc_fp0_regnum
>= 0)
280 for (i
= 0; i
< ppc_num_fprs
; i
++)
281 set_sim_regno (sim_regno
,
282 tdep
->ppc_fp0_regnum
+ i
,
283 sim_ppc_f0_regnum
+ i
);
284 if (tdep
->ppc_fpscr_regnum
>= 0)
285 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
287 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
288 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
289 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
291 /* Segment registers. */
292 for (i
= 0; i
< ppc_num_srs
; i
++)
296 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
298 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
301 /* Altivec registers. */
302 if (tdep
->ppc_vr0_regnum
>= 0)
304 for (i
= 0; i
< ppc_num_vrs
; i
++)
305 set_sim_regno (sim_regno
,
306 tdep
->ppc_vr0_regnum
+ i
,
307 sim_ppc_vr0_regnum
+ i
);
309 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
310 we can treat this more like the other cases. */
311 set_sim_regno (sim_regno
,
312 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
313 sim_ppc_vscr_regnum
);
315 /* vsave is a special-purpose register, so the code below handles it. */
317 /* SPE APU (E500) registers. */
318 if (tdep
->ppc_ev0_upper_regnum
>= 0)
319 for (i
= 0; i
< ppc_num_gprs
; i
++)
320 set_sim_regno (sim_regno
,
321 tdep
->ppc_ev0_upper_regnum
+ i
,
322 sim_ppc_rh0_regnum
+ i
);
323 if (tdep
->ppc_acc_regnum
>= 0)
324 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
325 /* spefscr is a special-purpose register, so the code below handles it. */
328 /* Now handle all special-purpose registers. Verify that they
329 haven't mistakenly been assigned numbers by any of the above
331 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
333 const char *spr_name
= sim_spr_register_name (i
);
336 if (spr_name
!= NULL
)
337 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
340 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
344 /* Drop the initialized array into place. */
345 tdep
->sim_regno
= sim_regno
;
349 /* Given a GDB register number REG, return the corresponding SIM
352 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
354 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
357 if (tdep
->sim_regno
== NULL
)
358 init_sim_regno_table (gdbarch
);
361 && reg
<= gdbarch_num_regs (gdbarch
)
362 + gdbarch_num_pseudo_regs (gdbarch
));
363 sim_regno
= tdep
->sim_regno
[reg
];
368 return LEGACY_SIM_REGNO_IGNORE
;
373 /* Register set support functions. */
375 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
376 Write the register to REGCACHE. */
379 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
380 const gdb_byte
*regs
, size_t offset
, int regsize
)
382 if (regnum
!= -1 && offset
!= -1)
386 struct gdbarch
*gdbarch
= regcache
->arch ();
387 int gdb_regsize
= register_size (gdbarch
, regnum
);
388 if (gdb_regsize
< regsize
389 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
390 offset
+= regsize
- gdb_regsize
;
392 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
396 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
397 in a field REGSIZE wide. Zero pad as necessary. */
400 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
401 gdb_byte
*regs
, size_t offset
, int regsize
)
403 if (regnum
!= -1 && offset
!= -1)
407 struct gdbarch
*gdbarch
= regcache
->arch ();
408 int gdb_regsize
= register_size (gdbarch
, regnum
);
409 if (gdb_regsize
< regsize
)
411 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
413 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
414 offset
+= regsize
- gdb_regsize
;
417 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
418 regsize
- gdb_regsize
);
421 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
426 ppc_greg_offset (struct gdbarch
*gdbarch
,
427 struct gdbarch_tdep
*tdep
,
428 const struct ppc_reg_offsets
*offsets
,
432 *regsize
= offsets
->gpr_size
;
433 if (regnum
>= tdep
->ppc_gp0_regnum
434 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
435 return (offsets
->r0_offset
436 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
438 if (regnum
== gdbarch_pc_regnum (gdbarch
))
439 return offsets
->pc_offset
;
441 if (regnum
== tdep
->ppc_ps_regnum
)
442 return offsets
->ps_offset
;
444 if (regnum
== tdep
->ppc_lr_regnum
)
445 return offsets
->lr_offset
;
447 if (regnum
== tdep
->ppc_ctr_regnum
)
448 return offsets
->ctr_offset
;
450 *regsize
= offsets
->xr_size
;
451 if (regnum
== tdep
->ppc_cr_regnum
)
452 return offsets
->cr_offset
;
454 if (regnum
== tdep
->ppc_xer_regnum
)
455 return offsets
->xer_offset
;
457 if (regnum
== tdep
->ppc_mq_regnum
)
458 return offsets
->mq_offset
;
464 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
465 const struct ppc_reg_offsets
*offsets
,
468 if (regnum
>= tdep
->ppc_fp0_regnum
469 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
470 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
472 if (regnum
== tdep
->ppc_fpscr_regnum
)
473 return offsets
->fpscr_offset
;
478 /* Supply register REGNUM in the general-purpose register set REGSET
479 from the buffer specified by GREGS and LEN to register cache
480 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
483 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
484 int regnum
, const void *gregs
, size_t len
)
486 struct gdbarch
*gdbarch
= regcache
->arch ();
487 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
488 const struct ppc_reg_offsets
*offsets
489 = (const struct ppc_reg_offsets
*) regset
->regmap
;
496 int gpr_size
= offsets
->gpr_size
;
498 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
499 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
500 i
++, offset
+= gpr_size
)
501 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
504 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
505 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
506 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
507 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
508 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
509 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
510 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
511 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
512 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
513 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
515 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
516 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
518 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
519 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
524 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
525 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
528 /* Supply register REGNUM in the floating-point register set REGSET
529 from the buffer specified by FPREGS and LEN to register cache
530 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
533 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
534 int regnum
, const void *fpregs
, size_t len
)
536 struct gdbarch
*gdbarch
= regcache
->arch ();
537 struct gdbarch_tdep
*tdep
;
538 const struct ppc_reg_offsets
*offsets
;
541 if (!ppc_floating_point_unit_p (gdbarch
))
544 tdep
= gdbarch_tdep (gdbarch
);
545 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
550 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
551 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
553 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
555 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
556 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
557 offsets
->fpscr_size
);
561 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
562 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
563 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
566 /* Collect register REGNUM in the general-purpose register set
567 REGSET from register cache REGCACHE into the buffer specified by
568 GREGS and LEN. If REGNUM is -1, do this for all registers in
572 ppc_collect_gregset (const struct regset
*regset
,
573 const struct regcache
*regcache
,
574 int regnum
, void *gregs
, size_t len
)
576 struct gdbarch
*gdbarch
= regcache
->arch ();
577 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
578 const struct ppc_reg_offsets
*offsets
579 = (const struct ppc_reg_offsets
*) regset
->regmap
;
586 int gpr_size
= offsets
->gpr_size
;
588 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
589 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
590 i
++, offset
+= gpr_size
)
591 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
593 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
594 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
595 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
596 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
597 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
598 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
599 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
600 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
601 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
602 (gdb_byte
*) gregs
, offsets
->cr_offset
,
604 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
605 (gdb_byte
*) gregs
, offsets
->xer_offset
,
607 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
608 (gdb_byte
*) gregs
, offsets
->mq_offset
,
613 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
614 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
617 /* Collect register REGNUM in the floating-point register set
618 REGSET from register cache REGCACHE into the buffer specified by
619 FPREGS and LEN. If REGNUM is -1, do this for all registers in
623 ppc_collect_fpregset (const struct regset
*regset
,
624 const struct regcache
*regcache
,
625 int regnum
, void *fpregs
, size_t len
)
627 struct gdbarch
*gdbarch
= regcache
->arch ();
628 struct gdbarch_tdep
*tdep
;
629 const struct ppc_reg_offsets
*offsets
;
632 if (!ppc_floating_point_unit_p (gdbarch
))
635 tdep
= gdbarch_tdep (gdbarch
);
636 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
641 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
642 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
644 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
646 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
647 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
648 offsets
->fpscr_size
);
652 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
653 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
654 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
658 insn_changes_sp_or_jumps (unsigned long insn
)
660 int opcode
= (insn
>> 26) & 0x03f;
661 int sd
= (insn
>> 21) & 0x01f;
662 int a
= (insn
>> 16) & 0x01f;
663 int subcode
= (insn
>> 1) & 0x3ff;
665 /* Changes the stack pointer. */
667 /* NOTE: There are many ways to change the value of a given register.
668 The ways below are those used when the register is R1, the SP,
669 in a funtion's epilogue. */
671 if (opcode
== 31 && subcode
== 444 && a
== 1)
672 return 1; /* mr R1,Rn */
673 if (opcode
== 14 && sd
== 1)
674 return 1; /* addi R1,Rn,simm */
675 if (opcode
== 58 && sd
== 1)
676 return 1; /* ld R1,ds(Rn) */
678 /* Transfers control. */
684 if (opcode
== 19 && subcode
== 16)
686 if (opcode
== 19 && subcode
== 528)
687 return 1; /* bcctr */
692 /* Return true if we are in the function's epilogue, i.e. after the
693 instruction that destroyed the function's stack frame.
695 1) scan forward from the point of execution:
696 a) If you find an instruction that modifies the stack pointer
697 or transfers control (except a return), execution is not in
699 b) Stop scanning if you find a return instruction or reach the
700 end of the function or reach the hard limit for the size of
702 2) scan backward from the point of execution:
703 a) If you find an instruction that modifies the stack pointer,
704 execution *is* in an epilogue, return.
705 b) Stop scanning if you reach an instruction that transfers
706 control or the beginning of the function or reach the hard
707 limit for the size of an epilogue. */
710 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
711 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
713 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
714 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
715 bfd_byte insn_buf
[PPC_INSN_SIZE
];
716 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
719 /* Find the search limits based on function boundaries and hard limit. */
721 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
724 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
725 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
727 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
728 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
730 /* Scan forward until next 'blr'. */
732 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
734 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
736 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
737 if (insn
== 0x4e800020)
739 /* Assume a bctr is a tail call unless it points strictly within
741 if (insn
== 0x4e800420)
743 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
744 tdep
->ppc_ctr_regnum
);
745 if (ctr
> func_start
&& ctr
< func_end
)
750 if (insn_changes_sp_or_jumps (insn
))
754 /* Scan backward until adjustment to stack pointer (R1). */
756 for (scan_pc
= pc
- PPC_INSN_SIZE
;
757 scan_pc
>= epilogue_start
;
758 scan_pc
-= PPC_INSN_SIZE
)
760 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
762 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
763 if (insn_changes_sp_or_jumps (insn
))
770 /* Implement the stack_frame_destroyed_p gdbarch method. */
773 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
775 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
779 /* Get the ith function argument for the current function. */
781 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
784 return get_frame_register_unsigned (frame
, 3 + argi
);
787 /* Sequence of bytes for breakpoint instruction. */
789 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
790 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
792 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
795 /* Instruction masks for displaced stepping. */
796 #define BRANCH_MASK 0xfc000000
797 #define BP_MASK 0xFC0007FE
798 #define B_INSN 0x48000000
799 #define BC_INSN 0x40000000
800 #define BXL_INSN 0x4c000000
801 #define BP_INSN 0x7C000008
803 /* Instruction masks used during single-stepping of atomic
805 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
806 #define LWARX_INSTRUCTION 0x7c000028
807 #define LDARX_INSTRUCTION 0x7c0000A8
808 #define LBARX_INSTRUCTION 0x7c000068
809 #define LHARX_INSTRUCTION 0x7c0000e8
810 #define LQARX_INSTRUCTION 0x7c000228
811 #define STORE_CONDITIONAL_MASK 0xfc0007ff
812 #define STWCX_INSTRUCTION 0x7c00012d
813 #define STDCX_INSTRUCTION 0x7c0001ad
814 #define STBCX_INSTRUCTION 0x7c00056d
815 #define STHCX_INSTRUCTION 0x7c0005ad
816 #define STQCX_INSTRUCTION 0x7c00016d
818 /* Check if insn is one of the Load And Reserve instructions used for atomic
820 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
821 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
822 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
823 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
824 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
825 /* Check if insn is one of the Store Conditional instructions used for atomic
827 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
828 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
829 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
830 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
831 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
833 typedef buf_displaced_step_closure ppc_displaced_step_closure
;
835 /* We can't displaced step atomic sequences. */
837 static struct displaced_step_closure
*
838 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
839 CORE_ADDR from
, CORE_ADDR to
,
840 struct regcache
*regs
)
842 size_t len
= gdbarch_max_insn_length (gdbarch
);
843 std::unique_ptr
<ppc_displaced_step_closure
> closure
844 (new ppc_displaced_step_closure (len
));
845 gdb_byte
*buf
= closure
->buf
.data ();
846 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
849 read_memory (from
, buf
, len
);
851 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
853 /* Assume all atomic sequences start with a Load and Reserve instruction. */
854 if (IS_LOAD_AND_RESERVE_INSN (insn
))
858 fprintf_unfiltered (gdb_stdlog
,
859 "displaced: can't displaced step "
860 "atomic sequence at %s\n",
861 paddress (gdbarch
, from
));
867 write_memory (to
, buf
, len
);
871 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
872 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
873 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
876 return closure
.release ();
879 /* Fix up the state of registers and memory after having single-stepped
880 a displaced instruction. */
882 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
883 struct displaced_step_closure
*closure_
,
884 CORE_ADDR from
, CORE_ADDR to
,
885 struct regcache
*regs
)
887 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
888 /* Our closure is a copy of the instruction. */
889 ppc_displaced_step_closure
*closure
= (ppc_displaced_step_closure
*) closure_
;
890 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
891 PPC_INSN_SIZE
, byte_order
);
893 /* Offset for non PC-relative instructions. */
894 LONGEST offset
= PPC_INSN_SIZE
;
896 opcode
= insn
& BRANCH_MASK
;
899 fprintf_unfiltered (gdb_stdlog
,
900 "displaced: (ppc) fixup (%s, %s)\n",
901 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
904 /* Handle PC-relative branch instructions. */
905 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
909 /* Read the current PC value after the instruction has been executed
910 in a displaced location. Calculate the offset to be applied to the
911 original PC value before the displaced stepping. */
912 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
914 offset
= current_pc
- to
;
916 if (opcode
!= BXL_INSN
)
918 /* Check for AA bit indicating whether this is an absolute
919 addressing or PC-relative (1: absolute, 0: relative). */
922 /* PC-relative addressing is being used in the branch. */
926 "displaced: (ppc) branch instruction: %s\n"
927 "displaced: (ppc) adjusted PC from %s to %s\n",
928 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
929 paddress (gdbarch
, from
+ offset
));
931 regcache_cooked_write_unsigned (regs
,
932 gdbarch_pc_regnum (gdbarch
),
938 /* If we're here, it means we have a branch to LR or CTR. If the
939 branch was taken, the offset is probably greater than 4 (the next
940 instruction), so it's safe to assume that an offset of 4 means we
941 did not take the branch. */
942 if (offset
== PPC_INSN_SIZE
)
943 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
944 from
+ PPC_INSN_SIZE
);
947 /* Check for LK bit indicating whether we should set the link
948 register to point to the next instruction
949 (1: Set, 0: Don't set). */
952 /* Link register needs to be set to the next instruction's PC. */
953 regcache_cooked_write_unsigned (regs
,
954 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
955 from
+ PPC_INSN_SIZE
);
957 fprintf_unfiltered (gdb_stdlog
,
958 "displaced: (ppc) adjusted LR to %s\n",
959 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
963 /* Check for breakpoints in the inferior. If we've found one, place the PC
964 right at the breakpoint instruction. */
965 else if ((insn
& BP_MASK
) == BP_INSN
)
966 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
968 /* Handle any other instructions that do not fit in the categories above. */
969 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
973 /* Always use hardware single-stepping to execute the
974 displaced instruction. */
976 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
977 struct displaced_step_closure
*closure
)
982 /* Checks for an atomic sequence of instructions beginning with a
983 Load And Reserve instruction and ending with a Store Conditional
984 instruction. If such a sequence is found, attempt to step through it.
985 A breakpoint is placed at the end of the sequence. */
986 std::vector
<CORE_ADDR
>
987 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
989 struct gdbarch
*gdbarch
= regcache
->arch ();
990 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
991 CORE_ADDR pc
= regcache_read_pc (regcache
);
992 CORE_ADDR breaks
[2] = {-1, -1};
994 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
995 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
998 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
999 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1000 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1002 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1003 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1006 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1008 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1010 loc
+= PPC_INSN_SIZE
;
1011 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1013 /* Assume that there is at most one conditional branch in the atomic
1014 sequence. If a conditional branch is found, put a breakpoint in
1015 its destination address. */
1016 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1018 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1019 int absolute
= insn
& 2;
1021 if (bc_insn_count
>= 1)
1022 return {}; /* More than one conditional branch found, fallback
1023 to the standard single-step code. */
1026 breaks
[1] = immediate
;
1028 breaks
[1] = loc
+ immediate
;
1034 if (IS_STORE_CONDITIONAL_INSN (insn
))
1038 /* Assume that the atomic sequence ends with a Store Conditional
1040 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1044 loc
+= PPC_INSN_SIZE
;
1046 /* Insert a breakpoint right after the end of the atomic sequence. */
1049 /* Check for duplicated breakpoints. Check also for a breakpoint
1050 placed (branch instruction's destination) anywhere in sequence. */
1052 && (breaks
[1] == breaks
[0]
1053 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1054 last_breakpoint
= 0;
1056 std::vector
<CORE_ADDR
> next_pcs
;
1058 for (index
= 0; index
<= last_breakpoint
; index
++)
1059 next_pcs
.push_back (breaks
[index
]);
1065 #define SIGNED_SHORT(x) \
1066 ((sizeof (short) == 2) \
1067 ? ((int)(short)(x)) \
1068 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1070 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1072 /* Limit the number of skipped non-prologue instructions, as the examining
1073 of the prologue is expensive. */
1074 static int max_skip_non_prologue_insns
= 10;
1076 /* Return nonzero if the given instruction OP can be part of the prologue
1077 of a function and saves a parameter on the stack. FRAMEP should be
1078 set if one of the previous instructions in the function has set the
1082 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1084 /* Move parameters from argument registers to temporary register. */
1085 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1087 /* Rx must be scratch register r0. */
1088 const int rx_regno
= (op
>> 16) & 31;
1089 /* Ry: Only r3 - r10 are used for parameter passing. */
1090 const int ry_regno
= GET_SRC_REG (op
);
1092 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1094 *r0_contains_arg
= 1;
1101 /* Save a General Purpose Register on stack. */
1103 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1104 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1106 /* Rx: Only r3 - r10 are used for parameter passing. */
1107 const int rx_regno
= GET_SRC_REG (op
);
1109 return (rx_regno
>= 3 && rx_regno
<= 10);
1112 /* Save a General Purpose Register on stack via the Frame Pointer. */
1115 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1116 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1117 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1119 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1120 However, the compiler sometimes uses r0 to hold an argument. */
1121 const int rx_regno
= GET_SRC_REG (op
);
1123 return ((rx_regno
>= 3 && rx_regno
<= 10)
1124 || (rx_regno
== 0 && *r0_contains_arg
));
1127 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1129 /* Only f2 - f8 are used for parameter passing. */
1130 const int src_regno
= GET_SRC_REG (op
);
1132 return (src_regno
>= 2 && src_regno
<= 8);
1135 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1137 /* Only f2 - f8 are used for parameter passing. */
1138 const int src_regno
= GET_SRC_REG (op
);
1140 return (src_regno
>= 2 && src_regno
<= 8);
1143 /* Not an insn that saves a parameter on stack. */
1147 /* Assuming that INSN is a "bl" instruction located at PC, return
1148 nonzero if the destination of the branch is a "blrl" instruction.
1150 This sequence is sometimes found in certain function prologues.
1151 It allows the function to load the LR register with a value that
1152 they can use to access PIC data using PC-relative offsets. */
1155 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1162 absolute
= (int) ((insn
>> 1) & 1);
1163 immediate
= ((insn
& ~3) << 6) >> 6;
1167 dest
= pc
+ immediate
;
1169 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1170 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1176 /* Return true if OP is a stw or std instruction with
1177 register operands RS and RA and any immediate offset.
1179 If WITH_UPDATE is true, also return true if OP is
1180 a stwu or stdu instruction with the same operands.
1182 Return false otherwise.
1185 store_insn_p (unsigned long op
, unsigned long rs
,
1186 unsigned long ra
, bool with_update
)
1191 if (/* std RS, SIMM(RA) */
1192 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1193 /* stw RS, SIMM(RA) */
1194 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1199 if (/* stdu RS, SIMM(RA) */
1200 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1201 /* stwu RS, SIMM(RA) */
1202 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1209 /* Masks for decoding a branch-and-link (bl) instruction.
1211 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1212 The former is anded with the opcode in question; if the result of
1213 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1214 question is a ``bl'' instruction.
1216 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1217 the branch displacement. */
1219 #define BL_MASK 0xfc000001
1220 #define BL_INSTRUCTION 0x48000001
1221 #define BL_DISPLACEMENT_MASK 0x03fffffc
1223 static unsigned long
1224 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1226 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1230 /* Fetch the instruction and convert it to an integer. */
1231 if (target_read_memory (pc
, buf
, 4))
1233 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1238 /* GCC generates several well-known sequences of instructions at the begining
1239 of each function prologue when compiling with -fstack-check. If one of
1240 such sequences starts at START_PC, then return the address of the
1241 instruction immediately past this sequence. Otherwise, return START_PC. */
1244 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1246 CORE_ADDR pc
= start_pc
;
1247 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1249 /* First possible sequence: A small number of probes.
1250 stw 0, -<some immediate>(1)
1251 [repeat this instruction any (small) number of times]. */
1253 if ((op
& 0xffff0000) == 0x90010000)
1255 while ((op
& 0xffff0000) == 0x90010000)
1258 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1263 /* Second sequence: A probing loop.
1264 addi 12,1,-<some immediate>
1265 lis 0,-<some immediate>
1266 [possibly ori 0,0,<some immediate>]
1270 addi 12,12,-<some immediate>
1273 [possibly one last probe: stw 0,<some immediate>(12)]. */
1277 /* addi 12,1,-<some immediate> */
1278 if ((op
& 0xffff0000) != 0x39810000)
1281 /* lis 0,-<some immediate> */
1283 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1284 if ((op
& 0xffff0000) != 0x3c000000)
1288 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1289 /* [possibly ori 0,0,<some immediate>] */
1290 if ((op
& 0xffff0000) == 0x60000000)
1293 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1296 if (op
!= 0x7c0c0214)
1301 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1302 if (op
!= 0x7c0c0000)
1307 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1308 if ((op
& 0xff9f0001) != 0x41820000)
1311 /* addi 12,12,-<some immediate> */
1313 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1314 if ((op
& 0xffff0000) != 0x398c0000)
1319 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1320 if (op
!= 0x900c0000)
1325 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1326 if ((op
& 0xfc000001) != 0x48000000)
1329 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1331 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1332 if ((op
& 0xffff0000) == 0x900c0000)
1335 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1338 /* We found a valid stack-check sequence, return the new PC. */
1342 /* Third sequence: No probe; instead, a comparizon between the stack size
1343 limit (saved in a run-time global variable) and the current stack
1346 addi 0,1,-<some immediate>
1347 lis 12,__gnat_stack_limit@ha
1348 lwz 12,__gnat_stack_limit@l(12)
1351 or, with a small variant in the case of a bigger stack frame:
1352 addis 0,1,<some immediate>
1353 addic 0,0,-<some immediate>
1354 lis 12,__gnat_stack_limit@ha
1355 lwz 12,__gnat_stack_limit@l(12)
1360 /* addi 0,1,-<some immediate> */
1361 if ((op
& 0xffff0000) != 0x38010000)
1363 /* small stack frame variant not recognized; try the
1364 big stack frame variant: */
1366 /* addis 0,1,<some immediate> */
1367 if ((op
& 0xffff0000) != 0x3c010000)
1370 /* addic 0,0,-<some immediate> */
1372 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1373 if ((op
& 0xffff0000) != 0x30000000)
1377 /* lis 12,<some immediate> */
1379 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1380 if ((op
& 0xffff0000) != 0x3d800000)
1383 /* lwz 12,<some immediate>(12) */
1385 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1386 if ((op
& 0xffff0000) != 0x818c0000)
1391 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1392 if ((op
& 0xfffffffe) != 0x7c406008)
1395 /* We found a valid stack-check sequence, return the new PC. */
1399 /* No stack check code in our prologue, return the start_pc. */
1403 /* return pc value after skipping a function prologue and also return
1404 information about a function frame.
1406 in struct rs6000_framedata fdata:
1407 - frameless is TRUE, if function does not have a frame.
1408 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1409 - offset is the initial size of this stack frame --- the amount by
1410 which we decrement the sp to allocate the frame.
1411 - saved_gpr is the number of the first saved gpr.
1412 - saved_fpr is the number of the first saved fpr.
1413 - saved_vr is the number of the first saved vr.
1414 - saved_ev is the number of the first saved ev.
1415 - alloca_reg is the number of the register used for alloca() handling.
1417 - gpr_offset is the offset of the first saved gpr from the previous frame.
1418 - fpr_offset is the offset of the first saved fpr from the previous frame.
1419 - vr_offset is the offset of the first saved vr from the previous frame.
1420 - ev_offset is the offset of the first saved ev from the previous frame.
1421 - lr_offset is the offset of the saved lr
1422 - cr_offset is the offset of the saved cr
1423 - vrsave_offset is the offset of the saved vrsave register. */
1426 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1427 struct rs6000_framedata
*fdata
)
1429 CORE_ADDR orig_pc
= pc
;
1430 CORE_ADDR last_prologue_pc
= pc
;
1431 CORE_ADDR li_found_pc
= 0;
1435 long alloca_reg_offset
= 0;
1436 long vr_saved_offset
= 0;
1442 int vrsave_reg
= -1;
1445 int minimal_toc_loaded
= 0;
1446 int prev_insn_was_prologue_insn
= 1;
1447 int num_skip_non_prologue_insns
= 0;
1448 int r0_contains_arg
= 0;
1449 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1450 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1451 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1453 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1454 fdata
->saved_gpr
= -1;
1455 fdata
->saved_fpr
= -1;
1456 fdata
->saved_vr
= -1;
1457 fdata
->saved_ev
= -1;
1458 fdata
->alloca_reg
= -1;
1459 fdata
->frameless
= 1;
1460 fdata
->nosavedpc
= 1;
1461 fdata
->lr_register
= -1;
1463 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1469 /* Sometimes it isn't clear if an instruction is a prologue
1470 instruction or not. When we encounter one of these ambiguous
1471 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1472 Otherwise, we'll assume that it really is a prologue instruction. */
1473 if (prev_insn_was_prologue_insn
)
1474 last_prologue_pc
= pc
;
1476 /* Stop scanning if we've hit the limit. */
1480 prev_insn_was_prologue_insn
= 1;
1482 /* Fetch the instruction and convert it to an integer. */
1483 if (target_read_memory (pc
, buf
, 4))
1485 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1487 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1489 /* Since shared library / PIC code, which needs to get its
1490 address at runtime, can appear to save more than one link
1504 remember just the first one, but skip over additional
1507 lr_reg
= (op
& 0x03e00000) >> 21;
1509 r0_contains_arg
= 0;
1512 else if ((op
& 0xfc1fffff) == 0x7c000026)
1514 cr_reg
= (op
& 0x03e00000) >> 21;
1516 r0_contains_arg
= 0;
1520 else if ((op
& 0xfc1f0000) == 0xd8010000)
1521 { /* stfd Rx,NUM(r1) */
1522 reg
= GET_SRC_REG (op
);
1523 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1525 fdata
->saved_fpr
= reg
;
1526 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1531 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1532 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1533 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1534 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1537 reg
= GET_SRC_REG (op
);
1538 if ((op
& 0xfc1f0000) == 0xbc010000)
1539 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1541 fdata
->gpr_mask
|= 1U << reg
;
1542 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1544 fdata
->saved_gpr
= reg
;
1545 if ((op
& 0xfc1f0003) == 0xf8010000)
1547 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1552 else if ((op
& 0xffff0000) == 0x3c4c0000
1553 || (op
& 0xffff0000) == 0x3c400000
1554 || (op
& 0xffff0000) == 0x38420000)
1556 /* . 0: addis 2,12,.TOC.-0b@ha
1557 . addi 2,2,.TOC.-0b@l
1561 used by ELFv2 global entry points to set up r2. */
1564 else if (op
== 0x60000000)
1567 /* Allow nops in the prologue, but do not consider them to
1568 be part of the prologue unless followed by other prologue
1570 prev_insn_was_prologue_insn
= 0;
1574 else if ((op
& 0xffff0000) == 0x3c000000)
1575 { /* addis 0,0,NUM, used for >= 32k frames */
1576 fdata
->offset
= (op
& 0x0000ffff) << 16;
1577 fdata
->frameless
= 0;
1578 r0_contains_arg
= 0;
1582 else if ((op
& 0xffff0000) == 0x60000000)
1583 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1584 fdata
->offset
|= (op
& 0x0000ffff);
1585 fdata
->frameless
= 0;
1586 r0_contains_arg
= 0;
1590 else if (lr_reg
>= 0 &&
1591 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1593 (store_insn_p (op
, lr_reg
,
1594 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1597 if (store_insn_p (op
, lr_reg
, 1, true))
1598 fdata
->lr_offset
= offset
;
1599 else /* LR save through frame pointer. */
1600 fdata
->lr_offset
= alloca_reg_offset
;
1602 fdata
->nosavedpc
= 0;
1603 /* Invalidate lr_reg, but don't set it to -1.
1604 That would mean that it had never been set. */
1606 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1607 (op
& 0xfc000000) == 0x90000000) /* stw */
1609 /* Does not update r1, so add displacement to lr_offset. */
1610 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1615 else if (cr_reg
>= 0 &&
1616 (store_insn_p (op
, cr_reg
, 1, true)))
1618 fdata
->cr_offset
= offset
;
1619 /* Invalidate cr_reg, but don't set it to -1.
1620 That would mean that it had never been set. */
1622 if ((op
& 0xfc000003) == 0xf8000000 ||
1623 (op
& 0xfc000000) == 0x90000000)
1625 /* Does not update r1, so add displacement to cr_offset. */
1626 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1631 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1633 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1634 prediction bits. If the LR has already been saved, we can
1638 else if (op
== 0x48000005)
1645 else if (op
== 0x48000004)
1650 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1651 in V.4 -mminimal-toc */
1652 (op
& 0xffff0000) == 0x3bde0000)
1653 { /* addi 30,30,foo@l */
1657 else if ((op
& 0xfc000001) == 0x48000001)
1661 fdata
->frameless
= 0;
1663 /* If the return address has already been saved, we can skip
1664 calls to blrl (for PIC). */
1665 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1671 /* Don't skip over the subroutine call if it is not within
1672 the first three instructions of the prologue and either
1673 we have no line table information or the line info tells
1674 us that the subroutine call is not part of the line
1675 associated with the prologue. */
1676 if ((pc
- orig_pc
) > 8)
1678 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1679 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1681 if ((prologue_sal
.line
== 0)
1682 || (prologue_sal
.line
!= this_sal
.line
))
1686 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1688 /* At this point, make sure this is not a trampoline
1689 function (a function that simply calls another functions,
1690 and nothing else). If the next is not a nop, this branch
1691 was part of the function prologue. */
1693 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1694 break; /* Don't skip over
1700 /* update stack pointer */
1701 else if ((op
& 0xfc1f0000) == 0x94010000)
1702 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1703 fdata
->frameless
= 0;
1704 fdata
->offset
= SIGNED_SHORT (op
);
1705 offset
= fdata
->offset
;
1708 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1709 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1710 /* No way to figure out what r1 is going to be. */
1711 fdata
->frameless
= 0;
1712 offset
= fdata
->offset
;
1715 else if ((op
& 0xfc1f0003) == 0xf8010001)
1716 { /* stdu rX,NUM(r1) */
1717 fdata
->frameless
= 0;
1718 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1719 offset
= fdata
->offset
;
1722 else if ((op
& 0xffff0000) == 0x38210000)
1723 { /* addi r1,r1,SIMM */
1724 fdata
->frameless
= 0;
1725 fdata
->offset
+= SIGNED_SHORT (op
);
1726 offset
= fdata
->offset
;
1729 /* Load up minimal toc pointer. Do not treat an epilogue restore
1730 of r31 as a minimal TOC load. */
1731 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1732 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1734 && !minimal_toc_loaded
)
1736 minimal_toc_loaded
= 1;
1739 /* move parameters from argument registers to local variable
1742 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1743 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1744 (((op
>> 21) & 31) <= 10) &&
1745 ((long) ((op
>> 16) & 31)
1746 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1750 /* store parameters in stack */
1752 /* Move parameters from argument registers to temporary register. */
1753 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1757 /* Set up frame pointer */
1759 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1761 fdata
->frameless
= 0;
1763 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1764 alloca_reg_offset
= offset
;
1767 /* Another way to set up the frame pointer. */
1769 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1770 || op
== 0x7c3f0b78)
1772 fdata
->frameless
= 0;
1774 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1775 alloca_reg_offset
= offset
;
1778 /* Another way to set up the frame pointer. */
1780 else if ((op
& 0xfc1fffff) == 0x38010000)
1781 { /* addi rX, r1, 0x0 */
1782 fdata
->frameless
= 0;
1784 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1785 + ((op
& ~0x38010000) >> 21));
1786 alloca_reg_offset
= offset
;
1789 /* AltiVec related instructions. */
1790 /* Store the vrsave register (spr 256) in another register for
1791 later manipulation, or load a register into the vrsave
1792 register. 2 instructions are used: mfvrsave and
1793 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1794 and mtspr SPR256, Rn. */
1795 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1796 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1797 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1799 vrsave_reg
= GET_SRC_REG (op
);
1802 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1806 /* Store the register where vrsave was saved to onto the stack:
1807 rS is the register where vrsave was stored in a previous
1809 /* 100100 sssss 00001 dddddddd dddddddd */
1810 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1812 if (vrsave_reg
== GET_SRC_REG (op
))
1814 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1819 /* Compute the new value of vrsave, by modifying the register
1820 where vrsave was saved to. */
1821 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1822 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1826 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1827 in a pair of insns to save the vector registers on the
1829 /* 001110 00000 00000 iiii iiii iiii iiii */
1830 /* 001110 01110 00000 iiii iiii iiii iiii */
1831 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1832 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1834 if ((op
& 0xffff0000) == 0x38000000)
1835 r0_contains_arg
= 0;
1837 vr_saved_offset
= SIGNED_SHORT (op
);
1839 /* This insn by itself is not part of the prologue, unless
1840 if part of the pair of insns mentioned above. So do not
1841 record this insn as part of the prologue yet. */
1842 prev_insn_was_prologue_insn
= 0;
1844 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1845 /* 011111 sssss 11111 00000 00111001110 */
1846 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1848 if (pc
== (li_found_pc
+ 4))
1850 vr_reg
= GET_SRC_REG (op
);
1851 /* If this is the first vector reg to be saved, or if
1852 it has a lower number than others previously seen,
1853 reupdate the frame info. */
1854 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1856 fdata
->saved_vr
= vr_reg
;
1857 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1859 vr_saved_offset
= -1;
1864 /* End AltiVec related instructions. */
1866 /* Start BookE related instructions. */
1867 /* Store gen register S at (r31+uimm).
1868 Any register less than r13 is volatile, so we don't care. */
1869 /* 000100 sssss 11111 iiiii 01100100001 */
1870 else if (arch_info
->mach
== bfd_mach_ppc_e500
1871 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1873 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1876 ev_reg
= GET_SRC_REG (op
);
1877 imm
= (op
>> 11) & 0x1f;
1878 ev_offset
= imm
* 8;
1879 /* If this is the first vector reg to be saved, or if
1880 it has a lower number than others previously seen,
1881 reupdate the frame info. */
1882 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1884 fdata
->saved_ev
= ev_reg
;
1885 fdata
->ev_offset
= ev_offset
+ offset
;
1890 /* Store gen register rS at (r1+rB). */
1891 /* 000100 sssss 00001 bbbbb 01100100000 */
1892 else if (arch_info
->mach
== bfd_mach_ppc_e500
1893 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1895 if (pc
== (li_found_pc
+ 4))
1897 ev_reg
= GET_SRC_REG (op
);
1898 /* If this is the first vector reg to be saved, or if
1899 it has a lower number than others previously seen,
1900 reupdate the frame info. */
1901 /* We know the contents of rB from the previous instruction. */
1902 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1904 fdata
->saved_ev
= ev_reg
;
1905 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1907 vr_saved_offset
= -1;
1913 /* Store gen register r31 at (rA+uimm). */
1914 /* 000100 11111 aaaaa iiiii 01100100001 */
1915 else if (arch_info
->mach
== bfd_mach_ppc_e500
1916 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1918 /* Wwe know that the source register is 31 already, but
1919 it can't hurt to compute it. */
1920 ev_reg
= GET_SRC_REG (op
);
1921 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1922 /* If this is the first vector reg to be saved, or if
1923 it has a lower number than others previously seen,
1924 reupdate the frame info. */
1925 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1927 fdata
->saved_ev
= ev_reg
;
1928 fdata
->ev_offset
= ev_offset
+ offset
;
1933 /* Store gen register S at (r31+r0).
1934 Store param on stack when offset from SP bigger than 4 bytes. */
1935 /* 000100 sssss 11111 00000 01100100000 */
1936 else if (arch_info
->mach
== bfd_mach_ppc_e500
1937 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1939 if (pc
== (li_found_pc
+ 4))
1941 if ((op
& 0x03e00000) >= 0x01a00000)
1943 ev_reg
= GET_SRC_REG (op
);
1944 /* If this is the first vector reg to be saved, or if
1945 it has a lower number than others previously seen,
1946 reupdate the frame info. */
1947 /* We know the contents of r0 from the previous
1949 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1951 fdata
->saved_ev
= ev_reg
;
1952 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1956 vr_saved_offset
= -1;
1961 /* End BookE related instructions. */
1965 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
1967 /* Not a recognized prologue instruction.
1968 Handle optimizer code motions into the prologue by continuing
1969 the search if we have no valid frame yet or if the return
1970 address is not yet saved in the frame. Also skip instructions
1971 if some of the GPRs expected to be saved are not yet saved. */
1972 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
1973 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
1976 if (op
== 0x4e800020 /* blr */
1977 || op
== 0x4e800420) /* bctr */
1978 /* Do not scan past epilogue in frameless functions or
1981 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1982 /* Never skip branches. */
1985 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1986 /* Do not scan too many insns, scanning insns is expensive with
1990 /* Continue scanning. */
1991 prev_insn_was_prologue_insn
= 0;
1997 /* I have problems with skipping over __main() that I need to address
1998 * sometime. Previously, I used to use misc_function_vector which
1999 * didn't work as well as I wanted to be. -MGO */
2001 /* If the first thing after skipping a prolog is a branch to a function,
2002 this might be a call to an initializer in main(), introduced by gcc2.
2003 We'd like to skip over it as well. Fortunately, xlc does some extra
2004 work before calling a function right after a prologue, thus we can
2005 single out such gcc2 behaviour. */
2008 if ((op
& 0xfc000001) == 0x48000001)
2009 { /* bl foo, an initializer function? */
2010 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2012 if (op
== 0x4def7b82)
2013 { /* cror 0xf, 0xf, 0xf (nop) */
2015 /* Check and see if we are in main. If so, skip over this
2016 initializer function as well. */
2018 tmp
= find_pc_misc_function (pc
);
2020 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2026 if (pc
== lim_pc
&& lr_reg
>= 0)
2027 fdata
->lr_register
= lr_reg
;
2029 fdata
->offset
= -fdata
->offset
;
2030 return last_prologue_pc
;
2034 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2036 struct rs6000_framedata frame
;
2037 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2039 /* See if we can determine the end of the prologue via the symbol table.
2040 If so, then return either PC, or the PC after the prologue, whichever
2042 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2044 CORE_ADDR post_prologue_pc
2045 = skip_prologue_using_sal (gdbarch
, func_addr
);
2046 if (post_prologue_pc
!= 0)
2047 return std::max (pc
, post_prologue_pc
);
2050 /* Can't determine prologue from the symbol table, need to examine
2053 /* Find an upper limit on the function prologue using the debug
2054 information. If the debug information could not be used to provide
2055 that bound, then use an arbitrary large number as the upper bound. */
2056 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2058 limit_pc
= pc
+ 100; /* Magic. */
2060 /* Do not allow limit_pc to be past the function end, if we know
2061 where that end is... */
2062 if (func_end_addr
&& limit_pc
> func_end_addr
)
2063 limit_pc
= func_end_addr
;
2065 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2069 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2070 in the prologue of main().
2072 The function below examines the code pointed at by PC and checks to
2073 see if it corresponds to a call to __eabi. If so, it returns the
2074 address of the instruction following that call. Otherwise, it simply
2078 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2080 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2084 if (target_read_memory (pc
, buf
, 4))
2086 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2088 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2090 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2091 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2092 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2094 /* We check for ___eabi (three leading underscores) in addition
2095 to __eabi in case the GCC option "-fleading-underscore" was
2096 used to compile the program. */
2097 if (s
.minsym
!= NULL
2098 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2099 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2100 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2106 /* All the ABI's require 16 byte alignment. */
2108 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2110 return (addr
& -16);
2113 /* Return whether handle_inferior_event() should proceed through code
2114 starting at PC in function NAME when stepping.
2116 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2117 handle memory references that are too distant to fit in instructions
2118 generated by the compiler. For example, if 'foo' in the following
2123 is greater than 32767, the linker might replace the lwz with a branch to
2124 somewhere in @FIX1 that does the load in 2 instructions and then branches
2125 back to where execution should continue.
2127 GDB should silently step over @FIX code, just like AIX dbx does.
2128 Unfortunately, the linker uses the "b" instruction for the
2129 branches, meaning that the link register doesn't get set.
2130 Therefore, GDB's usual step_over_function () mechanism won't work.
2132 Instead, use the gdbarch_skip_trampoline_code and
2133 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2137 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2138 CORE_ADDR pc
, const char *name
)
2140 return name
&& startswith (name
, "@FIX");
2143 /* Skip code that the user doesn't want to see when stepping:
2145 1. Indirect function calls use a piece of trampoline code to do context
2146 switching, i.e. to set the new TOC table. Skip such code if we are on
2147 its first instruction (as when we have single-stepped to here).
2149 2. Skip shared library trampoline code (which is different from
2150 indirect function call trampolines).
2152 3. Skip bigtoc fixup code.
2154 Result is desired PC to step until, or NULL if we are not in
2155 code that should be skipped. */
2158 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2160 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2161 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2162 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2163 unsigned int ii
, op
;
2165 CORE_ADDR solib_target_pc
;
2166 struct bound_minimal_symbol msymbol
;
2168 static unsigned trampoline_code
[] =
2170 0x800b0000, /* l r0,0x0(r11) */
2171 0x90410014, /* st r2,0x14(r1) */
2172 0x7c0903a6, /* mtctr r0 */
2173 0x804b0004, /* l r2,0x4(r11) */
2174 0x816b0008, /* l r11,0x8(r11) */
2175 0x4e800420, /* bctr */
2176 0x4e800020, /* br */
2180 /* Check for bigtoc fixup code. */
2181 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2183 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2184 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2186 /* Double-check that the third instruction from PC is relative "b". */
2187 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2188 if ((op
& 0xfc000003) == 0x48000000)
2190 /* Extract bits 6-29 as a signed 24-bit relative word address and
2191 add it to the containing PC. */
2192 rel
= ((int)(op
<< 6) >> 6);
2193 return pc
+ 8 + rel
;
2197 /* If pc is in a shared library trampoline, return its target. */
2198 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2199 if (solib_target_pc
)
2200 return solib_target_pc
;
2202 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2204 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2205 if (op
!= trampoline_code
[ii
])
2208 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2210 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2214 /* ISA-specific vector types. */
2216 static struct type
*
2217 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2219 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2221 if (!tdep
->ppc_builtin_type_vec64
)
2223 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2225 /* The type we're building is this: */
2227 union __gdb_builtin_type_vec64
2231 int32_t v2_int32
[2];
2232 int16_t v4_int16
[4];
2239 t
= arch_composite_type (gdbarch
,
2240 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2241 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2242 append_composite_type_field (t
, "v2_float",
2243 init_vector_type (bt
->builtin_float
, 2));
2244 append_composite_type_field (t
, "v2_int32",
2245 init_vector_type (bt
->builtin_int32
, 2));
2246 append_composite_type_field (t
, "v4_int16",
2247 init_vector_type (bt
->builtin_int16
, 4));
2248 append_composite_type_field (t
, "v8_int8",
2249 init_vector_type (bt
->builtin_int8
, 8));
2251 TYPE_VECTOR (t
) = 1;
2252 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2253 tdep
->ppc_builtin_type_vec64
= t
;
2256 return tdep
->ppc_builtin_type_vec64
;
2259 /* Vector 128 type. */
2261 static struct type
*
2262 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2264 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2266 if (!tdep
->ppc_builtin_type_vec128
)
2268 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2270 /* The type we're building is this
2272 type = union __ppc_builtin_type_vec128 {
2274 double v2_double[2];
2276 int32_t v4_int32[4];
2277 int16_t v8_int16[8];
2278 int8_t v16_int8[16];
2284 t
= arch_composite_type (gdbarch
,
2285 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2286 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2287 append_composite_type_field (t
, "v2_double",
2288 init_vector_type (bt
->builtin_double
, 2));
2289 append_composite_type_field (t
, "v4_float",
2290 init_vector_type (bt
->builtin_float
, 4));
2291 append_composite_type_field (t
, "v4_int32",
2292 init_vector_type (bt
->builtin_int32
, 4));
2293 append_composite_type_field (t
, "v8_int16",
2294 init_vector_type (bt
->builtin_int16
, 8));
2295 append_composite_type_field (t
, "v16_int8",
2296 init_vector_type (bt
->builtin_int8
, 16));
2298 TYPE_VECTOR (t
) = 1;
2299 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2300 tdep
->ppc_builtin_type_vec128
= t
;
2303 return tdep
->ppc_builtin_type_vec128
;
2306 /* Return the name of register number REGNO, or the empty string if it
2307 is an anonymous register. */
2310 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2314 /* The upper half "registers" have names in the XML description,
2315 but we present only the low GPRs and the full 64-bit registers
2317 if (tdep
->ppc_ev0_upper_regnum
>= 0
2318 && tdep
->ppc_ev0_upper_regnum
<= regno
2319 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2322 /* Hide the upper halves of the vs0~vs31 registers. */
2323 if (tdep
->ppc_vsr0_regnum
>= 0
2324 && tdep
->ppc_vsr0_upper_regnum
<= regno
2325 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2328 /* Check if the SPE pseudo registers are available. */
2329 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2331 static const char *const spe_regnames
[] = {
2332 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2333 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2334 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2335 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2337 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2340 /* Check if the decimal128 pseudo-registers are available. */
2341 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2343 static const char *const dfp128_regnames
[] = {
2344 "dl0", "dl1", "dl2", "dl3",
2345 "dl4", "dl5", "dl6", "dl7",
2346 "dl8", "dl9", "dl10", "dl11",
2347 "dl12", "dl13", "dl14", "dl15"
2349 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2352 /* Check if this is a VSX pseudo-register. */
2353 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2355 static const char *const vsx_regnames
[] = {
2356 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2357 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2358 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2359 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2360 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2361 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2362 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2363 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2364 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2366 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2369 /* Check if the this is a Extended FP pseudo-register. */
2370 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2372 static const char *const efpr_regnames
[] = {
2373 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2374 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2375 "f46", "f47", "f48", "f49", "f50", "f51",
2376 "f52", "f53", "f54", "f55", "f56", "f57",
2377 "f58", "f59", "f60", "f61", "f62", "f63"
2379 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2382 return tdesc_register_name (gdbarch
, regno
);
2385 /* Return the GDB type object for the "standard" data type of data in
2388 static struct type
*
2389 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2391 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2393 /* These are the only pseudo-registers we support. */
2394 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2395 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2396 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2397 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2399 /* These are the e500 pseudo-registers. */
2400 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2401 return rs6000_builtin_type_vec64 (gdbarch
);
2402 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2403 /* PPC decimal128 pseudo-registers. */
2404 return builtin_type (gdbarch
)->builtin_declong
;
2405 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2406 /* POWER7 VSX pseudo-registers. */
2407 return rs6000_builtin_type_vec128 (gdbarch
);
2409 /* POWER7 Extended FP pseudo-registers. */
2410 return builtin_type (gdbarch
)->builtin_double
;
2413 /* Is REGNUM a member of REGGROUP? */
2415 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2416 struct reggroup
*group
)
2418 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2420 /* These are the only pseudo-registers we support. */
2421 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2422 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2423 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2424 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2426 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2427 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2428 return group
== all_reggroup
|| group
== vector_reggroup
;
2430 /* PPC decimal128 or Extended FP pseudo-registers. */
2431 return group
== all_reggroup
|| group
== float_reggroup
;
2434 /* The register format for RS/6000 floating point registers is always
2435 double, we need a conversion if the memory format is float. */
2438 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2441 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2443 return (tdep
->ppc_fp0_regnum
>= 0
2444 && regnum
>= tdep
->ppc_fp0_regnum
2445 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2446 && TYPE_CODE (type
) == TYPE_CODE_FLT
2447 && TYPE_LENGTH (type
)
2448 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2452 rs6000_register_to_value (struct frame_info
*frame
,
2456 int *optimizedp
, int *unavailablep
)
2458 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2459 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2461 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2463 if (!get_frame_register_bytes (frame
, regnum
, 0,
2464 register_size (gdbarch
, regnum
),
2465 from
, optimizedp
, unavailablep
))
2468 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2470 *optimizedp
= *unavailablep
= 0;
2475 rs6000_value_to_register (struct frame_info
*frame
,
2478 const gdb_byte
*from
)
2480 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2481 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2483 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2485 target_float_convert (from
, type
,
2486 to
, builtin_type (gdbarch
)->builtin_double
);
2487 put_frame_register (frame
, regnum
, to
);
2490 /* The type of a function that moves the value of REG between CACHE
2491 or BUF --- in either direction. */
2492 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2495 /* Move SPE vector register values between a 64-bit buffer and the two
2496 32-bit raw register halves in a regcache. This function handles
2497 both splitting a 64-bit value into two 32-bit halves, and joining
2498 two halves into a whole 64-bit value, depending on the function
2499 passed as the MOVE argument.
2501 EV_REG must be the number of an SPE evN vector register --- a
2502 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2505 Call MOVE once for each 32-bit half of that register, passing
2506 REGCACHE, the number of the raw register corresponding to that
2507 half, and the address of the appropriate half of BUFFER.
2509 For example, passing 'regcache_raw_read' as the MOVE function will
2510 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2511 'regcache_raw_supply' will supply the contents of BUFFER to the
2512 appropriate pair of raw registers in REGCACHE.
2514 You may need to cast away some 'const' qualifiers when passing
2515 MOVE, since this function can't tell at compile-time which of
2516 REGCACHE or BUFFER is acting as the source of the data. If C had
2517 co-variant type qualifiers, ... */
2519 static enum register_status
2520 e500_move_ev_register (move_ev_register_func move
,
2521 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2523 struct gdbarch
*arch
= regcache
->arch ();
2524 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2526 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2527 enum register_status status
;
2529 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2531 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2533 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2535 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2537 if (status
== REG_VALID
)
2538 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2543 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2544 if (status
== REG_VALID
)
2545 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2552 static enum register_status
2553 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2555 regcache_raw_write (regcache
, regnum
, (const gdb_byte
*) buffer
);
2560 static enum register_status
2561 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2562 int ev_reg
, gdb_byte
*buffer
)
2564 struct gdbarch
*arch
= regcache
->arch ();
2565 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2567 enum register_status status
;
2569 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2571 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2573 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2575 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2577 if (status
== REG_VALID
)
2578 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2583 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2584 if (status
== REG_VALID
)
2585 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2594 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2595 int reg_nr
, const gdb_byte
*buffer
)
2597 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2598 reg_nr
, (void *) buffer
);
2601 /* Read method for DFP pseudo-registers. */
2602 static enum register_status
2603 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2604 int reg_nr
, gdb_byte
*buffer
)
2606 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2607 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2608 enum register_status status
;
2610 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2612 /* Read two FP registers to form a whole dl register. */
2613 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2614 2 * reg_index
, buffer
);
2615 if (status
== REG_VALID
)
2616 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2617 2 * reg_index
+ 1, buffer
+ 8);
2621 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2622 2 * reg_index
+ 1, buffer
);
2623 if (status
== REG_VALID
)
2624 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2625 2 * reg_index
, buffer
+ 8);
2631 /* Write method for DFP pseudo-registers. */
2633 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2634 int reg_nr
, const gdb_byte
*buffer
)
2636 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2637 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2639 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2641 /* Write each half of the dl register into a separate
2643 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2644 2 * reg_index
, buffer
);
2645 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2646 2 * reg_index
+ 1, buffer
+ 8);
2650 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2651 2 * reg_index
+ 1, buffer
);
2652 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2653 2 * reg_index
, buffer
+ 8);
2657 /* Read method for POWER7 VSX pseudo-registers. */
2658 static enum register_status
2659 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2660 int reg_nr
, gdb_byte
*buffer
)
2662 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2663 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2664 enum register_status status
;
2666 /* Read the portion that overlaps the VMX registers. */
2668 status
= regcache
->raw_read (tdep
->ppc_vr0_regnum
+
2669 reg_index
- 32, buffer
);
2671 /* Read the portion that overlaps the FPR registers. */
2672 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2674 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2676 if (status
== REG_VALID
)
2677 status
= regcache
->raw_read (tdep
->ppc_vsr0_upper_regnum
+
2678 reg_index
, buffer
+ 8);
2682 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2683 reg_index
, buffer
+ 8);
2684 if (status
== REG_VALID
)
2685 status
= regcache
->raw_read (tdep
->ppc_vsr0_upper_regnum
+
2692 /* Write method for POWER7 VSX pseudo-registers. */
2694 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2695 int reg_nr
, const gdb_byte
*buffer
)
2697 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2698 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2700 /* Write the portion that overlaps the VMX registers. */
2702 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2703 reg_index
- 32, buffer
);
2705 /* Write the portion that overlaps the FPR registers. */
2706 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2708 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2710 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2711 reg_index
, buffer
+ 8);
2715 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2716 reg_index
, buffer
+ 8);
2717 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2722 /* Read method for POWER7 Extended FP pseudo-registers. */
2723 static enum register_status
2724 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2725 int reg_nr
, gdb_byte
*buffer
)
2727 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2728 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2729 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2731 /* Read the portion that overlaps the VMX register. */
2732 return regcache
->raw_read_part (tdep
->ppc_vr0_regnum
+ reg_index
,
2733 offset
, register_size (gdbarch
, reg_nr
),
2737 /* Write method for POWER7 Extended FP pseudo-registers. */
2739 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2740 int reg_nr
, const gdb_byte
*buffer
)
2742 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2743 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2744 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2746 /* Write the portion that overlaps the VMX register. */
2747 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2748 offset
, register_size (gdbarch
, reg_nr
),
2752 static enum register_status
2753 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2754 readable_regcache
*regcache
,
2755 int reg_nr
, gdb_byte
*buffer
)
2757 struct gdbarch
*regcache_arch
= regcache
->arch ();
2758 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2760 gdb_assert (regcache_arch
== gdbarch
);
2762 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2763 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2764 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2765 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2766 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2767 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2768 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2769 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2771 internal_error (__FILE__
, __LINE__
,
2772 _("rs6000_pseudo_register_read: "
2773 "called on unexpected register '%s' (%d)"),
2774 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2778 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2779 struct regcache
*regcache
,
2780 int reg_nr
, const gdb_byte
*buffer
)
2782 struct gdbarch
*regcache_arch
= regcache
->arch ();
2783 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2785 gdb_assert (regcache_arch
== gdbarch
);
2787 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2788 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2789 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2790 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2791 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2792 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2793 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2794 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2796 internal_error (__FILE__
, __LINE__
,
2797 _("rs6000_pseudo_register_write: "
2798 "called on unexpected register '%s' (%d)"),
2799 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2803 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2804 struct agent_expr
*ax
, int reg_nr
)
2806 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2807 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2809 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
2810 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
2811 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
2813 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2815 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2816 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
);
2817 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
+ 1);
2819 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2821 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2824 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
- 32);
2828 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ reg_index
);
2829 ax_reg_mask (ax
, tdep
->ppc_vsr0_upper_regnum
+ reg_index
);
2832 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2834 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2835 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
);
2838 internal_error (__FILE__
, __LINE__
,
2839 _("rs6000_pseudo_register_collect: "
2840 "called on unexpected register '%s' (%d)"),
2841 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2847 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
2848 struct agent_expr
*ax
, struct axs_value
*value
,
2851 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2852 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
2853 value
->kind
= axs_lvalue_register
;
2854 value
->u
.reg
= tdep
->ppc_lr_regnum
;
2858 /* Convert a DBX STABS register number to a GDB register number. */
2860 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2862 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2864 if (0 <= num
&& num
<= 31)
2865 return tdep
->ppc_gp0_regnum
+ num
;
2866 else if (32 <= num
&& num
<= 63)
2867 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2868 specifies registers the architecture doesn't have? Our
2869 callers don't check the value we return. */
2870 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2871 else if (77 <= num
&& num
<= 108)
2872 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2873 else if (1200 <= num
&& num
< 1200 + 32)
2874 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2879 return tdep
->ppc_mq_regnum
;
2881 return tdep
->ppc_lr_regnum
;
2883 return tdep
->ppc_ctr_regnum
;
2885 return tdep
->ppc_xer_regnum
;
2887 return tdep
->ppc_vrsave_regnum
;
2889 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2891 return tdep
->ppc_acc_regnum
;
2893 return tdep
->ppc_spefscr_regnum
;
2900 /* Convert a Dwarf 2 register number to a GDB register number. */
2902 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2904 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2906 if (0 <= num
&& num
<= 31)
2907 return tdep
->ppc_gp0_regnum
+ num
;
2908 else if (32 <= num
&& num
<= 63)
2909 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2910 specifies registers the architecture doesn't have? Our
2911 callers don't check the value we return. */
2912 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2913 else if (1124 <= num
&& num
< 1124 + 32)
2914 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2915 else if (1200 <= num
&& num
< 1200 + 32)
2916 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2921 return tdep
->ppc_cr_regnum
;
2923 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2925 return tdep
->ppc_acc_regnum
;
2927 return tdep
->ppc_mq_regnum
;
2929 return tdep
->ppc_xer_regnum
;
2931 return tdep
->ppc_lr_regnum
;
2933 return tdep
->ppc_ctr_regnum
;
2935 return tdep
->ppc_vrsave_regnum
;
2937 return tdep
->ppc_spefscr_regnum
;
2943 /* Translate a .eh_frame register to DWARF register, or adjust a
2944 .debug_frame register. */
2947 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2949 /* GCC releases before 3.4 use GCC internal register numbering in
2950 .debug_frame (and .debug_info, et cetera). The numbering is
2951 different from the standard SysV numbering for everything except
2952 for GPRs and FPRs. We can not detect this problem in most cases
2953 - to get accurate debug info for variables living in lr, ctr, v0,
2954 et cetera, use a newer version of GCC. But we must detect
2955 one important case - lr is in column 65 in .debug_frame output,
2958 GCC 3.4, and the "hammer" branch, have a related problem. They
2959 record lr register saves in .debug_frame as 108, but still record
2960 the return column as 65. We fix that up too.
2962 We can do this because 65 is assigned to fpsr, and GCC never
2963 generates debug info referring to it. To add support for
2964 handwritten debug info that restores fpsr, we would need to add a
2965 producer version check to this. */
2974 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2975 internal register numbering; translate that to the standard DWARF2
2976 register numbering. */
2977 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2979 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2980 return num
- 68 + 86;
2981 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2982 return num
- 77 + 1124;
2994 case 109: /* vrsave */
2996 case 110: /* vscr */
2998 case 111: /* spe_acc */
3000 case 112: /* spefscr */
3008 /* Handling the various POWER/PowerPC variants. */
3010 /* Information about a particular processor variant. */
3014 /* Name of this variant. */
3017 /* English description of the variant. */
3018 const char *description
;
3020 /* bfd_arch_info.arch corresponding to variant. */
3021 enum bfd_architecture arch
;
3023 /* bfd_arch_info.mach corresponding to variant. */
3026 /* Target description for this variant. */
3027 struct target_desc
**tdesc
;
3030 static struct variant variants
[] =
3032 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3033 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3034 {"power", "POWER user-level", bfd_arch_rs6000
,
3035 bfd_mach_rs6k
, &tdesc_rs6000
},
3036 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3037 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3038 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3039 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3040 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3041 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3042 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3043 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3044 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3045 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3046 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3047 604, &tdesc_powerpc_604
},
3048 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3049 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3050 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3051 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3052 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3053 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3054 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3055 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3056 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3057 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3058 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3059 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3062 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3063 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3064 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3065 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3066 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3067 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3068 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3069 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3070 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3071 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3072 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3073 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3075 /* FIXME: I haven't checked the register sets of the following. */
3076 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3077 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3078 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3079 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3080 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3081 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3083 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3086 /* Return the variant corresponding to architecture ARCH and machine number
3087 MACH. If no such variant exists, return null. */
3089 static const struct variant
*
3090 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3092 const struct variant
*v
;
3094 for (v
= variants
; v
->name
; v
++)
3095 if (arch
== v
->arch
&& mach
== v
->mach
)
3103 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3105 return frame_unwind_register_unsigned (next_frame
,
3106 gdbarch_pc_regnum (gdbarch
));
3109 static struct frame_id
3110 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3112 return frame_id_build (get_frame_register_unsigned
3113 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3114 get_frame_pc (this_frame
));
3117 struct rs6000_frame_cache
3120 CORE_ADDR initial_sp
;
3121 struct trad_frame_saved_reg
*saved_regs
;
3123 /* Set BASE_P to true if this frame cache is properly initialized.
3124 Otherwise set to false because some registers or memory cannot
3127 /* Cache PC for building unavailable frame. */
3131 static struct rs6000_frame_cache
*
3132 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3134 struct rs6000_frame_cache
*cache
;
3135 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3137 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3138 struct rs6000_framedata fdata
;
3139 int wordsize
= tdep
->wordsize
;
3140 CORE_ADDR func
= 0, pc
= 0;
3142 if ((*this_cache
) != NULL
)
3143 return (struct rs6000_frame_cache
*) (*this_cache
);
3144 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3145 (*this_cache
) = cache
;
3147 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3151 func
= get_frame_func (this_frame
);
3153 pc
= get_frame_pc (this_frame
);
3154 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3156 /* Figure out the parent's stack pointer. */
3158 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3159 address of the current frame. Things might be easier if the
3160 ->frame pointed to the outer-most address of the frame. In
3161 the mean time, the address of the prev frame is used as the
3162 base address of this frame. */
3163 cache
->base
= get_frame_register_unsigned
3164 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3166 CATCH (ex
, RETURN_MASK_ERROR
)
3168 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3169 throw_exception (ex
);
3170 return (struct rs6000_frame_cache
*) (*this_cache
);
3174 /* If the function appears to be frameless, check a couple of likely
3175 indicators that we have simply failed to find the frame setup.
3176 Two common cases of this are missing symbols (i.e.
3177 get_frame_func returns the wrong address or 0), and assembly
3178 stubs which have a fast exit path but set up a frame on the slow
3181 If the LR appears to return to this function, then presume that
3182 we have an ABI compliant frame that we failed to find. */
3183 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3188 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3189 if (func
== 0 && saved_lr
== pc
)
3193 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3194 if (func
== saved_func
)
3200 fdata
.frameless
= 0;
3201 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3205 if (!fdata
.frameless
)
3207 /* Frameless really means stackless. */
3210 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3211 byte_order
, &backchain
))
3212 cache
->base
= (CORE_ADDR
) backchain
;
3215 trad_frame_set_value (cache
->saved_regs
,
3216 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3218 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3219 All fpr's from saved_fpr to fp31 are saved. */
3221 if (fdata
.saved_fpr
>= 0)
3224 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3226 /* If skip_prologue says floating-point registers were saved,
3227 but the current architecture has no floating-point registers,
3228 then that's strange. But we have no indices to even record
3229 the addresses under, so we just ignore it. */
3230 if (ppc_floating_point_unit_p (gdbarch
))
3231 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3233 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3238 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3239 All gpr's from saved_gpr to gpr31 are saved (except during the
3242 if (fdata
.saved_gpr
>= 0)
3245 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3246 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3248 if (fdata
.gpr_mask
& (1U << i
))
3249 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3250 gpr_addr
+= wordsize
;
3254 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3255 All vr's from saved_vr to vr31 are saved. */
3256 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3258 if (fdata
.saved_vr
>= 0)
3261 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3262 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3264 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3265 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3270 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3271 All vr's from saved_ev to ev31 are saved. ????? */
3272 if (tdep
->ppc_ev0_regnum
!= -1)
3274 if (fdata
.saved_ev
>= 0)
3277 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3278 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3280 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3282 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3283 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3284 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3289 /* If != 0, fdata.cr_offset is the offset from the frame that
3291 if (fdata
.cr_offset
!= 0)
3292 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3293 = cache
->base
+ fdata
.cr_offset
;
3295 /* If != 0, fdata.lr_offset is the offset from the frame that
3297 if (fdata
.lr_offset
!= 0)
3298 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3299 = cache
->base
+ fdata
.lr_offset
;
3300 else if (fdata
.lr_register
!= -1)
3301 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3302 /* The PC is found in the link register. */
3303 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3304 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3306 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3307 holds the VRSAVE. */
3308 if (fdata
.vrsave_offset
!= 0)
3309 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3310 = cache
->base
+ fdata
.vrsave_offset
;
3312 if (fdata
.alloca_reg
< 0)
3313 /* If no alloca register used, then fi->frame is the value of the
3314 %sp for this frame, and it is good enough. */
3316 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3319 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3326 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3327 struct frame_id
*this_id
)
3329 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3334 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3338 /* This marks the outermost frame. */
3339 if (info
->base
== 0)
3342 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3345 static struct value
*
3346 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3347 void **this_cache
, int regnum
)
3349 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3351 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3354 static const struct frame_unwind rs6000_frame_unwind
=
3357 default_frame_unwind_stop_reason
,
3358 rs6000_frame_this_id
,
3359 rs6000_frame_prev_register
,
3361 default_frame_sniffer
3364 /* Allocate and initialize a frame cache for an epilogue frame.
3365 SP is restored and prev-PC is stored in LR. */
3367 static struct rs6000_frame_cache
*
3368 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3370 struct rs6000_frame_cache
*cache
;
3371 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3372 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3375 return (struct rs6000_frame_cache
*) *this_cache
;
3377 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3378 (*this_cache
) = cache
;
3379 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3383 /* At this point the stack looks as if we just entered the
3384 function, and the return address is stored in LR. */
3387 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3388 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3391 cache
->initial_sp
= sp
;
3393 trad_frame_set_value (cache
->saved_regs
,
3394 gdbarch_pc_regnum (gdbarch
), lr
);
3396 CATCH (ex
, RETURN_MASK_ERROR
)
3398 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3399 throw_exception (ex
);
3406 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3407 Return the frame ID of an epilogue frame. */
3410 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3411 void **this_cache
, struct frame_id
*this_id
)
3414 struct rs6000_frame_cache
*info
=
3415 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3417 pc
= get_frame_func (this_frame
);
3418 if (info
->base
== 0)
3419 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3421 (*this_id
) = frame_id_build (info
->base
, pc
);
3424 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3425 Return the register value of REGNUM in previous frame. */
3427 static struct value
*
3428 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3429 void **this_cache
, int regnum
)
3431 struct rs6000_frame_cache
*info
=
3432 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3433 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3436 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3437 Check whether this an epilogue frame. */
3440 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3441 struct frame_info
*this_frame
,
3442 void **this_prologue_cache
)
3444 if (frame_relative_level (this_frame
) == 0)
3445 return rs6000_in_function_epilogue_frame_p (this_frame
,
3446 get_frame_arch (this_frame
),
3447 get_frame_pc (this_frame
));
3452 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3453 a function without debug information. */
3455 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3458 default_frame_unwind_stop_reason
,
3459 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3461 rs6000_epilogue_frame_sniffer
3466 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3468 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3470 return info
->initial_sp
;
3473 static const struct frame_base rs6000_frame_base
= {
3474 &rs6000_frame_unwind
,
3475 rs6000_frame_base_address
,
3476 rs6000_frame_base_address
,
3477 rs6000_frame_base_address
3480 static const struct frame_base
*
3481 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3483 return &rs6000_frame_base
;
3486 /* DWARF-2 frame support. Used to handle the detection of
3487 clobbered registers during function calls. */
3490 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3491 struct dwarf2_frame_state_reg
*reg
,
3492 struct frame_info
*this_frame
)
3494 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3496 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3497 non-volatile registers. We will use the same code for both. */
3499 /* Call-saved GP registers. */
3500 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3501 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3502 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3503 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3505 /* Call-clobbered GP registers. */
3506 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3507 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3508 || (regnum
== tdep
->ppc_gp0_regnum
))
3509 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3511 /* Deal with FP registers, if supported. */
3512 if (tdep
->ppc_fp0_regnum
>= 0)
3514 /* Call-saved FP registers. */
3515 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3516 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3517 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3519 /* Call-clobbered FP registers. */
3520 if ((regnum
>= tdep
->ppc_fp0_regnum
3521 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3522 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3525 /* Deal with ALTIVEC registers, if supported. */
3526 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3528 /* Call-saved Altivec registers. */
3529 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3530 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3531 || regnum
== tdep
->ppc_vrsave_regnum
)
3532 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3534 /* Call-clobbered Altivec registers. */
3535 if ((regnum
>= tdep
->ppc_vr0_regnum
3536 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3537 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3540 /* Handle PC register and Stack Pointer correctly. */
3541 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3542 reg
->how
= DWARF2_FRAME_REG_RA
;
3543 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3544 reg
->how
= DWARF2_FRAME_REG_CFA
;
3548 /* Return true if a .gnu_attributes section exists in BFD and it
3549 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3550 section exists in BFD and it indicates that SPE extensions are in
3551 use. Check the .gnu.attributes section first, as the binary might be
3552 compiled for SPE, but not actually using SPE instructions. */
3555 bfd_uses_spe_extensions (bfd
*abfd
)
3558 gdb_byte
*contents
= NULL
;
3568 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3569 could be using the SPE vector abi without actually using any spe
3570 bits whatsoever. But it's close enough for now. */
3571 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3572 Tag_GNU_Power_ABI_Vector
);
3573 if (vector_abi
== 3)
3577 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3581 size
= bfd_get_section_size (sect
);
3582 contents
= (gdb_byte
*) xmalloc (size
);
3583 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3589 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3595 char name[name_len rounded up to 4-byte alignment];
3596 char data[data_len];
3599 Technically, there's only supposed to be one such structure in a
3600 given apuinfo section, but the linker is not always vigilant about
3601 merging apuinfo sections from input files. Just go ahead and parse
3602 them all, exiting early when we discover the binary uses SPE
3605 It's not specified in what endianness the information in this
3606 section is stored. Assume that it's the endianness of the BFD. */
3610 unsigned int name_len
;
3611 unsigned int data_len
;
3614 /* If we can't read the first three fields, we're done. */
3618 name_len
= bfd_get_32 (abfd
, ptr
);
3619 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3620 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3621 type
= bfd_get_32 (abfd
, ptr
+ 8);
3624 /* The name must be "APUinfo\0". */
3626 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3630 /* The type must be 2. */
3634 /* The data is stored as a series of uint32. The upper half of
3635 each uint32 indicates the particular APU used and the lower
3636 half indicates the revision of that APU. We just care about
3639 /* Not 4-byte quantities. */
3645 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3646 unsigned int apu
= apuinfo
>> 16;
3650 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3652 if (apu
== 0x100 || apu
== 0x101)
3667 /* These are macros for parsing instruction fields (I.1.6.28) */
3669 #define PPC_FIELD(value, from, len) \
3670 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3671 #define PPC_SEXT(v, bs) \
3672 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3673 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3674 - ((CORE_ADDR) 1 << ((bs) - 1)))
3675 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3676 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3677 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3678 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3679 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3680 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3681 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3682 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3683 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3684 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3685 | (PPC_FIELD (insn, 16, 5) << 5))
3686 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3687 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3688 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3689 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3690 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3691 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3692 #define PPC_OE(insn) PPC_BIT (insn, 21)
3693 #define PPC_RC(insn) PPC_BIT (insn, 31)
3694 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3695 #define PPC_LK(insn) PPC_BIT (insn, 31)
3696 #define PPC_TX(insn) PPC_BIT (insn, 31)
3697 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3699 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3700 #define PPC_XER_NB(xer) (xer & 0x7f)
3702 /* Record Vector-Scalar Registers.
3703 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3704 Otherwise, it's just a VR register. Record them accordingly. */
3707 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3709 if (vsr
< 0 || vsr
>= 64)
3714 if (tdep
->ppc_vr0_regnum
>= 0)
3715 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3719 if (tdep
->ppc_fp0_regnum
>= 0)
3720 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3721 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3722 record_full_arch_list_add_reg (regcache
,
3723 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3729 /* Parse and record instructions primary opcode-4 at ADDR.
3730 Return 0 if successful. */
3733 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3734 CORE_ADDR addr
, uint32_t insn
)
3736 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3737 int ext
= PPC_FIELD (insn
, 21, 11);
3738 int vra
= PPC_FIELD (insn
, 11, 5);
3742 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3743 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3744 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3745 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3746 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3748 case 42: /* Vector Select */
3749 case 43: /* Vector Permute */
3750 case 59: /* Vector Permute Right-indexed */
3751 case 44: /* Vector Shift Left Double by Octet Immediate */
3752 case 45: /* Vector Permute and Exclusive-OR */
3753 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3754 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3755 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3756 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3757 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3758 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3759 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3760 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3761 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3762 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3763 case 46: /* Vector Multiply-Add Single-Precision */
3764 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3765 record_full_arch_list_add_reg (regcache
,
3766 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3769 case 48: /* Multiply-Add High Doubleword */
3770 case 49: /* Multiply-Add High Doubleword Unsigned */
3771 case 51: /* Multiply-Add Low Doubleword */
3772 record_full_arch_list_add_reg (regcache
,
3773 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3777 switch ((ext
& 0x1ff))
3780 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
3781 && vra
!= 2 /* Decimal Convert From Signed Quadword */
3782 && vra
!= 4 /* Decimal Convert To Zoned */
3783 && vra
!= 5 /* Decimal Convert To National */
3784 && vra
!= 6 /* Decimal Convert From Zoned */
3785 && vra
!= 7 /* Decimal Convert From National */
3786 && vra
!= 31) /* Decimal Set Sign */
3789 /* 5.16 Decimal Integer Arithmetic Instructions */
3790 case 1: /* Decimal Add Modulo */
3791 case 65: /* Decimal Subtract Modulo */
3793 case 193: /* Decimal Shift */
3794 case 129: /* Decimal Unsigned Shift */
3795 case 449: /* Decimal Shift and Round */
3797 case 257: /* Decimal Truncate */
3798 case 321: /* Decimal Unsigned Truncate */
3800 /* Bit-21 should be set. */
3801 if (!PPC_BIT (insn
, 21))
3804 record_full_arch_list_add_reg (regcache
,
3805 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3806 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3810 /* Bit-21 is used for RC */
3811 switch (ext
& 0x3ff)
3813 case 6: /* Vector Compare Equal To Unsigned Byte */
3814 case 70: /* Vector Compare Equal To Unsigned Halfword */
3815 case 134: /* Vector Compare Equal To Unsigned Word */
3816 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3817 case 774: /* Vector Compare Greater Than Signed Byte */
3818 case 838: /* Vector Compare Greater Than Signed Halfword */
3819 case 902: /* Vector Compare Greater Than Signed Word */
3820 case 967: /* Vector Compare Greater Than Signed Doubleword */
3821 case 518: /* Vector Compare Greater Than Unsigned Byte */
3822 case 646: /* Vector Compare Greater Than Unsigned Word */
3823 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3824 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3825 case 966: /* Vector Compare Bounds Single-Precision */
3826 case 198: /* Vector Compare Equal To Single-Precision */
3827 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3828 case 710: /* Vector Compare Greater Than Single-Precision */
3829 case 7: /* Vector Compare Not Equal Byte */
3830 case 71: /* Vector Compare Not Equal Halfword */
3831 case 135: /* Vector Compare Not Equal Word */
3832 case 263: /* Vector Compare Not Equal or Zero Byte */
3833 case 327: /* Vector Compare Not Equal or Zero Halfword */
3834 case 391: /* Vector Compare Not Equal or Zero Word */
3836 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3837 record_full_arch_list_add_reg (regcache
,
3838 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3846 case 0: /* Vector Count Leading Zero Least-Significant Bits
3848 case 1: /* Vector Count Trailing Zero Least-Significant Bits
3850 record_full_arch_list_add_reg (regcache
,
3851 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3854 case 6: /* Vector Negate Word */
3855 case 7: /* Vector Negate Doubleword */
3856 case 8: /* Vector Parity Byte Word */
3857 case 9: /* Vector Parity Byte Doubleword */
3858 case 10: /* Vector Parity Byte Quadword */
3859 case 16: /* Vector Extend Sign Byte To Word */
3860 case 17: /* Vector Extend Sign Halfword To Word */
3861 case 24: /* Vector Extend Sign Byte To Doubleword */
3862 case 25: /* Vector Extend Sign Halfword To Doubleword */
3863 case 26: /* Vector Extend Sign Word To Doubleword */
3864 case 28: /* Vector Count Trailing Zeros Byte */
3865 case 29: /* Vector Count Trailing Zeros Halfword */
3866 case 30: /* Vector Count Trailing Zeros Word */
3867 case 31: /* Vector Count Trailing Zeros Doubleword */
3868 record_full_arch_list_add_reg (regcache
,
3869 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3876 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
3877 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
3878 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
3879 case 334: /* Vector Pack Signed Word Unsigned Saturate */
3880 case 398: /* Vector Pack Signed Halfword Signed Saturate */
3881 case 462: /* Vector Pack Signed Word Signed Saturate */
3882 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
3883 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
3884 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
3885 case 512: /* Vector Add Unsigned Byte Saturate */
3886 case 576: /* Vector Add Unsigned Halfword Saturate */
3887 case 640: /* Vector Add Unsigned Word Saturate */
3888 case 768: /* Vector Add Signed Byte Saturate */
3889 case 832: /* Vector Add Signed Halfword Saturate */
3890 case 896: /* Vector Add Signed Word Saturate */
3891 case 1536: /* Vector Subtract Unsigned Byte Saturate */
3892 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
3893 case 1664: /* Vector Subtract Unsigned Word Saturate */
3894 case 1792: /* Vector Subtract Signed Byte Saturate */
3895 case 1856: /* Vector Subtract Signed Halfword Saturate */
3896 case 1920: /* Vector Subtract Signed Word Saturate */
3898 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
3899 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
3900 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
3901 case 1672: /* Vector Sum across Half Signed Word Saturate */
3902 case 1928: /* Vector Sum across Signed Word Saturate */
3903 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
3904 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
3905 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3907 case 12: /* Vector Merge High Byte */
3908 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
3909 case 76: /* Vector Merge High Halfword */
3910 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
3911 case 140: /* Vector Merge High Word */
3912 case 268: /* Vector Merge Low Byte */
3913 case 332: /* Vector Merge Low Halfword */
3914 case 396: /* Vector Merge Low Word */
3915 case 526: /* Vector Unpack High Signed Byte */
3916 case 590: /* Vector Unpack High Signed Halfword */
3917 case 654: /* Vector Unpack Low Signed Byte */
3918 case 718: /* Vector Unpack Low Signed Halfword */
3919 case 782: /* Vector Pack Pixel */
3920 case 846: /* Vector Unpack High Pixel */
3921 case 974: /* Vector Unpack Low Pixel */
3922 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
3923 case 1614: /* Vector Unpack High Signed Word */
3924 case 1676: /* Vector Merge Odd Word */
3925 case 1742: /* Vector Unpack Low Signed Word */
3926 case 1932: /* Vector Merge Even Word */
3927 case 524: /* Vector Splat Byte */
3928 case 588: /* Vector Splat Halfword */
3929 case 652: /* Vector Splat Word */
3930 case 780: /* Vector Splat Immediate Signed Byte */
3931 case 844: /* Vector Splat Immediate Signed Halfword */
3932 case 908: /* Vector Splat Immediate Signed Word */
3933 case 452: /* Vector Shift Left */
3934 case 708: /* Vector Shift Right */
3935 case 1036: /* Vector Shift Left by Octet */
3936 case 1100: /* Vector Shift Right by Octet */
3937 case 0: /* Vector Add Unsigned Byte Modulo */
3938 case 64: /* Vector Add Unsigned Halfword Modulo */
3939 case 128: /* Vector Add Unsigned Word Modulo */
3940 case 192: /* Vector Add Unsigned Doubleword Modulo */
3941 case 256: /* Vector Add Unsigned Quadword Modulo */
3942 case 320: /* Vector Add & write Carry Unsigned Quadword */
3943 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
3944 case 8: /* Vector Multiply Odd Unsigned Byte */
3945 case 72: /* Vector Multiply Odd Unsigned Halfword */
3946 case 136: /* Vector Multiply Odd Unsigned Word */
3947 case 264: /* Vector Multiply Odd Signed Byte */
3948 case 328: /* Vector Multiply Odd Signed Halfword */
3949 case 392: /* Vector Multiply Odd Signed Word */
3950 case 520: /* Vector Multiply Even Unsigned Byte */
3951 case 584: /* Vector Multiply Even Unsigned Halfword */
3952 case 648: /* Vector Multiply Even Unsigned Word */
3953 case 776: /* Vector Multiply Even Signed Byte */
3954 case 840: /* Vector Multiply Even Signed Halfword */
3955 case 904: /* Vector Multiply Even Signed Word */
3956 case 137: /* Vector Multiply Unsigned Word Modulo */
3957 case 1024: /* Vector Subtract Unsigned Byte Modulo */
3958 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
3959 case 1152: /* Vector Subtract Unsigned Word Modulo */
3960 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
3961 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
3962 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
3963 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
3964 case 1282: /* Vector Average Signed Byte */
3965 case 1346: /* Vector Average Signed Halfword */
3966 case 1410: /* Vector Average Signed Word */
3967 case 1026: /* Vector Average Unsigned Byte */
3968 case 1090: /* Vector Average Unsigned Halfword */
3969 case 1154: /* Vector Average Unsigned Word */
3970 case 258: /* Vector Maximum Signed Byte */
3971 case 322: /* Vector Maximum Signed Halfword */
3972 case 386: /* Vector Maximum Signed Word */
3973 case 450: /* Vector Maximum Signed Doubleword */
3974 case 2: /* Vector Maximum Unsigned Byte */
3975 case 66: /* Vector Maximum Unsigned Halfword */
3976 case 130: /* Vector Maximum Unsigned Word */
3977 case 194: /* Vector Maximum Unsigned Doubleword */
3978 case 770: /* Vector Minimum Signed Byte */
3979 case 834: /* Vector Minimum Signed Halfword */
3980 case 898: /* Vector Minimum Signed Word */
3981 case 962: /* Vector Minimum Signed Doubleword */
3982 case 514: /* Vector Minimum Unsigned Byte */
3983 case 578: /* Vector Minimum Unsigned Halfword */
3984 case 642: /* Vector Minimum Unsigned Word */
3985 case 706: /* Vector Minimum Unsigned Doubleword */
3986 case 1028: /* Vector Logical AND */
3987 case 1668: /* Vector Logical Equivalent */
3988 case 1092: /* Vector Logical AND with Complement */
3989 case 1412: /* Vector Logical NAND */
3990 case 1348: /* Vector Logical OR with Complement */
3991 case 1156: /* Vector Logical OR */
3992 case 1284: /* Vector Logical NOR */
3993 case 1220: /* Vector Logical XOR */
3994 case 4: /* Vector Rotate Left Byte */
3995 case 132: /* Vector Rotate Left Word VX-form */
3996 case 68: /* Vector Rotate Left Halfword */
3997 case 196: /* Vector Rotate Left Doubleword */
3998 case 260: /* Vector Shift Left Byte */
3999 case 388: /* Vector Shift Left Word */
4000 case 324: /* Vector Shift Left Halfword */
4001 case 1476: /* Vector Shift Left Doubleword */
4002 case 516: /* Vector Shift Right Byte */
4003 case 644: /* Vector Shift Right Word */
4004 case 580: /* Vector Shift Right Halfword */
4005 case 1732: /* Vector Shift Right Doubleword */
4006 case 772: /* Vector Shift Right Algebraic Byte */
4007 case 900: /* Vector Shift Right Algebraic Word */
4008 case 836: /* Vector Shift Right Algebraic Halfword */
4009 case 964: /* Vector Shift Right Algebraic Doubleword */
4010 case 10: /* Vector Add Single-Precision */
4011 case 74: /* Vector Subtract Single-Precision */
4012 case 1034: /* Vector Maximum Single-Precision */
4013 case 1098: /* Vector Minimum Single-Precision */
4014 case 842: /* Vector Convert From Signed Fixed-Point Word */
4015 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4016 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4017 case 522: /* Vector Round to Single-Precision Integer Nearest */
4018 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4019 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4020 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4021 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4022 case 266: /* Vector Reciprocal Estimate Single-Precision */
4023 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4024 case 1288: /* Vector AES Cipher */
4025 case 1289: /* Vector AES Cipher Last */
4026 case 1352: /* Vector AES Inverse Cipher */
4027 case 1353: /* Vector AES Inverse Cipher Last */
4028 case 1480: /* Vector AES SubBytes */
4029 case 1730: /* Vector SHA-512 Sigma Doubleword */
4030 case 1666: /* Vector SHA-256 Sigma Word */
4031 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4032 case 1160: /* Vector Polynomial Multiply-Sum Word */
4033 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4034 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4035 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4036 case 1794: /* Vector Count Leading Zeros Byte */
4037 case 1858: /* Vector Count Leading Zeros Halfword */
4038 case 1922: /* Vector Count Leading Zeros Word */
4039 case 1986: /* Vector Count Leading Zeros Doubleword */
4040 case 1795: /* Vector Population Count Byte */
4041 case 1859: /* Vector Population Count Halfword */
4042 case 1923: /* Vector Population Count Word */
4043 case 1987: /* Vector Population Count Doubleword */
4044 case 1356: /* Vector Bit Permute Quadword */
4045 case 1484: /* Vector Bit Permute Doubleword */
4046 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4047 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4049 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4050 case 65: /* Vector Multiply-by-10 Extended & write Carry
4051 Unsigned Quadword */
4052 case 1027: /* Vector Absolute Difference Unsigned Byte */
4053 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4054 case 1155: /* Vector Absolute Difference Unsigned Word */
4055 case 1796: /* Vector Shift Right Variable */
4056 case 1860: /* Vector Shift Left Variable */
4057 case 133: /* Vector Rotate Left Word then Mask Insert */
4058 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4059 case 389: /* Vector Rotate Left Word then AND with Mask */
4060 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4061 case 525: /* Vector Extract Unsigned Byte */
4062 case 589: /* Vector Extract Unsigned Halfword */
4063 case 653: /* Vector Extract Unsigned Word */
4064 case 717: /* Vector Extract Doubleword */
4065 case 781: /* Vector Insert Byte */
4066 case 845: /* Vector Insert Halfword */
4067 case 909: /* Vector Insert Word */
4068 case 973: /* Vector Insert Doubleword */
4069 record_full_arch_list_add_reg (regcache
,
4070 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4073 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4074 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4075 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4076 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4077 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4078 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4079 record_full_arch_list_add_reg (regcache
,
4080 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4083 case 1604: /* Move To Vector Status and Control Register */
4084 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4086 case 1540: /* Move From Vector Status and Control Register */
4087 record_full_arch_list_add_reg (regcache
,
4088 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4090 case 833: /* Decimal Copy Sign */
4091 record_full_arch_list_add_reg (regcache
,
4092 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4093 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4097 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4098 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4102 /* Parse and record instructions of primary opcode-19 at ADDR.
4103 Return 0 if successful. */
4106 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4107 CORE_ADDR addr
, uint32_t insn
)
4109 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4110 int ext
= PPC_EXTOP (insn
);
4112 switch (ext
& 0x01f)
4114 case 2: /* Add PC Immediate Shifted */
4115 record_full_arch_list_add_reg (regcache
,
4116 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4122 case 0: /* Move Condition Register Field */
4123 case 33: /* Condition Register NOR */
4124 case 129: /* Condition Register AND with Complement */
4125 case 193: /* Condition Register XOR */
4126 case 225: /* Condition Register NAND */
4127 case 257: /* Condition Register AND */
4128 case 289: /* Condition Register Equivalent */
4129 case 417: /* Condition Register OR with Complement */
4130 case 449: /* Condition Register OR */
4131 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4134 case 16: /* Branch Conditional */
4135 case 560: /* Branch Conditional to Branch Target Address Register */
4136 if ((PPC_BO (insn
) & 0x4) == 0)
4137 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4139 case 528: /* Branch Conditional to Count Register */
4141 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4144 case 150: /* Instruction Synchronize */
4149 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4150 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4154 /* Parse and record instructions of primary opcode-31 at ADDR.
4155 Return 0 if successful. */
4158 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4159 CORE_ADDR addr
, uint32_t insn
)
4161 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4162 int ext
= PPC_EXTOP (insn
);
4164 CORE_ADDR at_dcsz
, ea
= 0;
4165 ULONGEST rb
, ra
, xer
;
4168 /* These instructions have OE bit. */
4169 switch (ext
& 0x1ff)
4171 /* These write RT and XER. Update CR if RC is set. */
4172 case 8: /* Subtract from carrying */
4173 case 10: /* Add carrying */
4174 case 136: /* Subtract from extended */
4175 case 138: /* Add extended */
4176 case 200: /* Subtract from zero extended */
4177 case 202: /* Add to zero extended */
4178 case 232: /* Subtract from minus one extended */
4179 case 234: /* Add to minus one extended */
4180 /* CA is always altered, but SO/OV are only altered when OE=1.
4181 In any case, XER is always altered. */
4182 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4184 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4185 record_full_arch_list_add_reg (regcache
,
4186 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4189 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4190 case 40: /* Subtract from */
4191 case 104: /* Negate */
4192 case 233: /* Multiply low doubleword */
4193 case 235: /* Multiply low word */
4195 case 393: /* Divide Doubleword Extended Unsigned */
4196 case 395: /* Divide Word Extended Unsigned */
4197 case 425: /* Divide Doubleword Extended */
4198 case 427: /* Divide Word Extended */
4199 case 457: /* Divide Doubleword Unsigned */
4200 case 459: /* Divide Word Unsigned */
4201 case 489: /* Divide Doubleword */
4202 case 491: /* Divide Word */
4204 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4206 case 9: /* Multiply High Doubleword Unsigned */
4207 case 11: /* Multiply High Word Unsigned */
4208 case 73: /* Multiply High Doubleword */
4209 case 75: /* Multiply High Word */
4211 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4212 record_full_arch_list_add_reg (regcache
,
4213 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4217 if ((ext
& 0x1f) == 15)
4219 /* Integer Select. bit[16:20] is used for BC. */
4220 record_full_arch_list_add_reg (regcache
,
4221 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4225 if ((ext
& 0xff) == 170)
4227 /* Add Extended using alternate carry bits */
4228 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4229 record_full_arch_list_add_reg (regcache
,
4230 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4236 case 78: /* Determine Leftmost Zero Byte */
4238 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4239 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4240 record_full_arch_list_add_reg (regcache
,
4241 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4244 /* These only write RT. */
4245 case 19: /* Move from condition register */
4246 /* Move From One Condition Register Field */
4247 case 74: /* Add and Generate Sixes */
4248 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4249 case 302: /* Move From Branch History Rolling Buffer */
4250 case 339: /* Move From Special Purpose Register */
4251 case 371: /* Move From Time Base [Phased-Out] */
4252 case 309: /* Load Doubleword Monitored Indexed */
4253 case 128: /* Set Boolean */
4254 case 755: /* Deliver A Random Number */
4255 record_full_arch_list_add_reg (regcache
,
4256 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4259 /* These only write to RA. */
4260 case 51: /* Move From VSR Doubleword */
4261 case 115: /* Move From VSR Word and Zero */
4262 case 122: /* Population count bytes */
4263 case 378: /* Population count words */
4264 case 506: /* Population count doublewords */
4265 case 154: /* Parity Word */
4266 case 186: /* Parity Doubleword */
4267 case 252: /* Bit Permute Doubleword */
4268 case 282: /* Convert Declets To Binary Coded Decimal */
4269 case 314: /* Convert Binary Coded Decimal To Declets */
4270 case 508: /* Compare bytes */
4271 case 307: /* Move From VSR Lower Doubleword */
4272 record_full_arch_list_add_reg (regcache
,
4273 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4276 /* These write CR and optional RA. */
4277 case 792: /* Shift Right Algebraic Word */
4278 case 794: /* Shift Right Algebraic Doubleword */
4279 case 824: /* Shift Right Algebraic Word Immediate */
4280 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4281 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4282 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4283 record_full_arch_list_add_reg (regcache
,
4284 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4286 case 0: /* Compare */
4287 case 32: /* Compare logical */
4288 case 144: /* Move To Condition Register Fields */
4289 /* Move To One Condition Register Field */
4290 case 192: /* Compare Ranged Byte */
4291 case 224: /* Compare Equal Byte */
4292 case 576: /* Move XER to CR Extended */
4293 case 902: /* Paste (should always fail due to single-stepping and
4294 the memory location might not be accessible, so
4296 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4299 /* These write to RT. Update RA if 'update indexed.' */
4300 case 53: /* Load Doubleword with Update Indexed */
4301 case 119: /* Load Byte and Zero with Update Indexed */
4302 case 311: /* Load Halfword and Zero with Update Indexed */
4303 case 55: /* Load Word and Zero with Update Indexed */
4304 case 375: /* Load Halfword Algebraic with Update Indexed */
4305 case 373: /* Load Word Algebraic with Update Indexed */
4306 record_full_arch_list_add_reg (regcache
,
4307 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4309 case 21: /* Load Doubleword Indexed */
4310 case 52: /* Load Byte And Reserve Indexed */
4311 case 116: /* Load Halfword And Reserve Indexed */
4312 case 20: /* Load Word And Reserve Indexed */
4313 case 84: /* Load Doubleword And Reserve Indexed */
4314 case 87: /* Load Byte and Zero Indexed */
4315 case 279: /* Load Halfword and Zero Indexed */
4316 case 23: /* Load Word and Zero Indexed */
4317 case 343: /* Load Halfword Algebraic Indexed */
4318 case 341: /* Load Word Algebraic Indexed */
4319 case 790: /* Load Halfword Byte-Reverse Indexed */
4320 case 534: /* Load Word Byte-Reverse Indexed */
4321 case 532: /* Load Doubleword Byte-Reverse Indexed */
4322 case 582: /* Load Word Atomic */
4323 case 614: /* Load Doubleword Atomic */
4324 case 265: /* Modulo Unsigned Doubleword */
4325 case 777: /* Modulo Signed Doubleword */
4326 case 267: /* Modulo Unsigned Word */
4327 case 779: /* Modulo Signed Word */
4328 record_full_arch_list_add_reg (regcache
,
4329 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4332 case 597: /* Load String Word Immediate */
4333 case 533: /* Load String Word Indexed */
4342 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4343 nr
= PPC_XER_NB (xer
);
4348 /* If n=0, the contents of register RT are undefined. */
4352 for (i
= 0; i
< nr
; i
++)
4353 record_full_arch_list_add_reg (regcache
,
4354 tdep
->ppc_gp0_regnum
4355 + ((PPC_RT (insn
) + i
) & 0x1f));
4358 case 276: /* Load Quadword And Reserve Indexed */
4359 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4360 record_full_arch_list_add_reg (regcache
, tmp
);
4361 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4364 /* These write VRT. */
4365 case 6: /* Load Vector for Shift Left Indexed */
4366 case 38: /* Load Vector for Shift Right Indexed */
4367 case 7: /* Load Vector Element Byte Indexed */
4368 case 39: /* Load Vector Element Halfword Indexed */
4369 case 71: /* Load Vector Element Word Indexed */
4370 case 103: /* Load Vector Indexed */
4371 case 359: /* Load Vector Indexed LRU */
4372 record_full_arch_list_add_reg (regcache
,
4373 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4376 /* These write FRT. Update RA if 'update indexed.' */
4377 case 567: /* Load Floating-Point Single with Update Indexed */
4378 case 631: /* Load Floating-Point Double with Update Indexed */
4379 record_full_arch_list_add_reg (regcache
,
4380 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4382 case 535: /* Load Floating-Point Single Indexed */
4383 case 599: /* Load Floating-Point Double Indexed */
4384 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4385 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4386 record_full_arch_list_add_reg (regcache
,
4387 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4390 case 791: /* Load Floating-Point Double Pair Indexed */
4391 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4392 record_full_arch_list_add_reg (regcache
, tmp
);
4393 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4396 case 179: /* Move To VSR Doubleword */
4397 case 211: /* Move To VSR Word Algebraic */
4398 case 243: /* Move To VSR Word and Zero */
4399 case 588: /* Load VSX Scalar Doubleword Indexed */
4400 case 524: /* Load VSX Scalar Single-Precision Indexed */
4401 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4402 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4403 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4404 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4405 case 780: /* Load VSX Vector Word*4 Indexed */
4406 case 268: /* Load VSX Vector Indexed */
4407 case 364: /* Load VSX Vector Word & Splat Indexed */
4408 case 812: /* Load VSX Vector Halfword*8 Indexed */
4409 case 876: /* Load VSX Vector Byte*16 Indexed */
4410 case 269: /* Load VSX Vector with Length */
4411 case 301: /* Load VSX Vector Left-justified with Length */
4412 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4413 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4414 case 403: /* Move To VSR Word & Splat */
4415 case 435: /* Move To VSR Double Doubleword */
4416 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4419 /* These write RA. Update CR if RC is set. */
4420 case 24: /* Shift Left Word */
4421 case 26: /* Count Leading Zeros Word */
4422 case 27: /* Shift Left Doubleword */
4424 case 58: /* Count Leading Zeros Doubleword */
4425 case 60: /* AND with Complement */
4427 case 284: /* Equivalent */
4429 case 476: /* NAND */
4430 case 412: /* OR with Complement */
4432 case 536: /* Shift Right Word */
4433 case 539: /* Shift Right Doubleword */
4434 case 922: /* Extend Sign Halfword */
4435 case 954: /* Extend Sign Byte */
4436 case 986: /* Extend Sign Word */
4437 case 538: /* Count Trailing Zeros Word */
4438 case 570: /* Count Trailing Zeros Doubleword */
4439 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4440 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4442 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4443 record_full_arch_list_add_reg (regcache
,
4444 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4448 case 181: /* Store Doubleword with Update Indexed */
4449 case 183: /* Store Word with Update Indexed */
4450 case 247: /* Store Byte with Update Indexed */
4451 case 439: /* Store Half Word with Update Indexed */
4452 case 695: /* Store Floating-Point Single with Update Indexed */
4453 case 759: /* Store Floating-Point Double with Update Indexed */
4454 record_full_arch_list_add_reg (regcache
,
4455 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4457 case 135: /* Store Vector Element Byte Indexed */
4458 case 167: /* Store Vector Element Halfword Indexed */
4459 case 199: /* Store Vector Element Word Indexed */
4460 case 231: /* Store Vector Indexed */
4461 case 487: /* Store Vector Indexed LRU */
4462 case 716: /* Store VSX Scalar Doubleword Indexed */
4463 case 140: /* Store VSX Scalar as Integer Word Indexed */
4464 case 652: /* Store VSX Scalar Single-Precision Indexed */
4465 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4466 case 908: /* Store VSX Vector Word*4 Indexed */
4467 case 149: /* Store Doubleword Indexed */
4468 case 151: /* Store Word Indexed */
4469 case 215: /* Store Byte Indexed */
4470 case 407: /* Store Half Word Indexed */
4471 case 694: /* Store Byte Conditional Indexed */
4472 case 726: /* Store Halfword Conditional Indexed */
4473 case 150: /* Store Word Conditional Indexed */
4474 case 214: /* Store Doubleword Conditional Indexed */
4475 case 182: /* Store Quadword Conditional Indexed */
4476 case 662: /* Store Word Byte-Reverse Indexed */
4477 case 918: /* Store Halfword Byte-Reverse Indexed */
4478 case 660: /* Store Doubleword Byte-Reverse Indexed */
4479 case 663: /* Store Floating-Point Single Indexed */
4480 case 727: /* Store Floating-Point Double Indexed */
4481 case 919: /* Store Floating-Point Double Pair Indexed */
4482 case 983: /* Store Floating-Point as Integer Word Indexed */
4483 case 396: /* Store VSX Vector Indexed */
4484 case 940: /* Store VSX Vector Halfword*8 Indexed */
4485 case 1004: /* Store VSX Vector Byte*16 Indexed */
4486 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4487 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4488 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4489 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4492 if (PPC_RA (insn
) != 0)
4493 regcache_raw_read_unsigned (regcache
,
4494 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4495 regcache_raw_read_unsigned (regcache
,
4496 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4501 case 183: /* Store Word with Update Indexed */
4502 case 199: /* Store Vector Element Word Indexed */
4503 case 140: /* Store VSX Scalar as Integer Word Indexed */
4504 case 652: /* Store VSX Scalar Single-Precision Indexed */
4505 case 151: /* Store Word Indexed */
4506 case 150: /* Store Word Conditional Indexed */
4507 case 662: /* Store Word Byte-Reverse Indexed */
4508 case 663: /* Store Floating-Point Single Indexed */
4509 case 695: /* Store Floating-Point Single with Update Indexed */
4510 case 983: /* Store Floating-Point as Integer Word Indexed */
4513 case 247: /* Store Byte with Update Indexed */
4514 case 135: /* Store Vector Element Byte Indexed */
4515 case 215: /* Store Byte Indexed */
4516 case 694: /* Store Byte Conditional Indexed */
4517 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4520 case 439: /* Store Halfword with Update Indexed */
4521 case 167: /* Store Vector Element Halfword Indexed */
4522 case 407: /* Store Halfword Indexed */
4523 case 726: /* Store Halfword Conditional Indexed */
4524 case 918: /* Store Halfword Byte-Reverse Indexed */
4525 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4528 case 181: /* Store Doubleword with Update Indexed */
4529 case 716: /* Store VSX Scalar Doubleword Indexed */
4530 case 149: /* Store Doubleword Indexed */
4531 case 214: /* Store Doubleword Conditional Indexed */
4532 case 660: /* Store Doubleword Byte-Reverse Indexed */
4533 case 727: /* Store Floating-Point Double Indexed */
4534 case 759: /* Store Floating-Point Double with Update Indexed */
4537 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4538 case 908: /* Store VSX Vector Word*4 Indexed */
4539 case 182: /* Store Quadword Conditional Indexed */
4540 case 231: /* Store Vector Indexed */
4541 case 487: /* Store Vector Indexed LRU */
4542 case 919: /* Store Floating-Point Double Pair Indexed */
4543 case 396: /* Store VSX Vector Indexed */
4544 case 940: /* Store VSX Vector Halfword*8 Indexed */
4545 case 1004: /* Store VSX Vector Byte*16 Indexed */
4552 /* Align address for Store Vector instructions. */
4555 case 167: /* Store Vector Element Halfword Indexed */
4556 addr
= addr
& ~0x1ULL
;
4559 case 199: /* Store Vector Element Word Indexed */
4560 addr
= addr
& ~0x3ULL
;
4563 case 231: /* Store Vector Indexed */
4564 case 487: /* Store Vector Indexed LRU */
4565 addr
= addr
& ~0xfULL
;
4569 record_full_arch_list_add_mem (addr
, size
);
4572 case 397: /* Store VSX Vector with Length */
4573 case 429: /* Store VSX Vector Left-justified with Length */
4575 if (PPC_RA (insn
) != 0)
4576 regcache_raw_read_unsigned (regcache
,
4577 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4579 regcache_raw_read_unsigned (regcache
,
4580 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4581 /* Store up to 16 bytes. */
4582 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4584 record_full_arch_list_add_mem (ea
, nb
);
4587 case 710: /* Store Word Atomic */
4588 case 742: /* Store Doubleword Atomic */
4590 if (PPC_RA (insn
) != 0)
4591 regcache_raw_read_unsigned (regcache
,
4592 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4596 case 710: /* Store Word Atomic */
4599 case 742: /* Store Doubleword Atomic */
4605 record_full_arch_list_add_mem (ea
, size
);
4608 case 725: /* Store String Word Immediate */
4610 if (PPC_RA (insn
) != 0)
4611 regcache_raw_read_unsigned (regcache
,
4612 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4619 record_full_arch_list_add_mem (ea
, nb
);
4623 case 661: /* Store String Word Indexed */
4625 if (PPC_RA (insn
) != 0)
4626 regcache_raw_read_unsigned (regcache
,
4627 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4630 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4631 nb
= PPC_XER_NB (xer
);
4635 regcache_raw_read_unsigned (regcache
,
4636 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4639 record_full_arch_list_add_mem (ea
, nb
);
4644 case 467: /* Move To Special Purpose Register */
4645 switch (PPC_SPR (insn
))
4648 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4651 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4654 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4656 case 256: /* VRSAVE */
4657 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4663 case 147: /* Move To Split Little Endian */
4664 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4667 case 512: /* Move to Condition Register from XER */
4668 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4669 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4672 case 4: /* Trap Word */
4673 case 68: /* Trap Doubleword */
4674 case 430: /* Clear BHRB */
4675 case 598: /* Synchronize */
4676 case 62: /* Wait for Interrupt */
4678 case 22: /* Instruction Cache Block Touch */
4679 case 854: /* Enforce In-order Execution of I/O */
4680 case 246: /* Data Cache Block Touch for Store */
4681 case 54: /* Data Cache Block Store */
4682 case 86: /* Data Cache Block Flush */
4683 case 278: /* Data Cache Block Touch */
4684 case 758: /* Data Cache Block Allocate */
4685 case 982: /* Instruction Cache Block Invalidate */
4686 case 774: /* Copy */
4687 case 838: /* CP_Abort */
4690 case 654: /* Transaction Begin */
4691 case 686: /* Transaction End */
4692 case 750: /* Transaction Suspend or Resume */
4693 case 782: /* Transaction Abort Word Conditional */
4694 case 814: /* Transaction Abort Doubleword Conditional */
4695 case 846: /* Transaction Abort Word Conditional Immediate */
4696 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4697 case 910: /* Transaction Abort */
4698 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4700 case 718: /* Transaction Check */
4701 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4704 case 1014: /* Data Cache Block set to Zero */
4705 if (target_auxv_search (target_stack
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4707 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4710 if (PPC_RA (insn
) != 0)
4711 regcache_raw_read_unsigned (regcache
,
4712 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4713 regcache_raw_read_unsigned (regcache
,
4714 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4715 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4716 record_full_arch_list_add_mem (ea
, at_dcsz
);
4721 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4722 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4726 /* Parse and record instructions of primary opcode-59 at ADDR.
4727 Return 0 if successful. */
4730 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4731 CORE_ADDR addr
, uint32_t insn
)
4733 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4734 int ext
= PPC_EXTOP (insn
);
4738 case 18: /* Floating Divide */
4739 case 20: /* Floating Subtract */
4740 case 21: /* Floating Add */
4741 case 22: /* Floating Square Root */
4742 case 24: /* Floating Reciprocal Estimate */
4743 case 25: /* Floating Multiply */
4744 case 26: /* Floating Reciprocal Square Root Estimate */
4745 case 28: /* Floating Multiply-Subtract */
4746 case 29: /* Floating Multiply-Add */
4747 case 30: /* Floating Negative Multiply-Subtract */
4748 case 31: /* Floating Negative Multiply-Add */
4749 record_full_arch_list_add_reg (regcache
,
4750 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4752 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4753 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4760 case 2: /* DFP Add */
4761 case 3: /* DFP Quantize */
4762 case 34: /* DFP Multiply */
4763 case 35: /* DFP Reround */
4764 case 67: /* DFP Quantize Immediate */
4765 case 99: /* DFP Round To FP Integer With Inexact */
4766 case 227: /* DFP Round To FP Integer Without Inexact */
4767 case 258: /* DFP Convert To DFP Long! */
4768 case 290: /* DFP Convert To Fixed */
4769 case 514: /* DFP Subtract */
4770 case 546: /* DFP Divide */
4771 case 770: /* DFP Round To DFP Short! */
4772 case 802: /* DFP Convert From Fixed */
4773 case 834: /* DFP Encode BCD To DPD */
4775 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4776 record_full_arch_list_add_reg (regcache
,
4777 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4778 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4781 case 130: /* DFP Compare Ordered */
4782 case 162: /* DFP Test Exponent */
4783 case 194: /* DFP Test Data Class */
4784 case 226: /* DFP Test Data Group */
4785 case 642: /* DFP Compare Unordered */
4786 case 674: /* DFP Test Significance */
4787 case 675: /* DFP Test Significance Immediate */
4788 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4789 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4792 case 66: /* DFP Shift Significand Left Immediate */
4793 case 98: /* DFP Shift Significand Right Immediate */
4794 case 322: /* DFP Decode DPD To BCD */
4795 case 354: /* DFP Extract Biased Exponent */
4796 case 866: /* DFP Insert Biased Exponent */
4797 record_full_arch_list_add_reg (regcache
,
4798 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4800 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4803 case 846: /* Floating Convert From Integer Doubleword Single */
4804 case 974: /* Floating Convert From Integer Doubleword Unsigned
4806 record_full_arch_list_add_reg (regcache
,
4807 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4809 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4810 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4815 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4816 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4820 /* Parse and record instructions of primary opcode-60 at ADDR.
4821 Return 0 if successful. */
4824 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4825 CORE_ADDR addr
, uint32_t insn
)
4827 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4828 int ext
= PPC_EXTOP (insn
);
4832 case 0: /* VSX Scalar Add Single-Precision */
4833 case 32: /* VSX Scalar Add Double-Precision */
4834 case 24: /* VSX Scalar Divide Single-Precision */
4835 case 56: /* VSX Scalar Divide Double-Precision */
4836 case 176: /* VSX Scalar Copy Sign Double-Precision */
4837 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4838 case 41: /* ditto */
4839 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4841 case 160: /* VSX Scalar Maximum Double-Precision */
4842 case 168: /* VSX Scalar Minimum Double-Precision */
4843 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4844 case 57: /* ditto */
4845 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4846 case 25: /* ditto */
4847 case 48: /* VSX Scalar Multiply Double-Precision */
4848 case 16: /* VSX Scalar Multiply Single-Precision */
4849 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4850 case 169: /* ditto */
4851 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4852 case 137: /* ditto */
4853 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4854 case 185: /* ditto */
4855 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4856 case 153: /* ditto */
4857 case 40: /* VSX Scalar Subtract Double-Precision */
4858 case 8: /* VSX Scalar Subtract Single-Precision */
4859 case 96: /* VSX Vector Add Double-Precision */
4860 case 64: /* VSX Vector Add Single-Precision */
4861 case 120: /* VSX Vector Divide Double-Precision */
4862 case 88: /* VSX Vector Divide Single-Precision */
4863 case 97: /* VSX Vector Multiply-Add Double-Precision */
4864 case 105: /* ditto */
4865 case 65: /* VSX Vector Multiply-Add Single-Precision */
4866 case 73: /* ditto */
4867 case 224: /* VSX Vector Maximum Double-Precision */
4868 case 192: /* VSX Vector Maximum Single-Precision */
4869 case 232: /* VSX Vector Minimum Double-Precision */
4870 case 200: /* VSX Vector Minimum Single-Precision */
4871 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
4872 case 121: /* ditto */
4873 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
4874 case 89: /* ditto */
4875 case 112: /* VSX Vector Multiply Double-Precision */
4876 case 80: /* VSX Vector Multiply Single-Precision */
4877 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
4878 case 233: /* ditto */
4879 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
4880 case 201: /* ditto */
4881 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
4882 case 249: /* ditto */
4883 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
4884 case 217: /* ditto */
4885 case 104: /* VSX Vector Subtract Double-Precision */
4886 case 72: /* VSX Vector Subtract Single-Precision */
4887 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
4888 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
4889 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
4890 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
4891 case 3: /* VSX Scalar Compare Equal Double-Precision */
4892 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
4893 case 19: /* VSX Scalar Compare Greater Than or Equal
4895 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4897 case 240: /* VSX Vector Copy Sign Double-Precision */
4898 case 208: /* VSX Vector Copy Sign Single-Precision */
4899 case 130: /* VSX Logical AND */
4900 case 138: /* VSX Logical AND with Complement */
4901 case 186: /* VSX Logical Equivalence */
4902 case 178: /* VSX Logical NAND */
4903 case 170: /* VSX Logical OR with Complement */
4904 case 162: /* VSX Logical NOR */
4905 case 146: /* VSX Logical OR */
4906 case 154: /* VSX Logical XOR */
4907 case 18: /* VSX Merge High Word */
4908 case 50: /* VSX Merge Low Word */
4909 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
4910 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
4911 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
4912 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
4913 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
4914 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
4915 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
4916 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
4917 case 216: /* VSX Vector Insert Exponent Single-Precision */
4918 case 248: /* VSX Vector Insert Exponent Double-Precision */
4919 case 26: /* VSX Vector Permute */
4920 case 58: /* VSX Vector Permute Right-indexed */
4921 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
4922 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
4923 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
4924 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
4925 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4928 case 61: /* VSX Scalar Test for software Divide Double-Precision */
4929 case 125: /* VSX Vector Test for software Divide Double-Precision */
4930 case 93: /* VSX Vector Test for software Divide Single-Precision */
4931 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4934 case 35: /* VSX Scalar Compare Unordered Double-Precision */
4935 case 43: /* VSX Scalar Compare Ordered Double-Precision */
4936 case 59: /* VSX Scalar Compare Exponents Double-Precision */
4937 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4938 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4942 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
4944 case 99: /* VSX Vector Compare Equal To Double-Precision */
4945 case 67: /* VSX Vector Compare Equal To Single-Precision */
4946 case 115: /* VSX Vector Compare Greater Than or
4947 Equal To Double-Precision */
4948 case 83: /* VSX Vector Compare Greater Than or
4949 Equal To Single-Precision */
4950 case 107: /* VSX Vector Compare Greater Than Double-Precision */
4951 case 75: /* VSX Vector Compare Greater Than Single-Precision */
4953 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4954 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4955 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4961 case 265: /* VSX Scalar round Double-Precision to
4962 Single-Precision and Convert to
4963 Single-Precision format */
4964 case 344: /* VSX Scalar truncate Double-Precision to
4965 Integer and Convert to Signed Integer
4966 Doubleword format with Saturate */
4967 case 88: /* VSX Scalar truncate Double-Precision to
4968 Integer and Convert to Signed Integer Word
4969 Format with Saturate */
4970 case 328: /* VSX Scalar truncate Double-Precision integer
4971 and Convert to Unsigned Integer Doubleword
4972 Format with Saturate */
4973 case 72: /* VSX Scalar truncate Double-Precision to
4974 Integer and Convert to Unsigned Integer Word
4975 Format with Saturate */
4976 case 329: /* VSX Scalar Convert Single-Precision to
4977 Double-Precision format */
4978 case 376: /* VSX Scalar Convert Signed Integer
4979 Doubleword to floating-point format and
4980 Round to Double-Precision format */
4981 case 312: /* VSX Scalar Convert Signed Integer
4982 Doubleword to floating-point format and
4983 round to Single-Precision */
4984 case 360: /* VSX Scalar Convert Unsigned Integer
4985 Doubleword to floating-point format and
4986 Round to Double-Precision format */
4987 case 296: /* VSX Scalar Convert Unsigned Integer
4988 Doubleword to floating-point format and
4989 Round to Single-Precision */
4990 case 73: /* VSX Scalar Round to Double-Precision Integer
4991 Using Round to Nearest Away */
4992 case 107: /* VSX Scalar Round to Double-Precision Integer
4993 Exact using Current rounding mode */
4994 case 121: /* VSX Scalar Round to Double-Precision Integer
4995 Using Round toward -Infinity */
4996 case 105: /* VSX Scalar Round to Double-Precision Integer
4997 Using Round toward +Infinity */
4998 case 89: /* VSX Scalar Round to Double-Precision Integer
4999 Using Round toward Zero */
5000 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5001 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5002 case 281: /* VSX Scalar Round to Single-Precision */
5003 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5005 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5007 case 75: /* VSX Scalar Square Root Double-Precision */
5008 case 11: /* VSX Scalar Square Root Single-Precision */
5009 case 393: /* VSX Vector round Double-Precision to
5010 Single-Precision and Convert to
5011 Single-Precision format */
5012 case 472: /* VSX Vector truncate Double-Precision to
5013 Integer and Convert to Signed Integer
5014 Doubleword format with Saturate */
5015 case 216: /* VSX Vector truncate Double-Precision to
5016 Integer and Convert to Signed Integer Word
5017 Format with Saturate */
5018 case 456: /* VSX Vector truncate Double-Precision to
5019 Integer and Convert to Unsigned Integer
5020 Doubleword format with Saturate */
5021 case 200: /* VSX Vector truncate Double-Precision to
5022 Integer and Convert to Unsigned Integer Word
5023 Format with Saturate */
5024 case 457: /* VSX Vector Convert Single-Precision to
5025 Double-Precision format */
5026 case 408: /* VSX Vector truncate Single-Precision to
5027 Integer and Convert to Signed Integer
5028 Doubleword format with Saturate */
5029 case 152: /* VSX Vector truncate Single-Precision to
5030 Integer and Convert to Signed Integer Word
5031 Format with Saturate */
5032 case 392: /* VSX Vector truncate Single-Precision to
5033 Integer and Convert to Unsigned Integer
5034 Doubleword format with Saturate */
5035 case 136: /* VSX Vector truncate Single-Precision to
5036 Integer and Convert to Unsigned Integer Word
5037 Format with Saturate */
5038 case 504: /* VSX Vector Convert and round Signed Integer
5039 Doubleword to Double-Precision format */
5040 case 440: /* VSX Vector Convert and round Signed Integer
5041 Doubleword to Single-Precision format */
5042 case 248: /* VSX Vector Convert Signed Integer Word to
5043 Double-Precision format */
5044 case 184: /* VSX Vector Convert and round Signed Integer
5045 Word to Single-Precision format */
5046 case 488: /* VSX Vector Convert and round Unsigned
5047 Integer Doubleword to Double-Precision format */
5048 case 424: /* VSX Vector Convert and round Unsigned
5049 Integer Doubleword to Single-Precision format */
5050 case 232: /* VSX Vector Convert and round Unsigned
5051 Integer Word to Double-Precision format */
5052 case 168: /* VSX Vector Convert and round Unsigned
5053 Integer Word to Single-Precision format */
5054 case 201: /* VSX Vector Round to Double-Precision
5055 Integer using round to Nearest Away */
5056 case 235: /* VSX Vector Round to Double-Precision
5057 Integer Exact using Current rounding mode */
5058 case 249: /* VSX Vector Round to Double-Precision
5059 Integer using round toward -Infinity */
5060 case 233: /* VSX Vector Round to Double-Precision
5061 Integer using round toward +Infinity */
5062 case 217: /* VSX Vector Round to Double-Precision
5063 Integer using round toward Zero */
5064 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5065 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5066 case 137: /* VSX Vector Round to Single-Precision Integer
5067 Using Round to Nearest Away */
5068 case 171: /* VSX Vector Round to Single-Precision Integer
5069 Exact Using Current rounding mode */
5070 case 185: /* VSX Vector Round to Single-Precision Integer
5071 Using Round toward -Infinity */
5072 case 169: /* VSX Vector Round to Single-Precision Integer
5073 Using Round toward +Infinity */
5074 case 153: /* VSX Vector Round to Single-Precision Integer
5075 Using round toward Zero */
5076 case 202: /* VSX Vector Reciprocal Square Root Estimate
5078 case 138: /* VSX Vector Reciprocal Square Root Estimate
5080 case 203: /* VSX Vector Square Root Double-Precision */
5081 case 139: /* VSX Vector Square Root Single-Precision */
5082 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5084 case 345: /* VSX Scalar Absolute Value Double-Precision */
5085 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5086 Vector Single-Precision format Non-signalling */
5087 case 331: /* VSX Scalar Convert Single-Precision to
5088 Double-Precision format Non-signalling */
5089 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5090 case 377: /* VSX Scalar Negate Double-Precision */
5091 case 473: /* VSX Vector Absolute Value Double-Precision */
5092 case 409: /* VSX Vector Absolute Value Single-Precision */
5093 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5094 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5095 case 505: /* VSX Vector Negate Double-Precision */
5096 case 441: /* VSX Vector Negate Single-Precision */
5097 case 164: /* VSX Splat Word */
5098 case 165: /* VSX Vector Extract Unsigned Word */
5099 case 181: /* VSX Vector Insert Word */
5100 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5103 case 298: /* VSX Scalar Test Data Class Single-Precision */
5104 case 362: /* VSX Scalar Test Data Class Double-Precision */
5105 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5107 case 106: /* VSX Scalar Test for software Square Root
5109 case 234: /* VSX Vector Test for software Square Root
5111 case 170: /* VSX Vector Test for software Square Root
5113 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5117 switch (PPC_FIELD (insn
, 11, 5))
5119 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5120 case 1: /* VSX Scalar Extract Significand Double-Precision */
5121 record_full_arch_list_add_reg (regcache
,
5122 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5124 case 16: /* VSX Scalar Convert Half-Precision format to
5125 Double-Precision format */
5126 case 17: /* VSX Scalar round & Convert Double-Precision format
5127 to Half-Precision format */
5128 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5129 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5135 switch (PPC_FIELD (insn
, 11, 5))
5137 case 24: /* VSX Vector Convert Half-Precision format to
5138 Single-Precision format */
5139 case 25: /* VSX Vector round and Convert Single-Precision format
5140 to Half-Precision format */
5141 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5143 case 0: /* VSX Vector Extract Exponent Double-Precision */
5144 case 1: /* VSX Vector Extract Significand Double-Precision */
5145 case 7: /* VSX Vector Byte-Reverse Halfword */
5146 case 8: /* VSX Vector Extract Exponent Single-Precision */
5147 case 9: /* VSX Vector Extract Significand Single-Precision */
5148 case 15: /* VSX Vector Byte-Reverse Word */
5149 case 23: /* VSX Vector Byte-Reverse Doubleword */
5150 case 31: /* VSX Vector Byte-Reverse Quadword */
5151 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5159 case 360: /* VSX Vector Splat Immediate Byte */
5160 if (PPC_FIELD (insn
, 11, 2) == 0)
5162 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5166 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5167 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5171 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5173 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5177 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5178 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5182 /* Parse and record instructions of primary opcode-61 at ADDR.
5183 Return 0 if successful. */
5186 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5187 CORE_ADDR addr
, uint32_t insn
)
5189 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5195 case 0: /* Store Floating-Point Double Pair */
5196 case 2: /* Store VSX Scalar Doubleword */
5197 case 3: /* Store VSX Scalar Single */
5198 if (PPC_RA (insn
) != 0)
5199 regcache_raw_read_unsigned (regcache
,
5200 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5202 ea
+= PPC_DS (insn
) << 2;
5205 case 0: /* Store Floating-Point Double Pair */
5208 case 2: /* Store VSX Scalar Doubleword */
5211 case 3: /* Store VSX Scalar Single */
5217 record_full_arch_list_add_mem (ea
, size
);
5223 case 1: /* Load VSX Vector */
5224 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5226 case 5: /* Store VSX Vector */
5227 if (PPC_RA (insn
) != 0)
5228 regcache_raw_read_unsigned (regcache
,
5229 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5231 ea
+= PPC_DQ (insn
) << 4;
5232 record_full_arch_list_add_mem (ea
, 16);
5236 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5237 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5241 /* Parse and record instructions of primary opcode-63 at ADDR.
5242 Return 0 if successful. */
5245 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5246 CORE_ADDR addr
, uint32_t insn
)
5248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5249 int ext
= PPC_EXTOP (insn
);
5254 case 18: /* Floating Divide */
5255 case 20: /* Floating Subtract */
5256 case 21: /* Floating Add */
5257 case 22: /* Floating Square Root */
5258 case 24: /* Floating Reciprocal Estimate */
5259 case 25: /* Floating Multiply */
5260 case 26: /* Floating Reciprocal Square Root Estimate */
5261 case 28: /* Floating Multiply-Subtract */
5262 case 29: /* Floating Multiply-Add */
5263 case 30: /* Floating Negative Multiply-Subtract */
5264 case 31: /* Floating Negative Multiply-Add */
5265 record_full_arch_list_add_reg (regcache
,
5266 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5268 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5269 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5272 case 23: /* Floating Select */
5273 record_full_arch_list_add_reg (regcache
,
5274 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5276 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5282 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5283 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5285 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5286 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5292 case 2: /* DFP Add Quad */
5293 case 3: /* DFP Quantize Quad */
5294 case 34: /* DFP Multiply Quad */
5295 case 35: /* DFP Reround Quad */
5296 case 67: /* DFP Quantize Immediate Quad */
5297 case 99: /* DFP Round To FP Integer With Inexact Quad */
5298 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5299 case 258: /* DFP Convert To DFP Extended Quad */
5300 case 514: /* DFP Subtract Quad */
5301 case 546: /* DFP Divide Quad */
5302 case 770: /* DFP Round To DFP Long Quad */
5303 case 802: /* DFP Convert From Fixed Quad */
5304 case 834: /* DFP Encode BCD To DPD Quad */
5306 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5307 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5308 record_full_arch_list_add_reg (regcache
, tmp
);
5309 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5310 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5313 case 130: /* DFP Compare Ordered Quad */
5314 case 162: /* DFP Test Exponent Quad */
5315 case 194: /* DFP Test Data Class Quad */
5316 case 226: /* DFP Test Data Group Quad */
5317 case 642: /* DFP Compare Unordered Quad */
5318 case 674: /* DFP Test Significance Quad */
5319 case 675: /* DFP Test Significance Immediate Quad */
5320 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5321 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5324 case 66: /* DFP Shift Significand Left Immediate Quad */
5325 case 98: /* DFP Shift Significand Right Immediate Quad */
5326 case 322: /* DFP Decode DPD To BCD Quad */
5327 case 866: /* DFP Insert Biased Exponent Quad */
5328 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5329 record_full_arch_list_add_reg (regcache
, tmp
);
5330 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5332 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5335 case 290: /* DFP Convert To Fixed Quad */
5336 record_full_arch_list_add_reg (regcache
,
5337 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5339 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5340 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5343 case 354: /* DFP Extract Biased Exponent Quad */
5344 record_full_arch_list_add_reg (regcache
,
5345 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5347 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5350 case 12: /* Floating Round to Single-Precision */
5351 case 14: /* Floating Convert To Integer Word */
5352 case 15: /* Floating Convert To Integer Word
5353 with round toward Zero */
5354 case 142: /* Floating Convert To Integer Word Unsigned */
5355 case 143: /* Floating Convert To Integer Word Unsigned
5356 with round toward Zero */
5357 case 392: /* Floating Round to Integer Nearest */
5358 case 424: /* Floating Round to Integer Toward Zero */
5359 case 456: /* Floating Round to Integer Plus */
5360 case 488: /* Floating Round to Integer Minus */
5361 case 814: /* Floating Convert To Integer Doubleword */
5362 case 815: /* Floating Convert To Integer Doubleword
5363 with round toward Zero */
5364 case 846: /* Floating Convert From Integer Doubleword */
5365 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5366 case 943: /* Floating Convert To Integer Doubleword Unsigned
5367 with round toward Zero */
5368 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5369 record_full_arch_list_add_reg (regcache
,
5370 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5372 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5373 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5377 switch (PPC_FIELD (insn
, 11, 5))
5379 case 1: /* Move From FPSCR & Clear Enables */
5380 case 20: /* Move From FPSCR Control & set DRN */
5381 case 21: /* Move From FPSCR Control & set DRN Immediate */
5382 case 22: /* Move From FPSCR Control & set RN */
5383 case 23: /* Move From FPSCR Control & set RN Immediate */
5384 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5386 case 0: /* Move From FPSCR */
5387 case 24: /* Move From FPSCR Lightweight */
5388 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5389 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5390 record_full_arch_list_add_reg (regcache
,
5391 tdep
->ppc_fp0_regnum
5397 case 8: /* Floating Copy Sign */
5398 case 40: /* Floating Negate */
5399 case 72: /* Floating Move Register */
5400 case 136: /* Floating Negative Absolute Value */
5401 case 264: /* Floating Absolute Value */
5402 record_full_arch_list_add_reg (regcache
,
5403 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5405 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5408 case 838: /* Floating Merge Odd Word */
5409 case 966: /* Floating Merge Even Word */
5410 record_full_arch_list_add_reg (regcache
,
5411 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5414 case 38: /* Move To FPSCR Bit 1 */
5415 case 70: /* Move To FPSCR Bit 0 */
5416 case 134: /* Move To FPSCR Field Immediate */
5417 case 711: /* Move To FPSCR Fields */
5419 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5420 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5423 case 0: /* Floating Compare Unordered */
5424 case 32: /* Floating Compare Ordered */
5425 case 64: /* Move to Condition Register from FPSCR */
5426 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5427 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5428 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5429 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5430 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5432 case 128: /* Floating Test for software Divide */
5433 case 160: /* Floating Test for software Square Root */
5434 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5437 case 4: /* VSX Scalar Add Quad-Precision */
5438 case 36: /* VSX Scalar Multiply Quad-Precision */
5439 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5440 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5441 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5442 case 484: /* VSX Scalar Negative Multiply-Subtract
5444 case 516: /* VSX Scalar Subtract Quad-Precision */
5445 case 548: /* VSX Scalar Divide Quad-Precision */
5446 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5448 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5449 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5450 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5454 switch (PPC_FIELD (insn
, 11, 5))
5456 case 27: /* VSX Scalar Square Root Quad-Precision */
5457 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5459 case 0: /* VSX Scalar Absolute Quad-Precision */
5460 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5461 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5462 case 16: /* VSX Scalar Negate Quad-Precision */
5463 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5464 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5470 switch (PPC_FIELD (insn
, 11, 5))
5472 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5473 to Unsigned Word format */
5474 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5475 Quad-Precision format */
5476 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5477 to Signed Word format */
5478 case 10: /* VSX Scalar Convert Signed Doubleword format to
5479 Quad-Precision format */
5480 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5481 to Unsigned Doubleword format */
5482 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5483 Double-Precision format */
5484 case 22: /* VSX Scalar Convert Double-Precision format to
5485 Quad-Precision format */
5486 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5487 to Signed Doubleword format */
5488 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5489 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5494 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5495 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5499 /* Parse the current instruction and record the values of the registers and
5500 memory that will be changed in current instruction to "record_arch_list".
5501 Return -1 if something wrong. */
5504 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5507 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5508 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5512 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5513 op6
= PPC_OP6 (insn
);
5517 case 2: /* Trap Doubleword Immediate */
5518 case 3: /* Trap Word Immediate */
5523 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5527 case 17: /* System call */
5528 if (PPC_LEV (insn
) != 0)
5531 if (tdep
->ppc_syscall_record
!= NULL
)
5533 if (tdep
->ppc_syscall_record (regcache
) != 0)
5538 printf_unfiltered (_("no syscall record support\n"));
5543 case 7: /* Multiply Low Immediate */
5544 record_full_arch_list_add_reg (regcache
,
5545 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5548 case 8: /* Subtract From Immediate Carrying */
5549 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5550 record_full_arch_list_add_reg (regcache
,
5551 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5554 case 10: /* Compare Logical Immediate */
5555 case 11: /* Compare Immediate */
5556 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5559 case 13: /* Add Immediate Carrying and Record */
5560 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5562 case 12: /* Add Immediate Carrying */
5563 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5565 case 14: /* Add Immediate */
5566 case 15: /* Add Immediate Shifted */
5567 record_full_arch_list_add_reg (regcache
,
5568 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5571 case 16: /* Branch Conditional */
5572 if ((PPC_BO (insn
) & 0x4) == 0)
5573 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5575 case 18: /* Branch */
5577 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5581 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5585 case 20: /* Rotate Left Word Immediate then Mask Insert */
5586 case 21: /* Rotate Left Word Immediate then AND with Mask */
5587 case 23: /* Rotate Left Word then AND with Mask */
5588 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5589 /* Rotate Left Doubleword Immediate then Clear Right */
5590 /* Rotate Left Doubleword Immediate then Clear */
5591 /* Rotate Left Doubleword then Clear Left */
5592 /* Rotate Left Doubleword then Clear Right */
5593 /* Rotate Left Doubleword Immediate then Mask Insert */
5595 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5596 record_full_arch_list_add_reg (regcache
,
5597 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5600 case 28: /* AND Immediate */
5601 case 29: /* AND Immediate Shifted */
5602 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5604 case 24: /* OR Immediate */
5605 case 25: /* OR Immediate Shifted */
5606 case 26: /* XOR Immediate */
5607 case 27: /* XOR Immediate Shifted */
5608 record_full_arch_list_add_reg (regcache
,
5609 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5613 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5617 case 33: /* Load Word and Zero with Update */
5618 case 35: /* Load Byte and Zero with Update */
5619 case 41: /* Load Halfword and Zero with Update */
5620 case 43: /* Load Halfword Algebraic with Update */
5621 record_full_arch_list_add_reg (regcache
,
5622 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5624 case 32: /* Load Word and Zero */
5625 case 34: /* Load Byte and Zero */
5626 case 40: /* Load Halfword and Zero */
5627 case 42: /* Load Halfword Algebraic */
5628 record_full_arch_list_add_reg (regcache
,
5629 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5632 case 46: /* Load Multiple Word */
5633 for (i
= PPC_RT (insn
); i
< 32; i
++)
5634 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5637 case 56: /* Load Quadword */
5638 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5639 record_full_arch_list_add_reg (regcache
, tmp
);
5640 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5643 case 49: /* Load Floating-Point Single with Update */
5644 case 51: /* Load Floating-Point Double with Update */
5645 record_full_arch_list_add_reg (regcache
,
5646 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5648 case 48: /* Load Floating-Point Single */
5649 case 50: /* Load Floating-Point Double */
5650 record_full_arch_list_add_reg (regcache
,
5651 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5654 case 47: /* Store Multiple Word */
5658 if (PPC_RA (insn
) != 0)
5659 regcache_raw_read_unsigned (regcache
,
5660 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5663 addr
+= PPC_D (insn
);
5664 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5668 case 37: /* Store Word with Update */
5669 case 39: /* Store Byte with Update */
5670 case 45: /* Store Halfword with Update */
5671 case 53: /* Store Floating-Point Single with Update */
5672 case 55: /* Store Floating-Point Double with Update */
5673 record_full_arch_list_add_reg (regcache
,
5674 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5676 case 36: /* Store Word */
5677 case 38: /* Store Byte */
5678 case 44: /* Store Halfword */
5679 case 52: /* Store Floating-Point Single */
5680 case 54: /* Store Floating-Point Double */
5685 if (PPC_RA (insn
) != 0)
5686 regcache_raw_read_unsigned (regcache
,
5687 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5689 addr
+= PPC_D (insn
);
5691 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5693 else if (op6
== 54 || op6
== 55)
5695 else if (op6
== 44 || op6
== 45)
5697 else if (op6
== 38 || op6
== 39)
5702 record_full_arch_list_add_mem (addr
, size
);
5709 case 0: /* Load Floating-Point Double Pair */
5710 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5711 record_full_arch_list_add_reg (regcache
, tmp
);
5712 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5714 case 2: /* Load VSX Scalar Doubleword */
5715 case 3: /* Load VSX Scalar Single */
5716 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5723 case 58: /* Load Doubleword */
5724 /* Load Doubleword with Update */
5725 /* Load Word Algebraic */
5726 if (PPC_FIELD (insn
, 30, 2) > 2)
5729 record_full_arch_list_add_reg (regcache
,
5730 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5731 if (PPC_BIT (insn
, 31))
5732 record_full_arch_list_add_reg (regcache
,
5733 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5737 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5742 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5747 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
5751 case 62: /* Store Doubleword */
5752 /* Store Doubleword with Update */
5753 /* Store Quadword with Update */
5757 int sub2
= PPC_FIELD (insn
, 30, 2);
5762 if (PPC_RA (insn
) != 0)
5763 regcache_raw_read_unsigned (regcache
,
5764 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5767 size
= (sub2
== 2) ? 16 : 8;
5769 addr
+= PPC_DS (insn
) << 2;
5770 record_full_arch_list_add_mem (addr
, size
);
5772 if (op6
== 62 && sub2
== 1)
5773 record_full_arch_list_add_reg (regcache
,
5774 tdep
->ppc_gp0_regnum
+
5781 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5787 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5788 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5792 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5794 if (record_full_arch_list_add_end ())
5799 /* Initialize the current architecture based on INFO. If possible, re-use an
5800 architecture from ARCHES, which is a list of architectures already created
5801 during this debugging session.
5803 Called e.g. at program startup, when reading a core file, and when reading
5806 static struct gdbarch
*
5807 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5809 struct gdbarch
*gdbarch
;
5810 struct gdbarch_tdep
*tdep
;
5811 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5812 enum bfd_architecture arch
;
5815 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5817 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
5818 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5819 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5820 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
5822 int tdesc_wordsize
= -1;
5823 const struct target_desc
*tdesc
= info
.target_desc
;
5824 struct tdesc_arch_data
*tdesc_data
= NULL
;
5825 int num_pseudoregs
= 0;
5828 /* INFO may refer to a binary that is not of the PowerPC architecture,
5829 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5830 In this case, we must not attempt to infer properties of the (PowerPC
5831 side) of the target system from properties of that executable. Trust
5832 the target description instead. */
5834 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5835 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5838 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5839 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5841 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5842 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5844 /* Check word size. If INFO is from a binary file, infer it from
5845 that, else choose a likely default. */
5846 if (from_xcoff_exec
)
5848 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5853 else if (from_elf_exec
)
5855 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5860 else if (tdesc_has_registers (tdesc
))
5864 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
5865 wordsize
= (info
.bfd_arch_info
->bits_per_word
5866 / info
.bfd_arch_info
->bits_per_byte
);
5871 /* Get the architecture and machine from the BFD. */
5872 arch
= info
.bfd_arch_info
->arch
;
5873 mach
= info
.bfd_arch_info
->mach
;
5875 /* For e500 executables, the apuinfo section is of help here. Such
5876 section contains the identifier and revision number of each
5877 Application-specific Processing Unit that is present on the
5878 chip. The content of the section is determined by the assembler
5879 which looks at each instruction and determines which unit (and
5880 which version of it) can execute it. Grovel through the section
5881 looking for relevant e500 APUs. */
5883 if (bfd_uses_spe_extensions (info
.abfd
))
5885 arch
= info
.bfd_arch_info
->arch
;
5886 mach
= bfd_mach_ppc_e500
;
5887 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
5888 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
5891 /* Find a default target description which describes our register
5892 layout, if we do not already have one. */
5893 if (! tdesc_has_registers (tdesc
))
5895 const struct variant
*v
;
5897 /* Choose variant. */
5898 v
= find_variant_by_arch (arch
, mach
);
5905 gdb_assert (tdesc_has_registers (tdesc
));
5907 /* Check any target description for validity. */
5908 if (tdesc_has_registers (tdesc
))
5910 static const char *const gprs
[] = {
5911 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5912 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5913 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5914 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5916 const struct tdesc_feature
*feature
;
5918 static const char *const msr_names
[] = { "msr", "ps" };
5919 static const char *const cr_names
[] = { "cr", "cnd" };
5920 static const char *const ctr_names
[] = { "ctr", "cnt" };
5922 feature
= tdesc_find_feature (tdesc
,
5923 "org.gnu.gdb.power.core");
5924 if (feature
== NULL
)
5927 tdesc_data
= tdesc_data_alloc ();
5930 for (i
= 0; i
< ppc_num_gprs
; i
++)
5931 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
5932 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
5934 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
5936 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
5939 /* Allow alternate names for these registers, to accomodate GDB's
5941 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5942 PPC_MSR_REGNUM
, msr_names
);
5943 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5944 PPC_CR_REGNUM
, cr_names
);
5945 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5946 PPC_CTR_REGNUM
, ctr_names
);
5950 tdesc_data_cleanup (tdesc_data
);
5954 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
5957 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
5959 wordsize
= tdesc_wordsize
;
5961 feature
= tdesc_find_feature (tdesc
,
5962 "org.gnu.gdb.power.fpu");
5963 if (feature
!= NULL
)
5965 static const char *const fprs
[] = {
5966 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5967 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5968 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5969 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
5972 for (i
= 0; i
< ppc_num_fprs
; i
++)
5973 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5974 PPC_F0_REGNUM
+ i
, fprs
[i
]);
5975 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5976 PPC_FPSCR_REGNUM
, "fpscr");
5980 tdesc_data_cleanup (tdesc_data
);
5988 /* The DFP pseudo-registers will be available when there are floating
5990 have_dfp
= have_fpu
;
5992 feature
= tdesc_find_feature (tdesc
,
5993 "org.gnu.gdb.power.altivec");
5994 if (feature
!= NULL
)
5996 static const char *const vector_regs
[] = {
5997 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
5998 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
5999 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6000 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6004 for (i
= 0; i
< ppc_num_gprs
; i
++)
6005 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6008 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6009 PPC_VSCR_REGNUM
, "vscr");
6010 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6011 PPC_VRSAVE_REGNUM
, "vrsave");
6013 if (have_spe
|| !valid_p
)
6015 tdesc_data_cleanup (tdesc_data
);
6023 /* Check for POWER7 VSX registers support. */
6024 feature
= tdesc_find_feature (tdesc
,
6025 "org.gnu.gdb.power.vsx");
6027 if (feature
!= NULL
)
6029 static const char *const vsx_regs
[] = {
6030 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6031 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6032 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6033 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6034 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6040 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6041 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6042 PPC_VSR0_UPPER_REGNUM
+ i
,
6046 tdesc_data_cleanup (tdesc_data
);
6055 /* On machines supporting the SPE APU, the general-purpose registers
6056 are 64 bits long. There are SIMD vector instructions to treat them
6057 as pairs of floats, but the rest of the instruction set treats them
6058 as 32-bit registers, and only operates on their lower halves.
6060 In the GDB regcache, we treat their high and low halves as separate
6061 registers. The low halves we present as the general-purpose
6062 registers, and then we have pseudo-registers that stitch together
6063 the upper and lower halves and present them as pseudo-registers.
6065 Thus, the target description is expected to supply the upper
6066 halves separately. */
6068 feature
= tdesc_find_feature (tdesc
,
6069 "org.gnu.gdb.power.spe");
6070 if (feature
!= NULL
)
6072 static const char *const upper_spe
[] = {
6073 "ev0h", "ev1h", "ev2h", "ev3h",
6074 "ev4h", "ev5h", "ev6h", "ev7h",
6075 "ev8h", "ev9h", "ev10h", "ev11h",
6076 "ev12h", "ev13h", "ev14h", "ev15h",
6077 "ev16h", "ev17h", "ev18h", "ev19h",
6078 "ev20h", "ev21h", "ev22h", "ev23h",
6079 "ev24h", "ev25h", "ev26h", "ev27h",
6080 "ev28h", "ev29h", "ev30h", "ev31h"
6084 for (i
= 0; i
< ppc_num_gprs
; i
++)
6085 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6086 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6088 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6089 PPC_SPE_ACC_REGNUM
, "acc");
6090 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6091 PPC_SPE_FSCR_REGNUM
, "spefscr");
6093 if (have_mq
|| have_fpu
|| !valid_p
)
6095 tdesc_data_cleanup (tdesc_data
);
6104 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6105 complain for a 32-bit binary on a 64-bit target; we do not yet
6106 support that. For instance, the 32-bit ABI routines expect
6109 As long as there isn't an explicit target description, we'll
6110 choose one based on the BFD architecture and get a word size
6111 matching the binary (probably powerpc:common or
6112 powerpc:common64). So there is only trouble if a 64-bit target
6113 supplies a 64-bit description while debugging a 32-bit
6115 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6117 tdesc_data_cleanup (tdesc_data
);
6124 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6127 elf_abi
= POWERPC_ELF_V1
;
6130 elf_abi
= POWERPC_ELF_V2
;
6137 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6139 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6140 Tag_GNU_Power_ABI_FP
) & 3)
6143 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6146 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6153 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6155 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6156 Tag_GNU_Power_ABI_FP
) >> 2)
6159 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6162 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6169 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6171 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6172 Tag_GNU_Power_ABI_Vector
))
6175 vector_abi
= POWERPC_VEC_GENERIC
;
6178 vector_abi
= POWERPC_VEC_ALTIVEC
;
6181 vector_abi
= POWERPC_VEC_SPE
;
6189 /* At this point, the only supported ELF-based 64-bit little-endian
6190 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6191 default. All other supported ELF-based operating systems use the
6192 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6193 e.g. because we run a legacy binary, or have attached to a process
6194 and have not found any associated binary file, set the default
6195 according to this heuristic. */
6196 if (elf_abi
== POWERPC_ELF_AUTO
)
6198 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6199 elf_abi
= POWERPC_ELF_V2
;
6201 elf_abi
= POWERPC_ELF_V1
;
6204 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6206 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6209 soft_float
= !have_fpu
;
6211 /* If we have a hard float binary or setting but no floating point
6212 registers, downgrade to soft float anyway. We're still somewhat
6213 useful in this scenario. */
6214 if (!soft_float
&& !have_fpu
)
6217 /* Similarly for vector registers. */
6218 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6219 vector_abi
= POWERPC_VEC_GENERIC
;
6221 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6222 vector_abi
= POWERPC_VEC_GENERIC
;
6224 if (vector_abi
== POWERPC_VEC_AUTO
)
6227 vector_abi
= POWERPC_VEC_ALTIVEC
;
6229 vector_abi
= POWERPC_VEC_SPE
;
6231 vector_abi
= POWERPC_VEC_GENERIC
;
6234 /* Do not limit the vector ABI based on available hardware, since we
6235 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6237 /* Find a candidate among extant architectures. */
6238 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6240 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6242 /* Word size in the various PowerPC bfd_arch_info structs isn't
6243 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6244 separate word size check. */
6245 tdep
= gdbarch_tdep (arches
->gdbarch
);
6246 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6248 if (tdep
&& tdep
->soft_float
!= soft_float
)
6250 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6252 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6254 if (tdep
&& tdep
->wordsize
== wordsize
)
6256 if (tdesc_data
!= NULL
)
6257 tdesc_data_cleanup (tdesc_data
);
6258 return arches
->gdbarch
;
6262 /* None found, create a new architecture from INFO, whose bfd_arch_info
6263 validity depends on the source:
6264 - executable useless
6265 - rs6000_host_arch() good
6267 - "set arch" trust blindly
6268 - GDB startup useless but harmless */
6270 tdep
= XCNEW (struct gdbarch_tdep
);
6271 tdep
->wordsize
= wordsize
;
6272 tdep
->elf_abi
= elf_abi
;
6273 tdep
->soft_float
= soft_float
;
6274 tdep
->long_double_abi
= long_double_abi
;
6275 tdep
->vector_abi
= vector_abi
;
6277 gdbarch
= gdbarch_alloc (&info
, tdep
);
6279 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6280 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6281 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6282 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6283 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6284 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6285 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6286 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6288 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6289 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6290 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6291 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6292 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6293 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6294 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6295 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6297 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6298 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6299 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6300 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6302 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6303 GDB traditionally called it "ps", though, so let GDB add an
6305 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6308 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6310 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6312 /* Set lr_frame_offset. */
6314 tdep
->lr_frame_offset
= 16;
6316 tdep
->lr_frame_offset
= 4;
6318 if (have_spe
|| have_dfp
|| have_vsx
)
6320 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6321 set_gdbarch_pseudo_register_write (gdbarch
,
6322 rs6000_pseudo_register_write
);
6323 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6324 rs6000_ax_pseudo_register_collect
);
6327 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6329 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6331 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6334 num_pseudoregs
+= 32;
6336 num_pseudoregs
+= 16;
6338 /* Include both VSX and Extended FP registers. */
6339 num_pseudoregs
+= 96;
6341 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6343 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6344 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6345 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6346 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6347 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6348 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6349 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6350 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6351 set_gdbarch_char_signed (gdbarch
, 0);
6353 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6356 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6358 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6359 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6360 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6362 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6363 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6366 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6367 else if (wordsize
== 8)
6368 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6370 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6371 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6372 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6374 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6376 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6377 rs6000_breakpoint::kind_from_pc
);
6378 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6379 rs6000_breakpoint::bp_from_kind
);
6381 /* The value of symbols of type N_SO and N_FUN maybe null when
6383 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6385 /* Handles single stepping of atomic sequences. */
6386 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6388 /* Not sure on this. FIXMEmgo */
6389 set_gdbarch_frame_args_skip (gdbarch
, 8);
6391 /* Helpers for function argument information. */
6392 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6395 set_gdbarch_in_solib_return_trampoline
6396 (gdbarch
, rs6000_in_solib_return_trampoline
);
6397 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6399 /* Hook in the DWARF CFI frame unwinder. */
6400 dwarf2_append_unwinders (gdbarch
);
6401 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6403 /* Frame handling. */
6404 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6406 /* Setup displaced stepping. */
6407 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6408 ppc_displaced_step_copy_insn
);
6409 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6410 ppc_displaced_step_hw_singlestep
);
6411 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6412 set_gdbarch_displaced_step_location (gdbarch
,
6413 displaced_step_at_entry_point
);
6415 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6417 /* Hook in ABI-specific overrides, if they have been registered. */
6418 info
.target_desc
= tdesc
;
6419 info
.tdesc_data
= tdesc_data
;
6420 gdbarch_init_osabi (info
, gdbarch
);
6424 case GDB_OSABI_LINUX
:
6425 case GDB_OSABI_NETBSD
:
6426 case GDB_OSABI_UNKNOWN
:
6427 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6428 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6429 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6430 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6431 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6434 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6436 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6437 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6438 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6439 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6440 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6443 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6444 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6445 rs6000_pseudo_register_reggroup_p
);
6446 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6448 /* Override the normal target description method to make the SPE upper
6449 halves anonymous. */
6450 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6452 /* Choose register numbers for all supported pseudo-registers. */
6453 tdep
->ppc_ev0_regnum
= -1;
6454 tdep
->ppc_dl0_regnum
= -1;
6455 tdep
->ppc_vsr0_regnum
= -1;
6456 tdep
->ppc_efpr0_regnum
= -1;
6458 cur_reg
= gdbarch_num_regs (gdbarch
);
6462 tdep
->ppc_ev0_regnum
= cur_reg
;
6467 tdep
->ppc_dl0_regnum
= cur_reg
;
6472 tdep
->ppc_vsr0_regnum
= cur_reg
;
6474 tdep
->ppc_efpr0_regnum
= cur_reg
;
6478 gdb_assert (gdbarch_num_regs (gdbarch
)
6479 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
6481 /* Register the ravenscar_arch_ops. */
6482 if (mach
== bfd_mach_ppc_e500
)
6483 register_e500_ravenscar_ops (gdbarch
);
6485 register_ppc_ravenscar_ops (gdbarch
);
6487 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
6488 set_gdbarch_valid_disassembler_options (gdbarch
,
6489 disassembler_options_powerpc ());
6495 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6497 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6502 /* FIXME: Dump gdbarch_tdep. */
6505 /* PowerPC-specific commands. */
6508 set_powerpc_command (const char *args
, int from_tty
)
6510 printf_unfiltered (_("\
6511 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6512 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6516 show_powerpc_command (const char *args
, int from_tty
)
6518 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6522 powerpc_set_soft_float (const char *args
, int from_tty
,
6523 struct cmd_list_element
*c
)
6525 struct gdbarch_info info
;
6527 /* Update the architecture. */
6528 gdbarch_info_init (&info
);
6529 if (!gdbarch_update_p (info
))
6530 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6534 powerpc_set_vector_abi (const char *args
, int from_tty
,
6535 struct cmd_list_element
*c
)
6537 struct gdbarch_info info
;
6540 for (vector_abi
= POWERPC_VEC_AUTO
;
6541 vector_abi
!= POWERPC_VEC_LAST
;
6543 if (strcmp (powerpc_vector_abi_string
,
6544 powerpc_vector_strings
[vector_abi
]) == 0)
6546 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6550 if (vector_abi
== POWERPC_VEC_LAST
)
6551 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6552 powerpc_vector_abi_string
);
6554 /* Update the architecture. */
6555 gdbarch_info_init (&info
);
6556 if (!gdbarch_update_p (info
))
6557 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6560 /* Show the current setting of the exact watchpoints flag. */
6563 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6564 struct cmd_list_element
*c
,
6567 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6570 /* Read a PPC instruction from memory. */
6573 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6575 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6576 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6578 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6581 /* Return non-zero if the instructions at PC match the series
6582 described in PATTERN, or zero otherwise. PATTERN is an array of
6583 'struct ppc_insn_pattern' objects, terminated by an entry whose
6586 When the match is successful, fill INSNS[i] with what PATTERN[i]
6587 matched. If PATTERN[i] is optional, and the instruction wasn't
6588 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
6589 INSNS should have as many elements as PATTERN, minus the terminator.
6590 Note that, if PATTERN contains optional instructions which aren't
6591 present in memory, then INSNS will have holes, so INSNS[i] isn't
6592 necessarily the i'th instruction in memory. */
6595 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6596 const struct ppc_insn_pattern
*pattern
,
6597 unsigned int *insns
)
6602 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6605 insn
= read_insn (frame
, pc
);
6607 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6613 else if (!pattern
[i
].optional
)
6620 /* Return the 'd' field of the d-form instruction INSN, properly
6624 ppc_insn_d_field (unsigned int insn
)
6626 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6629 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6630 zero bits concatenated at the right, and properly
6634 ppc_insn_ds_field (unsigned int insn
)
6636 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6639 /* Initialization code. */
6642 _initialize_rs6000_tdep (void)
6644 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6645 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6647 /* Initialize the standard target descriptions. */
6648 initialize_tdesc_powerpc_32 ();
6649 initialize_tdesc_powerpc_altivec32 ();
6650 initialize_tdesc_powerpc_vsx32 ();
6651 initialize_tdesc_powerpc_403 ();
6652 initialize_tdesc_powerpc_403gc ();
6653 initialize_tdesc_powerpc_405 ();
6654 initialize_tdesc_powerpc_505 ();
6655 initialize_tdesc_powerpc_601 ();
6656 initialize_tdesc_powerpc_602 ();
6657 initialize_tdesc_powerpc_603 ();
6658 initialize_tdesc_powerpc_604 ();
6659 initialize_tdesc_powerpc_64 ();
6660 initialize_tdesc_powerpc_altivec64 ();
6661 initialize_tdesc_powerpc_vsx64 ();
6662 initialize_tdesc_powerpc_7400 ();
6663 initialize_tdesc_powerpc_750 ();
6664 initialize_tdesc_powerpc_860 ();
6665 initialize_tdesc_powerpc_e500 ();
6666 initialize_tdesc_rs6000 ();
6668 /* Add root prefix command for all "set powerpc"/"show powerpc"
6670 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6671 _("Various PowerPC-specific commands."),
6672 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6674 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6675 _("Various PowerPC-specific commands."),
6676 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6678 /* Add a command to allow the user to force the ABI. */
6679 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6680 &powerpc_soft_float_global
,
6681 _("Set whether to use a soft-float ABI."),
6682 _("Show whether to use a soft-float ABI."),
6684 powerpc_set_soft_float
, NULL
,
6685 &setpowerpccmdlist
, &showpowerpccmdlist
);
6687 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6688 &powerpc_vector_abi_string
,
6689 _("Set the vector ABI."),
6690 _("Show the vector ABI."),
6691 NULL
, powerpc_set_vector_abi
, NULL
,
6692 &setpowerpccmdlist
, &showpowerpccmdlist
);
6694 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6695 &target_exact_watchpoints
,
6697 Set whether to use just one debug register for watchpoints on scalars."),
6699 Show whether to use just one debug register for watchpoints on scalars."),
6701 If true, GDB will use only one debug register when watching a variable of\n\
6702 scalar type, thus assuming that the variable is accessed through the address\n\
6703 of its first byte."),
6704 NULL
, show_powerpc_exact_watchpoints
,
6705 &setpowerpccmdlist
, &showpowerpccmdlist
);