1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "libbfd.h" /* for bfd_default_set_arch_mach */
47 #include "coff/internal.h" /* for libcoff.h */
48 #include "libcoff.h" /* for xcoff_data */
49 #include "coff/xcoff.h"
54 #include "elf/ppc64.h"
56 #include "solib-svr4.h"
58 #include "ppc-ravenscar-thread.h"
62 #include "trad-frame.h"
63 #include "frame-unwind.h"
64 #include "frame-base.h"
66 #include "features/rs6000/powerpc-32.c"
67 #include "features/rs6000/powerpc-altivec32.c"
68 #include "features/rs6000/powerpc-vsx32.c"
69 #include "features/rs6000/powerpc-403.c"
70 #include "features/rs6000/powerpc-403gc.c"
71 #include "features/rs6000/powerpc-405.c"
72 #include "features/rs6000/powerpc-505.c"
73 #include "features/rs6000/powerpc-601.c"
74 #include "features/rs6000/powerpc-602.c"
75 #include "features/rs6000/powerpc-603.c"
76 #include "features/rs6000/powerpc-604.c"
77 #include "features/rs6000/powerpc-64.c"
78 #include "features/rs6000/powerpc-altivec64.c"
79 #include "features/rs6000/powerpc-vsx64.c"
80 #include "features/rs6000/powerpc-7400.c"
81 #include "features/rs6000/powerpc-750.c"
82 #include "features/rs6000/powerpc-860.c"
83 #include "features/rs6000/powerpc-e500.c"
84 #include "features/rs6000/rs6000.c"
86 /* Determine if regnum is an SPE pseudo-register. */
87 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
88 && (regnum) >= (tdep)->ppc_ev0_regnum \
89 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
91 /* Determine if regnum is a decimal float pseudo-register. */
92 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
93 && (regnum) >= (tdep)->ppc_dl0_regnum \
94 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
96 /* Determine if regnum is a POWER7 VSX register. */
97 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
98 && (regnum) >= (tdep)->ppc_vsr0_regnum \
99 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
101 /* Determine if regnum is a POWER7 Extended FP register. */
102 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_efpr0_regnum \
104 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
106 /* The list of available "set powerpc ..." and "show powerpc ..."
108 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
109 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
111 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
113 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
114 static const char *const powerpc_vector_strings
[] =
123 /* A variable that can be configured by the user. */
124 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
125 static const char *powerpc_vector_abi_string
= "auto";
127 /* To be used by skip_prologue. */
129 struct rs6000_framedata
131 int offset
; /* total size of frame --- the distance
132 by which we decrement sp to allocate
134 int saved_gpr
; /* smallest # of saved gpr */
135 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
136 int saved_fpr
; /* smallest # of saved fpr */
137 int saved_vr
; /* smallest # of saved vr */
138 int saved_ev
; /* smallest # of saved ev */
139 int alloca_reg
; /* alloca register number (frame ptr) */
140 char frameless
; /* true if frameless functions. */
141 char nosavedpc
; /* true if pc not saved. */
142 char used_bl
; /* true if link register clobbered */
143 int gpr_offset
; /* offset of saved gprs from prev sp */
144 int fpr_offset
; /* offset of saved fprs from prev sp */
145 int vr_offset
; /* offset of saved vrs from prev sp */
146 int ev_offset
; /* offset of saved evs from prev sp */
147 int lr_offset
; /* offset of saved lr */
148 int lr_register
; /* register of saved lr, if trustworthy */
149 int cr_offset
; /* offset of saved cr */
150 int vrsave_offset
; /* offset of saved vrsave register */
154 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
156 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 if (tdep
->ppc_vsr0_regnum
< 0)
162 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
163 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
166 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
168 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
170 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
171 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
174 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
178 /* Return true if REGNO is an SPE register, false otherwise. */
180 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
182 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
184 /* Is it a reference to EV0 -- EV31, and do we have those? */
185 if (IS_SPE_PSEUDOREG (tdep
, regno
))
188 /* Is it a reference to one of the raw upper GPR halves? */
189 if (tdep
->ppc_ev0_upper_regnum
>= 0
190 && tdep
->ppc_ev0_upper_regnum
<= regno
191 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
194 /* Is it a reference to the 64-bit accumulator, and do we have that? */
195 if (tdep
->ppc_acc_regnum
>= 0
196 && tdep
->ppc_acc_regnum
== regno
)
199 /* Is it a reference to the SPE floating-point status and control register,
200 and do we have that? */
201 if (tdep
->ppc_spefscr_regnum
>= 0
202 && tdep
->ppc_spefscr_regnum
== regno
)
209 /* Return non-zero if the architecture described by GDBARCH has
210 floating-point registers (f0 --- f31 and fpscr). */
212 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 return (tdep
->ppc_fp0_regnum
>= 0
217 && tdep
->ppc_fpscr_regnum
>= 0);
220 /* Return non-zero if the architecture described by GDBARCH has
221 VSX registers (vsr0 --- vsr63). */
223 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 return tdep
->ppc_vsr0_regnum
>= 0;
230 /* Return non-zero if the architecture described by GDBARCH has
231 Altivec registers (vr0 --- vr31, vrsave and vscr). */
233 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
237 return (tdep
->ppc_vr0_regnum
>= 0
238 && tdep
->ppc_vrsave_regnum
>= 0);
241 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
244 This is a helper function for init_sim_regno_table, constructing
245 the table mapping GDB register numbers to sim register numbers; we
246 initialize every element in that table to -1 before we start
249 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
251 /* Make sure we don't try to assign any given GDB register a sim
252 register number more than once. */
253 gdb_assert (table
[gdb_regno
] == -1);
254 table
[gdb_regno
] = sim_regno
;
258 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
259 numbers to simulator register numbers, based on the values placed
260 in the ARCH->tdep->ppc_foo_regnum members. */
262 init_sim_regno_table (struct gdbarch
*arch
)
264 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
265 int total_regs
= gdbarch_num_regs (arch
);
266 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
268 static const char *const segment_regs
[] = {
269 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
270 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
273 /* Presume that all registers not explicitly mentioned below are
274 unavailable from the sim. */
275 for (i
= 0; i
< total_regs
; i
++)
278 /* General-purpose registers. */
279 for (i
= 0; i
< ppc_num_gprs
; i
++)
280 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
282 /* Floating-point registers. */
283 if (tdep
->ppc_fp0_regnum
>= 0)
284 for (i
= 0; i
< ppc_num_fprs
; i
++)
285 set_sim_regno (sim_regno
,
286 tdep
->ppc_fp0_regnum
+ i
,
287 sim_ppc_f0_regnum
+ i
);
288 if (tdep
->ppc_fpscr_regnum
>= 0)
289 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
291 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
292 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
293 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
295 /* Segment registers. */
296 for (i
= 0; i
< ppc_num_srs
; i
++)
300 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
302 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
305 /* Altivec registers. */
306 if (tdep
->ppc_vr0_regnum
>= 0)
308 for (i
= 0; i
< ppc_num_vrs
; i
++)
309 set_sim_regno (sim_regno
,
310 tdep
->ppc_vr0_regnum
+ i
,
311 sim_ppc_vr0_regnum
+ i
);
313 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
314 we can treat this more like the other cases. */
315 set_sim_regno (sim_regno
,
316 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
317 sim_ppc_vscr_regnum
);
319 /* vsave is a special-purpose register, so the code below handles it. */
321 /* SPE APU (E500) registers. */
322 if (tdep
->ppc_ev0_upper_regnum
>= 0)
323 for (i
= 0; i
< ppc_num_gprs
; i
++)
324 set_sim_regno (sim_regno
,
325 tdep
->ppc_ev0_upper_regnum
+ i
,
326 sim_ppc_rh0_regnum
+ i
);
327 if (tdep
->ppc_acc_regnum
>= 0)
328 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
329 /* spefscr is a special-purpose register, so the code below handles it. */
332 /* Now handle all special-purpose registers. Verify that they
333 haven't mistakenly been assigned numbers by any of the above
335 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
337 const char *spr_name
= sim_spr_register_name (i
);
340 if (spr_name
!= NULL
)
341 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
344 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
348 /* Drop the initialized array into place. */
349 tdep
->sim_regno
= sim_regno
;
353 /* Given a GDB register number REG, return the corresponding SIM
356 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
358 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
361 if (tdep
->sim_regno
== NULL
)
362 init_sim_regno_table (gdbarch
);
365 && reg
<= gdbarch_num_regs (gdbarch
)
366 + gdbarch_num_pseudo_regs (gdbarch
));
367 sim_regno
= tdep
->sim_regno
[reg
];
372 return LEGACY_SIM_REGNO_IGNORE
;
377 /* Register set support functions. */
379 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
380 Write the register to REGCACHE. */
383 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
384 const gdb_byte
*regs
, size_t offset
, int regsize
)
386 if (regnum
!= -1 && offset
!= -1)
390 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
391 int gdb_regsize
= register_size (gdbarch
, regnum
);
392 if (gdb_regsize
< regsize
393 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
394 offset
+= regsize
- gdb_regsize
;
396 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
400 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
401 in a field REGSIZE wide. Zero pad as necessary. */
404 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
405 gdb_byte
*regs
, size_t offset
, int regsize
)
407 if (regnum
!= -1 && offset
!= -1)
411 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
412 int gdb_regsize
= register_size (gdbarch
, regnum
);
413 if (gdb_regsize
< regsize
)
415 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
417 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
418 offset
+= regsize
- gdb_regsize
;
421 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
422 regsize
- gdb_regsize
);
425 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
430 ppc_greg_offset (struct gdbarch
*gdbarch
,
431 struct gdbarch_tdep
*tdep
,
432 const struct ppc_reg_offsets
*offsets
,
436 *regsize
= offsets
->gpr_size
;
437 if (regnum
>= tdep
->ppc_gp0_regnum
438 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
439 return (offsets
->r0_offset
440 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
442 if (regnum
== gdbarch_pc_regnum (gdbarch
))
443 return offsets
->pc_offset
;
445 if (regnum
== tdep
->ppc_ps_regnum
)
446 return offsets
->ps_offset
;
448 if (regnum
== tdep
->ppc_lr_regnum
)
449 return offsets
->lr_offset
;
451 if (regnum
== tdep
->ppc_ctr_regnum
)
452 return offsets
->ctr_offset
;
454 *regsize
= offsets
->xr_size
;
455 if (regnum
== tdep
->ppc_cr_regnum
)
456 return offsets
->cr_offset
;
458 if (regnum
== tdep
->ppc_xer_regnum
)
459 return offsets
->xer_offset
;
461 if (regnum
== tdep
->ppc_mq_regnum
)
462 return offsets
->mq_offset
;
468 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
469 const struct ppc_reg_offsets
*offsets
,
472 if (regnum
>= tdep
->ppc_fp0_regnum
473 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
474 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
476 if (regnum
== tdep
->ppc_fpscr_regnum
)
477 return offsets
->fpscr_offset
;
483 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
484 const struct ppc_reg_offsets
*offsets
,
487 if (regnum
>= tdep
->ppc_vr0_regnum
488 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
489 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
491 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
492 return offsets
->vscr_offset
;
494 if (regnum
== tdep
->ppc_vrsave_regnum
)
495 return offsets
->vrsave_offset
;
500 /* Supply register REGNUM in the general-purpose register set REGSET
501 from the buffer specified by GREGS and LEN to register cache
502 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
505 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
506 int regnum
, const void *gregs
, size_t len
)
508 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
510 const struct ppc_reg_offsets
*offsets
= regset
->regmap
;
517 int gpr_size
= offsets
->gpr_size
;
519 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
520 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
521 i
++, offset
+= gpr_size
)
522 ppc_supply_reg (regcache
, i
, gregs
, offset
, gpr_size
);
524 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
525 gregs
, offsets
->pc_offset
, gpr_size
);
526 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
527 gregs
, offsets
->ps_offset
, gpr_size
);
528 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
529 gregs
, offsets
->lr_offset
, gpr_size
);
530 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
531 gregs
, offsets
->ctr_offset
, gpr_size
);
532 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
533 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
535 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
536 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
537 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
541 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
542 ppc_supply_reg (regcache
, regnum
, gregs
, offset
, regsize
);
545 /* Supply register REGNUM in the floating-point register set REGSET
546 from the buffer specified by FPREGS and LEN to register cache
547 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
550 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
551 int regnum
, const void *fpregs
, size_t len
)
553 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
554 struct gdbarch_tdep
*tdep
;
555 const struct ppc_reg_offsets
*offsets
;
558 if (!ppc_floating_point_unit_p (gdbarch
))
561 tdep
= gdbarch_tdep (gdbarch
);
562 offsets
= regset
->regmap
;
567 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
568 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
570 ppc_supply_reg (regcache
, i
, fpregs
, offset
, 8);
572 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
573 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
577 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
578 ppc_supply_reg (regcache
, regnum
, fpregs
, offset
,
579 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
582 /* Supply register REGNUM in the VSX register set REGSET
583 from the buffer specified by VSXREGS and LEN to register cache
584 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
587 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
588 int regnum
, const void *vsxregs
, size_t len
)
590 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
591 struct gdbarch_tdep
*tdep
;
593 if (!ppc_vsx_support_p (gdbarch
))
596 tdep
= gdbarch_tdep (gdbarch
);
602 for (i
= tdep
->ppc_vsr0_upper_regnum
;
603 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
605 ppc_supply_reg (regcache
, i
, vsxregs
, 0, 8);
610 ppc_supply_reg (regcache
, regnum
, vsxregs
, 0, 8);
613 /* Supply register REGNUM in the Altivec register set REGSET
614 from the buffer specified by VRREGS and LEN to register cache
615 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
618 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
619 int regnum
, const void *vrregs
, size_t len
)
621 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
622 struct gdbarch_tdep
*tdep
;
623 const struct ppc_reg_offsets
*offsets
;
626 if (!ppc_altivec_support_p (gdbarch
))
629 tdep
= gdbarch_tdep (gdbarch
);
630 offsets
= regset
->regmap
;
635 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
636 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
638 ppc_supply_reg (regcache
, i
, vrregs
, offset
, 16);
640 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
641 vrregs
, offsets
->vscr_offset
, 4);
643 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
644 vrregs
, offsets
->vrsave_offset
, 4);
648 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
649 if (regnum
!= tdep
->ppc_vrsave_regnum
650 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
651 ppc_supply_reg (regcache
, regnum
, vrregs
, offset
, 16);
653 ppc_supply_reg (regcache
, regnum
,
657 /* Collect register REGNUM in the general-purpose register set
658 REGSET from register cache REGCACHE into the buffer specified by
659 GREGS and LEN. If REGNUM is -1, do this for all registers in
663 ppc_collect_gregset (const struct regset
*regset
,
664 const struct regcache
*regcache
,
665 int regnum
, void *gregs
, size_t len
)
667 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
668 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
669 const struct ppc_reg_offsets
*offsets
= regset
->regmap
;
676 int gpr_size
= offsets
->gpr_size
;
678 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
679 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
680 i
++, offset
+= gpr_size
)
681 ppc_collect_reg (regcache
, i
, gregs
, offset
, gpr_size
);
683 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
684 gregs
, offsets
->pc_offset
, gpr_size
);
685 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
686 gregs
, offsets
->ps_offset
, gpr_size
);
687 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
688 gregs
, offsets
->lr_offset
, gpr_size
);
689 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
690 gregs
, offsets
->ctr_offset
, gpr_size
);
691 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
692 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
693 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
694 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
695 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
696 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
700 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
701 ppc_collect_reg (regcache
, regnum
, gregs
, offset
, regsize
);
704 /* Collect register REGNUM in the floating-point register set
705 REGSET from register cache REGCACHE into the buffer specified by
706 FPREGS and LEN. If REGNUM is -1, do this for all registers in
710 ppc_collect_fpregset (const struct regset
*regset
,
711 const struct regcache
*regcache
,
712 int regnum
, void *fpregs
, size_t len
)
714 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
715 struct gdbarch_tdep
*tdep
;
716 const struct ppc_reg_offsets
*offsets
;
719 if (!ppc_floating_point_unit_p (gdbarch
))
722 tdep
= gdbarch_tdep (gdbarch
);
723 offsets
= regset
->regmap
;
728 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
729 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
731 ppc_collect_reg (regcache
, i
, fpregs
, offset
, 8);
733 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
734 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
738 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
739 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
,
740 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
743 /* Collect register REGNUM in the VSX register set
744 REGSET from register cache REGCACHE into the buffer specified by
745 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
749 ppc_collect_vsxregset (const struct regset
*regset
,
750 const struct regcache
*regcache
,
751 int regnum
, void *vsxregs
, size_t len
)
753 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
754 struct gdbarch_tdep
*tdep
;
756 if (!ppc_vsx_support_p (gdbarch
))
759 tdep
= gdbarch_tdep (gdbarch
);
765 for (i
= tdep
->ppc_vsr0_upper_regnum
;
766 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
768 ppc_collect_reg (regcache
, i
, vsxregs
, 0, 8);
773 ppc_collect_reg (regcache
, regnum
, vsxregs
, 0, 8);
777 /* Collect register REGNUM in the Altivec register set
778 REGSET from register cache REGCACHE into the buffer specified by
779 VRREGS and LEN. If REGNUM is -1, do this for all registers in
783 ppc_collect_vrregset (const struct regset
*regset
,
784 const struct regcache
*regcache
,
785 int regnum
, void *vrregs
, size_t len
)
787 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
788 struct gdbarch_tdep
*tdep
;
789 const struct ppc_reg_offsets
*offsets
;
792 if (!ppc_altivec_support_p (gdbarch
))
795 tdep
= gdbarch_tdep (gdbarch
);
796 offsets
= regset
->regmap
;
801 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
802 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
804 ppc_collect_reg (regcache
, i
, vrregs
, offset
, 16);
806 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
807 vrregs
, offsets
->vscr_offset
, 4);
809 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
810 vrregs
, offsets
->vrsave_offset
, 4);
814 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
815 if (regnum
!= tdep
->ppc_vrsave_regnum
816 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
817 ppc_collect_reg (regcache
, regnum
, vrregs
, offset
, 16);
819 ppc_collect_reg (regcache
, regnum
,
825 insn_changes_sp_or_jumps (unsigned long insn
)
827 int opcode
= (insn
>> 26) & 0x03f;
828 int sd
= (insn
>> 21) & 0x01f;
829 int a
= (insn
>> 16) & 0x01f;
830 int subcode
= (insn
>> 1) & 0x3ff;
832 /* Changes the stack pointer. */
834 /* NOTE: There are many ways to change the value of a given register.
835 The ways below are those used when the register is R1, the SP,
836 in a funtion's epilogue. */
838 if (opcode
== 31 && subcode
== 444 && a
== 1)
839 return 1; /* mr R1,Rn */
840 if (opcode
== 14 && sd
== 1)
841 return 1; /* addi R1,Rn,simm */
842 if (opcode
== 58 && sd
== 1)
843 return 1; /* ld R1,ds(Rn) */
845 /* Transfers control. */
851 if (opcode
== 19 && subcode
== 16)
853 if (opcode
== 19 && subcode
== 528)
854 return 1; /* bcctr */
859 /* Return true if we are in the function's epilogue, i.e. after the
860 instruction that destroyed the function's stack frame.
862 1) scan forward from the point of execution:
863 a) If you find an instruction that modifies the stack pointer
864 or transfers control (except a return), execution is not in
866 b) Stop scanning if you find a return instruction or reach the
867 end of the function or reach the hard limit for the size of
869 2) scan backward from the point of execution:
870 a) If you find an instruction that modifies the stack pointer,
871 execution *is* in an epilogue, return.
872 b) Stop scanning if you reach an instruction that transfers
873 control or the beginning of the function or reach the hard
874 limit for the size of an epilogue. */
877 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
878 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
880 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
881 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
882 bfd_byte insn_buf
[PPC_INSN_SIZE
];
883 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
886 /* Find the search limits based on function boundaries and hard limit. */
888 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
891 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
892 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
894 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
895 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
897 /* Scan forward until next 'blr'. */
899 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
901 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
903 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
904 if (insn
== 0x4e800020)
906 /* Assume a bctr is a tail call unless it points strictly within
908 if (insn
== 0x4e800420)
910 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
911 tdep
->ppc_ctr_regnum
);
912 if (ctr
> func_start
&& ctr
< func_end
)
917 if (insn_changes_sp_or_jumps (insn
))
921 /* Scan backward until adjustment to stack pointer (R1). */
923 for (scan_pc
= pc
- PPC_INSN_SIZE
;
924 scan_pc
>= epilogue_start
;
925 scan_pc
-= PPC_INSN_SIZE
)
927 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
929 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
930 if (insn_changes_sp_or_jumps (insn
))
937 /* Implementation of gdbarch_in_function_epilogue_p. */
940 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
942 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
946 /* Get the ith function argument for the current function. */
948 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
951 return get_frame_register_unsigned (frame
, 3 + argi
);
954 /* Sequence of bytes for breakpoint instruction. */
956 static const unsigned char *
957 rs6000_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
960 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
961 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
963 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
964 return big_breakpoint
;
966 return little_breakpoint
;
969 /* Instruction masks for displaced stepping. */
970 #define BRANCH_MASK 0xfc000000
971 #define BP_MASK 0xFC0007FE
972 #define B_INSN 0x48000000
973 #define BC_INSN 0x40000000
974 #define BXL_INSN 0x4c000000
975 #define BP_INSN 0x7C000008
977 /* Fix up the state of registers and memory after having single-stepped
978 a displaced instruction. */
980 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
981 struct displaced_step_closure
*closure
,
982 CORE_ADDR from
, CORE_ADDR to
,
983 struct regcache
*regs
)
985 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
986 /* Since we use simple_displaced_step_copy_insn, our closure is a
987 copy of the instruction. */
988 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
989 PPC_INSN_SIZE
, byte_order
);
991 /* Offset for non PC-relative instructions. */
992 LONGEST offset
= PPC_INSN_SIZE
;
994 opcode
= insn
& BRANCH_MASK
;
997 fprintf_unfiltered (gdb_stdlog
,
998 "displaced: (ppc) fixup (%s, %s)\n",
999 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1002 /* Handle PC-relative branch instructions. */
1003 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1005 ULONGEST current_pc
;
1007 /* Read the current PC value after the instruction has been executed
1008 in a displaced location. Calculate the offset to be applied to the
1009 original PC value before the displaced stepping. */
1010 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1012 offset
= current_pc
- to
;
1014 if (opcode
!= BXL_INSN
)
1016 /* Check for AA bit indicating whether this is an absolute
1017 addressing or PC-relative (1: absolute, 0: relative). */
1020 /* PC-relative addressing is being used in the branch. */
1021 if (debug_displaced
)
1024 "displaced: (ppc) branch instruction: %s\n"
1025 "displaced: (ppc) adjusted PC from %s to %s\n",
1026 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1027 paddress (gdbarch
, from
+ offset
));
1029 regcache_cooked_write_unsigned (regs
,
1030 gdbarch_pc_regnum (gdbarch
),
1036 /* If we're here, it means we have a branch to LR or CTR. If the
1037 branch was taken, the offset is probably greater than 4 (the next
1038 instruction), so it's safe to assume that an offset of 4 means we
1039 did not take the branch. */
1040 if (offset
== PPC_INSN_SIZE
)
1041 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1042 from
+ PPC_INSN_SIZE
);
1045 /* Check for LK bit indicating whether we should set the link
1046 register to point to the next instruction
1047 (1: Set, 0: Don't set). */
1050 /* Link register needs to be set to the next instruction's PC. */
1051 regcache_cooked_write_unsigned (regs
,
1052 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1053 from
+ PPC_INSN_SIZE
);
1054 if (debug_displaced
)
1055 fprintf_unfiltered (gdb_stdlog
,
1056 "displaced: (ppc) adjusted LR to %s\n",
1057 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1061 /* Check for breakpoints in the inferior. If we've found one, place the PC
1062 right at the breakpoint instruction. */
1063 else if ((insn
& BP_MASK
) == BP_INSN
)
1064 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1066 /* Handle any other instructions that do not fit in the categories above. */
1067 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1071 /* Always use hardware single-stepping to execute the
1072 displaced instruction. */
1074 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1075 struct displaced_step_closure
*closure
)
1080 /* Instruction masks used during single-stepping of atomic sequences. */
1081 #define LWARX_MASK 0xfc0007fe
1082 #define LWARX_INSTRUCTION 0x7c000028
1083 #define LDARX_INSTRUCTION 0x7c0000A8
1084 #define STWCX_MASK 0xfc0007ff
1085 #define STWCX_INSTRUCTION 0x7c00012d
1086 #define STDCX_INSTRUCTION 0x7c0001ad
1088 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1089 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1090 is found, attempt to step through it. A breakpoint is placed at the end of
1094 ppc_deal_with_atomic_sequence (struct frame_info
*frame
)
1096 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1097 struct address_space
*aspace
= get_frame_address_space (frame
);
1098 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1099 CORE_ADDR pc
= get_frame_pc (frame
);
1100 CORE_ADDR breaks
[2] = {-1, -1};
1102 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1103 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1106 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1107 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1108 int opcode
; /* Branch instruction's OPcode. */
1109 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1111 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1112 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
1113 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
1116 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1118 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1120 loc
+= PPC_INSN_SIZE
;
1121 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1123 /* Assume that there is at most one conditional branch in the atomic
1124 sequence. If a conditional branch is found, put a breakpoint in
1125 its destination address. */
1126 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1128 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1129 int absolute
= insn
& 2;
1131 if (bc_insn_count
>= 1)
1132 return 0; /* More than one conditional branch found, fallback
1133 to the standard single-step code. */
1136 breaks
[1] = immediate
;
1138 breaks
[1] = loc
+ immediate
;
1144 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
1145 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
1149 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1150 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
1151 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
1155 loc
+= PPC_INSN_SIZE
;
1156 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1158 /* Insert a breakpoint right after the end of the atomic sequence. */
1161 /* Check for duplicated breakpoints. Check also for a breakpoint
1162 placed (branch instruction's destination) anywhere in sequence. */
1164 && (breaks
[1] == breaks
[0]
1165 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1166 last_breakpoint
= 0;
1168 /* Effectively inserts the breakpoints. */
1169 for (index
= 0; index
<= last_breakpoint
; index
++)
1170 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
1176 #define SIGNED_SHORT(x) \
1177 ((sizeof (short) == 2) \
1178 ? ((int)(short)(x)) \
1179 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1181 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1183 /* Limit the number of skipped non-prologue instructions, as the examining
1184 of the prologue is expensive. */
1185 static int max_skip_non_prologue_insns
= 10;
1187 /* Return nonzero if the given instruction OP can be part of the prologue
1188 of a function and saves a parameter on the stack. FRAMEP should be
1189 set if one of the previous instructions in the function has set the
1193 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1195 /* Move parameters from argument registers to temporary register. */
1196 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1198 /* Rx must be scratch register r0. */
1199 const int rx_regno
= (op
>> 16) & 31;
1200 /* Ry: Only r3 - r10 are used for parameter passing. */
1201 const int ry_regno
= GET_SRC_REG (op
);
1203 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1205 *r0_contains_arg
= 1;
1212 /* Save a General Purpose Register on stack. */
1214 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1215 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1217 /* Rx: Only r3 - r10 are used for parameter passing. */
1218 const int rx_regno
= GET_SRC_REG (op
);
1220 return (rx_regno
>= 3 && rx_regno
<= 10);
1223 /* Save a General Purpose Register on stack via the Frame Pointer. */
1226 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1227 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1228 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1230 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1231 However, the compiler sometimes uses r0 to hold an argument. */
1232 const int rx_regno
= GET_SRC_REG (op
);
1234 return ((rx_regno
>= 3 && rx_regno
<= 10)
1235 || (rx_regno
== 0 && *r0_contains_arg
));
1238 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1240 /* Only f2 - f8 are used for parameter passing. */
1241 const int src_regno
= GET_SRC_REG (op
);
1243 return (src_regno
>= 2 && src_regno
<= 8);
1246 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1248 /* Only f2 - f8 are used for parameter passing. */
1249 const int src_regno
= GET_SRC_REG (op
);
1251 return (src_regno
>= 2 && src_regno
<= 8);
1254 /* Not an insn that saves a parameter on stack. */
1258 /* Assuming that INSN is a "bl" instruction located at PC, return
1259 nonzero if the destination of the branch is a "blrl" instruction.
1261 This sequence is sometimes found in certain function prologues.
1262 It allows the function to load the LR register with a value that
1263 they can use to access PIC data using PC-relative offsets. */
1266 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1273 absolute
= (int) ((insn
>> 1) & 1);
1274 immediate
= ((insn
& ~3) << 6) >> 6;
1278 dest
= pc
+ immediate
;
1280 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1281 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1287 /* Masks for decoding a branch-and-link (bl) instruction.
1289 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1290 The former is anded with the opcode in question; if the result of
1291 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1292 question is a ``bl'' instruction.
1294 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1295 the branch displacement. */
1297 #define BL_MASK 0xfc000001
1298 #define BL_INSTRUCTION 0x48000001
1299 #define BL_DISPLACEMENT_MASK 0x03fffffc
1301 static unsigned long
1302 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1304 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1308 /* Fetch the instruction and convert it to an integer. */
1309 if (target_read_memory (pc
, buf
, 4))
1311 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1316 /* GCC generates several well-known sequences of instructions at the begining
1317 of each function prologue when compiling with -fstack-check. If one of
1318 such sequences starts at START_PC, then return the address of the
1319 instruction immediately past this sequence. Otherwise, return START_PC. */
1322 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1324 CORE_ADDR pc
= start_pc
;
1325 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1327 /* First possible sequence: A small number of probes.
1328 stw 0, -<some immediate>(1)
1329 [repeat this instruction any (small) number of times]. */
1331 if ((op
& 0xffff0000) == 0x90010000)
1333 while ((op
& 0xffff0000) == 0x90010000)
1336 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1341 /* Second sequence: A probing loop.
1342 addi 12,1,-<some immediate>
1343 lis 0,-<some immediate>
1344 [possibly ori 0,0,<some immediate>]
1348 addi 12,12,-<some immediate>
1351 [possibly one last probe: stw 0,<some immediate>(12)]. */
1355 /* addi 12,1,-<some immediate> */
1356 if ((op
& 0xffff0000) != 0x39810000)
1359 /* lis 0,-<some immediate> */
1361 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1362 if ((op
& 0xffff0000) != 0x3c000000)
1366 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1367 /* [possibly ori 0,0,<some immediate>] */
1368 if ((op
& 0xffff0000) == 0x60000000)
1371 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1374 if (op
!= 0x7c0c0214)
1379 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1380 if (op
!= 0x7c0c0000)
1385 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1386 if ((op
& 0xff9f0001) != 0x41820000)
1389 /* addi 12,12,-<some immediate> */
1391 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1392 if ((op
& 0xffff0000) != 0x398c0000)
1397 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1398 if (op
!= 0x900c0000)
1403 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1404 if ((op
& 0xfc000001) != 0x48000000)
1407 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1409 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1410 if ((op
& 0xffff0000) == 0x900c0000)
1413 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1416 /* We found a valid stack-check sequence, return the new PC. */
1420 /* Third sequence: No probe; instead, a comparizon between the stack size
1421 limit (saved in a run-time global variable) and the current stack
1424 addi 0,1,-<some immediate>
1425 lis 12,__gnat_stack_limit@ha
1426 lwz 12,__gnat_stack_limit@l(12)
1429 or, with a small variant in the case of a bigger stack frame:
1430 addis 0,1,<some immediate>
1431 addic 0,0,-<some immediate>
1432 lis 12,__gnat_stack_limit@ha
1433 lwz 12,__gnat_stack_limit@l(12)
1438 /* addi 0,1,-<some immediate> */
1439 if ((op
& 0xffff0000) != 0x38010000)
1441 /* small stack frame variant not recognized; try the
1442 big stack frame variant: */
1444 /* addis 0,1,<some immediate> */
1445 if ((op
& 0xffff0000) != 0x3c010000)
1448 /* addic 0,0,-<some immediate> */
1450 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1451 if ((op
& 0xffff0000) != 0x30000000)
1455 /* lis 12,<some immediate> */
1457 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1458 if ((op
& 0xffff0000) != 0x3d800000)
1461 /* lwz 12,<some immediate>(12) */
1463 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1464 if ((op
& 0xffff0000) != 0x818c0000)
1469 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1470 if ((op
& 0xfffffffe) != 0x7c406008)
1473 /* We found a valid stack-check sequence, return the new PC. */
1477 /* No stack check code in our prologue, return the start_pc. */
1481 /* return pc value after skipping a function prologue and also return
1482 information about a function frame.
1484 in struct rs6000_framedata fdata:
1485 - frameless is TRUE, if function does not have a frame.
1486 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1487 - offset is the initial size of this stack frame --- the amount by
1488 which we decrement the sp to allocate the frame.
1489 - saved_gpr is the number of the first saved gpr.
1490 - saved_fpr is the number of the first saved fpr.
1491 - saved_vr is the number of the first saved vr.
1492 - saved_ev is the number of the first saved ev.
1493 - alloca_reg is the number of the register used for alloca() handling.
1495 - gpr_offset is the offset of the first saved gpr from the previous frame.
1496 - fpr_offset is the offset of the first saved fpr from the previous frame.
1497 - vr_offset is the offset of the first saved vr from the previous frame.
1498 - ev_offset is the offset of the first saved ev from the previous frame.
1499 - lr_offset is the offset of the saved lr
1500 - cr_offset is the offset of the saved cr
1501 - vrsave_offset is the offset of the saved vrsave register. */
1504 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1505 struct rs6000_framedata
*fdata
)
1507 CORE_ADDR orig_pc
= pc
;
1508 CORE_ADDR last_prologue_pc
= pc
;
1509 CORE_ADDR li_found_pc
= 0;
1513 long vr_saved_offset
= 0;
1519 int vrsave_reg
= -1;
1522 int minimal_toc_loaded
= 0;
1523 int prev_insn_was_prologue_insn
= 1;
1524 int num_skip_non_prologue_insns
= 0;
1525 int r0_contains_arg
= 0;
1526 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1527 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1528 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1530 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1531 fdata
->saved_gpr
= -1;
1532 fdata
->saved_fpr
= -1;
1533 fdata
->saved_vr
= -1;
1534 fdata
->saved_ev
= -1;
1535 fdata
->alloca_reg
= -1;
1536 fdata
->frameless
= 1;
1537 fdata
->nosavedpc
= 1;
1538 fdata
->lr_register
= -1;
1540 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1546 /* Sometimes it isn't clear if an instruction is a prologue
1547 instruction or not. When we encounter one of these ambiguous
1548 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1549 Otherwise, we'll assume that it really is a prologue instruction. */
1550 if (prev_insn_was_prologue_insn
)
1551 last_prologue_pc
= pc
;
1553 /* Stop scanning if we've hit the limit. */
1557 prev_insn_was_prologue_insn
= 1;
1559 /* Fetch the instruction and convert it to an integer. */
1560 if (target_read_memory (pc
, buf
, 4))
1562 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1564 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1566 /* Since shared library / PIC code, which needs to get its
1567 address at runtime, can appear to save more than one link
1581 remember just the first one, but skip over additional
1584 lr_reg
= (op
& 0x03e00000) >> 21;
1586 r0_contains_arg
= 0;
1589 else if ((op
& 0xfc1fffff) == 0x7c000026)
1591 cr_reg
= (op
& 0x03e00000);
1593 r0_contains_arg
= 0;
1597 else if ((op
& 0xfc1f0000) == 0xd8010000)
1598 { /* stfd Rx,NUM(r1) */
1599 reg
= GET_SRC_REG (op
);
1600 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1602 fdata
->saved_fpr
= reg
;
1603 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1608 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1609 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1610 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1611 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1614 reg
= GET_SRC_REG (op
);
1615 if ((op
& 0xfc1f0000) == 0xbc010000)
1616 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1618 fdata
->gpr_mask
|= 1U << reg
;
1619 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1621 fdata
->saved_gpr
= reg
;
1622 if ((op
& 0xfc1f0003) == 0xf8010000)
1624 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1629 else if ((op
& 0xffff0000) == 0x3c4c0000
1630 || (op
& 0xffff0000) == 0x3c400000
1631 || (op
& 0xffff0000) == 0x38420000)
1633 /* . 0: addis 2,12,.TOC.-0b@ha
1634 . addi 2,2,.TOC.-0b@l
1638 used by ELFv2 global entry points to set up r2. */
1641 else if (op
== 0x60000000)
1644 /* Allow nops in the prologue, but do not consider them to
1645 be part of the prologue unless followed by other prologue
1647 prev_insn_was_prologue_insn
= 0;
1651 else if ((op
& 0xffff0000) == 0x3c000000)
1652 { /* addis 0,0,NUM, used for >= 32k frames */
1653 fdata
->offset
= (op
& 0x0000ffff) << 16;
1654 fdata
->frameless
= 0;
1655 r0_contains_arg
= 0;
1659 else if ((op
& 0xffff0000) == 0x60000000)
1660 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1661 fdata
->offset
|= (op
& 0x0000ffff);
1662 fdata
->frameless
= 0;
1663 r0_contains_arg
= 0;
1667 else if (lr_reg
>= 0 &&
1668 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1669 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1670 /* stw Rx, NUM(r1) */
1671 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1672 /* stwu Rx, NUM(r1) */
1673 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1674 { /* where Rx == lr */
1675 fdata
->lr_offset
= offset
;
1676 fdata
->nosavedpc
= 0;
1677 /* Invalidate lr_reg, but don't set it to -1.
1678 That would mean that it had never been set. */
1680 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1681 (op
& 0xfc000000) == 0x90000000) /* stw */
1683 /* Does not update r1, so add displacement to lr_offset. */
1684 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1689 else if (cr_reg
>= 0 &&
1690 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1691 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1692 /* stw Rx, NUM(r1) */
1693 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1694 /* stwu Rx, NUM(r1) */
1695 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1696 { /* where Rx == cr */
1697 fdata
->cr_offset
= offset
;
1698 /* Invalidate cr_reg, but don't set it to -1.
1699 That would mean that it had never been set. */
1701 if ((op
& 0xfc000003) == 0xf8000000 ||
1702 (op
& 0xfc000000) == 0x90000000)
1704 /* Does not update r1, so add displacement to cr_offset. */
1705 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1710 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1712 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1713 prediction bits. If the LR has already been saved, we can
1717 else if (op
== 0x48000005)
1724 else if (op
== 0x48000004)
1729 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1730 in V.4 -mminimal-toc */
1731 (op
& 0xffff0000) == 0x3bde0000)
1732 { /* addi 30,30,foo@l */
1736 else if ((op
& 0xfc000001) == 0x48000001)
1740 fdata
->frameless
= 0;
1742 /* If the return address has already been saved, we can skip
1743 calls to blrl (for PIC). */
1744 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1750 /* Don't skip over the subroutine call if it is not within
1751 the first three instructions of the prologue and either
1752 we have no line table information or the line info tells
1753 us that the subroutine call is not part of the line
1754 associated with the prologue. */
1755 if ((pc
- orig_pc
) > 8)
1757 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1758 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1760 if ((prologue_sal
.line
== 0)
1761 || (prologue_sal
.line
!= this_sal
.line
))
1765 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1767 /* At this point, make sure this is not a trampoline
1768 function (a function that simply calls another functions,
1769 and nothing else). If the next is not a nop, this branch
1770 was part of the function prologue. */
1772 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1773 break; /* Don't skip over
1779 /* update stack pointer */
1780 else if ((op
& 0xfc1f0000) == 0x94010000)
1781 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1782 fdata
->frameless
= 0;
1783 fdata
->offset
= SIGNED_SHORT (op
);
1784 offset
= fdata
->offset
;
1787 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1788 { /* stwux rX,r1,rY */
1789 /* No way to figure out what r1 is going to be. */
1790 fdata
->frameless
= 0;
1791 offset
= fdata
->offset
;
1794 else if ((op
& 0xfc1f0003) == 0xf8010001)
1795 { /* stdu rX,NUM(r1) */
1796 fdata
->frameless
= 0;
1797 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1798 offset
= fdata
->offset
;
1801 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1802 { /* stdux rX,r1,rY */
1803 /* No way to figure out what r1 is going to be. */
1804 fdata
->frameless
= 0;
1805 offset
= fdata
->offset
;
1808 else if ((op
& 0xffff0000) == 0x38210000)
1809 { /* addi r1,r1,SIMM */
1810 fdata
->frameless
= 0;
1811 fdata
->offset
+= SIGNED_SHORT (op
);
1812 offset
= fdata
->offset
;
1815 /* Load up minimal toc pointer. Do not treat an epilogue restore
1816 of r31 as a minimal TOC load. */
1817 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1818 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1820 && !minimal_toc_loaded
)
1822 minimal_toc_loaded
= 1;
1825 /* move parameters from argument registers to local variable
1828 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1829 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1830 (((op
>> 21) & 31) <= 10) &&
1831 ((long) ((op
>> 16) & 31)
1832 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1836 /* store parameters in stack */
1838 /* Move parameters from argument registers to temporary register. */
1839 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1843 /* Set up frame pointer */
1845 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1847 fdata
->frameless
= 0;
1849 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1852 /* Another way to set up the frame pointer. */
1854 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1855 || op
== 0x7c3f0b78)
1857 fdata
->frameless
= 0;
1859 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1862 /* Another way to set up the frame pointer. */
1864 else if ((op
& 0xfc1fffff) == 0x38010000)
1865 { /* addi rX, r1, 0x0 */
1866 fdata
->frameless
= 0;
1868 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1869 + ((op
& ~0x38010000) >> 21));
1872 /* AltiVec related instructions. */
1873 /* Store the vrsave register (spr 256) in another register for
1874 later manipulation, or load a register into the vrsave
1875 register. 2 instructions are used: mfvrsave and
1876 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1877 and mtspr SPR256, Rn. */
1878 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1879 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1880 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1882 vrsave_reg
= GET_SRC_REG (op
);
1885 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1889 /* Store the register where vrsave was saved to onto the stack:
1890 rS is the register where vrsave was stored in a previous
1892 /* 100100 sssss 00001 dddddddd dddddddd */
1893 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1895 if (vrsave_reg
== GET_SRC_REG (op
))
1897 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1902 /* Compute the new value of vrsave, by modifying the register
1903 where vrsave was saved to. */
1904 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1905 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1909 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1910 in a pair of insns to save the vector registers on the
1912 /* 001110 00000 00000 iiii iiii iiii iiii */
1913 /* 001110 01110 00000 iiii iiii iiii iiii */
1914 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1915 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1917 if ((op
& 0xffff0000) == 0x38000000)
1918 r0_contains_arg
= 0;
1920 vr_saved_offset
= SIGNED_SHORT (op
);
1922 /* This insn by itself is not part of the prologue, unless
1923 if part of the pair of insns mentioned above. So do not
1924 record this insn as part of the prologue yet. */
1925 prev_insn_was_prologue_insn
= 0;
1927 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1928 /* 011111 sssss 11111 00000 00111001110 */
1929 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1931 if (pc
== (li_found_pc
+ 4))
1933 vr_reg
= GET_SRC_REG (op
);
1934 /* If this is the first vector reg to be saved, or if
1935 it has a lower number than others previously seen,
1936 reupdate the frame info. */
1937 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1939 fdata
->saved_vr
= vr_reg
;
1940 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1942 vr_saved_offset
= -1;
1947 /* End AltiVec related instructions. */
1949 /* Start BookE related instructions. */
1950 /* Store gen register S at (r31+uimm).
1951 Any register less than r13 is volatile, so we don't care. */
1952 /* 000100 sssss 11111 iiiii 01100100001 */
1953 else if (arch_info
->mach
== bfd_mach_ppc_e500
1954 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1956 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1959 ev_reg
= GET_SRC_REG (op
);
1960 imm
= (op
>> 11) & 0x1f;
1961 ev_offset
= imm
* 8;
1962 /* If this is the first vector reg to be saved, or if
1963 it has a lower number than others previously seen,
1964 reupdate the frame info. */
1965 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1967 fdata
->saved_ev
= ev_reg
;
1968 fdata
->ev_offset
= ev_offset
+ offset
;
1973 /* Store gen register rS at (r1+rB). */
1974 /* 000100 sssss 00001 bbbbb 01100100000 */
1975 else if (arch_info
->mach
== bfd_mach_ppc_e500
1976 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1978 if (pc
== (li_found_pc
+ 4))
1980 ev_reg
= GET_SRC_REG (op
);
1981 /* If this is the first vector reg to be saved, or if
1982 it has a lower number than others previously seen,
1983 reupdate the frame info. */
1984 /* We know the contents of rB from the previous instruction. */
1985 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1987 fdata
->saved_ev
= ev_reg
;
1988 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1990 vr_saved_offset
= -1;
1996 /* Store gen register r31 at (rA+uimm). */
1997 /* 000100 11111 aaaaa iiiii 01100100001 */
1998 else if (arch_info
->mach
== bfd_mach_ppc_e500
1999 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2001 /* Wwe know that the source register is 31 already, but
2002 it can't hurt to compute it. */
2003 ev_reg
= GET_SRC_REG (op
);
2004 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2005 /* If this is the first vector reg to be saved, or if
2006 it has a lower number than others previously seen,
2007 reupdate the frame info. */
2008 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2010 fdata
->saved_ev
= ev_reg
;
2011 fdata
->ev_offset
= ev_offset
+ offset
;
2016 /* Store gen register S at (r31+r0).
2017 Store param on stack when offset from SP bigger than 4 bytes. */
2018 /* 000100 sssss 11111 00000 01100100000 */
2019 else if (arch_info
->mach
== bfd_mach_ppc_e500
2020 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2022 if (pc
== (li_found_pc
+ 4))
2024 if ((op
& 0x03e00000) >= 0x01a00000)
2026 ev_reg
= GET_SRC_REG (op
);
2027 /* If this is the first vector reg to be saved, or if
2028 it has a lower number than others previously seen,
2029 reupdate the frame info. */
2030 /* We know the contents of r0 from the previous
2032 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2034 fdata
->saved_ev
= ev_reg
;
2035 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2039 vr_saved_offset
= -1;
2044 /* End BookE related instructions. */
2048 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2050 /* Not a recognized prologue instruction.
2051 Handle optimizer code motions into the prologue by continuing
2052 the search if we have no valid frame yet or if the return
2053 address is not yet saved in the frame. Also skip instructions
2054 if some of the GPRs expected to be saved are not yet saved. */
2055 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2056 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2059 if (op
== 0x4e800020 /* blr */
2060 || op
== 0x4e800420) /* bctr */
2061 /* Do not scan past epilogue in frameless functions or
2064 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2065 /* Never skip branches. */
2068 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2069 /* Do not scan too many insns, scanning insns is expensive with
2073 /* Continue scanning. */
2074 prev_insn_was_prologue_insn
= 0;
2080 /* I have problems with skipping over __main() that I need to address
2081 * sometime. Previously, I used to use misc_function_vector which
2082 * didn't work as well as I wanted to be. -MGO */
2084 /* If the first thing after skipping a prolog is a branch to a function,
2085 this might be a call to an initializer in main(), introduced by gcc2.
2086 We'd like to skip over it as well. Fortunately, xlc does some extra
2087 work before calling a function right after a prologue, thus we can
2088 single out such gcc2 behaviour. */
2091 if ((op
& 0xfc000001) == 0x48000001)
2092 { /* bl foo, an initializer function? */
2093 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2095 if (op
== 0x4def7b82)
2096 { /* cror 0xf, 0xf, 0xf (nop) */
2098 /* Check and see if we are in main. If so, skip over this
2099 initializer function as well. */
2101 tmp
= find_pc_misc_function (pc
);
2103 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2109 if (pc
== lim_pc
&& lr_reg
>= 0)
2110 fdata
->lr_register
= lr_reg
;
2112 fdata
->offset
= -fdata
->offset
;
2113 return last_prologue_pc
;
2117 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2119 struct rs6000_framedata frame
;
2120 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2122 /* See if we can determine the end of the prologue via the symbol table.
2123 If so, then return either PC, or the PC after the prologue, whichever
2125 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2127 CORE_ADDR post_prologue_pc
2128 = skip_prologue_using_sal (gdbarch
, func_addr
);
2129 if (post_prologue_pc
!= 0)
2130 return max (pc
, post_prologue_pc
);
2133 /* Can't determine prologue from the symbol table, need to examine
2136 /* Find an upper limit on the function prologue using the debug
2137 information. If the debug information could not be used to provide
2138 that bound, then use an arbitrary large number as the upper bound. */
2139 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2141 limit_pc
= pc
+ 100; /* Magic. */
2143 /* Do not allow limit_pc to be past the function end, if we know
2144 where that end is... */
2145 if (func_end_addr
&& limit_pc
> func_end_addr
)
2146 limit_pc
= func_end_addr
;
2148 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2152 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2153 in the prologue of main().
2155 The function below examines the code pointed at by PC and checks to
2156 see if it corresponds to a call to __eabi. If so, it returns the
2157 address of the instruction following that call. Otherwise, it simply
2161 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2163 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2167 if (target_read_memory (pc
, buf
, 4))
2169 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2171 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2173 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2174 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2175 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2177 /* We check for ___eabi (three leading underscores) in addition
2178 to __eabi in case the GCC option "-fleading-underscore" was
2179 used to compile the program. */
2180 if (s
.minsym
!= NULL
2181 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2182 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2183 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2189 /* All the ABI's require 16 byte alignment. */
2191 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2193 return (addr
& -16);
2196 /* Return whether handle_inferior_event() should proceed through code
2197 starting at PC in function NAME when stepping.
2199 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2200 handle memory references that are too distant to fit in instructions
2201 generated by the compiler. For example, if 'foo' in the following
2206 is greater than 32767, the linker might replace the lwz with a branch to
2207 somewhere in @FIX1 that does the load in 2 instructions and then branches
2208 back to where execution should continue.
2210 GDB should silently step over @FIX code, just like AIX dbx does.
2211 Unfortunately, the linker uses the "b" instruction for the
2212 branches, meaning that the link register doesn't get set.
2213 Therefore, GDB's usual step_over_function () mechanism won't work.
2215 Instead, use the gdbarch_skip_trampoline_code and
2216 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2220 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2221 CORE_ADDR pc
, const char *name
)
2223 return name
&& !strncmp (name
, "@FIX", 4);
2226 /* Skip code that the user doesn't want to see when stepping:
2228 1. Indirect function calls use a piece of trampoline code to do context
2229 switching, i.e. to set the new TOC table. Skip such code if we are on
2230 its first instruction (as when we have single-stepped to here).
2232 2. Skip shared library trampoline code (which is different from
2233 indirect function call trampolines).
2235 3. Skip bigtoc fixup code.
2237 Result is desired PC to step until, or NULL if we are not in
2238 code that should be skipped. */
2241 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2243 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2244 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2245 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2246 unsigned int ii
, op
;
2248 CORE_ADDR solib_target_pc
;
2249 struct bound_minimal_symbol msymbol
;
2251 static unsigned trampoline_code
[] =
2253 0x800b0000, /* l r0,0x0(r11) */
2254 0x90410014, /* st r2,0x14(r1) */
2255 0x7c0903a6, /* mtctr r0 */
2256 0x804b0004, /* l r2,0x4(r11) */
2257 0x816b0008, /* l r11,0x8(r11) */
2258 0x4e800420, /* bctr */
2259 0x4e800020, /* br */
2263 /* Check for bigtoc fixup code. */
2264 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2266 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2267 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2269 /* Double-check that the third instruction from PC is relative "b". */
2270 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2271 if ((op
& 0xfc000003) == 0x48000000)
2273 /* Extract bits 6-29 as a signed 24-bit relative word address and
2274 add it to the containing PC. */
2275 rel
= ((int)(op
<< 6) >> 6);
2276 return pc
+ 8 + rel
;
2280 /* If pc is in a shared library trampoline, return its target. */
2281 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2282 if (solib_target_pc
)
2283 return solib_target_pc
;
2285 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2287 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2288 if (op
!= trampoline_code
[ii
])
2291 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2293 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2297 /* ISA-specific vector types. */
2299 static struct type
*
2300 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2302 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2304 if (!tdep
->ppc_builtin_type_vec64
)
2306 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2308 /* The type we're building is this: */
2310 union __gdb_builtin_type_vec64
2314 int32_t v2_int32
[2];
2315 int16_t v4_int16
[4];
2322 t
= arch_composite_type (gdbarch
,
2323 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2324 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2325 append_composite_type_field (t
, "v2_float",
2326 init_vector_type (bt
->builtin_float
, 2));
2327 append_composite_type_field (t
, "v2_int32",
2328 init_vector_type (bt
->builtin_int32
, 2));
2329 append_composite_type_field (t
, "v4_int16",
2330 init_vector_type (bt
->builtin_int16
, 4));
2331 append_composite_type_field (t
, "v8_int8",
2332 init_vector_type (bt
->builtin_int8
, 8));
2334 TYPE_VECTOR (t
) = 1;
2335 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2336 tdep
->ppc_builtin_type_vec64
= t
;
2339 return tdep
->ppc_builtin_type_vec64
;
2342 /* Vector 128 type. */
2344 static struct type
*
2345 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2347 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2349 if (!tdep
->ppc_builtin_type_vec128
)
2351 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2353 /* The type we're building is this
2355 type = union __ppc_builtin_type_vec128 {
2357 double v2_double[2];
2359 int32_t v4_int32[4];
2360 int16_t v8_int16[8];
2361 int8_t v16_int8[16];
2367 t
= arch_composite_type (gdbarch
,
2368 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2369 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2370 append_composite_type_field (t
, "v2_double",
2371 init_vector_type (bt
->builtin_double
, 2));
2372 append_composite_type_field (t
, "v4_float",
2373 init_vector_type (bt
->builtin_float
, 4));
2374 append_composite_type_field (t
, "v4_int32",
2375 init_vector_type (bt
->builtin_int32
, 4));
2376 append_composite_type_field (t
, "v8_int16",
2377 init_vector_type (bt
->builtin_int16
, 8));
2378 append_composite_type_field (t
, "v16_int8",
2379 init_vector_type (bt
->builtin_int8
, 16));
2381 TYPE_VECTOR (t
) = 1;
2382 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2383 tdep
->ppc_builtin_type_vec128
= t
;
2386 return tdep
->ppc_builtin_type_vec128
;
2389 /* Return the name of register number REGNO, or the empty string if it
2390 is an anonymous register. */
2393 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2395 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2397 /* The upper half "registers" have names in the XML description,
2398 but we present only the low GPRs and the full 64-bit registers
2400 if (tdep
->ppc_ev0_upper_regnum
>= 0
2401 && tdep
->ppc_ev0_upper_regnum
<= regno
2402 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2405 /* Hide the upper halves of the vs0~vs31 registers. */
2406 if (tdep
->ppc_vsr0_regnum
>= 0
2407 && tdep
->ppc_vsr0_upper_regnum
<= regno
2408 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2411 /* Check if the SPE pseudo registers are available. */
2412 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2414 static const char *const spe_regnames
[] = {
2415 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2416 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2417 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2418 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2420 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2423 /* Check if the decimal128 pseudo-registers are available. */
2424 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2426 static const char *const dfp128_regnames
[] = {
2427 "dl0", "dl1", "dl2", "dl3",
2428 "dl4", "dl5", "dl6", "dl7",
2429 "dl8", "dl9", "dl10", "dl11",
2430 "dl12", "dl13", "dl14", "dl15"
2432 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2435 /* Check if this is a VSX pseudo-register. */
2436 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2438 static const char *const vsx_regnames
[] = {
2439 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2440 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2441 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2442 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2443 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2444 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2445 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2446 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2447 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2449 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2452 /* Check if the this is a Extended FP pseudo-register. */
2453 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2455 static const char *const efpr_regnames
[] = {
2456 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2457 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2458 "f46", "f47", "f48", "f49", "f50", "f51",
2459 "f52", "f53", "f54", "f55", "f56", "f57",
2460 "f58", "f59", "f60", "f61", "f62", "f63"
2462 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2465 return tdesc_register_name (gdbarch
, regno
);
2468 /* Return the GDB type object for the "standard" data type of data in
2471 static struct type
*
2472 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2474 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2476 /* These are the only pseudo-registers we support. */
2477 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2478 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2479 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2480 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2482 /* These are the e500 pseudo-registers. */
2483 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2484 return rs6000_builtin_type_vec64 (gdbarch
);
2485 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2486 /* PPC decimal128 pseudo-registers. */
2487 return builtin_type (gdbarch
)->builtin_declong
;
2488 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2489 /* POWER7 VSX pseudo-registers. */
2490 return rs6000_builtin_type_vec128 (gdbarch
);
2492 /* POWER7 Extended FP pseudo-registers. */
2493 return builtin_type (gdbarch
)->builtin_double
;
2496 /* Is REGNUM a member of REGGROUP? */
2498 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2499 struct reggroup
*group
)
2501 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2503 /* These are the only pseudo-registers we support. */
2504 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2505 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2506 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2507 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2509 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2510 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2511 return group
== all_reggroup
|| group
== vector_reggroup
;
2513 /* PPC decimal128 or Extended FP pseudo-registers. */
2514 return group
== all_reggroup
|| group
== float_reggroup
;
2517 /* The register format for RS/6000 floating point registers is always
2518 double, we need a conversion if the memory format is float. */
2521 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2524 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2526 return (tdep
->ppc_fp0_regnum
>= 0
2527 && regnum
>= tdep
->ppc_fp0_regnum
2528 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2529 && TYPE_CODE (type
) == TYPE_CODE_FLT
2530 && TYPE_LENGTH (type
)
2531 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2535 rs6000_register_to_value (struct frame_info
*frame
,
2539 int *optimizedp
, int *unavailablep
)
2541 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2542 gdb_byte from
[MAX_REGISTER_SIZE
];
2544 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2546 if (!get_frame_register_bytes (frame
, regnum
, 0,
2547 register_size (gdbarch
, regnum
),
2548 from
, optimizedp
, unavailablep
))
2551 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2553 *optimizedp
= *unavailablep
= 0;
2558 rs6000_value_to_register (struct frame_info
*frame
,
2561 const gdb_byte
*from
)
2563 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2564 gdb_byte to
[MAX_REGISTER_SIZE
];
2566 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2568 convert_typed_floating (from
, type
,
2569 to
, builtin_type (gdbarch
)->builtin_double
);
2570 put_frame_register (frame
, regnum
, to
);
2573 /* The type of a function that moves the value of REG between CACHE
2574 or BUF --- in either direction. */
2575 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2578 /* Move SPE vector register values between a 64-bit buffer and the two
2579 32-bit raw register halves in a regcache. This function handles
2580 both splitting a 64-bit value into two 32-bit halves, and joining
2581 two halves into a whole 64-bit value, depending on the function
2582 passed as the MOVE argument.
2584 EV_REG must be the number of an SPE evN vector register --- a
2585 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2588 Call MOVE once for each 32-bit half of that register, passing
2589 REGCACHE, the number of the raw register corresponding to that
2590 half, and the address of the appropriate half of BUFFER.
2592 For example, passing 'regcache_raw_read' as the MOVE function will
2593 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2594 'regcache_raw_supply' will supply the contents of BUFFER to the
2595 appropriate pair of raw registers in REGCACHE.
2597 You may need to cast away some 'const' qualifiers when passing
2598 MOVE, since this function can't tell at compile-time which of
2599 REGCACHE or BUFFER is acting as the source of the data. If C had
2600 co-variant type qualifiers, ... */
2602 static enum register_status
2603 e500_move_ev_register (move_ev_register_func move
,
2604 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2606 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2607 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2609 gdb_byte
*byte_buffer
= buffer
;
2610 enum register_status status
;
2612 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2614 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2616 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2618 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2620 if (status
== REG_VALID
)
2621 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2626 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2627 if (status
== REG_VALID
)
2628 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2635 static enum register_status
2636 do_regcache_raw_read (struct regcache
*regcache
, int regnum
, void *buffer
)
2638 return regcache_raw_read (regcache
, regnum
, buffer
);
2641 static enum register_status
2642 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2644 regcache_raw_write (regcache
, regnum
, buffer
);
2649 static enum register_status
2650 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2651 int reg_nr
, gdb_byte
*buffer
)
2653 return e500_move_ev_register (do_regcache_raw_read
, regcache
, reg_nr
, buffer
);
2657 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2658 int reg_nr
, const gdb_byte
*buffer
)
2660 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2661 reg_nr
, (void *) buffer
);
2664 /* Read method for DFP pseudo-registers. */
2665 static enum register_status
2666 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2667 int reg_nr
, gdb_byte
*buffer
)
2669 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2670 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2671 enum register_status status
;
2673 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2675 /* Read two FP registers to form a whole dl register. */
2676 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2677 2 * reg_index
, buffer
);
2678 if (status
== REG_VALID
)
2679 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2680 2 * reg_index
+ 1, buffer
+ 8);
2684 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2685 2 * reg_index
+ 1, buffer
);
2686 if (status
== REG_VALID
)
2687 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2688 2 * reg_index
, buffer
+ 8);
2694 /* Write method for DFP pseudo-registers. */
2696 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2697 int reg_nr
, const gdb_byte
*buffer
)
2699 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2700 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2702 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2704 /* Write each half of the dl register into a separate
2706 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2707 2 * reg_index
, buffer
);
2708 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2709 2 * reg_index
+ 1, buffer
+ 8);
2713 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2714 2 * reg_index
+ 1, buffer
);
2715 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2716 2 * reg_index
, buffer
+ 8);
2720 /* Read method for POWER7 VSX pseudo-registers. */
2721 static enum register_status
2722 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2723 int reg_nr
, gdb_byte
*buffer
)
2725 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2726 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2727 enum register_status status
;
2729 /* Read the portion that overlaps the VMX registers. */
2731 status
= regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2732 reg_index
- 32, buffer
);
2734 /* Read the portion that overlaps the FPR registers. */
2735 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2737 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2739 if (status
== REG_VALID
)
2740 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2741 reg_index
, buffer
+ 8);
2745 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2746 reg_index
, buffer
+ 8);
2747 if (status
== REG_VALID
)
2748 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2755 /* Write method for POWER7 VSX pseudo-registers. */
2757 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2758 int reg_nr
, const gdb_byte
*buffer
)
2760 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2761 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2763 /* Write the portion that overlaps the VMX registers. */
2765 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2766 reg_index
- 32, buffer
);
2768 /* Write the portion that overlaps the FPR registers. */
2769 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2771 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2773 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2774 reg_index
, buffer
+ 8);
2778 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2779 reg_index
, buffer
+ 8);
2780 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2785 /* Read method for POWER7 Extended FP pseudo-registers. */
2786 static enum register_status
2787 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2788 int reg_nr
, gdb_byte
*buffer
)
2790 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2791 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2792 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2794 /* Read the portion that overlaps the VMX register. */
2795 return regcache_raw_read_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2796 offset
, register_size (gdbarch
, reg_nr
),
2800 /* Write method for POWER7 Extended FP pseudo-registers. */
2802 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2803 int reg_nr
, const gdb_byte
*buffer
)
2805 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2806 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2807 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2809 /* Write the portion that overlaps the VMX register. */
2810 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2811 offset
, register_size (gdbarch
, reg_nr
),
2815 static enum register_status
2816 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2817 struct regcache
*regcache
,
2818 int reg_nr
, gdb_byte
*buffer
)
2820 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2821 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2823 gdb_assert (regcache_arch
== gdbarch
);
2825 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2826 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2827 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2828 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2829 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2830 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2831 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2832 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2834 internal_error (__FILE__
, __LINE__
,
2835 _("rs6000_pseudo_register_read: "
2836 "called on unexpected register '%s' (%d)"),
2837 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2841 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2842 struct regcache
*regcache
,
2843 int reg_nr
, const gdb_byte
*buffer
)
2845 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2846 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2848 gdb_assert (regcache_arch
== gdbarch
);
2850 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2851 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2852 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2853 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2854 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2855 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2856 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2857 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2859 internal_error (__FILE__
, __LINE__
,
2860 _("rs6000_pseudo_register_write: "
2861 "called on unexpected register '%s' (%d)"),
2862 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2865 /* Convert a DBX STABS register number to a GDB register number. */
2867 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2869 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2871 if (0 <= num
&& num
<= 31)
2872 return tdep
->ppc_gp0_regnum
+ num
;
2873 else if (32 <= num
&& num
<= 63)
2874 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2875 specifies registers the architecture doesn't have? Our
2876 callers don't check the value we return. */
2877 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2878 else if (77 <= num
&& num
<= 108)
2879 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2880 else if (1200 <= num
&& num
< 1200 + 32)
2881 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2886 return tdep
->ppc_mq_regnum
;
2888 return tdep
->ppc_lr_regnum
;
2890 return tdep
->ppc_ctr_regnum
;
2892 return tdep
->ppc_xer_regnum
;
2894 return tdep
->ppc_vrsave_regnum
;
2896 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2898 return tdep
->ppc_acc_regnum
;
2900 return tdep
->ppc_spefscr_regnum
;
2907 /* Convert a Dwarf 2 register number to a GDB register number. */
2909 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2911 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2913 if (0 <= num
&& num
<= 31)
2914 return tdep
->ppc_gp0_regnum
+ num
;
2915 else if (32 <= num
&& num
<= 63)
2916 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2917 specifies registers the architecture doesn't have? Our
2918 callers don't check the value we return. */
2919 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2920 else if (1124 <= num
&& num
< 1124 + 32)
2921 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2922 else if (1200 <= num
&& num
< 1200 + 32)
2923 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2928 return tdep
->ppc_cr_regnum
;
2930 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2932 return tdep
->ppc_acc_regnum
;
2934 return tdep
->ppc_mq_regnum
;
2936 return tdep
->ppc_xer_regnum
;
2938 return tdep
->ppc_lr_regnum
;
2940 return tdep
->ppc_ctr_regnum
;
2942 return tdep
->ppc_vrsave_regnum
;
2944 return tdep
->ppc_spefscr_regnum
;
2950 /* Translate a .eh_frame register to DWARF register, or adjust a
2951 .debug_frame register. */
2954 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2956 /* GCC releases before 3.4 use GCC internal register numbering in
2957 .debug_frame (and .debug_info, et cetera). The numbering is
2958 different from the standard SysV numbering for everything except
2959 for GPRs and FPRs. We can not detect this problem in most cases
2960 - to get accurate debug info for variables living in lr, ctr, v0,
2961 et cetera, use a newer version of GCC. But we must detect
2962 one important case - lr is in column 65 in .debug_frame output,
2965 GCC 3.4, and the "hammer" branch, have a related problem. They
2966 record lr register saves in .debug_frame as 108, but still record
2967 the return column as 65. We fix that up too.
2969 We can do this because 65 is assigned to fpsr, and GCC never
2970 generates debug info referring to it. To add support for
2971 handwritten debug info that restores fpsr, we would need to add a
2972 producer version check to this. */
2981 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2982 internal register numbering; translate that to the standard DWARF2
2983 register numbering. */
2984 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2986 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2987 return num
- 68 + 86;
2988 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2989 return num
- 77 + 1124;
3001 case 109: /* vrsave */
3003 case 110: /* vscr */
3005 case 111: /* spe_acc */
3007 case 112: /* spefscr */
3015 /* Handling the various POWER/PowerPC variants. */
3017 /* Information about a particular processor variant. */
3021 /* Name of this variant. */
3024 /* English description of the variant. */
3027 /* bfd_arch_info.arch corresponding to variant. */
3028 enum bfd_architecture arch
;
3030 /* bfd_arch_info.mach corresponding to variant. */
3033 /* Target description for this variant. */
3034 struct target_desc
**tdesc
;
3037 static struct variant variants
[] =
3039 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3040 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3041 {"power", "POWER user-level", bfd_arch_rs6000
,
3042 bfd_mach_rs6k
, &tdesc_rs6000
},
3043 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3044 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3045 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3046 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3047 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3048 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3049 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3050 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3051 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3052 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3053 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3054 604, &tdesc_powerpc_604
},
3055 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3056 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3057 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3058 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3059 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3060 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3061 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3062 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3063 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3064 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3065 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3066 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3069 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3070 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3071 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3072 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3073 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3074 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3075 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3076 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3077 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3078 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3079 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3080 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3082 /* FIXME: I haven't checked the register sets of the following. */
3083 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3084 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3085 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3086 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3087 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3088 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3093 /* Return the variant corresponding to architecture ARCH and machine number
3094 MACH. If no such variant exists, return null. */
3096 static const struct variant
*
3097 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3099 const struct variant
*v
;
3101 for (v
= variants
; v
->name
; v
++)
3102 if (arch
== v
->arch
&& mach
== v
->mach
)
3109 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3111 if (info
->endian
== BFD_ENDIAN_BIG
)
3112 return print_insn_big_powerpc (memaddr
, info
);
3114 return print_insn_little_powerpc (memaddr
, info
);
3118 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3120 return frame_unwind_register_unsigned (next_frame
,
3121 gdbarch_pc_regnum (gdbarch
));
3124 static struct frame_id
3125 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3127 return frame_id_build (get_frame_register_unsigned
3128 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3129 get_frame_pc (this_frame
));
3132 struct rs6000_frame_cache
3135 CORE_ADDR initial_sp
;
3136 struct trad_frame_saved_reg
*saved_regs
;
3139 static struct rs6000_frame_cache
*
3140 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3142 struct rs6000_frame_cache
*cache
;
3143 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3144 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3145 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3146 struct rs6000_framedata fdata
;
3147 int wordsize
= tdep
->wordsize
;
3150 if ((*this_cache
) != NULL
)
3151 return (*this_cache
);
3152 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3153 (*this_cache
) = cache
;
3154 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3156 func
= get_frame_func (this_frame
);
3157 pc
= get_frame_pc (this_frame
);
3158 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3160 /* Figure out the parent's stack pointer. */
3162 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3163 address of the current frame. Things might be easier if the
3164 ->frame pointed to the outer-most address of the frame. In
3165 the mean time, the address of the prev frame is used as the
3166 base address of this frame. */
3167 cache
->base
= get_frame_register_unsigned
3168 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3170 /* If the function appears to be frameless, check a couple of likely
3171 indicators that we have simply failed to find the frame setup.
3172 Two common cases of this are missing symbols (i.e.
3173 get_frame_func returns the wrong address or 0), and assembly
3174 stubs which have a fast exit path but set up a frame on the slow
3177 If the LR appears to return to this function, then presume that
3178 we have an ABI compliant frame that we failed to find. */
3179 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3184 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3185 if (func
== 0 && saved_lr
== pc
)
3189 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3190 if (func
== saved_func
)
3196 fdata
.frameless
= 0;
3197 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3201 if (!fdata
.frameless
)
3203 /* Frameless really means stackless. */
3206 if (safe_read_memory_integer (cache
->base
, wordsize
,
3207 byte_order
, &backchain
))
3208 cache
->base
= (CORE_ADDR
) backchain
;
3211 trad_frame_set_value (cache
->saved_regs
,
3212 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3214 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3215 All fpr's from saved_fpr to fp31 are saved. */
3217 if (fdata
.saved_fpr
>= 0)
3220 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3222 /* If skip_prologue says floating-point registers were saved,
3223 but the current architecture has no floating-point registers,
3224 then that's strange. But we have no indices to even record
3225 the addresses under, so we just ignore it. */
3226 if (ppc_floating_point_unit_p (gdbarch
))
3227 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3229 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3234 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3235 All gpr's from saved_gpr to gpr31 are saved (except during the
3238 if (fdata
.saved_gpr
>= 0)
3241 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3242 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3244 if (fdata
.gpr_mask
& (1U << i
))
3245 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3246 gpr_addr
+= wordsize
;
3250 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3251 All vr's from saved_vr to vr31 are saved. */
3252 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3254 if (fdata
.saved_vr
>= 0)
3257 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3258 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3260 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3261 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3266 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3267 All vr's from saved_ev to ev31 are saved. ????? */
3268 if (tdep
->ppc_ev0_regnum
!= -1)
3270 if (fdata
.saved_ev
>= 0)
3273 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3274 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3276 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3278 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3279 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3280 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3285 /* If != 0, fdata.cr_offset is the offset from the frame that
3287 if (fdata
.cr_offset
!= 0)
3288 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3289 = cache
->base
+ fdata
.cr_offset
;
3291 /* If != 0, fdata.lr_offset is the offset from the frame that
3293 if (fdata
.lr_offset
!= 0)
3294 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3295 = cache
->base
+ fdata
.lr_offset
;
3296 else if (fdata
.lr_register
!= -1)
3297 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3298 /* The PC is found in the link register. */
3299 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3300 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3302 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3303 holds the VRSAVE. */
3304 if (fdata
.vrsave_offset
!= 0)
3305 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3306 = cache
->base
+ fdata
.vrsave_offset
;
3308 if (fdata
.alloca_reg
< 0)
3309 /* If no alloca register used, then fi->frame is the value of the
3310 %sp for this frame, and it is good enough. */
3312 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3315 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3321 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3322 struct frame_id
*this_id
)
3324 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3326 /* This marks the outermost frame. */
3327 if (info
->base
== 0)
3330 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3333 static struct value
*
3334 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3335 void **this_cache
, int regnum
)
3337 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3339 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3342 static const struct frame_unwind rs6000_frame_unwind
=
3345 default_frame_unwind_stop_reason
,
3346 rs6000_frame_this_id
,
3347 rs6000_frame_prev_register
,
3349 default_frame_sniffer
3352 /* Allocate and initialize a frame cache for an epilogue frame.
3353 SP is restored and prev-PC is stored in LR. */
3355 static struct rs6000_frame_cache
*
3356 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3358 volatile struct gdb_exception ex
;
3359 struct rs6000_frame_cache
*cache
;
3360 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3361 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3366 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3367 (*this_cache
) = cache
;
3368 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3370 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
3372 /* At this point the stack looks as if we just entered the
3373 function, and the return address is stored in LR. */
3376 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3377 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3380 cache
->initial_sp
= sp
;
3382 trad_frame_set_value (cache
->saved_regs
,
3383 gdbarch_pc_regnum (gdbarch
), lr
);
3385 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
3386 throw_exception (ex
);
3391 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3392 Return the frame ID of an epilogue frame. */
3395 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3396 void **this_cache
, struct frame_id
*this_id
)
3399 struct rs6000_frame_cache
*info
=
3400 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3402 pc
= get_frame_func (this_frame
);
3403 if (info
->base
== 0)
3404 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3406 (*this_id
) = frame_id_build (info
->base
, pc
);
3409 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3410 Return the register value of REGNUM in previous frame. */
3412 static struct value
*
3413 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3414 void **this_cache
, int regnum
)
3416 struct rs6000_frame_cache
*info
=
3417 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3418 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3421 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3422 Check whether this an epilogue frame. */
3425 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3426 struct frame_info
*this_frame
,
3427 void **this_prologue_cache
)
3429 if (frame_relative_level (this_frame
) == 0)
3430 return rs6000_in_function_epilogue_frame_p (this_frame
,
3431 get_frame_arch (this_frame
),
3432 get_frame_pc (this_frame
));
3437 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3438 a function without debug information. */
3440 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3443 default_frame_unwind_stop_reason
,
3444 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3446 rs6000_epilogue_frame_sniffer
3451 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3453 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3455 return info
->initial_sp
;
3458 static const struct frame_base rs6000_frame_base
= {
3459 &rs6000_frame_unwind
,
3460 rs6000_frame_base_address
,
3461 rs6000_frame_base_address
,
3462 rs6000_frame_base_address
3465 static const struct frame_base
*
3466 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3468 return &rs6000_frame_base
;
3471 /* DWARF-2 frame support. Used to handle the detection of
3472 clobbered registers during function calls. */
3475 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3476 struct dwarf2_frame_state_reg
*reg
,
3477 struct frame_info
*this_frame
)
3479 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3481 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3482 non-volatile registers. We will use the same code for both. */
3484 /* Call-saved GP registers. */
3485 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3486 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3487 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3488 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3490 /* Call-clobbered GP registers. */
3491 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3492 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3493 || (regnum
== tdep
->ppc_gp0_regnum
))
3494 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3496 /* Deal with FP registers, if supported. */
3497 if (tdep
->ppc_fp0_regnum
>= 0)
3499 /* Call-saved FP registers. */
3500 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3501 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3502 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3504 /* Call-clobbered FP registers. */
3505 if ((regnum
>= tdep
->ppc_fp0_regnum
3506 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3507 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3510 /* Deal with ALTIVEC registers, if supported. */
3511 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3513 /* Call-saved Altivec registers. */
3514 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3515 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3516 || regnum
== tdep
->ppc_vrsave_regnum
)
3517 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3519 /* Call-clobbered Altivec registers. */
3520 if ((regnum
>= tdep
->ppc_vr0_regnum
3521 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3522 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3525 /* Handle PC register and Stack Pointer correctly. */
3526 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3527 reg
->how
= DWARF2_FRAME_REG_RA
;
3528 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3529 reg
->how
= DWARF2_FRAME_REG_CFA
;
3533 /* Return true if a .gnu_attributes section exists in BFD and it
3534 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3535 section exists in BFD and it indicates that SPE extensions are in
3536 use. Check the .gnu.attributes section first, as the binary might be
3537 compiled for SPE, but not actually using SPE instructions. */
3540 bfd_uses_spe_extensions (bfd
*abfd
)
3543 gdb_byte
*contents
= NULL
;
3553 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3554 could be using the SPE vector abi without actually using any spe
3555 bits whatsoever. But it's close enough for now. */
3556 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3557 Tag_GNU_Power_ABI_Vector
);
3558 if (vector_abi
== 3)
3562 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3566 size
= bfd_get_section_size (sect
);
3567 contents
= xmalloc (size
);
3568 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3574 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3580 char name[name_len rounded up to 4-byte alignment];
3581 char data[data_len];
3584 Technically, there's only supposed to be one such structure in a
3585 given apuinfo section, but the linker is not always vigilant about
3586 merging apuinfo sections from input files. Just go ahead and parse
3587 them all, exiting early when we discover the binary uses SPE
3590 It's not specified in what endianness the information in this
3591 section is stored. Assume that it's the endianness of the BFD. */
3595 unsigned int name_len
;
3596 unsigned int data_len
;
3599 /* If we can't read the first three fields, we're done. */
3603 name_len
= bfd_get_32 (abfd
, ptr
);
3604 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3605 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3606 type
= bfd_get_32 (abfd
, ptr
+ 8);
3609 /* The name must be "APUinfo\0". */
3611 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3615 /* The type must be 2. */
3619 /* The data is stored as a series of uint32. The upper half of
3620 each uint32 indicates the particular APU used and the lower
3621 half indicates the revision of that APU. We just care about
3624 /* Not 4-byte quantities. */
3630 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3631 unsigned int apu
= apuinfo
>> 16;
3635 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3637 if (apu
== 0x100 || apu
== 0x101)
3652 /* These are macros for parsing instruction fields (I.1.6.28) */
3654 #define PPC_FIELD(value, from, len) \
3655 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3656 #define PPC_SEXT(v, bs) \
3657 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3658 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3659 - ((CORE_ADDR) 1 << ((bs) - 1)))
3660 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3661 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3662 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3663 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3664 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3665 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3666 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3667 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3668 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3669 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3670 | (PPC_FIELD (insn, 16, 5) << 5))
3671 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3672 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3673 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3674 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3675 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3676 #define PPC_OE(insn) PPC_BIT (insn, 21)
3677 #define PPC_RC(insn) PPC_BIT (insn, 31)
3678 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3679 #define PPC_LK(insn) PPC_BIT (insn, 31)
3680 #define PPC_TX(insn) PPC_BIT (insn, 31)
3681 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3683 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3684 #define PPC_XER_NB(xer) (xer & 0x7f)
3686 /* Record Vector-Scalar Registers.
3687 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3688 Otherwise, it's just a VR register. Record them accordingly. */
3691 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3693 if (vsr
< 0 || vsr
>= 64)
3698 if (tdep
->ppc_vr0_regnum
>= 0)
3699 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3703 if (tdep
->ppc_fp0_regnum
>= 0)
3704 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3705 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3706 record_full_arch_list_add_reg (regcache
,
3707 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3713 /* Parse and record instructions primary opcode-4 at ADDR.
3714 Return 0 if successful. */
3717 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3718 CORE_ADDR addr
, uint32_t insn
)
3720 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3721 int ext
= PPC_FIELD (insn
, 21, 11);
3725 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3726 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3727 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3728 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3729 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3731 case 42: /* Vector Select */
3732 case 43: /* Vector Permute */
3733 case 44: /* Vector Shift Left Double by Octet Immediate */
3734 case 45: /* Vector Permute and Exclusive-OR */
3735 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3736 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3737 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3738 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3739 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3740 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3741 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3742 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3743 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3744 case 46: /* Vector Multiply-Add Single-Precision */
3745 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3746 record_full_arch_list_add_reg (regcache
,
3747 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3751 switch ((ext
& 0x1ff))
3753 /* 5.16 Decimal Integer Arithmetic Instructions */
3754 case 1: /* Decimal Add Modulo */
3755 case 65: /* Decimal Subtract Modulo */
3757 /* Bit-21 should be set. */
3758 if (!PPC_BIT (insn
, 21))
3761 record_full_arch_list_add_reg (regcache
,
3762 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3763 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3767 /* Bit-21 is used for RC */
3768 switch (ext
& 0x3ff)
3770 case 6: /* Vector Compare Equal To Unsigned Byte */
3771 case 70: /* Vector Compare Equal To Unsigned Halfword */
3772 case 134: /* Vector Compare Equal To Unsigned Word */
3773 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3774 case 774: /* Vector Compare Greater Than Signed Byte */
3775 case 838: /* Vector Compare Greater Than Signed Halfword */
3776 case 902: /* Vector Compare Greater Than Signed Word */
3777 case 967: /* Vector Compare Greater Than Signed Doubleword */
3778 case 518: /* Vector Compare Greater Than Unsigned Byte */
3779 case 646: /* Vector Compare Greater Than Unsigned Word */
3780 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3781 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3782 case 966: /* Vector Compare Bounds Single-Precision */
3783 case 198: /* Vector Compare Equal To Single-Precision */
3784 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3785 case 710: /* Vector Compare Greater Than Single-Precision */
3787 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3788 record_full_arch_list_add_reg (regcache
,
3789 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3795 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
3796 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
3797 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
3798 case 334: /* Vector Pack Signed Word Unsigned Saturate */
3799 case 398: /* Vector Pack Signed Halfword Signed Saturate */
3800 case 462: /* Vector Pack Signed Word Signed Saturate */
3801 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
3802 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
3803 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
3804 case 512: /* Vector Add Unsigned Byte Saturate */
3805 case 576: /* Vector Add Unsigned Halfword Saturate */
3806 case 640: /* Vector Add Unsigned Word Saturate */
3807 case 768: /* Vector Add Signed Byte Saturate */
3808 case 832: /* Vector Add Signed Halfword Saturate */
3809 case 896: /* Vector Add Signed Word Saturate */
3810 case 1536: /* Vector Subtract Unsigned Byte Saturate */
3811 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
3812 case 1664: /* Vector Subtract Unsigned Word Saturate */
3813 case 1792: /* Vector Subtract Signed Byte Saturate */
3814 case 1856: /* Vector Subtract Signed Halfword Saturate */
3815 case 1920: /* Vector Subtract Signed Word Saturate */
3817 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
3818 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
3819 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
3820 case 1672: /* Vector Sum across Half Signed Word Saturate */
3821 case 1928: /* Vector Sum across Signed Word Saturate */
3822 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
3823 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
3824 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3826 case 12: /* Vector Merge High Byte */
3827 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
3828 case 76: /* Vector Merge High Halfword */
3829 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
3830 case 140: /* Vector Merge High Word */
3831 case 268: /* Vector Merge Low Byte */
3832 case 332: /* Vector Merge Low Halfword */
3833 case 396: /* Vector Merge Low Word */
3834 case 526: /* Vector Unpack High Signed Byte */
3835 case 590: /* Vector Unpack High Signed Halfword */
3836 case 654: /* Vector Unpack Low Signed Byte */
3837 case 718: /* Vector Unpack Low Signed Halfword */
3838 case 782: /* Vector Pack Pixel */
3839 case 846: /* Vector Unpack High Pixel */
3840 case 974: /* Vector Unpack Low Pixel */
3841 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
3842 case 1614: /* Vector Unpack High Signed Word */
3843 case 1676: /* Vector Merge Odd Word */
3844 case 1742: /* Vector Unpack Low Signed Word */
3845 case 1932: /* Vector Merge Even Word */
3846 case 524: /* Vector Splat Byte */
3847 case 588: /* Vector Splat Halfword */
3848 case 652: /* Vector Splat Word */
3849 case 780: /* Vector Splat Immediate Signed Byte */
3850 case 844: /* Vector Splat Immediate Signed Halfword */
3851 case 908: /* Vector Splat Immediate Signed Word */
3852 case 452: /* Vector Shift Left */
3853 case 708: /* Vector Shift Right */
3854 case 1036: /* Vector Shift Left by Octet */
3855 case 1100: /* Vector Shift Right by Octet */
3856 case 0: /* Vector Add Unsigned Byte Modulo */
3857 case 64: /* Vector Add Unsigned Halfword Modulo */
3858 case 128: /* Vector Add Unsigned Word Modulo */
3859 case 192: /* Vector Add Unsigned Doubleword Modulo */
3860 case 256: /* Vector Add Unsigned Quadword Modulo */
3861 case 320: /* Vector Add & write Carry Unsigned Quadword */
3862 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
3863 case 8: /* Vector Multiply Odd Unsigned Byte */
3864 case 72: /* Vector Multiply Odd Unsigned Halfword */
3865 case 136: /* Vector Multiply Odd Unsigned Word */
3866 case 264: /* Vector Multiply Odd Signed Byte */
3867 case 328: /* Vector Multiply Odd Signed Halfword */
3868 case 392: /* Vector Multiply Odd Signed Word */
3869 case 520: /* Vector Multiply Even Unsigned Byte */
3870 case 584: /* Vector Multiply Even Unsigned Halfword */
3871 case 648: /* Vector Multiply Even Unsigned Word */
3872 case 776: /* Vector Multiply Even Signed Byte */
3873 case 840: /* Vector Multiply Even Signed Halfword */
3874 case 904: /* Vector Multiply Even Signed Word */
3875 case 137: /* Vector Multiply Unsigned Word Modulo */
3876 case 1024: /* Vector Subtract Unsigned Byte Modulo */
3877 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
3878 case 1152: /* Vector Subtract Unsigned Word Modulo */
3879 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
3880 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
3881 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
3882 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
3883 case 1282: /* Vector Average Signed Byte */
3884 case 1346: /* Vector Average Signed Halfword */
3885 case 1410: /* Vector Average Signed Word */
3886 case 1026: /* Vector Average Unsigned Byte */
3887 case 1090: /* Vector Average Unsigned Halfword */
3888 case 1154: /* Vector Average Unsigned Word */
3889 case 258: /* Vector Maximum Signed Byte */
3890 case 322: /* Vector Maximum Signed Halfword */
3891 case 386: /* Vector Maximum Signed Word */
3892 case 450: /* Vector Maximum Signed Doubleword */
3893 case 2: /* Vector Maximum Unsigned Byte */
3894 case 66: /* Vector Maximum Unsigned Halfword */
3895 case 130: /* Vector Maximum Unsigned Word */
3896 case 194: /* Vector Maximum Unsigned Doubleword */
3897 case 770: /* Vector Minimum Signed Byte */
3898 case 834: /* Vector Minimum Signed Halfword */
3899 case 898: /* Vector Minimum Signed Word */
3900 case 962: /* Vector Minimum Signed Doubleword */
3901 case 514: /* Vector Minimum Unsigned Byte */
3902 case 578: /* Vector Minimum Unsigned Halfword */
3903 case 642: /* Vector Minimum Unsigned Word */
3904 case 706: /* Vector Minimum Unsigned Doubleword */
3905 case 1028: /* Vector Logical AND */
3906 case 1668: /* Vector Logical Equivalent */
3907 case 1092: /* Vector Logical AND with Complement */
3908 case 1412: /* Vector Logical NAND */
3909 case 1348: /* Vector Logical OR with Complement */
3910 case 1156: /* Vector Logical OR */
3911 case 1284: /* Vector Logical NOR */
3912 case 1220: /* Vector Logical XOR */
3913 case 4: /* Vector Rotate Left Byte */
3914 case 132: /* Vector Rotate Left Word VX-form */
3915 case 68: /* Vector Rotate Left Halfword */
3916 case 196: /* Vector Rotate Left Doubleword */
3917 case 260: /* Vector Shift Left Byte */
3918 case 388: /* Vector Shift Left Word */
3919 case 324: /* Vector Shift Left Halfword */
3920 case 1476: /* Vector Shift Left Doubleword */
3921 case 516: /* Vector Shift Right Byte */
3922 case 644: /* Vector Shift Right Word */
3923 case 580: /* Vector Shift Right Halfword */
3924 case 1732: /* Vector Shift Right Doubleword */
3925 case 772: /* Vector Shift Right Algebraic Byte */
3926 case 900: /* Vector Shift Right Algebraic Word */
3927 case 836: /* Vector Shift Right Algebraic Halfword */
3928 case 964: /* Vector Shift Right Algebraic Doubleword */
3929 case 10: /* Vector Add Single-Precision */
3930 case 74: /* Vector Subtract Single-Precision */
3931 case 1034: /* Vector Maximum Single-Precision */
3932 case 1098: /* Vector Minimum Single-Precision */
3933 case 842: /* Vector Convert From Signed Fixed-Point Word */
3934 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
3935 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
3936 case 522: /* Vector Round to Single-Precision Integer Nearest */
3937 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
3938 case 586: /* Vector Round to Single-Precision Integer toward Zero */
3939 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
3940 case 458: /* Vector Log Base 2 Estimate Floating-Point */
3941 case 266: /* Vector Reciprocal Estimate Single-Precision */
3942 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
3943 case 1288: /* Vector AES Cipher */
3944 case 1289: /* Vector AES Cipher Last */
3945 case 1352: /* Vector AES Inverse Cipher */
3946 case 1353: /* Vector AES Inverse Cipher Last */
3947 case 1480: /* Vector AES SubBytes */
3948 case 1730: /* Vector SHA-512 Sigma Doubleword */
3949 case 1666: /* Vector SHA-256 Sigma Word */
3950 case 1032: /* Vector Polynomial Multiply-Sum Byte */
3951 case 1160: /* Vector Polynomial Multiply-Sum Word */
3952 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
3953 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
3954 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
3955 case 1794: /* Vector Count Leading Zeros Byte */
3956 case 1858: /* Vector Count Leading Zeros Halfword */
3957 case 1922: /* Vector Count Leading Zeros Word */
3958 case 1986: /* Vector Count Leading Zeros Doubleword */
3959 case 1795: /* Vector Population Count Byte */
3960 case 1859: /* Vector Population Count Halfword */
3961 case 1923: /* Vector Population Count Word */
3962 case 1987: /* Vector Population Count Doubleword */
3963 case 1356: /* Vector Bit Permute Quadword */
3964 record_full_arch_list_add_reg (regcache
,
3965 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3968 case 1604: /* Move To Vector Status and Control Register */
3969 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3971 case 1540: /* Move From Vector Status and Control Register */
3972 record_full_arch_list_add_reg (regcache
,
3973 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3977 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
3978 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
3982 /* Parse and record instructions of primary opcode-19 at ADDR.
3983 Return 0 if successful. */
3986 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3987 CORE_ADDR addr
, uint32_t insn
)
3989 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3990 int ext
= PPC_EXTOP (insn
);
3994 case 0: /* Move Condition Register Field */
3995 case 33: /* Condition Register NOR */
3996 case 129: /* Condition Register AND with Complement */
3997 case 193: /* Condition Register XOR */
3998 case 225: /* Condition Register NAND */
3999 case 257: /* Condition Register AND */
4000 case 289: /* Condition Register Equivalent */
4001 case 417: /* Condition Register OR with Complement */
4002 case 449: /* Condition Register OR */
4003 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4006 case 16: /* Branch Conditional */
4007 case 560: /* Branch Conditional to Branch Target Address Register */
4008 if ((PPC_BO (insn
) & 0x4) == 0)
4009 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4011 case 528: /* Branch Conditional to Count Register */
4013 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4016 case 150: /* Instruction Synchronize */
4021 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4022 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4026 /* Parse and record instructions of primary opcode-31 at ADDR.
4027 Return 0 if successful. */
4030 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4031 CORE_ADDR addr
, uint32_t insn
)
4033 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4034 int ext
= PPC_EXTOP (insn
);
4036 CORE_ADDR at_dcsz
, ea
= 0;
4037 ULONGEST rb
, ra
, xer
;
4040 /* These instructions have OE bit. */
4041 switch (ext
& 0x1ff)
4043 /* These write RT and XER. Update CR if RC is set. */
4044 case 8: /* Subtract from carrying */
4045 case 10: /* Add carrying */
4046 case 136: /* Subtract from extended */
4047 case 138: /* Add extended */
4048 case 200: /* Subtract from zero extended */
4049 case 202: /* Add to zero extended */
4050 case 232: /* Subtract from minus one extended */
4051 case 234: /* Add to minus one extended */
4052 /* CA is always altered, but SO/OV are only altered when OE=1.
4053 In any case, XER is always altered. */
4054 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4056 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4057 record_full_arch_list_add_reg (regcache
,
4058 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4061 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4062 case 40: /* Subtract from */
4063 case 104: /* Negate */
4064 case 233: /* Multiply low doubleword */
4065 case 235: /* Multiply low word */
4067 case 393: /* Divide Doubleword Extended Unsigned */
4068 case 395: /* Divide Word Extended Unsigned */
4069 case 425: /* Divide Doubleword Extended */
4070 case 427: /* Divide Word Extended */
4071 case 457: /* Divide Doubleword Unsigned */
4072 case 459: /* Divide Word Unsigned */
4073 case 489: /* Divide Doubleword */
4074 case 491: /* Divide Word */
4076 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4078 case 9: /* Multiply High Doubleword Unsigned */
4079 case 11: /* Multiply High Word Unsigned */
4080 case 73: /* Multiply High Doubleword */
4081 case 75: /* Multiply High Word */
4083 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4084 record_full_arch_list_add_reg (regcache
,
4085 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4089 if ((ext
& 0x1f) == 15)
4091 /* Integer Select. bit[16:20] is used for BC. */
4092 record_full_arch_list_add_reg (regcache
,
4093 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4099 case 78: /* Determine Leftmost Zero Byte */
4101 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4102 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4103 record_full_arch_list_add_reg (regcache
,
4104 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4107 /* These only write RT. */
4108 case 19: /* Move from condition register */
4109 /* Move From One Condition Register Field */
4110 case 74: /* Add and Generate Sixes */
4111 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4112 case 302: /* Move From Branch History Rolling Buffer */
4113 case 339: /* Move From Special Purpose Register */
4114 case 371: /* Move From Time Base [Phased-Out] */
4115 record_full_arch_list_add_reg (regcache
,
4116 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4119 /* These only write to RA. */
4120 case 51: /* Move From VSR Doubleword */
4121 case 115: /* Move From VSR Word and Zero */
4122 case 122: /* Population count bytes */
4123 case 378: /* Population count words */
4124 case 506: /* Population count doublewords */
4125 case 154: /* Parity Word */
4126 case 186: /* Parity Doubleword */
4127 case 252: /* Bit Permute Doubleword */
4128 case 282: /* Convert Declets To Binary Coded Decimal */
4129 case 314: /* Convert Binary Coded Decimal To Declets */
4130 case 508: /* Compare bytes */
4131 record_full_arch_list_add_reg (regcache
,
4132 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4135 /* These write CR and optional RA. */
4136 case 792: /* Shift Right Algebraic Word */
4137 case 794: /* Shift Right Algebraic Doubleword */
4138 case 824: /* Shift Right Algebraic Word Immediate */
4139 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4140 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4141 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4142 record_full_arch_list_add_reg (regcache
,
4143 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4145 case 0: /* Compare */
4146 case 32: /* Compare logical */
4147 case 144: /* Move To Condition Register Fields */
4148 /* Move To One Condition Register Field */
4149 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4152 /* These write to RT. Update RA if 'update indexed.' */
4153 case 53: /* Load Doubleword with Update Indexed */
4154 case 119: /* Load Byte and Zero with Update Indexed */
4155 case 311: /* Load Halfword and Zero with Update Indexed */
4156 case 55: /* Load Word and Zero with Update Indexed */
4157 case 375: /* Load Halfword Algebraic with Update Indexed */
4158 case 373: /* Load Word Algebraic with Update Indexed */
4159 record_full_arch_list_add_reg (regcache
,
4160 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4162 case 21: /* Load Doubleword Indexed */
4163 case 52: /* Load Byte And Reserve Indexed */
4164 case 116: /* Load Halfword And Reserve Indexed */
4165 case 20: /* Load Word And Reserve Indexed */
4166 case 84: /* Load Doubleword And Reserve Indexed */
4167 case 87: /* Load Byte and Zero Indexed */
4168 case 279: /* Load Halfword and Zero Indexed */
4169 case 23: /* Load Word and Zero Indexed */
4170 case 343: /* Load Halfword Algebraic Indexed */
4171 case 341: /* Load Word Algebraic Indexed */
4172 case 790: /* Load Halfword Byte-Reverse Indexed */
4173 case 534: /* Load Word Byte-Reverse Indexed */
4174 case 532: /* Load Doubleword Byte-Reverse Indexed */
4175 record_full_arch_list_add_reg (regcache
,
4176 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4179 case 597: /* Load String Word Immediate */
4180 case 533: /* Load String Word Indexed */
4189 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4190 nr
= PPC_XER_NB (xer
);
4195 /* If n=0, the contents of register RT are undefined. */
4199 for (i
= 0; i
< nr
; i
++)
4200 record_full_arch_list_add_reg (regcache
,
4201 tdep
->ppc_gp0_regnum
4202 + ((PPC_RT (insn
) + i
) & 0x1f));
4205 case 276: /* Load Quadword And Reserve Indexed */
4206 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4207 record_full_arch_list_add_reg (regcache
, tmp
);
4208 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4211 /* These write VRT. */
4212 case 6: /* Load Vector for Shift Left Indexed */
4213 case 38: /* Load Vector for Shift Right Indexed */
4214 case 7: /* Load Vector Element Byte Indexed */
4215 case 39: /* Load Vector Element Halfword Indexed */
4216 case 71: /* Load Vector Element Word Indexed */
4217 case 103: /* Load Vector Indexed */
4218 case 359: /* Load Vector Indexed LRU */
4219 record_full_arch_list_add_reg (regcache
,
4220 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4223 /* These write FRT. Update RA if 'update indexed.' */
4224 case 567: /* Load Floating-Point Single with Update Indexed */
4225 case 631: /* Load Floating-Point Double with Update Indexed */
4226 record_full_arch_list_add_reg (regcache
,
4227 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4229 case 535: /* Load Floating-Point Single Indexed */
4230 case 599: /* Load Floating-Point Double Indexed */
4231 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4232 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4233 record_full_arch_list_add_reg (regcache
,
4234 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4237 case 791: /* Load Floating-Point Double Pair Indexed */
4238 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4239 record_full_arch_list_add_reg (regcache
, tmp
);
4240 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4243 case 179: /* Move To VSR Doubleword */
4244 case 211: /* Move To VSR Word Algebraic */
4245 case 243: /* Move To VSR Word and Zero */
4246 case 588: /* Load VSX Scalar Doubleword Indexed */
4247 case 524: /* Load VSX Scalar Single-Precision Indexed */
4248 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4249 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4250 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4251 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4252 case 780: /* Load VSX Vector Word*4 Indexed */
4253 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4256 /* These write RA. Update CR if RC is set. */
4257 case 24: /* Shift Left Word */
4258 case 26: /* Count Leading Zeros Word */
4259 case 27: /* Shift Left Doubleword */
4261 case 58: /* Count Leading Zeros Doubleword */
4262 case 60: /* AND with Complement */
4264 case 284: /* Equivalent */
4266 case 476: /* NAND */
4267 case 412: /* OR with Complement */
4269 case 536: /* Shift Right Word */
4270 case 539: /* Shift Right Doubleword */
4271 case 922: /* Extend Sign Halfword */
4272 case 954: /* Extend Sign Byte */
4273 case 986: /* Extend Sign Word */
4275 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4276 record_full_arch_list_add_reg (regcache
,
4277 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4281 case 181: /* Store Doubleword with Update Indexed */
4282 case 183: /* Store Word with Update Indexed */
4283 case 247: /* Store Byte with Update Indexed */
4284 case 439: /* Store Half Word with Update Indexed */
4285 case 695: /* Store Floating-Point Single with Update Indexed */
4286 case 759: /* Store Floating-Point Double with Update Indexed */
4287 record_full_arch_list_add_reg (regcache
,
4288 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4290 case 135: /* Store Vector Element Byte Indexed */
4291 case 167: /* Store Vector Element Halfword Indexed */
4292 case 199: /* Store Vector Element Word Indexed */
4293 case 231: /* Store Vector Indexed */
4294 case 487: /* Store Vector Indexed LRU */
4295 case 716: /* Store VSX Scalar Doubleword Indexed */
4296 case 140: /* Store VSX Scalar as Integer Word Indexed */
4297 case 652: /* Store VSX Scalar Single-Precision Indexed */
4298 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4299 case 908: /* Store VSX Vector Word*4 Indexed */
4300 case 149: /* Store Doubleword Indexed */
4301 case 151: /* Store Word Indexed */
4302 case 215: /* Store Byte Indexed */
4303 case 407: /* Store Half Word Indexed */
4304 case 694: /* Store Byte Conditional Indexed */
4305 case 726: /* Store Halfword Conditional Indexed */
4306 case 150: /* Store Word Conditional Indexed */
4307 case 214: /* Store Doubleword Conditional Indexed */
4308 case 182: /* Store Quadword Conditional Indexed */
4309 case 662: /* Store Word Byte-Reverse Indexed */
4310 case 918: /* Store Halfword Byte-Reverse Indexed */
4311 case 660: /* Store Doubleword Byte-Reverse Indexed */
4312 case 663: /* Store Floating-Point Single Indexed */
4313 case 727: /* Store Floating-Point Double Indexed */
4314 case 919: /* Store Floating-Point Double Pair Indexed */
4315 case 983: /* Store Floating-Point as Integer Word Indexed */
4316 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4317 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4320 if (PPC_RA (insn
) != 0)
4321 regcache_raw_read_unsigned (regcache
,
4322 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4323 regcache_raw_read_unsigned (regcache
,
4324 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4329 case 183: /* Store Word with Update Indexed */
4330 case 199: /* Store Vector Element Word Indexed */
4331 case 140: /* Store VSX Scalar as Integer Word Indexed */
4332 case 652: /* Store VSX Scalar Single-Precision Indexed */
4333 case 151: /* Store Word Indexed */
4334 case 150: /* Store Word Conditional Indexed */
4335 case 662: /* Store Word Byte-Reverse Indexed */
4336 case 663: /* Store Floating-Point Single Indexed */
4337 case 695: /* Store Floating-Point Single with Update Indexed */
4338 case 983: /* Store Floating-Point as Integer Word Indexed */
4341 case 247: /* Store Byte with Update Indexed */
4342 case 135: /* Store Vector Element Byte Indexed */
4343 case 215: /* Store Byte Indexed */
4344 case 694: /* Store Byte Conditional Indexed */
4347 case 439: /* Store Halfword with Update Indexed */
4348 case 167: /* Store Vector Element Halfword Indexed */
4349 case 407: /* Store Halfword Indexed */
4350 case 726: /* Store Halfword Conditional Indexed */
4351 case 918: /* Store Halfword Byte-Reverse Indexed */
4354 case 181: /* Store Doubleword with Update Indexed */
4355 case 716: /* Store VSX Scalar Doubleword Indexed */
4356 case 149: /* Store Doubleword Indexed */
4357 case 214: /* Store Doubleword Conditional Indexed */
4358 case 660: /* Store Doubleword Byte-Reverse Indexed */
4359 case 727: /* Store Floating-Point Double Indexed */
4360 case 759: /* Store Floating-Point Double with Update Indexed */
4363 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4364 case 908: /* Store VSX Vector Word*4 Indexed */
4365 case 182: /* Store Quadword Conditional Indexed */
4366 case 231: /* Store Vector Indexed */
4367 case 487: /* Store Vector Indexed LRU */
4368 case 919: /* Store Floating-Point Double Pair Indexed */
4375 /* Align address for Store Vector instructions. */
4378 case 167: /* Store Vector Element Halfword Indexed */
4379 addr
= addr
& ~0x1ULL
;
4382 case 199: /* Store Vector Element Word Indexed */
4383 addr
= addr
& ~0x3ULL
;
4386 case 231: /* Store Vector Indexed */
4387 case 487: /* Store Vector Indexed LRU */
4388 addr
= addr
& ~0xfULL
;
4392 record_full_arch_list_add_mem (addr
, size
);
4395 case 725: /* Store String Word Immediate */
4397 if (PPC_RA (insn
) != 0)
4398 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &ra
);
4405 record_full_arch_list_add_mem (ea
, nb
);
4409 case 661: /* Store String Word Indexed */
4411 if (PPC_RA (insn
) != 0)
4412 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &ra
);
4415 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4416 nb
= PPC_XER_NB (xer
);
4420 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &rb
);
4422 record_full_arch_list_add_mem (ea
, nb
);
4427 case 467: /* Move To Special Purpose Register */
4428 switch (PPC_SPR (insn
))
4431 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4434 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4437 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4439 case 256: /* VRSAVE */
4440 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4446 case 147: /* Move To Split Little Endian */
4447 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4450 case 512: /* Move to Condition Register from XER */
4451 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4452 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4455 case 4: /* Trap Word */
4456 case 68: /* Trap Doubleword */
4457 case 430: /* Clear BHRB */
4458 case 598: /* Synchronize */
4459 case 62: /* Wait for Interrupt */
4460 case 22: /* Instruction Cache Block Touch */
4461 case 854: /* Enforce In-order Execution of I/O */
4462 case 246: /* Data Cache Block Touch for Store */
4463 case 54: /* Data Cache Block Store */
4464 case 86: /* Data Cache Block Flush */
4465 case 278: /* Data Cache Block Touch */
4466 case 758: /* Data Cache Block Allocate */
4467 case 982: /* Instruction Cache Block Invalidate */
4470 case 654: /* Transaction Begin */
4471 case 686: /* Transaction End */
4472 case 718: /* Transaction Check */
4473 case 750: /* Transaction Suspend or Resume */
4474 case 782: /* Transaction Abort Word Conditional */
4475 case 814: /* Transaction Abort Doubleword Conditional */
4476 case 846: /* Transaction Abort Word Conditional Immediate */
4477 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4478 case 910: /* Transaction Abort */
4479 fprintf_unfiltered (gdb_stdlog
, "Cannot record Transaction instructions. "
4480 "%08x at %s, 31-%d.\n",
4481 insn
, paddress (gdbarch
, addr
), ext
);
4484 case 1014: /* Data Cache Block set to Zero */
4485 if (target_auxv_search (¤t_target
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4487 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4489 if (PPC_RA (insn
) != 0)
4490 regcache_raw_read_unsigned (regcache
,
4491 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4492 regcache_raw_read_unsigned (regcache
,
4493 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4494 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4495 record_full_arch_list_add_mem (ea
, at_dcsz
);
4500 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4501 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4505 /* Parse and record instructions of primary opcode-59 at ADDR.
4506 Return 0 if successful. */
4509 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4510 CORE_ADDR addr
, uint32_t insn
)
4512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4513 int ext
= PPC_EXTOP (insn
);
4517 case 18: /* Floating Divide */
4518 case 20: /* Floating Subtract */
4519 case 21: /* Floating Add */
4520 case 22: /* Floating Square Root */
4521 case 24: /* Floating Reciprocal Estimate */
4522 case 25: /* Floating Multiply */
4523 case 26: /* Floating Reciprocal Square Root Estimate */
4524 case 28: /* Floating Multiply-Subtract */
4525 case 29: /* Floating Multiply-Add */
4526 case 30: /* Floating Negative Multiply-Subtract */
4527 case 31: /* Floating Negative Multiply-Add */
4528 record_full_arch_list_add_reg (regcache
,
4529 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4531 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4532 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4539 case 2: /* DFP Add */
4540 case 3: /* DFP Quantize */
4541 case 34: /* DFP Multiply */
4542 case 35: /* DFP Reround */
4543 case 67: /* DFP Quantize Immediate */
4544 case 99: /* DFP Round To FP Integer With Inexact */
4545 case 227: /* DFP Round To FP Integer Without Inexact */
4546 case 258: /* DFP Convert To DFP Long! */
4547 case 290: /* DFP Convert To Fixed */
4548 case 514: /* DFP Subtract */
4549 case 546: /* DFP Divide */
4550 case 770: /* DFP Round To DFP Short! */
4551 case 802: /* DFP Convert From Fixed */
4552 case 834: /* DFP Encode BCD To DPD */
4554 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4555 record_full_arch_list_add_reg (regcache
,
4556 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4557 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4560 case 130: /* DFP Compare Ordered */
4561 case 162: /* DFP Test Exponent */
4562 case 194: /* DFP Test Data Class */
4563 case 226: /* DFP Test Data Group */
4564 case 642: /* DFP Compare Unordered */
4565 case 674: /* DFP Test Significance */
4566 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4567 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4570 case 66: /* DFP Shift Significand Left Immediate */
4571 case 98: /* DFP Shift Significand Right Immediate */
4572 case 322: /* DFP Decode DPD To BCD */
4573 case 354: /* DFP Extract Biased Exponent */
4574 case 866: /* DFP Insert Biased Exponent */
4575 record_full_arch_list_add_reg (regcache
,
4576 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4578 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4581 case 846: /* Floating Convert From Integer Doubleword Single */
4582 case 974: /* Floating Convert From Integer Doubleword Unsigned
4584 record_full_arch_list_add_reg (regcache
,
4585 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4587 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4588 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4593 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4594 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4598 /* Parse and record instructions of primary opcode-60 at ADDR.
4599 Return 0 if successful. */
4602 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4603 CORE_ADDR addr
, uint32_t insn
)
4605 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4606 int ext
= PPC_EXTOP (insn
);
4610 case 0: /* VSX Scalar Add Single-Precision */
4611 case 32: /* VSX Scalar Add Double-Precision */
4612 case 24: /* VSX Scalar Divide Single-Precision */
4613 case 56: /* VSX Scalar Divide Double-Precision */
4614 case 176: /* VSX Scalar Copy Sign Double-Precision */
4615 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4616 case 41: /* ditto */
4617 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4619 case 160: /* VSX Scalar Maximum Double-Precision */
4620 case 168: /* VSX Scalar Minimum Double-Precision */
4621 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4622 case 57: /* ditto */
4623 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4624 case 25: /* ditto */
4625 case 48: /* VSX Scalar Multiply Double-Precision */
4626 case 16: /* VSX Scalar Multiply Single-Precision */
4627 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4628 case 169: /* ditto */
4629 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4630 case 137: /* ditto */
4631 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4632 case 185: /* ditto */
4633 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4634 case 153: /* ditto */
4635 case 40: /* VSX Scalar Subtract Double-Precision */
4636 case 8: /* VSX Scalar Subtract Single-Precision */
4637 case 96: /* VSX Vector Add Double-Precision */
4638 case 64: /* VSX Vector Add Single-Precision */
4639 case 120: /* VSX Vector Divide Double-Precision */
4640 case 88: /* VSX Vector Divide Single-Precision */
4641 case 97: /* VSX Vector Multiply-Add Double-Precision */
4642 case 105: /* ditto */
4643 case 65: /* VSX Vector Multiply-Add Single-Precision */
4644 case 73: /* ditto */
4645 case 224: /* VSX Vector Maximum Double-Precision */
4646 case 192: /* VSX Vector Maximum Single-Precision */
4647 case 232: /* VSX Vector Minimum Double-Precision */
4648 case 200: /* VSX Vector Minimum Single-Precision */
4649 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
4650 case 121: /* ditto */
4651 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
4652 case 89: /* ditto */
4653 case 112: /* VSX Vector Multiply Double-Precision */
4654 case 80: /* VSX Vector Multiply Single-Precision */
4655 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
4656 case 233: /* ditto */
4657 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
4658 case 201: /* ditto */
4659 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
4660 case 249: /* ditto */
4661 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
4662 case 217: /* ditto */
4663 case 104: /* VSX Vector Subtract Double-Precision */
4664 case 72: /* VSX Vector Subtract Single-Precision */
4665 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4666 case 240: /* VSX Vector Copy Sign Double-Precision */
4667 case 208: /* VSX Vector Copy Sign Single-Precision */
4668 case 130: /* VSX Logical AND */
4669 case 138: /* VSX Logical AND with Complement */
4670 case 186: /* VSX Logical Equivalence */
4671 case 178: /* VSX Logical NAND */
4672 case 170: /* VSX Logical OR with Complement */
4673 case 162: /* VSX Logical NOR */
4674 case 146: /* VSX Logical OR */
4675 case 154: /* VSX Logical XOR */
4676 case 18: /* VSX Merge High Word */
4677 case 50: /* VSX Merge Low Word */
4678 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
4679 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
4680 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
4681 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
4682 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
4683 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
4684 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
4685 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
4686 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4689 case 61: /* VSX Scalar Test for software Divide Double-Precision */
4690 case 125: /* VSX Vector Test for software Divide Double-Precision */
4691 case 93: /* VSX Vector Test for software Divide Single-Precision */
4692 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4695 case 35: /* VSX Scalar Compare Unordered Double-Precision */
4696 case 43: /* VSX Scalar Compare Ordered Double-Precision */
4697 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4698 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4702 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
4704 case 99: /* VSX Vector Compare Equal To Double-Precision */
4705 case 67: /* VSX Vector Compare Equal To Single-Precision */
4706 case 115: /* VSX Vector Compare Greater Than or
4707 Equal To Double-Precision */
4708 case 83: /* VSX Vector Compare Greater Than or
4709 Equal To Single-Precision */
4710 case 107: /* VSX Vector Compare Greater Than Double-Precision */
4711 case 75: /* VSX Vector Compare Greater Than Single-Precision */
4713 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4714 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4715 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4721 case 265: /* VSX Scalar round Double-Precision to
4722 Single-Precision and Convert to
4723 Single-Precision format */
4724 case 344: /* VSX Scalar truncate Double-Precision to
4725 Integer and Convert to Signed Integer
4726 Doubleword format with Saturate */
4727 case 88: /* VSX Scalar truncate Double-Precision to
4728 Integer and Convert to Signed Integer Word
4729 Format with Saturate */
4730 case 328: /* VSX Scalar truncate Double-Precision integer
4731 and Convert to Unsigned Integer Doubleword
4732 Format with Saturate */
4733 case 72: /* VSX Scalar truncate Double-Precision to
4734 Integer and Convert to Unsigned Integer Word
4735 Format with Saturate */
4736 case 329: /* VSX Scalar Convert Single-Precision to
4737 Double-Precision format */
4738 case 376: /* VSX Scalar Convert Signed Integer
4739 Doubleword to floating-point format and
4740 Round to Double-Precision format */
4741 case 312: /* VSX Scalar Convert Signed Integer
4742 Doubleword to floating-point format and
4743 round to Single-Precision */
4744 case 360: /* VSX Scalar Convert Unsigned Integer
4745 Doubleword to floating-point format and
4746 Round to Double-Precision format */
4747 case 296: /* VSX Scalar Convert Unsigned Integer
4748 Doubleword to floating-point format and
4749 Round to Single-Precision */
4750 case 73: /* VSX Scalar Round to Double-Precision Integer
4751 Using Round to Nearest Away */
4752 case 107: /* VSX Scalar Round to Double-Precision Integer
4753 Exact using Current rounding mode */
4754 case 121: /* VSX Scalar Round to Double-Precision Integer
4755 Using Round toward -Infinity */
4756 case 105: /* VSX Scalar Round to Double-Precision Integer
4757 Using Round toward +Infinity */
4758 case 89: /* VSX Scalar Round to Double-Precision Integer
4759 Using Round toward Zero */
4760 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
4761 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
4762 case 281: /* VSX Scalar Round to Single-Precision */
4763 case 74: /* VSX Scalar Reciprocal Square Root Estimate
4765 case 10: /* VSX Scalar Reciprocal Square Root Estimate
4767 case 75: /* VSX Scalar Square Root Double-Precision */
4768 case 11: /* VSX Scalar Square Root Single-Precision */
4769 case 393: /* VSX Vector round Double-Precision to
4770 Single-Precision and Convert to
4771 Single-Precision format */
4772 case 472: /* VSX Vector truncate Double-Precision to
4773 Integer and Convert to Signed Integer
4774 Doubleword format with Saturate */
4775 case 216: /* VSX Vector truncate Double-Precision to
4776 Integer and Convert to Signed Integer Word
4777 Format with Saturate */
4778 case 456: /* VSX Vector truncate Double-Precision to
4779 Integer and Convert to Unsigned Integer
4780 Doubleword format with Saturate */
4781 case 200: /* VSX Vector truncate Double-Precision to
4782 Integer and Convert to Unsigned Integer Word
4783 Format with Saturate */
4784 case 457: /* VSX Vector Convert Single-Precision to
4785 Double-Precision format */
4786 case 408: /* VSX Vector truncate Single-Precision to
4787 Integer and Convert to Signed Integer
4788 Doubleword format with Saturate */
4789 case 152: /* VSX Vector truncate Single-Precision to
4790 Integer and Convert to Signed Integer Word
4791 Format with Saturate */
4792 case 392: /* VSX Vector truncate Single-Precision to
4793 Integer and Convert to Unsigned Integer
4794 Doubleword format with Saturate */
4795 case 136: /* VSX Vector truncate Single-Precision to
4796 Integer and Convert to Unsigned Integer Word
4797 Format with Saturate */
4798 case 504: /* VSX Vector Convert and round Signed Integer
4799 Doubleword to Double-Precision format */
4800 case 440: /* VSX Vector Convert and round Signed Integer
4801 Doubleword to Single-Precision format */
4802 case 248: /* VSX Vector Convert Signed Integer Word to
4803 Double-Precision format */
4804 case 184: /* VSX Vector Convert and round Signed Integer
4805 Word to Single-Precision format */
4806 case 488: /* VSX Vector Convert and round Unsigned
4807 Integer Doubleword to Double-Precision format */
4808 case 424: /* VSX Vector Convert and round Unsigned
4809 Integer Doubleword to Single-Precision format */
4810 case 232: /* VSX Vector Convert and round Unsigned
4811 Integer Word to Double-Precision format */
4812 case 168: /* VSX Vector Convert and round Unsigned
4813 Integer Word to Single-Precision format */
4814 case 201: /* VSX Vector Round to Double-Precision
4815 Integer using round to Nearest Away */
4816 case 235: /* VSX Vector Round to Double-Precision
4817 Integer Exact using Current rounding mode */
4818 case 249: /* VSX Vector Round to Double-Precision
4819 Integer using round toward -Infinity */
4820 case 233: /* VSX Vector Round to Double-Precision
4821 Integer using round toward +Infinity */
4822 case 217: /* VSX Vector Round to Double-Precision
4823 Integer using round toward Zero */
4824 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
4825 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
4826 case 137: /* VSX Vector Round to Single-Precision Integer
4827 Using Round to Nearest Away */
4828 case 171: /* VSX Vector Round to Single-Precision Integer
4829 Exact Using Current rounding mode */
4830 case 185: /* VSX Vector Round to Single-Precision Integer
4831 Using Round toward -Infinity */
4832 case 169: /* VSX Vector Round to Single-Precision Integer
4833 Using Round toward +Infinity */
4834 case 153: /* VSX Vector Round to Single-Precision Integer
4835 Using round toward Zero */
4836 case 202: /* VSX Vector Reciprocal Square Root Estimate
4838 case 138: /* VSX Vector Reciprocal Square Root Estimate
4840 case 203: /* VSX Vector Square Root Double-Precision */
4841 case 139: /* VSX Vector Square Root Single-Precision */
4842 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4843 case 345: /* VSX Scalar Absolute Value Double-Precision */
4844 case 267: /* VSX Scalar Convert Scalar Single-Precision to
4845 Vector Single-Precision format Non-signalling */
4846 case 331: /* VSX Scalar Convert Single-Precision to
4847 Double-Precision format Non-signalling */
4848 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
4849 case 377: /* VSX Scalar Negate Double-Precision */
4850 case 473: /* VSX Vector Absolute Value Double-Precision */
4851 case 409: /* VSX Vector Absolute Value Single-Precision */
4852 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
4853 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
4854 case 505: /* VSX Vector Negate Double-Precision */
4855 case 441: /* VSX Vector Negate Single-Precision */
4856 case 164: /* VSX Splat Word */
4857 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4860 case 106: /* VSX Scalar Test for software Square Root
4862 case 234: /* VSX Vector Test for software Square Root
4864 case 170: /* VSX Vector Test for software Square Root
4866 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4870 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
4872 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4876 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4877 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4881 /* Parse and record instructions of primary opcode-63 at ADDR.
4882 Return 0 if successful. */
4885 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4886 CORE_ADDR addr
, uint32_t insn
)
4888 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4889 int ext
= PPC_EXTOP (insn
);
4894 case 18: /* Floating Divide */
4895 case 20: /* Floating Subtract */
4896 case 21: /* Floating Add */
4897 case 22: /* Floating Square Root */
4898 case 24: /* Floating Reciprocal Estimate */
4899 case 25: /* Floating Multiply */
4900 case 26: /* Floating Reciprocal Square Root Estimate */
4901 case 28: /* Floating Multiply-Subtract */
4902 case 29: /* Floating Multiply-Add */
4903 case 30: /* Floating Negative Multiply-Subtract */
4904 case 31: /* Floating Negative Multiply-Add */
4905 record_full_arch_list_add_reg (regcache
,
4906 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4908 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4909 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4912 case 23: /* Floating Select */
4913 record_full_arch_list_add_reg (regcache
,
4914 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4916 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4921 case 2: /* DFP Add Quad */
4922 case 3: /* DFP Quantize Quad */
4923 case 34: /* DFP Multiply Quad */
4924 case 35: /* DFP Reround Quad */
4925 case 67: /* DFP Quantize Immediate Quad */
4926 case 99: /* DFP Round To FP Integer With Inexact Quad */
4927 case 227: /* DFP Round To FP Integer Without Inexact Quad */
4928 case 258: /* DFP Convert To DFP Extended Quad */
4929 case 514: /* DFP Subtract Quad */
4930 case 546: /* DFP Divide Quad */
4931 case 770: /* DFP Round To DFP Long Quad */
4932 case 802: /* DFP Convert From Fixed Quad */
4933 case 834: /* DFP Encode BCD To DPD Quad */
4935 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4936 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4937 record_full_arch_list_add_reg (regcache
, tmp
);
4938 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4939 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4942 case 130: /* DFP Compare Ordered Quad */
4943 case 162: /* DFP Test Exponent Quad */
4944 case 194: /* DFP Test Data Class Quad */
4945 case 226: /* DFP Test Data Group Quad */
4946 case 642: /* DFP Compare Unordered Quad */
4947 case 674: /* DFP Test Significance Quad */
4948 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4949 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4952 case 66: /* DFP Shift Significand Left Immediate Quad */
4953 case 98: /* DFP Shift Significand Right Immediate Quad */
4954 case 322: /* DFP Decode DPD To BCD Quad */
4955 case 866: /* DFP Insert Biased Exponent Quad */
4956 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4957 record_full_arch_list_add_reg (regcache
, tmp
);
4958 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4960 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4963 case 290: /* DFP Convert To Fixed Quad */
4964 record_full_arch_list_add_reg (regcache
,
4965 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4967 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4968 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4971 case 354: /* DFP Extract Biased Exponent Quad */
4972 record_full_arch_list_add_reg (regcache
,
4973 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4975 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4978 case 12: /* Floating Round to Single-Precision */
4979 case 14: /* Floating Convert To Integer Word */
4980 case 15: /* Floating Convert To Integer Word
4981 with round toward Zero */
4982 case 142: /* Floating Convert To Integer Word Unsigned */
4983 case 143: /* Floating Convert To Integer Word Unsigned
4984 with round toward Zero */
4985 case 392: /* Floating Round to Integer Nearest */
4986 case 424: /* Floating Round to Integer Toward Zero */
4987 case 456: /* Floating Round to Integer Plus */
4988 case 488: /* Floating Round to Integer Minus */
4989 case 814: /* Floating Convert To Integer Doubleword */
4990 case 815: /* Floating Convert To Integer Doubleword
4991 with round toward Zero */
4992 case 846: /* Floating Convert From Integer Doubleword */
4993 case 942: /* Floating Convert To Integer Doubleword Unsigned */
4994 case 943: /* Floating Convert To Integer Doubleword Unsigned
4995 with round toward Zero */
4996 case 974: /* Floating Convert From Integer Doubleword Unsigned */
4997 record_full_arch_list_add_reg (regcache
,
4998 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5000 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5001 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5004 case 583: /* Move From FPSCR */
5005 case 8: /* Floating Copy Sign */
5006 case 40: /* Floating Negate */
5007 case 72: /* Floating Move Register */
5008 case 136: /* Floating Negative Absolute Value */
5009 case 264: /* Floating Absolute Value */
5010 record_full_arch_list_add_reg (regcache
,
5011 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5013 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5016 case 838: /* Floating Merge Odd Word */
5017 case 966: /* Floating Merge Even Word */
5018 record_full_arch_list_add_reg (regcache
,
5019 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5022 case 38: /* Move To FPSCR Bit 1 */
5023 case 70: /* Move To FPSCR Bit 0 */
5024 case 134: /* Move To FPSCR Field Immediate */
5025 case 711: /* Move To FPSCR Fields */
5027 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5028 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5031 case 0: /* Floating Compare Unordered */
5032 case 32: /* Floating Compare Ordered */
5033 case 64: /* Move to Condition Register from FPSCR */
5034 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5036 case 128: /* Floating Test for software Divide */
5037 case 160: /* Floating Test for software Square Root */
5038 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5043 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5044 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5048 /* Parse the current instruction and record the values of the registers and
5049 memory that will be changed in current instruction to "record_arch_list".
5050 Return -1 if something wrong. */
5053 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5056 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5057 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5061 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5062 op6
= PPC_OP6 (insn
);
5066 case 2: /* Trap Doubleword Immediate */
5067 case 3: /* Trap Word Immediate */
5072 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5076 case 17: /* System call */
5077 if (PPC_LEV (insn
) != 0)
5080 if (tdep
->ppc_syscall_record
!= NULL
)
5082 if (tdep
->ppc_syscall_record (regcache
) != 0)
5087 printf_unfiltered (_("no syscall record support\n"));
5092 case 7: /* Multiply Low Immediate */
5093 record_full_arch_list_add_reg (regcache
,
5094 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5097 case 8: /* Subtract From Immediate Carrying */
5098 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5099 record_full_arch_list_add_reg (regcache
,
5100 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5103 case 10: /* Compare Logical Immediate */
5104 case 11: /* Compare Immediate */
5105 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5108 case 13: /* Add Immediate Carrying and Record */
5109 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5111 case 12: /* Add Immediate Carrying */
5112 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5114 case 14: /* Add Immediate */
5115 case 15: /* Add Immediate Shifted */
5116 record_full_arch_list_add_reg (regcache
,
5117 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5120 case 16: /* Branch Conditional */
5121 if ((PPC_BO (insn
) & 0x4) == 0)
5122 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5124 case 18: /* Branch */
5126 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5130 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5134 case 20: /* Rotate Left Word Immediate then Mask Insert */
5135 case 21: /* Rotate Left Word Immediate then AND with Mask */
5136 case 23: /* Rotate Left Word then AND with Mask */
5137 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5138 /* Rotate Left Doubleword Immediate then Clear Right */
5139 /* Rotate Left Doubleword Immediate then Clear */
5140 /* Rotate Left Doubleword then Clear Left */
5141 /* Rotate Left Doubleword then Clear Right */
5142 /* Rotate Left Doubleword Immediate then Mask Insert */
5144 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5145 record_full_arch_list_add_reg (regcache
,
5146 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5149 case 28: /* AND Immediate */
5150 case 29: /* AND Immediate Shifted */
5151 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5153 case 24: /* OR Immediate */
5154 case 25: /* OR Immediate Shifted */
5155 case 26: /* XOR Immediate */
5156 case 27: /* XOR Immediate Shifted */
5157 record_full_arch_list_add_reg (regcache
,
5158 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5162 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5166 case 33: /* Load Word and Zero with Update */
5167 case 35: /* Load Byte and Zero with Update */
5168 case 41: /* Load Halfword and Zero with Update */
5169 case 43: /* Load Halfword Algebraic with Update */
5170 record_full_arch_list_add_reg (regcache
,
5171 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5173 case 32: /* Load Word and Zero */
5174 case 34: /* Load Byte and Zero */
5175 case 40: /* Load Halfword and Zero */
5176 case 42: /* Load Halfword Algebraic */
5177 record_full_arch_list_add_reg (regcache
,
5178 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5181 case 46: /* Load Multiple Word */
5182 for (i
= PPC_RT (insn
); i
< 32; i
++)
5183 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5186 case 56: /* Load Quadword */
5187 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5188 record_full_arch_list_add_reg (regcache
, tmp
);
5189 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5192 case 49: /* Load Floating-Point Single with Update */
5193 case 51: /* Load Floating-Point Double with Update */
5194 record_full_arch_list_add_reg (regcache
,
5195 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5197 case 48: /* Load Floating-Point Single */
5198 case 50: /* Load Floating-Point Double */
5199 record_full_arch_list_add_reg (regcache
,
5200 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5203 case 47: /* Store Multiple Word */
5207 if (PPC_RA (insn
) != 0)
5208 regcache_raw_read_unsigned (regcache
,
5209 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5212 addr
+= PPC_D (insn
);
5213 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5217 case 37: /* Store Word with Update */
5218 case 39: /* Store Byte with Update */
5219 case 45: /* Store Halfword with Update */
5220 case 53: /* Store Floating-Point Single with Update */
5221 case 55: /* Store Floating-Point Double with Update */
5222 record_full_arch_list_add_reg (regcache
,
5223 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5225 case 36: /* Store Word */
5226 case 38: /* Store Byte */
5227 case 44: /* Store Halfword */
5228 case 52: /* Store Floating-Point Single */
5229 case 54: /* Store Floating-Point Double */
5234 if (PPC_RA (insn
) != 0)
5235 regcache_raw_read_unsigned (regcache
,
5236 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5238 addr
+= PPC_D (insn
);
5240 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5242 else if (op6
== 54 || op6
== 55)
5244 else if (op6
== 44 || op6
== 45)
5246 else if (op6
== 38 || op6
== 39)
5251 record_full_arch_list_add_mem (addr
, size
);
5255 case 57: /* Load Floating-Point Double Pair */
5256 if (PPC_FIELD (insn
, 30, 2) != 0)
5258 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5259 record_full_arch_list_add_reg (regcache
, tmp
);
5260 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5263 case 58: /* Load Doubleword */
5264 /* Load Doubleword with Update */
5265 /* Load Word Algebraic */
5266 if (PPC_FIELD (insn
, 30, 2) > 2)
5269 record_full_arch_list_add_reg (regcache
,
5270 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5271 if (PPC_BIT (insn
, 31))
5272 record_full_arch_list_add_reg (regcache
,
5273 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5277 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5282 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5286 case 61: /* Store Floating-Point Double Pair */
5287 case 62: /* Store Doubleword */
5288 /* Store Doubleword with Update */
5289 /* Store Quadword with Update */
5293 int sub2
= PPC_FIELD (insn
, 30, 2);
5295 if ((op6
== 61 && sub2
!= 0) || (op6
== 62 && sub2
> 2))
5298 if (PPC_RA (insn
) != 0)
5299 regcache_raw_read_unsigned (regcache
,
5300 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5303 size
= ((op6
== 61) || sub2
== 2) ? 16 : 8;
5305 addr
+= PPC_DS (insn
) << 2;
5306 record_full_arch_list_add_mem (addr
, size
);
5308 if (op6
== 62 && sub2
== 1)
5309 record_full_arch_list_add_reg (regcache
,
5310 tdep
->ppc_gp0_regnum
+
5317 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5323 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5324 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5328 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5330 if (record_full_arch_list_add_end ())
5335 /* Initialize the current architecture based on INFO. If possible, re-use an
5336 architecture from ARCHES, which is a list of architectures already created
5337 during this debugging session.
5339 Called e.g. at program startup, when reading a core file, and when reading
5342 static struct gdbarch
*
5343 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5345 struct gdbarch
*gdbarch
;
5346 struct gdbarch_tdep
*tdep
;
5347 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5348 enum bfd_architecture arch
;
5351 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5353 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5354 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5355 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
5357 int tdesc_wordsize
= -1;
5358 const struct target_desc
*tdesc
= info
.target_desc
;
5359 struct tdesc_arch_data
*tdesc_data
= NULL
;
5360 int num_pseudoregs
= 0;
5363 /* INFO may refer to a binary that is not of the PowerPC architecture,
5364 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5365 In this case, we must not attempt to infer properties of the (PowerPC
5366 side) of the target system from properties of that executable. Trust
5367 the target description instead. */
5369 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5370 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5373 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5374 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5376 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5377 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5379 /* Check word size. If INFO is from a binary file, infer it from
5380 that, else choose a likely default. */
5381 if (from_xcoff_exec
)
5383 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5388 else if (from_elf_exec
)
5390 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5395 else if (tdesc_has_registers (tdesc
))
5399 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
5400 wordsize
= (info
.bfd_arch_info
->bits_per_word
5401 / info
.bfd_arch_info
->bits_per_byte
);
5406 /* Get the architecture and machine from the BFD. */
5407 arch
= info
.bfd_arch_info
->arch
;
5408 mach
= info
.bfd_arch_info
->mach
;
5410 /* For e500 executables, the apuinfo section is of help here. Such
5411 section contains the identifier and revision number of each
5412 Application-specific Processing Unit that is present on the
5413 chip. The content of the section is determined by the assembler
5414 which looks at each instruction and determines which unit (and
5415 which version of it) can execute it. Grovel through the section
5416 looking for relevant e500 APUs. */
5418 if (bfd_uses_spe_extensions (info
.abfd
))
5420 arch
= info
.bfd_arch_info
->arch
;
5421 mach
= bfd_mach_ppc_e500
;
5422 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
5423 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
5426 /* Find a default target description which describes our register
5427 layout, if we do not already have one. */
5428 if (! tdesc_has_registers (tdesc
))
5430 const struct variant
*v
;
5432 /* Choose variant. */
5433 v
= find_variant_by_arch (arch
, mach
);
5440 gdb_assert (tdesc_has_registers (tdesc
));
5442 /* Check any target description for validity. */
5443 if (tdesc_has_registers (tdesc
))
5445 static const char *const gprs
[] = {
5446 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5447 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5448 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5449 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5451 const struct tdesc_feature
*feature
;
5453 static const char *const msr_names
[] = { "msr", "ps" };
5454 static const char *const cr_names
[] = { "cr", "cnd" };
5455 static const char *const ctr_names
[] = { "ctr", "cnt" };
5457 feature
= tdesc_find_feature (tdesc
,
5458 "org.gnu.gdb.power.core");
5459 if (feature
== NULL
)
5462 tdesc_data
= tdesc_data_alloc ();
5465 for (i
= 0; i
< ppc_num_gprs
; i
++)
5466 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
5467 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
5469 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
5471 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
5474 /* Allow alternate names for these registers, to accomodate GDB's
5476 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5477 PPC_MSR_REGNUM
, msr_names
);
5478 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5479 PPC_CR_REGNUM
, cr_names
);
5480 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5481 PPC_CTR_REGNUM
, ctr_names
);
5485 tdesc_data_cleanup (tdesc_data
);
5489 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
5492 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
5494 wordsize
= tdesc_wordsize
;
5496 feature
= tdesc_find_feature (tdesc
,
5497 "org.gnu.gdb.power.fpu");
5498 if (feature
!= NULL
)
5500 static const char *const fprs
[] = {
5501 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5502 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5503 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5504 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
5507 for (i
= 0; i
< ppc_num_fprs
; i
++)
5508 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5509 PPC_F0_REGNUM
+ i
, fprs
[i
]);
5510 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5511 PPC_FPSCR_REGNUM
, "fpscr");
5515 tdesc_data_cleanup (tdesc_data
);
5523 /* The DFP pseudo-registers will be available when there are floating
5525 have_dfp
= have_fpu
;
5527 feature
= tdesc_find_feature (tdesc
,
5528 "org.gnu.gdb.power.altivec");
5529 if (feature
!= NULL
)
5531 static const char *const vector_regs
[] = {
5532 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
5533 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
5534 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
5535 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
5539 for (i
= 0; i
< ppc_num_gprs
; i
++)
5540 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5543 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5544 PPC_VSCR_REGNUM
, "vscr");
5545 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5546 PPC_VRSAVE_REGNUM
, "vrsave");
5548 if (have_spe
|| !valid_p
)
5550 tdesc_data_cleanup (tdesc_data
);
5558 /* Check for POWER7 VSX registers support. */
5559 feature
= tdesc_find_feature (tdesc
,
5560 "org.gnu.gdb.power.vsx");
5562 if (feature
!= NULL
)
5564 static const char *const vsx_regs
[] = {
5565 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
5566 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
5567 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
5568 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
5569 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
5575 for (i
= 0; i
< ppc_num_vshrs
; i
++)
5576 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5577 PPC_VSR0_UPPER_REGNUM
+ i
,
5581 tdesc_data_cleanup (tdesc_data
);
5590 /* On machines supporting the SPE APU, the general-purpose registers
5591 are 64 bits long. There are SIMD vector instructions to treat them
5592 as pairs of floats, but the rest of the instruction set treats them
5593 as 32-bit registers, and only operates on their lower halves.
5595 In the GDB regcache, we treat their high and low halves as separate
5596 registers. The low halves we present as the general-purpose
5597 registers, and then we have pseudo-registers that stitch together
5598 the upper and lower halves and present them as pseudo-registers.
5600 Thus, the target description is expected to supply the upper
5601 halves separately. */
5603 feature
= tdesc_find_feature (tdesc
,
5604 "org.gnu.gdb.power.spe");
5605 if (feature
!= NULL
)
5607 static const char *const upper_spe
[] = {
5608 "ev0h", "ev1h", "ev2h", "ev3h",
5609 "ev4h", "ev5h", "ev6h", "ev7h",
5610 "ev8h", "ev9h", "ev10h", "ev11h",
5611 "ev12h", "ev13h", "ev14h", "ev15h",
5612 "ev16h", "ev17h", "ev18h", "ev19h",
5613 "ev20h", "ev21h", "ev22h", "ev23h",
5614 "ev24h", "ev25h", "ev26h", "ev27h",
5615 "ev28h", "ev29h", "ev30h", "ev31h"
5619 for (i
= 0; i
< ppc_num_gprs
; i
++)
5620 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5621 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
5623 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5624 PPC_SPE_ACC_REGNUM
, "acc");
5625 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5626 PPC_SPE_FSCR_REGNUM
, "spefscr");
5628 if (have_mq
|| have_fpu
|| !valid_p
)
5630 tdesc_data_cleanup (tdesc_data
);
5639 /* If we have a 64-bit binary on a 32-bit target, complain. Also
5640 complain for a 32-bit binary on a 64-bit target; we do not yet
5641 support that. For instance, the 32-bit ABI routines expect
5644 As long as there isn't an explicit target description, we'll
5645 choose one based on the BFD architecture and get a word size
5646 matching the binary (probably powerpc:common or
5647 powerpc:common64). So there is only trouble if a 64-bit target
5648 supplies a 64-bit description while debugging a 32-bit
5650 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
5652 tdesc_data_cleanup (tdesc_data
);
5659 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
5662 elf_abi
= POWERPC_ELF_V1
;
5665 elf_abi
= POWERPC_ELF_V2
;
5672 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
5674 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5675 Tag_GNU_Power_ABI_FP
))
5678 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
5681 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
5688 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
5690 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5691 Tag_GNU_Power_ABI_Vector
))
5694 vector_abi
= POWERPC_VEC_GENERIC
;
5697 vector_abi
= POWERPC_VEC_ALTIVEC
;
5700 vector_abi
= POWERPC_VEC_SPE
;
5708 /* At this point, the only supported ELF-based 64-bit little-endian
5709 operating system is GNU/Linux, and this uses the ELFv2 ABI by
5710 default. All other supported ELF-based operating systems use the
5711 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
5712 e.g. because we run a legacy binary, or have attached to a process
5713 and have not found any associated binary file, set the default
5714 according to this heuristic. */
5715 if (elf_abi
== POWERPC_ELF_AUTO
)
5717 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
5718 elf_abi
= POWERPC_ELF_V2
;
5720 elf_abi
= POWERPC_ELF_V1
;
5723 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
5725 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
5728 soft_float
= !have_fpu
;
5730 /* If we have a hard float binary or setting but no floating point
5731 registers, downgrade to soft float anyway. We're still somewhat
5732 useful in this scenario. */
5733 if (!soft_float
&& !have_fpu
)
5736 /* Similarly for vector registers. */
5737 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
5738 vector_abi
= POWERPC_VEC_GENERIC
;
5740 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
5741 vector_abi
= POWERPC_VEC_GENERIC
;
5743 if (vector_abi
== POWERPC_VEC_AUTO
)
5746 vector_abi
= POWERPC_VEC_ALTIVEC
;
5748 vector_abi
= POWERPC_VEC_SPE
;
5750 vector_abi
= POWERPC_VEC_GENERIC
;
5753 /* Do not limit the vector ABI based on available hardware, since we
5754 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
5756 /* Find a candidate among extant architectures. */
5757 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5759 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5761 /* Word size in the various PowerPC bfd_arch_info structs isn't
5762 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
5763 separate word size check. */
5764 tdep
= gdbarch_tdep (arches
->gdbarch
);
5765 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
5767 if (tdep
&& tdep
->soft_float
!= soft_float
)
5769 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
5771 if (tdep
&& tdep
->wordsize
== wordsize
)
5773 if (tdesc_data
!= NULL
)
5774 tdesc_data_cleanup (tdesc_data
);
5775 return arches
->gdbarch
;
5779 /* None found, create a new architecture from INFO, whose bfd_arch_info
5780 validity depends on the source:
5781 - executable useless
5782 - rs6000_host_arch() good
5784 - "set arch" trust blindly
5785 - GDB startup useless but harmless */
5787 tdep
= XCNEW (struct gdbarch_tdep
);
5788 tdep
->wordsize
= wordsize
;
5789 tdep
->elf_abi
= elf_abi
;
5790 tdep
->soft_float
= soft_float
;
5791 tdep
->vector_abi
= vector_abi
;
5793 gdbarch
= gdbarch_alloc (&info
, tdep
);
5795 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
5796 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
5797 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
5798 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
5799 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
5800 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
5801 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
5802 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
5804 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
5805 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
5806 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
5807 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
5808 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
5809 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
5810 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
5811 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
5813 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
5814 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
5815 set_gdbarch_deprecated_fp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
5816 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
5817 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
5819 /* The XML specification for PowerPC sensibly calls the MSR "msr".
5820 GDB traditionally called it "ps", though, so let GDB add an
5822 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
5825 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
5827 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
5829 /* Set lr_frame_offset. */
5831 tdep
->lr_frame_offset
= 16;
5833 tdep
->lr_frame_offset
= 4;
5835 if (have_spe
|| have_dfp
|| have_vsx
)
5837 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
5838 set_gdbarch_pseudo_register_write (gdbarch
,
5839 rs6000_pseudo_register_write
);
5842 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5844 /* Select instruction printer. */
5845 if (arch
== bfd_arch_rs6000
)
5846 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
5848 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
5850 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
5853 num_pseudoregs
+= 32;
5855 num_pseudoregs
+= 16;
5857 /* Include both VSX and Extended FP registers. */
5858 num_pseudoregs
+= 96;
5860 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
5862 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
5863 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
5864 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
5865 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
5866 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
5867 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
5868 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
5869 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
5870 set_gdbarch_char_signed (gdbarch
, 0);
5872 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
5875 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
5877 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
5878 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
5879 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
5881 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
5882 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
5885 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
5886 else if (wordsize
== 8)
5887 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
5889 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
5890 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
5891 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
5893 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5894 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
5896 /* The value of symbols of type N_SO and N_FUN maybe null when
5898 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
5900 /* Handles single stepping of atomic sequences. */
5901 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
5903 /* Not sure on this. FIXMEmgo */
5904 set_gdbarch_frame_args_skip (gdbarch
, 8);
5906 /* Helpers for function argument information. */
5907 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
5910 set_gdbarch_in_solib_return_trampoline
5911 (gdbarch
, rs6000_in_solib_return_trampoline
);
5912 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
5914 /* Hook in the DWARF CFI frame unwinder. */
5915 dwarf2_append_unwinders (gdbarch
);
5916 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
5918 /* Frame handling. */
5919 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
5921 /* Setup displaced stepping. */
5922 set_gdbarch_displaced_step_copy_insn (gdbarch
,
5923 simple_displaced_step_copy_insn
);
5924 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
5925 ppc_displaced_step_hw_singlestep
);
5926 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
5927 set_gdbarch_displaced_step_free_closure (gdbarch
,
5928 simple_displaced_step_free_closure
);
5929 set_gdbarch_displaced_step_location (gdbarch
,
5930 displaced_step_at_entry_point
);
5932 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
5934 /* Hook in ABI-specific overrides, if they have been registered. */
5935 info
.target_desc
= tdesc
;
5936 info
.tdep_info
= (void *) tdesc_data
;
5937 gdbarch_init_osabi (info
, gdbarch
);
5941 case GDB_OSABI_LINUX
:
5942 case GDB_OSABI_NETBSD_AOUT
:
5943 case GDB_OSABI_NETBSD_ELF
:
5944 case GDB_OSABI_UNKNOWN
:
5945 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
5946 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
5947 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
5948 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
5949 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
5952 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
5954 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
5955 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
5956 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
5957 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
5958 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
5961 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
5962 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
5963 rs6000_pseudo_register_reggroup_p
);
5964 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
5966 /* Override the normal target description method to make the SPE upper
5967 halves anonymous. */
5968 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
5970 /* Choose register numbers for all supported pseudo-registers. */
5971 tdep
->ppc_ev0_regnum
= -1;
5972 tdep
->ppc_dl0_regnum
= -1;
5973 tdep
->ppc_vsr0_regnum
= -1;
5974 tdep
->ppc_efpr0_regnum
= -1;
5976 cur_reg
= gdbarch_num_regs (gdbarch
);
5980 tdep
->ppc_ev0_regnum
= cur_reg
;
5985 tdep
->ppc_dl0_regnum
= cur_reg
;
5990 tdep
->ppc_vsr0_regnum
= cur_reg
;
5992 tdep
->ppc_efpr0_regnum
= cur_reg
;
5996 gdb_assert (gdbarch_num_regs (gdbarch
)
5997 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
5999 /* Register the ravenscar_arch_ops. */
6000 if (mach
== bfd_mach_ppc_e500
)
6001 register_e500_ravenscar_ops (gdbarch
);
6003 register_ppc_ravenscar_ops (gdbarch
);
6009 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6011 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6016 /* FIXME: Dump gdbarch_tdep. */
6019 /* PowerPC-specific commands. */
6022 set_powerpc_command (char *args
, int from_tty
)
6024 printf_unfiltered (_("\
6025 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6026 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6030 show_powerpc_command (char *args
, int from_tty
)
6032 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6036 powerpc_set_soft_float (char *args
, int from_tty
,
6037 struct cmd_list_element
*c
)
6039 struct gdbarch_info info
;
6041 /* Update the architecture. */
6042 gdbarch_info_init (&info
);
6043 if (!gdbarch_update_p (info
))
6044 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6048 powerpc_set_vector_abi (char *args
, int from_tty
,
6049 struct cmd_list_element
*c
)
6051 struct gdbarch_info info
;
6054 for (vector_abi
= POWERPC_VEC_AUTO
;
6055 vector_abi
!= POWERPC_VEC_LAST
;
6057 if (strcmp (powerpc_vector_abi_string
,
6058 powerpc_vector_strings
[vector_abi
]) == 0)
6060 powerpc_vector_abi_global
= vector_abi
;
6064 if (vector_abi
== POWERPC_VEC_LAST
)
6065 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6066 powerpc_vector_abi_string
);
6068 /* Update the architecture. */
6069 gdbarch_info_init (&info
);
6070 if (!gdbarch_update_p (info
))
6071 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6074 /* Show the current setting of the exact watchpoints flag. */
6077 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6078 struct cmd_list_element
*c
,
6081 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6084 /* Read a PPC instruction from memory. */
6087 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6089 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6090 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6092 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6095 /* Return non-zero if the instructions at PC match the series
6096 described in PATTERN, or zero otherwise. PATTERN is an array of
6097 'struct ppc_insn_pattern' objects, terminated by an entry whose
6100 When the match is successful, fill INSN[i] with what PATTERN[i]
6101 matched. If PATTERN[i] is optional, and the instruction wasn't
6102 present, set INSN[i] to 0 (which is not a valid PPC instruction).
6103 INSN should have as many elements as PATTERN. Note that, if
6104 PATTERN contains optional instructions which aren't present in
6105 memory, then INSN will have holes, so INSN[i] isn't necessarily the
6106 i'th instruction in memory. */
6109 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6110 struct ppc_insn_pattern
*pattern
,
6111 unsigned int *insns
)
6116 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6119 insn
= read_insn (frame
, pc
);
6121 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6127 else if (!pattern
[i
].optional
)
6134 /* Return the 'd' field of the d-form instruction INSN, properly
6138 ppc_insn_d_field (unsigned int insn
)
6140 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6143 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6144 zero bits concatenated at the right, and properly
6148 ppc_insn_ds_field (unsigned int insn
)
6150 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6153 /* Initialization code. */
6155 /* -Wmissing-prototypes */
6156 extern initialize_file_ftype _initialize_rs6000_tdep
;
6159 _initialize_rs6000_tdep (void)
6161 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6162 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6164 /* Initialize the standard target descriptions. */
6165 initialize_tdesc_powerpc_32 ();
6166 initialize_tdesc_powerpc_altivec32 ();
6167 initialize_tdesc_powerpc_vsx32 ();
6168 initialize_tdesc_powerpc_403 ();
6169 initialize_tdesc_powerpc_403gc ();
6170 initialize_tdesc_powerpc_405 ();
6171 initialize_tdesc_powerpc_505 ();
6172 initialize_tdesc_powerpc_601 ();
6173 initialize_tdesc_powerpc_602 ();
6174 initialize_tdesc_powerpc_603 ();
6175 initialize_tdesc_powerpc_604 ();
6176 initialize_tdesc_powerpc_64 ();
6177 initialize_tdesc_powerpc_altivec64 ();
6178 initialize_tdesc_powerpc_vsx64 ();
6179 initialize_tdesc_powerpc_7400 ();
6180 initialize_tdesc_powerpc_750 ();
6181 initialize_tdesc_powerpc_860 ();
6182 initialize_tdesc_powerpc_e500 ();
6183 initialize_tdesc_rs6000 ();
6185 /* Add root prefix command for all "set powerpc"/"show powerpc"
6187 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6188 _("Various PowerPC-specific commands."),
6189 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6191 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6192 _("Various PowerPC-specific commands."),
6193 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6195 /* Add a command to allow the user to force the ABI. */
6196 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6197 &powerpc_soft_float_global
,
6198 _("Set whether to use a soft-float ABI."),
6199 _("Show whether to use a soft-float ABI."),
6201 powerpc_set_soft_float
, NULL
,
6202 &setpowerpccmdlist
, &showpowerpccmdlist
);
6204 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6205 &powerpc_vector_abi_string
,
6206 _("Set the vector ABI."),
6207 _("Show the vector ABI."),
6208 NULL
, powerpc_set_vector_abi
, NULL
,
6209 &setpowerpccmdlist
, &showpowerpccmdlist
);
6211 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6212 &target_exact_watchpoints
,
6214 Set whether to use just one debug register for watchpoints on scalars."),
6216 Show whether to use just one debug register for watchpoints on scalars."),
6218 If true, GDB will use only one debug register when watching a variable of\n\
6219 scalar type, thus assuming that the variable is accessed through the address\n\
6220 of its first byte."),
6221 NULL
, show_powerpc_exact_watchpoints
,
6222 &setpowerpccmdlist
, &showpowerpccmdlist
);