1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "libbfd.h" /* for bfd_default_set_arch_mach */
41 #include "coff/internal.h" /* for libcoff.h */
42 #include "libcoff.h" /* for xcoff_data */
43 #include "coff/xcoff.h"
48 #include "solib-svr4.h"
51 #include "gdb_assert.h"
54 #include "trad-frame.h"
55 #include "frame-unwind.h"
56 #include "frame-base.h"
58 /* If the kernel has to deliver a signal, it pushes a sigcontext
59 structure on the stack and then calls the signal handler, passing
60 the address of the sigcontext in an argument register. Usually
61 the signal handler doesn't save this register, so we have to
62 access the sigcontext structure via an offset from the signal handler
64 The following constants were determined by experimentation on AIX 3.2. */
65 #define SIG_FRAME_PC_OFFSET 96
66 #define SIG_FRAME_LR_OFFSET 108
67 #define SIG_FRAME_FP_OFFSET 284
69 /* To be used by skip_prologue. */
71 struct rs6000_framedata
73 int offset
; /* total size of frame --- the distance
74 by which we decrement sp to allocate
76 int saved_gpr
; /* smallest # of saved gpr */
77 int saved_fpr
; /* smallest # of saved fpr */
78 int saved_vr
; /* smallest # of saved vr */
79 int saved_ev
; /* smallest # of saved ev */
80 int alloca_reg
; /* alloca register number (frame ptr) */
81 char frameless
; /* true if frameless functions. */
82 char nosavedpc
; /* true if pc not saved. */
83 int gpr_offset
; /* offset of saved gprs from prev sp */
84 int fpr_offset
; /* offset of saved fprs from prev sp */
85 int vr_offset
; /* offset of saved vrs from prev sp */
86 int ev_offset
; /* offset of saved evs from prev sp */
87 int lr_offset
; /* offset of saved lr */
88 int cr_offset
; /* offset of saved cr */
89 int vrsave_offset
; /* offset of saved vrsave register */
92 /* Description of a single register. */
96 char *name
; /* name of register */
97 unsigned char sz32
; /* size on 32-bit arch, 0 if nonextant */
98 unsigned char sz64
; /* size on 64-bit arch, 0 if nonextant */
99 unsigned char fpr
; /* whether register is floating-point */
100 unsigned char pseudo
; /* whether register is pseudo */
103 /* Breakpoint shadows for the single step instructions will be kept here. */
105 static struct sstep_breaks
107 /* Address, or 0 if this is not in use. */
109 /* Shadow contents. */
114 /* Hook for determining the TOC address when calling functions in the
115 inferior under AIX. The initialization code in rs6000-nat.c sets
116 this hook to point to find_toc_address. */
118 CORE_ADDR (*rs6000_find_toc_address_hook
) (CORE_ADDR
) = NULL
;
120 /* Hook to set the current architecture when starting a child process.
121 rs6000-nat.c sets this. */
123 void (*rs6000_set_host_arch_hook
) (int) = NULL
;
125 /* Static function prototypes */
127 static CORE_ADDR
branch_dest (int opcode
, int instr
, CORE_ADDR pc
,
129 static CORE_ADDR
skip_prologue (CORE_ADDR
, CORE_ADDR
,
130 struct rs6000_framedata
*);
132 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
134 altivec_register_p (int regno
)
136 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
137 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
140 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
144 /* Return non-zero if the architecture described by GDBARCH has
145 floating-point registers (f0 --- f31 and fpscr). */
147 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
149 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
151 return (tdep
->ppc_fp0_regnum
>= 0
152 && tdep
->ppc_fpscr_regnum
>= 0);
156 /* Register set support functions. */
159 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
160 const char *regs
, size_t offset
)
162 if (regnum
!= -1 && offset
!= -1)
163 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
167 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
168 char *regs
, size_t offset
)
170 if (regnum
!= -1 && offset
!= -1)
171 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
174 /* Supply register REGNUM in the general-purpose register set REGSET
175 from the buffer specified by GREGS and LEN to register cache
176 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
179 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
180 int regnum
, const void *gregs
, size_t len
)
182 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
183 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
184 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
188 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
189 i
< tdep
->ppc_gp0_regnum
+ 32;
192 if (regnum
== -1 || regnum
== i
)
193 ppc_supply_reg (regcache
, i
, gregs
, offset
);
196 if (regnum
== -1 || regnum
== PC_REGNUM
)
197 ppc_supply_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
198 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
199 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
200 gregs
, offsets
->ps_offset
);
201 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
202 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
203 gregs
, offsets
->cr_offset
);
204 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
205 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
206 gregs
, offsets
->lr_offset
);
207 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
208 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
209 gregs
, offsets
->ctr_offset
);
210 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
211 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
212 gregs
, offsets
->cr_offset
);
213 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
214 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
, gregs
, offsets
->mq_offset
);
217 /* Supply register REGNUM in the floating-point register set REGSET
218 from the buffer specified by FPREGS and LEN to register cache
219 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
222 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
223 int regnum
, const void *fpregs
, size_t len
)
225 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
226 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
231 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
233 offset
= offsets
->f0_offset
;
234 for (i
= tdep
->ppc_fp0_regnum
;
235 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
238 if (regnum
== -1 || regnum
== i
)
239 ppc_supply_reg (regcache
, i
, fpregs
, offset
);
242 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
243 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
244 fpregs
, offsets
->fpscr_offset
);
247 /* Collect register REGNUM in the general-purpose register set
248 REGSET. from register cache REGCACHE into the buffer specified by
249 GREGS and LEN. If REGNUM is -1, do this for all registers in
253 ppc_collect_gregset (const struct regset
*regset
,
254 const struct regcache
*regcache
,
255 int regnum
, void *gregs
, size_t len
)
257 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
258 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
259 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
263 offset
= offsets
->r0_offset
;
264 for (i
= tdep
->ppc_gp0_regnum
;
265 i
< tdep
->ppc_gp0_regnum
+ 32;
268 if (regnum
== -1 || regnum
== i
)
269 ppc_collect_reg (regcache
, i
, gregs
, offset
);
272 if (regnum
== -1 || regnum
== PC_REGNUM
)
273 ppc_collect_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
274 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
275 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
276 gregs
, offsets
->ps_offset
);
277 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
278 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
279 gregs
, offsets
->cr_offset
);
280 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
281 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
282 gregs
, offsets
->lr_offset
);
283 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
284 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
285 gregs
, offsets
->ctr_offset
);
286 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
287 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
288 gregs
, offsets
->xer_offset
);
289 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
290 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
291 gregs
, offsets
->mq_offset
);
294 /* Collect register REGNUM in the floating-point register set
295 REGSET. from register cache REGCACHE into the buffer specified by
296 FPREGS and LEN. If REGNUM is -1, do this for all registers in
300 ppc_collect_fpregset (const struct regset
*regset
,
301 const struct regcache
*regcache
,
302 int regnum
, void *fpregs
, size_t len
)
304 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
305 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
306 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
310 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
312 offset
= offsets
->f0_offset
;
313 for (i
= tdep
->ppc_fp0_regnum
;
314 i
<= tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
317 if (regnum
== -1 || regnum
== i
)
318 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
);
321 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
322 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
323 fpregs
, offsets
->fpscr_offset
);
327 /* Read a LEN-byte address from debugged memory address MEMADDR. */
330 read_memory_addr (CORE_ADDR memaddr
, int len
)
332 return read_memory_unsigned_integer (memaddr
, len
);
336 rs6000_skip_prologue (CORE_ADDR pc
)
338 struct rs6000_framedata frame
;
339 pc
= skip_prologue (pc
, 0, &frame
);
344 /* Fill in fi->saved_regs */
346 struct frame_extra_info
348 /* Functions calling alloca() change the value of the stack
349 pointer. We need to use initial stack pointer (which is saved in
350 r31 by gcc) in such cases. If a compiler emits traceback table,
351 then we should use the alloca register specified in traceback
353 CORE_ADDR initial_sp
; /* initial stack pointer. */
356 /* Get the ith function argument for the current function. */
358 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
362 get_frame_register (frame
, 3 + argi
, &addr
);
366 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
369 branch_dest (int opcode
, int instr
, CORE_ADDR pc
, CORE_ADDR safety
)
376 absolute
= (int) ((instr
>> 1) & 1);
381 immediate
= ((instr
& ~3) << 6) >> 6; /* br unconditional */
385 dest
= pc
+ immediate
;
389 immediate
= ((instr
& ~3) << 16) >> 16; /* br conditional */
393 dest
= pc
+ immediate
;
397 ext_op
= (instr
>> 1) & 0x3ff;
399 if (ext_op
== 16) /* br conditional register */
401 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
403 /* If we are about to return from a signal handler, dest is
404 something like 0x3c90. The current frame is a signal handler
405 caller frame, upon completion of the sigreturn system call
406 execution will return to the saved PC in the frame. */
407 if (dest
< TEXT_SEGMENT_BASE
)
409 struct frame_info
*fi
;
411 fi
= get_current_frame ();
413 dest
= read_memory_addr (get_frame_base (fi
) + SIG_FRAME_PC_OFFSET
,
414 gdbarch_tdep (current_gdbarch
)->wordsize
);
418 else if (ext_op
== 528) /* br cond to count reg */
420 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_ctr_regnum
) & ~3;
422 /* If we are about to execute a system call, dest is something
423 like 0x22fc or 0x3b00. Upon completion the system call
424 will return to the address in the link register. */
425 if (dest
< TEXT_SEGMENT_BASE
)
426 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
435 return (dest
< TEXT_SEGMENT_BASE
) ? safety
: dest
;
439 /* Sequence of bytes for breakpoint instruction. */
441 const static unsigned char *
442 rs6000_breakpoint_from_pc (CORE_ADDR
*bp_addr
, int *bp_size
)
444 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
445 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
447 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
448 return big_breakpoint
;
450 return little_breakpoint
;
454 /* AIX does not support PT_STEP. Simulate it. */
457 rs6000_software_single_step (enum target_signal signal
,
458 int insert_breakpoints_p
)
462 const char *breakp
= rs6000_breakpoint_from_pc (&dummy
, &breakp_sz
);
468 if (insert_breakpoints_p
)
473 insn
= read_memory_integer (loc
, 4);
475 breaks
[0] = loc
+ breakp_sz
;
477 breaks
[1] = branch_dest (opcode
, insn
, loc
, breaks
[0]);
479 /* Don't put two breakpoints on the same address. */
480 if (breaks
[1] == breaks
[0])
483 stepBreaks
[1].address
= 0;
485 for (ii
= 0; ii
< 2; ++ii
)
488 /* ignore invalid breakpoint. */
489 if (breaks
[ii
] == -1)
491 target_insert_breakpoint (breaks
[ii
], stepBreaks
[ii
].data
);
492 stepBreaks
[ii
].address
= breaks
[ii
];
499 /* remove step breakpoints. */
500 for (ii
= 0; ii
< 2; ++ii
)
501 if (stepBreaks
[ii
].address
!= 0)
502 target_remove_breakpoint (stepBreaks
[ii
].address
,
503 stepBreaks
[ii
].data
);
505 errno
= 0; /* FIXME, don't ignore errors! */
506 /* What errors? {read,write}_memory call error(). */
510 /* return pc value after skipping a function prologue and also return
511 information about a function frame.
513 in struct rs6000_framedata fdata:
514 - frameless is TRUE, if function does not have a frame.
515 - nosavedpc is TRUE, if function does not save %pc value in its frame.
516 - offset is the initial size of this stack frame --- the amount by
517 which we decrement the sp to allocate the frame.
518 - saved_gpr is the number of the first saved gpr.
519 - saved_fpr is the number of the first saved fpr.
520 - saved_vr is the number of the first saved vr.
521 - saved_ev is the number of the first saved ev.
522 - alloca_reg is the number of the register used for alloca() handling.
524 - gpr_offset is the offset of the first saved gpr from the previous frame.
525 - fpr_offset is the offset of the first saved fpr from the previous frame.
526 - vr_offset is the offset of the first saved vr from the previous frame.
527 - ev_offset is the offset of the first saved ev from the previous frame.
528 - lr_offset is the offset of the saved lr
529 - cr_offset is the offset of the saved cr
530 - vrsave_offset is the offset of the saved vrsave register
533 #define SIGNED_SHORT(x) \
534 ((sizeof (short) == 2) \
535 ? ((int)(short)(x)) \
536 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
538 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
540 /* Limit the number of skipped non-prologue instructions, as the examining
541 of the prologue is expensive. */
542 static int max_skip_non_prologue_insns
= 10;
544 /* Given PC representing the starting address of a function, and
545 LIM_PC which is the (sloppy) limit to which to scan when looking
546 for a prologue, attempt to further refine this limit by using
547 the line data in the symbol table. If successful, a better guess
548 on where the prologue ends is returned, otherwise the previous
549 value of lim_pc is returned. */
551 /* FIXME: cagney/2004-02-14: This function and logic have largely been
552 superseded by skip_prologue_using_sal. */
555 refine_prologue_limit (CORE_ADDR pc
, CORE_ADDR lim_pc
)
557 struct symtab_and_line prologue_sal
;
559 prologue_sal
= find_pc_line (pc
, 0);
560 if (prologue_sal
.line
!= 0)
563 CORE_ADDR addr
= prologue_sal
.end
;
565 /* Handle the case in which compiler's optimizer/scheduler
566 has moved instructions into the prologue. We scan ahead
567 in the function looking for address ranges whose corresponding
568 line number is less than or equal to the first one that we
569 found for the function. (It can be less than when the
570 scheduler puts a body instruction before the first prologue
572 for (i
= 2 * max_skip_non_prologue_insns
;
573 i
> 0 && (lim_pc
== 0 || addr
< lim_pc
);
576 struct symtab_and_line sal
;
578 sal
= find_pc_line (addr
, 0);
581 if (sal
.line
<= prologue_sal
.line
582 && sal
.symtab
== prologue_sal
.symtab
)
589 if (lim_pc
== 0 || prologue_sal
.end
< lim_pc
)
590 lim_pc
= prologue_sal
.end
;
597 skip_prologue (CORE_ADDR pc
, CORE_ADDR lim_pc
, struct rs6000_framedata
*fdata
)
599 CORE_ADDR orig_pc
= pc
;
600 CORE_ADDR last_prologue_pc
= pc
;
601 CORE_ADDR li_found_pc
= 0;
605 long vr_saved_offset
= 0;
614 int minimal_toc_loaded
= 0;
615 int prev_insn_was_prologue_insn
= 1;
616 int num_skip_non_prologue_insns
= 0;
617 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (current_gdbarch
);
618 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
620 /* Attempt to find the end of the prologue when no limit is specified.
621 Note that refine_prologue_limit() has been written so that it may
622 be used to "refine" the limits of non-zero PC values too, but this
623 is only safe if we 1) trust the line information provided by the
624 compiler and 2) iterate enough to actually find the end of the
627 It may become a good idea at some point (for both performance and
628 accuracy) to unconditionally call refine_prologue_limit(). But,
629 until we can make a clear determination that this is beneficial,
630 we'll play it safe and only use it to obtain a limit when none
631 has been specified. */
633 lim_pc
= refine_prologue_limit (pc
, lim_pc
);
635 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
636 fdata
->saved_gpr
= -1;
637 fdata
->saved_fpr
= -1;
638 fdata
->saved_vr
= -1;
639 fdata
->saved_ev
= -1;
640 fdata
->alloca_reg
= -1;
641 fdata
->frameless
= 1;
642 fdata
->nosavedpc
= 1;
646 /* Sometimes it isn't clear if an instruction is a prologue
647 instruction or not. When we encounter one of these ambiguous
648 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
649 Otherwise, we'll assume that it really is a prologue instruction. */
650 if (prev_insn_was_prologue_insn
)
651 last_prologue_pc
= pc
;
653 /* Stop scanning if we've hit the limit. */
654 if (lim_pc
!= 0 && pc
>= lim_pc
)
657 prev_insn_was_prologue_insn
= 1;
659 /* Fetch the instruction and convert it to an integer. */
660 if (target_read_memory (pc
, buf
, 4))
662 op
= extract_signed_integer (buf
, 4);
664 if ((op
& 0xfc1fffff) == 0x7c0802a6)
666 /* Since shared library / PIC code, which needs to get its
667 address at runtime, can appear to save more than one link
681 remember just the first one, but skip over additional
684 lr_reg
= (op
& 0x03e00000);
687 else if ((op
& 0xfc1fffff) == 0x7c000026)
689 cr_reg
= (op
& 0x03e00000);
693 else if ((op
& 0xfc1f0000) == 0xd8010000)
694 { /* stfd Rx,NUM(r1) */
695 reg
= GET_SRC_REG (op
);
696 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
698 fdata
->saved_fpr
= reg
;
699 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
704 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
705 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
706 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
707 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
710 reg
= GET_SRC_REG (op
);
711 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
713 fdata
->saved_gpr
= reg
;
714 if ((op
& 0xfc1f0003) == 0xf8010000)
716 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
721 else if ((op
& 0xffff0000) == 0x60000000)
724 /* Allow nops in the prologue, but do not consider them to
725 be part of the prologue unless followed by other prologue
727 prev_insn_was_prologue_insn
= 0;
731 else if ((op
& 0xffff0000) == 0x3c000000)
732 { /* addis 0,0,NUM, used
734 fdata
->offset
= (op
& 0x0000ffff) << 16;
735 fdata
->frameless
= 0;
739 else if ((op
& 0xffff0000) == 0x60000000)
740 { /* ori 0,0,NUM, 2nd ha
741 lf of >= 32k frames */
742 fdata
->offset
|= (op
& 0x0000ffff);
743 fdata
->frameless
= 0;
747 else if (lr_reg
!= -1 &&
748 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
749 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
750 /* stw Rx, NUM(r1) */
751 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
752 /* stwu Rx, NUM(r1) */
753 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
754 { /* where Rx == lr */
755 fdata
->lr_offset
= offset
;
756 fdata
->nosavedpc
= 0;
758 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
759 (op
& 0xfc000000) == 0x90000000) /* stw */
761 /* Does not update r1, so add displacement to lr_offset. */
762 fdata
->lr_offset
+= SIGNED_SHORT (op
);
767 else if (cr_reg
!= -1 &&
768 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
769 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
770 /* stw Rx, NUM(r1) */
771 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
772 /* stwu Rx, NUM(r1) */
773 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
774 { /* where Rx == cr */
775 fdata
->cr_offset
= offset
;
777 if ((op
& 0xfc000003) == 0xf8000000 ||
778 (op
& 0xfc000000) == 0x90000000)
780 /* Does not update r1, so add displacement to cr_offset. */
781 fdata
->cr_offset
+= SIGNED_SHORT (op
);
786 else if (op
== 0x48000005)
792 else if (op
== 0x48000004)
797 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
798 in V.4 -mminimal-toc */
799 (op
& 0xffff0000) == 0x3bde0000)
800 { /* addi 30,30,foo@l */
804 else if ((op
& 0xfc000001) == 0x48000001)
808 fdata
->frameless
= 0;
809 /* Don't skip over the subroutine call if it is not within
810 the first three instructions of the prologue. */
811 if ((pc
- orig_pc
) > 8)
814 op
= read_memory_integer (pc
+ 4, 4);
816 /* At this point, make sure this is not a trampoline
817 function (a function that simply calls another functions,
818 and nothing else). If the next is not a nop, this branch
819 was part of the function prologue. */
821 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
822 break; /* don't skip over
827 /* update stack pointer */
828 else if ((op
& 0xfc1f0000) == 0x94010000)
829 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
830 fdata
->frameless
= 0;
831 fdata
->offset
= SIGNED_SHORT (op
);
832 offset
= fdata
->offset
;
835 else if ((op
& 0xfc1f016a) == 0x7c01016e)
836 { /* stwux rX,r1,rY */
837 /* no way to figure out what r1 is going to be */
838 fdata
->frameless
= 0;
839 offset
= fdata
->offset
;
842 else if ((op
& 0xfc1f0003) == 0xf8010001)
843 { /* stdu rX,NUM(r1) */
844 fdata
->frameless
= 0;
845 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
846 offset
= fdata
->offset
;
849 else if ((op
& 0xfc1f016a) == 0x7c01016a)
850 { /* stdux rX,r1,rY */
851 /* no way to figure out what r1 is going to be */
852 fdata
->frameless
= 0;
853 offset
= fdata
->offset
;
856 /* Load up minimal toc pointer */
857 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
858 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
859 && !minimal_toc_loaded
)
861 minimal_toc_loaded
= 1;
864 /* move parameters from argument registers to local variable
867 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
868 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
869 (((op
>> 21) & 31) <= 10) &&
870 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
874 /* store parameters in stack */
876 /* Move parameters from argument registers to temporary register. */
877 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
878 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
879 (((op
>> 21) & 31) <= 10) &&
880 (((op
>> 16) & 31) == 0)) /* Rx: scratch register r0 */
884 else if ((op
& 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */
885 (op
& 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */
886 (op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
890 /* store parameters in stack via frame pointer */
893 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
894 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
895 (op
& 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r31) */
896 (op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
900 /* Set up frame pointer */
902 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
905 fdata
->frameless
= 0;
907 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
910 /* Another way to set up the frame pointer. */
912 else if ((op
& 0xfc1fffff) == 0x38010000)
913 { /* addi rX, r1, 0x0 */
914 fdata
->frameless
= 0;
916 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
917 + ((op
& ~0x38010000) >> 21));
920 /* AltiVec related instructions. */
921 /* Store the vrsave register (spr 256) in another register for
922 later manipulation, or load a register into the vrsave
923 register. 2 instructions are used: mfvrsave and
924 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
925 and mtspr SPR256, Rn. */
926 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
927 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
928 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
930 vrsave_reg
= GET_SRC_REG (op
);
933 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
937 /* Store the register where vrsave was saved to onto the stack:
938 rS is the register where vrsave was stored in a previous
940 /* 100100 sssss 00001 dddddddd dddddddd */
941 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
943 if (vrsave_reg
== GET_SRC_REG (op
))
945 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
950 /* Compute the new value of vrsave, by modifying the register
951 where vrsave was saved to. */
952 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
953 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
957 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
958 in a pair of insns to save the vector registers on the
960 /* 001110 00000 00000 iiii iiii iiii iiii */
961 /* 001110 01110 00000 iiii iiii iiii iiii */
962 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
963 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
966 vr_saved_offset
= SIGNED_SHORT (op
);
968 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
969 /* 011111 sssss 11111 00000 00111001110 */
970 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
972 if (pc
== (li_found_pc
+ 4))
974 vr_reg
= GET_SRC_REG (op
);
975 /* If this is the first vector reg to be saved, or if
976 it has a lower number than others previously seen,
977 reupdate the frame info. */
978 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
980 fdata
->saved_vr
= vr_reg
;
981 fdata
->vr_offset
= vr_saved_offset
+ offset
;
983 vr_saved_offset
= -1;
988 /* End AltiVec related instructions. */
990 /* Start BookE related instructions. */
991 /* Store gen register S at (r31+uimm).
992 Any register less than r13 is volatile, so we don't care. */
993 /* 000100 sssss 11111 iiiii 01100100001 */
994 else if (arch_info
->mach
== bfd_mach_ppc_e500
995 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
997 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1000 ev_reg
= GET_SRC_REG (op
);
1001 imm
= (op
>> 11) & 0x1f;
1002 ev_offset
= imm
* 8;
1003 /* If this is the first vector reg to be saved, or if
1004 it has a lower number than others previously seen,
1005 reupdate the frame info. */
1006 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1008 fdata
->saved_ev
= ev_reg
;
1009 fdata
->ev_offset
= ev_offset
+ offset
;
1014 /* Store gen register rS at (r1+rB). */
1015 /* 000100 sssss 00001 bbbbb 01100100000 */
1016 else if (arch_info
->mach
== bfd_mach_ppc_e500
1017 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1019 if (pc
== (li_found_pc
+ 4))
1021 ev_reg
= GET_SRC_REG (op
);
1022 /* If this is the first vector reg to be saved, or if
1023 it has a lower number than others previously seen,
1024 reupdate the frame info. */
1025 /* We know the contents of rB from the previous instruction. */
1026 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1028 fdata
->saved_ev
= ev_reg
;
1029 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1031 vr_saved_offset
= -1;
1037 /* Store gen register r31 at (rA+uimm). */
1038 /* 000100 11111 aaaaa iiiii 01100100001 */
1039 else if (arch_info
->mach
== bfd_mach_ppc_e500
1040 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1042 /* Wwe know that the source register is 31 already, but
1043 it can't hurt to compute it. */
1044 ev_reg
= GET_SRC_REG (op
);
1045 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1046 /* If this is the first vector reg to be saved, or if
1047 it has a lower number than others previously seen,
1048 reupdate the frame info. */
1049 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1051 fdata
->saved_ev
= ev_reg
;
1052 fdata
->ev_offset
= ev_offset
+ offset
;
1057 /* Store gen register S at (r31+r0).
1058 Store param on stack when offset from SP bigger than 4 bytes. */
1059 /* 000100 sssss 11111 00000 01100100000 */
1060 else if (arch_info
->mach
== bfd_mach_ppc_e500
1061 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1063 if (pc
== (li_found_pc
+ 4))
1065 if ((op
& 0x03e00000) >= 0x01a00000)
1067 ev_reg
= GET_SRC_REG (op
);
1068 /* If this is the first vector reg to be saved, or if
1069 it has a lower number than others previously seen,
1070 reupdate the frame info. */
1071 /* We know the contents of r0 from the previous
1073 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1075 fdata
->saved_ev
= ev_reg
;
1076 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1080 vr_saved_offset
= -1;
1085 /* End BookE related instructions. */
1089 /* Not a recognized prologue instruction.
1090 Handle optimizer code motions into the prologue by continuing
1091 the search if we have no valid frame yet or if the return
1092 address is not yet saved in the frame. */
1093 if (fdata
->frameless
== 0
1094 && (lr_reg
== -1 || fdata
->nosavedpc
== 0))
1097 if (op
== 0x4e800020 /* blr */
1098 || op
== 0x4e800420) /* bctr */
1099 /* Do not scan past epilogue in frameless functions or
1102 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1103 /* Never skip branches. */
1106 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1107 /* Do not scan too many insns, scanning insns is expensive with
1111 /* Continue scanning. */
1112 prev_insn_was_prologue_insn
= 0;
1118 /* I have problems with skipping over __main() that I need to address
1119 * sometime. Previously, I used to use misc_function_vector which
1120 * didn't work as well as I wanted to be. -MGO */
1122 /* If the first thing after skipping a prolog is a branch to a function,
1123 this might be a call to an initializer in main(), introduced by gcc2.
1124 We'd like to skip over it as well. Fortunately, xlc does some extra
1125 work before calling a function right after a prologue, thus we can
1126 single out such gcc2 behaviour. */
1129 if ((op
& 0xfc000001) == 0x48000001)
1130 { /* bl foo, an initializer function? */
1131 op
= read_memory_integer (pc
+ 4, 4);
1133 if (op
== 0x4def7b82)
1134 { /* cror 0xf, 0xf, 0xf (nop) */
1136 /* Check and see if we are in main. If so, skip over this
1137 initializer function as well. */
1139 tmp
= find_pc_misc_function (pc
);
1141 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
1147 fdata
->offset
= -fdata
->offset
;
1148 return last_prologue_pc
;
1152 /*************************************************************************
1153 Support for creating pushing a dummy frame into the stack, and popping
1155 *************************************************************************/
1158 /* All the ABI's require 16 byte alignment. */
1160 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1162 return (addr
& -16);
1165 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1166 the first eight words of the argument list (that might be less than
1167 eight parameters if some parameters occupy more than one word) are
1168 passed in r3..r10 registers. float and double parameters are
1169 passed in fpr's, in addition to that. Rest of the parameters if any
1170 are passed in user stack. There might be cases in which half of the
1171 parameter is copied into registers, the other half is pushed into
1174 Stack must be aligned on 64-bit boundaries when synthesizing
1177 If the function is returning a structure, then the return address is passed
1178 in r3, then the first 7 words of the parameters can be passed in registers,
1179 starting from r4. */
1182 rs6000_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
1183 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1184 int nargs
, struct value
**args
, CORE_ADDR sp
,
1185 int struct_return
, CORE_ADDR struct_addr
)
1187 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1190 int argno
; /* current argument number */
1191 int argbytes
; /* current argument byte */
1192 char tmp_buffer
[50];
1193 int f_argno
= 0; /* current floating point argno */
1194 int wordsize
= gdbarch_tdep (current_gdbarch
)->wordsize
;
1196 struct value
*arg
= 0;
1201 /* The calling convention this function implements assumes the
1202 processor has floating-point registers. We shouldn't be using it
1203 on PPC variants that lack them. */
1204 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1206 /* The first eight words of ther arguments are passed in registers.
1207 Copy them appropriately. */
1210 /* If the function is returning a `struct', then the first word
1211 (which will be passed in r3) is used for struct return address.
1212 In that case we should advance one word and start from r4
1213 register to copy parameters. */
1216 regcache_raw_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1222 effectively indirect call... gcc does...
1224 return_val example( float, int);
1227 float in fp0, int in r3
1228 offset of stack on overflow 8/16
1229 for varargs, must go by type.
1231 float in r3&r4, int in r5
1232 offset of stack on overflow different
1234 return in r3 or f0. If no float, must study how gcc emulates floats;
1235 pay attention to arg promotion.
1236 User may have to cast\args to handle promotion correctly
1237 since gdb won't know if prototype supplied or not.
1240 for (argno
= 0, argbytes
= 0; argno
< nargs
&& ii
< 8; ++ii
)
1242 int reg_size
= DEPRECATED_REGISTER_RAW_SIZE (ii
+ 3);
1245 type
= check_typedef (VALUE_TYPE (arg
));
1246 len
= TYPE_LENGTH (type
);
1248 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1251 /* Floating point arguments are passed in fpr's, as well as gpr's.
1252 There are 13 fpr's reserved for passing parameters. At this point
1253 there is no way we would run out of them. */
1257 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno
);
1259 memcpy (&deprecated_registers
[DEPRECATED_REGISTER_BYTE
1260 (tdep
->ppc_fp0_regnum
+ 1 + f_argno
)],
1261 VALUE_CONTENTS (arg
),
1269 /* Argument takes more than one register. */
1270 while (argbytes
< len
)
1272 memset (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)], 0,
1274 memcpy (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)],
1275 ((char *) VALUE_CONTENTS (arg
)) + argbytes
,
1276 (len
- argbytes
) > reg_size
1277 ? reg_size
: len
- argbytes
);
1278 ++ii
, argbytes
+= reg_size
;
1281 goto ran_out_of_registers_for_arguments
;
1288 /* Argument can fit in one register. No problem. */
1289 int adj
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? reg_size
- len
: 0;
1290 memset (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)], 0, reg_size
);
1291 memcpy ((char *)&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)] + adj
,
1292 VALUE_CONTENTS (arg
), len
);
1297 ran_out_of_registers_for_arguments
:
1299 saved_sp
= read_sp ();
1301 /* Location for 8 parameters are always reserved. */
1304 /* Another six words for back chain, TOC register, link register, etc. */
1307 /* Stack pointer must be quadword aligned. */
1310 /* If there are more arguments, allocate space for them in
1311 the stack, then push them starting from the ninth one. */
1313 if ((argno
< nargs
) || argbytes
)
1319 space
+= ((len
- argbytes
+ 3) & -4);
1325 for (; jj
< nargs
; ++jj
)
1327 struct value
*val
= args
[jj
];
1328 space
+= ((TYPE_LENGTH (VALUE_TYPE (val
))) + 3) & -4;
1331 /* Add location required for the rest of the parameters. */
1332 space
= (space
+ 15) & -16;
1335 /* This is another instance we need to be concerned about
1336 securing our stack space. If we write anything underneath %sp
1337 (r1), we might conflict with the kernel who thinks he is free
1338 to use this area. So, update %sp first before doing anything
1341 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1343 /* If the last argument copied into the registers didn't fit there
1344 completely, push the rest of it into stack. */
1348 write_memory (sp
+ 24 + (ii
* 4),
1349 ((char *) VALUE_CONTENTS (arg
)) + argbytes
,
1352 ii
+= ((len
- argbytes
+ 3) & -4) / 4;
1355 /* Push the rest of the arguments into stack. */
1356 for (; argno
< nargs
; ++argno
)
1360 type
= check_typedef (VALUE_TYPE (arg
));
1361 len
= TYPE_LENGTH (type
);
1364 /* Float types should be passed in fpr's, as well as in the
1366 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& f_argno
< 13)
1371 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno
);
1373 memcpy (&(deprecated_registers
1374 [DEPRECATED_REGISTER_BYTE
1375 (tdep
->ppc_fp0_regnum
+ 1 + f_argno
)]),
1376 VALUE_CONTENTS (arg
),
1381 write_memory (sp
+ 24 + (ii
* 4), (char *) VALUE_CONTENTS (arg
), len
);
1382 ii
+= ((len
+ 3) & -4) / 4;
1386 /* Set the stack pointer. According to the ABI, the SP is meant to
1387 be set _before_ the corresponding stack space is used. On AIX,
1388 this even applies when the target has been completely stopped!
1389 Not doing this can lead to conflicts with the kernel which thinks
1390 that it still has control over this not-yet-allocated stack
1392 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1394 /* Set back chain properly. */
1395 store_unsigned_integer (tmp_buffer
, 4, saved_sp
);
1396 write_memory (sp
, tmp_buffer
, 4);
1398 /* Point the inferior function call's return address at the dummy's
1400 regcache_raw_write_signed (regcache
, tdep
->ppc_lr_regnum
, bp_addr
);
1402 /* Set the TOC register, get the value from the objfile reader
1403 which, in turn, gets it from the VMAP table. */
1404 if (rs6000_find_toc_address_hook
!= NULL
)
1406 CORE_ADDR tocvalue
= (*rs6000_find_toc_address_hook
) (func_addr
);
1407 regcache_raw_write_signed (regcache
, tdep
->ppc_toc_regnum
, tocvalue
);
1410 target_store_registers (-1);
1414 /* PowerOpen always puts structures in memory. Vectors, which were
1415 added later, do get returned in a register though. */
1418 rs6000_use_struct_convention (int gcc_p
, struct type
*value_type
)
1420 if ((TYPE_LENGTH (value_type
) == 16 || TYPE_LENGTH (value_type
) == 8)
1421 && TYPE_VECTOR (value_type
))
1427 rs6000_extract_return_value (struct type
*valtype
, char *regbuf
, char *valbuf
)
1430 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1432 /* The calling convention this function implements assumes the
1433 processor has floating-point registers. We shouldn't be using it
1434 on PPC variants that lack them. */
1435 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1437 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
)
1440 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1441 We need to truncate the return value into float size (4 byte) if
1444 convert_typed_floating (®buf
[DEPRECATED_REGISTER_BYTE
1445 (tdep
->ppc_fp0_regnum
+ 1)],
1446 builtin_type_double
,
1450 else if (TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
1451 && TYPE_LENGTH (valtype
) == 16
1452 && TYPE_VECTOR (valtype
))
1454 memcpy (valbuf
, regbuf
+ DEPRECATED_REGISTER_BYTE (tdep
->ppc_vr0_regnum
+ 2),
1455 TYPE_LENGTH (valtype
));
1459 /* return value is copied starting from r3. */
1460 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
1461 && TYPE_LENGTH (valtype
) < DEPRECATED_REGISTER_RAW_SIZE (3))
1462 offset
= DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype
);
1465 regbuf
+ DEPRECATED_REGISTER_BYTE (3) + offset
,
1466 TYPE_LENGTH (valtype
));
1470 /* Return whether handle_inferior_event() should proceed through code
1471 starting at PC in function NAME when stepping.
1473 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1474 handle memory references that are too distant to fit in instructions
1475 generated by the compiler. For example, if 'foo' in the following
1480 is greater than 32767, the linker might replace the lwz with a branch to
1481 somewhere in @FIX1 that does the load in 2 instructions and then branches
1482 back to where execution should continue.
1484 GDB should silently step over @FIX code, just like AIX dbx does.
1485 Unfortunately, the linker uses the "b" instruction for the branches,
1486 meaning that the link register doesn't get set. Therefore, GDB's usual
1487 step_over_function() mechanism won't work.
1489 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
1490 in handle_inferior_event() to skip past @FIX code. */
1493 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
1495 return name
&& !strncmp (name
, "@FIX", 4);
1498 /* Skip code that the user doesn't want to see when stepping:
1500 1. Indirect function calls use a piece of trampoline code to do context
1501 switching, i.e. to set the new TOC table. Skip such code if we are on
1502 its first instruction (as when we have single-stepped to here).
1504 2. Skip shared library trampoline code (which is different from
1505 indirect function call trampolines).
1507 3. Skip bigtoc fixup code.
1509 Result is desired PC to step until, or NULL if we are not in
1510 code that should be skipped. */
1513 rs6000_skip_trampoline_code (CORE_ADDR pc
)
1515 unsigned int ii
, op
;
1517 CORE_ADDR solib_target_pc
;
1518 struct minimal_symbol
*msymbol
;
1520 static unsigned trampoline_code
[] =
1522 0x800b0000, /* l r0,0x0(r11) */
1523 0x90410014, /* st r2,0x14(r1) */
1524 0x7c0903a6, /* mtctr r0 */
1525 0x804b0004, /* l r2,0x4(r11) */
1526 0x816b0008, /* l r11,0x8(r11) */
1527 0x4e800420, /* bctr */
1528 0x4e800020, /* br */
1532 /* Check for bigtoc fixup code. */
1533 msymbol
= lookup_minimal_symbol_by_pc (pc
);
1534 if (msymbol
&& rs6000_in_solib_return_trampoline (pc
, DEPRECATED_SYMBOL_NAME (msymbol
)))
1536 /* Double-check that the third instruction from PC is relative "b". */
1537 op
= read_memory_integer (pc
+ 8, 4);
1538 if ((op
& 0xfc000003) == 0x48000000)
1540 /* Extract bits 6-29 as a signed 24-bit relative word address and
1541 add it to the containing PC. */
1542 rel
= ((int)(op
<< 6) >> 6);
1543 return pc
+ 8 + rel
;
1547 /* If pc is in a shared library trampoline, return its target. */
1548 solib_target_pc
= find_solib_trampoline_target (pc
);
1549 if (solib_target_pc
)
1550 return solib_target_pc
;
1552 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
1554 op
= read_memory_integer (pc
+ (ii
* 4), 4);
1555 if (op
!= trampoline_code
[ii
])
1558 ii
= read_register (11); /* r11 holds destination addr */
1559 pc
= read_memory_addr (ii
, gdbarch_tdep (current_gdbarch
)->wordsize
); /* (r11) value */
1563 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1564 isn't available with that word size, return 0. */
1567 regsize (const struct reg
*reg
, int wordsize
)
1569 return wordsize
== 8 ? reg
->sz64
: reg
->sz32
;
1572 /* Return the name of register number N, or null if no such register exists
1573 in the current architecture. */
1576 rs6000_register_name (int n
)
1578 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1579 const struct reg
*reg
= tdep
->regs
+ n
;
1581 if (!regsize (reg
, tdep
->wordsize
))
1586 /* Index within `registers' of the first byte of the space for
1590 rs6000_register_byte (int n
)
1592 return gdbarch_tdep (current_gdbarch
)->regoff
[n
];
1595 /* Return the number of bytes of storage in the actual machine representation
1596 for register N if that register is available, else return 0. */
1599 rs6000_register_raw_size (int n
)
1601 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1602 const struct reg
*reg
= tdep
->regs
+ n
;
1603 return regsize (reg
, tdep
->wordsize
);
1606 /* Return the GDB type object for the "standard" data type
1607 of data in register N. */
1609 static struct type
*
1610 rs6000_register_virtual_type (int n
)
1612 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1613 const struct reg
*reg
= tdep
->regs
+ n
;
1616 return builtin_type_double
;
1619 int size
= regsize (reg
, tdep
->wordsize
);
1623 return builtin_type_int0
;
1625 return builtin_type_uint32
;
1627 if (tdep
->ppc_ev0_regnum
<= n
&& n
<= tdep
->ppc_ev31_regnum
)
1628 return builtin_type_vec64
;
1630 return builtin_type_uint64
;
1633 return builtin_type_vec128
;
1636 internal_error (__FILE__
, __LINE__
, "Register %d size %d unknown",
1642 /* Return whether register N requires conversion when moving from raw format
1645 The register format for RS/6000 floating point registers is always
1646 double, we need a conversion if the memory format is float. */
1649 rs6000_register_convertible (int n
)
1651 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ n
;
1655 /* Convert data from raw format for register N in buffer FROM
1656 to virtual format with type TYPE in buffer TO. */
1659 rs6000_register_convert_to_virtual (int n
, struct type
*type
,
1660 char *from
, char *to
)
1662 if (TYPE_LENGTH (type
) != DEPRECATED_REGISTER_RAW_SIZE (n
))
1664 double val
= deprecated_extract_floating (from
, DEPRECATED_REGISTER_RAW_SIZE (n
));
1665 deprecated_store_floating (to
, TYPE_LENGTH (type
), val
);
1668 memcpy (to
, from
, DEPRECATED_REGISTER_RAW_SIZE (n
));
1671 /* Convert data from virtual format with type TYPE in buffer FROM
1672 to raw format for register N in buffer TO. */
1675 rs6000_register_convert_to_raw (struct type
*type
, int n
,
1676 const char *from
, char *to
)
1678 if (TYPE_LENGTH (type
) != DEPRECATED_REGISTER_RAW_SIZE (n
))
1680 double val
= deprecated_extract_floating (from
, TYPE_LENGTH (type
));
1681 deprecated_store_floating (to
, DEPRECATED_REGISTER_RAW_SIZE (n
), val
);
1684 memcpy (to
, from
, DEPRECATED_REGISTER_RAW_SIZE (n
));
1688 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1689 int reg_nr
, void *buffer
)
1693 char temp_buffer
[MAX_REGISTER_SIZE
];
1694 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1696 if (reg_nr
>= tdep
->ppc_gp0_regnum
1697 && reg_nr
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
1699 base_regnum
= reg_nr
- tdep
->ppc_gp0_regnum
+ tdep
->ppc_ev0_regnum
;
1701 /* Build the value in the provided buffer. */
1702 /* Read the raw register of which this one is the lower portion. */
1703 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1704 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1706 memcpy ((char *) buffer
, temp_buffer
+ offset
, 4);
1711 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1712 int reg_nr
, const void *buffer
)
1716 char temp_buffer
[MAX_REGISTER_SIZE
];
1717 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1719 if (reg_nr
>= tdep
->ppc_gp0_regnum
1720 && reg_nr
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
1722 base_regnum
= reg_nr
- tdep
->ppc_gp0_regnum
+ tdep
->ppc_ev0_regnum
;
1723 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1724 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1727 /* Let's read the value of the base register into a temporary
1728 buffer, so that overwriting the last four bytes with the new
1729 value of the pseudo will leave the upper 4 bytes unchanged. */
1730 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1732 /* Write as an 8 byte quantity. */
1733 memcpy (temp_buffer
+ offset
, (char *) buffer
, 4);
1734 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1738 /* Convert a dbx stab or Dwarf 2 register number (from `r'
1739 declaration) to a gdb REGNUM. */
1741 rs6000_dwarf2_stab_reg_to_regnum (int num
)
1743 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1745 if (0 <= num
&& num
<= 31)
1746 return tdep
->ppc_gp0_regnum
+ num
;
1747 else if (32 <= num
&& num
<= 63)
1748 /* FIXME: jimb/2004-05-05: What should we do when the debug info
1749 specifies registers the architecture doesn't have? Our
1750 callers don't check the value we return. */
1751 return tdep
->ppc_fp0_regnum
+ (num
- 32);
1752 else if (1200 <= num
&& num
< 1200 + 32)
1753 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
1758 return tdep
->ppc_mq_regnum
;
1760 return tdep
->ppc_lr_regnum
;
1762 return tdep
->ppc_ctr_regnum
;
1764 return tdep
->ppc_xer_regnum
;
1766 return tdep
->ppc_vrsave_regnum
;
1771 /* FIXME: jimb/2004-03-28: Doesn't something need to be done here
1772 for the Altivec registers, too?
1774 Looking at GCC, the headers in config/rs6000 never define a
1775 DBX_REGISTER_NUMBER macro, so the debug info uses the same
1776 numbers GCC does internally. Then, looking at the REGISTER_NAMES
1777 macro defined in config/rs6000/rs6000.h, it seems that GCC gives
1778 v0 -- v31 the numbers 77 -- 108. But we number them 119 -- 150.
1780 I don't have a way to test this ready to hand, but I noticed it
1781 and thought I should include a note. */
1785 rs6000_store_return_value (struct type
*type
, char *valbuf
)
1787 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1789 /* The calling convention this function implements assumes the
1790 processor has floating-point registers. We shouldn't be using it
1791 on PPC variants that lack them. */
1792 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1794 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1796 /* Floating point values are returned starting from FPR1 and up.
1797 Say a double_double_double type could be returned in
1798 FPR1/FPR2/FPR3 triple. */
1800 deprecated_write_register_bytes
1801 (DEPRECATED_REGISTER_BYTE (tdep
->ppc_fp0_regnum
+ 1),
1803 TYPE_LENGTH (type
));
1804 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1806 if (TYPE_LENGTH (type
) == 16
1807 && TYPE_VECTOR (type
))
1808 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep
->ppc_vr0_regnum
+ 2),
1809 valbuf
, TYPE_LENGTH (type
));
1812 /* Everything else is returned in GPR3 and up. */
1813 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch
)->ppc_gp0_regnum
+ 3),
1814 valbuf
, TYPE_LENGTH (type
));
1817 /* Extract from an array REGBUF containing the (raw) register state
1818 the address in which a function should return its structure value,
1819 as a CORE_ADDR (or an expression that can be used as one). */
1822 rs6000_extract_struct_value_address (struct regcache
*regcache
)
1824 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
1825 function call GDB knows the address of the struct return value
1826 and hence, should not need to call this function. Unfortunately,
1827 the current call_function_by_hand() code only saves the most
1828 recent struct address leading to occasional calls. The code
1829 should instead maintain a stack of such addresses (in the dummy
1831 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
1832 really got no idea where the return value is being stored. While
1833 r3, on function entry, contained the address it will have since
1834 been reused (scratch) and hence wouldn't be valid */
1838 /* Hook called when a new child process is started. */
1841 rs6000_create_inferior (int pid
)
1843 if (rs6000_set_host_arch_hook
)
1844 rs6000_set_host_arch_hook (pid
);
1847 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
1849 Usually a function pointer's representation is simply the address
1850 of the function. On the RS/6000 however, a function pointer is
1851 represented by a pointer to a TOC entry. This TOC entry contains
1852 three words, the first word is the address of the function, the
1853 second word is the TOC pointer (r2), and the third word is the
1854 static chain value. Throughout GDB it is currently assumed that a
1855 function pointer contains the address of the function, which is not
1856 easy to fix. In addition, the conversion of a function address to
1857 a function pointer would require allocation of a TOC entry in the
1858 inferior's memory space, with all its drawbacks. To be able to
1859 call C++ virtual methods in the inferior (which are called via
1860 function pointers), find_function_addr uses this function to get the
1861 function address from a function pointer. */
1863 /* Return real function address if ADDR (a function pointer) is in the data
1864 space and is therefore a special function pointer. */
1867 rs6000_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
,
1869 struct target_ops
*targ
)
1871 struct obj_section
*s
;
1873 s
= find_pc_section (addr
);
1874 if (s
&& s
->the_bfd_section
->flags
& SEC_CODE
)
1877 /* ADDR is in the data space, so it's a special function pointer. */
1878 return read_memory_addr (addr
, gdbarch_tdep (current_gdbarch
)->wordsize
);
1882 /* Handling the various POWER/PowerPC variants. */
1885 /* The arrays here called registers_MUMBLE hold information about available
1888 For each family of PPC variants, I've tried to isolate out the
1889 common registers and put them up front, so that as long as you get
1890 the general family right, GDB will correctly identify the registers
1891 common to that family. The common register sets are:
1893 For the 60x family: hid0 hid1 iabr dabr pir
1895 For the 505 and 860 family: eie eid nri
1897 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
1898 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
1901 Most of these register groups aren't anything formal. I arrived at
1902 them by looking at the registers that occurred in more than one
1905 Note: kevinb/2002-04-30: Support for the fpscr register was added
1906 during April, 2002. Slot 70 is being used for PowerPC and slot 71
1907 for Power. For PowerPC, slot 70 was unused and was already in the
1908 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
1909 slot 70 was being used for "mq", so the next available slot (71)
1910 was chosen. It would have been nice to be able to make the
1911 register numbers the same across processor cores, but this wasn't
1912 possible without either 1) renumbering some registers for some
1913 processors or 2) assigning fpscr to a really high slot that's
1914 larger than any current register number. Doing (1) is bad because
1915 existing stubs would break. Doing (2) is undesirable because it
1916 would introduce a really large gap between fpscr and the rest of
1917 the registers for most processors. */
1919 /* Convenience macros for populating register arrays. */
1921 /* Within another macro, convert S to a string. */
1925 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
1926 and 64 bits on 64-bit systems. */
1927 #define R(name) { STR(name), 4, 8, 0, 0 }
1929 /* Return a struct reg defining register NAME that's 32 bits on all
1931 #define R4(name) { STR(name), 4, 4, 0, 0 }
1933 /* Return a struct reg defining register NAME that's 64 bits on all
1935 #define R8(name) { STR(name), 8, 8, 0, 0 }
1937 /* Return a struct reg defining register NAME that's 128 bits on all
1939 #define R16(name) { STR(name), 16, 16, 0, 0 }
1941 /* Return a struct reg defining floating-point register NAME. */
1942 #define F(name) { STR(name), 8, 8, 1, 0 }
1944 /* Return a struct reg defining a pseudo register NAME. */
1945 #define P(name) { STR(name), 4, 8, 0, 1}
1947 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
1948 systems and that doesn't exist on 64-bit systems. */
1949 #define R32(name) { STR(name), 4, 0, 0, 0 }
1951 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
1952 systems and that doesn't exist on 32-bit systems. */
1953 #define R64(name) { STR(name), 0, 8, 0, 0 }
1955 /* Return a struct reg placeholder for a register that doesn't exist. */
1956 #define R0 { 0, 0, 0, 0, 0 }
1958 /* UISA registers common across all architectures, including POWER. */
1960 #define COMMON_UISA_REGS \
1961 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
1962 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
1963 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
1964 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
1965 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
1966 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
1967 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
1968 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
1969 /* 64 */ R(pc), R(ps)
1971 #define COMMON_UISA_NOFP_REGS \
1972 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
1973 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
1974 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
1975 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
1976 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1977 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1978 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1979 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1980 /* 64 */ R(pc), R(ps)
1982 /* UISA-level SPRs for PowerPC. */
1983 #define PPC_UISA_SPRS \
1984 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
1986 /* UISA-level SPRs for PowerPC without floating point support. */
1987 #define PPC_UISA_NOFP_SPRS \
1988 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
1990 /* Segment registers, for PowerPC. */
1991 #define PPC_SEGMENT_REGS \
1992 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
1993 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
1994 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
1995 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
1997 /* OEA SPRs for PowerPC. */
1998 #define PPC_OEA_SPRS \
2000 /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
2001 /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
2002 /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
2003 /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
2004 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
2005 /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
2006 /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
2007 /* 116 */ R4(dec), R(dabr), R4(ear)
2009 /* AltiVec registers. */
2010 #define PPC_ALTIVEC_REGS \
2011 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2012 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2013 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2014 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2015 /*151*/R4(vscr), R4(vrsave)
2017 /* Vectors of hi-lo general purpose registers. */
2018 #define PPC_EV_REGS \
2019 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
2020 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
2021 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
2022 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
2024 /* Lower half of the EV registers. */
2025 #define PPC_GPRS_PSEUDO_REGS \
2026 /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \
2027 /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \
2028 /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \
2029 /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31)
2031 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2032 user-level SPR's. */
2033 static const struct reg registers_power
[] =
2036 /* 66 */ R4(cnd
), R(lr
), R(cnt
), R4(xer
), R4(mq
),
2040 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2041 view of the PowerPC. */
2042 static const struct reg registers_powerpc
[] =
2049 /* PowerPC UISA - a PPC processor as viewed by user-level
2050 code, but without floating point registers. */
2051 static const struct reg registers_powerpc_nofp
[] =
2053 COMMON_UISA_NOFP_REGS
,
2057 /* IBM PowerPC 403. */
2058 static const struct reg registers_403
[] =
2064 /* 119 */ R(icdbdr
), R(esr
), R(dear
), R(evpr
),
2065 /* 123 */ R(cdbcr
), R(tsr
), R(tcr
), R(pit
),
2066 /* 127 */ R(tbhi
), R(tblo
), R(srr2
), R(srr3
),
2067 /* 131 */ R(dbsr
), R(dbcr
), R(iac1
), R(iac2
),
2068 /* 135 */ R(dac1
), R(dac2
), R(dccr
), R(iccr
),
2069 /* 139 */ R(pbl1
), R(pbu1
), R(pbl2
), R(pbu2
)
2072 /* IBM PowerPC 403GC. */
2073 static const struct reg registers_403GC
[] =
2079 /* 119 */ R(icdbdr
), R(esr
), R(dear
), R(evpr
),
2080 /* 123 */ R(cdbcr
), R(tsr
), R(tcr
), R(pit
),
2081 /* 127 */ R(tbhi
), R(tblo
), R(srr2
), R(srr3
),
2082 /* 131 */ R(dbsr
), R(dbcr
), R(iac1
), R(iac2
),
2083 /* 135 */ R(dac1
), R(dac2
), R(dccr
), R(iccr
),
2084 /* 139 */ R(pbl1
), R(pbu1
), R(pbl2
), R(pbu2
),
2085 /* 143 */ R(zpr
), R(pid
), R(sgr
), R(dcwr
),
2086 /* 147 */ R(tbhu
), R(tblu
)
2089 /* Motorola PowerPC 505. */
2090 static const struct reg registers_505
[] =
2096 /* 119 */ R(eie
), R(eid
), R(nri
)
2099 /* Motorola PowerPC 860 or 850. */
2100 static const struct reg registers_860
[] =
2106 /* 119 */ R(eie
), R(eid
), R(nri
), R(cmpa
),
2107 /* 123 */ R(cmpb
), R(cmpc
), R(cmpd
), R(icr
),
2108 /* 127 */ R(der
), R(counta
), R(countb
), R(cmpe
),
2109 /* 131 */ R(cmpf
), R(cmpg
), R(cmph
), R(lctrl1
),
2110 /* 135 */ R(lctrl2
), R(ictrl
), R(bar
), R(ic_cst
),
2111 /* 139 */ R(ic_adr
), R(ic_dat
), R(dc_cst
), R(dc_adr
),
2112 /* 143 */ R(dc_dat
), R(dpdr
), R(dpir
), R(immr
),
2113 /* 147 */ R(mi_ctr
), R(mi_ap
), R(mi_epn
), R(mi_twc
),
2114 /* 151 */ R(mi_rpn
), R(md_ctr
), R(m_casid
), R(md_ap
),
2115 /* 155 */ R(md_epn
), R(md_twb
), R(md_twc
), R(md_rpn
),
2116 /* 159 */ R(m_tw
), R(mi_dbcam
), R(mi_dbram0
), R(mi_dbram1
),
2117 /* 163 */ R(md_dbcam
), R(md_dbram0
), R(md_dbram1
)
2120 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2121 for reading and writing RTCU and RTCL. However, how one reads and writes a
2122 register is the stub's problem. */
2123 static const struct reg registers_601
[] =
2129 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R(dabr
),
2130 /* 123 */ R(pir
), R(mq
), R(rtcu
), R(rtcl
)
2133 /* Motorola PowerPC 602. */
2134 static const struct reg registers_602
[] =
2140 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R0
,
2141 /* 123 */ R0
, R(tcr
), R(ibr
), R(esassr
),
2142 /* 127 */ R(sebr
), R(ser
), R(sp
), R(lt
)
2145 /* Motorola/IBM PowerPC 603 or 603e. */
2146 static const struct reg registers_603
[] =
2152 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R0
,
2153 /* 123 */ R0
, R(dmiss
), R(dcmp
), R(hash1
),
2154 /* 127 */ R(hash2
), R(imiss
), R(icmp
), R(rpa
)
2157 /* Motorola PowerPC 604 or 604e. */
2158 static const struct reg registers_604
[] =
2164 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R(dabr
),
2165 /* 123 */ R(pir
), R(mmcr0
), R(pmc1
), R(pmc2
),
2166 /* 127 */ R(sia
), R(sda
)
2169 /* Motorola/IBM PowerPC 750 or 740. */
2170 static const struct reg registers_750
[] =
2176 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R(dabr
),
2177 /* 123 */ R0
, R(ummcr0
), R(upmc1
), R(upmc2
),
2178 /* 127 */ R(usia
), R(ummcr1
), R(upmc3
), R(upmc4
),
2179 /* 131 */ R(mmcr0
), R(pmc1
), R(pmc2
), R(sia
),
2180 /* 135 */ R(mmcr1
), R(pmc3
), R(pmc4
), R(l2cr
),
2181 /* 139 */ R(ictc
), R(thrm1
), R(thrm2
), R(thrm3
)
2185 /* Motorola PowerPC 7400. */
2186 static const struct reg registers_7400
[] =
2188 /* gpr0-gpr31, fpr0-fpr31 */
2190 /* cr, lr, ctr, xer, fpscr */
2195 /* vr0-vr31, vrsave, vscr */
2197 /* FIXME? Add more registers? */
2200 /* Motorola e500. */
2201 static const struct reg registers_e500
[] =
2204 /* cr, lr, ctr, xer, "" */
2208 R8(acc
), R(spefscr
),
2209 /* NOTE: Add new registers here the end of the raw register
2210 list and just before the first pseudo register. */
2212 PPC_GPRS_PSEUDO_REGS
2215 /* Information about a particular processor variant. */
2219 /* Name of this variant. */
2222 /* English description of the variant. */
2225 /* bfd_arch_info.arch corresponding to variant. */
2226 enum bfd_architecture arch
;
2228 /* bfd_arch_info.mach corresponding to variant. */
2231 /* Number of real registers. */
2234 /* Number of pseudo registers. */
2237 /* Number of total registers (the sum of nregs and npregs). */
2240 /* Table of register names; registers[R] is the name of the register
2242 const struct reg
*regs
;
2245 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2248 num_registers (const struct reg
*reg_list
, int num_tot_regs
)
2253 for (i
= 0; i
< num_tot_regs
; i
++)
2254 if (!reg_list
[i
].pseudo
)
2261 num_pseudo_registers (const struct reg
*reg_list
, int num_tot_regs
)
2266 for (i
= 0; i
< num_tot_regs
; i
++)
2267 if (reg_list
[i
].pseudo
)
2273 /* Information in this table comes from the following web sites:
2274 IBM: http://www.chips.ibm.com:80/products/embedded/
2275 Motorola: http://www.mot.com/SPS/PowerPC/
2277 I'm sure I've got some of the variant descriptions not quite right.
2278 Please report any inaccuracies you find to GDB's maintainer.
2280 If you add entries to this table, please be sure to allow the new
2281 value as an argument to the --with-cpu flag, in configure.in. */
2283 static struct variant variants
[] =
2286 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2287 bfd_mach_ppc
, -1, -1, tot_num_registers (registers_powerpc
),
2289 {"power", "POWER user-level", bfd_arch_rs6000
,
2290 bfd_mach_rs6k
, -1, -1, tot_num_registers (registers_power
),
2292 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2293 bfd_mach_ppc_403
, -1, -1, tot_num_registers (registers_403
),
2295 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2296 bfd_mach_ppc_601
, -1, -1, tot_num_registers (registers_601
),
2298 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2299 bfd_mach_ppc_602
, -1, -1, tot_num_registers (registers_602
),
2301 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2302 bfd_mach_ppc_603
, -1, -1, tot_num_registers (registers_603
),
2304 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2305 604, -1, -1, tot_num_registers (registers_604
),
2307 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2308 bfd_mach_ppc_403gc
, -1, -1, tot_num_registers (registers_403GC
),
2310 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2311 bfd_mach_ppc_505
, -1, -1, tot_num_registers (registers_505
),
2313 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2314 bfd_mach_ppc_860
, -1, -1, tot_num_registers (registers_860
),
2316 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2317 bfd_mach_ppc_750
, -1, -1, tot_num_registers (registers_750
),
2319 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2320 bfd_mach_ppc_7400
, -1, -1, tot_num_registers (registers_7400
),
2322 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2323 bfd_mach_ppc_e500
, -1, -1, tot_num_registers (registers_e500
),
2327 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2328 bfd_mach_ppc64
, -1, -1, tot_num_registers (registers_powerpc
),
2330 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2331 bfd_mach_ppc_620
, -1, -1, tot_num_registers (registers_powerpc
),
2333 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2334 bfd_mach_ppc_630
, -1, -1, tot_num_registers (registers_powerpc
),
2336 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2337 bfd_mach_ppc_a35
, -1, -1, tot_num_registers (registers_powerpc
),
2339 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2340 bfd_mach_ppc_rs64ii
, -1, -1, tot_num_registers (registers_powerpc
),
2342 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2343 bfd_mach_ppc_rs64iii
, -1, -1, tot_num_registers (registers_powerpc
),
2346 /* FIXME: I haven't checked the register sets of the following. */
2347 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2348 bfd_mach_rs6k_rs1
, -1, -1, tot_num_registers (registers_power
),
2350 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2351 bfd_mach_rs6k_rsc
, -1, -1, tot_num_registers (registers_power
),
2353 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2354 bfd_mach_rs6k_rs2
, -1, -1, tot_num_registers (registers_power
),
2357 {0, 0, 0, 0, 0, 0, 0, 0}
2360 /* Initialize the number of registers and pseudo registers in each variant. */
2363 init_variants (void)
2367 for (v
= variants
; v
->name
; v
++)
2370 v
->nregs
= num_registers (v
->regs
, v
->num_tot_regs
);
2371 if (v
->npregs
== -1)
2372 v
->npregs
= num_pseudo_registers (v
->regs
, v
->num_tot_regs
);
2376 /* Return the variant corresponding to architecture ARCH and machine number
2377 MACH. If no such variant exists, return null. */
2379 static const struct variant
*
2380 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
2382 const struct variant
*v
;
2384 for (v
= variants
; v
->name
; v
++)
2385 if (arch
== v
->arch
&& mach
== v
->mach
)
2392 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
2394 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2395 return print_insn_big_powerpc (memaddr
, info
);
2397 return print_insn_little_powerpc (memaddr
, info
);
2401 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2403 return frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
2406 static struct frame_id
2407 rs6000_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2409 return frame_id_build (frame_unwind_register_unsigned (next_frame
,
2411 frame_pc_unwind (next_frame
));
2414 struct rs6000_frame_cache
2417 CORE_ADDR initial_sp
;
2418 struct trad_frame_saved_reg
*saved_regs
;
2421 static struct rs6000_frame_cache
*
2422 rs6000_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2424 struct rs6000_frame_cache
*cache
;
2425 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2426 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2427 struct rs6000_framedata fdata
;
2428 int wordsize
= tdep
->wordsize
;
2430 if ((*this_cache
) != NULL
)
2431 return (*this_cache
);
2432 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
2433 (*this_cache
) = cache
;
2434 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2436 skip_prologue (frame_func_unwind (next_frame
), frame_pc_unwind (next_frame
),
2439 /* If there were any saved registers, figure out parent's stack
2441 /* The following is true only if the frame doesn't have a call to
2444 if (fdata
.saved_fpr
== 0
2445 && fdata
.saved_gpr
== 0
2446 && fdata
.saved_vr
== 0
2447 && fdata
.saved_ev
== 0
2448 && fdata
.lr_offset
== 0
2449 && fdata
.cr_offset
== 0
2450 && fdata
.vr_offset
== 0
2451 && fdata
.ev_offset
== 0)
2452 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2455 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2456 address of the current frame. Things might be easier if the
2457 ->frame pointed to the outer-most address of the frame. In
2458 the mean time, the address of the prev frame is used as the
2459 base address of this frame. */
2460 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2461 if (!fdata
.frameless
)
2462 /* Frameless really means stackless. */
2463 cache
->base
= read_memory_addr (cache
->base
, wordsize
);
2465 trad_frame_set_value (cache
->saved_regs
, SP_REGNUM
, cache
->base
);
2467 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2468 All fpr's from saved_fpr to fp31 are saved. */
2470 if (fdata
.saved_fpr
>= 0)
2473 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
2475 /* If skip_prologue says floating-point registers were saved,
2476 but the current architecture has no floating-point registers,
2477 then that's strange. But we have no indices to even record
2478 the addresses under, so we just ignore it. */
2479 if (ppc_floating_point_unit_p (gdbarch
))
2480 for (i
= fdata
.saved_fpr
; i
< 32; i
++)
2482 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
2487 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2488 All gpr's from saved_gpr to gpr31 are saved. */
2490 if (fdata
.saved_gpr
>= 0)
2493 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
2494 for (i
= fdata
.saved_gpr
; i
< 32; i
++)
2496 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
2497 gpr_addr
+= wordsize
;
2501 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2502 All vr's from saved_vr to vr31 are saved. */
2503 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
2505 if (fdata
.saved_vr
>= 0)
2508 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
2509 for (i
= fdata
.saved_vr
; i
< 32; i
++)
2511 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
2512 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
2517 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2518 All vr's from saved_ev to ev31 are saved. ????? */
2519 if (tdep
->ppc_ev0_regnum
!= -1 && tdep
->ppc_ev31_regnum
!= -1)
2521 if (fdata
.saved_ev
>= 0)
2524 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
2525 for (i
= fdata
.saved_ev
; i
< 32; i
++)
2527 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
2528 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
2529 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
2534 /* If != 0, fdata.cr_offset is the offset from the frame that
2536 if (fdata
.cr_offset
!= 0)
2537 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
2539 /* If != 0, fdata.lr_offset is the offset from the frame that
2541 if (fdata
.lr_offset
!= 0)
2542 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
2543 /* The PC is found in the link register. */
2544 cache
->saved_regs
[PC_REGNUM
] = cache
->saved_regs
[tdep
->ppc_lr_regnum
];
2546 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2547 holds the VRSAVE. */
2548 if (fdata
.vrsave_offset
!= 0)
2549 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
2551 if (fdata
.alloca_reg
< 0)
2552 /* If no alloca register used, then fi->frame is the value of the
2553 %sp for this frame, and it is good enough. */
2554 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2556 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
,
2563 rs6000_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2564 struct frame_id
*this_id
)
2566 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2568 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2572 rs6000_frame_prev_register (struct frame_info
*next_frame
,
2574 int regnum
, int *optimizedp
,
2575 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2576 int *realnump
, void *valuep
)
2578 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2580 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
2581 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2584 static const struct frame_unwind rs6000_frame_unwind
=
2587 rs6000_frame_this_id
,
2588 rs6000_frame_prev_register
2591 static const struct frame_unwind
*
2592 rs6000_frame_sniffer (struct frame_info
*next_frame
)
2594 return &rs6000_frame_unwind
;
2600 rs6000_frame_base_address (struct frame_info
*next_frame
,
2603 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2605 return info
->initial_sp
;
2608 static const struct frame_base rs6000_frame_base
= {
2609 &rs6000_frame_unwind
,
2610 rs6000_frame_base_address
,
2611 rs6000_frame_base_address
,
2612 rs6000_frame_base_address
2615 static const struct frame_base
*
2616 rs6000_frame_base_sniffer (struct frame_info
*next_frame
)
2618 return &rs6000_frame_base
;
2621 /* Initialize the current architecture based on INFO. If possible, re-use an
2622 architecture from ARCHES, which is a list of architectures already created
2623 during this debugging session.
2625 Called e.g. at program startup, when reading a core file, and when reading
2628 static struct gdbarch
*
2629 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2631 struct gdbarch
*gdbarch
;
2632 struct gdbarch_tdep
*tdep
;
2633 int wordsize
, from_xcoff_exec
, from_elf_exec
, power
, i
, off
;
2635 const struct variant
*v
;
2636 enum bfd_architecture arch
;
2642 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2643 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
2645 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2646 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2648 sysv_abi
= info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2650 /* Check word size. If INFO is from a binary file, infer it from
2651 that, else choose a likely default. */
2652 if (from_xcoff_exec
)
2654 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
2659 else if (from_elf_exec
)
2661 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
2668 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
2669 wordsize
= info
.bfd_arch_info
->bits_per_word
/
2670 info
.bfd_arch_info
->bits_per_byte
;
2675 /* Find a candidate among extant architectures. */
2676 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2678 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2680 /* Word size in the various PowerPC bfd_arch_info structs isn't
2681 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
2682 separate word size check. */
2683 tdep
= gdbarch_tdep (arches
->gdbarch
);
2684 if (tdep
&& tdep
->wordsize
== wordsize
)
2685 return arches
->gdbarch
;
2688 /* None found, create a new architecture from INFO, whose bfd_arch_info
2689 validity depends on the source:
2690 - executable useless
2691 - rs6000_host_arch() good
2693 - "set arch" trust blindly
2694 - GDB startup useless but harmless */
2696 if (!from_xcoff_exec
)
2698 arch
= info
.bfd_arch_info
->arch
;
2699 mach
= info
.bfd_arch_info
->mach
;
2703 arch
= bfd_arch_powerpc
;
2704 bfd_default_set_arch_mach (&abfd
, arch
, 0);
2705 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2706 mach
= info
.bfd_arch_info
->mach
;
2708 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2709 tdep
->wordsize
= wordsize
;
2711 /* For e500 executables, the apuinfo section is of help here. Such
2712 section contains the identifier and revision number of each
2713 Application-specific Processing Unit that is present on the
2714 chip. The content of the section is determined by the assembler
2715 which looks at each instruction and determines which unit (and
2716 which version of it) can execute it. In our case we just look for
2717 the existance of the section. */
2721 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
2724 arch
= info
.bfd_arch_info
->arch
;
2725 mach
= bfd_mach_ppc_e500
;
2726 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
2727 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2731 gdbarch
= gdbarch_alloc (&info
, tdep
);
2732 power
= arch
== bfd_arch_rs6000
;
2734 /* Initialize the number of real and pseudo registers in each variant. */
2737 /* Choose variant. */
2738 v
= find_variant_by_arch (arch
, mach
);
2742 tdep
->regs
= v
->regs
;
2744 tdep
->ppc_gp0_regnum
= 0;
2745 tdep
->ppc_toc_regnum
= 2;
2746 tdep
->ppc_ps_regnum
= 65;
2747 tdep
->ppc_cr_regnum
= 66;
2748 tdep
->ppc_lr_regnum
= 67;
2749 tdep
->ppc_ctr_regnum
= 68;
2750 tdep
->ppc_xer_regnum
= 69;
2751 if (v
->mach
== bfd_mach_ppc_601
)
2752 tdep
->ppc_mq_regnum
= 124;
2754 tdep
->ppc_mq_regnum
= 70;
2756 tdep
->ppc_mq_regnum
= -1;
2757 tdep
->ppc_fp0_regnum
= 32;
2758 tdep
->ppc_fpscr_regnum
= power
? 71 : 70;
2760 set_gdbarch_pc_regnum (gdbarch
, 64);
2761 set_gdbarch_sp_regnum (gdbarch
, 1);
2762 set_gdbarch_deprecated_fp_regnum (gdbarch
, 1);
2763 if (sysv_abi
&& wordsize
== 8)
2764 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
2765 else if (sysv_abi
&& wordsize
== 4)
2766 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
2769 set_gdbarch_deprecated_extract_return_value (gdbarch
, rs6000_extract_return_value
);
2770 set_gdbarch_deprecated_store_return_value (gdbarch
, rs6000_store_return_value
);
2773 if (v
->arch
== bfd_arch_powerpc
)
2777 tdep
->ppc_vr0_regnum
= 71;
2778 tdep
->ppc_vrsave_regnum
= 104;
2779 tdep
->ppc_ev0_regnum
= -1;
2780 tdep
->ppc_ev31_regnum
= -1;
2782 case bfd_mach_ppc_7400
:
2783 tdep
->ppc_vr0_regnum
= 119;
2784 tdep
->ppc_vrsave_regnum
= 152;
2785 tdep
->ppc_ev0_regnum
= -1;
2786 tdep
->ppc_ev31_regnum
= -1;
2788 case bfd_mach_ppc_e500
:
2789 tdep
->ppc_gp0_regnum
= 41;
2790 tdep
->ppc_toc_regnum
= -1;
2791 tdep
->ppc_ps_regnum
= 1;
2792 tdep
->ppc_cr_regnum
= 2;
2793 tdep
->ppc_lr_regnum
= 3;
2794 tdep
->ppc_ctr_regnum
= 4;
2795 tdep
->ppc_xer_regnum
= 5;
2796 tdep
->ppc_ev0_regnum
= 7;
2797 tdep
->ppc_ev31_regnum
= 38;
2798 tdep
->ppc_fp0_regnum
= -1;
2799 tdep
->ppc_fpscr_regnum
= -1;
2800 set_gdbarch_pc_regnum (gdbarch
, 0);
2801 set_gdbarch_sp_regnum (gdbarch
, tdep
->ppc_gp0_regnum
+ 1);
2802 set_gdbarch_deprecated_fp_regnum (gdbarch
, tdep
->ppc_gp0_regnum
+ 1);
2803 set_gdbarch_pseudo_register_read (gdbarch
, e500_pseudo_register_read
);
2804 set_gdbarch_pseudo_register_write (gdbarch
, e500_pseudo_register_write
);
2807 tdep
->ppc_vr0_regnum
= -1;
2808 tdep
->ppc_vrsave_regnum
= -1;
2809 tdep
->ppc_ev0_regnum
= -1;
2810 tdep
->ppc_ev31_regnum
= -1;
2814 /* Sanity check on registers. */
2815 gdb_assert (strcmp (tdep
->regs
[tdep
->ppc_gp0_regnum
].name
, "r0") == 0);
2817 /* Set lr_frame_offset. */
2819 tdep
->lr_frame_offset
= 16;
2821 tdep
->lr_frame_offset
= 4;
2823 tdep
->lr_frame_offset
= 8;
2825 /* Calculate byte offsets in raw register array. */
2826 tdep
->regoff
= xmalloc (v
->num_tot_regs
* sizeof (int));
2827 for (i
= off
= 0; i
< v
->num_tot_regs
; i
++)
2829 tdep
->regoff
[i
] = off
;
2830 off
+= regsize (v
->regs
+ i
, wordsize
);
2833 /* Select instruction printer. */
2835 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
2837 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
2839 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
2841 set_gdbarch_num_regs (gdbarch
, v
->nregs
);
2842 set_gdbarch_num_pseudo_regs (gdbarch
, v
->npregs
);
2843 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
2844 set_gdbarch_deprecated_register_size (gdbarch
, wordsize
);
2845 set_gdbarch_deprecated_register_bytes (gdbarch
, off
);
2846 set_gdbarch_deprecated_register_byte (gdbarch
, rs6000_register_byte
);
2847 set_gdbarch_deprecated_register_raw_size (gdbarch
, rs6000_register_raw_size
);
2848 set_gdbarch_deprecated_register_virtual_type (gdbarch
, rs6000_register_virtual_type
);
2850 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
2851 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2852 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2853 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
2854 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2855 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2856 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2858 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
2860 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2861 set_gdbarch_char_signed (gdbarch
, 0);
2863 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
2864 if (sysv_abi
&& wordsize
== 8)
2866 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
2867 else if (!sysv_abi
&& wordsize
== 4)
2868 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
2869 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
2870 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
2872 set_gdbarch_frame_red_zone_size (gdbarch
, 224);
2874 set_gdbarch_deprecated_register_convertible (gdbarch
, rs6000_register_convertible
);
2875 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch
, rs6000_register_convert_to_virtual
);
2876 set_gdbarch_deprecated_register_convert_to_raw (gdbarch
, rs6000_register_convert_to_raw
);
2877 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_dwarf2_stab_reg_to_regnum
);
2878 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_stab_reg_to_regnum
);
2879 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
2880 is correct for the SysV ABI when the wordsize is 8, but I'm also
2881 fairly certain that ppc_sysv_abi_push_arguments() will give even
2882 worse results since it only works for 32-bit code. So, for the moment,
2883 we're better off calling rs6000_push_arguments() since it works for
2884 64-bit code. At some point in the future, this matter needs to be
2886 if (sysv_abi
&& wordsize
== 4)
2887 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
2888 else if (sysv_abi
&& wordsize
== 8)
2889 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
2891 set_gdbarch_push_dummy_call (gdbarch
, rs6000_push_dummy_call
);
2893 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, rs6000_extract_struct_value_address
);
2895 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
2896 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2897 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
2899 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
2900 for the descriptor and ".FN" for the entry-point -- a user
2901 specifying "break FN" will unexpectedly end up with a breakpoint
2902 on the descriptor and not the function. This architecture method
2903 transforms any breakpoints on descriptors into breakpoints on the
2904 corresponding entry point. */
2905 if (sysv_abi
&& wordsize
== 8)
2906 set_gdbarch_adjust_breakpoint_address (gdbarch
, ppc64_sysv_abi_adjust_breakpoint_address
);
2908 /* Not sure on this. FIXMEmgo */
2909 set_gdbarch_frame_args_skip (gdbarch
, 8);
2912 set_gdbarch_use_struct_convention (gdbarch
,
2913 rs6000_use_struct_convention
);
2917 /* Handle RS/6000 function pointers (which are really function
2919 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
2920 rs6000_convert_from_func_ptr_addr
);
2923 /* Helpers for function argument information. */
2924 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
2926 /* Hook in ABI-specific overrides, if they have been registered. */
2927 gdbarch_init_osabi (info
, gdbarch
);
2931 case GDB_OSABI_NETBSD_AOUT
:
2932 case GDB_OSABI_NETBSD_ELF
:
2933 case GDB_OSABI_UNKNOWN
:
2934 case GDB_OSABI_LINUX
:
2935 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
2936 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
2937 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
2938 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
2941 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2943 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
2944 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
2945 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
2946 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
2949 if (from_xcoff_exec
)
2951 /* NOTE: jimix/2003-06-09: This test should really check for
2952 GDB_OSABI_AIX when that is defined and becomes
2953 available. (Actually, once things are properly split apart,
2954 the test goes away.) */
2955 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
2956 set_gdbarch_software_single_step (gdbarch
, rs6000_software_single_step
);
2963 rs6000_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2965 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2970 /* FIXME: Dump gdbarch_tdep. */
2973 static struct cmd_list_element
*info_powerpc_cmdlist
= NULL
;
2976 rs6000_info_powerpc_command (char *args
, int from_tty
)
2978 help_list (info_powerpc_cmdlist
, "info powerpc ", class_info
, gdb_stdout
);
2981 /* Initialization code. */
2983 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
2986 _initialize_rs6000_tdep (void)
2988 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
2989 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
2991 /* Add root prefix command for "info powerpc" commands */
2992 add_prefix_cmd ("powerpc", class_info
, rs6000_info_powerpc_command
,
2993 "Various POWERPC info specific commands.",
2994 &info_powerpc_cmdlist
, "info powerpc ", 0, &infolist
);