1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* The list of available "set powerpc ..." and "show powerpc ..."
111 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
112 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
114 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
116 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
117 static const char *const powerpc_vector_strings
[] =
126 /* A variable that can be configured by the user. */
127 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
128 static const char *powerpc_vector_abi_string
= "auto";
130 /* To be used by skip_prologue. */
132 struct rs6000_framedata
134 int offset
; /* total size of frame --- the distance
135 by which we decrement sp to allocate
137 int saved_gpr
; /* smallest # of saved gpr */
138 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
139 int saved_fpr
; /* smallest # of saved fpr */
140 int saved_vr
; /* smallest # of saved vr */
141 int saved_ev
; /* smallest # of saved ev */
142 int alloca_reg
; /* alloca register number (frame ptr) */
143 char frameless
; /* true if frameless functions. */
144 char nosavedpc
; /* true if pc not saved. */
145 char used_bl
; /* true if link register clobbered */
146 int gpr_offset
; /* offset of saved gprs from prev sp */
147 int fpr_offset
; /* offset of saved fprs from prev sp */
148 int vr_offset
; /* offset of saved vrs from prev sp */
149 int ev_offset
; /* offset of saved evs from prev sp */
150 int lr_offset
; /* offset of saved lr */
151 int lr_register
; /* register of saved lr, if trustworthy */
152 int cr_offset
; /* offset of saved cr */
153 int vrsave_offset
; /* offset of saved vrsave register */
157 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
159 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
161 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
162 if (tdep
->ppc_vsr0_regnum
< 0)
165 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
166 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
169 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
171 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
173 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
174 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
177 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
181 /* Return true if REGNO is an SPE register, false otherwise. */
183 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
185 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 /* Is it a reference to EV0 -- EV31, and do we have those? */
188 if (IS_SPE_PSEUDOREG (tdep
, regno
))
191 /* Is it a reference to one of the raw upper GPR halves? */
192 if (tdep
->ppc_ev0_upper_regnum
>= 0
193 && tdep
->ppc_ev0_upper_regnum
<= regno
194 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
197 /* Is it a reference to the 64-bit accumulator, and do we have that? */
198 if (tdep
->ppc_acc_regnum
>= 0
199 && tdep
->ppc_acc_regnum
== regno
)
202 /* Is it a reference to the SPE floating-point status and control register,
203 and do we have that? */
204 if (tdep
->ppc_spefscr_regnum
>= 0
205 && tdep
->ppc_spefscr_regnum
== regno
)
212 /* Return non-zero if the architecture described by GDBARCH has
213 floating-point registers (f0 --- f31 and fpscr). */
215 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
217 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
219 return (tdep
->ppc_fp0_regnum
>= 0
220 && tdep
->ppc_fpscr_regnum
>= 0);
223 /* Return non-zero if the architecture described by GDBARCH has
224 VSX registers (vsr0 --- vsr63). */
226 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
230 return tdep
->ppc_vsr0_regnum
>= 0;
233 /* Return non-zero if the architecture described by GDBARCH has
234 Altivec registers (vr0 --- vr31, vrsave and vscr). */
236 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
238 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
240 return (tdep
->ppc_vr0_regnum
>= 0
241 && tdep
->ppc_vrsave_regnum
>= 0);
244 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
247 This is a helper function for init_sim_regno_table, constructing
248 the table mapping GDB register numbers to sim register numbers; we
249 initialize every element in that table to -1 before we start
252 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
254 /* Make sure we don't try to assign any given GDB register a sim
255 register number more than once. */
256 gdb_assert (table
[gdb_regno
] == -1);
257 table
[gdb_regno
] = sim_regno
;
261 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
262 numbers to simulator register numbers, based on the values placed
263 in the ARCH->tdep->ppc_foo_regnum members. */
265 init_sim_regno_table (struct gdbarch
*arch
)
267 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
268 int total_regs
= gdbarch_num_regs (arch
);
269 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
271 static const char *const segment_regs
[] = {
272 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
273 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
276 /* Presume that all registers not explicitly mentioned below are
277 unavailable from the sim. */
278 for (i
= 0; i
< total_regs
; i
++)
281 /* General-purpose registers. */
282 for (i
= 0; i
< ppc_num_gprs
; i
++)
283 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
285 /* Floating-point registers. */
286 if (tdep
->ppc_fp0_regnum
>= 0)
287 for (i
= 0; i
< ppc_num_fprs
; i
++)
288 set_sim_regno (sim_regno
,
289 tdep
->ppc_fp0_regnum
+ i
,
290 sim_ppc_f0_regnum
+ i
);
291 if (tdep
->ppc_fpscr_regnum
>= 0)
292 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
294 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
295 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
296 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
298 /* Segment registers. */
299 for (i
= 0; i
< ppc_num_srs
; i
++)
303 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
305 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
308 /* Altivec registers. */
309 if (tdep
->ppc_vr0_regnum
>= 0)
311 for (i
= 0; i
< ppc_num_vrs
; i
++)
312 set_sim_regno (sim_regno
,
313 tdep
->ppc_vr0_regnum
+ i
,
314 sim_ppc_vr0_regnum
+ i
);
316 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
317 we can treat this more like the other cases. */
318 set_sim_regno (sim_regno
,
319 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
320 sim_ppc_vscr_regnum
);
322 /* vsave is a special-purpose register, so the code below handles it. */
324 /* SPE APU (E500) registers. */
325 if (tdep
->ppc_ev0_upper_regnum
>= 0)
326 for (i
= 0; i
< ppc_num_gprs
; i
++)
327 set_sim_regno (sim_regno
,
328 tdep
->ppc_ev0_upper_regnum
+ i
,
329 sim_ppc_rh0_regnum
+ i
);
330 if (tdep
->ppc_acc_regnum
>= 0)
331 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
332 /* spefscr is a special-purpose register, so the code below handles it. */
335 /* Now handle all special-purpose registers. Verify that they
336 haven't mistakenly been assigned numbers by any of the above
338 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
340 const char *spr_name
= sim_spr_register_name (i
);
343 if (spr_name
!= NULL
)
344 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
347 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
351 /* Drop the initialized array into place. */
352 tdep
->sim_regno
= sim_regno
;
356 /* Given a GDB register number REG, return the corresponding SIM
359 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
361 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
364 if (tdep
->sim_regno
== NULL
)
365 init_sim_regno_table (gdbarch
);
368 && reg
<= gdbarch_num_regs (gdbarch
)
369 + gdbarch_num_pseudo_regs (gdbarch
));
370 sim_regno
= tdep
->sim_regno
[reg
];
375 return LEGACY_SIM_REGNO_IGNORE
;
380 /* Register set support functions. */
382 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
383 Write the register to REGCACHE. */
386 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
387 const gdb_byte
*regs
, size_t offset
, int regsize
)
389 if (regnum
!= -1 && offset
!= -1)
393 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
394 int gdb_regsize
= register_size (gdbarch
, regnum
);
395 if (gdb_regsize
< regsize
396 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
397 offset
+= regsize
- gdb_regsize
;
399 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
403 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
404 in a field REGSIZE wide. Zero pad as necessary. */
407 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
408 gdb_byte
*regs
, size_t offset
, int regsize
)
410 if (regnum
!= -1 && offset
!= -1)
414 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
415 int gdb_regsize
= register_size (gdbarch
, regnum
);
416 if (gdb_regsize
< regsize
)
418 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
420 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
421 offset
+= regsize
- gdb_regsize
;
424 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
425 regsize
- gdb_regsize
);
428 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
433 ppc_greg_offset (struct gdbarch
*gdbarch
,
434 struct gdbarch_tdep
*tdep
,
435 const struct ppc_reg_offsets
*offsets
,
439 *regsize
= offsets
->gpr_size
;
440 if (regnum
>= tdep
->ppc_gp0_regnum
441 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
442 return (offsets
->r0_offset
443 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
445 if (regnum
== gdbarch_pc_regnum (gdbarch
))
446 return offsets
->pc_offset
;
448 if (regnum
== tdep
->ppc_ps_regnum
)
449 return offsets
->ps_offset
;
451 if (regnum
== tdep
->ppc_lr_regnum
)
452 return offsets
->lr_offset
;
454 if (regnum
== tdep
->ppc_ctr_regnum
)
455 return offsets
->ctr_offset
;
457 *regsize
= offsets
->xr_size
;
458 if (regnum
== tdep
->ppc_cr_regnum
)
459 return offsets
->cr_offset
;
461 if (regnum
== tdep
->ppc_xer_regnum
)
462 return offsets
->xer_offset
;
464 if (regnum
== tdep
->ppc_mq_regnum
)
465 return offsets
->mq_offset
;
471 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
472 const struct ppc_reg_offsets
*offsets
,
475 if (regnum
>= tdep
->ppc_fp0_regnum
476 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
477 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
479 if (regnum
== tdep
->ppc_fpscr_regnum
)
480 return offsets
->fpscr_offset
;
486 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
487 const struct ppc_reg_offsets
*offsets
,
490 if (regnum
>= tdep
->ppc_vr0_regnum
491 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
492 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
494 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
495 return offsets
->vscr_offset
;
497 if (regnum
== tdep
->ppc_vrsave_regnum
)
498 return offsets
->vrsave_offset
;
503 /* Supply register REGNUM in the general-purpose register set REGSET
504 from the buffer specified by GREGS and LEN to register cache
505 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
508 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
509 int regnum
, const void *gregs
, size_t len
)
511 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
513 const struct ppc_reg_offsets
*offsets
514 = (const struct ppc_reg_offsets
*) regset
->regmap
;
521 int gpr_size
= offsets
->gpr_size
;
523 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
524 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
525 i
++, offset
+= gpr_size
)
526 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
529 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
530 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
531 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
532 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
533 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
534 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
535 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
536 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
537 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
538 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
540 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
541 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
543 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
544 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
549 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
550 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
553 /* Supply register REGNUM in the floating-point register set REGSET
554 from the buffer specified by FPREGS and LEN to register cache
555 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
558 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
559 int regnum
, const void *fpregs
, size_t len
)
561 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
562 struct gdbarch_tdep
*tdep
;
563 const struct ppc_reg_offsets
*offsets
;
566 if (!ppc_floating_point_unit_p (gdbarch
))
569 tdep
= gdbarch_tdep (gdbarch
);
570 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
575 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
576 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
578 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
580 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
581 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
582 offsets
->fpscr_size
);
586 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
587 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
588 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
591 /* Supply register REGNUM in the VSX register set REGSET
592 from the buffer specified by VSXREGS and LEN to register cache
593 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
596 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
597 int regnum
, const void *vsxregs
, size_t len
)
599 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
600 struct gdbarch_tdep
*tdep
;
602 if (!ppc_vsx_support_p (gdbarch
))
605 tdep
= gdbarch_tdep (gdbarch
);
611 for (i
= tdep
->ppc_vsr0_upper_regnum
;
612 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
614 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vsxregs
, 0, 8);
619 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vsxregs
, 0, 8);
622 /* Supply register REGNUM in the Altivec register set REGSET
623 from the buffer specified by VRREGS and LEN to register cache
624 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
627 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
628 int regnum
, const void *vrregs
, size_t len
)
630 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
631 struct gdbarch_tdep
*tdep
;
632 const struct ppc_reg_offsets
*offsets
;
635 if (!ppc_altivec_support_p (gdbarch
))
638 tdep
= gdbarch_tdep (gdbarch
);
639 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
644 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
645 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
647 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vrregs
, offset
, 16);
649 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
650 (const gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
652 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
653 (const gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
657 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
658 if (regnum
!= tdep
->ppc_vrsave_regnum
659 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
660 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vrregs
, offset
, 16);
662 ppc_supply_reg (regcache
, regnum
,
663 (const gdb_byte
*) vrregs
, offset
, 4);
666 /* Collect register REGNUM in the general-purpose register set
667 REGSET from register cache REGCACHE into the buffer specified by
668 GREGS and LEN. If REGNUM is -1, do this for all registers in
672 ppc_collect_gregset (const struct regset
*regset
,
673 const struct regcache
*regcache
,
674 int regnum
, void *gregs
, size_t len
)
676 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
677 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
678 const struct ppc_reg_offsets
*offsets
679 = (const struct ppc_reg_offsets
*) regset
->regmap
;
686 int gpr_size
= offsets
->gpr_size
;
688 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
689 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
690 i
++, offset
+= gpr_size
)
691 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
693 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
694 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
695 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
696 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
697 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
698 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
699 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
700 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
701 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
702 (gdb_byte
*) gregs
, offsets
->cr_offset
,
704 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
705 (gdb_byte
*) gregs
, offsets
->xer_offset
,
707 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
708 (gdb_byte
*) gregs
, offsets
->mq_offset
,
713 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
714 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
717 /* Collect register REGNUM in the floating-point register set
718 REGSET from register cache REGCACHE into the buffer specified by
719 FPREGS and LEN. If REGNUM is -1, do this for all registers in
723 ppc_collect_fpregset (const struct regset
*regset
,
724 const struct regcache
*regcache
,
725 int regnum
, void *fpregs
, size_t len
)
727 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
728 struct gdbarch_tdep
*tdep
;
729 const struct ppc_reg_offsets
*offsets
;
732 if (!ppc_floating_point_unit_p (gdbarch
))
735 tdep
= gdbarch_tdep (gdbarch
);
736 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
741 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
742 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
744 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
746 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
747 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
748 offsets
->fpscr_size
);
752 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
753 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
754 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
757 /* Collect register REGNUM in the VSX register set
758 REGSET from register cache REGCACHE into the buffer specified by
759 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
763 ppc_collect_vsxregset (const struct regset
*regset
,
764 const struct regcache
*regcache
,
765 int regnum
, void *vsxregs
, size_t len
)
767 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
768 struct gdbarch_tdep
*tdep
;
770 if (!ppc_vsx_support_p (gdbarch
))
773 tdep
= gdbarch_tdep (gdbarch
);
779 for (i
= tdep
->ppc_vsr0_upper_regnum
;
780 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
782 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vsxregs
, 0, 8);
787 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vsxregs
, 0, 8);
791 /* Collect register REGNUM in the Altivec register set
792 REGSET from register cache REGCACHE into the buffer specified by
793 VRREGS and LEN. If REGNUM is -1, do this for all registers in
797 ppc_collect_vrregset (const struct regset
*regset
,
798 const struct regcache
*regcache
,
799 int regnum
, void *vrregs
, size_t len
)
801 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
802 struct gdbarch_tdep
*tdep
;
803 const struct ppc_reg_offsets
*offsets
;
806 if (!ppc_altivec_support_p (gdbarch
))
809 tdep
= gdbarch_tdep (gdbarch
);
810 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
815 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
816 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
818 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vrregs
, offset
, 16);
820 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
821 (gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
823 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
824 (gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
828 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
829 if (regnum
!= tdep
->ppc_vrsave_regnum
830 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
831 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vrregs
, offset
, 16);
833 ppc_collect_reg (regcache
, regnum
,
834 (gdb_byte
*) vrregs
, offset
, 4);
839 insn_changes_sp_or_jumps (unsigned long insn
)
841 int opcode
= (insn
>> 26) & 0x03f;
842 int sd
= (insn
>> 21) & 0x01f;
843 int a
= (insn
>> 16) & 0x01f;
844 int subcode
= (insn
>> 1) & 0x3ff;
846 /* Changes the stack pointer. */
848 /* NOTE: There are many ways to change the value of a given register.
849 The ways below are those used when the register is R1, the SP,
850 in a funtion's epilogue. */
852 if (opcode
== 31 && subcode
== 444 && a
== 1)
853 return 1; /* mr R1,Rn */
854 if (opcode
== 14 && sd
== 1)
855 return 1; /* addi R1,Rn,simm */
856 if (opcode
== 58 && sd
== 1)
857 return 1; /* ld R1,ds(Rn) */
859 /* Transfers control. */
865 if (opcode
== 19 && subcode
== 16)
867 if (opcode
== 19 && subcode
== 528)
868 return 1; /* bcctr */
873 /* Return true if we are in the function's epilogue, i.e. after the
874 instruction that destroyed the function's stack frame.
876 1) scan forward from the point of execution:
877 a) If you find an instruction that modifies the stack pointer
878 or transfers control (except a return), execution is not in
880 b) Stop scanning if you find a return instruction or reach the
881 end of the function or reach the hard limit for the size of
883 2) scan backward from the point of execution:
884 a) If you find an instruction that modifies the stack pointer,
885 execution *is* in an epilogue, return.
886 b) Stop scanning if you reach an instruction that transfers
887 control or the beginning of the function or reach the hard
888 limit for the size of an epilogue. */
891 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
892 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
894 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
895 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
896 bfd_byte insn_buf
[PPC_INSN_SIZE
];
897 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
900 /* Find the search limits based on function boundaries and hard limit. */
902 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
905 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
906 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
908 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
909 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
911 /* Scan forward until next 'blr'. */
913 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
915 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
917 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
918 if (insn
== 0x4e800020)
920 /* Assume a bctr is a tail call unless it points strictly within
922 if (insn
== 0x4e800420)
924 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
925 tdep
->ppc_ctr_regnum
);
926 if (ctr
> func_start
&& ctr
< func_end
)
931 if (insn_changes_sp_or_jumps (insn
))
935 /* Scan backward until adjustment to stack pointer (R1). */
937 for (scan_pc
= pc
- PPC_INSN_SIZE
;
938 scan_pc
>= epilogue_start
;
939 scan_pc
-= PPC_INSN_SIZE
)
941 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
943 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
944 if (insn_changes_sp_or_jumps (insn
))
951 /* Implement the stack_frame_destroyed_p gdbarch method. */
954 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
956 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
960 /* Get the ith function argument for the current function. */
962 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
965 return get_frame_register_unsigned (frame
, 3 + argi
);
968 /* Sequence of bytes for breakpoint instruction. */
970 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
971 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
973 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
976 /* Instruction masks for displaced stepping. */
977 #define BRANCH_MASK 0xfc000000
978 #define BP_MASK 0xFC0007FE
979 #define B_INSN 0x48000000
980 #define BC_INSN 0x40000000
981 #define BXL_INSN 0x4c000000
982 #define BP_INSN 0x7C000008
984 /* Instruction masks used during single-stepping of atomic
986 #define LWARX_MASK 0xfc0007fe
987 #define LWARX_INSTRUCTION 0x7c000028
988 #define LDARX_INSTRUCTION 0x7c0000A8
989 #define STWCX_MASK 0xfc0007ff
990 #define STWCX_INSTRUCTION 0x7c00012d
991 #define STDCX_INSTRUCTION 0x7c0001ad
993 /* We can't displaced step atomic sequences. Otherwise this is just
994 like simple_displaced_step_copy_insn. */
996 static struct displaced_step_closure
*
997 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
998 CORE_ADDR from
, CORE_ADDR to
,
999 struct regcache
*regs
)
1001 size_t len
= gdbarch_max_insn_length (gdbarch
);
1002 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
);
1003 struct cleanup
*old_chain
= make_cleanup (xfree
, buf
);
1004 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1007 read_memory (from
, buf
, len
);
1009 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
1011 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1012 if ((insn
& LWARX_MASK
) == LWARX_INSTRUCTION
1013 || (insn
& LWARX_MASK
) == LDARX_INSTRUCTION
)
1015 if (debug_displaced
)
1017 fprintf_unfiltered (gdb_stdlog
,
1018 "displaced: can't displaced step "
1019 "atomic sequence at %s\n",
1020 paddress (gdbarch
, from
));
1022 do_cleanups (old_chain
);
1026 write_memory (to
, buf
, len
);
1028 if (debug_displaced
)
1030 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1031 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1032 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1035 discard_cleanups (old_chain
);
1036 return (struct displaced_step_closure
*) buf
;
1039 /* Fix up the state of registers and memory after having single-stepped
1040 a displaced instruction. */
1042 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
1043 struct displaced_step_closure
*closure
,
1044 CORE_ADDR from
, CORE_ADDR to
,
1045 struct regcache
*regs
)
1047 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1048 /* Our closure is a copy of the instruction. */
1049 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
1050 PPC_INSN_SIZE
, byte_order
);
1051 ULONGEST opcode
= 0;
1052 /* Offset for non PC-relative instructions. */
1053 LONGEST offset
= PPC_INSN_SIZE
;
1055 opcode
= insn
& BRANCH_MASK
;
1057 if (debug_displaced
)
1058 fprintf_unfiltered (gdb_stdlog
,
1059 "displaced: (ppc) fixup (%s, %s)\n",
1060 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1063 /* Handle PC-relative branch instructions. */
1064 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1066 ULONGEST current_pc
;
1068 /* Read the current PC value after the instruction has been executed
1069 in a displaced location. Calculate the offset to be applied to the
1070 original PC value before the displaced stepping. */
1071 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1073 offset
= current_pc
- to
;
1075 if (opcode
!= BXL_INSN
)
1077 /* Check for AA bit indicating whether this is an absolute
1078 addressing or PC-relative (1: absolute, 0: relative). */
1081 /* PC-relative addressing is being used in the branch. */
1082 if (debug_displaced
)
1085 "displaced: (ppc) branch instruction: %s\n"
1086 "displaced: (ppc) adjusted PC from %s to %s\n",
1087 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1088 paddress (gdbarch
, from
+ offset
));
1090 regcache_cooked_write_unsigned (regs
,
1091 gdbarch_pc_regnum (gdbarch
),
1097 /* If we're here, it means we have a branch to LR or CTR. If the
1098 branch was taken, the offset is probably greater than 4 (the next
1099 instruction), so it's safe to assume that an offset of 4 means we
1100 did not take the branch. */
1101 if (offset
== PPC_INSN_SIZE
)
1102 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1103 from
+ PPC_INSN_SIZE
);
1106 /* Check for LK bit indicating whether we should set the link
1107 register to point to the next instruction
1108 (1: Set, 0: Don't set). */
1111 /* Link register needs to be set to the next instruction's PC. */
1112 regcache_cooked_write_unsigned (regs
,
1113 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1114 from
+ PPC_INSN_SIZE
);
1115 if (debug_displaced
)
1116 fprintf_unfiltered (gdb_stdlog
,
1117 "displaced: (ppc) adjusted LR to %s\n",
1118 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1122 /* Check for breakpoints in the inferior. If we've found one, place the PC
1123 right at the breakpoint instruction. */
1124 else if ((insn
& BP_MASK
) == BP_INSN
)
1125 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1127 /* Handle any other instructions that do not fit in the categories above. */
1128 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1132 /* Always use hardware single-stepping to execute the
1133 displaced instruction. */
1135 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1136 struct displaced_step_closure
*closure
)
1141 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1142 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1143 is found, attempt to step through it. A breakpoint is placed at the end of
1147 ppc_deal_with_atomic_sequence (struct frame_info
*frame
)
1149 struct regcache
*regcache
= get_current_regcache ();
1150 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1151 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1152 CORE_ADDR pc
= regcache_read_pc (regcache
);
1153 CORE_ADDR breaks
[2] = {-1, -1};
1155 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1156 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1159 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1160 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1161 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1162 VEC (CORE_ADDR
) *next_pcs
= NULL
;
1164 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1165 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
1166 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
1169 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1171 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1173 loc
+= PPC_INSN_SIZE
;
1174 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1176 /* Assume that there is at most one conditional branch in the atomic
1177 sequence. If a conditional branch is found, put a breakpoint in
1178 its destination address. */
1179 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1181 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1182 int absolute
= insn
& 2;
1184 if (bc_insn_count
>= 1)
1185 return 0; /* More than one conditional branch found, fallback
1186 to the standard single-step code. */
1189 breaks
[1] = immediate
;
1191 breaks
[1] = loc
+ immediate
;
1197 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
1198 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
1202 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1203 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
1204 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
1208 loc
+= PPC_INSN_SIZE
;
1209 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1211 /* Insert a breakpoint right after the end of the atomic sequence. */
1214 /* Check for duplicated breakpoints. Check also for a breakpoint
1215 placed (branch instruction's destination) anywhere in sequence. */
1217 && (breaks
[1] == breaks
[0]
1218 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1219 last_breakpoint
= 0;
1221 for (index
= 0; index
<= last_breakpoint
; index
++)
1222 VEC_safe_push (CORE_ADDR
, next_pcs
, breaks
[index
]);
1228 #define SIGNED_SHORT(x) \
1229 ((sizeof (short) == 2) \
1230 ? ((int)(short)(x)) \
1231 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1233 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1235 /* Limit the number of skipped non-prologue instructions, as the examining
1236 of the prologue is expensive. */
1237 static int max_skip_non_prologue_insns
= 10;
1239 /* Return nonzero if the given instruction OP can be part of the prologue
1240 of a function and saves a parameter on the stack. FRAMEP should be
1241 set if one of the previous instructions in the function has set the
1245 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1247 /* Move parameters from argument registers to temporary register. */
1248 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1250 /* Rx must be scratch register r0. */
1251 const int rx_regno
= (op
>> 16) & 31;
1252 /* Ry: Only r3 - r10 are used for parameter passing. */
1253 const int ry_regno
= GET_SRC_REG (op
);
1255 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1257 *r0_contains_arg
= 1;
1264 /* Save a General Purpose Register on stack. */
1266 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1267 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1269 /* Rx: Only r3 - r10 are used for parameter passing. */
1270 const int rx_regno
= GET_SRC_REG (op
);
1272 return (rx_regno
>= 3 && rx_regno
<= 10);
1275 /* Save a General Purpose Register on stack via the Frame Pointer. */
1278 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1279 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1280 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1282 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1283 However, the compiler sometimes uses r0 to hold an argument. */
1284 const int rx_regno
= GET_SRC_REG (op
);
1286 return ((rx_regno
>= 3 && rx_regno
<= 10)
1287 || (rx_regno
== 0 && *r0_contains_arg
));
1290 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1292 /* Only f2 - f8 are used for parameter passing. */
1293 const int src_regno
= GET_SRC_REG (op
);
1295 return (src_regno
>= 2 && src_regno
<= 8);
1298 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1300 /* Only f2 - f8 are used for parameter passing. */
1301 const int src_regno
= GET_SRC_REG (op
);
1303 return (src_regno
>= 2 && src_regno
<= 8);
1306 /* Not an insn that saves a parameter on stack. */
1310 /* Assuming that INSN is a "bl" instruction located at PC, return
1311 nonzero if the destination of the branch is a "blrl" instruction.
1313 This sequence is sometimes found in certain function prologues.
1314 It allows the function to load the LR register with a value that
1315 they can use to access PIC data using PC-relative offsets. */
1318 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1325 absolute
= (int) ((insn
>> 1) & 1);
1326 immediate
= ((insn
& ~3) << 6) >> 6;
1330 dest
= pc
+ immediate
;
1332 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1333 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1339 /* Masks for decoding a branch-and-link (bl) instruction.
1341 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1342 The former is anded with the opcode in question; if the result of
1343 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1344 question is a ``bl'' instruction.
1346 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1347 the branch displacement. */
1349 #define BL_MASK 0xfc000001
1350 #define BL_INSTRUCTION 0x48000001
1351 #define BL_DISPLACEMENT_MASK 0x03fffffc
1353 static unsigned long
1354 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1356 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1360 /* Fetch the instruction and convert it to an integer. */
1361 if (target_read_memory (pc
, buf
, 4))
1363 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1368 /* GCC generates several well-known sequences of instructions at the begining
1369 of each function prologue when compiling with -fstack-check. If one of
1370 such sequences starts at START_PC, then return the address of the
1371 instruction immediately past this sequence. Otherwise, return START_PC. */
1374 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1376 CORE_ADDR pc
= start_pc
;
1377 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1379 /* First possible sequence: A small number of probes.
1380 stw 0, -<some immediate>(1)
1381 [repeat this instruction any (small) number of times]. */
1383 if ((op
& 0xffff0000) == 0x90010000)
1385 while ((op
& 0xffff0000) == 0x90010000)
1388 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1393 /* Second sequence: A probing loop.
1394 addi 12,1,-<some immediate>
1395 lis 0,-<some immediate>
1396 [possibly ori 0,0,<some immediate>]
1400 addi 12,12,-<some immediate>
1403 [possibly one last probe: stw 0,<some immediate>(12)]. */
1407 /* addi 12,1,-<some immediate> */
1408 if ((op
& 0xffff0000) != 0x39810000)
1411 /* lis 0,-<some immediate> */
1413 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1414 if ((op
& 0xffff0000) != 0x3c000000)
1418 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1419 /* [possibly ori 0,0,<some immediate>] */
1420 if ((op
& 0xffff0000) == 0x60000000)
1423 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1426 if (op
!= 0x7c0c0214)
1431 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1432 if (op
!= 0x7c0c0000)
1437 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1438 if ((op
& 0xff9f0001) != 0x41820000)
1441 /* addi 12,12,-<some immediate> */
1443 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1444 if ((op
& 0xffff0000) != 0x398c0000)
1449 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1450 if (op
!= 0x900c0000)
1455 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1456 if ((op
& 0xfc000001) != 0x48000000)
1459 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1461 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1462 if ((op
& 0xffff0000) == 0x900c0000)
1465 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1468 /* We found a valid stack-check sequence, return the new PC. */
1472 /* Third sequence: No probe; instead, a comparizon between the stack size
1473 limit (saved in a run-time global variable) and the current stack
1476 addi 0,1,-<some immediate>
1477 lis 12,__gnat_stack_limit@ha
1478 lwz 12,__gnat_stack_limit@l(12)
1481 or, with a small variant in the case of a bigger stack frame:
1482 addis 0,1,<some immediate>
1483 addic 0,0,-<some immediate>
1484 lis 12,__gnat_stack_limit@ha
1485 lwz 12,__gnat_stack_limit@l(12)
1490 /* addi 0,1,-<some immediate> */
1491 if ((op
& 0xffff0000) != 0x38010000)
1493 /* small stack frame variant not recognized; try the
1494 big stack frame variant: */
1496 /* addis 0,1,<some immediate> */
1497 if ((op
& 0xffff0000) != 0x3c010000)
1500 /* addic 0,0,-<some immediate> */
1502 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1503 if ((op
& 0xffff0000) != 0x30000000)
1507 /* lis 12,<some immediate> */
1509 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1510 if ((op
& 0xffff0000) != 0x3d800000)
1513 /* lwz 12,<some immediate>(12) */
1515 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1516 if ((op
& 0xffff0000) != 0x818c0000)
1521 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1522 if ((op
& 0xfffffffe) != 0x7c406008)
1525 /* We found a valid stack-check sequence, return the new PC. */
1529 /* No stack check code in our prologue, return the start_pc. */
1533 /* return pc value after skipping a function prologue and also return
1534 information about a function frame.
1536 in struct rs6000_framedata fdata:
1537 - frameless is TRUE, if function does not have a frame.
1538 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1539 - offset is the initial size of this stack frame --- the amount by
1540 which we decrement the sp to allocate the frame.
1541 - saved_gpr is the number of the first saved gpr.
1542 - saved_fpr is the number of the first saved fpr.
1543 - saved_vr is the number of the first saved vr.
1544 - saved_ev is the number of the first saved ev.
1545 - alloca_reg is the number of the register used for alloca() handling.
1547 - gpr_offset is the offset of the first saved gpr from the previous frame.
1548 - fpr_offset is the offset of the first saved fpr from the previous frame.
1549 - vr_offset is the offset of the first saved vr from the previous frame.
1550 - ev_offset is the offset of the first saved ev from the previous frame.
1551 - lr_offset is the offset of the saved lr
1552 - cr_offset is the offset of the saved cr
1553 - vrsave_offset is the offset of the saved vrsave register. */
1556 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1557 struct rs6000_framedata
*fdata
)
1559 CORE_ADDR orig_pc
= pc
;
1560 CORE_ADDR last_prologue_pc
= pc
;
1561 CORE_ADDR li_found_pc
= 0;
1565 long vr_saved_offset
= 0;
1571 int vrsave_reg
= -1;
1574 int minimal_toc_loaded
= 0;
1575 int prev_insn_was_prologue_insn
= 1;
1576 int num_skip_non_prologue_insns
= 0;
1577 int r0_contains_arg
= 0;
1578 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1579 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1580 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1582 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1583 fdata
->saved_gpr
= -1;
1584 fdata
->saved_fpr
= -1;
1585 fdata
->saved_vr
= -1;
1586 fdata
->saved_ev
= -1;
1587 fdata
->alloca_reg
= -1;
1588 fdata
->frameless
= 1;
1589 fdata
->nosavedpc
= 1;
1590 fdata
->lr_register
= -1;
1592 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1598 /* Sometimes it isn't clear if an instruction is a prologue
1599 instruction or not. When we encounter one of these ambiguous
1600 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1601 Otherwise, we'll assume that it really is a prologue instruction. */
1602 if (prev_insn_was_prologue_insn
)
1603 last_prologue_pc
= pc
;
1605 /* Stop scanning if we've hit the limit. */
1609 prev_insn_was_prologue_insn
= 1;
1611 /* Fetch the instruction and convert it to an integer. */
1612 if (target_read_memory (pc
, buf
, 4))
1614 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1616 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1618 /* Since shared library / PIC code, which needs to get its
1619 address at runtime, can appear to save more than one link
1633 remember just the first one, but skip over additional
1636 lr_reg
= (op
& 0x03e00000) >> 21;
1638 r0_contains_arg
= 0;
1641 else if ((op
& 0xfc1fffff) == 0x7c000026)
1643 cr_reg
= (op
& 0x03e00000);
1645 r0_contains_arg
= 0;
1649 else if ((op
& 0xfc1f0000) == 0xd8010000)
1650 { /* stfd Rx,NUM(r1) */
1651 reg
= GET_SRC_REG (op
);
1652 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1654 fdata
->saved_fpr
= reg
;
1655 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1660 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1661 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1662 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1663 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1666 reg
= GET_SRC_REG (op
);
1667 if ((op
& 0xfc1f0000) == 0xbc010000)
1668 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1670 fdata
->gpr_mask
|= 1U << reg
;
1671 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1673 fdata
->saved_gpr
= reg
;
1674 if ((op
& 0xfc1f0003) == 0xf8010000)
1676 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1681 else if ((op
& 0xffff0000) == 0x3c4c0000
1682 || (op
& 0xffff0000) == 0x3c400000
1683 || (op
& 0xffff0000) == 0x38420000)
1685 /* . 0: addis 2,12,.TOC.-0b@ha
1686 . addi 2,2,.TOC.-0b@l
1690 used by ELFv2 global entry points to set up r2. */
1693 else if (op
== 0x60000000)
1696 /* Allow nops in the prologue, but do not consider them to
1697 be part of the prologue unless followed by other prologue
1699 prev_insn_was_prologue_insn
= 0;
1703 else if ((op
& 0xffff0000) == 0x3c000000)
1704 { /* addis 0,0,NUM, used for >= 32k frames */
1705 fdata
->offset
= (op
& 0x0000ffff) << 16;
1706 fdata
->frameless
= 0;
1707 r0_contains_arg
= 0;
1711 else if ((op
& 0xffff0000) == 0x60000000)
1712 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1713 fdata
->offset
|= (op
& 0x0000ffff);
1714 fdata
->frameless
= 0;
1715 r0_contains_arg
= 0;
1719 else if (lr_reg
>= 0 &&
1720 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1721 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1722 /* stw Rx, NUM(r1) */
1723 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1724 /* stwu Rx, NUM(r1) */
1725 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1726 { /* where Rx == lr */
1727 fdata
->lr_offset
= offset
;
1728 fdata
->nosavedpc
= 0;
1729 /* Invalidate lr_reg, but don't set it to -1.
1730 That would mean that it had never been set. */
1732 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1733 (op
& 0xfc000000) == 0x90000000) /* stw */
1735 /* Does not update r1, so add displacement to lr_offset. */
1736 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1741 else if (cr_reg
>= 0 &&
1742 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1743 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1744 /* stw Rx, NUM(r1) */
1745 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1746 /* stwu Rx, NUM(r1) */
1747 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1748 { /* where Rx == cr */
1749 fdata
->cr_offset
= offset
;
1750 /* Invalidate cr_reg, but don't set it to -1.
1751 That would mean that it had never been set. */
1753 if ((op
& 0xfc000003) == 0xf8000000 ||
1754 (op
& 0xfc000000) == 0x90000000)
1756 /* Does not update r1, so add displacement to cr_offset. */
1757 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1762 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1764 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1765 prediction bits. If the LR has already been saved, we can
1769 else if (op
== 0x48000005)
1776 else if (op
== 0x48000004)
1781 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1782 in V.4 -mminimal-toc */
1783 (op
& 0xffff0000) == 0x3bde0000)
1784 { /* addi 30,30,foo@l */
1788 else if ((op
& 0xfc000001) == 0x48000001)
1792 fdata
->frameless
= 0;
1794 /* If the return address has already been saved, we can skip
1795 calls to blrl (for PIC). */
1796 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1802 /* Don't skip over the subroutine call if it is not within
1803 the first three instructions of the prologue and either
1804 we have no line table information or the line info tells
1805 us that the subroutine call is not part of the line
1806 associated with the prologue. */
1807 if ((pc
- orig_pc
) > 8)
1809 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1810 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1812 if ((prologue_sal
.line
== 0)
1813 || (prologue_sal
.line
!= this_sal
.line
))
1817 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1819 /* At this point, make sure this is not a trampoline
1820 function (a function that simply calls another functions,
1821 and nothing else). If the next is not a nop, this branch
1822 was part of the function prologue. */
1824 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1825 break; /* Don't skip over
1831 /* update stack pointer */
1832 else if ((op
& 0xfc1f0000) == 0x94010000)
1833 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1834 fdata
->frameless
= 0;
1835 fdata
->offset
= SIGNED_SHORT (op
);
1836 offset
= fdata
->offset
;
1839 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1840 { /* stwux rX,r1,rY */
1841 /* No way to figure out what r1 is going to be. */
1842 fdata
->frameless
= 0;
1843 offset
= fdata
->offset
;
1846 else if ((op
& 0xfc1f0003) == 0xf8010001)
1847 { /* stdu rX,NUM(r1) */
1848 fdata
->frameless
= 0;
1849 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1850 offset
= fdata
->offset
;
1853 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1854 { /* stdux rX,r1,rY */
1855 /* No way to figure out what r1 is going to be. */
1856 fdata
->frameless
= 0;
1857 offset
= fdata
->offset
;
1860 else if ((op
& 0xffff0000) == 0x38210000)
1861 { /* addi r1,r1,SIMM */
1862 fdata
->frameless
= 0;
1863 fdata
->offset
+= SIGNED_SHORT (op
);
1864 offset
= fdata
->offset
;
1867 /* Load up minimal toc pointer. Do not treat an epilogue restore
1868 of r31 as a minimal TOC load. */
1869 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1870 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1872 && !minimal_toc_loaded
)
1874 minimal_toc_loaded
= 1;
1877 /* move parameters from argument registers to local variable
1880 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1881 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1882 (((op
>> 21) & 31) <= 10) &&
1883 ((long) ((op
>> 16) & 31)
1884 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1888 /* store parameters in stack */
1890 /* Move parameters from argument registers to temporary register. */
1891 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1895 /* Set up frame pointer */
1897 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1899 fdata
->frameless
= 0;
1901 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1904 /* Another way to set up the frame pointer. */
1906 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1907 || op
== 0x7c3f0b78)
1909 fdata
->frameless
= 0;
1911 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1914 /* Another way to set up the frame pointer. */
1916 else if ((op
& 0xfc1fffff) == 0x38010000)
1917 { /* addi rX, r1, 0x0 */
1918 fdata
->frameless
= 0;
1920 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1921 + ((op
& ~0x38010000) >> 21));
1924 /* AltiVec related instructions. */
1925 /* Store the vrsave register (spr 256) in another register for
1926 later manipulation, or load a register into the vrsave
1927 register. 2 instructions are used: mfvrsave and
1928 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1929 and mtspr SPR256, Rn. */
1930 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1931 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1932 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1934 vrsave_reg
= GET_SRC_REG (op
);
1937 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1941 /* Store the register where vrsave was saved to onto the stack:
1942 rS is the register where vrsave was stored in a previous
1944 /* 100100 sssss 00001 dddddddd dddddddd */
1945 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1947 if (vrsave_reg
== GET_SRC_REG (op
))
1949 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1954 /* Compute the new value of vrsave, by modifying the register
1955 where vrsave was saved to. */
1956 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1957 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1961 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1962 in a pair of insns to save the vector registers on the
1964 /* 001110 00000 00000 iiii iiii iiii iiii */
1965 /* 001110 01110 00000 iiii iiii iiii iiii */
1966 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1967 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1969 if ((op
& 0xffff0000) == 0x38000000)
1970 r0_contains_arg
= 0;
1972 vr_saved_offset
= SIGNED_SHORT (op
);
1974 /* This insn by itself is not part of the prologue, unless
1975 if part of the pair of insns mentioned above. So do not
1976 record this insn as part of the prologue yet. */
1977 prev_insn_was_prologue_insn
= 0;
1979 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1980 /* 011111 sssss 11111 00000 00111001110 */
1981 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1983 if (pc
== (li_found_pc
+ 4))
1985 vr_reg
= GET_SRC_REG (op
);
1986 /* If this is the first vector reg to be saved, or if
1987 it has a lower number than others previously seen,
1988 reupdate the frame info. */
1989 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1991 fdata
->saved_vr
= vr_reg
;
1992 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1994 vr_saved_offset
= -1;
1999 /* End AltiVec related instructions. */
2001 /* Start BookE related instructions. */
2002 /* Store gen register S at (r31+uimm).
2003 Any register less than r13 is volatile, so we don't care. */
2004 /* 000100 sssss 11111 iiiii 01100100001 */
2005 else if (arch_info
->mach
== bfd_mach_ppc_e500
2006 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2008 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2011 ev_reg
= GET_SRC_REG (op
);
2012 imm
= (op
>> 11) & 0x1f;
2013 ev_offset
= imm
* 8;
2014 /* If this is the first vector reg to be saved, or if
2015 it has a lower number than others previously seen,
2016 reupdate the frame info. */
2017 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2019 fdata
->saved_ev
= ev_reg
;
2020 fdata
->ev_offset
= ev_offset
+ offset
;
2025 /* Store gen register rS at (r1+rB). */
2026 /* 000100 sssss 00001 bbbbb 01100100000 */
2027 else if (arch_info
->mach
== bfd_mach_ppc_e500
2028 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2030 if (pc
== (li_found_pc
+ 4))
2032 ev_reg
= GET_SRC_REG (op
);
2033 /* If this is the first vector reg to be saved, or if
2034 it has a lower number than others previously seen,
2035 reupdate the frame info. */
2036 /* We know the contents of rB from the previous instruction. */
2037 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2039 fdata
->saved_ev
= ev_reg
;
2040 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2042 vr_saved_offset
= -1;
2048 /* Store gen register r31 at (rA+uimm). */
2049 /* 000100 11111 aaaaa iiiii 01100100001 */
2050 else if (arch_info
->mach
== bfd_mach_ppc_e500
2051 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2053 /* Wwe know that the source register is 31 already, but
2054 it can't hurt to compute it. */
2055 ev_reg
= GET_SRC_REG (op
);
2056 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2057 /* If this is the first vector reg to be saved, or if
2058 it has a lower number than others previously seen,
2059 reupdate the frame info. */
2060 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2062 fdata
->saved_ev
= ev_reg
;
2063 fdata
->ev_offset
= ev_offset
+ offset
;
2068 /* Store gen register S at (r31+r0).
2069 Store param on stack when offset from SP bigger than 4 bytes. */
2070 /* 000100 sssss 11111 00000 01100100000 */
2071 else if (arch_info
->mach
== bfd_mach_ppc_e500
2072 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2074 if (pc
== (li_found_pc
+ 4))
2076 if ((op
& 0x03e00000) >= 0x01a00000)
2078 ev_reg
= GET_SRC_REG (op
);
2079 /* If this is the first vector reg to be saved, or if
2080 it has a lower number than others previously seen,
2081 reupdate the frame info. */
2082 /* We know the contents of r0 from the previous
2084 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2086 fdata
->saved_ev
= ev_reg
;
2087 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2091 vr_saved_offset
= -1;
2096 /* End BookE related instructions. */
2100 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2102 /* Not a recognized prologue instruction.
2103 Handle optimizer code motions into the prologue by continuing
2104 the search if we have no valid frame yet or if the return
2105 address is not yet saved in the frame. Also skip instructions
2106 if some of the GPRs expected to be saved are not yet saved. */
2107 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2108 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2111 if (op
== 0x4e800020 /* blr */
2112 || op
== 0x4e800420) /* bctr */
2113 /* Do not scan past epilogue in frameless functions or
2116 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2117 /* Never skip branches. */
2120 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2121 /* Do not scan too many insns, scanning insns is expensive with
2125 /* Continue scanning. */
2126 prev_insn_was_prologue_insn
= 0;
2132 /* I have problems with skipping over __main() that I need to address
2133 * sometime. Previously, I used to use misc_function_vector which
2134 * didn't work as well as I wanted to be. -MGO */
2136 /* If the first thing after skipping a prolog is a branch to a function,
2137 this might be a call to an initializer in main(), introduced by gcc2.
2138 We'd like to skip over it as well. Fortunately, xlc does some extra
2139 work before calling a function right after a prologue, thus we can
2140 single out such gcc2 behaviour. */
2143 if ((op
& 0xfc000001) == 0x48000001)
2144 { /* bl foo, an initializer function? */
2145 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2147 if (op
== 0x4def7b82)
2148 { /* cror 0xf, 0xf, 0xf (nop) */
2150 /* Check and see if we are in main. If so, skip over this
2151 initializer function as well. */
2153 tmp
= find_pc_misc_function (pc
);
2155 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2161 if (pc
== lim_pc
&& lr_reg
>= 0)
2162 fdata
->lr_register
= lr_reg
;
2164 fdata
->offset
= -fdata
->offset
;
2165 return last_prologue_pc
;
2169 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2171 struct rs6000_framedata frame
;
2172 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2174 /* See if we can determine the end of the prologue via the symbol table.
2175 If so, then return either PC, or the PC after the prologue, whichever
2177 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2179 CORE_ADDR post_prologue_pc
2180 = skip_prologue_using_sal (gdbarch
, func_addr
);
2181 if (post_prologue_pc
!= 0)
2182 return std::max (pc
, post_prologue_pc
);
2185 /* Can't determine prologue from the symbol table, need to examine
2188 /* Find an upper limit on the function prologue using the debug
2189 information. If the debug information could not be used to provide
2190 that bound, then use an arbitrary large number as the upper bound. */
2191 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2193 limit_pc
= pc
+ 100; /* Magic. */
2195 /* Do not allow limit_pc to be past the function end, if we know
2196 where that end is... */
2197 if (func_end_addr
&& limit_pc
> func_end_addr
)
2198 limit_pc
= func_end_addr
;
2200 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2204 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2205 in the prologue of main().
2207 The function below examines the code pointed at by PC and checks to
2208 see if it corresponds to a call to __eabi. If so, it returns the
2209 address of the instruction following that call. Otherwise, it simply
2213 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2215 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2219 if (target_read_memory (pc
, buf
, 4))
2221 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2223 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2225 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2226 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2227 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2229 /* We check for ___eabi (three leading underscores) in addition
2230 to __eabi in case the GCC option "-fleading-underscore" was
2231 used to compile the program. */
2232 if (s
.minsym
!= NULL
2233 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2234 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2235 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2241 /* All the ABI's require 16 byte alignment. */
2243 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2245 return (addr
& -16);
2248 /* Return whether handle_inferior_event() should proceed through code
2249 starting at PC in function NAME when stepping.
2251 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2252 handle memory references that are too distant to fit in instructions
2253 generated by the compiler. For example, if 'foo' in the following
2258 is greater than 32767, the linker might replace the lwz with a branch to
2259 somewhere in @FIX1 that does the load in 2 instructions and then branches
2260 back to where execution should continue.
2262 GDB should silently step over @FIX code, just like AIX dbx does.
2263 Unfortunately, the linker uses the "b" instruction for the
2264 branches, meaning that the link register doesn't get set.
2265 Therefore, GDB's usual step_over_function () mechanism won't work.
2267 Instead, use the gdbarch_skip_trampoline_code and
2268 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2272 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2273 CORE_ADDR pc
, const char *name
)
2275 return name
&& startswith (name
, "@FIX");
2278 /* Skip code that the user doesn't want to see when stepping:
2280 1. Indirect function calls use a piece of trampoline code to do context
2281 switching, i.e. to set the new TOC table. Skip such code if we are on
2282 its first instruction (as when we have single-stepped to here).
2284 2. Skip shared library trampoline code (which is different from
2285 indirect function call trampolines).
2287 3. Skip bigtoc fixup code.
2289 Result is desired PC to step until, or NULL if we are not in
2290 code that should be skipped. */
2293 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2295 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2296 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2297 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2298 unsigned int ii
, op
;
2300 CORE_ADDR solib_target_pc
;
2301 struct bound_minimal_symbol msymbol
;
2303 static unsigned trampoline_code
[] =
2305 0x800b0000, /* l r0,0x0(r11) */
2306 0x90410014, /* st r2,0x14(r1) */
2307 0x7c0903a6, /* mtctr r0 */
2308 0x804b0004, /* l r2,0x4(r11) */
2309 0x816b0008, /* l r11,0x8(r11) */
2310 0x4e800420, /* bctr */
2311 0x4e800020, /* br */
2315 /* Check for bigtoc fixup code. */
2316 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2318 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2319 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2321 /* Double-check that the third instruction from PC is relative "b". */
2322 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2323 if ((op
& 0xfc000003) == 0x48000000)
2325 /* Extract bits 6-29 as a signed 24-bit relative word address and
2326 add it to the containing PC. */
2327 rel
= ((int)(op
<< 6) >> 6);
2328 return pc
+ 8 + rel
;
2332 /* If pc is in a shared library trampoline, return its target. */
2333 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2334 if (solib_target_pc
)
2335 return solib_target_pc
;
2337 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2339 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2340 if (op
!= trampoline_code
[ii
])
2343 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2345 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2349 /* ISA-specific vector types. */
2351 static struct type
*
2352 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2354 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2356 if (!tdep
->ppc_builtin_type_vec64
)
2358 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2360 /* The type we're building is this: */
2362 union __gdb_builtin_type_vec64
2366 int32_t v2_int32
[2];
2367 int16_t v4_int16
[4];
2374 t
= arch_composite_type (gdbarch
,
2375 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2376 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2377 append_composite_type_field (t
, "v2_float",
2378 init_vector_type (bt
->builtin_float
, 2));
2379 append_composite_type_field (t
, "v2_int32",
2380 init_vector_type (bt
->builtin_int32
, 2));
2381 append_composite_type_field (t
, "v4_int16",
2382 init_vector_type (bt
->builtin_int16
, 4));
2383 append_composite_type_field (t
, "v8_int8",
2384 init_vector_type (bt
->builtin_int8
, 8));
2386 TYPE_VECTOR (t
) = 1;
2387 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2388 tdep
->ppc_builtin_type_vec64
= t
;
2391 return tdep
->ppc_builtin_type_vec64
;
2394 /* Vector 128 type. */
2396 static struct type
*
2397 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2399 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2401 if (!tdep
->ppc_builtin_type_vec128
)
2403 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2405 /* The type we're building is this
2407 type = union __ppc_builtin_type_vec128 {
2409 double v2_double[2];
2411 int32_t v4_int32[4];
2412 int16_t v8_int16[8];
2413 int8_t v16_int8[16];
2419 t
= arch_composite_type (gdbarch
,
2420 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2421 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2422 append_composite_type_field (t
, "v2_double",
2423 init_vector_type (bt
->builtin_double
, 2));
2424 append_composite_type_field (t
, "v4_float",
2425 init_vector_type (bt
->builtin_float
, 4));
2426 append_composite_type_field (t
, "v4_int32",
2427 init_vector_type (bt
->builtin_int32
, 4));
2428 append_composite_type_field (t
, "v8_int16",
2429 init_vector_type (bt
->builtin_int16
, 8));
2430 append_composite_type_field (t
, "v16_int8",
2431 init_vector_type (bt
->builtin_int8
, 16));
2433 TYPE_VECTOR (t
) = 1;
2434 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2435 tdep
->ppc_builtin_type_vec128
= t
;
2438 return tdep
->ppc_builtin_type_vec128
;
2441 /* Return the name of register number REGNO, or the empty string if it
2442 is an anonymous register. */
2445 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2447 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2449 /* The upper half "registers" have names in the XML description,
2450 but we present only the low GPRs and the full 64-bit registers
2452 if (tdep
->ppc_ev0_upper_regnum
>= 0
2453 && tdep
->ppc_ev0_upper_regnum
<= regno
2454 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2457 /* Hide the upper halves of the vs0~vs31 registers. */
2458 if (tdep
->ppc_vsr0_regnum
>= 0
2459 && tdep
->ppc_vsr0_upper_regnum
<= regno
2460 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2463 /* Check if the SPE pseudo registers are available. */
2464 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2466 static const char *const spe_regnames
[] = {
2467 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2468 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2469 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2470 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2472 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2475 /* Check if the decimal128 pseudo-registers are available. */
2476 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2478 static const char *const dfp128_regnames
[] = {
2479 "dl0", "dl1", "dl2", "dl3",
2480 "dl4", "dl5", "dl6", "dl7",
2481 "dl8", "dl9", "dl10", "dl11",
2482 "dl12", "dl13", "dl14", "dl15"
2484 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2487 /* Check if this is a VSX pseudo-register. */
2488 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2490 static const char *const vsx_regnames
[] = {
2491 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2492 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2493 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2494 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2495 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2496 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2497 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2498 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2499 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2501 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2504 /* Check if the this is a Extended FP pseudo-register. */
2505 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2507 static const char *const efpr_regnames
[] = {
2508 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2509 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2510 "f46", "f47", "f48", "f49", "f50", "f51",
2511 "f52", "f53", "f54", "f55", "f56", "f57",
2512 "f58", "f59", "f60", "f61", "f62", "f63"
2514 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2517 return tdesc_register_name (gdbarch
, regno
);
2520 /* Return the GDB type object for the "standard" data type of data in
2523 static struct type
*
2524 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2526 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2528 /* These are the only pseudo-registers we support. */
2529 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2530 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2531 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2532 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2534 /* These are the e500 pseudo-registers. */
2535 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2536 return rs6000_builtin_type_vec64 (gdbarch
);
2537 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2538 /* PPC decimal128 pseudo-registers. */
2539 return builtin_type (gdbarch
)->builtin_declong
;
2540 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2541 /* POWER7 VSX pseudo-registers. */
2542 return rs6000_builtin_type_vec128 (gdbarch
);
2544 /* POWER7 Extended FP pseudo-registers. */
2545 return builtin_type (gdbarch
)->builtin_double
;
2548 /* Is REGNUM a member of REGGROUP? */
2550 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2551 struct reggroup
*group
)
2553 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2555 /* These are the only pseudo-registers we support. */
2556 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2557 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2558 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2559 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2561 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2562 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2563 return group
== all_reggroup
|| group
== vector_reggroup
;
2565 /* PPC decimal128 or Extended FP pseudo-registers. */
2566 return group
== all_reggroup
|| group
== float_reggroup
;
2569 /* The register format for RS/6000 floating point registers is always
2570 double, we need a conversion if the memory format is float. */
2573 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2576 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2578 return (tdep
->ppc_fp0_regnum
>= 0
2579 && regnum
>= tdep
->ppc_fp0_regnum
2580 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2581 && TYPE_CODE (type
) == TYPE_CODE_FLT
2582 && TYPE_LENGTH (type
)
2583 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2587 rs6000_register_to_value (struct frame_info
*frame
,
2591 int *optimizedp
, int *unavailablep
)
2593 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2594 gdb_byte from
[MAX_REGISTER_SIZE
];
2596 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2598 if (!get_frame_register_bytes (frame
, regnum
, 0,
2599 register_size (gdbarch
, regnum
),
2600 from
, optimizedp
, unavailablep
))
2603 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2605 *optimizedp
= *unavailablep
= 0;
2610 rs6000_value_to_register (struct frame_info
*frame
,
2613 const gdb_byte
*from
)
2615 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2616 gdb_byte to
[MAX_REGISTER_SIZE
];
2618 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2620 convert_typed_floating (from
, type
,
2621 to
, builtin_type (gdbarch
)->builtin_double
);
2622 put_frame_register (frame
, regnum
, to
);
2625 /* The type of a function that moves the value of REG between CACHE
2626 or BUF --- in either direction. */
2627 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2630 /* Move SPE vector register values between a 64-bit buffer and the two
2631 32-bit raw register halves in a regcache. This function handles
2632 both splitting a 64-bit value into two 32-bit halves, and joining
2633 two halves into a whole 64-bit value, depending on the function
2634 passed as the MOVE argument.
2636 EV_REG must be the number of an SPE evN vector register --- a
2637 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2640 Call MOVE once for each 32-bit half of that register, passing
2641 REGCACHE, the number of the raw register corresponding to that
2642 half, and the address of the appropriate half of BUFFER.
2644 For example, passing 'regcache_raw_read' as the MOVE function will
2645 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2646 'regcache_raw_supply' will supply the contents of BUFFER to the
2647 appropriate pair of raw registers in REGCACHE.
2649 You may need to cast away some 'const' qualifiers when passing
2650 MOVE, since this function can't tell at compile-time which of
2651 REGCACHE or BUFFER is acting as the source of the data. If C had
2652 co-variant type qualifiers, ... */
2654 static enum register_status
2655 e500_move_ev_register (move_ev_register_func move
,
2656 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2658 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2659 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2661 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2662 enum register_status status
;
2664 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2666 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2668 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2670 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2672 if (status
== REG_VALID
)
2673 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2678 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2679 if (status
== REG_VALID
)
2680 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2687 static enum register_status
2688 do_regcache_raw_read (struct regcache
*regcache
, int regnum
, void *buffer
)
2690 return regcache_raw_read (regcache
, regnum
, (gdb_byte
*) buffer
);
2693 static enum register_status
2694 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2696 regcache_raw_write (regcache
, regnum
, (const gdb_byte
*) buffer
);
2701 static enum register_status
2702 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2703 int reg_nr
, gdb_byte
*buffer
)
2705 return e500_move_ev_register (do_regcache_raw_read
, regcache
, reg_nr
, buffer
);
2709 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2710 int reg_nr
, const gdb_byte
*buffer
)
2712 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2713 reg_nr
, (void *) buffer
);
2716 /* Read method for DFP pseudo-registers. */
2717 static enum register_status
2718 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2719 int reg_nr
, gdb_byte
*buffer
)
2721 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2722 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2723 enum register_status status
;
2725 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2727 /* Read two FP registers to form a whole dl register. */
2728 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2729 2 * reg_index
, buffer
);
2730 if (status
== REG_VALID
)
2731 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2732 2 * reg_index
+ 1, buffer
+ 8);
2736 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2737 2 * reg_index
+ 1, buffer
);
2738 if (status
== REG_VALID
)
2739 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2740 2 * reg_index
, buffer
+ 8);
2746 /* Write method for DFP pseudo-registers. */
2748 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2749 int reg_nr
, const gdb_byte
*buffer
)
2751 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2752 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2754 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2756 /* Write each half of the dl register into a separate
2758 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2759 2 * reg_index
, buffer
);
2760 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2761 2 * reg_index
+ 1, buffer
+ 8);
2765 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2766 2 * reg_index
+ 1, buffer
);
2767 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2768 2 * reg_index
, buffer
+ 8);
2772 /* Read method for POWER7 VSX pseudo-registers. */
2773 static enum register_status
2774 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2775 int reg_nr
, gdb_byte
*buffer
)
2777 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2778 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2779 enum register_status status
;
2781 /* Read the portion that overlaps the VMX registers. */
2783 status
= regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2784 reg_index
- 32, buffer
);
2786 /* Read the portion that overlaps the FPR registers. */
2787 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2789 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2791 if (status
== REG_VALID
)
2792 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2793 reg_index
, buffer
+ 8);
2797 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2798 reg_index
, buffer
+ 8);
2799 if (status
== REG_VALID
)
2800 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2807 /* Write method for POWER7 VSX pseudo-registers. */
2809 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2810 int reg_nr
, const gdb_byte
*buffer
)
2812 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2813 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2815 /* Write the portion that overlaps the VMX registers. */
2817 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2818 reg_index
- 32, buffer
);
2820 /* Write the portion that overlaps the FPR registers. */
2821 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2823 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2825 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2826 reg_index
, buffer
+ 8);
2830 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2831 reg_index
, buffer
+ 8);
2832 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2837 /* Read method for POWER7 Extended FP pseudo-registers. */
2838 static enum register_status
2839 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2840 int reg_nr
, gdb_byte
*buffer
)
2842 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2843 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2844 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2846 /* Read the portion that overlaps the VMX register. */
2847 return regcache_raw_read_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2848 offset
, register_size (gdbarch
, reg_nr
),
2852 /* Write method for POWER7 Extended FP pseudo-registers. */
2854 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2855 int reg_nr
, const gdb_byte
*buffer
)
2857 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2858 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2859 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2861 /* Write the portion that overlaps the VMX register. */
2862 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2863 offset
, register_size (gdbarch
, reg_nr
),
2867 static enum register_status
2868 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2869 struct regcache
*regcache
,
2870 int reg_nr
, gdb_byte
*buffer
)
2872 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2873 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2875 gdb_assert (regcache_arch
== gdbarch
);
2877 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2878 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2879 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2880 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2881 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2882 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2883 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2884 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2886 internal_error (__FILE__
, __LINE__
,
2887 _("rs6000_pseudo_register_read: "
2888 "called on unexpected register '%s' (%d)"),
2889 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2893 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2894 struct regcache
*regcache
,
2895 int reg_nr
, const gdb_byte
*buffer
)
2897 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2898 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2900 gdb_assert (regcache_arch
== gdbarch
);
2902 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2903 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2904 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2905 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2906 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2907 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2908 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2909 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2911 internal_error (__FILE__
, __LINE__
,
2912 _("rs6000_pseudo_register_write: "
2913 "called on unexpected register '%s' (%d)"),
2914 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2918 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2919 struct agent_expr
*ax
, int reg_nr
)
2921 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2922 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2924 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
2925 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
2926 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
2928 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2930 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2931 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
);
2932 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
+ 1);
2934 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2936 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2939 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
- 32);
2943 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ reg_index
);
2944 ax_reg_mask (ax
, tdep
->ppc_vsr0_upper_regnum
+ reg_index
);
2947 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2949 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2950 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
);
2953 internal_error (__FILE__
, __LINE__
,
2954 _("rs6000_pseudo_register_collect: "
2955 "called on unexpected register '%s' (%d)"),
2956 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2962 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
2963 struct agent_expr
*ax
, struct axs_value
*value
,
2966 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2967 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
2968 value
->kind
= axs_lvalue_register
;
2969 value
->u
.reg
= tdep
->ppc_lr_regnum
;
2973 /* Convert a DBX STABS register number to a GDB register number. */
2975 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2977 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2979 if (0 <= num
&& num
<= 31)
2980 return tdep
->ppc_gp0_regnum
+ num
;
2981 else if (32 <= num
&& num
<= 63)
2982 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2983 specifies registers the architecture doesn't have? Our
2984 callers don't check the value we return. */
2985 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2986 else if (77 <= num
&& num
<= 108)
2987 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2988 else if (1200 <= num
&& num
< 1200 + 32)
2989 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2994 return tdep
->ppc_mq_regnum
;
2996 return tdep
->ppc_lr_regnum
;
2998 return tdep
->ppc_ctr_regnum
;
3000 return tdep
->ppc_xer_regnum
;
3002 return tdep
->ppc_vrsave_regnum
;
3004 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3006 return tdep
->ppc_acc_regnum
;
3008 return tdep
->ppc_spefscr_regnum
;
3015 /* Convert a Dwarf 2 register number to a GDB register number. */
3017 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3019 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3021 if (0 <= num
&& num
<= 31)
3022 return tdep
->ppc_gp0_regnum
+ num
;
3023 else if (32 <= num
&& num
<= 63)
3024 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3025 specifies registers the architecture doesn't have? Our
3026 callers don't check the value we return. */
3027 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3028 else if (1124 <= num
&& num
< 1124 + 32)
3029 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3030 else if (1200 <= num
&& num
< 1200 + 32)
3031 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3036 return tdep
->ppc_cr_regnum
;
3038 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3040 return tdep
->ppc_acc_regnum
;
3042 return tdep
->ppc_mq_regnum
;
3044 return tdep
->ppc_xer_regnum
;
3046 return tdep
->ppc_lr_regnum
;
3048 return tdep
->ppc_ctr_regnum
;
3050 return tdep
->ppc_vrsave_regnum
;
3052 return tdep
->ppc_spefscr_regnum
;
3058 /* Translate a .eh_frame register to DWARF register, or adjust a
3059 .debug_frame register. */
3062 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3064 /* GCC releases before 3.4 use GCC internal register numbering in
3065 .debug_frame (and .debug_info, et cetera). The numbering is
3066 different from the standard SysV numbering for everything except
3067 for GPRs and FPRs. We can not detect this problem in most cases
3068 - to get accurate debug info for variables living in lr, ctr, v0,
3069 et cetera, use a newer version of GCC. But we must detect
3070 one important case - lr is in column 65 in .debug_frame output,
3073 GCC 3.4, and the "hammer" branch, have a related problem. They
3074 record lr register saves in .debug_frame as 108, but still record
3075 the return column as 65. We fix that up too.
3077 We can do this because 65 is assigned to fpsr, and GCC never
3078 generates debug info referring to it. To add support for
3079 handwritten debug info that restores fpsr, we would need to add a
3080 producer version check to this. */
3089 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3090 internal register numbering; translate that to the standard DWARF2
3091 register numbering. */
3092 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3094 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3095 return num
- 68 + 86;
3096 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3097 return num
- 77 + 1124;
3109 case 109: /* vrsave */
3111 case 110: /* vscr */
3113 case 111: /* spe_acc */
3115 case 112: /* spefscr */
3123 /* Handling the various POWER/PowerPC variants. */
3125 /* Information about a particular processor variant. */
3129 /* Name of this variant. */
3132 /* English description of the variant. */
3135 /* bfd_arch_info.arch corresponding to variant. */
3136 enum bfd_architecture arch
;
3138 /* bfd_arch_info.mach corresponding to variant. */
3141 /* Target description for this variant. */
3142 struct target_desc
**tdesc
;
3145 static struct variant variants
[] =
3147 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3148 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3149 {"power", "POWER user-level", bfd_arch_rs6000
,
3150 bfd_mach_rs6k
, &tdesc_rs6000
},
3151 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3152 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3153 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3154 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3155 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3156 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3157 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3158 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3159 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3160 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3161 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3162 604, &tdesc_powerpc_604
},
3163 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3164 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3165 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3166 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3167 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3168 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3169 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3170 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3171 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3172 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3173 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3174 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3177 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3178 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3179 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3180 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3181 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3182 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3183 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3184 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3185 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3186 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3187 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3188 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3190 /* FIXME: I haven't checked the register sets of the following. */
3191 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3192 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3193 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3194 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3195 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3196 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3198 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3201 /* Return the variant corresponding to architecture ARCH and machine number
3202 MACH. If no such variant exists, return null. */
3204 static const struct variant
*
3205 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3207 const struct variant
*v
;
3209 for (v
= variants
; v
->name
; v
++)
3210 if (arch
== v
->arch
&& mach
== v
->mach
)
3217 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3219 if (info
->endian
== BFD_ENDIAN_BIG
)
3220 return print_insn_big_powerpc (memaddr
, info
);
3222 return print_insn_little_powerpc (memaddr
, info
);
3226 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3228 return frame_unwind_register_unsigned (next_frame
,
3229 gdbarch_pc_regnum (gdbarch
));
3232 static struct frame_id
3233 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3235 return frame_id_build (get_frame_register_unsigned
3236 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3237 get_frame_pc (this_frame
));
3240 struct rs6000_frame_cache
3243 CORE_ADDR initial_sp
;
3244 struct trad_frame_saved_reg
*saved_regs
;
3246 /* Set BASE_P to true if this frame cache is properly initialized.
3247 Otherwise set to false because some registers or memory cannot
3250 /* Cache PC for building unavailable frame. */
3254 static struct rs6000_frame_cache
*
3255 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3257 struct rs6000_frame_cache
*cache
;
3258 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3259 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3260 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3261 struct rs6000_framedata fdata
;
3262 int wordsize
= tdep
->wordsize
;
3263 CORE_ADDR func
= 0, pc
= 0;
3265 if ((*this_cache
) != NULL
)
3266 return (struct rs6000_frame_cache
*) (*this_cache
);
3267 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3268 (*this_cache
) = cache
;
3270 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3274 func
= get_frame_func (this_frame
);
3276 pc
= get_frame_pc (this_frame
);
3277 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3279 /* Figure out the parent's stack pointer. */
3281 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3282 address of the current frame. Things might be easier if the
3283 ->frame pointed to the outer-most address of the frame. In
3284 the mean time, the address of the prev frame is used as the
3285 base address of this frame. */
3286 cache
->base
= get_frame_register_unsigned
3287 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3289 CATCH (ex
, RETURN_MASK_ERROR
)
3291 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3292 throw_exception (ex
);
3293 return (struct rs6000_frame_cache
*) (*this_cache
);
3297 /* If the function appears to be frameless, check a couple of likely
3298 indicators that we have simply failed to find the frame setup.
3299 Two common cases of this are missing symbols (i.e.
3300 get_frame_func returns the wrong address or 0), and assembly
3301 stubs which have a fast exit path but set up a frame on the slow
3304 If the LR appears to return to this function, then presume that
3305 we have an ABI compliant frame that we failed to find. */
3306 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3311 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3312 if (func
== 0 && saved_lr
== pc
)
3316 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3317 if (func
== saved_func
)
3323 fdata
.frameless
= 0;
3324 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3328 if (!fdata
.frameless
)
3330 /* Frameless really means stackless. */
3333 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3334 byte_order
, &backchain
))
3335 cache
->base
= (CORE_ADDR
) backchain
;
3338 trad_frame_set_value (cache
->saved_regs
,
3339 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3341 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3342 All fpr's from saved_fpr to fp31 are saved. */
3344 if (fdata
.saved_fpr
>= 0)
3347 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3349 /* If skip_prologue says floating-point registers were saved,
3350 but the current architecture has no floating-point registers,
3351 then that's strange. But we have no indices to even record
3352 the addresses under, so we just ignore it. */
3353 if (ppc_floating_point_unit_p (gdbarch
))
3354 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3356 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3361 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3362 All gpr's from saved_gpr to gpr31 are saved (except during the
3365 if (fdata
.saved_gpr
>= 0)
3368 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3369 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3371 if (fdata
.gpr_mask
& (1U << i
))
3372 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3373 gpr_addr
+= wordsize
;
3377 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3378 All vr's from saved_vr to vr31 are saved. */
3379 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3381 if (fdata
.saved_vr
>= 0)
3384 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3385 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3387 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3388 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3393 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3394 All vr's from saved_ev to ev31 are saved. ????? */
3395 if (tdep
->ppc_ev0_regnum
!= -1)
3397 if (fdata
.saved_ev
>= 0)
3400 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3401 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3403 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3405 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3406 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3407 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3412 /* If != 0, fdata.cr_offset is the offset from the frame that
3414 if (fdata
.cr_offset
!= 0)
3415 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3416 = cache
->base
+ fdata
.cr_offset
;
3418 /* If != 0, fdata.lr_offset is the offset from the frame that
3420 if (fdata
.lr_offset
!= 0)
3421 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3422 = cache
->base
+ fdata
.lr_offset
;
3423 else if (fdata
.lr_register
!= -1)
3424 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3425 /* The PC is found in the link register. */
3426 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3427 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3429 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3430 holds the VRSAVE. */
3431 if (fdata
.vrsave_offset
!= 0)
3432 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3433 = cache
->base
+ fdata
.vrsave_offset
;
3435 if (fdata
.alloca_reg
< 0)
3436 /* If no alloca register used, then fi->frame is the value of the
3437 %sp for this frame, and it is good enough. */
3439 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3442 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3449 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3450 struct frame_id
*this_id
)
3452 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3457 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3461 /* This marks the outermost frame. */
3462 if (info
->base
== 0)
3465 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3468 static struct value
*
3469 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3470 void **this_cache
, int regnum
)
3472 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3474 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3477 static const struct frame_unwind rs6000_frame_unwind
=
3480 default_frame_unwind_stop_reason
,
3481 rs6000_frame_this_id
,
3482 rs6000_frame_prev_register
,
3484 default_frame_sniffer
3487 /* Allocate and initialize a frame cache for an epilogue frame.
3488 SP is restored and prev-PC is stored in LR. */
3490 static struct rs6000_frame_cache
*
3491 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3493 struct rs6000_frame_cache
*cache
;
3494 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3495 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3498 return (struct rs6000_frame_cache
*) *this_cache
;
3500 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3501 (*this_cache
) = cache
;
3502 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3506 /* At this point the stack looks as if we just entered the
3507 function, and the return address is stored in LR. */
3510 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3511 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3514 cache
->initial_sp
= sp
;
3516 trad_frame_set_value (cache
->saved_regs
,
3517 gdbarch_pc_regnum (gdbarch
), lr
);
3519 CATCH (ex
, RETURN_MASK_ERROR
)
3521 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3522 throw_exception (ex
);
3529 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3530 Return the frame ID of an epilogue frame. */
3533 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3534 void **this_cache
, struct frame_id
*this_id
)
3537 struct rs6000_frame_cache
*info
=
3538 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3540 pc
= get_frame_func (this_frame
);
3541 if (info
->base
== 0)
3542 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3544 (*this_id
) = frame_id_build (info
->base
, pc
);
3547 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3548 Return the register value of REGNUM in previous frame. */
3550 static struct value
*
3551 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3552 void **this_cache
, int regnum
)
3554 struct rs6000_frame_cache
*info
=
3555 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3556 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3559 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3560 Check whether this an epilogue frame. */
3563 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3564 struct frame_info
*this_frame
,
3565 void **this_prologue_cache
)
3567 if (frame_relative_level (this_frame
) == 0)
3568 return rs6000_in_function_epilogue_frame_p (this_frame
,
3569 get_frame_arch (this_frame
),
3570 get_frame_pc (this_frame
));
3575 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3576 a function without debug information. */
3578 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3581 default_frame_unwind_stop_reason
,
3582 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3584 rs6000_epilogue_frame_sniffer
3589 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3591 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3593 return info
->initial_sp
;
3596 static const struct frame_base rs6000_frame_base
= {
3597 &rs6000_frame_unwind
,
3598 rs6000_frame_base_address
,
3599 rs6000_frame_base_address
,
3600 rs6000_frame_base_address
3603 static const struct frame_base
*
3604 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3606 return &rs6000_frame_base
;
3609 /* DWARF-2 frame support. Used to handle the detection of
3610 clobbered registers during function calls. */
3613 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3614 struct dwarf2_frame_state_reg
*reg
,
3615 struct frame_info
*this_frame
)
3617 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3619 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3620 non-volatile registers. We will use the same code for both. */
3622 /* Call-saved GP registers. */
3623 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3624 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3625 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3626 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3628 /* Call-clobbered GP registers. */
3629 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3630 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3631 || (regnum
== tdep
->ppc_gp0_regnum
))
3632 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3634 /* Deal with FP registers, if supported. */
3635 if (tdep
->ppc_fp0_regnum
>= 0)
3637 /* Call-saved FP registers. */
3638 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3639 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3640 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3642 /* Call-clobbered FP registers. */
3643 if ((regnum
>= tdep
->ppc_fp0_regnum
3644 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3645 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3648 /* Deal with ALTIVEC registers, if supported. */
3649 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3651 /* Call-saved Altivec registers. */
3652 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3653 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3654 || regnum
== tdep
->ppc_vrsave_regnum
)
3655 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3657 /* Call-clobbered Altivec registers. */
3658 if ((regnum
>= tdep
->ppc_vr0_regnum
3659 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3660 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3663 /* Handle PC register and Stack Pointer correctly. */
3664 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3665 reg
->how
= DWARF2_FRAME_REG_RA
;
3666 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3667 reg
->how
= DWARF2_FRAME_REG_CFA
;
3671 /* Return true if a .gnu_attributes section exists in BFD and it
3672 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3673 section exists in BFD and it indicates that SPE extensions are in
3674 use. Check the .gnu.attributes section first, as the binary might be
3675 compiled for SPE, but not actually using SPE instructions. */
3678 bfd_uses_spe_extensions (bfd
*abfd
)
3681 gdb_byte
*contents
= NULL
;
3691 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3692 could be using the SPE vector abi without actually using any spe
3693 bits whatsoever. But it's close enough for now. */
3694 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3695 Tag_GNU_Power_ABI_Vector
);
3696 if (vector_abi
== 3)
3700 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3704 size
= bfd_get_section_size (sect
);
3705 contents
= (gdb_byte
*) xmalloc (size
);
3706 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3712 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3718 char name[name_len rounded up to 4-byte alignment];
3719 char data[data_len];
3722 Technically, there's only supposed to be one such structure in a
3723 given apuinfo section, but the linker is not always vigilant about
3724 merging apuinfo sections from input files. Just go ahead and parse
3725 them all, exiting early when we discover the binary uses SPE
3728 It's not specified in what endianness the information in this
3729 section is stored. Assume that it's the endianness of the BFD. */
3733 unsigned int name_len
;
3734 unsigned int data_len
;
3737 /* If we can't read the first three fields, we're done. */
3741 name_len
= bfd_get_32 (abfd
, ptr
);
3742 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3743 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3744 type
= bfd_get_32 (abfd
, ptr
+ 8);
3747 /* The name must be "APUinfo\0". */
3749 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3753 /* The type must be 2. */
3757 /* The data is stored as a series of uint32. The upper half of
3758 each uint32 indicates the particular APU used and the lower
3759 half indicates the revision of that APU. We just care about
3762 /* Not 4-byte quantities. */
3768 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3769 unsigned int apu
= apuinfo
>> 16;
3773 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3775 if (apu
== 0x100 || apu
== 0x101)
3790 /* These are macros for parsing instruction fields (I.1.6.28) */
3792 #define PPC_FIELD(value, from, len) \
3793 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3794 #define PPC_SEXT(v, bs) \
3795 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3796 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3797 - ((CORE_ADDR) 1 << ((bs) - 1)))
3798 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3799 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3800 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3801 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3802 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3803 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3804 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3805 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3806 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3807 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3808 | (PPC_FIELD (insn, 16, 5) << 5))
3809 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3810 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3811 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3812 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3813 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3814 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3815 #define PPC_OE(insn) PPC_BIT (insn, 21)
3816 #define PPC_RC(insn) PPC_BIT (insn, 31)
3817 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3818 #define PPC_LK(insn) PPC_BIT (insn, 31)
3819 #define PPC_TX(insn) PPC_BIT (insn, 31)
3820 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3822 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3823 #define PPC_XER_NB(xer) (xer & 0x7f)
3825 /* Record Vector-Scalar Registers.
3826 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3827 Otherwise, it's just a VR register. Record them accordingly. */
3830 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3832 if (vsr
< 0 || vsr
>= 64)
3837 if (tdep
->ppc_vr0_regnum
>= 0)
3838 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3842 if (tdep
->ppc_fp0_regnum
>= 0)
3843 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3844 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3845 record_full_arch_list_add_reg (regcache
,
3846 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3852 /* Parse and record instructions primary opcode-4 at ADDR.
3853 Return 0 if successful. */
3856 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3857 CORE_ADDR addr
, uint32_t insn
)
3859 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3860 int ext
= PPC_FIELD (insn
, 21, 11);
3861 int vra
= PPC_FIELD (insn
, 11, 5);
3865 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3866 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3867 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3868 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3869 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3871 case 42: /* Vector Select */
3872 case 43: /* Vector Permute */
3873 case 59: /* Vector Permute Right-indexed */
3874 case 44: /* Vector Shift Left Double by Octet Immediate */
3875 case 45: /* Vector Permute and Exclusive-OR */
3876 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3877 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3878 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3879 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3880 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3881 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3882 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3883 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3884 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3885 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3886 case 46: /* Vector Multiply-Add Single-Precision */
3887 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3888 record_full_arch_list_add_reg (regcache
,
3889 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3892 case 48: /* Multiply-Add High Doubleword */
3893 case 49: /* Multiply-Add High Doubleword Unsigned */
3894 case 51: /* Multiply-Add Low Doubleword */
3895 record_full_arch_list_add_reg (regcache
,
3896 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3900 switch ((ext
& 0x1ff))
3903 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
3904 && vra
!= 2 /* Decimal Convert From Signed Quadword */
3905 && vra
!= 4 /* Decimal Convert To Zoned */
3906 && vra
!= 5 /* Decimal Convert To National */
3907 && vra
!= 6 /* Decimal Convert From Zoned */
3908 && vra
!= 7 /* Decimal Convert From National */
3909 && vra
!= 31) /* Decimal Set Sign */
3911 /* 5.16 Decimal Integer Arithmetic Instructions */
3912 case 1: /* Decimal Add Modulo */
3913 case 65: /* Decimal Subtract Modulo */
3915 case 193: /* Decimal Shift */
3916 case 129: /* Decimal Unsigned Shift */
3917 case 449: /* Decimal Shift and Round */
3919 case 257: /* Decimal Truncate */
3920 case 321: /* Decimal Unsigned Truncate */
3922 /* Bit-21 should be set. */
3923 if (!PPC_BIT (insn
, 21))
3926 record_full_arch_list_add_reg (regcache
,
3927 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3928 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3932 /* Bit-21 is used for RC */
3933 switch (ext
& 0x3ff)
3935 case 6: /* Vector Compare Equal To Unsigned Byte */
3936 case 70: /* Vector Compare Equal To Unsigned Halfword */
3937 case 134: /* Vector Compare Equal To Unsigned Word */
3938 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3939 case 774: /* Vector Compare Greater Than Signed Byte */
3940 case 838: /* Vector Compare Greater Than Signed Halfword */
3941 case 902: /* Vector Compare Greater Than Signed Word */
3942 case 967: /* Vector Compare Greater Than Signed Doubleword */
3943 case 518: /* Vector Compare Greater Than Unsigned Byte */
3944 case 646: /* Vector Compare Greater Than Unsigned Word */
3945 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3946 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3947 case 966: /* Vector Compare Bounds Single-Precision */
3948 case 198: /* Vector Compare Equal To Single-Precision */
3949 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3950 case 710: /* Vector Compare Greater Than Single-Precision */
3951 case 7: /* Vector Compare Not Equal Byte */
3952 case 71: /* Vector Compare Not Equal Halfword */
3953 case 135: /* Vector Compare Not Equal Word */
3954 case 263: /* Vector Compare Not Equal or Zero Byte */
3955 case 327: /* Vector Compare Not Equal or Zero Halfword */
3956 case 391: /* Vector Compare Not Equal or Zero Word */
3958 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3959 record_full_arch_list_add_reg (regcache
,
3960 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3968 case 0: /* Vector Count Leading Zero Least-Significant Bits
3970 case 1: /* Vector Count Trailing Zero Least-Significant Bits
3972 record_full_arch_list_add_reg (regcache
,
3973 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3976 case 6: /* Vector Negate Word */
3977 case 7: /* Vector Negate Doubleword */
3978 case 8: /* Vector Parity Byte Word */
3979 case 9: /* Vector Parity Byte Doubleword */
3980 case 10: /* Vector Parity Byte Quadword */
3981 case 16: /* Vector Extend Sign Byte To Word */
3982 case 17: /* Vector Extend Sign Halfword To Word */
3983 case 24: /* Vector Extend Sign Byte To Doubleword */
3984 case 25: /* Vector Extend Sign Halfword To Doubleword */
3985 case 26: /* Vector Extend Sign Word To Doubleword */
3986 case 28: /* Vector Count Trailing Zeros Byte */
3987 case 29: /* Vector Count Trailing Zeros Halfword */
3988 case 30: /* Vector Count Trailing Zeros Word */
3989 case 31: /* Vector Count Trailing Zeros Doubleword */
3990 record_full_arch_list_add_reg (regcache
,
3991 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3998 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
3999 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4000 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4001 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4002 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4003 case 462: /* Vector Pack Signed Word Signed Saturate */
4004 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4005 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4006 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4007 case 512: /* Vector Add Unsigned Byte Saturate */
4008 case 576: /* Vector Add Unsigned Halfword Saturate */
4009 case 640: /* Vector Add Unsigned Word Saturate */
4010 case 768: /* Vector Add Signed Byte Saturate */
4011 case 832: /* Vector Add Signed Halfword Saturate */
4012 case 896: /* Vector Add Signed Word Saturate */
4013 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4014 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4015 case 1664: /* Vector Subtract Unsigned Word Saturate */
4016 case 1792: /* Vector Subtract Signed Byte Saturate */
4017 case 1856: /* Vector Subtract Signed Halfword Saturate */
4018 case 1920: /* Vector Subtract Signed Word Saturate */
4020 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4021 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4022 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4023 case 1672: /* Vector Sum across Half Signed Word Saturate */
4024 case 1928: /* Vector Sum across Signed Word Saturate */
4025 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4026 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4027 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4029 case 12: /* Vector Merge High Byte */
4030 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4031 case 76: /* Vector Merge High Halfword */
4032 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4033 case 140: /* Vector Merge High Word */
4034 case 268: /* Vector Merge Low Byte */
4035 case 332: /* Vector Merge Low Halfword */
4036 case 396: /* Vector Merge Low Word */
4037 case 526: /* Vector Unpack High Signed Byte */
4038 case 590: /* Vector Unpack High Signed Halfword */
4039 case 654: /* Vector Unpack Low Signed Byte */
4040 case 718: /* Vector Unpack Low Signed Halfword */
4041 case 782: /* Vector Pack Pixel */
4042 case 846: /* Vector Unpack High Pixel */
4043 case 974: /* Vector Unpack Low Pixel */
4044 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4045 case 1614: /* Vector Unpack High Signed Word */
4046 case 1676: /* Vector Merge Odd Word */
4047 case 1742: /* Vector Unpack Low Signed Word */
4048 case 1932: /* Vector Merge Even Word */
4049 case 524: /* Vector Splat Byte */
4050 case 588: /* Vector Splat Halfword */
4051 case 652: /* Vector Splat Word */
4052 case 780: /* Vector Splat Immediate Signed Byte */
4053 case 844: /* Vector Splat Immediate Signed Halfword */
4054 case 908: /* Vector Splat Immediate Signed Word */
4055 case 452: /* Vector Shift Left */
4056 case 708: /* Vector Shift Right */
4057 case 1036: /* Vector Shift Left by Octet */
4058 case 1100: /* Vector Shift Right by Octet */
4059 case 0: /* Vector Add Unsigned Byte Modulo */
4060 case 64: /* Vector Add Unsigned Halfword Modulo */
4061 case 128: /* Vector Add Unsigned Word Modulo */
4062 case 192: /* Vector Add Unsigned Doubleword Modulo */
4063 case 256: /* Vector Add Unsigned Quadword Modulo */
4064 case 320: /* Vector Add & write Carry Unsigned Quadword */
4065 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4066 case 8: /* Vector Multiply Odd Unsigned Byte */
4067 case 72: /* Vector Multiply Odd Unsigned Halfword */
4068 case 136: /* Vector Multiply Odd Unsigned Word */
4069 case 264: /* Vector Multiply Odd Signed Byte */
4070 case 328: /* Vector Multiply Odd Signed Halfword */
4071 case 392: /* Vector Multiply Odd Signed Word */
4072 case 520: /* Vector Multiply Even Unsigned Byte */
4073 case 584: /* Vector Multiply Even Unsigned Halfword */
4074 case 648: /* Vector Multiply Even Unsigned Word */
4075 case 776: /* Vector Multiply Even Signed Byte */
4076 case 840: /* Vector Multiply Even Signed Halfword */
4077 case 904: /* Vector Multiply Even Signed Word */
4078 case 137: /* Vector Multiply Unsigned Word Modulo */
4079 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4080 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4081 case 1152: /* Vector Subtract Unsigned Word Modulo */
4082 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4083 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4084 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4085 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4086 case 1282: /* Vector Average Signed Byte */
4087 case 1346: /* Vector Average Signed Halfword */
4088 case 1410: /* Vector Average Signed Word */
4089 case 1026: /* Vector Average Unsigned Byte */
4090 case 1090: /* Vector Average Unsigned Halfword */
4091 case 1154: /* Vector Average Unsigned Word */
4092 case 258: /* Vector Maximum Signed Byte */
4093 case 322: /* Vector Maximum Signed Halfword */
4094 case 386: /* Vector Maximum Signed Word */
4095 case 450: /* Vector Maximum Signed Doubleword */
4096 case 2: /* Vector Maximum Unsigned Byte */
4097 case 66: /* Vector Maximum Unsigned Halfword */
4098 case 130: /* Vector Maximum Unsigned Word */
4099 case 194: /* Vector Maximum Unsigned Doubleword */
4100 case 770: /* Vector Minimum Signed Byte */
4101 case 834: /* Vector Minimum Signed Halfword */
4102 case 898: /* Vector Minimum Signed Word */
4103 case 962: /* Vector Minimum Signed Doubleword */
4104 case 514: /* Vector Minimum Unsigned Byte */
4105 case 578: /* Vector Minimum Unsigned Halfword */
4106 case 642: /* Vector Minimum Unsigned Word */
4107 case 706: /* Vector Minimum Unsigned Doubleword */
4108 case 1028: /* Vector Logical AND */
4109 case 1668: /* Vector Logical Equivalent */
4110 case 1092: /* Vector Logical AND with Complement */
4111 case 1412: /* Vector Logical NAND */
4112 case 1348: /* Vector Logical OR with Complement */
4113 case 1156: /* Vector Logical OR */
4114 case 1284: /* Vector Logical NOR */
4115 case 1220: /* Vector Logical XOR */
4116 case 4: /* Vector Rotate Left Byte */
4117 case 132: /* Vector Rotate Left Word VX-form */
4118 case 68: /* Vector Rotate Left Halfword */
4119 case 196: /* Vector Rotate Left Doubleword */
4120 case 260: /* Vector Shift Left Byte */
4121 case 388: /* Vector Shift Left Word */
4122 case 324: /* Vector Shift Left Halfword */
4123 case 1476: /* Vector Shift Left Doubleword */
4124 case 516: /* Vector Shift Right Byte */
4125 case 644: /* Vector Shift Right Word */
4126 case 580: /* Vector Shift Right Halfword */
4127 case 1732: /* Vector Shift Right Doubleword */
4128 case 772: /* Vector Shift Right Algebraic Byte */
4129 case 900: /* Vector Shift Right Algebraic Word */
4130 case 836: /* Vector Shift Right Algebraic Halfword */
4131 case 964: /* Vector Shift Right Algebraic Doubleword */
4132 case 10: /* Vector Add Single-Precision */
4133 case 74: /* Vector Subtract Single-Precision */
4134 case 1034: /* Vector Maximum Single-Precision */
4135 case 1098: /* Vector Minimum Single-Precision */
4136 case 842: /* Vector Convert From Signed Fixed-Point Word */
4137 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4138 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4139 case 522: /* Vector Round to Single-Precision Integer Nearest */
4140 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4141 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4142 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4143 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4144 case 266: /* Vector Reciprocal Estimate Single-Precision */
4145 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4146 case 1288: /* Vector AES Cipher */
4147 case 1289: /* Vector AES Cipher Last */
4148 case 1352: /* Vector AES Inverse Cipher */
4149 case 1353: /* Vector AES Inverse Cipher Last */
4150 case 1480: /* Vector AES SubBytes */
4151 case 1730: /* Vector SHA-512 Sigma Doubleword */
4152 case 1666: /* Vector SHA-256 Sigma Word */
4153 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4154 case 1160: /* Vector Polynomial Multiply-Sum Word */
4155 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4156 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4157 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4158 case 1794: /* Vector Count Leading Zeros Byte */
4159 case 1858: /* Vector Count Leading Zeros Halfword */
4160 case 1922: /* Vector Count Leading Zeros Word */
4161 case 1986: /* Vector Count Leading Zeros Doubleword */
4162 case 1795: /* Vector Population Count Byte */
4163 case 1859: /* Vector Population Count Halfword */
4164 case 1923: /* Vector Population Count Word */
4165 case 1987: /* Vector Population Count Doubleword */
4166 case 1356: /* Vector Bit Permute Quadword */
4167 case 1484: /* Vector Bit Permute Doubleword */
4168 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4169 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4171 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4172 case 65: /* Vector Multiply-by-10 Extended & write Carry
4173 Unsigned Quadword */
4174 case 1027: /* Vector Absolute Difference Unsigned Byte */
4175 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4176 case 1155: /* Vector Absolute Difference Unsigned Word */
4177 case 1796: /* Vector Shift Right Variable */
4178 case 1860: /* Vector Shift Left Variable */
4179 case 133: /* Vector Rotate Left Word then Mask Insert */
4180 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4181 case 389: /* Vector Rotate Left Word then AND with Mask */
4182 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4183 case 525: /* Vector Extract Unsigned Byte */
4184 case 589: /* Vector Extract Unsigned Halfword */
4185 case 653: /* Vector Extract Unsigned Word */
4186 case 717: /* Vector Extract Doubleword */
4187 case 781: /* Vector Insert Byte */
4188 case 845: /* Vector Insert Halfword */
4189 case 909: /* Vector Insert Word */
4190 case 973: /* Vector Insert Doubleword */
4191 record_full_arch_list_add_reg (regcache
,
4192 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4195 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4196 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4197 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4198 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4199 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4200 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4201 record_full_arch_list_add_reg (regcache
,
4202 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4205 case 1604: /* Move To Vector Status and Control Register */
4206 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4208 case 1540: /* Move From Vector Status and Control Register */
4209 record_full_arch_list_add_reg (regcache
,
4210 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4212 case 833: /* Decimal Copy Sign */
4213 record_full_arch_list_add_reg (regcache
,
4214 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4215 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4219 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4220 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4224 /* Parse and record instructions of primary opcode-19 at ADDR.
4225 Return 0 if successful. */
4228 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4229 CORE_ADDR addr
, uint32_t insn
)
4231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4232 int ext
= PPC_EXTOP (insn
);
4234 switch (ext
& 0x01f)
4236 case 2: /* Add PC Immediate Shifted */
4237 record_full_arch_list_add_reg (regcache
,
4238 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4244 case 0: /* Move Condition Register Field */
4245 case 33: /* Condition Register NOR */
4246 case 129: /* Condition Register AND with Complement */
4247 case 193: /* Condition Register XOR */
4248 case 225: /* Condition Register NAND */
4249 case 257: /* Condition Register AND */
4250 case 289: /* Condition Register Equivalent */
4251 case 417: /* Condition Register OR with Complement */
4252 case 449: /* Condition Register OR */
4253 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4256 case 16: /* Branch Conditional */
4257 case 560: /* Branch Conditional to Branch Target Address Register */
4258 if ((PPC_BO (insn
) & 0x4) == 0)
4259 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4261 case 528: /* Branch Conditional to Count Register */
4263 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4266 case 150: /* Instruction Synchronize */
4271 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4272 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4276 /* Parse and record instructions of primary opcode-31 at ADDR.
4277 Return 0 if successful. */
4280 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4281 CORE_ADDR addr
, uint32_t insn
)
4283 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4284 int ext
= PPC_EXTOP (insn
);
4286 CORE_ADDR at_dcsz
, ea
= 0;
4287 ULONGEST rb
, ra
, xer
;
4290 /* These instructions have OE bit. */
4291 switch (ext
& 0x1ff)
4293 /* These write RT and XER. Update CR if RC is set. */
4294 case 8: /* Subtract from carrying */
4295 case 10: /* Add carrying */
4296 case 136: /* Subtract from extended */
4297 case 138: /* Add extended */
4298 case 200: /* Subtract from zero extended */
4299 case 202: /* Add to zero extended */
4300 case 232: /* Subtract from minus one extended */
4301 case 234: /* Add to minus one extended */
4302 /* CA is always altered, but SO/OV are only altered when OE=1.
4303 In any case, XER is always altered. */
4304 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4306 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4307 record_full_arch_list_add_reg (regcache
,
4308 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4311 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4312 case 40: /* Subtract from */
4313 case 104: /* Negate */
4314 case 233: /* Multiply low doubleword */
4315 case 235: /* Multiply low word */
4317 case 393: /* Divide Doubleword Extended Unsigned */
4318 case 395: /* Divide Word Extended Unsigned */
4319 case 425: /* Divide Doubleword Extended */
4320 case 427: /* Divide Word Extended */
4321 case 457: /* Divide Doubleword Unsigned */
4322 case 459: /* Divide Word Unsigned */
4323 case 489: /* Divide Doubleword */
4324 case 491: /* Divide Word */
4326 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4328 case 9: /* Multiply High Doubleword Unsigned */
4329 case 11: /* Multiply High Word Unsigned */
4330 case 73: /* Multiply High Doubleword */
4331 case 75: /* Multiply High Word */
4333 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4334 record_full_arch_list_add_reg (regcache
,
4335 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4339 if ((ext
& 0x1f) == 15)
4341 /* Integer Select. bit[16:20] is used for BC. */
4342 record_full_arch_list_add_reg (regcache
,
4343 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4347 if ((ext
& 0xff) == 170)
4349 /* Add Extended using alternate carry bits */
4350 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4351 record_full_arch_list_add_reg (regcache
,
4352 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4358 case 78: /* Determine Leftmost Zero Byte */
4360 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4361 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4362 record_full_arch_list_add_reg (regcache
,
4363 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4366 /* These only write RT. */
4367 case 19: /* Move from condition register */
4368 /* Move From One Condition Register Field */
4369 case 74: /* Add and Generate Sixes */
4370 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4371 case 302: /* Move From Branch History Rolling Buffer */
4372 case 339: /* Move From Special Purpose Register */
4373 case 371: /* Move From Time Base [Phased-Out] */
4374 case 309: /* Load Doubleword Monitored Indexed */
4375 case 128: /* Set Boolean */
4376 case 755: /* Deliver A Random Number */
4377 record_full_arch_list_add_reg (regcache
,
4378 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4381 /* These only write to RA. */
4382 case 51: /* Move From VSR Doubleword */
4383 case 115: /* Move From VSR Word and Zero */
4384 case 122: /* Population count bytes */
4385 case 378: /* Population count words */
4386 case 506: /* Population count doublewords */
4387 case 154: /* Parity Word */
4388 case 186: /* Parity Doubleword */
4389 case 252: /* Bit Permute Doubleword */
4390 case 282: /* Convert Declets To Binary Coded Decimal */
4391 case 314: /* Convert Binary Coded Decimal To Declets */
4392 case 508: /* Compare bytes */
4393 case 307: /* Move From VSR Lower Doubleword */
4394 record_full_arch_list_add_reg (regcache
,
4395 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4398 /* These write CR and optional RA. */
4399 case 792: /* Shift Right Algebraic Word */
4400 case 794: /* Shift Right Algebraic Doubleword */
4401 case 824: /* Shift Right Algebraic Word Immediate */
4402 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4403 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4404 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4405 record_full_arch_list_add_reg (regcache
,
4406 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4408 case 0: /* Compare */
4409 case 32: /* Compare logical */
4410 case 144: /* Move To Condition Register Fields */
4411 /* Move To One Condition Register Field */
4412 case 192: /* Compare Ranged Byte */
4413 case 224: /* Compare Equal Byte */
4414 case 576: /* Move XER to CR Extended */
4415 case 902: /* Paste (should always fail due to single-stepping and
4416 the memory location might not be accessible, so
4418 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4421 /* These write to RT. Update RA if 'update indexed.' */
4422 case 53: /* Load Doubleword with Update Indexed */
4423 case 119: /* Load Byte and Zero with Update Indexed */
4424 case 311: /* Load Halfword and Zero with Update Indexed */
4425 case 55: /* Load Word and Zero with Update Indexed */
4426 case 375: /* Load Halfword Algebraic with Update Indexed */
4427 case 373: /* Load Word Algebraic with Update Indexed */
4428 record_full_arch_list_add_reg (regcache
,
4429 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4431 case 21: /* Load Doubleword Indexed */
4432 case 52: /* Load Byte And Reserve Indexed */
4433 case 116: /* Load Halfword And Reserve Indexed */
4434 case 20: /* Load Word And Reserve Indexed */
4435 case 84: /* Load Doubleword And Reserve Indexed */
4436 case 87: /* Load Byte and Zero Indexed */
4437 case 279: /* Load Halfword and Zero Indexed */
4438 case 23: /* Load Word and Zero Indexed */
4439 case 343: /* Load Halfword Algebraic Indexed */
4440 case 341: /* Load Word Algebraic Indexed */
4441 case 790: /* Load Halfword Byte-Reverse Indexed */
4442 case 534: /* Load Word Byte-Reverse Indexed */
4443 case 532: /* Load Doubleword Byte-Reverse Indexed */
4444 case 582: /* Load Word Atomic */
4445 case 614: /* Load Doubleword Atomic */
4446 case 265: /* Modulo Unsigned Doubleword */
4447 case 777: /* Modulo Signed Doubleword */
4448 case 267: /* Modulo Unsigned Word */
4449 case 779: /* Modulo Signed Word */
4450 record_full_arch_list_add_reg (regcache
,
4451 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4454 case 597: /* Load String Word Immediate */
4455 case 533: /* Load String Word Indexed */
4464 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4465 nr
= PPC_XER_NB (xer
);
4470 /* If n=0, the contents of register RT are undefined. */
4474 for (i
= 0; i
< nr
; i
++)
4475 record_full_arch_list_add_reg (regcache
,
4476 tdep
->ppc_gp0_regnum
4477 + ((PPC_RT (insn
) + i
) & 0x1f));
4480 case 276: /* Load Quadword And Reserve Indexed */
4481 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4482 record_full_arch_list_add_reg (regcache
, tmp
);
4483 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4486 /* These write VRT. */
4487 case 6: /* Load Vector for Shift Left Indexed */
4488 case 38: /* Load Vector for Shift Right Indexed */
4489 case 7: /* Load Vector Element Byte Indexed */
4490 case 39: /* Load Vector Element Halfword Indexed */
4491 case 71: /* Load Vector Element Word Indexed */
4492 case 103: /* Load Vector Indexed */
4493 case 359: /* Load Vector Indexed LRU */
4494 record_full_arch_list_add_reg (regcache
,
4495 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4498 /* These write FRT. Update RA if 'update indexed.' */
4499 case 567: /* Load Floating-Point Single with Update Indexed */
4500 case 631: /* Load Floating-Point Double with Update Indexed */
4501 record_full_arch_list_add_reg (regcache
,
4502 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4504 case 535: /* Load Floating-Point Single Indexed */
4505 case 599: /* Load Floating-Point Double Indexed */
4506 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4507 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4508 record_full_arch_list_add_reg (regcache
,
4509 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4512 case 791: /* Load Floating-Point Double Pair Indexed */
4513 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4514 record_full_arch_list_add_reg (regcache
, tmp
);
4515 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4518 case 179: /* Move To VSR Doubleword */
4519 case 211: /* Move To VSR Word Algebraic */
4520 case 243: /* Move To VSR Word and Zero */
4521 case 588: /* Load VSX Scalar Doubleword Indexed */
4522 case 524: /* Load VSX Scalar Single-Precision Indexed */
4523 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4524 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4525 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4526 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4527 case 780: /* Load VSX Vector Word*4 Indexed */
4528 case 268: /* Load VSX Vector Indexed */
4529 case 364: /* Load VSX Vector Word & Splat Indexed */
4530 case 812: /* Load VSX Vector Halfword*8 Indexed */
4531 case 876: /* Load VSX Vector Byte*16 Indexed */
4532 case 269: /* Load VSX Vector with Length */
4533 case 301: /* Load VSX Vector Left-justified with Length */
4534 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4535 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4536 case 403: /* Move To VSR Word & Splat */
4537 case 435: /* Move To VSR Double Doubleword */
4538 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4541 /* These write RA. Update CR if RC is set. */
4542 case 24: /* Shift Left Word */
4543 case 26: /* Count Leading Zeros Word */
4544 case 27: /* Shift Left Doubleword */
4546 case 58: /* Count Leading Zeros Doubleword */
4547 case 60: /* AND with Complement */
4549 case 284: /* Equivalent */
4551 case 476: /* NAND */
4552 case 412: /* OR with Complement */
4554 case 536: /* Shift Right Word */
4555 case 539: /* Shift Right Doubleword */
4556 case 922: /* Extend Sign Halfword */
4557 case 954: /* Extend Sign Byte */
4558 case 986: /* Extend Sign Word */
4559 case 538: /* Count Trailing Zeros Word */
4560 case 570: /* Count Trailing Zeros Doubleword */
4561 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4562 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4564 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4565 record_full_arch_list_add_reg (regcache
,
4566 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4570 case 181: /* Store Doubleword with Update Indexed */
4571 case 183: /* Store Word with Update Indexed */
4572 case 247: /* Store Byte with Update Indexed */
4573 case 439: /* Store Half Word with Update Indexed */
4574 case 695: /* Store Floating-Point Single with Update Indexed */
4575 case 759: /* Store Floating-Point Double with Update Indexed */
4576 record_full_arch_list_add_reg (regcache
,
4577 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4579 case 135: /* Store Vector Element Byte Indexed */
4580 case 167: /* Store Vector Element Halfword Indexed */
4581 case 199: /* Store Vector Element Word Indexed */
4582 case 231: /* Store Vector Indexed */
4583 case 487: /* Store Vector Indexed LRU */
4584 case 716: /* Store VSX Scalar Doubleword Indexed */
4585 case 140: /* Store VSX Scalar as Integer Word Indexed */
4586 case 652: /* Store VSX Scalar Single-Precision Indexed */
4587 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4588 case 908: /* Store VSX Vector Word*4 Indexed */
4589 case 149: /* Store Doubleword Indexed */
4590 case 151: /* Store Word Indexed */
4591 case 215: /* Store Byte Indexed */
4592 case 407: /* Store Half Word Indexed */
4593 case 694: /* Store Byte Conditional Indexed */
4594 case 726: /* Store Halfword Conditional Indexed */
4595 case 150: /* Store Word Conditional Indexed */
4596 case 214: /* Store Doubleword Conditional Indexed */
4597 case 182: /* Store Quadword Conditional Indexed */
4598 case 662: /* Store Word Byte-Reverse Indexed */
4599 case 918: /* Store Halfword Byte-Reverse Indexed */
4600 case 660: /* Store Doubleword Byte-Reverse Indexed */
4601 case 663: /* Store Floating-Point Single Indexed */
4602 case 727: /* Store Floating-Point Double Indexed */
4603 case 919: /* Store Floating-Point Double Pair Indexed */
4604 case 983: /* Store Floating-Point as Integer Word Indexed */
4605 case 396: /* Store VSX Vector Indexed */
4606 case 940: /* Store VSX Vector Halfword*8 Indexed */
4607 case 1004: /* Store VSX Vector Byte*16 Indexed */
4608 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4609 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4610 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4611 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4614 if (PPC_RA (insn
) != 0)
4615 regcache_raw_read_unsigned (regcache
,
4616 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4617 regcache_raw_read_unsigned (regcache
,
4618 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4623 case 183: /* Store Word with Update Indexed */
4624 case 199: /* Store Vector Element Word Indexed */
4625 case 140: /* Store VSX Scalar as Integer Word Indexed */
4626 case 652: /* Store VSX Scalar Single-Precision Indexed */
4627 case 151: /* Store Word Indexed */
4628 case 150: /* Store Word Conditional Indexed */
4629 case 662: /* Store Word Byte-Reverse Indexed */
4630 case 663: /* Store Floating-Point Single Indexed */
4631 case 695: /* Store Floating-Point Single with Update Indexed */
4632 case 983: /* Store Floating-Point as Integer Word Indexed */
4635 case 247: /* Store Byte with Update Indexed */
4636 case 135: /* Store Vector Element Byte Indexed */
4637 case 215: /* Store Byte Indexed */
4638 case 694: /* Store Byte Conditional Indexed */
4639 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4642 case 439: /* Store Halfword with Update Indexed */
4643 case 167: /* Store Vector Element Halfword Indexed */
4644 case 407: /* Store Halfword Indexed */
4645 case 726: /* Store Halfword Conditional Indexed */
4646 case 918: /* Store Halfword Byte-Reverse Indexed */
4647 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4650 case 181: /* Store Doubleword with Update Indexed */
4651 case 716: /* Store VSX Scalar Doubleword Indexed */
4652 case 149: /* Store Doubleword Indexed */
4653 case 214: /* Store Doubleword Conditional Indexed */
4654 case 660: /* Store Doubleword Byte-Reverse Indexed */
4655 case 727: /* Store Floating-Point Double Indexed */
4656 case 759: /* Store Floating-Point Double with Update Indexed */
4659 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4660 case 908: /* Store VSX Vector Word*4 Indexed */
4661 case 182: /* Store Quadword Conditional Indexed */
4662 case 231: /* Store Vector Indexed */
4663 case 487: /* Store Vector Indexed LRU */
4664 case 919: /* Store Floating-Point Double Pair Indexed */
4665 case 396: /* Store VSX Vector Indexed */
4666 case 940: /* Store VSX Vector Halfword*8 Indexed */
4667 case 1004: /* Store VSX Vector Byte*16 Indexed */
4674 /* Align address for Store Vector instructions. */
4677 case 167: /* Store Vector Element Halfword Indexed */
4678 addr
= addr
& ~0x1ULL
;
4681 case 199: /* Store Vector Element Word Indexed */
4682 addr
= addr
& ~0x3ULL
;
4685 case 231: /* Store Vector Indexed */
4686 case 487: /* Store Vector Indexed LRU */
4687 addr
= addr
& ~0xfULL
;
4691 record_full_arch_list_add_mem (addr
, size
);
4694 case 397: /* Store VSX Vector with Length */
4695 case 429: /* Store VSX Vector Left-justified with Length */
4697 if (PPC_RA (insn
) != 0)
4698 regcache_raw_read_unsigned (regcache
,
4699 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4701 regcache_raw_read_unsigned (regcache
,
4702 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4703 /* Store up to 16 bytes. */
4704 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4706 record_full_arch_list_add_mem (ea
, nb
);
4709 case 710: /* Store Word Atomic */
4710 case 742: /* Store Doubleword Atomic */
4712 if (PPC_RA (insn
) != 0)
4713 regcache_raw_read_unsigned (regcache
,
4714 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4718 case 710: /* Store Word Atomic */
4721 case 742: /* Store Doubleword Atomic */
4727 record_full_arch_list_add_mem (ea
, size
);
4730 case 725: /* Store String Word Immediate */
4732 if (PPC_RA (insn
) != 0)
4733 regcache_raw_read_unsigned (regcache
,
4734 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4741 record_full_arch_list_add_mem (ea
, nb
);
4745 case 661: /* Store String Word Indexed */
4747 if (PPC_RA (insn
) != 0)
4748 regcache_raw_read_unsigned (regcache
,
4749 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4752 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4753 nb
= PPC_XER_NB (xer
);
4757 regcache_raw_read_unsigned (regcache
,
4758 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4761 record_full_arch_list_add_mem (ea
, nb
);
4766 case 467: /* Move To Special Purpose Register */
4767 switch (PPC_SPR (insn
))
4770 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4773 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4776 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4778 case 256: /* VRSAVE */
4779 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4785 case 147: /* Move To Split Little Endian */
4786 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4789 case 512: /* Move to Condition Register from XER */
4790 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4791 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4794 case 4: /* Trap Word */
4795 case 68: /* Trap Doubleword */
4796 case 430: /* Clear BHRB */
4797 case 598: /* Synchronize */
4798 case 62: /* Wait for Interrupt */
4800 case 22: /* Instruction Cache Block Touch */
4801 case 854: /* Enforce In-order Execution of I/O */
4802 case 246: /* Data Cache Block Touch for Store */
4803 case 54: /* Data Cache Block Store */
4804 case 86: /* Data Cache Block Flush */
4805 case 278: /* Data Cache Block Touch */
4806 case 758: /* Data Cache Block Allocate */
4807 case 982: /* Instruction Cache Block Invalidate */
4808 case 774: /* Copy */
4809 case 838: /* CP_Abort */
4812 case 654: /* Transaction Begin */
4813 case 686: /* Transaction End */
4814 case 750: /* Transaction Suspend or Resume */
4815 case 782: /* Transaction Abort Word Conditional */
4816 case 814: /* Transaction Abort Doubleword Conditional */
4817 case 846: /* Transaction Abort Word Conditional Immediate */
4818 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4819 case 910: /* Transaction Abort */
4820 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4822 case 718: /* Transaction Check */
4823 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4826 case 1014: /* Data Cache Block set to Zero */
4827 if (target_auxv_search (¤t_target
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4829 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4832 if (PPC_RA (insn
) != 0)
4833 regcache_raw_read_unsigned (regcache
,
4834 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4835 regcache_raw_read_unsigned (regcache
,
4836 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4837 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4838 record_full_arch_list_add_mem (ea
, at_dcsz
);
4843 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4844 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4848 /* Parse and record instructions of primary opcode-59 at ADDR.
4849 Return 0 if successful. */
4852 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4853 CORE_ADDR addr
, uint32_t insn
)
4855 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4856 int ext
= PPC_EXTOP (insn
);
4860 case 18: /* Floating Divide */
4861 case 20: /* Floating Subtract */
4862 case 21: /* Floating Add */
4863 case 22: /* Floating Square Root */
4864 case 24: /* Floating Reciprocal Estimate */
4865 case 25: /* Floating Multiply */
4866 case 26: /* Floating Reciprocal Square Root Estimate */
4867 case 28: /* Floating Multiply-Subtract */
4868 case 29: /* Floating Multiply-Add */
4869 case 30: /* Floating Negative Multiply-Subtract */
4870 case 31: /* Floating Negative Multiply-Add */
4871 record_full_arch_list_add_reg (regcache
,
4872 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4874 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4875 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4882 case 2: /* DFP Add */
4883 case 3: /* DFP Quantize */
4884 case 34: /* DFP Multiply */
4885 case 35: /* DFP Reround */
4886 case 67: /* DFP Quantize Immediate */
4887 case 99: /* DFP Round To FP Integer With Inexact */
4888 case 227: /* DFP Round To FP Integer Without Inexact */
4889 case 258: /* DFP Convert To DFP Long! */
4890 case 290: /* DFP Convert To Fixed */
4891 case 514: /* DFP Subtract */
4892 case 546: /* DFP Divide */
4893 case 770: /* DFP Round To DFP Short! */
4894 case 802: /* DFP Convert From Fixed */
4895 case 834: /* DFP Encode BCD To DPD */
4897 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4898 record_full_arch_list_add_reg (regcache
,
4899 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4900 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4903 case 130: /* DFP Compare Ordered */
4904 case 162: /* DFP Test Exponent */
4905 case 194: /* DFP Test Data Class */
4906 case 226: /* DFP Test Data Group */
4907 case 642: /* DFP Compare Unordered */
4908 case 674: /* DFP Test Significance */
4909 case 675: /* DFP Test Significance Immediate */
4910 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4911 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4914 case 66: /* DFP Shift Significand Left Immediate */
4915 case 98: /* DFP Shift Significand Right Immediate */
4916 case 322: /* DFP Decode DPD To BCD */
4917 case 354: /* DFP Extract Biased Exponent */
4918 case 866: /* DFP Insert Biased Exponent */
4919 record_full_arch_list_add_reg (regcache
,
4920 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4922 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4925 case 846: /* Floating Convert From Integer Doubleword Single */
4926 case 974: /* Floating Convert From Integer Doubleword Unsigned
4928 record_full_arch_list_add_reg (regcache
,
4929 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4931 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4932 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4937 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4938 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4942 /* Parse and record instructions of primary opcode-60 at ADDR.
4943 Return 0 if successful. */
4946 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4947 CORE_ADDR addr
, uint32_t insn
)
4949 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4950 int ext
= PPC_EXTOP (insn
);
4954 case 0: /* VSX Scalar Add Single-Precision */
4955 case 32: /* VSX Scalar Add Double-Precision */
4956 case 24: /* VSX Scalar Divide Single-Precision */
4957 case 56: /* VSX Scalar Divide Double-Precision */
4958 case 176: /* VSX Scalar Copy Sign Double-Precision */
4959 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4960 case 41: /* ditto */
4961 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4963 case 160: /* VSX Scalar Maximum Double-Precision */
4964 case 168: /* VSX Scalar Minimum Double-Precision */
4965 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4966 case 57: /* ditto */
4967 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4968 case 25: /* ditto */
4969 case 48: /* VSX Scalar Multiply Double-Precision */
4970 case 16: /* VSX Scalar Multiply Single-Precision */
4971 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4972 case 169: /* ditto */
4973 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4974 case 137: /* ditto */
4975 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4976 case 185: /* ditto */
4977 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4978 case 153: /* ditto */
4979 case 40: /* VSX Scalar Subtract Double-Precision */
4980 case 8: /* VSX Scalar Subtract Single-Precision */
4981 case 96: /* VSX Vector Add Double-Precision */
4982 case 64: /* VSX Vector Add Single-Precision */
4983 case 120: /* VSX Vector Divide Double-Precision */
4984 case 88: /* VSX Vector Divide Single-Precision */
4985 case 97: /* VSX Vector Multiply-Add Double-Precision */
4986 case 105: /* ditto */
4987 case 65: /* VSX Vector Multiply-Add Single-Precision */
4988 case 73: /* ditto */
4989 case 224: /* VSX Vector Maximum Double-Precision */
4990 case 192: /* VSX Vector Maximum Single-Precision */
4991 case 232: /* VSX Vector Minimum Double-Precision */
4992 case 200: /* VSX Vector Minimum Single-Precision */
4993 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
4994 case 121: /* ditto */
4995 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
4996 case 89: /* ditto */
4997 case 112: /* VSX Vector Multiply Double-Precision */
4998 case 80: /* VSX Vector Multiply Single-Precision */
4999 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5000 case 233: /* ditto */
5001 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5002 case 201: /* ditto */
5003 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5004 case 249: /* ditto */
5005 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5006 case 217: /* ditto */
5007 case 104: /* VSX Vector Subtract Double-Precision */
5008 case 72: /* VSX Vector Subtract Single-Precision */
5009 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5010 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5011 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5012 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5013 case 3: /* VSX Scalar Compare Equal Double-Precision */
5014 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5015 case 19: /* VSX Scalar Compare Greater Than or Equal
5017 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5019 case 240: /* VSX Vector Copy Sign Double-Precision */
5020 case 208: /* VSX Vector Copy Sign Single-Precision */
5021 case 130: /* VSX Logical AND */
5022 case 138: /* VSX Logical AND with Complement */
5023 case 186: /* VSX Logical Equivalence */
5024 case 178: /* VSX Logical NAND */
5025 case 170: /* VSX Logical OR with Complement */
5026 case 162: /* VSX Logical NOR */
5027 case 146: /* VSX Logical OR */
5028 case 154: /* VSX Logical XOR */
5029 case 18: /* VSX Merge High Word */
5030 case 50: /* VSX Merge Low Word */
5031 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5032 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5033 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5034 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5035 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5036 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5037 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5038 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5039 case 216: /* VSX Vector Insert Exponent Single-Precision */
5040 case 248: /* VSX Vector Insert Exponent Double-Precision */
5041 case 26: /* VSX Vector Permute */
5042 case 58: /* VSX Vector Permute Right-indexed */
5043 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5044 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5045 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5046 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5047 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5050 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5051 case 125: /* VSX Vector Test for software Divide Double-Precision */
5052 case 93: /* VSX Vector Test for software Divide Single-Precision */
5053 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5056 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5057 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5058 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5059 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5060 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5064 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5066 case 99: /* VSX Vector Compare Equal To Double-Precision */
5067 case 67: /* VSX Vector Compare Equal To Single-Precision */
5068 case 115: /* VSX Vector Compare Greater Than or
5069 Equal To Double-Precision */
5070 case 83: /* VSX Vector Compare Greater Than or
5071 Equal To Single-Precision */
5072 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5073 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5075 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5076 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5077 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5083 case 265: /* VSX Scalar round Double-Precision to
5084 Single-Precision and Convert to
5085 Single-Precision format */
5086 case 344: /* VSX Scalar truncate Double-Precision to
5087 Integer and Convert to Signed Integer
5088 Doubleword format with Saturate */
5089 case 88: /* VSX Scalar truncate Double-Precision to
5090 Integer and Convert to Signed Integer Word
5091 Format with Saturate */
5092 case 328: /* VSX Scalar truncate Double-Precision integer
5093 and Convert to Unsigned Integer Doubleword
5094 Format with Saturate */
5095 case 72: /* VSX Scalar truncate Double-Precision to
5096 Integer and Convert to Unsigned Integer Word
5097 Format with Saturate */
5098 case 329: /* VSX Scalar Convert Single-Precision to
5099 Double-Precision format */
5100 case 376: /* VSX Scalar Convert Signed Integer
5101 Doubleword to floating-point format and
5102 Round to Double-Precision format */
5103 case 312: /* VSX Scalar Convert Signed Integer
5104 Doubleword to floating-point format and
5105 round to Single-Precision */
5106 case 360: /* VSX Scalar Convert Unsigned Integer
5107 Doubleword to floating-point format and
5108 Round to Double-Precision format */
5109 case 296: /* VSX Scalar Convert Unsigned Integer
5110 Doubleword to floating-point format and
5111 Round to Single-Precision */
5112 case 73: /* VSX Scalar Round to Double-Precision Integer
5113 Using Round to Nearest Away */
5114 case 107: /* VSX Scalar Round to Double-Precision Integer
5115 Exact using Current rounding mode */
5116 case 121: /* VSX Scalar Round to Double-Precision Integer
5117 Using Round toward -Infinity */
5118 case 105: /* VSX Scalar Round to Double-Precision Integer
5119 Using Round toward +Infinity */
5120 case 89: /* VSX Scalar Round to Double-Precision Integer
5121 Using Round toward Zero */
5122 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5123 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5124 case 281: /* VSX Scalar Round to Single-Precision */
5125 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5127 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5129 case 75: /* VSX Scalar Square Root Double-Precision */
5130 case 11: /* VSX Scalar Square Root Single-Precision */
5131 case 393: /* VSX Vector round Double-Precision to
5132 Single-Precision and Convert to
5133 Single-Precision format */
5134 case 472: /* VSX Vector truncate Double-Precision to
5135 Integer and Convert to Signed Integer
5136 Doubleword format with Saturate */
5137 case 216: /* VSX Vector truncate Double-Precision to
5138 Integer and Convert to Signed Integer Word
5139 Format with Saturate */
5140 case 456: /* VSX Vector truncate Double-Precision to
5141 Integer and Convert to Unsigned Integer
5142 Doubleword format with Saturate */
5143 case 200: /* VSX Vector truncate Double-Precision to
5144 Integer and Convert to Unsigned Integer Word
5145 Format with Saturate */
5146 case 457: /* VSX Vector Convert Single-Precision to
5147 Double-Precision format */
5148 case 408: /* VSX Vector truncate Single-Precision to
5149 Integer and Convert to Signed Integer
5150 Doubleword format with Saturate */
5151 case 152: /* VSX Vector truncate Single-Precision to
5152 Integer and Convert to Signed Integer Word
5153 Format with Saturate */
5154 case 392: /* VSX Vector truncate Single-Precision to
5155 Integer and Convert to Unsigned Integer
5156 Doubleword format with Saturate */
5157 case 136: /* VSX Vector truncate Single-Precision to
5158 Integer and Convert to Unsigned Integer Word
5159 Format with Saturate */
5160 case 504: /* VSX Vector Convert and round Signed Integer
5161 Doubleword to Double-Precision format */
5162 case 440: /* VSX Vector Convert and round Signed Integer
5163 Doubleword to Single-Precision format */
5164 case 248: /* VSX Vector Convert Signed Integer Word to
5165 Double-Precision format */
5166 case 184: /* VSX Vector Convert and round Signed Integer
5167 Word to Single-Precision format */
5168 case 488: /* VSX Vector Convert and round Unsigned
5169 Integer Doubleword to Double-Precision format */
5170 case 424: /* VSX Vector Convert and round Unsigned
5171 Integer Doubleword to Single-Precision format */
5172 case 232: /* VSX Vector Convert and round Unsigned
5173 Integer Word to Double-Precision format */
5174 case 168: /* VSX Vector Convert and round Unsigned
5175 Integer Word to Single-Precision format */
5176 case 201: /* VSX Vector Round to Double-Precision
5177 Integer using round to Nearest Away */
5178 case 235: /* VSX Vector Round to Double-Precision
5179 Integer Exact using Current rounding mode */
5180 case 249: /* VSX Vector Round to Double-Precision
5181 Integer using round toward -Infinity */
5182 case 233: /* VSX Vector Round to Double-Precision
5183 Integer using round toward +Infinity */
5184 case 217: /* VSX Vector Round to Double-Precision
5185 Integer using round toward Zero */
5186 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5187 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5188 case 137: /* VSX Vector Round to Single-Precision Integer
5189 Using Round to Nearest Away */
5190 case 171: /* VSX Vector Round to Single-Precision Integer
5191 Exact Using Current rounding mode */
5192 case 185: /* VSX Vector Round to Single-Precision Integer
5193 Using Round toward -Infinity */
5194 case 169: /* VSX Vector Round to Single-Precision Integer
5195 Using Round toward +Infinity */
5196 case 153: /* VSX Vector Round to Single-Precision Integer
5197 Using round toward Zero */
5198 case 202: /* VSX Vector Reciprocal Square Root Estimate
5200 case 138: /* VSX Vector Reciprocal Square Root Estimate
5202 case 203: /* VSX Vector Square Root Double-Precision */
5203 case 139: /* VSX Vector Square Root Single-Precision */
5204 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5206 case 345: /* VSX Scalar Absolute Value Double-Precision */
5207 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5208 Vector Single-Precision format Non-signalling */
5209 case 331: /* VSX Scalar Convert Single-Precision to
5210 Double-Precision format Non-signalling */
5211 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5212 case 377: /* VSX Scalar Negate Double-Precision */
5213 case 473: /* VSX Vector Absolute Value Double-Precision */
5214 case 409: /* VSX Vector Absolute Value Single-Precision */
5215 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5216 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5217 case 505: /* VSX Vector Negate Double-Precision */
5218 case 441: /* VSX Vector Negate Single-Precision */
5219 case 164: /* VSX Splat Word */
5220 case 165: /* VSX Vector Extract Unsigned Word */
5221 case 181: /* VSX Vector Insert Word */
5222 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5225 case 298: /* VSX Scalar Test Data Class Single-Precision */
5226 case 362: /* VSX Scalar Test Data Class Double-Precision */
5227 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5229 case 106: /* VSX Scalar Test for software Square Root
5231 case 234: /* VSX Vector Test for software Square Root
5233 case 170: /* VSX Vector Test for software Square Root
5235 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5239 switch (PPC_FIELD (insn
, 11, 5))
5241 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5242 case 1: /* VSX Scalar Extract Significand Double-Precision */
5243 record_full_arch_list_add_reg (regcache
,
5244 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5246 case 16: /* VSX Scalar Convert Half-Precision format to
5247 Double-Precision format */
5248 case 17: /* VSX Scalar round & Convert Double-Precision format
5249 to Half-Precision format */
5250 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5251 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5257 switch (PPC_FIELD (insn
, 11, 5))
5259 case 24: /* VSX Vector Convert Half-Precision format to
5260 Single-Precision format */
5261 case 25: /* VSX Vector round and Convert Single-Precision format
5262 to Half-Precision format */
5263 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5265 case 0: /* VSX Vector Extract Exponent Double-Precision */
5266 case 1: /* VSX Vector Extract Significand Double-Precision */
5267 case 7: /* VSX Vector Byte-Reverse Halfword */
5268 case 8: /* VSX Vector Extract Exponent Single-Precision */
5269 case 9: /* VSX Vector Extract Significand Single-Precision */
5270 case 15: /* VSX Vector Byte-Reverse Word */
5271 case 23: /* VSX Vector Byte-Reverse Doubleword */
5272 case 31: /* VSX Vector Byte-Reverse Quadword */
5273 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5281 case 360: /* VSX Vector Splat Immediate Byte */
5282 if (PPC_FIELD (insn
, 11, 2) == 0)
5284 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5288 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5289 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5293 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5295 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5299 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5300 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5304 /* Parse and record instructions of primary opcode-61 at ADDR.
5305 Return 0 if successful. */
5308 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5309 CORE_ADDR addr
, uint32_t insn
)
5311 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5317 case 0: /* Store Floating-Point Double Pair */
5318 case 2: /* Store VSX Scalar Doubleword */
5319 case 3: /* Store VSX Scalar Single */
5320 if (PPC_RA (insn
) != 0)
5321 regcache_raw_read_unsigned (regcache
,
5322 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5324 ea
+= PPC_DS (insn
) << 2;
5327 case 0: /* Store Floating-Point Double Pair */
5330 case 2: /* Store VSX Scalar Doubleword */
5333 case 3: /* Store VSX Scalar Single */
5339 record_full_arch_list_add_mem (ea
, size
);
5345 case 1: /* Load VSX Vector */
5346 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5348 case 5: /* Store VSX Vector */
5349 if (PPC_RA (insn
) != 0)
5350 regcache_raw_read_unsigned (regcache
,
5351 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5353 ea
+= PPC_DQ (insn
) << 4;
5354 record_full_arch_list_add_mem (ea
, 16);
5358 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5359 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5363 /* Parse and record instructions of primary opcode-63 at ADDR.
5364 Return 0 if successful. */
5367 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5368 CORE_ADDR addr
, uint32_t insn
)
5370 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5371 int ext
= PPC_EXTOP (insn
);
5376 case 18: /* Floating Divide */
5377 case 20: /* Floating Subtract */
5378 case 21: /* Floating Add */
5379 case 22: /* Floating Square Root */
5380 case 24: /* Floating Reciprocal Estimate */
5381 case 25: /* Floating Multiply */
5382 case 26: /* Floating Reciprocal Square Root Estimate */
5383 case 28: /* Floating Multiply-Subtract */
5384 case 29: /* Floating Multiply-Add */
5385 case 30: /* Floating Negative Multiply-Subtract */
5386 case 31: /* Floating Negative Multiply-Add */
5387 record_full_arch_list_add_reg (regcache
,
5388 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5390 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5391 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5394 case 23: /* Floating Select */
5395 record_full_arch_list_add_reg (regcache
,
5396 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5398 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5404 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5405 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5407 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5408 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5414 case 2: /* DFP Add Quad */
5415 case 3: /* DFP Quantize Quad */
5416 case 34: /* DFP Multiply Quad */
5417 case 35: /* DFP Reround Quad */
5418 case 67: /* DFP Quantize Immediate Quad */
5419 case 99: /* DFP Round To FP Integer With Inexact Quad */
5420 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5421 case 258: /* DFP Convert To DFP Extended Quad */
5422 case 514: /* DFP Subtract Quad */
5423 case 546: /* DFP Divide Quad */
5424 case 770: /* DFP Round To DFP Long Quad */
5425 case 802: /* DFP Convert From Fixed Quad */
5426 case 834: /* DFP Encode BCD To DPD Quad */
5428 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5429 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5430 record_full_arch_list_add_reg (regcache
, tmp
);
5431 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5432 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5435 case 130: /* DFP Compare Ordered Quad */
5436 case 162: /* DFP Test Exponent Quad */
5437 case 194: /* DFP Test Data Class Quad */
5438 case 226: /* DFP Test Data Group Quad */
5439 case 642: /* DFP Compare Unordered Quad */
5440 case 674: /* DFP Test Significance Quad */
5441 case 675: /* DFP Test Significance Immediate Quad */
5442 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5443 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5446 case 66: /* DFP Shift Significand Left Immediate Quad */
5447 case 98: /* DFP Shift Significand Right Immediate Quad */
5448 case 322: /* DFP Decode DPD To BCD Quad */
5449 case 866: /* DFP Insert Biased Exponent Quad */
5450 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5451 record_full_arch_list_add_reg (regcache
, tmp
);
5452 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5454 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5457 case 290: /* DFP Convert To Fixed Quad */
5458 record_full_arch_list_add_reg (regcache
,
5459 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5461 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5462 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5465 case 354: /* DFP Extract Biased Exponent Quad */
5466 record_full_arch_list_add_reg (regcache
,
5467 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5469 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5472 case 12: /* Floating Round to Single-Precision */
5473 case 14: /* Floating Convert To Integer Word */
5474 case 15: /* Floating Convert To Integer Word
5475 with round toward Zero */
5476 case 142: /* Floating Convert To Integer Word Unsigned */
5477 case 143: /* Floating Convert To Integer Word Unsigned
5478 with round toward Zero */
5479 case 392: /* Floating Round to Integer Nearest */
5480 case 424: /* Floating Round to Integer Toward Zero */
5481 case 456: /* Floating Round to Integer Plus */
5482 case 488: /* Floating Round to Integer Minus */
5483 case 814: /* Floating Convert To Integer Doubleword */
5484 case 815: /* Floating Convert To Integer Doubleword
5485 with round toward Zero */
5486 case 846: /* Floating Convert From Integer Doubleword */
5487 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5488 case 943: /* Floating Convert To Integer Doubleword Unsigned
5489 with round toward Zero */
5490 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5491 record_full_arch_list_add_reg (regcache
,
5492 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5494 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5495 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5499 switch (PPC_FIELD (insn
, 11, 5))
5501 case 1: /* Move From FPSCR & Clear Enables */
5502 case 20: /* Move From FPSCR Control & set DRN */
5503 case 21: /* Move From FPSCR Control & set DRN Immediate */
5504 case 22: /* Move From FPSCR Control & set RN */
5505 case 23: /* Move From FPSCR Control & set RN Immediate */
5506 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5507 case 0: /* Move From FPSCR */
5508 case 24: /* Move From FPSCR Lightweight */
5509 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5510 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5511 record_full_arch_list_add_reg (regcache
,
5512 tdep
->ppc_fp0_regnum
5518 case 8: /* Floating Copy Sign */
5519 case 40: /* Floating Negate */
5520 case 72: /* Floating Move Register */
5521 case 136: /* Floating Negative Absolute Value */
5522 case 264: /* Floating Absolute Value */
5523 record_full_arch_list_add_reg (regcache
,
5524 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5526 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5529 case 838: /* Floating Merge Odd Word */
5530 case 966: /* Floating Merge Even Word */
5531 record_full_arch_list_add_reg (regcache
,
5532 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5535 case 38: /* Move To FPSCR Bit 1 */
5536 case 70: /* Move To FPSCR Bit 0 */
5537 case 134: /* Move To FPSCR Field Immediate */
5538 case 711: /* Move To FPSCR Fields */
5540 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5541 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5544 case 0: /* Floating Compare Unordered */
5545 case 32: /* Floating Compare Ordered */
5546 case 64: /* Move to Condition Register from FPSCR */
5547 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5548 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5549 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5550 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5551 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5553 case 128: /* Floating Test for software Divide */
5554 case 160: /* Floating Test for software Square Root */
5555 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5558 case 4: /* VSX Scalar Add Quad-Precision */
5559 case 36: /* VSX Scalar Multiply Quad-Precision */
5560 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5561 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5562 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5563 case 484: /* VSX Scalar Negative Multiply-Subtract
5565 case 516: /* VSX Scalar Subtract Quad-Precision */
5566 case 548: /* VSX Scalar Divide Quad-Precision */
5567 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5569 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5570 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5571 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5575 switch (PPC_FIELD (insn
, 11, 5))
5577 case 27: /* VSX Scalar Square Root Quad-Precision */
5578 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5580 case 0: /* VSX Scalar Absolute Quad-Precision */
5581 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5582 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5583 case 16: /* VSX Scalar Negate Quad-Precision */
5584 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5585 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5591 switch (PPC_FIELD (insn
, 11, 5))
5593 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5594 to Unsigned Word format */
5595 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5596 Quad-Precision format */
5597 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5598 to Signed Word format */
5599 case 10: /* VSX Scalar Convert Signed Doubleword format to
5600 Quad-Precision format */
5601 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5602 to Unsigned Doubleword format */
5603 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5604 Double-Precision format */
5605 case 22: /* VSX Scalar Convert Double-Precision format to
5606 Quad-Precision format */
5607 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5608 to Signed Doubleword format */
5609 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5610 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5615 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5616 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5620 /* Parse the current instruction and record the values of the registers and
5621 memory that will be changed in current instruction to "record_arch_list".
5622 Return -1 if something wrong. */
5625 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5628 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5629 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5633 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5634 op6
= PPC_OP6 (insn
);
5638 case 2: /* Trap Doubleword Immediate */
5639 case 3: /* Trap Word Immediate */
5644 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5648 case 17: /* System call */
5649 if (PPC_LEV (insn
) != 0)
5652 if (tdep
->ppc_syscall_record
!= NULL
)
5654 if (tdep
->ppc_syscall_record (regcache
) != 0)
5659 printf_unfiltered (_("no syscall record support\n"));
5664 case 7: /* Multiply Low Immediate */
5665 record_full_arch_list_add_reg (regcache
,
5666 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5669 case 8: /* Subtract From Immediate Carrying */
5670 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5671 record_full_arch_list_add_reg (regcache
,
5672 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5675 case 10: /* Compare Logical Immediate */
5676 case 11: /* Compare Immediate */
5677 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5680 case 13: /* Add Immediate Carrying and Record */
5681 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5683 case 12: /* Add Immediate Carrying */
5684 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5686 case 14: /* Add Immediate */
5687 case 15: /* Add Immediate Shifted */
5688 record_full_arch_list_add_reg (regcache
,
5689 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5692 case 16: /* Branch Conditional */
5693 if ((PPC_BO (insn
) & 0x4) == 0)
5694 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5696 case 18: /* Branch */
5698 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5702 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5706 case 20: /* Rotate Left Word Immediate then Mask Insert */
5707 case 21: /* Rotate Left Word Immediate then AND with Mask */
5708 case 23: /* Rotate Left Word then AND with Mask */
5709 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5710 /* Rotate Left Doubleword Immediate then Clear Right */
5711 /* Rotate Left Doubleword Immediate then Clear */
5712 /* Rotate Left Doubleword then Clear Left */
5713 /* Rotate Left Doubleword then Clear Right */
5714 /* Rotate Left Doubleword Immediate then Mask Insert */
5716 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5717 record_full_arch_list_add_reg (regcache
,
5718 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5721 case 28: /* AND Immediate */
5722 case 29: /* AND Immediate Shifted */
5723 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5725 case 24: /* OR Immediate */
5726 case 25: /* OR Immediate Shifted */
5727 case 26: /* XOR Immediate */
5728 case 27: /* XOR Immediate Shifted */
5729 record_full_arch_list_add_reg (regcache
,
5730 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5734 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5738 case 33: /* Load Word and Zero with Update */
5739 case 35: /* Load Byte and Zero with Update */
5740 case 41: /* Load Halfword and Zero with Update */
5741 case 43: /* Load Halfword Algebraic with Update */
5742 record_full_arch_list_add_reg (regcache
,
5743 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5745 case 32: /* Load Word and Zero */
5746 case 34: /* Load Byte and Zero */
5747 case 40: /* Load Halfword and Zero */
5748 case 42: /* Load Halfword Algebraic */
5749 record_full_arch_list_add_reg (regcache
,
5750 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5753 case 46: /* Load Multiple Word */
5754 for (i
= PPC_RT (insn
); i
< 32; i
++)
5755 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5758 case 56: /* Load Quadword */
5759 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5760 record_full_arch_list_add_reg (regcache
, tmp
);
5761 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5764 case 49: /* Load Floating-Point Single with Update */
5765 case 51: /* Load Floating-Point Double with Update */
5766 record_full_arch_list_add_reg (regcache
,
5767 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5769 case 48: /* Load Floating-Point Single */
5770 case 50: /* Load Floating-Point Double */
5771 record_full_arch_list_add_reg (regcache
,
5772 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5775 case 47: /* Store Multiple Word */
5779 if (PPC_RA (insn
) != 0)
5780 regcache_raw_read_unsigned (regcache
,
5781 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5784 addr
+= PPC_D (insn
);
5785 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5789 case 37: /* Store Word with Update */
5790 case 39: /* Store Byte with Update */
5791 case 45: /* Store Halfword with Update */
5792 case 53: /* Store Floating-Point Single with Update */
5793 case 55: /* Store Floating-Point Double with Update */
5794 record_full_arch_list_add_reg (regcache
,
5795 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5797 case 36: /* Store Word */
5798 case 38: /* Store Byte */
5799 case 44: /* Store Halfword */
5800 case 52: /* Store Floating-Point Single */
5801 case 54: /* Store Floating-Point Double */
5806 if (PPC_RA (insn
) != 0)
5807 regcache_raw_read_unsigned (regcache
,
5808 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5810 addr
+= PPC_D (insn
);
5812 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5814 else if (op6
== 54 || op6
== 55)
5816 else if (op6
== 44 || op6
== 45)
5818 else if (op6
== 38 || op6
== 39)
5823 record_full_arch_list_add_mem (addr
, size
);
5830 case 0: /* Load Floating-Point Double Pair */
5831 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5832 record_full_arch_list_add_reg (regcache
, tmp
);
5833 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5835 case 2: /* Load VSX Scalar Doubleword */
5836 case 3: /* Load VSX Scalar Single */
5837 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5844 case 58: /* Load Doubleword */
5845 /* Load Doubleword with Update */
5846 /* Load Word Algebraic */
5847 if (PPC_FIELD (insn
, 30, 2) > 2)
5850 record_full_arch_list_add_reg (regcache
,
5851 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5852 if (PPC_BIT (insn
, 31))
5853 record_full_arch_list_add_reg (regcache
,
5854 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5858 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5863 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5868 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
5872 case 62: /* Store Doubleword */
5873 /* Store Doubleword with Update */
5874 /* Store Quadword with Update */
5878 int sub2
= PPC_FIELD (insn
, 30, 2);
5883 if (PPC_RA (insn
) != 0)
5884 regcache_raw_read_unsigned (regcache
,
5885 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5888 size
= (sub2
== 2) ? 16 : 8;
5890 addr
+= PPC_DS (insn
) << 2;
5891 record_full_arch_list_add_mem (addr
, size
);
5893 if (op6
== 62 && sub2
== 1)
5894 record_full_arch_list_add_reg (regcache
,
5895 tdep
->ppc_gp0_regnum
+
5902 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5908 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5909 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5913 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5915 if (record_full_arch_list_add_end ())
5920 /* Initialize the current architecture based on INFO. If possible, re-use an
5921 architecture from ARCHES, which is a list of architectures already created
5922 during this debugging session.
5924 Called e.g. at program startup, when reading a core file, and when reading
5927 static struct gdbarch
*
5928 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5930 struct gdbarch
*gdbarch
;
5931 struct gdbarch_tdep
*tdep
;
5932 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5933 enum bfd_architecture arch
;
5936 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5938 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5939 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5940 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
5942 int tdesc_wordsize
= -1;
5943 const struct target_desc
*tdesc
= info
.target_desc
;
5944 struct tdesc_arch_data
*tdesc_data
= NULL
;
5945 int num_pseudoregs
= 0;
5948 /* INFO may refer to a binary that is not of the PowerPC architecture,
5949 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5950 In this case, we must not attempt to infer properties of the (PowerPC
5951 side) of the target system from properties of that executable. Trust
5952 the target description instead. */
5954 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5955 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5958 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5959 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5961 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5962 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5964 /* Check word size. If INFO is from a binary file, infer it from
5965 that, else choose a likely default. */
5966 if (from_xcoff_exec
)
5968 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5973 else if (from_elf_exec
)
5975 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5980 else if (tdesc_has_registers (tdesc
))
5984 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
5985 wordsize
= (info
.bfd_arch_info
->bits_per_word
5986 / info
.bfd_arch_info
->bits_per_byte
);
5991 /* Get the architecture and machine from the BFD. */
5992 arch
= info
.bfd_arch_info
->arch
;
5993 mach
= info
.bfd_arch_info
->mach
;
5995 /* For e500 executables, the apuinfo section is of help here. Such
5996 section contains the identifier and revision number of each
5997 Application-specific Processing Unit that is present on the
5998 chip. The content of the section is determined by the assembler
5999 which looks at each instruction and determines which unit (and
6000 which version of it) can execute it. Grovel through the section
6001 looking for relevant e500 APUs. */
6003 if (bfd_uses_spe_extensions (info
.abfd
))
6005 arch
= info
.bfd_arch_info
->arch
;
6006 mach
= bfd_mach_ppc_e500
;
6007 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6008 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6011 /* Find a default target description which describes our register
6012 layout, if we do not already have one. */
6013 if (! tdesc_has_registers (tdesc
))
6015 const struct variant
*v
;
6017 /* Choose variant. */
6018 v
= find_variant_by_arch (arch
, mach
);
6025 gdb_assert (tdesc_has_registers (tdesc
));
6027 /* Check any target description for validity. */
6028 if (tdesc_has_registers (tdesc
))
6030 static const char *const gprs
[] = {
6031 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6032 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6033 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6034 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6036 const struct tdesc_feature
*feature
;
6038 static const char *const msr_names
[] = { "msr", "ps" };
6039 static const char *const cr_names
[] = { "cr", "cnd" };
6040 static const char *const ctr_names
[] = { "ctr", "cnt" };
6042 feature
= tdesc_find_feature (tdesc
,
6043 "org.gnu.gdb.power.core");
6044 if (feature
== NULL
)
6047 tdesc_data
= tdesc_data_alloc ();
6050 for (i
= 0; i
< ppc_num_gprs
; i
++)
6051 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
6052 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
6054 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
6056 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
6059 /* Allow alternate names for these registers, to accomodate GDB's
6061 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6062 PPC_MSR_REGNUM
, msr_names
);
6063 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6064 PPC_CR_REGNUM
, cr_names
);
6065 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6066 PPC_CTR_REGNUM
, ctr_names
);
6070 tdesc_data_cleanup (tdesc_data
);
6074 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
6077 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
6079 wordsize
= tdesc_wordsize
;
6081 feature
= tdesc_find_feature (tdesc
,
6082 "org.gnu.gdb.power.fpu");
6083 if (feature
!= NULL
)
6085 static const char *const fprs
[] = {
6086 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6087 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6088 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6089 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6092 for (i
= 0; i
< ppc_num_fprs
; i
++)
6093 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6094 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6095 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6096 PPC_FPSCR_REGNUM
, "fpscr");
6100 tdesc_data_cleanup (tdesc_data
);
6108 /* The DFP pseudo-registers will be available when there are floating
6110 have_dfp
= have_fpu
;
6112 feature
= tdesc_find_feature (tdesc
,
6113 "org.gnu.gdb.power.altivec");
6114 if (feature
!= NULL
)
6116 static const char *const vector_regs
[] = {
6117 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6118 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6119 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6120 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6124 for (i
= 0; i
< ppc_num_gprs
; i
++)
6125 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6128 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6129 PPC_VSCR_REGNUM
, "vscr");
6130 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6131 PPC_VRSAVE_REGNUM
, "vrsave");
6133 if (have_spe
|| !valid_p
)
6135 tdesc_data_cleanup (tdesc_data
);
6143 /* Check for POWER7 VSX registers support. */
6144 feature
= tdesc_find_feature (tdesc
,
6145 "org.gnu.gdb.power.vsx");
6147 if (feature
!= NULL
)
6149 static const char *const vsx_regs
[] = {
6150 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6151 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6152 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6153 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6154 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6160 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6161 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6162 PPC_VSR0_UPPER_REGNUM
+ i
,
6166 tdesc_data_cleanup (tdesc_data
);
6175 /* On machines supporting the SPE APU, the general-purpose registers
6176 are 64 bits long. There are SIMD vector instructions to treat them
6177 as pairs of floats, but the rest of the instruction set treats them
6178 as 32-bit registers, and only operates on their lower halves.
6180 In the GDB regcache, we treat their high and low halves as separate
6181 registers. The low halves we present as the general-purpose
6182 registers, and then we have pseudo-registers that stitch together
6183 the upper and lower halves and present them as pseudo-registers.
6185 Thus, the target description is expected to supply the upper
6186 halves separately. */
6188 feature
= tdesc_find_feature (tdesc
,
6189 "org.gnu.gdb.power.spe");
6190 if (feature
!= NULL
)
6192 static const char *const upper_spe
[] = {
6193 "ev0h", "ev1h", "ev2h", "ev3h",
6194 "ev4h", "ev5h", "ev6h", "ev7h",
6195 "ev8h", "ev9h", "ev10h", "ev11h",
6196 "ev12h", "ev13h", "ev14h", "ev15h",
6197 "ev16h", "ev17h", "ev18h", "ev19h",
6198 "ev20h", "ev21h", "ev22h", "ev23h",
6199 "ev24h", "ev25h", "ev26h", "ev27h",
6200 "ev28h", "ev29h", "ev30h", "ev31h"
6204 for (i
= 0; i
< ppc_num_gprs
; i
++)
6205 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6206 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6208 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6209 PPC_SPE_ACC_REGNUM
, "acc");
6210 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6211 PPC_SPE_FSCR_REGNUM
, "spefscr");
6213 if (have_mq
|| have_fpu
|| !valid_p
)
6215 tdesc_data_cleanup (tdesc_data
);
6224 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6225 complain for a 32-bit binary on a 64-bit target; we do not yet
6226 support that. For instance, the 32-bit ABI routines expect
6229 As long as there isn't an explicit target description, we'll
6230 choose one based on the BFD architecture and get a word size
6231 matching the binary (probably powerpc:common or
6232 powerpc:common64). So there is only trouble if a 64-bit target
6233 supplies a 64-bit description while debugging a 32-bit
6235 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6237 tdesc_data_cleanup (tdesc_data
);
6244 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6247 elf_abi
= POWERPC_ELF_V1
;
6250 elf_abi
= POWERPC_ELF_V2
;
6257 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6259 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6260 Tag_GNU_Power_ABI_FP
))
6263 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6266 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6273 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6275 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6276 Tag_GNU_Power_ABI_Vector
))
6279 vector_abi
= POWERPC_VEC_GENERIC
;
6282 vector_abi
= POWERPC_VEC_ALTIVEC
;
6285 vector_abi
= POWERPC_VEC_SPE
;
6293 /* At this point, the only supported ELF-based 64-bit little-endian
6294 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6295 default. All other supported ELF-based operating systems use the
6296 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6297 e.g. because we run a legacy binary, or have attached to a process
6298 and have not found any associated binary file, set the default
6299 according to this heuristic. */
6300 if (elf_abi
== POWERPC_ELF_AUTO
)
6302 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6303 elf_abi
= POWERPC_ELF_V2
;
6305 elf_abi
= POWERPC_ELF_V1
;
6308 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6310 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6313 soft_float
= !have_fpu
;
6315 /* If we have a hard float binary or setting but no floating point
6316 registers, downgrade to soft float anyway. We're still somewhat
6317 useful in this scenario. */
6318 if (!soft_float
&& !have_fpu
)
6321 /* Similarly for vector registers. */
6322 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6323 vector_abi
= POWERPC_VEC_GENERIC
;
6325 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6326 vector_abi
= POWERPC_VEC_GENERIC
;
6328 if (vector_abi
== POWERPC_VEC_AUTO
)
6331 vector_abi
= POWERPC_VEC_ALTIVEC
;
6333 vector_abi
= POWERPC_VEC_SPE
;
6335 vector_abi
= POWERPC_VEC_GENERIC
;
6338 /* Do not limit the vector ABI based on available hardware, since we
6339 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6341 /* Find a candidate among extant architectures. */
6342 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6344 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6346 /* Word size in the various PowerPC bfd_arch_info structs isn't
6347 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6348 separate word size check. */
6349 tdep
= gdbarch_tdep (arches
->gdbarch
);
6350 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6352 if (tdep
&& tdep
->soft_float
!= soft_float
)
6354 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6356 if (tdep
&& tdep
->wordsize
== wordsize
)
6358 if (tdesc_data
!= NULL
)
6359 tdesc_data_cleanup (tdesc_data
);
6360 return arches
->gdbarch
;
6364 /* None found, create a new architecture from INFO, whose bfd_arch_info
6365 validity depends on the source:
6366 - executable useless
6367 - rs6000_host_arch() good
6369 - "set arch" trust blindly
6370 - GDB startup useless but harmless */
6372 tdep
= XCNEW (struct gdbarch_tdep
);
6373 tdep
->wordsize
= wordsize
;
6374 tdep
->elf_abi
= elf_abi
;
6375 tdep
->soft_float
= soft_float
;
6376 tdep
->vector_abi
= vector_abi
;
6378 gdbarch
= gdbarch_alloc (&info
, tdep
);
6380 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6381 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6382 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6383 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6384 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6385 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6386 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6387 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6389 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6390 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6391 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6392 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6393 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6394 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6395 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6396 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6398 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6399 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6400 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6401 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6403 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6404 GDB traditionally called it "ps", though, so let GDB add an
6406 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6409 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6411 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6413 /* Set lr_frame_offset. */
6415 tdep
->lr_frame_offset
= 16;
6417 tdep
->lr_frame_offset
= 4;
6419 if (have_spe
|| have_dfp
|| have_vsx
)
6421 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6422 set_gdbarch_pseudo_register_write (gdbarch
,
6423 rs6000_pseudo_register_write
);
6424 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6425 rs6000_ax_pseudo_register_collect
);
6428 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6430 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6432 /* Select instruction printer. */
6433 if (arch
== bfd_arch_rs6000
)
6434 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
6436 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
6438 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6441 num_pseudoregs
+= 32;
6443 num_pseudoregs
+= 16;
6445 /* Include both VSX and Extended FP registers. */
6446 num_pseudoregs
+= 96;
6448 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6450 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6451 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6452 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6453 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6454 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6455 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6456 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6457 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6458 set_gdbarch_char_signed (gdbarch
, 0);
6460 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6463 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6465 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6466 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6467 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6469 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6470 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6473 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6474 else if (wordsize
== 8)
6475 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6477 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6478 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6479 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6481 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6483 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6484 rs6000_breakpoint::kind_from_pc
);
6485 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6486 rs6000_breakpoint::bp_from_kind
);
6488 /* The value of symbols of type N_SO and N_FUN maybe null when
6490 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6492 /* Handles single stepping of atomic sequences. */
6493 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6495 /* Not sure on this. FIXMEmgo */
6496 set_gdbarch_frame_args_skip (gdbarch
, 8);
6498 /* Helpers for function argument information. */
6499 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6502 set_gdbarch_in_solib_return_trampoline
6503 (gdbarch
, rs6000_in_solib_return_trampoline
);
6504 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6506 /* Hook in the DWARF CFI frame unwinder. */
6507 dwarf2_append_unwinders (gdbarch
);
6508 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6510 /* Frame handling. */
6511 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6513 /* Setup displaced stepping. */
6514 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6515 ppc_displaced_step_copy_insn
);
6516 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6517 ppc_displaced_step_hw_singlestep
);
6518 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6519 set_gdbarch_displaced_step_free_closure (gdbarch
,
6520 simple_displaced_step_free_closure
);
6521 set_gdbarch_displaced_step_location (gdbarch
,
6522 displaced_step_at_entry_point
);
6524 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6526 /* Hook in ABI-specific overrides, if they have been registered. */
6527 info
.target_desc
= tdesc
;
6528 info
.tdep_info
= tdesc_data
;
6529 gdbarch_init_osabi (info
, gdbarch
);
6533 case GDB_OSABI_LINUX
:
6534 case GDB_OSABI_NETBSD_AOUT
:
6535 case GDB_OSABI_NETBSD_ELF
:
6536 case GDB_OSABI_UNKNOWN
:
6537 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6538 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6539 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6540 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6541 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6544 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6546 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6547 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6548 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6549 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6550 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6553 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6554 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6555 rs6000_pseudo_register_reggroup_p
);
6556 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6558 /* Override the normal target description method to make the SPE upper
6559 halves anonymous. */
6560 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6562 /* Choose register numbers for all supported pseudo-registers. */
6563 tdep
->ppc_ev0_regnum
= -1;
6564 tdep
->ppc_dl0_regnum
= -1;
6565 tdep
->ppc_vsr0_regnum
= -1;
6566 tdep
->ppc_efpr0_regnum
= -1;
6568 cur_reg
= gdbarch_num_regs (gdbarch
);
6572 tdep
->ppc_ev0_regnum
= cur_reg
;
6577 tdep
->ppc_dl0_regnum
= cur_reg
;
6582 tdep
->ppc_vsr0_regnum
= cur_reg
;
6584 tdep
->ppc_efpr0_regnum
= cur_reg
;
6588 gdb_assert (gdbarch_num_regs (gdbarch
)
6589 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
6591 /* Register the ravenscar_arch_ops. */
6592 if (mach
== bfd_mach_ppc_e500
)
6593 register_e500_ravenscar_ops (gdbarch
);
6595 register_ppc_ravenscar_ops (gdbarch
);
6601 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6603 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6608 /* FIXME: Dump gdbarch_tdep. */
6611 /* PowerPC-specific commands. */
6614 set_powerpc_command (char *args
, int from_tty
)
6616 printf_unfiltered (_("\
6617 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6618 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6622 show_powerpc_command (char *args
, int from_tty
)
6624 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6628 powerpc_set_soft_float (char *args
, int from_tty
,
6629 struct cmd_list_element
*c
)
6631 struct gdbarch_info info
;
6633 /* Update the architecture. */
6634 gdbarch_info_init (&info
);
6635 if (!gdbarch_update_p (info
))
6636 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6640 powerpc_set_vector_abi (char *args
, int from_tty
,
6641 struct cmd_list_element
*c
)
6643 struct gdbarch_info info
;
6646 for (vector_abi
= POWERPC_VEC_AUTO
;
6647 vector_abi
!= POWERPC_VEC_LAST
;
6649 if (strcmp (powerpc_vector_abi_string
,
6650 powerpc_vector_strings
[vector_abi
]) == 0)
6652 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6656 if (vector_abi
== POWERPC_VEC_LAST
)
6657 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6658 powerpc_vector_abi_string
);
6660 /* Update the architecture. */
6661 gdbarch_info_init (&info
);
6662 if (!gdbarch_update_p (info
))
6663 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6666 /* Show the current setting of the exact watchpoints flag. */
6669 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6670 struct cmd_list_element
*c
,
6673 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6676 /* Read a PPC instruction from memory. */
6679 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6681 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6682 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6684 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6687 /* Return non-zero if the instructions at PC match the series
6688 described in PATTERN, or zero otherwise. PATTERN is an array of
6689 'struct ppc_insn_pattern' objects, terminated by an entry whose
6692 When the match is successful, fill INSN[i] with what PATTERN[i]
6693 matched. If PATTERN[i] is optional, and the instruction wasn't
6694 present, set INSN[i] to 0 (which is not a valid PPC instruction).
6695 INSN should have as many elements as PATTERN. Note that, if
6696 PATTERN contains optional instructions which aren't present in
6697 memory, then INSN will have holes, so INSN[i] isn't necessarily the
6698 i'th instruction in memory. */
6701 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6702 struct ppc_insn_pattern
*pattern
,
6703 unsigned int *insns
)
6708 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6711 insn
= read_insn (frame
, pc
);
6713 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6719 else if (!pattern
[i
].optional
)
6726 /* Return the 'd' field of the d-form instruction INSN, properly
6730 ppc_insn_d_field (unsigned int insn
)
6732 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6735 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6736 zero bits concatenated at the right, and properly
6740 ppc_insn_ds_field (unsigned int insn
)
6742 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6745 /* Initialization code. */
6747 /* -Wmissing-prototypes */
6748 extern initialize_file_ftype _initialize_rs6000_tdep
;
6751 _initialize_rs6000_tdep (void)
6753 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6754 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6756 /* Initialize the standard target descriptions. */
6757 initialize_tdesc_powerpc_32 ();
6758 initialize_tdesc_powerpc_altivec32 ();
6759 initialize_tdesc_powerpc_vsx32 ();
6760 initialize_tdesc_powerpc_403 ();
6761 initialize_tdesc_powerpc_403gc ();
6762 initialize_tdesc_powerpc_405 ();
6763 initialize_tdesc_powerpc_505 ();
6764 initialize_tdesc_powerpc_601 ();
6765 initialize_tdesc_powerpc_602 ();
6766 initialize_tdesc_powerpc_603 ();
6767 initialize_tdesc_powerpc_604 ();
6768 initialize_tdesc_powerpc_64 ();
6769 initialize_tdesc_powerpc_altivec64 ();
6770 initialize_tdesc_powerpc_vsx64 ();
6771 initialize_tdesc_powerpc_7400 ();
6772 initialize_tdesc_powerpc_750 ();
6773 initialize_tdesc_powerpc_860 ();
6774 initialize_tdesc_powerpc_e500 ();
6775 initialize_tdesc_rs6000 ();
6777 /* Add root prefix command for all "set powerpc"/"show powerpc"
6779 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6780 _("Various PowerPC-specific commands."),
6781 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6783 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6784 _("Various PowerPC-specific commands."),
6785 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6787 /* Add a command to allow the user to force the ABI. */
6788 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6789 &powerpc_soft_float_global
,
6790 _("Set whether to use a soft-float ABI."),
6791 _("Show whether to use a soft-float ABI."),
6793 powerpc_set_soft_float
, NULL
,
6794 &setpowerpccmdlist
, &showpowerpccmdlist
);
6796 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6797 &powerpc_vector_abi_string
,
6798 _("Set the vector ABI."),
6799 _("Show the vector ABI."),
6800 NULL
, powerpc_set_vector_abi
, NULL
,
6801 &setpowerpccmdlist
, &showpowerpccmdlist
);
6803 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6804 &target_exact_watchpoints
,
6806 Set whether to use just one debug register for watchpoints on scalars."),
6808 Show whether to use just one debug register for watchpoints on scalars."),
6810 If true, GDB will use only one debug register when watching a variable of\n\
6811 scalar type, thus assuming that the variable is accessed through the address\n\
6812 of its first byte."),
6813 NULL
, show_powerpc_exact_watchpoints
,
6814 &setpowerpccmdlist
, &showpowerpccmdlist
);