1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "dwarf2-frame.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
42 #include "record-full.h"
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
52 #include "elf/ppc64.h"
54 #include "solib-svr4.h"
56 #include "ppc-ravenscar-thread.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
68 #include "features/rs6000/powerpc-32.c"
69 #include "features/rs6000/powerpc-altivec32.c"
70 #include "features/rs6000/powerpc-vsx32.c"
71 #include "features/rs6000/powerpc-403.c"
72 #include "features/rs6000/powerpc-403gc.c"
73 #include "features/rs6000/powerpc-405.c"
74 #include "features/rs6000/powerpc-505.c"
75 #include "features/rs6000/powerpc-601.c"
76 #include "features/rs6000/powerpc-602.c"
77 #include "features/rs6000/powerpc-603.c"
78 #include "features/rs6000/powerpc-604.c"
79 #include "features/rs6000/powerpc-64.c"
80 #include "features/rs6000/powerpc-altivec64.c"
81 #include "features/rs6000/powerpc-vsx64.c"
82 #include "features/rs6000/powerpc-7400.c"
83 #include "features/rs6000/powerpc-750.c"
84 #include "features/rs6000/powerpc-860.c"
85 #include "features/rs6000/powerpc-e500.c"
86 #include "features/rs6000/rs6000.c"
88 /* Determine if regnum is an SPE pseudo-register. */
89 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
90 && (regnum) >= (tdep)->ppc_ev0_regnum \
91 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
93 /* Determine if regnum is a decimal float pseudo-register. */
94 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
95 && (regnum) >= (tdep)->ppc_dl0_regnum \
96 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
98 /* Determine if regnum is a POWER7 VSX register. */
99 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
100 && (regnum) >= (tdep)->ppc_vsr0_regnum \
101 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
103 /* Determine if regnum is a POWER7 Extended FP register. */
104 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
105 && (regnum) >= (tdep)->ppc_efpr0_regnum \
106 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
108 /* Holds the current set of options to be passed to the disassembler. */
109 static char *powerpc_disassembler_options
;
111 /* The list of available "set powerpc ..." and "show powerpc ..."
113 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
114 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
116 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
118 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
119 static const char *const powerpc_vector_strings
[] =
128 /* A variable that can be configured by the user. */
129 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
130 static const char *powerpc_vector_abi_string
= "auto";
132 /* To be used by skip_prologue. */
134 struct rs6000_framedata
136 int offset
; /* total size of frame --- the distance
137 by which we decrement sp to allocate
139 int saved_gpr
; /* smallest # of saved gpr */
140 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
141 int saved_fpr
; /* smallest # of saved fpr */
142 int saved_vr
; /* smallest # of saved vr */
143 int saved_ev
; /* smallest # of saved ev */
144 int alloca_reg
; /* alloca register number (frame ptr) */
145 char frameless
; /* true if frameless functions. */
146 char nosavedpc
; /* true if pc not saved. */
147 char used_bl
; /* true if link register clobbered */
148 int gpr_offset
; /* offset of saved gprs from prev sp */
149 int fpr_offset
; /* offset of saved fprs from prev sp */
150 int vr_offset
; /* offset of saved vrs from prev sp */
151 int ev_offset
; /* offset of saved evs from prev sp */
152 int lr_offset
; /* offset of saved lr */
153 int lr_register
; /* register of saved lr, if trustworthy */
154 int cr_offset
; /* offset of saved cr */
155 int vrsave_offset
; /* offset of saved vrsave register */
159 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
161 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
163 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
164 if (tdep
->ppc_vsr0_regnum
< 0)
167 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
168 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
171 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
173 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
175 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
176 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
179 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
183 /* Return true if REGNO is an SPE register, false otherwise. */
185 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
187 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
189 /* Is it a reference to EV0 -- EV31, and do we have those? */
190 if (IS_SPE_PSEUDOREG (tdep
, regno
))
193 /* Is it a reference to one of the raw upper GPR halves? */
194 if (tdep
->ppc_ev0_upper_regnum
>= 0
195 && tdep
->ppc_ev0_upper_regnum
<= regno
196 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
199 /* Is it a reference to the 64-bit accumulator, and do we have that? */
200 if (tdep
->ppc_acc_regnum
>= 0
201 && tdep
->ppc_acc_regnum
== regno
)
204 /* Is it a reference to the SPE floating-point status and control register,
205 and do we have that? */
206 if (tdep
->ppc_spefscr_regnum
>= 0
207 && tdep
->ppc_spefscr_regnum
== regno
)
214 /* Return non-zero if the architecture described by GDBARCH has
215 floating-point registers (f0 --- f31 and fpscr). */
217 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
219 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
221 return (tdep
->ppc_fp0_regnum
>= 0
222 && tdep
->ppc_fpscr_regnum
>= 0);
225 /* Return non-zero if the architecture described by GDBARCH has
226 Altivec registers (vr0 --- vr31, vrsave and vscr). */
228 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
230 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
232 return (tdep
->ppc_vr0_regnum
>= 0
233 && tdep
->ppc_vrsave_regnum
>= 0);
236 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
239 This is a helper function for init_sim_regno_table, constructing
240 the table mapping GDB register numbers to sim register numbers; we
241 initialize every element in that table to -1 before we start
244 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
246 /* Make sure we don't try to assign any given GDB register a sim
247 register number more than once. */
248 gdb_assert (table
[gdb_regno
] == -1);
249 table
[gdb_regno
] = sim_regno
;
253 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
254 numbers to simulator register numbers, based on the values placed
255 in the ARCH->tdep->ppc_foo_regnum members. */
257 init_sim_regno_table (struct gdbarch
*arch
)
259 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
260 int total_regs
= gdbarch_num_regs (arch
);
261 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
263 static const char *const segment_regs
[] = {
264 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
265 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
268 /* Presume that all registers not explicitly mentioned below are
269 unavailable from the sim. */
270 for (i
= 0; i
< total_regs
; i
++)
273 /* General-purpose registers. */
274 for (i
= 0; i
< ppc_num_gprs
; i
++)
275 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
277 /* Floating-point registers. */
278 if (tdep
->ppc_fp0_regnum
>= 0)
279 for (i
= 0; i
< ppc_num_fprs
; i
++)
280 set_sim_regno (sim_regno
,
281 tdep
->ppc_fp0_regnum
+ i
,
282 sim_ppc_f0_regnum
+ i
);
283 if (tdep
->ppc_fpscr_regnum
>= 0)
284 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
286 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
287 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
288 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
290 /* Segment registers. */
291 for (i
= 0; i
< ppc_num_srs
; i
++)
295 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
297 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
300 /* Altivec registers. */
301 if (tdep
->ppc_vr0_regnum
>= 0)
303 for (i
= 0; i
< ppc_num_vrs
; i
++)
304 set_sim_regno (sim_regno
,
305 tdep
->ppc_vr0_regnum
+ i
,
306 sim_ppc_vr0_regnum
+ i
);
308 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
309 we can treat this more like the other cases. */
310 set_sim_regno (sim_regno
,
311 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
312 sim_ppc_vscr_regnum
);
314 /* vsave is a special-purpose register, so the code below handles it. */
316 /* SPE APU (E500) registers. */
317 if (tdep
->ppc_ev0_upper_regnum
>= 0)
318 for (i
= 0; i
< ppc_num_gprs
; i
++)
319 set_sim_regno (sim_regno
,
320 tdep
->ppc_ev0_upper_regnum
+ i
,
321 sim_ppc_rh0_regnum
+ i
);
322 if (tdep
->ppc_acc_regnum
>= 0)
323 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
324 /* spefscr is a special-purpose register, so the code below handles it. */
327 /* Now handle all special-purpose registers. Verify that they
328 haven't mistakenly been assigned numbers by any of the above
330 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
332 const char *spr_name
= sim_spr_register_name (i
);
335 if (spr_name
!= NULL
)
336 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
339 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
343 /* Drop the initialized array into place. */
344 tdep
->sim_regno
= sim_regno
;
348 /* Given a GDB register number REG, return the corresponding SIM
351 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
353 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
356 if (tdep
->sim_regno
== NULL
)
357 init_sim_regno_table (gdbarch
);
359 gdb_assert (0 <= reg
&& reg
<= gdbarch_num_cooked_regs (gdbarch
));
360 sim_regno
= tdep
->sim_regno
[reg
];
365 return LEGACY_SIM_REGNO_IGNORE
;
370 /* Register set support functions. */
372 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
373 Write the register to REGCACHE. */
376 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
377 const gdb_byte
*regs
, size_t offset
, int regsize
)
379 if (regnum
!= -1 && offset
!= -1)
383 struct gdbarch
*gdbarch
= regcache
->arch ();
384 int gdb_regsize
= register_size (gdbarch
, regnum
);
385 if (gdb_regsize
< regsize
386 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
387 offset
+= regsize
- gdb_regsize
;
389 regcache
->raw_supply (regnum
, regs
+ offset
);
393 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
394 in a field REGSIZE wide. Zero pad as necessary. */
397 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
398 gdb_byte
*regs
, size_t offset
, int regsize
)
400 if (regnum
!= -1 && offset
!= -1)
404 struct gdbarch
*gdbarch
= regcache
->arch ();
405 int gdb_regsize
= register_size (gdbarch
, regnum
);
406 if (gdb_regsize
< regsize
)
408 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
410 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
411 offset
+= regsize
- gdb_regsize
;
414 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
415 regsize
- gdb_regsize
);
418 regcache
->raw_collect (regnum
, regs
+ offset
);
423 ppc_greg_offset (struct gdbarch
*gdbarch
,
424 struct gdbarch_tdep
*tdep
,
425 const struct ppc_reg_offsets
*offsets
,
429 *regsize
= offsets
->gpr_size
;
430 if (regnum
>= tdep
->ppc_gp0_regnum
431 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
432 return (offsets
->r0_offset
433 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
435 if (regnum
== gdbarch_pc_regnum (gdbarch
))
436 return offsets
->pc_offset
;
438 if (regnum
== tdep
->ppc_ps_regnum
)
439 return offsets
->ps_offset
;
441 if (regnum
== tdep
->ppc_lr_regnum
)
442 return offsets
->lr_offset
;
444 if (regnum
== tdep
->ppc_ctr_regnum
)
445 return offsets
->ctr_offset
;
447 *regsize
= offsets
->xr_size
;
448 if (regnum
== tdep
->ppc_cr_regnum
)
449 return offsets
->cr_offset
;
451 if (regnum
== tdep
->ppc_xer_regnum
)
452 return offsets
->xer_offset
;
454 if (regnum
== tdep
->ppc_mq_regnum
)
455 return offsets
->mq_offset
;
461 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
462 const struct ppc_reg_offsets
*offsets
,
465 if (regnum
>= tdep
->ppc_fp0_regnum
466 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
467 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
469 if (regnum
== tdep
->ppc_fpscr_regnum
)
470 return offsets
->fpscr_offset
;
475 /* Supply register REGNUM in the general-purpose register set REGSET
476 from the buffer specified by GREGS and LEN to register cache
477 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
480 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
481 int regnum
, const void *gregs
, size_t len
)
483 struct gdbarch
*gdbarch
= regcache
->arch ();
484 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
485 const struct ppc_reg_offsets
*offsets
486 = (const struct ppc_reg_offsets
*) regset
->regmap
;
493 int gpr_size
= offsets
->gpr_size
;
495 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
496 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
497 i
++, offset
+= gpr_size
)
498 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
501 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
502 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
503 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
504 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
505 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
506 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
507 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
508 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
509 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
510 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
512 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
513 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
515 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
516 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
521 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
522 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
525 /* Supply register REGNUM in the floating-point register set REGSET
526 from the buffer specified by FPREGS and LEN to register cache
527 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
530 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
531 int regnum
, const void *fpregs
, size_t len
)
533 struct gdbarch
*gdbarch
= regcache
->arch ();
534 struct gdbarch_tdep
*tdep
;
535 const struct ppc_reg_offsets
*offsets
;
538 if (!ppc_floating_point_unit_p (gdbarch
))
541 tdep
= gdbarch_tdep (gdbarch
);
542 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
547 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
548 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
550 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
552 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
553 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
554 offsets
->fpscr_size
);
558 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
559 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
560 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
563 /* Collect register REGNUM in the general-purpose register set
564 REGSET from register cache REGCACHE into the buffer specified by
565 GREGS and LEN. If REGNUM is -1, do this for all registers in
569 ppc_collect_gregset (const struct regset
*regset
,
570 const struct regcache
*regcache
,
571 int regnum
, void *gregs
, size_t len
)
573 struct gdbarch
*gdbarch
= regcache
->arch ();
574 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
575 const struct ppc_reg_offsets
*offsets
576 = (const struct ppc_reg_offsets
*) regset
->regmap
;
583 int gpr_size
= offsets
->gpr_size
;
585 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
586 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
587 i
++, offset
+= gpr_size
)
588 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
590 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
591 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
592 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
593 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
594 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
595 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
596 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
597 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
598 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
599 (gdb_byte
*) gregs
, offsets
->cr_offset
,
601 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
602 (gdb_byte
*) gregs
, offsets
->xer_offset
,
604 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
605 (gdb_byte
*) gregs
, offsets
->mq_offset
,
610 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
611 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
614 /* Collect register REGNUM in the floating-point register set
615 REGSET from register cache REGCACHE into the buffer specified by
616 FPREGS and LEN. If REGNUM is -1, do this for all registers in
620 ppc_collect_fpregset (const struct regset
*regset
,
621 const struct regcache
*regcache
,
622 int regnum
, void *fpregs
, size_t len
)
624 struct gdbarch
*gdbarch
= regcache
->arch ();
625 struct gdbarch_tdep
*tdep
;
626 const struct ppc_reg_offsets
*offsets
;
629 if (!ppc_floating_point_unit_p (gdbarch
))
632 tdep
= gdbarch_tdep (gdbarch
);
633 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
638 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
639 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
641 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
643 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
644 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
645 offsets
->fpscr_size
);
649 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
650 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
651 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
655 insn_changes_sp_or_jumps (unsigned long insn
)
657 int opcode
= (insn
>> 26) & 0x03f;
658 int sd
= (insn
>> 21) & 0x01f;
659 int a
= (insn
>> 16) & 0x01f;
660 int subcode
= (insn
>> 1) & 0x3ff;
662 /* Changes the stack pointer. */
664 /* NOTE: There are many ways to change the value of a given register.
665 The ways below are those used when the register is R1, the SP,
666 in a funtion's epilogue. */
668 if (opcode
== 31 && subcode
== 444 && a
== 1)
669 return 1; /* mr R1,Rn */
670 if (opcode
== 14 && sd
== 1)
671 return 1; /* addi R1,Rn,simm */
672 if (opcode
== 58 && sd
== 1)
673 return 1; /* ld R1,ds(Rn) */
675 /* Transfers control. */
681 if (opcode
== 19 && subcode
== 16)
683 if (opcode
== 19 && subcode
== 528)
684 return 1; /* bcctr */
689 /* Return true if we are in the function's epilogue, i.e. after the
690 instruction that destroyed the function's stack frame.
692 1) scan forward from the point of execution:
693 a) If you find an instruction that modifies the stack pointer
694 or transfers control (except a return), execution is not in
696 b) Stop scanning if you find a return instruction or reach the
697 end of the function or reach the hard limit for the size of
699 2) scan backward from the point of execution:
700 a) If you find an instruction that modifies the stack pointer,
701 execution *is* in an epilogue, return.
702 b) Stop scanning if you reach an instruction that transfers
703 control or the beginning of the function or reach the hard
704 limit for the size of an epilogue. */
707 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
708 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
710 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
711 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
712 bfd_byte insn_buf
[PPC_INSN_SIZE
];
713 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
716 /* Find the search limits based on function boundaries and hard limit. */
718 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
721 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
722 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
724 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
725 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
727 /* Scan forward until next 'blr'. */
729 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
731 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
733 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
734 if (insn
== 0x4e800020)
736 /* Assume a bctr is a tail call unless it points strictly within
738 if (insn
== 0x4e800420)
740 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
741 tdep
->ppc_ctr_regnum
);
742 if (ctr
> func_start
&& ctr
< func_end
)
747 if (insn_changes_sp_or_jumps (insn
))
751 /* Scan backward until adjustment to stack pointer (R1). */
753 for (scan_pc
= pc
- PPC_INSN_SIZE
;
754 scan_pc
>= epilogue_start
;
755 scan_pc
-= PPC_INSN_SIZE
)
757 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
759 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
760 if (insn_changes_sp_or_jumps (insn
))
767 /* Implement the stack_frame_destroyed_p gdbarch method. */
770 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
772 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
776 /* Get the ith function argument for the current function. */
778 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
781 return get_frame_register_unsigned (frame
, 3 + argi
);
784 /* Sequence of bytes for breakpoint instruction. */
786 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
787 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
789 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
792 /* Instruction masks for displaced stepping. */
793 #define BRANCH_MASK 0xfc000000
794 #define BP_MASK 0xFC0007FE
795 #define B_INSN 0x48000000
796 #define BC_INSN 0x40000000
797 #define BXL_INSN 0x4c000000
798 #define BP_INSN 0x7C000008
800 /* Instruction masks used during single-stepping of atomic
802 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
803 #define LWARX_INSTRUCTION 0x7c000028
804 #define LDARX_INSTRUCTION 0x7c0000A8
805 #define LBARX_INSTRUCTION 0x7c000068
806 #define LHARX_INSTRUCTION 0x7c0000e8
807 #define LQARX_INSTRUCTION 0x7c000228
808 #define STORE_CONDITIONAL_MASK 0xfc0007ff
809 #define STWCX_INSTRUCTION 0x7c00012d
810 #define STDCX_INSTRUCTION 0x7c0001ad
811 #define STBCX_INSTRUCTION 0x7c00056d
812 #define STHCX_INSTRUCTION 0x7c0005ad
813 #define STQCX_INSTRUCTION 0x7c00016d
815 /* Check if insn is one of the Load And Reserve instructions used for atomic
817 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
818 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
819 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
820 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
821 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
822 /* Check if insn is one of the Store Conditional instructions used for atomic
824 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
825 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
826 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
827 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
828 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
830 typedef buf_displaced_step_closure ppc_displaced_step_closure
;
832 /* We can't displaced step atomic sequences. */
834 static struct displaced_step_closure
*
835 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
836 CORE_ADDR from
, CORE_ADDR to
,
837 struct regcache
*regs
)
839 size_t len
= gdbarch_max_insn_length (gdbarch
);
840 std::unique_ptr
<ppc_displaced_step_closure
> closure
841 (new ppc_displaced_step_closure (len
));
842 gdb_byte
*buf
= closure
->buf
.data ();
843 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
846 read_memory (from
, buf
, len
);
848 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
850 /* Assume all atomic sequences start with a Load and Reserve instruction. */
851 if (IS_LOAD_AND_RESERVE_INSN (insn
))
855 fprintf_unfiltered (gdb_stdlog
,
856 "displaced: can't displaced step "
857 "atomic sequence at %s\n",
858 paddress (gdbarch
, from
));
864 write_memory (to
, buf
, len
);
868 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
869 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
870 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
873 return closure
.release ();
876 /* Fix up the state of registers and memory after having single-stepped
877 a displaced instruction. */
879 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
880 struct displaced_step_closure
*closure_
,
881 CORE_ADDR from
, CORE_ADDR to
,
882 struct regcache
*regs
)
884 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
885 /* Our closure is a copy of the instruction. */
886 ppc_displaced_step_closure
*closure
= (ppc_displaced_step_closure
*) closure_
;
887 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
888 PPC_INSN_SIZE
, byte_order
);
890 /* Offset for non PC-relative instructions. */
891 LONGEST offset
= PPC_INSN_SIZE
;
893 opcode
= insn
& BRANCH_MASK
;
896 fprintf_unfiltered (gdb_stdlog
,
897 "displaced: (ppc) fixup (%s, %s)\n",
898 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
901 /* Handle PC-relative branch instructions. */
902 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
906 /* Read the current PC value after the instruction has been executed
907 in a displaced location. Calculate the offset to be applied to the
908 original PC value before the displaced stepping. */
909 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
911 offset
= current_pc
- to
;
913 if (opcode
!= BXL_INSN
)
915 /* Check for AA bit indicating whether this is an absolute
916 addressing or PC-relative (1: absolute, 0: relative). */
919 /* PC-relative addressing is being used in the branch. */
923 "displaced: (ppc) branch instruction: %s\n"
924 "displaced: (ppc) adjusted PC from %s to %s\n",
925 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
926 paddress (gdbarch
, from
+ offset
));
928 regcache_cooked_write_unsigned (regs
,
929 gdbarch_pc_regnum (gdbarch
),
935 /* If we're here, it means we have a branch to LR or CTR. If the
936 branch was taken, the offset is probably greater than 4 (the next
937 instruction), so it's safe to assume that an offset of 4 means we
938 did not take the branch. */
939 if (offset
== PPC_INSN_SIZE
)
940 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
941 from
+ PPC_INSN_SIZE
);
944 /* Check for LK bit indicating whether we should set the link
945 register to point to the next instruction
946 (1: Set, 0: Don't set). */
949 /* Link register needs to be set to the next instruction's PC. */
950 regcache_cooked_write_unsigned (regs
,
951 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
952 from
+ PPC_INSN_SIZE
);
954 fprintf_unfiltered (gdb_stdlog
,
955 "displaced: (ppc) adjusted LR to %s\n",
956 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
960 /* Check for breakpoints in the inferior. If we've found one, place the PC
961 right at the breakpoint instruction. */
962 else if ((insn
& BP_MASK
) == BP_INSN
)
963 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
965 /* Handle any other instructions that do not fit in the categories above. */
966 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
970 /* Always use hardware single-stepping to execute the
971 displaced instruction. */
973 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
974 struct displaced_step_closure
*closure
)
979 /* Checks for an atomic sequence of instructions beginning with a
980 Load And Reserve instruction and ending with a Store Conditional
981 instruction. If such a sequence is found, attempt to step through it.
982 A breakpoint is placed at the end of the sequence. */
983 std::vector
<CORE_ADDR
>
984 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
986 struct gdbarch
*gdbarch
= regcache
->arch ();
987 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
988 CORE_ADDR pc
= regcache_read_pc (regcache
);
989 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
991 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
992 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
995 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
996 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
997 int bc_insn_count
= 0; /* Conditional branch instruction count. */
999 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1000 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1003 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1005 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1007 loc
+= PPC_INSN_SIZE
;
1008 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1010 /* Assume that there is at most one conditional branch in the atomic
1011 sequence. If a conditional branch is found, put a breakpoint in
1012 its destination address. */
1013 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1015 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1016 int absolute
= insn
& 2;
1018 if (bc_insn_count
>= 1)
1019 return {}; /* More than one conditional branch found, fallback
1020 to the standard single-step code. */
1023 breaks
[1] = immediate
;
1025 breaks
[1] = loc
+ immediate
;
1031 if (IS_STORE_CONDITIONAL_INSN (insn
))
1035 /* Assume that the atomic sequence ends with a Store Conditional
1037 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1041 loc
+= PPC_INSN_SIZE
;
1043 /* Insert a breakpoint right after the end of the atomic sequence. */
1046 /* Check for duplicated breakpoints. Check also for a breakpoint
1047 placed (branch instruction's destination) anywhere in sequence. */
1049 && (breaks
[1] == breaks
[0]
1050 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1051 last_breakpoint
= 0;
1053 std::vector
<CORE_ADDR
> next_pcs
;
1055 for (index
= 0; index
<= last_breakpoint
; index
++)
1056 next_pcs
.push_back (breaks
[index
]);
1062 #define SIGNED_SHORT(x) \
1063 ((sizeof (short) == 2) \
1064 ? ((int)(short)(x)) \
1065 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1067 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1069 /* Limit the number of skipped non-prologue instructions, as the examining
1070 of the prologue is expensive. */
1071 static int max_skip_non_prologue_insns
= 10;
1073 /* Return nonzero if the given instruction OP can be part of the prologue
1074 of a function and saves a parameter on the stack. FRAMEP should be
1075 set if one of the previous instructions in the function has set the
1079 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1081 /* Move parameters from argument registers to temporary register. */
1082 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1084 /* Rx must be scratch register r0. */
1085 const int rx_regno
= (op
>> 16) & 31;
1086 /* Ry: Only r3 - r10 are used for parameter passing. */
1087 const int ry_regno
= GET_SRC_REG (op
);
1089 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1091 *r0_contains_arg
= 1;
1098 /* Save a General Purpose Register on stack. */
1100 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1101 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1103 /* Rx: Only r3 - r10 are used for parameter passing. */
1104 const int rx_regno
= GET_SRC_REG (op
);
1106 return (rx_regno
>= 3 && rx_regno
<= 10);
1109 /* Save a General Purpose Register on stack via the Frame Pointer. */
1112 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1113 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1114 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1116 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1117 However, the compiler sometimes uses r0 to hold an argument. */
1118 const int rx_regno
= GET_SRC_REG (op
);
1120 return ((rx_regno
>= 3 && rx_regno
<= 10)
1121 || (rx_regno
== 0 && *r0_contains_arg
));
1124 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1126 /* Only f2 - f8 are used for parameter passing. */
1127 const int src_regno
= GET_SRC_REG (op
);
1129 return (src_regno
>= 2 && src_regno
<= 8);
1132 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1134 /* Only f2 - f8 are used for parameter passing. */
1135 const int src_regno
= GET_SRC_REG (op
);
1137 return (src_regno
>= 2 && src_regno
<= 8);
1140 /* Not an insn that saves a parameter on stack. */
1144 /* Assuming that INSN is a "bl" instruction located at PC, return
1145 nonzero if the destination of the branch is a "blrl" instruction.
1147 This sequence is sometimes found in certain function prologues.
1148 It allows the function to load the LR register with a value that
1149 they can use to access PIC data using PC-relative offsets. */
1152 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1159 absolute
= (int) ((insn
>> 1) & 1);
1160 immediate
= ((insn
& ~3) << 6) >> 6;
1164 dest
= pc
+ immediate
;
1166 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1167 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1173 /* Return true if OP is a stw or std instruction with
1174 register operands RS and RA and any immediate offset.
1176 If WITH_UPDATE is true, also return true if OP is
1177 a stwu or stdu instruction with the same operands.
1179 Return false otherwise.
1182 store_insn_p (unsigned long op
, unsigned long rs
,
1183 unsigned long ra
, bool with_update
)
1188 if (/* std RS, SIMM(RA) */
1189 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1190 /* stw RS, SIMM(RA) */
1191 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1196 if (/* stdu RS, SIMM(RA) */
1197 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1198 /* stwu RS, SIMM(RA) */
1199 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1206 /* Masks for decoding a branch-and-link (bl) instruction.
1208 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1209 The former is anded with the opcode in question; if the result of
1210 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1211 question is a ``bl'' instruction.
1213 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1214 the branch displacement. */
1216 #define BL_MASK 0xfc000001
1217 #define BL_INSTRUCTION 0x48000001
1218 #define BL_DISPLACEMENT_MASK 0x03fffffc
1220 static unsigned long
1221 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1223 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1227 /* Fetch the instruction and convert it to an integer. */
1228 if (target_read_memory (pc
, buf
, 4))
1230 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1235 /* GCC generates several well-known sequences of instructions at the begining
1236 of each function prologue when compiling with -fstack-check. If one of
1237 such sequences starts at START_PC, then return the address of the
1238 instruction immediately past this sequence. Otherwise, return START_PC. */
1241 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1243 CORE_ADDR pc
= start_pc
;
1244 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1246 /* First possible sequence: A small number of probes.
1247 stw 0, -<some immediate>(1)
1248 [repeat this instruction any (small) number of times]. */
1250 if ((op
& 0xffff0000) == 0x90010000)
1252 while ((op
& 0xffff0000) == 0x90010000)
1255 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1260 /* Second sequence: A probing loop.
1261 addi 12,1,-<some immediate>
1262 lis 0,-<some immediate>
1263 [possibly ori 0,0,<some immediate>]
1267 addi 12,12,-<some immediate>
1270 [possibly one last probe: stw 0,<some immediate>(12)]. */
1274 /* addi 12,1,-<some immediate> */
1275 if ((op
& 0xffff0000) != 0x39810000)
1278 /* lis 0,-<some immediate> */
1280 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1281 if ((op
& 0xffff0000) != 0x3c000000)
1285 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1286 /* [possibly ori 0,0,<some immediate>] */
1287 if ((op
& 0xffff0000) == 0x60000000)
1290 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1293 if (op
!= 0x7c0c0214)
1298 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1299 if (op
!= 0x7c0c0000)
1304 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1305 if ((op
& 0xff9f0001) != 0x41820000)
1308 /* addi 12,12,-<some immediate> */
1310 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1311 if ((op
& 0xffff0000) != 0x398c0000)
1316 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1317 if (op
!= 0x900c0000)
1322 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1323 if ((op
& 0xfc000001) != 0x48000000)
1326 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1328 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1329 if ((op
& 0xffff0000) == 0x900c0000)
1332 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1335 /* We found a valid stack-check sequence, return the new PC. */
1339 /* Third sequence: No probe; instead, a comparizon between the stack size
1340 limit (saved in a run-time global variable) and the current stack
1343 addi 0,1,-<some immediate>
1344 lis 12,__gnat_stack_limit@ha
1345 lwz 12,__gnat_stack_limit@l(12)
1348 or, with a small variant in the case of a bigger stack frame:
1349 addis 0,1,<some immediate>
1350 addic 0,0,-<some immediate>
1351 lis 12,__gnat_stack_limit@ha
1352 lwz 12,__gnat_stack_limit@l(12)
1357 /* addi 0,1,-<some immediate> */
1358 if ((op
& 0xffff0000) != 0x38010000)
1360 /* small stack frame variant not recognized; try the
1361 big stack frame variant: */
1363 /* addis 0,1,<some immediate> */
1364 if ((op
& 0xffff0000) != 0x3c010000)
1367 /* addic 0,0,-<some immediate> */
1369 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1370 if ((op
& 0xffff0000) != 0x30000000)
1374 /* lis 12,<some immediate> */
1376 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1377 if ((op
& 0xffff0000) != 0x3d800000)
1380 /* lwz 12,<some immediate>(12) */
1382 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1383 if ((op
& 0xffff0000) != 0x818c0000)
1388 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1389 if ((op
& 0xfffffffe) != 0x7c406008)
1392 /* We found a valid stack-check sequence, return the new PC. */
1396 /* No stack check code in our prologue, return the start_pc. */
1400 /* return pc value after skipping a function prologue and also return
1401 information about a function frame.
1403 in struct rs6000_framedata fdata:
1404 - frameless is TRUE, if function does not have a frame.
1405 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1406 - offset is the initial size of this stack frame --- the amount by
1407 which we decrement the sp to allocate the frame.
1408 - saved_gpr is the number of the first saved gpr.
1409 - saved_fpr is the number of the first saved fpr.
1410 - saved_vr is the number of the first saved vr.
1411 - saved_ev is the number of the first saved ev.
1412 - alloca_reg is the number of the register used for alloca() handling.
1414 - gpr_offset is the offset of the first saved gpr from the previous frame.
1415 - fpr_offset is the offset of the first saved fpr from the previous frame.
1416 - vr_offset is the offset of the first saved vr from the previous frame.
1417 - ev_offset is the offset of the first saved ev from the previous frame.
1418 - lr_offset is the offset of the saved lr
1419 - cr_offset is the offset of the saved cr
1420 - vrsave_offset is the offset of the saved vrsave register. */
1423 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1424 struct rs6000_framedata
*fdata
)
1426 CORE_ADDR orig_pc
= pc
;
1427 CORE_ADDR last_prologue_pc
= pc
;
1428 CORE_ADDR li_found_pc
= 0;
1432 long alloca_reg_offset
= 0;
1433 long vr_saved_offset
= 0;
1439 int vrsave_reg
= -1;
1442 int minimal_toc_loaded
= 0;
1443 int prev_insn_was_prologue_insn
= 1;
1444 int num_skip_non_prologue_insns
= 0;
1445 int r0_contains_arg
= 0;
1446 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1447 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1448 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1450 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1451 fdata
->saved_gpr
= -1;
1452 fdata
->saved_fpr
= -1;
1453 fdata
->saved_vr
= -1;
1454 fdata
->saved_ev
= -1;
1455 fdata
->alloca_reg
= -1;
1456 fdata
->frameless
= 1;
1457 fdata
->nosavedpc
= 1;
1458 fdata
->lr_register
= -1;
1460 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1466 /* Sometimes it isn't clear if an instruction is a prologue
1467 instruction or not. When we encounter one of these ambiguous
1468 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1469 Otherwise, we'll assume that it really is a prologue instruction. */
1470 if (prev_insn_was_prologue_insn
)
1471 last_prologue_pc
= pc
;
1473 /* Stop scanning if we've hit the limit. */
1477 prev_insn_was_prologue_insn
= 1;
1479 /* Fetch the instruction and convert it to an integer. */
1480 if (target_read_memory (pc
, buf
, 4))
1482 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1484 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1486 /* Since shared library / PIC code, which needs to get its
1487 address at runtime, can appear to save more than one link
1501 remember just the first one, but skip over additional
1504 lr_reg
= (op
& 0x03e00000) >> 21;
1506 r0_contains_arg
= 0;
1509 else if ((op
& 0xfc1fffff) == 0x7c000026)
1511 cr_reg
= (op
& 0x03e00000) >> 21;
1513 r0_contains_arg
= 0;
1517 else if ((op
& 0xfc1f0000) == 0xd8010000)
1518 { /* stfd Rx,NUM(r1) */
1519 reg
= GET_SRC_REG (op
);
1520 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1522 fdata
->saved_fpr
= reg
;
1523 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1528 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1529 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1530 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1531 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1534 reg
= GET_SRC_REG (op
);
1535 if ((op
& 0xfc1f0000) == 0xbc010000)
1536 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1538 fdata
->gpr_mask
|= 1U << reg
;
1539 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1541 fdata
->saved_gpr
= reg
;
1542 if ((op
& 0xfc1f0003) == 0xf8010000)
1544 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1549 else if ((op
& 0xffff0000) == 0x3c4c0000
1550 || (op
& 0xffff0000) == 0x3c400000
1551 || (op
& 0xffff0000) == 0x38420000)
1553 /* . 0: addis 2,12,.TOC.-0b@ha
1554 . addi 2,2,.TOC.-0b@l
1558 used by ELFv2 global entry points to set up r2. */
1561 else if (op
== 0x60000000)
1564 /* Allow nops in the prologue, but do not consider them to
1565 be part of the prologue unless followed by other prologue
1567 prev_insn_was_prologue_insn
= 0;
1571 else if ((op
& 0xffff0000) == 0x3c000000)
1572 { /* addis 0,0,NUM, used for >= 32k frames */
1573 fdata
->offset
= (op
& 0x0000ffff) << 16;
1574 fdata
->frameless
= 0;
1575 r0_contains_arg
= 0;
1579 else if ((op
& 0xffff0000) == 0x60000000)
1580 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1581 fdata
->offset
|= (op
& 0x0000ffff);
1582 fdata
->frameless
= 0;
1583 r0_contains_arg
= 0;
1587 else if (lr_reg
>= 0 &&
1588 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1590 (store_insn_p (op
, lr_reg
,
1591 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1594 if (store_insn_p (op
, lr_reg
, 1, true))
1595 fdata
->lr_offset
= offset
;
1596 else /* LR save through frame pointer. */
1597 fdata
->lr_offset
= alloca_reg_offset
;
1599 fdata
->nosavedpc
= 0;
1600 /* Invalidate lr_reg, but don't set it to -1.
1601 That would mean that it had never been set. */
1603 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1604 (op
& 0xfc000000) == 0x90000000) /* stw */
1606 /* Does not update r1, so add displacement to lr_offset. */
1607 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1612 else if (cr_reg
>= 0 &&
1613 (store_insn_p (op
, cr_reg
, 1, true)))
1615 fdata
->cr_offset
= offset
;
1616 /* Invalidate cr_reg, but don't set it to -1.
1617 That would mean that it had never been set. */
1619 if ((op
& 0xfc000003) == 0xf8000000 ||
1620 (op
& 0xfc000000) == 0x90000000)
1622 /* Does not update r1, so add displacement to cr_offset. */
1623 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1628 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1630 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1631 prediction bits. If the LR has already been saved, we can
1635 else if (op
== 0x48000005)
1642 else if (op
== 0x48000004)
1647 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1648 in V.4 -mminimal-toc */
1649 (op
& 0xffff0000) == 0x3bde0000)
1650 { /* addi 30,30,foo@l */
1654 else if ((op
& 0xfc000001) == 0x48000001)
1658 fdata
->frameless
= 0;
1660 /* If the return address has already been saved, we can skip
1661 calls to blrl (for PIC). */
1662 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1668 /* Don't skip over the subroutine call if it is not within
1669 the first three instructions of the prologue and either
1670 we have no line table information or the line info tells
1671 us that the subroutine call is not part of the line
1672 associated with the prologue. */
1673 if ((pc
- orig_pc
) > 8)
1675 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1676 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1678 if ((prologue_sal
.line
== 0)
1679 || (prologue_sal
.line
!= this_sal
.line
))
1683 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1685 /* At this point, make sure this is not a trampoline
1686 function (a function that simply calls another functions,
1687 and nothing else). If the next is not a nop, this branch
1688 was part of the function prologue. */
1690 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1691 break; /* Don't skip over
1697 /* update stack pointer */
1698 else if ((op
& 0xfc1f0000) == 0x94010000)
1699 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1700 fdata
->frameless
= 0;
1701 fdata
->offset
= SIGNED_SHORT (op
);
1702 offset
= fdata
->offset
;
1705 else if ((op
& 0xfc1f07fa) == 0x7c01016a)
1706 { /* stwux rX,r1,rY || stdux rX,r1,rY */
1707 /* No way to figure out what r1 is going to be. */
1708 fdata
->frameless
= 0;
1709 offset
= fdata
->offset
;
1712 else if ((op
& 0xfc1f0003) == 0xf8010001)
1713 { /* stdu rX,NUM(r1) */
1714 fdata
->frameless
= 0;
1715 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1716 offset
= fdata
->offset
;
1719 else if ((op
& 0xffff0000) == 0x38210000)
1720 { /* addi r1,r1,SIMM */
1721 fdata
->frameless
= 0;
1722 fdata
->offset
+= SIGNED_SHORT (op
);
1723 offset
= fdata
->offset
;
1726 /* Load up minimal toc pointer. Do not treat an epilogue restore
1727 of r31 as a minimal TOC load. */
1728 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1729 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1731 && !minimal_toc_loaded
)
1733 minimal_toc_loaded
= 1;
1736 /* move parameters from argument registers to local variable
1739 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1740 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1741 (((op
>> 21) & 31) <= 10) &&
1742 ((long) ((op
>> 16) & 31)
1743 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1747 /* store parameters in stack */
1749 /* Move parameters from argument registers to temporary register. */
1750 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1754 /* Set up frame pointer */
1756 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1758 fdata
->frameless
= 0;
1760 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1761 alloca_reg_offset
= offset
;
1764 /* Another way to set up the frame pointer. */
1766 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1767 || op
== 0x7c3f0b78)
1769 fdata
->frameless
= 0;
1771 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1772 alloca_reg_offset
= offset
;
1775 /* Another way to set up the frame pointer. */
1777 else if ((op
& 0xfc1fffff) == 0x38010000)
1778 { /* addi rX, r1, 0x0 */
1779 fdata
->frameless
= 0;
1781 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1782 + ((op
& ~0x38010000) >> 21));
1783 alloca_reg_offset
= offset
;
1786 /* AltiVec related instructions. */
1787 /* Store the vrsave register (spr 256) in another register for
1788 later manipulation, or load a register into the vrsave
1789 register. 2 instructions are used: mfvrsave and
1790 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1791 and mtspr SPR256, Rn. */
1792 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1793 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1794 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1796 vrsave_reg
= GET_SRC_REG (op
);
1799 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1803 /* Store the register where vrsave was saved to onto the stack:
1804 rS is the register where vrsave was stored in a previous
1806 /* 100100 sssss 00001 dddddddd dddddddd */
1807 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1809 if (vrsave_reg
== GET_SRC_REG (op
))
1811 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1816 /* Compute the new value of vrsave, by modifying the register
1817 where vrsave was saved to. */
1818 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1819 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1823 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1824 in a pair of insns to save the vector registers on the
1826 /* 001110 00000 00000 iiii iiii iiii iiii */
1827 /* 001110 01110 00000 iiii iiii iiii iiii */
1828 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1829 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1831 if ((op
& 0xffff0000) == 0x38000000)
1832 r0_contains_arg
= 0;
1834 vr_saved_offset
= SIGNED_SHORT (op
);
1836 /* This insn by itself is not part of the prologue, unless
1837 if part of the pair of insns mentioned above. So do not
1838 record this insn as part of the prologue yet. */
1839 prev_insn_was_prologue_insn
= 0;
1841 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1842 /* 011111 sssss 11111 00000 00111001110 */
1843 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1845 if (pc
== (li_found_pc
+ 4))
1847 vr_reg
= GET_SRC_REG (op
);
1848 /* If this is the first vector reg to be saved, or if
1849 it has a lower number than others previously seen,
1850 reupdate the frame info. */
1851 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1853 fdata
->saved_vr
= vr_reg
;
1854 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1856 vr_saved_offset
= -1;
1861 /* End AltiVec related instructions. */
1863 /* Start BookE related instructions. */
1864 /* Store gen register S at (r31+uimm).
1865 Any register less than r13 is volatile, so we don't care. */
1866 /* 000100 sssss 11111 iiiii 01100100001 */
1867 else if (arch_info
->mach
== bfd_mach_ppc_e500
1868 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1870 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1873 ev_reg
= GET_SRC_REG (op
);
1874 imm
= (op
>> 11) & 0x1f;
1875 ev_offset
= imm
* 8;
1876 /* If this is the first vector reg to be saved, or if
1877 it has a lower number than others previously seen,
1878 reupdate the frame info. */
1879 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1881 fdata
->saved_ev
= ev_reg
;
1882 fdata
->ev_offset
= ev_offset
+ offset
;
1887 /* Store gen register rS at (r1+rB). */
1888 /* 000100 sssss 00001 bbbbb 01100100000 */
1889 else if (arch_info
->mach
== bfd_mach_ppc_e500
1890 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1892 if (pc
== (li_found_pc
+ 4))
1894 ev_reg
= GET_SRC_REG (op
);
1895 /* If this is the first vector reg to be saved, or if
1896 it has a lower number than others previously seen,
1897 reupdate the frame info. */
1898 /* We know the contents of rB from the previous instruction. */
1899 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1901 fdata
->saved_ev
= ev_reg
;
1902 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1904 vr_saved_offset
= -1;
1910 /* Store gen register r31 at (rA+uimm). */
1911 /* 000100 11111 aaaaa iiiii 01100100001 */
1912 else if (arch_info
->mach
== bfd_mach_ppc_e500
1913 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1915 /* Wwe know that the source register is 31 already, but
1916 it can't hurt to compute it. */
1917 ev_reg
= GET_SRC_REG (op
);
1918 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1919 /* If this is the first vector reg to be saved, or if
1920 it has a lower number than others previously seen,
1921 reupdate the frame info. */
1922 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1924 fdata
->saved_ev
= ev_reg
;
1925 fdata
->ev_offset
= ev_offset
+ offset
;
1930 /* Store gen register S at (r31+r0).
1931 Store param on stack when offset from SP bigger than 4 bytes. */
1932 /* 000100 sssss 11111 00000 01100100000 */
1933 else if (arch_info
->mach
== bfd_mach_ppc_e500
1934 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1936 if (pc
== (li_found_pc
+ 4))
1938 if ((op
& 0x03e00000) >= 0x01a00000)
1940 ev_reg
= GET_SRC_REG (op
);
1941 /* If this is the first vector reg to be saved, or if
1942 it has a lower number than others previously seen,
1943 reupdate the frame info. */
1944 /* We know the contents of r0 from the previous
1946 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1948 fdata
->saved_ev
= ev_reg
;
1949 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1953 vr_saved_offset
= -1;
1958 /* End BookE related instructions. */
1962 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
1964 /* Not a recognized prologue instruction.
1965 Handle optimizer code motions into the prologue by continuing
1966 the search if we have no valid frame yet or if the return
1967 address is not yet saved in the frame. Also skip instructions
1968 if some of the GPRs expected to be saved are not yet saved. */
1969 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
1970 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
1973 if (op
== 0x4e800020 /* blr */
1974 || op
== 0x4e800420) /* bctr */
1975 /* Do not scan past epilogue in frameless functions or
1978 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1979 /* Never skip branches. */
1982 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1983 /* Do not scan too many insns, scanning insns is expensive with
1987 /* Continue scanning. */
1988 prev_insn_was_prologue_insn
= 0;
1994 /* I have problems with skipping over __main() that I need to address
1995 * sometime. Previously, I used to use misc_function_vector which
1996 * didn't work as well as I wanted to be. -MGO */
1998 /* If the first thing after skipping a prolog is a branch to a function,
1999 this might be a call to an initializer in main(), introduced by gcc2.
2000 We'd like to skip over it as well. Fortunately, xlc does some extra
2001 work before calling a function right after a prologue, thus we can
2002 single out such gcc2 behaviour. */
2005 if ((op
& 0xfc000001) == 0x48000001)
2006 { /* bl foo, an initializer function? */
2007 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2009 if (op
== 0x4def7b82)
2010 { /* cror 0xf, 0xf, 0xf (nop) */
2012 /* Check and see if we are in main. If so, skip over this
2013 initializer function as well. */
2015 tmp
= find_pc_misc_function (pc
);
2017 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2023 if (pc
== lim_pc
&& lr_reg
>= 0)
2024 fdata
->lr_register
= lr_reg
;
2026 fdata
->offset
= -fdata
->offset
;
2027 return last_prologue_pc
;
2031 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2033 struct rs6000_framedata frame
;
2034 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2036 /* See if we can determine the end of the prologue via the symbol table.
2037 If so, then return either PC, or the PC after the prologue, whichever
2039 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2041 CORE_ADDR post_prologue_pc
2042 = skip_prologue_using_sal (gdbarch
, func_addr
);
2043 if (post_prologue_pc
!= 0)
2044 return std::max (pc
, post_prologue_pc
);
2047 /* Can't determine prologue from the symbol table, need to examine
2050 /* Find an upper limit on the function prologue using the debug
2051 information. If the debug information could not be used to provide
2052 that bound, then use an arbitrary large number as the upper bound. */
2053 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2055 limit_pc
= pc
+ 100; /* Magic. */
2057 /* Do not allow limit_pc to be past the function end, if we know
2058 where that end is... */
2059 if (func_end_addr
&& limit_pc
> func_end_addr
)
2060 limit_pc
= func_end_addr
;
2062 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2066 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2067 in the prologue of main().
2069 The function below examines the code pointed at by PC and checks to
2070 see if it corresponds to a call to __eabi. If so, it returns the
2071 address of the instruction following that call. Otherwise, it simply
2075 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2077 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2081 if (target_read_memory (pc
, buf
, 4))
2083 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2085 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2087 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2088 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2089 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2091 /* We check for ___eabi (three leading underscores) in addition
2092 to __eabi in case the GCC option "-fleading-underscore" was
2093 used to compile the program. */
2094 if (s
.minsym
!= NULL
2095 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2096 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2097 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2103 /* All the ABI's require 16 byte alignment. */
2105 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2107 return (addr
& -16);
2110 /* Return whether handle_inferior_event() should proceed through code
2111 starting at PC in function NAME when stepping.
2113 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2114 handle memory references that are too distant to fit in instructions
2115 generated by the compiler. For example, if 'foo' in the following
2120 is greater than 32767, the linker might replace the lwz with a branch to
2121 somewhere in @FIX1 that does the load in 2 instructions and then branches
2122 back to where execution should continue.
2124 GDB should silently step over @FIX code, just like AIX dbx does.
2125 Unfortunately, the linker uses the "b" instruction for the
2126 branches, meaning that the link register doesn't get set.
2127 Therefore, GDB's usual step_over_function () mechanism won't work.
2129 Instead, use the gdbarch_skip_trampoline_code and
2130 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2134 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2135 CORE_ADDR pc
, const char *name
)
2137 return name
&& startswith (name
, "@FIX");
2140 /* Skip code that the user doesn't want to see when stepping:
2142 1. Indirect function calls use a piece of trampoline code to do context
2143 switching, i.e. to set the new TOC table. Skip such code if we are on
2144 its first instruction (as when we have single-stepped to here).
2146 2. Skip shared library trampoline code (which is different from
2147 indirect function call trampolines).
2149 3. Skip bigtoc fixup code.
2151 Result is desired PC to step until, or NULL if we are not in
2152 code that should be skipped. */
2155 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2157 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2159 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2160 unsigned int ii
, op
;
2162 CORE_ADDR solib_target_pc
;
2163 struct bound_minimal_symbol msymbol
;
2165 static unsigned trampoline_code
[] =
2167 0x800b0000, /* l r0,0x0(r11) */
2168 0x90410014, /* st r2,0x14(r1) */
2169 0x7c0903a6, /* mtctr r0 */
2170 0x804b0004, /* l r2,0x4(r11) */
2171 0x816b0008, /* l r11,0x8(r11) */
2172 0x4e800420, /* bctr */
2173 0x4e800020, /* br */
2177 /* Check for bigtoc fixup code. */
2178 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2180 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2181 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2183 /* Double-check that the third instruction from PC is relative "b". */
2184 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2185 if ((op
& 0xfc000003) == 0x48000000)
2187 /* Extract bits 6-29 as a signed 24-bit relative word address and
2188 add it to the containing PC. */
2189 rel
= ((int)(op
<< 6) >> 6);
2190 return pc
+ 8 + rel
;
2194 /* If pc is in a shared library trampoline, return its target. */
2195 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2196 if (solib_target_pc
)
2197 return solib_target_pc
;
2199 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2201 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2202 if (op
!= trampoline_code
[ii
])
2205 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2207 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2211 /* ISA-specific vector types. */
2213 static struct type
*
2214 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2216 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2218 if (!tdep
->ppc_builtin_type_vec64
)
2220 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2222 /* The type we're building is this: */
2224 union __gdb_builtin_type_vec64
2228 int32_t v2_int32
[2];
2229 int16_t v4_int16
[4];
2236 t
= arch_composite_type (gdbarch
,
2237 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2238 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2239 append_composite_type_field (t
, "v2_float",
2240 init_vector_type (bt
->builtin_float
, 2));
2241 append_composite_type_field (t
, "v2_int32",
2242 init_vector_type (bt
->builtin_int32
, 2));
2243 append_composite_type_field (t
, "v4_int16",
2244 init_vector_type (bt
->builtin_int16
, 4));
2245 append_composite_type_field (t
, "v8_int8",
2246 init_vector_type (bt
->builtin_int8
, 8));
2248 TYPE_VECTOR (t
) = 1;
2249 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2250 tdep
->ppc_builtin_type_vec64
= t
;
2253 return tdep
->ppc_builtin_type_vec64
;
2256 /* Vector 128 type. */
2258 static struct type
*
2259 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2261 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2263 if (!tdep
->ppc_builtin_type_vec128
)
2265 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2267 /* The type we're building is this
2269 type = union __ppc_builtin_type_vec128 {
2271 double v2_double[2];
2273 int32_t v4_int32[4];
2274 int16_t v8_int16[8];
2275 int8_t v16_int8[16];
2281 t
= arch_composite_type (gdbarch
,
2282 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2283 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2284 append_composite_type_field (t
, "v2_double",
2285 init_vector_type (bt
->builtin_double
, 2));
2286 append_composite_type_field (t
, "v4_float",
2287 init_vector_type (bt
->builtin_float
, 4));
2288 append_composite_type_field (t
, "v4_int32",
2289 init_vector_type (bt
->builtin_int32
, 4));
2290 append_composite_type_field (t
, "v8_int16",
2291 init_vector_type (bt
->builtin_int16
, 8));
2292 append_composite_type_field (t
, "v16_int8",
2293 init_vector_type (bt
->builtin_int8
, 16));
2295 TYPE_VECTOR (t
) = 1;
2296 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2297 tdep
->ppc_builtin_type_vec128
= t
;
2300 return tdep
->ppc_builtin_type_vec128
;
2303 /* Return the name of register number REGNO, or the empty string if it
2304 is an anonymous register. */
2307 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2309 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2311 /* The upper half "registers" have names in the XML description,
2312 but we present only the low GPRs and the full 64-bit registers
2314 if (tdep
->ppc_ev0_upper_regnum
>= 0
2315 && tdep
->ppc_ev0_upper_regnum
<= regno
2316 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2319 /* Hide the upper halves of the vs0~vs31 registers. */
2320 if (tdep
->ppc_vsr0_regnum
>= 0
2321 && tdep
->ppc_vsr0_upper_regnum
<= regno
2322 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2325 /* Check if the SPE pseudo registers are available. */
2326 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2328 static const char *const spe_regnames
[] = {
2329 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2330 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2331 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2332 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2334 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2337 /* Check if the decimal128 pseudo-registers are available. */
2338 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2340 static const char *const dfp128_regnames
[] = {
2341 "dl0", "dl1", "dl2", "dl3",
2342 "dl4", "dl5", "dl6", "dl7",
2343 "dl8", "dl9", "dl10", "dl11",
2344 "dl12", "dl13", "dl14", "dl15"
2346 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2349 /* Check if this is a VSX pseudo-register. */
2350 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2352 static const char *const vsx_regnames
[] = {
2353 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2354 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2355 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2356 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2357 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2358 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2359 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2360 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2361 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2363 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2366 /* Check if the this is a Extended FP pseudo-register. */
2367 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2369 static const char *const efpr_regnames
[] = {
2370 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2371 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2372 "f46", "f47", "f48", "f49", "f50", "f51",
2373 "f52", "f53", "f54", "f55", "f56", "f57",
2374 "f58", "f59", "f60", "f61", "f62", "f63"
2376 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2379 return tdesc_register_name (gdbarch
, regno
);
2382 /* Return the GDB type object for the "standard" data type of data in
2385 static struct type
*
2386 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2388 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2390 /* These are the only pseudo-registers we support. */
2391 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2392 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2393 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2394 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2396 /* These are the e500 pseudo-registers. */
2397 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2398 return rs6000_builtin_type_vec64 (gdbarch
);
2399 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2400 /* PPC decimal128 pseudo-registers. */
2401 return builtin_type (gdbarch
)->builtin_declong
;
2402 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2403 /* POWER7 VSX pseudo-registers. */
2404 return rs6000_builtin_type_vec128 (gdbarch
);
2406 /* POWER7 Extended FP pseudo-registers. */
2407 return builtin_type (gdbarch
)->builtin_double
;
2410 /* The register format for RS/6000 floating point registers is always
2411 double, we need a conversion if the memory format is float. */
2414 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2417 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2419 return (tdep
->ppc_fp0_regnum
>= 0
2420 && regnum
>= tdep
->ppc_fp0_regnum
2421 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2422 && TYPE_CODE (type
) == TYPE_CODE_FLT
2423 && TYPE_LENGTH (type
)
2424 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2428 rs6000_register_to_value (struct frame_info
*frame
,
2432 int *optimizedp
, int *unavailablep
)
2434 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2435 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2437 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2439 if (!get_frame_register_bytes (frame
, regnum
, 0,
2440 register_size (gdbarch
, regnum
),
2441 from
, optimizedp
, unavailablep
))
2444 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2446 *optimizedp
= *unavailablep
= 0;
2451 rs6000_value_to_register (struct frame_info
*frame
,
2454 const gdb_byte
*from
)
2456 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2457 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2459 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2461 target_float_convert (from
, type
,
2462 to
, builtin_type (gdbarch
)->builtin_double
);
2463 put_frame_register (frame
, regnum
, to
);
2466 /* The type of a function that moves the value of REG between CACHE
2467 or BUF --- in either direction. */
2468 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2471 /* Move SPE vector register values between a 64-bit buffer and the two
2472 32-bit raw register halves in a regcache. This function handles
2473 both splitting a 64-bit value into two 32-bit halves, and joining
2474 two halves into a whole 64-bit value, depending on the function
2475 passed as the MOVE argument.
2477 EV_REG must be the number of an SPE evN vector register --- a
2478 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2481 Call MOVE once for each 32-bit half of that register, passing
2482 REGCACHE, the number of the raw register corresponding to that
2483 half, and the address of the appropriate half of BUFFER.
2485 For example, passing 'regcache_raw_read' as the MOVE function will
2486 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2487 'regcache_raw_supply' will supply the contents of BUFFER to the
2488 appropriate pair of raw registers in REGCACHE.
2490 You may need to cast away some 'const' qualifiers when passing
2491 MOVE, since this function can't tell at compile-time which of
2492 REGCACHE or BUFFER is acting as the source of the data. If C had
2493 co-variant type qualifiers, ... */
2495 static enum register_status
2496 e500_move_ev_register (move_ev_register_func move
,
2497 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2499 struct gdbarch
*arch
= regcache
->arch ();
2500 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2502 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2503 enum register_status status
;
2505 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2507 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2509 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2511 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2513 if (status
== REG_VALID
)
2514 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2519 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2520 if (status
== REG_VALID
)
2521 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2528 static enum register_status
2529 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2531 regcache
->raw_write (regnum
, (const gdb_byte
*) buffer
);
2536 static enum register_status
2537 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2538 int ev_reg
, gdb_byte
*buffer
)
2540 struct gdbarch
*arch
= regcache
->arch ();
2541 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2543 enum register_status status
;
2545 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2547 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2549 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2551 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2553 if (status
== REG_VALID
)
2554 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2559 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2560 if (status
== REG_VALID
)
2561 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2570 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2571 int reg_nr
, const gdb_byte
*buffer
)
2573 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2574 reg_nr
, (void *) buffer
);
2577 /* Read method for DFP pseudo-registers. */
2578 static enum register_status
2579 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2580 int reg_nr
, gdb_byte
*buffer
)
2582 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2583 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2584 enum register_status status
;
2586 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2588 /* Read two FP registers to form a whole dl register. */
2589 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2590 2 * reg_index
, buffer
);
2591 if (status
== REG_VALID
)
2592 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2593 2 * reg_index
+ 1, buffer
+ 8);
2597 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2598 2 * reg_index
+ 1, buffer
);
2599 if (status
== REG_VALID
)
2600 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2601 2 * reg_index
, buffer
+ 8);
2607 /* Write method for DFP pseudo-registers. */
2609 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2610 int reg_nr
, const gdb_byte
*buffer
)
2612 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2613 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2615 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2617 /* Write each half of the dl register into a separate
2619 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2620 2 * reg_index
, buffer
);
2621 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2622 2 * reg_index
+ 1, buffer
+ 8);
2626 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2627 2 * reg_index
+ 1, buffer
);
2628 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2629 2 * reg_index
, buffer
+ 8);
2633 /* Read method for POWER7 VSX pseudo-registers. */
2634 static enum register_status
2635 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2636 int reg_nr
, gdb_byte
*buffer
)
2638 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2639 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2640 enum register_status status
;
2642 /* Read the portion that overlaps the VMX registers. */
2644 status
= regcache
->raw_read (tdep
->ppc_vr0_regnum
+
2645 reg_index
- 32, buffer
);
2647 /* Read the portion that overlaps the FPR registers. */
2648 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2650 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2652 if (status
== REG_VALID
)
2653 status
= regcache
->raw_read (tdep
->ppc_vsr0_upper_regnum
+
2654 reg_index
, buffer
+ 8);
2658 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2659 reg_index
, buffer
+ 8);
2660 if (status
== REG_VALID
)
2661 status
= regcache
->raw_read (tdep
->ppc_vsr0_upper_regnum
+
2668 /* Write method for POWER7 VSX pseudo-registers. */
2670 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2671 int reg_nr
, const gdb_byte
*buffer
)
2673 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2674 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2676 /* Write the portion that overlaps the VMX registers. */
2678 regcache
->raw_write (tdep
->ppc_vr0_regnum
+
2679 reg_index
- 32, buffer
);
2681 /* Write the portion that overlaps the FPR registers. */
2682 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2684 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2686 regcache
->raw_write (tdep
->ppc_vsr0_upper_regnum
+
2687 reg_index
, buffer
+ 8);
2691 regcache
->raw_write (tdep
->ppc_fp0_regnum
+
2692 reg_index
, buffer
+ 8);
2693 regcache
->raw_write (tdep
->ppc_vsr0_upper_regnum
+
2698 /* Read method for POWER7 Extended FP pseudo-registers. */
2699 static enum register_status
2700 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2701 int reg_nr
, gdb_byte
*buffer
)
2703 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2704 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2705 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2707 /* Read the portion that overlaps the VMX register. */
2708 return regcache
->raw_read_part (tdep
->ppc_vr0_regnum
+ reg_index
,
2709 offset
, register_size (gdbarch
, reg_nr
),
2713 /* Write method for POWER7 Extended FP pseudo-registers. */
2715 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2716 int reg_nr
, const gdb_byte
*buffer
)
2718 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2719 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2720 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2722 /* Write the portion that overlaps the VMX register. */
2723 regcache
->raw_write_part (tdep
->ppc_vr0_regnum
+ reg_index
, offset
,
2724 register_size (gdbarch
, reg_nr
), buffer
);
2727 static enum register_status
2728 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2729 readable_regcache
*regcache
,
2730 int reg_nr
, gdb_byte
*buffer
)
2732 struct gdbarch
*regcache_arch
= regcache
->arch ();
2733 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2735 gdb_assert (regcache_arch
== gdbarch
);
2737 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2738 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2739 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2740 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2741 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2742 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2743 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2744 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2746 internal_error (__FILE__
, __LINE__
,
2747 _("rs6000_pseudo_register_read: "
2748 "called on unexpected register '%s' (%d)"),
2749 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2753 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2754 struct regcache
*regcache
,
2755 int reg_nr
, const gdb_byte
*buffer
)
2757 struct gdbarch
*regcache_arch
= regcache
->arch ();
2758 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2760 gdb_assert (regcache_arch
== gdbarch
);
2762 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2763 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2764 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2765 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2766 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2767 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2768 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2769 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2771 internal_error (__FILE__
, __LINE__
,
2772 _("rs6000_pseudo_register_write: "
2773 "called on unexpected register '%s' (%d)"),
2774 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2778 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2779 struct agent_expr
*ax
, int reg_nr
)
2781 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2782 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2784 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
2785 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
2786 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
2788 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2790 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2791 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
);
2792 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
+ 1);
2794 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2796 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2799 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
- 32);
2803 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ reg_index
);
2804 ax_reg_mask (ax
, tdep
->ppc_vsr0_upper_regnum
+ reg_index
);
2807 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2809 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2810 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
);
2813 internal_error (__FILE__
, __LINE__
,
2814 _("rs6000_pseudo_register_collect: "
2815 "called on unexpected register '%s' (%d)"),
2816 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2822 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
2823 struct agent_expr
*ax
, struct axs_value
*value
,
2826 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2827 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
2828 value
->kind
= axs_lvalue_register
;
2829 value
->u
.reg
= tdep
->ppc_lr_regnum
;
2833 /* Convert a DBX STABS register number to a GDB register number. */
2835 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2837 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2839 if (0 <= num
&& num
<= 31)
2840 return tdep
->ppc_gp0_regnum
+ num
;
2841 else if (32 <= num
&& num
<= 63)
2842 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2843 specifies registers the architecture doesn't have? Our
2844 callers don't check the value we return. */
2845 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2846 else if (77 <= num
&& num
<= 108)
2847 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2848 else if (1200 <= num
&& num
< 1200 + 32)
2849 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2854 return tdep
->ppc_mq_regnum
;
2856 return tdep
->ppc_lr_regnum
;
2858 return tdep
->ppc_ctr_regnum
;
2860 return tdep
->ppc_xer_regnum
;
2862 return tdep
->ppc_vrsave_regnum
;
2864 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2866 return tdep
->ppc_acc_regnum
;
2868 return tdep
->ppc_spefscr_regnum
;
2875 /* Convert a Dwarf 2 register number to a GDB register number. */
2877 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2879 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2881 if (0 <= num
&& num
<= 31)
2882 return tdep
->ppc_gp0_regnum
+ num
;
2883 else if (32 <= num
&& num
<= 63)
2884 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2885 specifies registers the architecture doesn't have? Our
2886 callers don't check the value we return. */
2887 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2888 else if (1124 <= num
&& num
< 1124 + 32)
2889 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2890 else if (1200 <= num
&& num
< 1200 + 32)
2891 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2896 return tdep
->ppc_cr_regnum
;
2898 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2900 return tdep
->ppc_acc_regnum
;
2902 return tdep
->ppc_mq_regnum
;
2904 return tdep
->ppc_xer_regnum
;
2906 return tdep
->ppc_lr_regnum
;
2908 return tdep
->ppc_ctr_regnum
;
2910 return tdep
->ppc_vrsave_regnum
;
2912 return tdep
->ppc_spefscr_regnum
;
2918 /* Translate a .eh_frame register to DWARF register, or adjust a
2919 .debug_frame register. */
2922 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2924 /* GCC releases before 3.4 use GCC internal register numbering in
2925 .debug_frame (and .debug_info, et cetera). The numbering is
2926 different from the standard SysV numbering for everything except
2927 for GPRs and FPRs. We can not detect this problem in most cases
2928 - to get accurate debug info for variables living in lr, ctr, v0,
2929 et cetera, use a newer version of GCC. But we must detect
2930 one important case - lr is in column 65 in .debug_frame output,
2933 GCC 3.4, and the "hammer" branch, have a related problem. They
2934 record lr register saves in .debug_frame as 108, but still record
2935 the return column as 65. We fix that up too.
2937 We can do this because 65 is assigned to fpsr, and GCC never
2938 generates debug info referring to it. To add support for
2939 handwritten debug info that restores fpsr, we would need to add a
2940 producer version check to this. */
2949 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2950 internal register numbering; translate that to the standard DWARF2
2951 register numbering. */
2952 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2954 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2955 return num
- 68 + 86;
2956 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2957 return num
- 77 + 1124;
2969 case 109: /* vrsave */
2971 case 110: /* vscr */
2973 case 111: /* spe_acc */
2975 case 112: /* spefscr */
2983 /* Handling the various POWER/PowerPC variants. */
2985 /* Information about a particular processor variant. */
2989 /* Name of this variant. */
2992 /* English description of the variant. */
2993 const char *description
;
2995 /* bfd_arch_info.arch corresponding to variant. */
2996 enum bfd_architecture arch
;
2998 /* bfd_arch_info.mach corresponding to variant. */
3001 /* Target description for this variant. */
3002 struct target_desc
**tdesc
;
3005 static struct variant variants
[] =
3007 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3008 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3009 {"power", "POWER user-level", bfd_arch_rs6000
,
3010 bfd_mach_rs6k
, &tdesc_rs6000
},
3011 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3012 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3013 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3014 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3015 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3016 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3017 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3018 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3019 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3020 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3021 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3022 604, &tdesc_powerpc_604
},
3023 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3024 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3025 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3026 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3027 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3028 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3029 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3030 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3031 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3032 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3033 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3034 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3037 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3038 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3039 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3040 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3041 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3042 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3043 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3044 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3045 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3046 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3047 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3048 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3050 /* FIXME: I haven't checked the register sets of the following. */
3051 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3052 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3053 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3054 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3055 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3056 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3058 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3061 /* Return the variant corresponding to architecture ARCH and machine number
3062 MACH. If no such variant exists, return null. */
3064 static const struct variant
*
3065 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3067 const struct variant
*v
;
3069 for (v
= variants
; v
->name
; v
++)
3070 if (arch
== v
->arch
&& mach
== v
->mach
)
3078 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3080 return frame_unwind_register_unsigned (next_frame
,
3081 gdbarch_pc_regnum (gdbarch
));
3084 static struct frame_id
3085 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3087 return frame_id_build (get_frame_register_unsigned
3088 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3089 get_frame_pc (this_frame
));
3092 struct rs6000_frame_cache
3095 CORE_ADDR initial_sp
;
3096 struct trad_frame_saved_reg
*saved_regs
;
3098 /* Set BASE_P to true if this frame cache is properly initialized.
3099 Otherwise set to false because some registers or memory cannot
3102 /* Cache PC for building unavailable frame. */
3106 static struct rs6000_frame_cache
*
3107 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3109 struct rs6000_frame_cache
*cache
;
3110 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3111 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3112 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3113 struct rs6000_framedata fdata
;
3114 int wordsize
= tdep
->wordsize
;
3115 CORE_ADDR func
= 0, pc
= 0;
3117 if ((*this_cache
) != NULL
)
3118 return (struct rs6000_frame_cache
*) (*this_cache
);
3119 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3120 (*this_cache
) = cache
;
3122 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3126 func
= get_frame_func (this_frame
);
3128 pc
= get_frame_pc (this_frame
);
3129 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3131 /* Figure out the parent's stack pointer. */
3133 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3134 address of the current frame. Things might be easier if the
3135 ->frame pointed to the outer-most address of the frame. In
3136 the mean time, the address of the prev frame is used as the
3137 base address of this frame. */
3138 cache
->base
= get_frame_register_unsigned
3139 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3141 CATCH (ex
, RETURN_MASK_ERROR
)
3143 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3144 throw_exception (ex
);
3145 return (struct rs6000_frame_cache
*) (*this_cache
);
3149 /* If the function appears to be frameless, check a couple of likely
3150 indicators that we have simply failed to find the frame setup.
3151 Two common cases of this are missing symbols (i.e.
3152 get_frame_func returns the wrong address or 0), and assembly
3153 stubs which have a fast exit path but set up a frame on the slow
3156 If the LR appears to return to this function, then presume that
3157 we have an ABI compliant frame that we failed to find. */
3158 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3163 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3164 if (func
== 0 && saved_lr
== pc
)
3168 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3169 if (func
== saved_func
)
3175 fdata
.frameless
= 0;
3176 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3180 if (!fdata
.frameless
)
3182 /* Frameless really means stackless. */
3185 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3186 byte_order
, &backchain
))
3187 cache
->base
= (CORE_ADDR
) backchain
;
3190 trad_frame_set_value (cache
->saved_regs
,
3191 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3193 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3194 All fpr's from saved_fpr to fp31 are saved. */
3196 if (fdata
.saved_fpr
>= 0)
3199 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3201 /* If skip_prologue says floating-point registers were saved,
3202 but the current architecture has no floating-point registers,
3203 then that's strange. But we have no indices to even record
3204 the addresses under, so we just ignore it. */
3205 if (ppc_floating_point_unit_p (gdbarch
))
3206 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3208 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3213 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3214 All gpr's from saved_gpr to gpr31 are saved (except during the
3217 if (fdata
.saved_gpr
>= 0)
3220 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3221 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3223 if (fdata
.gpr_mask
& (1U << i
))
3224 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3225 gpr_addr
+= wordsize
;
3229 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3230 All vr's from saved_vr to vr31 are saved. */
3231 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3233 if (fdata
.saved_vr
>= 0)
3236 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3237 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3239 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3240 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3245 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3246 All vr's from saved_ev to ev31 are saved. ????? */
3247 if (tdep
->ppc_ev0_regnum
!= -1)
3249 if (fdata
.saved_ev
>= 0)
3252 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3253 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3255 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3257 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3258 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3259 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3264 /* If != 0, fdata.cr_offset is the offset from the frame that
3266 if (fdata
.cr_offset
!= 0)
3267 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3268 = cache
->base
+ fdata
.cr_offset
;
3270 /* If != 0, fdata.lr_offset is the offset from the frame that
3272 if (fdata
.lr_offset
!= 0)
3273 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3274 = cache
->base
+ fdata
.lr_offset
;
3275 else if (fdata
.lr_register
!= -1)
3276 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3277 /* The PC is found in the link register. */
3278 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3279 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3281 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3282 holds the VRSAVE. */
3283 if (fdata
.vrsave_offset
!= 0)
3284 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3285 = cache
->base
+ fdata
.vrsave_offset
;
3287 if (fdata
.alloca_reg
< 0)
3288 /* If no alloca register used, then fi->frame is the value of the
3289 %sp for this frame, and it is good enough. */
3291 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3294 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3301 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3302 struct frame_id
*this_id
)
3304 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3309 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3313 /* This marks the outermost frame. */
3314 if (info
->base
== 0)
3317 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3320 static struct value
*
3321 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3322 void **this_cache
, int regnum
)
3324 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3326 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3329 static const struct frame_unwind rs6000_frame_unwind
=
3332 default_frame_unwind_stop_reason
,
3333 rs6000_frame_this_id
,
3334 rs6000_frame_prev_register
,
3336 default_frame_sniffer
3339 /* Allocate and initialize a frame cache for an epilogue frame.
3340 SP is restored and prev-PC is stored in LR. */
3342 static struct rs6000_frame_cache
*
3343 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3345 struct rs6000_frame_cache
*cache
;
3346 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3347 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3350 return (struct rs6000_frame_cache
*) *this_cache
;
3352 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3353 (*this_cache
) = cache
;
3354 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3358 /* At this point the stack looks as if we just entered the
3359 function, and the return address is stored in LR. */
3362 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3363 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3366 cache
->initial_sp
= sp
;
3368 trad_frame_set_value (cache
->saved_regs
,
3369 gdbarch_pc_regnum (gdbarch
), lr
);
3371 CATCH (ex
, RETURN_MASK_ERROR
)
3373 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3374 throw_exception (ex
);
3381 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3382 Return the frame ID of an epilogue frame. */
3385 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3386 void **this_cache
, struct frame_id
*this_id
)
3389 struct rs6000_frame_cache
*info
=
3390 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3392 pc
= get_frame_func (this_frame
);
3393 if (info
->base
== 0)
3394 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3396 (*this_id
) = frame_id_build (info
->base
, pc
);
3399 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3400 Return the register value of REGNUM in previous frame. */
3402 static struct value
*
3403 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3404 void **this_cache
, int regnum
)
3406 struct rs6000_frame_cache
*info
=
3407 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3408 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3411 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3412 Check whether this an epilogue frame. */
3415 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3416 struct frame_info
*this_frame
,
3417 void **this_prologue_cache
)
3419 if (frame_relative_level (this_frame
) == 0)
3420 return rs6000_in_function_epilogue_frame_p (this_frame
,
3421 get_frame_arch (this_frame
),
3422 get_frame_pc (this_frame
));
3427 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3428 a function without debug information. */
3430 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3433 default_frame_unwind_stop_reason
,
3434 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3436 rs6000_epilogue_frame_sniffer
3441 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3443 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3445 return info
->initial_sp
;
3448 static const struct frame_base rs6000_frame_base
= {
3449 &rs6000_frame_unwind
,
3450 rs6000_frame_base_address
,
3451 rs6000_frame_base_address
,
3452 rs6000_frame_base_address
3455 static const struct frame_base
*
3456 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3458 return &rs6000_frame_base
;
3461 /* DWARF-2 frame support. Used to handle the detection of
3462 clobbered registers during function calls. */
3465 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3466 struct dwarf2_frame_state_reg
*reg
,
3467 struct frame_info
*this_frame
)
3469 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3471 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3472 non-volatile registers. We will use the same code for both. */
3474 /* Call-saved GP registers. */
3475 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3476 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3477 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3478 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3480 /* Call-clobbered GP registers. */
3481 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3482 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3483 || (regnum
== tdep
->ppc_gp0_regnum
))
3484 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3486 /* Deal with FP registers, if supported. */
3487 if (tdep
->ppc_fp0_regnum
>= 0)
3489 /* Call-saved FP registers. */
3490 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3491 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3492 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3494 /* Call-clobbered FP registers. */
3495 if ((regnum
>= tdep
->ppc_fp0_regnum
3496 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3497 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3500 /* Deal with ALTIVEC registers, if supported. */
3501 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3503 /* Call-saved Altivec registers. */
3504 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3505 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3506 || regnum
== tdep
->ppc_vrsave_regnum
)
3507 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3509 /* Call-clobbered Altivec registers. */
3510 if ((regnum
>= tdep
->ppc_vr0_regnum
3511 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3512 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3515 /* Handle PC register and Stack Pointer correctly. */
3516 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3517 reg
->how
= DWARF2_FRAME_REG_RA
;
3518 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3519 reg
->how
= DWARF2_FRAME_REG_CFA
;
3523 /* Return true if a .gnu_attributes section exists in BFD and it
3524 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3525 section exists in BFD and it indicates that SPE extensions are in
3526 use. Check the .gnu.attributes section first, as the binary might be
3527 compiled for SPE, but not actually using SPE instructions. */
3530 bfd_uses_spe_extensions (bfd
*abfd
)
3533 gdb_byte
*contents
= NULL
;
3542 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3543 could be using the SPE vector abi without actually using any spe
3544 bits whatsoever. But it's close enough for now. */
3545 int vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3546 Tag_GNU_Power_ABI_Vector
);
3547 if (vector_abi
== 3)
3551 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3555 size
= bfd_get_section_size (sect
);
3556 contents
= (gdb_byte
*) xmalloc (size
);
3557 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3563 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3569 char name[name_len rounded up to 4-byte alignment];
3570 char data[data_len];
3573 Technically, there's only supposed to be one such structure in a
3574 given apuinfo section, but the linker is not always vigilant about
3575 merging apuinfo sections from input files. Just go ahead and parse
3576 them all, exiting early when we discover the binary uses SPE
3579 It's not specified in what endianness the information in this
3580 section is stored. Assume that it's the endianness of the BFD. */
3584 unsigned int name_len
;
3585 unsigned int data_len
;
3588 /* If we can't read the first three fields, we're done. */
3592 name_len
= bfd_get_32 (abfd
, ptr
);
3593 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3594 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3595 type
= bfd_get_32 (abfd
, ptr
+ 8);
3598 /* The name must be "APUinfo\0". */
3600 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3604 /* The type must be 2. */
3608 /* The data is stored as a series of uint32. The upper half of
3609 each uint32 indicates the particular APU used and the lower
3610 half indicates the revision of that APU. We just care about
3613 /* Not 4-byte quantities. */
3619 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3620 unsigned int apu
= apuinfo
>> 16;
3624 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3626 if (apu
== 0x100 || apu
== 0x101)
3641 /* These are macros for parsing instruction fields (I.1.6.28) */
3643 #define PPC_FIELD(value, from, len) \
3644 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3645 #define PPC_SEXT(v, bs) \
3646 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3647 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3648 - ((CORE_ADDR) 1 << ((bs) - 1)))
3649 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3650 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3651 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3652 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3653 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3654 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3655 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3656 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3657 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3658 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3659 | (PPC_FIELD (insn, 16, 5) << 5))
3660 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3661 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3662 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3663 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3664 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3665 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3666 #define PPC_OE(insn) PPC_BIT (insn, 21)
3667 #define PPC_RC(insn) PPC_BIT (insn, 31)
3668 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3669 #define PPC_LK(insn) PPC_BIT (insn, 31)
3670 #define PPC_TX(insn) PPC_BIT (insn, 31)
3671 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3673 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3674 #define PPC_XER_NB(xer) (xer & 0x7f)
3676 /* Record Vector-Scalar Registers.
3677 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3678 Otherwise, it's just a VR register. Record them accordingly. */
3681 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3683 if (vsr
< 0 || vsr
>= 64)
3688 if (tdep
->ppc_vr0_regnum
>= 0)
3689 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3693 if (tdep
->ppc_fp0_regnum
>= 0)
3694 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3695 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3696 record_full_arch_list_add_reg (regcache
,
3697 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3703 /* Parse and record instructions primary opcode-4 at ADDR.
3704 Return 0 if successful. */
3707 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3708 CORE_ADDR addr
, uint32_t insn
)
3710 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3711 int ext
= PPC_FIELD (insn
, 21, 11);
3712 int vra
= PPC_FIELD (insn
, 11, 5);
3716 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3717 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3718 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3719 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3720 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3722 case 42: /* Vector Select */
3723 case 43: /* Vector Permute */
3724 case 59: /* Vector Permute Right-indexed */
3725 case 44: /* Vector Shift Left Double by Octet Immediate */
3726 case 45: /* Vector Permute and Exclusive-OR */
3727 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3728 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3729 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3730 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3731 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3732 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3733 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3734 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3735 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3736 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3737 case 46: /* Vector Multiply-Add Single-Precision */
3738 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3739 record_full_arch_list_add_reg (regcache
,
3740 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3743 case 48: /* Multiply-Add High Doubleword */
3744 case 49: /* Multiply-Add High Doubleword Unsigned */
3745 case 51: /* Multiply-Add Low Doubleword */
3746 record_full_arch_list_add_reg (regcache
,
3747 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3751 switch ((ext
& 0x1ff))
3754 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
3755 && vra
!= 2 /* Decimal Convert From Signed Quadword */
3756 && vra
!= 4 /* Decimal Convert To Zoned */
3757 && vra
!= 5 /* Decimal Convert To National */
3758 && vra
!= 6 /* Decimal Convert From Zoned */
3759 && vra
!= 7 /* Decimal Convert From National */
3760 && vra
!= 31) /* Decimal Set Sign */
3763 /* 5.16 Decimal Integer Arithmetic Instructions */
3764 case 1: /* Decimal Add Modulo */
3765 case 65: /* Decimal Subtract Modulo */
3767 case 193: /* Decimal Shift */
3768 case 129: /* Decimal Unsigned Shift */
3769 case 449: /* Decimal Shift and Round */
3771 case 257: /* Decimal Truncate */
3772 case 321: /* Decimal Unsigned Truncate */
3774 /* Bit-21 should be set. */
3775 if (!PPC_BIT (insn
, 21))
3778 record_full_arch_list_add_reg (regcache
,
3779 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3780 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3784 /* Bit-21 is used for RC */
3785 switch (ext
& 0x3ff)
3787 case 6: /* Vector Compare Equal To Unsigned Byte */
3788 case 70: /* Vector Compare Equal To Unsigned Halfword */
3789 case 134: /* Vector Compare Equal To Unsigned Word */
3790 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3791 case 774: /* Vector Compare Greater Than Signed Byte */
3792 case 838: /* Vector Compare Greater Than Signed Halfword */
3793 case 902: /* Vector Compare Greater Than Signed Word */
3794 case 967: /* Vector Compare Greater Than Signed Doubleword */
3795 case 518: /* Vector Compare Greater Than Unsigned Byte */
3796 case 646: /* Vector Compare Greater Than Unsigned Word */
3797 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3798 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3799 case 966: /* Vector Compare Bounds Single-Precision */
3800 case 198: /* Vector Compare Equal To Single-Precision */
3801 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3802 case 710: /* Vector Compare Greater Than Single-Precision */
3803 case 7: /* Vector Compare Not Equal Byte */
3804 case 71: /* Vector Compare Not Equal Halfword */
3805 case 135: /* Vector Compare Not Equal Word */
3806 case 263: /* Vector Compare Not Equal or Zero Byte */
3807 case 327: /* Vector Compare Not Equal or Zero Halfword */
3808 case 391: /* Vector Compare Not Equal or Zero Word */
3810 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3811 record_full_arch_list_add_reg (regcache
,
3812 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3820 case 0: /* Vector Count Leading Zero Least-Significant Bits
3822 case 1: /* Vector Count Trailing Zero Least-Significant Bits
3824 record_full_arch_list_add_reg (regcache
,
3825 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3828 case 6: /* Vector Negate Word */
3829 case 7: /* Vector Negate Doubleword */
3830 case 8: /* Vector Parity Byte Word */
3831 case 9: /* Vector Parity Byte Doubleword */
3832 case 10: /* Vector Parity Byte Quadword */
3833 case 16: /* Vector Extend Sign Byte To Word */
3834 case 17: /* Vector Extend Sign Halfword To Word */
3835 case 24: /* Vector Extend Sign Byte To Doubleword */
3836 case 25: /* Vector Extend Sign Halfword To Doubleword */
3837 case 26: /* Vector Extend Sign Word To Doubleword */
3838 case 28: /* Vector Count Trailing Zeros Byte */
3839 case 29: /* Vector Count Trailing Zeros Halfword */
3840 case 30: /* Vector Count Trailing Zeros Word */
3841 case 31: /* Vector Count Trailing Zeros Doubleword */
3842 record_full_arch_list_add_reg (regcache
,
3843 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3850 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
3851 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
3852 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
3853 case 334: /* Vector Pack Signed Word Unsigned Saturate */
3854 case 398: /* Vector Pack Signed Halfword Signed Saturate */
3855 case 462: /* Vector Pack Signed Word Signed Saturate */
3856 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
3857 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
3858 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
3859 case 512: /* Vector Add Unsigned Byte Saturate */
3860 case 576: /* Vector Add Unsigned Halfword Saturate */
3861 case 640: /* Vector Add Unsigned Word Saturate */
3862 case 768: /* Vector Add Signed Byte Saturate */
3863 case 832: /* Vector Add Signed Halfword Saturate */
3864 case 896: /* Vector Add Signed Word Saturate */
3865 case 1536: /* Vector Subtract Unsigned Byte Saturate */
3866 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
3867 case 1664: /* Vector Subtract Unsigned Word Saturate */
3868 case 1792: /* Vector Subtract Signed Byte Saturate */
3869 case 1856: /* Vector Subtract Signed Halfword Saturate */
3870 case 1920: /* Vector Subtract Signed Word Saturate */
3872 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
3873 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
3874 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
3875 case 1672: /* Vector Sum across Half Signed Word Saturate */
3876 case 1928: /* Vector Sum across Signed Word Saturate */
3877 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
3878 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
3879 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3881 case 12: /* Vector Merge High Byte */
3882 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
3883 case 76: /* Vector Merge High Halfword */
3884 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
3885 case 140: /* Vector Merge High Word */
3886 case 268: /* Vector Merge Low Byte */
3887 case 332: /* Vector Merge Low Halfword */
3888 case 396: /* Vector Merge Low Word */
3889 case 526: /* Vector Unpack High Signed Byte */
3890 case 590: /* Vector Unpack High Signed Halfword */
3891 case 654: /* Vector Unpack Low Signed Byte */
3892 case 718: /* Vector Unpack Low Signed Halfword */
3893 case 782: /* Vector Pack Pixel */
3894 case 846: /* Vector Unpack High Pixel */
3895 case 974: /* Vector Unpack Low Pixel */
3896 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
3897 case 1614: /* Vector Unpack High Signed Word */
3898 case 1676: /* Vector Merge Odd Word */
3899 case 1742: /* Vector Unpack Low Signed Word */
3900 case 1932: /* Vector Merge Even Word */
3901 case 524: /* Vector Splat Byte */
3902 case 588: /* Vector Splat Halfword */
3903 case 652: /* Vector Splat Word */
3904 case 780: /* Vector Splat Immediate Signed Byte */
3905 case 844: /* Vector Splat Immediate Signed Halfword */
3906 case 908: /* Vector Splat Immediate Signed Word */
3907 case 452: /* Vector Shift Left */
3908 case 708: /* Vector Shift Right */
3909 case 1036: /* Vector Shift Left by Octet */
3910 case 1100: /* Vector Shift Right by Octet */
3911 case 0: /* Vector Add Unsigned Byte Modulo */
3912 case 64: /* Vector Add Unsigned Halfword Modulo */
3913 case 128: /* Vector Add Unsigned Word Modulo */
3914 case 192: /* Vector Add Unsigned Doubleword Modulo */
3915 case 256: /* Vector Add Unsigned Quadword Modulo */
3916 case 320: /* Vector Add & write Carry Unsigned Quadword */
3917 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
3918 case 8: /* Vector Multiply Odd Unsigned Byte */
3919 case 72: /* Vector Multiply Odd Unsigned Halfword */
3920 case 136: /* Vector Multiply Odd Unsigned Word */
3921 case 264: /* Vector Multiply Odd Signed Byte */
3922 case 328: /* Vector Multiply Odd Signed Halfword */
3923 case 392: /* Vector Multiply Odd Signed Word */
3924 case 520: /* Vector Multiply Even Unsigned Byte */
3925 case 584: /* Vector Multiply Even Unsigned Halfword */
3926 case 648: /* Vector Multiply Even Unsigned Word */
3927 case 776: /* Vector Multiply Even Signed Byte */
3928 case 840: /* Vector Multiply Even Signed Halfword */
3929 case 904: /* Vector Multiply Even Signed Word */
3930 case 137: /* Vector Multiply Unsigned Word Modulo */
3931 case 1024: /* Vector Subtract Unsigned Byte Modulo */
3932 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
3933 case 1152: /* Vector Subtract Unsigned Word Modulo */
3934 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
3935 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
3936 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
3937 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
3938 case 1282: /* Vector Average Signed Byte */
3939 case 1346: /* Vector Average Signed Halfword */
3940 case 1410: /* Vector Average Signed Word */
3941 case 1026: /* Vector Average Unsigned Byte */
3942 case 1090: /* Vector Average Unsigned Halfword */
3943 case 1154: /* Vector Average Unsigned Word */
3944 case 258: /* Vector Maximum Signed Byte */
3945 case 322: /* Vector Maximum Signed Halfword */
3946 case 386: /* Vector Maximum Signed Word */
3947 case 450: /* Vector Maximum Signed Doubleword */
3948 case 2: /* Vector Maximum Unsigned Byte */
3949 case 66: /* Vector Maximum Unsigned Halfword */
3950 case 130: /* Vector Maximum Unsigned Word */
3951 case 194: /* Vector Maximum Unsigned Doubleword */
3952 case 770: /* Vector Minimum Signed Byte */
3953 case 834: /* Vector Minimum Signed Halfword */
3954 case 898: /* Vector Minimum Signed Word */
3955 case 962: /* Vector Minimum Signed Doubleword */
3956 case 514: /* Vector Minimum Unsigned Byte */
3957 case 578: /* Vector Minimum Unsigned Halfword */
3958 case 642: /* Vector Minimum Unsigned Word */
3959 case 706: /* Vector Minimum Unsigned Doubleword */
3960 case 1028: /* Vector Logical AND */
3961 case 1668: /* Vector Logical Equivalent */
3962 case 1092: /* Vector Logical AND with Complement */
3963 case 1412: /* Vector Logical NAND */
3964 case 1348: /* Vector Logical OR with Complement */
3965 case 1156: /* Vector Logical OR */
3966 case 1284: /* Vector Logical NOR */
3967 case 1220: /* Vector Logical XOR */
3968 case 4: /* Vector Rotate Left Byte */
3969 case 132: /* Vector Rotate Left Word VX-form */
3970 case 68: /* Vector Rotate Left Halfword */
3971 case 196: /* Vector Rotate Left Doubleword */
3972 case 260: /* Vector Shift Left Byte */
3973 case 388: /* Vector Shift Left Word */
3974 case 324: /* Vector Shift Left Halfword */
3975 case 1476: /* Vector Shift Left Doubleword */
3976 case 516: /* Vector Shift Right Byte */
3977 case 644: /* Vector Shift Right Word */
3978 case 580: /* Vector Shift Right Halfword */
3979 case 1732: /* Vector Shift Right Doubleword */
3980 case 772: /* Vector Shift Right Algebraic Byte */
3981 case 900: /* Vector Shift Right Algebraic Word */
3982 case 836: /* Vector Shift Right Algebraic Halfword */
3983 case 964: /* Vector Shift Right Algebraic Doubleword */
3984 case 10: /* Vector Add Single-Precision */
3985 case 74: /* Vector Subtract Single-Precision */
3986 case 1034: /* Vector Maximum Single-Precision */
3987 case 1098: /* Vector Minimum Single-Precision */
3988 case 842: /* Vector Convert From Signed Fixed-Point Word */
3989 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
3990 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
3991 case 522: /* Vector Round to Single-Precision Integer Nearest */
3992 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
3993 case 586: /* Vector Round to Single-Precision Integer toward Zero */
3994 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
3995 case 458: /* Vector Log Base 2 Estimate Floating-Point */
3996 case 266: /* Vector Reciprocal Estimate Single-Precision */
3997 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
3998 case 1288: /* Vector AES Cipher */
3999 case 1289: /* Vector AES Cipher Last */
4000 case 1352: /* Vector AES Inverse Cipher */
4001 case 1353: /* Vector AES Inverse Cipher Last */
4002 case 1480: /* Vector AES SubBytes */
4003 case 1730: /* Vector SHA-512 Sigma Doubleword */
4004 case 1666: /* Vector SHA-256 Sigma Word */
4005 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4006 case 1160: /* Vector Polynomial Multiply-Sum Word */
4007 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4008 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4009 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4010 case 1794: /* Vector Count Leading Zeros Byte */
4011 case 1858: /* Vector Count Leading Zeros Halfword */
4012 case 1922: /* Vector Count Leading Zeros Word */
4013 case 1986: /* Vector Count Leading Zeros Doubleword */
4014 case 1795: /* Vector Population Count Byte */
4015 case 1859: /* Vector Population Count Halfword */
4016 case 1923: /* Vector Population Count Word */
4017 case 1987: /* Vector Population Count Doubleword */
4018 case 1356: /* Vector Bit Permute Quadword */
4019 case 1484: /* Vector Bit Permute Doubleword */
4020 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4021 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4023 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4024 case 65: /* Vector Multiply-by-10 Extended & write Carry
4025 Unsigned Quadword */
4026 case 1027: /* Vector Absolute Difference Unsigned Byte */
4027 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4028 case 1155: /* Vector Absolute Difference Unsigned Word */
4029 case 1796: /* Vector Shift Right Variable */
4030 case 1860: /* Vector Shift Left Variable */
4031 case 133: /* Vector Rotate Left Word then Mask Insert */
4032 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4033 case 389: /* Vector Rotate Left Word then AND with Mask */
4034 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4035 case 525: /* Vector Extract Unsigned Byte */
4036 case 589: /* Vector Extract Unsigned Halfword */
4037 case 653: /* Vector Extract Unsigned Word */
4038 case 717: /* Vector Extract Doubleword */
4039 case 781: /* Vector Insert Byte */
4040 case 845: /* Vector Insert Halfword */
4041 case 909: /* Vector Insert Word */
4042 case 973: /* Vector Insert Doubleword */
4043 record_full_arch_list_add_reg (regcache
,
4044 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4047 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4048 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4049 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4050 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4051 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4052 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4053 record_full_arch_list_add_reg (regcache
,
4054 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4057 case 1604: /* Move To Vector Status and Control Register */
4058 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4060 case 1540: /* Move From Vector Status and Control Register */
4061 record_full_arch_list_add_reg (regcache
,
4062 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4064 case 833: /* Decimal Copy Sign */
4065 record_full_arch_list_add_reg (regcache
,
4066 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4067 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4071 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4072 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4076 /* Parse and record instructions of primary opcode-19 at ADDR.
4077 Return 0 if successful. */
4080 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4081 CORE_ADDR addr
, uint32_t insn
)
4083 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4084 int ext
= PPC_EXTOP (insn
);
4086 switch (ext
& 0x01f)
4088 case 2: /* Add PC Immediate Shifted */
4089 record_full_arch_list_add_reg (regcache
,
4090 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4096 case 0: /* Move Condition Register Field */
4097 case 33: /* Condition Register NOR */
4098 case 129: /* Condition Register AND with Complement */
4099 case 193: /* Condition Register XOR */
4100 case 225: /* Condition Register NAND */
4101 case 257: /* Condition Register AND */
4102 case 289: /* Condition Register Equivalent */
4103 case 417: /* Condition Register OR with Complement */
4104 case 449: /* Condition Register OR */
4105 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4108 case 16: /* Branch Conditional */
4109 case 560: /* Branch Conditional to Branch Target Address Register */
4110 if ((PPC_BO (insn
) & 0x4) == 0)
4111 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4113 case 528: /* Branch Conditional to Count Register */
4115 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4118 case 150: /* Instruction Synchronize */
4123 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4124 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4128 /* Parse and record instructions of primary opcode-31 at ADDR.
4129 Return 0 if successful. */
4132 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4133 CORE_ADDR addr
, uint32_t insn
)
4135 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4136 int ext
= PPC_EXTOP (insn
);
4138 CORE_ADDR at_dcsz
, ea
= 0;
4139 ULONGEST rb
, ra
, xer
;
4142 /* These instructions have OE bit. */
4143 switch (ext
& 0x1ff)
4145 /* These write RT and XER. Update CR if RC is set. */
4146 case 8: /* Subtract from carrying */
4147 case 10: /* Add carrying */
4148 case 136: /* Subtract from extended */
4149 case 138: /* Add extended */
4150 case 200: /* Subtract from zero extended */
4151 case 202: /* Add to zero extended */
4152 case 232: /* Subtract from minus one extended */
4153 case 234: /* Add to minus one extended */
4154 /* CA is always altered, but SO/OV are only altered when OE=1.
4155 In any case, XER is always altered. */
4156 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4158 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4159 record_full_arch_list_add_reg (regcache
,
4160 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4163 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4164 case 40: /* Subtract from */
4165 case 104: /* Negate */
4166 case 233: /* Multiply low doubleword */
4167 case 235: /* Multiply low word */
4169 case 393: /* Divide Doubleword Extended Unsigned */
4170 case 395: /* Divide Word Extended Unsigned */
4171 case 425: /* Divide Doubleword Extended */
4172 case 427: /* Divide Word Extended */
4173 case 457: /* Divide Doubleword Unsigned */
4174 case 459: /* Divide Word Unsigned */
4175 case 489: /* Divide Doubleword */
4176 case 491: /* Divide Word */
4178 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4180 case 9: /* Multiply High Doubleword Unsigned */
4181 case 11: /* Multiply High Word Unsigned */
4182 case 73: /* Multiply High Doubleword */
4183 case 75: /* Multiply High Word */
4185 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4186 record_full_arch_list_add_reg (regcache
,
4187 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4191 if ((ext
& 0x1f) == 15)
4193 /* Integer Select. bit[16:20] is used for BC. */
4194 record_full_arch_list_add_reg (regcache
,
4195 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4199 if ((ext
& 0xff) == 170)
4201 /* Add Extended using alternate carry bits */
4202 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4203 record_full_arch_list_add_reg (regcache
,
4204 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4210 case 78: /* Determine Leftmost Zero Byte */
4212 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4213 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4214 record_full_arch_list_add_reg (regcache
,
4215 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4218 /* These only write RT. */
4219 case 19: /* Move from condition register */
4220 /* Move From One Condition Register Field */
4221 case 74: /* Add and Generate Sixes */
4222 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4223 case 302: /* Move From Branch History Rolling Buffer */
4224 case 339: /* Move From Special Purpose Register */
4225 case 371: /* Move From Time Base [Phased-Out] */
4226 case 309: /* Load Doubleword Monitored Indexed */
4227 case 128: /* Set Boolean */
4228 case 755: /* Deliver A Random Number */
4229 record_full_arch_list_add_reg (regcache
,
4230 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4233 /* These only write to RA. */
4234 case 51: /* Move From VSR Doubleword */
4235 case 115: /* Move From VSR Word and Zero */
4236 case 122: /* Population count bytes */
4237 case 378: /* Population count words */
4238 case 506: /* Population count doublewords */
4239 case 154: /* Parity Word */
4240 case 186: /* Parity Doubleword */
4241 case 252: /* Bit Permute Doubleword */
4242 case 282: /* Convert Declets To Binary Coded Decimal */
4243 case 314: /* Convert Binary Coded Decimal To Declets */
4244 case 508: /* Compare bytes */
4245 case 307: /* Move From VSR Lower Doubleword */
4246 record_full_arch_list_add_reg (regcache
,
4247 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4250 /* These write CR and optional RA. */
4251 case 792: /* Shift Right Algebraic Word */
4252 case 794: /* Shift Right Algebraic Doubleword */
4253 case 824: /* Shift Right Algebraic Word Immediate */
4254 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4255 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4256 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4257 record_full_arch_list_add_reg (regcache
,
4258 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4260 case 0: /* Compare */
4261 case 32: /* Compare logical */
4262 case 144: /* Move To Condition Register Fields */
4263 /* Move To One Condition Register Field */
4264 case 192: /* Compare Ranged Byte */
4265 case 224: /* Compare Equal Byte */
4266 case 576: /* Move XER to CR Extended */
4267 case 902: /* Paste (should always fail due to single-stepping and
4268 the memory location might not be accessible, so
4270 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4273 /* These write to RT. Update RA if 'update indexed.' */
4274 case 53: /* Load Doubleword with Update Indexed */
4275 case 119: /* Load Byte and Zero with Update Indexed */
4276 case 311: /* Load Halfword and Zero with Update Indexed */
4277 case 55: /* Load Word and Zero with Update Indexed */
4278 case 375: /* Load Halfword Algebraic with Update Indexed */
4279 case 373: /* Load Word Algebraic with Update Indexed */
4280 record_full_arch_list_add_reg (regcache
,
4281 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4283 case 21: /* Load Doubleword Indexed */
4284 case 52: /* Load Byte And Reserve Indexed */
4285 case 116: /* Load Halfword And Reserve Indexed */
4286 case 20: /* Load Word And Reserve Indexed */
4287 case 84: /* Load Doubleword And Reserve Indexed */
4288 case 87: /* Load Byte and Zero Indexed */
4289 case 279: /* Load Halfword and Zero Indexed */
4290 case 23: /* Load Word and Zero Indexed */
4291 case 343: /* Load Halfword Algebraic Indexed */
4292 case 341: /* Load Word Algebraic Indexed */
4293 case 790: /* Load Halfword Byte-Reverse Indexed */
4294 case 534: /* Load Word Byte-Reverse Indexed */
4295 case 532: /* Load Doubleword Byte-Reverse Indexed */
4296 case 582: /* Load Word Atomic */
4297 case 614: /* Load Doubleword Atomic */
4298 case 265: /* Modulo Unsigned Doubleword */
4299 case 777: /* Modulo Signed Doubleword */
4300 case 267: /* Modulo Unsigned Word */
4301 case 779: /* Modulo Signed Word */
4302 record_full_arch_list_add_reg (regcache
,
4303 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4306 case 597: /* Load String Word Immediate */
4307 case 533: /* Load String Word Indexed */
4316 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4317 nr
= PPC_XER_NB (xer
);
4322 /* If n=0, the contents of register RT are undefined. */
4326 for (i
= 0; i
< nr
; i
++)
4327 record_full_arch_list_add_reg (regcache
,
4328 tdep
->ppc_gp0_regnum
4329 + ((PPC_RT (insn
) + i
) & 0x1f));
4332 case 276: /* Load Quadword And Reserve Indexed */
4333 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4334 record_full_arch_list_add_reg (regcache
, tmp
);
4335 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4338 /* These write VRT. */
4339 case 6: /* Load Vector for Shift Left Indexed */
4340 case 38: /* Load Vector for Shift Right Indexed */
4341 case 7: /* Load Vector Element Byte Indexed */
4342 case 39: /* Load Vector Element Halfword Indexed */
4343 case 71: /* Load Vector Element Word Indexed */
4344 case 103: /* Load Vector Indexed */
4345 case 359: /* Load Vector Indexed LRU */
4346 record_full_arch_list_add_reg (regcache
,
4347 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4350 /* These write FRT. Update RA if 'update indexed.' */
4351 case 567: /* Load Floating-Point Single with Update Indexed */
4352 case 631: /* Load Floating-Point Double with Update Indexed */
4353 record_full_arch_list_add_reg (regcache
,
4354 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4356 case 535: /* Load Floating-Point Single Indexed */
4357 case 599: /* Load Floating-Point Double Indexed */
4358 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4359 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4360 record_full_arch_list_add_reg (regcache
,
4361 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4364 case 791: /* Load Floating-Point Double Pair Indexed */
4365 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4366 record_full_arch_list_add_reg (regcache
, tmp
);
4367 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4370 case 179: /* Move To VSR Doubleword */
4371 case 211: /* Move To VSR Word Algebraic */
4372 case 243: /* Move To VSR Word and Zero */
4373 case 588: /* Load VSX Scalar Doubleword Indexed */
4374 case 524: /* Load VSX Scalar Single-Precision Indexed */
4375 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4376 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4377 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4378 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4379 case 780: /* Load VSX Vector Word*4 Indexed */
4380 case 268: /* Load VSX Vector Indexed */
4381 case 364: /* Load VSX Vector Word & Splat Indexed */
4382 case 812: /* Load VSX Vector Halfword*8 Indexed */
4383 case 876: /* Load VSX Vector Byte*16 Indexed */
4384 case 269: /* Load VSX Vector with Length */
4385 case 301: /* Load VSX Vector Left-justified with Length */
4386 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4387 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4388 case 403: /* Move To VSR Word & Splat */
4389 case 435: /* Move To VSR Double Doubleword */
4390 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4393 /* These write RA. Update CR if RC is set. */
4394 case 24: /* Shift Left Word */
4395 case 26: /* Count Leading Zeros Word */
4396 case 27: /* Shift Left Doubleword */
4398 case 58: /* Count Leading Zeros Doubleword */
4399 case 60: /* AND with Complement */
4401 case 284: /* Equivalent */
4403 case 476: /* NAND */
4404 case 412: /* OR with Complement */
4406 case 536: /* Shift Right Word */
4407 case 539: /* Shift Right Doubleword */
4408 case 922: /* Extend Sign Halfword */
4409 case 954: /* Extend Sign Byte */
4410 case 986: /* Extend Sign Word */
4411 case 538: /* Count Trailing Zeros Word */
4412 case 570: /* Count Trailing Zeros Doubleword */
4413 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4414 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4416 if (ext
== 444 && tdep
->ppc_ppr_regnum
>= 0
4417 && (PPC_RS (insn
) == PPC_RA (insn
))
4418 && (PPC_RA (insn
) == PPC_RB (insn
))
4421 /* or Rx,Rx,Rx alters PRI in PPR. */
4422 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4427 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4428 record_full_arch_list_add_reg (regcache
,
4429 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4433 case 181: /* Store Doubleword with Update Indexed */
4434 case 183: /* Store Word with Update Indexed */
4435 case 247: /* Store Byte with Update Indexed */
4436 case 439: /* Store Half Word with Update Indexed */
4437 case 695: /* Store Floating-Point Single with Update Indexed */
4438 case 759: /* Store Floating-Point Double with Update Indexed */
4439 record_full_arch_list_add_reg (regcache
,
4440 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4442 case 135: /* Store Vector Element Byte Indexed */
4443 case 167: /* Store Vector Element Halfword Indexed */
4444 case 199: /* Store Vector Element Word Indexed */
4445 case 231: /* Store Vector Indexed */
4446 case 487: /* Store Vector Indexed LRU */
4447 case 716: /* Store VSX Scalar Doubleword Indexed */
4448 case 140: /* Store VSX Scalar as Integer Word Indexed */
4449 case 652: /* Store VSX Scalar Single-Precision Indexed */
4450 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4451 case 908: /* Store VSX Vector Word*4 Indexed */
4452 case 149: /* Store Doubleword Indexed */
4453 case 151: /* Store Word Indexed */
4454 case 215: /* Store Byte Indexed */
4455 case 407: /* Store Half Word Indexed */
4456 case 694: /* Store Byte Conditional Indexed */
4457 case 726: /* Store Halfword Conditional Indexed */
4458 case 150: /* Store Word Conditional Indexed */
4459 case 214: /* Store Doubleword Conditional Indexed */
4460 case 182: /* Store Quadword Conditional Indexed */
4461 case 662: /* Store Word Byte-Reverse Indexed */
4462 case 918: /* Store Halfword Byte-Reverse Indexed */
4463 case 660: /* Store Doubleword Byte-Reverse Indexed */
4464 case 663: /* Store Floating-Point Single Indexed */
4465 case 727: /* Store Floating-Point Double Indexed */
4466 case 919: /* Store Floating-Point Double Pair Indexed */
4467 case 983: /* Store Floating-Point as Integer Word Indexed */
4468 case 396: /* Store VSX Vector Indexed */
4469 case 940: /* Store VSX Vector Halfword*8 Indexed */
4470 case 1004: /* Store VSX Vector Byte*16 Indexed */
4471 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4472 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4473 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4474 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4477 if (PPC_RA (insn
) != 0)
4478 regcache_raw_read_unsigned (regcache
,
4479 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4480 regcache_raw_read_unsigned (regcache
,
4481 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4486 case 183: /* Store Word with Update Indexed */
4487 case 199: /* Store Vector Element Word Indexed */
4488 case 140: /* Store VSX Scalar as Integer Word Indexed */
4489 case 652: /* Store VSX Scalar Single-Precision Indexed */
4490 case 151: /* Store Word Indexed */
4491 case 150: /* Store Word Conditional Indexed */
4492 case 662: /* Store Word Byte-Reverse Indexed */
4493 case 663: /* Store Floating-Point Single Indexed */
4494 case 695: /* Store Floating-Point Single with Update Indexed */
4495 case 983: /* Store Floating-Point as Integer Word Indexed */
4498 case 247: /* Store Byte with Update Indexed */
4499 case 135: /* Store Vector Element Byte Indexed */
4500 case 215: /* Store Byte Indexed */
4501 case 694: /* Store Byte Conditional Indexed */
4502 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4505 case 439: /* Store Halfword with Update Indexed */
4506 case 167: /* Store Vector Element Halfword Indexed */
4507 case 407: /* Store Halfword Indexed */
4508 case 726: /* Store Halfword Conditional Indexed */
4509 case 918: /* Store Halfword Byte-Reverse Indexed */
4510 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4513 case 181: /* Store Doubleword with Update Indexed */
4514 case 716: /* Store VSX Scalar Doubleword Indexed */
4515 case 149: /* Store Doubleword Indexed */
4516 case 214: /* Store Doubleword Conditional Indexed */
4517 case 660: /* Store Doubleword Byte-Reverse Indexed */
4518 case 727: /* Store Floating-Point Double Indexed */
4519 case 759: /* Store Floating-Point Double with Update Indexed */
4522 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4523 case 908: /* Store VSX Vector Word*4 Indexed */
4524 case 182: /* Store Quadword Conditional Indexed */
4525 case 231: /* Store Vector Indexed */
4526 case 487: /* Store Vector Indexed LRU */
4527 case 919: /* Store Floating-Point Double Pair Indexed */
4528 case 396: /* Store VSX Vector Indexed */
4529 case 940: /* Store VSX Vector Halfword*8 Indexed */
4530 case 1004: /* Store VSX Vector Byte*16 Indexed */
4537 /* Align address for Store Vector instructions. */
4540 case 167: /* Store Vector Element Halfword Indexed */
4541 addr
= addr
& ~0x1ULL
;
4544 case 199: /* Store Vector Element Word Indexed */
4545 addr
= addr
& ~0x3ULL
;
4548 case 231: /* Store Vector Indexed */
4549 case 487: /* Store Vector Indexed LRU */
4550 addr
= addr
& ~0xfULL
;
4554 record_full_arch_list_add_mem (addr
, size
);
4557 case 397: /* Store VSX Vector with Length */
4558 case 429: /* Store VSX Vector Left-justified with Length */
4560 if (PPC_RA (insn
) != 0)
4561 regcache_raw_read_unsigned (regcache
,
4562 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4564 regcache_raw_read_unsigned (regcache
,
4565 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4566 /* Store up to 16 bytes. */
4567 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4569 record_full_arch_list_add_mem (ea
, nb
);
4572 case 710: /* Store Word Atomic */
4573 case 742: /* Store Doubleword Atomic */
4575 if (PPC_RA (insn
) != 0)
4576 regcache_raw_read_unsigned (regcache
,
4577 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4581 case 710: /* Store Word Atomic */
4584 case 742: /* Store Doubleword Atomic */
4590 record_full_arch_list_add_mem (ea
, size
);
4593 case 725: /* Store String Word Immediate */
4595 if (PPC_RA (insn
) != 0)
4596 regcache_raw_read_unsigned (regcache
,
4597 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4604 record_full_arch_list_add_mem (ea
, nb
);
4608 case 661: /* Store String Word Indexed */
4610 if (PPC_RA (insn
) != 0)
4611 regcache_raw_read_unsigned (regcache
,
4612 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4615 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4616 nb
= PPC_XER_NB (xer
);
4620 regcache_raw_read_unsigned (regcache
,
4621 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4624 record_full_arch_list_add_mem (ea
, nb
);
4629 case 467: /* Move To Special Purpose Register */
4630 switch (PPC_SPR (insn
))
4633 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4636 if (tdep
->ppc_dscr_regnum
>= 0)
4637 record_full_arch_list_add_reg (regcache
, tdep
->ppc_dscr_regnum
);
4640 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4643 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4645 case 256: /* VRSAVE */
4646 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4650 if (tdep
->ppc_ppr_regnum
>= 0)
4651 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ppr_regnum
);
4657 case 147: /* Move To Split Little Endian */
4658 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4661 case 512: /* Move to Condition Register from XER */
4662 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4663 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4666 case 4: /* Trap Word */
4667 case 68: /* Trap Doubleword */
4668 case 430: /* Clear BHRB */
4669 case 598: /* Synchronize */
4670 case 62: /* Wait for Interrupt */
4672 case 22: /* Instruction Cache Block Touch */
4673 case 854: /* Enforce In-order Execution of I/O */
4674 case 246: /* Data Cache Block Touch for Store */
4675 case 54: /* Data Cache Block Store */
4676 case 86: /* Data Cache Block Flush */
4677 case 278: /* Data Cache Block Touch */
4678 case 758: /* Data Cache Block Allocate */
4679 case 982: /* Instruction Cache Block Invalidate */
4680 case 774: /* Copy */
4681 case 838: /* CP_Abort */
4684 case 654: /* Transaction Begin */
4685 case 686: /* Transaction End */
4686 case 750: /* Transaction Suspend or Resume */
4687 case 782: /* Transaction Abort Word Conditional */
4688 case 814: /* Transaction Abort Doubleword Conditional */
4689 case 846: /* Transaction Abort Word Conditional Immediate */
4690 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4691 case 910: /* Transaction Abort */
4692 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4694 case 718: /* Transaction Check */
4695 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4698 case 1014: /* Data Cache Block set to Zero */
4699 if (target_auxv_search (current_top_target (), AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4701 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4704 if (PPC_RA (insn
) != 0)
4705 regcache_raw_read_unsigned (regcache
,
4706 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4707 regcache_raw_read_unsigned (regcache
,
4708 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4709 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4710 record_full_arch_list_add_mem (ea
, at_dcsz
);
4715 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4716 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4720 /* Parse and record instructions of primary opcode-59 at ADDR.
4721 Return 0 if successful. */
4724 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4725 CORE_ADDR addr
, uint32_t insn
)
4727 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4728 int ext
= PPC_EXTOP (insn
);
4732 case 18: /* Floating Divide */
4733 case 20: /* Floating Subtract */
4734 case 21: /* Floating Add */
4735 case 22: /* Floating Square Root */
4736 case 24: /* Floating Reciprocal Estimate */
4737 case 25: /* Floating Multiply */
4738 case 26: /* Floating Reciprocal Square Root Estimate */
4739 case 28: /* Floating Multiply-Subtract */
4740 case 29: /* Floating Multiply-Add */
4741 case 30: /* Floating Negative Multiply-Subtract */
4742 case 31: /* Floating Negative Multiply-Add */
4743 record_full_arch_list_add_reg (regcache
,
4744 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4746 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4747 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4754 case 2: /* DFP Add */
4755 case 3: /* DFP Quantize */
4756 case 34: /* DFP Multiply */
4757 case 35: /* DFP Reround */
4758 case 67: /* DFP Quantize Immediate */
4759 case 99: /* DFP Round To FP Integer With Inexact */
4760 case 227: /* DFP Round To FP Integer Without Inexact */
4761 case 258: /* DFP Convert To DFP Long! */
4762 case 290: /* DFP Convert To Fixed */
4763 case 514: /* DFP Subtract */
4764 case 546: /* DFP Divide */
4765 case 770: /* DFP Round To DFP Short! */
4766 case 802: /* DFP Convert From Fixed */
4767 case 834: /* DFP Encode BCD To DPD */
4769 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4770 record_full_arch_list_add_reg (regcache
,
4771 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4772 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4775 case 130: /* DFP Compare Ordered */
4776 case 162: /* DFP Test Exponent */
4777 case 194: /* DFP Test Data Class */
4778 case 226: /* DFP Test Data Group */
4779 case 642: /* DFP Compare Unordered */
4780 case 674: /* DFP Test Significance */
4781 case 675: /* DFP Test Significance Immediate */
4782 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4783 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4786 case 66: /* DFP Shift Significand Left Immediate */
4787 case 98: /* DFP Shift Significand Right Immediate */
4788 case 322: /* DFP Decode DPD To BCD */
4789 case 354: /* DFP Extract Biased Exponent */
4790 case 866: /* DFP Insert Biased Exponent */
4791 record_full_arch_list_add_reg (regcache
,
4792 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4794 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4797 case 846: /* Floating Convert From Integer Doubleword Single */
4798 case 974: /* Floating Convert From Integer Doubleword Unsigned
4800 record_full_arch_list_add_reg (regcache
,
4801 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4803 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4804 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4809 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4810 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4814 /* Parse and record instructions of primary opcode-60 at ADDR.
4815 Return 0 if successful. */
4818 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4819 CORE_ADDR addr
, uint32_t insn
)
4821 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4822 int ext
= PPC_EXTOP (insn
);
4826 case 0: /* VSX Scalar Add Single-Precision */
4827 case 32: /* VSX Scalar Add Double-Precision */
4828 case 24: /* VSX Scalar Divide Single-Precision */
4829 case 56: /* VSX Scalar Divide Double-Precision */
4830 case 176: /* VSX Scalar Copy Sign Double-Precision */
4831 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4832 case 41: /* ditto */
4833 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4835 case 160: /* VSX Scalar Maximum Double-Precision */
4836 case 168: /* VSX Scalar Minimum Double-Precision */
4837 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4838 case 57: /* ditto */
4839 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4840 case 25: /* ditto */
4841 case 48: /* VSX Scalar Multiply Double-Precision */
4842 case 16: /* VSX Scalar Multiply Single-Precision */
4843 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4844 case 169: /* ditto */
4845 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4846 case 137: /* ditto */
4847 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4848 case 185: /* ditto */
4849 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4850 case 153: /* ditto */
4851 case 40: /* VSX Scalar Subtract Double-Precision */
4852 case 8: /* VSX Scalar Subtract Single-Precision */
4853 case 96: /* VSX Vector Add Double-Precision */
4854 case 64: /* VSX Vector Add Single-Precision */
4855 case 120: /* VSX Vector Divide Double-Precision */
4856 case 88: /* VSX Vector Divide Single-Precision */
4857 case 97: /* VSX Vector Multiply-Add Double-Precision */
4858 case 105: /* ditto */
4859 case 65: /* VSX Vector Multiply-Add Single-Precision */
4860 case 73: /* ditto */
4861 case 224: /* VSX Vector Maximum Double-Precision */
4862 case 192: /* VSX Vector Maximum Single-Precision */
4863 case 232: /* VSX Vector Minimum Double-Precision */
4864 case 200: /* VSX Vector Minimum Single-Precision */
4865 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
4866 case 121: /* ditto */
4867 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
4868 case 89: /* ditto */
4869 case 112: /* VSX Vector Multiply Double-Precision */
4870 case 80: /* VSX Vector Multiply Single-Precision */
4871 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
4872 case 233: /* ditto */
4873 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
4874 case 201: /* ditto */
4875 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
4876 case 249: /* ditto */
4877 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
4878 case 217: /* ditto */
4879 case 104: /* VSX Vector Subtract Double-Precision */
4880 case 72: /* VSX Vector Subtract Single-Precision */
4881 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
4882 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
4883 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
4884 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
4885 case 3: /* VSX Scalar Compare Equal Double-Precision */
4886 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
4887 case 19: /* VSX Scalar Compare Greater Than or Equal
4889 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4891 case 240: /* VSX Vector Copy Sign Double-Precision */
4892 case 208: /* VSX Vector Copy Sign Single-Precision */
4893 case 130: /* VSX Logical AND */
4894 case 138: /* VSX Logical AND with Complement */
4895 case 186: /* VSX Logical Equivalence */
4896 case 178: /* VSX Logical NAND */
4897 case 170: /* VSX Logical OR with Complement */
4898 case 162: /* VSX Logical NOR */
4899 case 146: /* VSX Logical OR */
4900 case 154: /* VSX Logical XOR */
4901 case 18: /* VSX Merge High Word */
4902 case 50: /* VSX Merge Low Word */
4903 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
4904 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
4905 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
4906 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
4907 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
4908 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
4909 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
4910 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
4911 case 216: /* VSX Vector Insert Exponent Single-Precision */
4912 case 248: /* VSX Vector Insert Exponent Double-Precision */
4913 case 26: /* VSX Vector Permute */
4914 case 58: /* VSX Vector Permute Right-indexed */
4915 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
4916 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
4917 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
4918 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
4919 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4922 case 61: /* VSX Scalar Test for software Divide Double-Precision */
4923 case 125: /* VSX Vector Test for software Divide Double-Precision */
4924 case 93: /* VSX Vector Test for software Divide Single-Precision */
4925 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4928 case 35: /* VSX Scalar Compare Unordered Double-Precision */
4929 case 43: /* VSX Scalar Compare Ordered Double-Precision */
4930 case 59: /* VSX Scalar Compare Exponents Double-Precision */
4931 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4932 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4936 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
4938 case 99: /* VSX Vector Compare Equal To Double-Precision */
4939 case 67: /* VSX Vector Compare Equal To Single-Precision */
4940 case 115: /* VSX Vector Compare Greater Than or
4941 Equal To Double-Precision */
4942 case 83: /* VSX Vector Compare Greater Than or
4943 Equal To Single-Precision */
4944 case 107: /* VSX Vector Compare Greater Than Double-Precision */
4945 case 75: /* VSX Vector Compare Greater Than Single-Precision */
4947 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4948 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4949 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4955 case 265: /* VSX Scalar round Double-Precision to
4956 Single-Precision and Convert to
4957 Single-Precision format */
4958 case 344: /* VSX Scalar truncate Double-Precision to
4959 Integer and Convert to Signed Integer
4960 Doubleword format with Saturate */
4961 case 88: /* VSX Scalar truncate Double-Precision to
4962 Integer and Convert to Signed Integer Word
4963 Format with Saturate */
4964 case 328: /* VSX Scalar truncate Double-Precision integer
4965 and Convert to Unsigned Integer Doubleword
4966 Format with Saturate */
4967 case 72: /* VSX Scalar truncate Double-Precision to
4968 Integer and Convert to Unsigned Integer Word
4969 Format with Saturate */
4970 case 329: /* VSX Scalar Convert Single-Precision to
4971 Double-Precision format */
4972 case 376: /* VSX Scalar Convert Signed Integer
4973 Doubleword to floating-point format and
4974 Round to Double-Precision format */
4975 case 312: /* VSX Scalar Convert Signed Integer
4976 Doubleword to floating-point format and
4977 round to Single-Precision */
4978 case 360: /* VSX Scalar Convert Unsigned Integer
4979 Doubleword to floating-point format and
4980 Round to Double-Precision format */
4981 case 296: /* VSX Scalar Convert Unsigned Integer
4982 Doubleword to floating-point format and
4983 Round to Single-Precision */
4984 case 73: /* VSX Scalar Round to Double-Precision Integer
4985 Using Round to Nearest Away */
4986 case 107: /* VSX Scalar Round to Double-Precision Integer
4987 Exact using Current rounding mode */
4988 case 121: /* VSX Scalar Round to Double-Precision Integer
4989 Using Round toward -Infinity */
4990 case 105: /* VSX Scalar Round to Double-Precision Integer
4991 Using Round toward +Infinity */
4992 case 89: /* VSX Scalar Round to Double-Precision Integer
4993 Using Round toward Zero */
4994 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
4995 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
4996 case 281: /* VSX Scalar Round to Single-Precision */
4997 case 74: /* VSX Scalar Reciprocal Square Root Estimate
4999 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5001 case 75: /* VSX Scalar Square Root Double-Precision */
5002 case 11: /* VSX Scalar Square Root Single-Precision */
5003 case 393: /* VSX Vector round Double-Precision to
5004 Single-Precision and Convert to
5005 Single-Precision format */
5006 case 472: /* VSX Vector truncate Double-Precision to
5007 Integer and Convert to Signed Integer
5008 Doubleword format with Saturate */
5009 case 216: /* VSX Vector truncate Double-Precision to
5010 Integer and Convert to Signed Integer Word
5011 Format with Saturate */
5012 case 456: /* VSX Vector truncate Double-Precision to
5013 Integer and Convert to Unsigned Integer
5014 Doubleword format with Saturate */
5015 case 200: /* VSX Vector truncate Double-Precision to
5016 Integer and Convert to Unsigned Integer Word
5017 Format with Saturate */
5018 case 457: /* VSX Vector Convert Single-Precision to
5019 Double-Precision format */
5020 case 408: /* VSX Vector truncate Single-Precision to
5021 Integer and Convert to Signed Integer
5022 Doubleword format with Saturate */
5023 case 152: /* VSX Vector truncate Single-Precision to
5024 Integer and Convert to Signed Integer Word
5025 Format with Saturate */
5026 case 392: /* VSX Vector truncate Single-Precision to
5027 Integer and Convert to Unsigned Integer
5028 Doubleword format with Saturate */
5029 case 136: /* VSX Vector truncate Single-Precision to
5030 Integer and Convert to Unsigned Integer Word
5031 Format with Saturate */
5032 case 504: /* VSX Vector Convert and round Signed Integer
5033 Doubleword to Double-Precision format */
5034 case 440: /* VSX Vector Convert and round Signed Integer
5035 Doubleword to Single-Precision format */
5036 case 248: /* VSX Vector Convert Signed Integer Word to
5037 Double-Precision format */
5038 case 184: /* VSX Vector Convert and round Signed Integer
5039 Word to Single-Precision format */
5040 case 488: /* VSX Vector Convert and round Unsigned
5041 Integer Doubleword to Double-Precision format */
5042 case 424: /* VSX Vector Convert and round Unsigned
5043 Integer Doubleword to Single-Precision format */
5044 case 232: /* VSX Vector Convert and round Unsigned
5045 Integer Word to Double-Precision format */
5046 case 168: /* VSX Vector Convert and round Unsigned
5047 Integer Word to Single-Precision format */
5048 case 201: /* VSX Vector Round to Double-Precision
5049 Integer using round to Nearest Away */
5050 case 235: /* VSX Vector Round to Double-Precision
5051 Integer Exact using Current rounding mode */
5052 case 249: /* VSX Vector Round to Double-Precision
5053 Integer using round toward -Infinity */
5054 case 233: /* VSX Vector Round to Double-Precision
5055 Integer using round toward +Infinity */
5056 case 217: /* VSX Vector Round to Double-Precision
5057 Integer using round toward Zero */
5058 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5059 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5060 case 137: /* VSX Vector Round to Single-Precision Integer
5061 Using Round to Nearest Away */
5062 case 171: /* VSX Vector Round to Single-Precision Integer
5063 Exact Using Current rounding mode */
5064 case 185: /* VSX Vector Round to Single-Precision Integer
5065 Using Round toward -Infinity */
5066 case 169: /* VSX Vector Round to Single-Precision Integer
5067 Using Round toward +Infinity */
5068 case 153: /* VSX Vector Round to Single-Precision Integer
5069 Using round toward Zero */
5070 case 202: /* VSX Vector Reciprocal Square Root Estimate
5072 case 138: /* VSX Vector Reciprocal Square Root Estimate
5074 case 203: /* VSX Vector Square Root Double-Precision */
5075 case 139: /* VSX Vector Square Root Single-Precision */
5076 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5078 case 345: /* VSX Scalar Absolute Value Double-Precision */
5079 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5080 Vector Single-Precision format Non-signalling */
5081 case 331: /* VSX Scalar Convert Single-Precision to
5082 Double-Precision format Non-signalling */
5083 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5084 case 377: /* VSX Scalar Negate Double-Precision */
5085 case 473: /* VSX Vector Absolute Value Double-Precision */
5086 case 409: /* VSX Vector Absolute Value Single-Precision */
5087 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5088 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5089 case 505: /* VSX Vector Negate Double-Precision */
5090 case 441: /* VSX Vector Negate Single-Precision */
5091 case 164: /* VSX Splat Word */
5092 case 165: /* VSX Vector Extract Unsigned Word */
5093 case 181: /* VSX Vector Insert Word */
5094 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5097 case 298: /* VSX Scalar Test Data Class Single-Precision */
5098 case 362: /* VSX Scalar Test Data Class Double-Precision */
5099 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5101 case 106: /* VSX Scalar Test for software Square Root
5103 case 234: /* VSX Vector Test for software Square Root
5105 case 170: /* VSX Vector Test for software Square Root
5107 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5111 switch (PPC_FIELD (insn
, 11, 5))
5113 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5114 case 1: /* VSX Scalar Extract Significand Double-Precision */
5115 record_full_arch_list_add_reg (regcache
,
5116 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5118 case 16: /* VSX Scalar Convert Half-Precision format to
5119 Double-Precision format */
5120 case 17: /* VSX Scalar round & Convert Double-Precision format
5121 to Half-Precision format */
5122 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5123 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5129 switch (PPC_FIELD (insn
, 11, 5))
5131 case 24: /* VSX Vector Convert Half-Precision format to
5132 Single-Precision format */
5133 case 25: /* VSX Vector round and Convert Single-Precision format
5134 to Half-Precision format */
5135 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5137 case 0: /* VSX Vector Extract Exponent Double-Precision */
5138 case 1: /* VSX Vector Extract Significand Double-Precision */
5139 case 7: /* VSX Vector Byte-Reverse Halfword */
5140 case 8: /* VSX Vector Extract Exponent Single-Precision */
5141 case 9: /* VSX Vector Extract Significand Single-Precision */
5142 case 15: /* VSX Vector Byte-Reverse Word */
5143 case 23: /* VSX Vector Byte-Reverse Doubleword */
5144 case 31: /* VSX Vector Byte-Reverse Quadword */
5145 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5153 case 360: /* VSX Vector Splat Immediate Byte */
5154 if (PPC_FIELD (insn
, 11, 2) == 0)
5156 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5160 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5161 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5165 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5167 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5171 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5172 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5176 /* Parse and record instructions of primary opcode-61 at ADDR.
5177 Return 0 if successful. */
5180 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5181 CORE_ADDR addr
, uint32_t insn
)
5183 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5189 case 0: /* Store Floating-Point Double Pair */
5190 case 2: /* Store VSX Scalar Doubleword */
5191 case 3: /* Store VSX Scalar Single */
5192 if (PPC_RA (insn
) != 0)
5193 regcache_raw_read_unsigned (regcache
,
5194 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5196 ea
+= PPC_DS (insn
) << 2;
5199 case 0: /* Store Floating-Point Double Pair */
5202 case 2: /* Store VSX Scalar Doubleword */
5205 case 3: /* Store VSX Scalar Single */
5211 record_full_arch_list_add_mem (ea
, size
);
5217 case 1: /* Load VSX Vector */
5218 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5220 case 5: /* Store VSX Vector */
5221 if (PPC_RA (insn
) != 0)
5222 regcache_raw_read_unsigned (regcache
,
5223 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5225 ea
+= PPC_DQ (insn
) << 4;
5226 record_full_arch_list_add_mem (ea
, 16);
5230 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5231 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5235 /* Parse and record instructions of primary opcode-63 at ADDR.
5236 Return 0 if successful. */
5239 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5240 CORE_ADDR addr
, uint32_t insn
)
5242 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5243 int ext
= PPC_EXTOP (insn
);
5248 case 18: /* Floating Divide */
5249 case 20: /* Floating Subtract */
5250 case 21: /* Floating Add */
5251 case 22: /* Floating Square Root */
5252 case 24: /* Floating Reciprocal Estimate */
5253 case 25: /* Floating Multiply */
5254 case 26: /* Floating Reciprocal Square Root Estimate */
5255 case 28: /* Floating Multiply-Subtract */
5256 case 29: /* Floating Multiply-Add */
5257 case 30: /* Floating Negative Multiply-Subtract */
5258 case 31: /* Floating Negative Multiply-Add */
5259 record_full_arch_list_add_reg (regcache
,
5260 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5262 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5263 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5266 case 23: /* Floating Select */
5267 record_full_arch_list_add_reg (regcache
,
5268 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5270 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5276 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5277 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5279 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5280 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5286 case 2: /* DFP Add Quad */
5287 case 3: /* DFP Quantize Quad */
5288 case 34: /* DFP Multiply Quad */
5289 case 35: /* DFP Reround Quad */
5290 case 67: /* DFP Quantize Immediate Quad */
5291 case 99: /* DFP Round To FP Integer With Inexact Quad */
5292 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5293 case 258: /* DFP Convert To DFP Extended Quad */
5294 case 514: /* DFP Subtract Quad */
5295 case 546: /* DFP Divide Quad */
5296 case 770: /* DFP Round To DFP Long Quad */
5297 case 802: /* DFP Convert From Fixed Quad */
5298 case 834: /* DFP Encode BCD To DPD Quad */
5300 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5301 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5302 record_full_arch_list_add_reg (regcache
, tmp
);
5303 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5304 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5307 case 130: /* DFP Compare Ordered Quad */
5308 case 162: /* DFP Test Exponent Quad */
5309 case 194: /* DFP Test Data Class Quad */
5310 case 226: /* DFP Test Data Group Quad */
5311 case 642: /* DFP Compare Unordered Quad */
5312 case 674: /* DFP Test Significance Quad */
5313 case 675: /* DFP Test Significance Immediate Quad */
5314 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5315 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5318 case 66: /* DFP Shift Significand Left Immediate Quad */
5319 case 98: /* DFP Shift Significand Right Immediate Quad */
5320 case 322: /* DFP Decode DPD To BCD Quad */
5321 case 866: /* DFP Insert Biased Exponent Quad */
5322 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5323 record_full_arch_list_add_reg (regcache
, tmp
);
5324 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5326 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5329 case 290: /* DFP Convert To Fixed Quad */
5330 record_full_arch_list_add_reg (regcache
,
5331 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5333 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5334 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5337 case 354: /* DFP Extract Biased Exponent Quad */
5338 record_full_arch_list_add_reg (regcache
,
5339 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5341 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5344 case 12: /* Floating Round to Single-Precision */
5345 case 14: /* Floating Convert To Integer Word */
5346 case 15: /* Floating Convert To Integer Word
5347 with round toward Zero */
5348 case 142: /* Floating Convert To Integer Word Unsigned */
5349 case 143: /* Floating Convert To Integer Word Unsigned
5350 with round toward Zero */
5351 case 392: /* Floating Round to Integer Nearest */
5352 case 424: /* Floating Round to Integer Toward Zero */
5353 case 456: /* Floating Round to Integer Plus */
5354 case 488: /* Floating Round to Integer Minus */
5355 case 814: /* Floating Convert To Integer Doubleword */
5356 case 815: /* Floating Convert To Integer Doubleword
5357 with round toward Zero */
5358 case 846: /* Floating Convert From Integer Doubleword */
5359 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5360 case 943: /* Floating Convert To Integer Doubleword Unsigned
5361 with round toward Zero */
5362 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5363 record_full_arch_list_add_reg (regcache
,
5364 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5366 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5367 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5371 switch (PPC_FIELD (insn
, 11, 5))
5373 case 1: /* Move From FPSCR & Clear Enables */
5374 case 20: /* Move From FPSCR Control & set DRN */
5375 case 21: /* Move From FPSCR Control & set DRN Immediate */
5376 case 22: /* Move From FPSCR Control & set RN */
5377 case 23: /* Move From FPSCR Control & set RN Immediate */
5378 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5380 case 0: /* Move From FPSCR */
5381 case 24: /* Move From FPSCR Lightweight */
5382 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5383 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5384 record_full_arch_list_add_reg (regcache
,
5385 tdep
->ppc_fp0_regnum
5391 case 8: /* Floating Copy Sign */
5392 case 40: /* Floating Negate */
5393 case 72: /* Floating Move Register */
5394 case 136: /* Floating Negative Absolute Value */
5395 case 264: /* Floating Absolute Value */
5396 record_full_arch_list_add_reg (regcache
,
5397 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5399 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5402 case 838: /* Floating Merge Odd Word */
5403 case 966: /* Floating Merge Even Word */
5404 record_full_arch_list_add_reg (regcache
,
5405 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5408 case 38: /* Move To FPSCR Bit 1 */
5409 case 70: /* Move To FPSCR Bit 0 */
5410 case 134: /* Move To FPSCR Field Immediate */
5411 case 711: /* Move To FPSCR Fields */
5413 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5414 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5417 case 0: /* Floating Compare Unordered */
5418 case 32: /* Floating Compare Ordered */
5419 case 64: /* Move to Condition Register from FPSCR */
5420 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5421 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5422 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5423 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5424 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5426 case 128: /* Floating Test for software Divide */
5427 case 160: /* Floating Test for software Square Root */
5428 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5431 case 4: /* VSX Scalar Add Quad-Precision */
5432 case 36: /* VSX Scalar Multiply Quad-Precision */
5433 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5434 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5435 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5436 case 484: /* VSX Scalar Negative Multiply-Subtract
5438 case 516: /* VSX Scalar Subtract Quad-Precision */
5439 case 548: /* VSX Scalar Divide Quad-Precision */
5440 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5442 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5443 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5444 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5448 switch (PPC_FIELD (insn
, 11, 5))
5450 case 27: /* VSX Scalar Square Root Quad-Precision */
5451 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5453 case 0: /* VSX Scalar Absolute Quad-Precision */
5454 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5455 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5456 case 16: /* VSX Scalar Negate Quad-Precision */
5457 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5458 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5464 switch (PPC_FIELD (insn
, 11, 5))
5466 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5467 to Unsigned Word format */
5468 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5469 Quad-Precision format */
5470 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5471 to Signed Word format */
5472 case 10: /* VSX Scalar Convert Signed Doubleword format to
5473 Quad-Precision format */
5474 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5475 to Unsigned Doubleword format */
5476 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5477 Double-Precision format */
5478 case 22: /* VSX Scalar Convert Double-Precision format to
5479 Quad-Precision format */
5480 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5481 to Signed Doubleword format */
5482 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5483 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5488 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5489 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5493 /* Parse the current instruction and record the values of the registers and
5494 memory that will be changed in current instruction to "record_arch_list".
5495 Return -1 if something wrong. */
5498 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5501 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5502 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5506 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5507 op6
= PPC_OP6 (insn
);
5511 case 2: /* Trap Doubleword Immediate */
5512 case 3: /* Trap Word Immediate */
5517 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5521 case 17: /* System call */
5522 if (PPC_LEV (insn
) != 0)
5525 if (tdep
->ppc_syscall_record
!= NULL
)
5527 if (tdep
->ppc_syscall_record (regcache
) != 0)
5532 printf_unfiltered (_("no syscall record support\n"));
5537 case 7: /* Multiply Low Immediate */
5538 record_full_arch_list_add_reg (regcache
,
5539 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5542 case 8: /* Subtract From Immediate Carrying */
5543 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5544 record_full_arch_list_add_reg (regcache
,
5545 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5548 case 10: /* Compare Logical Immediate */
5549 case 11: /* Compare Immediate */
5550 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5553 case 13: /* Add Immediate Carrying and Record */
5554 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5556 case 12: /* Add Immediate Carrying */
5557 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5559 case 14: /* Add Immediate */
5560 case 15: /* Add Immediate Shifted */
5561 record_full_arch_list_add_reg (regcache
,
5562 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5565 case 16: /* Branch Conditional */
5566 if ((PPC_BO (insn
) & 0x4) == 0)
5567 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5569 case 18: /* Branch */
5571 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5575 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5579 case 20: /* Rotate Left Word Immediate then Mask Insert */
5580 case 21: /* Rotate Left Word Immediate then AND with Mask */
5581 case 23: /* Rotate Left Word then AND with Mask */
5582 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5583 /* Rotate Left Doubleword Immediate then Clear Right */
5584 /* Rotate Left Doubleword Immediate then Clear */
5585 /* Rotate Left Doubleword then Clear Left */
5586 /* Rotate Left Doubleword then Clear Right */
5587 /* Rotate Left Doubleword Immediate then Mask Insert */
5589 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5590 record_full_arch_list_add_reg (regcache
,
5591 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5594 case 28: /* AND Immediate */
5595 case 29: /* AND Immediate Shifted */
5596 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5598 case 24: /* OR Immediate */
5599 case 25: /* OR Immediate Shifted */
5600 case 26: /* XOR Immediate */
5601 case 27: /* XOR Immediate Shifted */
5602 record_full_arch_list_add_reg (regcache
,
5603 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5607 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5611 case 33: /* Load Word and Zero with Update */
5612 case 35: /* Load Byte and Zero with Update */
5613 case 41: /* Load Halfword and Zero with Update */
5614 case 43: /* Load Halfword Algebraic with Update */
5615 record_full_arch_list_add_reg (regcache
,
5616 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5618 case 32: /* Load Word and Zero */
5619 case 34: /* Load Byte and Zero */
5620 case 40: /* Load Halfword and Zero */
5621 case 42: /* Load Halfword Algebraic */
5622 record_full_arch_list_add_reg (regcache
,
5623 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5626 case 46: /* Load Multiple Word */
5627 for (i
= PPC_RT (insn
); i
< 32; i
++)
5628 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5631 case 56: /* Load Quadword */
5632 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5633 record_full_arch_list_add_reg (regcache
, tmp
);
5634 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5637 case 49: /* Load Floating-Point Single with Update */
5638 case 51: /* Load Floating-Point Double with Update */
5639 record_full_arch_list_add_reg (regcache
,
5640 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5642 case 48: /* Load Floating-Point Single */
5643 case 50: /* Load Floating-Point Double */
5644 record_full_arch_list_add_reg (regcache
,
5645 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5648 case 47: /* Store Multiple Word */
5652 if (PPC_RA (insn
) != 0)
5653 regcache_raw_read_unsigned (regcache
,
5654 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5657 iaddr
+= PPC_D (insn
);
5658 record_full_arch_list_add_mem (iaddr
, 4 * (32 - PPC_RS (insn
)));
5662 case 37: /* Store Word with Update */
5663 case 39: /* Store Byte with Update */
5664 case 45: /* Store Halfword with Update */
5665 case 53: /* Store Floating-Point Single with Update */
5666 case 55: /* Store Floating-Point Double with Update */
5667 record_full_arch_list_add_reg (regcache
,
5668 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5670 case 36: /* Store Word */
5671 case 38: /* Store Byte */
5672 case 44: /* Store Halfword */
5673 case 52: /* Store Floating-Point Single */
5674 case 54: /* Store Floating-Point Double */
5679 if (PPC_RA (insn
) != 0)
5680 regcache_raw_read_unsigned (regcache
,
5681 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5683 iaddr
+= PPC_D (insn
);
5685 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5687 else if (op6
== 54 || op6
== 55)
5689 else if (op6
== 44 || op6
== 45)
5691 else if (op6
== 38 || op6
== 39)
5696 record_full_arch_list_add_mem (iaddr
, size
);
5703 case 0: /* Load Floating-Point Double Pair */
5704 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5705 record_full_arch_list_add_reg (regcache
, tmp
);
5706 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5708 case 2: /* Load VSX Scalar Doubleword */
5709 case 3: /* Load VSX Scalar Single */
5710 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5717 case 58: /* Load Doubleword */
5718 /* Load Doubleword with Update */
5719 /* Load Word Algebraic */
5720 if (PPC_FIELD (insn
, 30, 2) > 2)
5723 record_full_arch_list_add_reg (regcache
,
5724 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5725 if (PPC_BIT (insn
, 31))
5726 record_full_arch_list_add_reg (regcache
,
5727 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5731 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5736 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5741 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
5745 case 62: /* Store Doubleword */
5746 /* Store Doubleword with Update */
5747 /* Store Quadword with Update */
5751 int sub2
= PPC_FIELD (insn
, 30, 2);
5756 if (PPC_RA (insn
) != 0)
5757 regcache_raw_read_unsigned (regcache
,
5758 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5761 size
= (sub2
== 2) ? 16 : 8;
5763 iaddr
+= PPC_DS (insn
) << 2;
5764 record_full_arch_list_add_mem (iaddr
, size
);
5766 if (op6
== 62 && sub2
== 1)
5767 record_full_arch_list_add_reg (regcache
,
5768 tdep
->ppc_gp0_regnum
+
5775 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5781 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5782 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5786 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5788 if (record_full_arch_list_add_end ())
5793 /* Initialize the current architecture based on INFO. If possible, re-use an
5794 architecture from ARCHES, which is a list of architectures already created
5795 during this debugging session.
5797 Called e.g. at program startup, when reading a core file, and when reading
5800 static struct gdbarch
*
5801 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5803 struct gdbarch
*gdbarch
;
5804 struct gdbarch_tdep
*tdep
;
5805 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5806 enum bfd_architecture arch
;
5809 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5811 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
5812 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5813 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5814 int have_fpu
= 0, have_spe
= 0, have_mq
= 0, have_altivec
= 0;
5815 int have_dfp
= 0, have_vsx
= 0, have_ppr
= 0, have_dscr
= 0;
5816 int tdesc_wordsize
= -1;
5817 const struct target_desc
*tdesc
= info
.target_desc
;
5818 struct tdesc_arch_data
*tdesc_data
= NULL
;
5819 int num_pseudoregs
= 0;
5822 /* INFO may refer to a binary that is not of the PowerPC architecture,
5823 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5824 In this case, we must not attempt to infer properties of the (PowerPC
5825 side) of the target system from properties of that executable. Trust
5826 the target description instead. */
5828 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5829 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5832 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5833 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5835 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5836 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5838 /* Check word size. If INFO is from a binary file, infer it from
5839 that, else choose a likely default. */
5840 if (from_xcoff_exec
)
5842 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5847 else if (from_elf_exec
)
5849 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5854 else if (tdesc_has_registers (tdesc
))
5858 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
5859 wordsize
= (info
.bfd_arch_info
->bits_per_word
5860 / info
.bfd_arch_info
->bits_per_byte
);
5865 /* Get the architecture and machine from the BFD. */
5866 arch
= info
.bfd_arch_info
->arch
;
5867 mach
= info
.bfd_arch_info
->mach
;
5869 /* For e500 executables, the apuinfo section is of help here. Such
5870 section contains the identifier and revision number of each
5871 Application-specific Processing Unit that is present on the
5872 chip. The content of the section is determined by the assembler
5873 which looks at each instruction and determines which unit (and
5874 which version of it) can execute it. Grovel through the section
5875 looking for relevant e500 APUs. */
5877 if (bfd_uses_spe_extensions (info
.abfd
))
5879 arch
= info
.bfd_arch_info
->arch
;
5880 mach
= bfd_mach_ppc_e500
;
5881 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
5882 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
5885 /* Find a default target description which describes our register
5886 layout, if we do not already have one. */
5887 if (! tdesc_has_registers (tdesc
))
5889 const struct variant
*v
;
5891 /* Choose variant. */
5892 v
= find_variant_by_arch (arch
, mach
);
5899 gdb_assert (tdesc_has_registers (tdesc
));
5901 /* Check any target description for validity. */
5902 if (tdesc_has_registers (tdesc
))
5904 static const char *const gprs
[] = {
5905 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5906 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5907 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5908 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5910 const struct tdesc_feature
*feature
;
5912 static const char *const msr_names
[] = { "msr", "ps" };
5913 static const char *const cr_names
[] = { "cr", "cnd" };
5914 static const char *const ctr_names
[] = { "ctr", "cnt" };
5916 feature
= tdesc_find_feature (tdesc
,
5917 "org.gnu.gdb.power.core");
5918 if (feature
== NULL
)
5921 tdesc_data
= tdesc_data_alloc ();
5924 for (i
= 0; i
< ppc_num_gprs
; i
++)
5925 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
5926 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
5928 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
5930 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
5933 /* Allow alternate names for these registers, to accomodate GDB's
5935 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5936 PPC_MSR_REGNUM
, msr_names
);
5937 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5938 PPC_CR_REGNUM
, cr_names
);
5939 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5940 PPC_CTR_REGNUM
, ctr_names
);
5944 tdesc_data_cleanup (tdesc_data
);
5948 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
5951 tdesc_wordsize
= tdesc_register_bitsize (feature
, "pc") / 8;
5953 wordsize
= tdesc_wordsize
;
5955 feature
= tdesc_find_feature (tdesc
,
5956 "org.gnu.gdb.power.fpu");
5957 if (feature
!= NULL
)
5959 static const char *const fprs
[] = {
5960 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5961 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5962 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5963 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
5966 for (i
= 0; i
< ppc_num_fprs
; i
++)
5967 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5968 PPC_F0_REGNUM
+ i
, fprs
[i
]);
5969 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5970 PPC_FPSCR_REGNUM
, "fpscr");
5974 tdesc_data_cleanup (tdesc_data
);
5979 /* The fpscr register was expanded in isa 2.05 to 64 bits
5980 along with the addition of the decimal floating point
5982 if (tdesc_register_bitsize (feature
, "fpscr") > 32)
5988 feature
= tdesc_find_feature (tdesc
,
5989 "org.gnu.gdb.power.altivec");
5990 if (feature
!= NULL
)
5992 static const char *const vector_regs
[] = {
5993 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
5994 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
5995 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
5996 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6000 for (i
= 0; i
< ppc_num_gprs
; i
++)
6001 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6004 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6005 PPC_VSCR_REGNUM
, "vscr");
6006 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6007 PPC_VRSAVE_REGNUM
, "vrsave");
6009 if (have_spe
|| !valid_p
)
6011 tdesc_data_cleanup (tdesc_data
);
6019 /* Check for POWER7 VSX registers support. */
6020 feature
= tdesc_find_feature (tdesc
,
6021 "org.gnu.gdb.power.vsx");
6023 if (feature
!= NULL
)
6025 static const char *const vsx_regs
[] = {
6026 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6027 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6028 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6029 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6030 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6036 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6037 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6038 PPC_VSR0_UPPER_REGNUM
+ i
,
6042 tdesc_data_cleanup (tdesc_data
);
6051 /* On machines supporting the SPE APU, the general-purpose registers
6052 are 64 bits long. There are SIMD vector instructions to treat them
6053 as pairs of floats, but the rest of the instruction set treats them
6054 as 32-bit registers, and only operates on their lower halves.
6056 In the GDB regcache, we treat their high and low halves as separate
6057 registers. The low halves we present as the general-purpose
6058 registers, and then we have pseudo-registers that stitch together
6059 the upper and lower halves and present them as pseudo-registers.
6061 Thus, the target description is expected to supply the upper
6062 halves separately. */
6064 feature
= tdesc_find_feature (tdesc
,
6065 "org.gnu.gdb.power.spe");
6066 if (feature
!= NULL
)
6068 static const char *const upper_spe
[] = {
6069 "ev0h", "ev1h", "ev2h", "ev3h",
6070 "ev4h", "ev5h", "ev6h", "ev7h",
6071 "ev8h", "ev9h", "ev10h", "ev11h",
6072 "ev12h", "ev13h", "ev14h", "ev15h",
6073 "ev16h", "ev17h", "ev18h", "ev19h",
6074 "ev20h", "ev21h", "ev22h", "ev23h",
6075 "ev24h", "ev25h", "ev26h", "ev27h",
6076 "ev28h", "ev29h", "ev30h", "ev31h"
6080 for (i
= 0; i
< ppc_num_gprs
; i
++)
6081 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6082 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6084 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6085 PPC_SPE_ACC_REGNUM
, "acc");
6086 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6087 PPC_SPE_FSCR_REGNUM
, "spefscr");
6089 if (have_mq
|| have_fpu
|| !valid_p
)
6091 tdesc_data_cleanup (tdesc_data
);
6099 /* Program Priority Register. */
6100 feature
= tdesc_find_feature (tdesc
,
6101 "org.gnu.gdb.power.ppr");
6102 if (feature
!= NULL
)
6105 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6106 PPC_PPR_REGNUM
, "ppr");
6110 tdesc_data_cleanup (tdesc_data
);
6118 /* Data Stream Control Register. */
6119 feature
= tdesc_find_feature (tdesc
,
6120 "org.gnu.gdb.power.dscr");
6121 if (feature
!= NULL
)
6124 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6125 PPC_DSCR_REGNUM
, "dscr");
6129 tdesc_data_cleanup (tdesc_data
);
6138 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6139 complain for a 32-bit binary on a 64-bit target; we do not yet
6140 support that. For instance, the 32-bit ABI routines expect
6143 As long as there isn't an explicit target description, we'll
6144 choose one based on the BFD architecture and get a word size
6145 matching the binary (probably powerpc:common or
6146 powerpc:common64). So there is only trouble if a 64-bit target
6147 supplies a 64-bit description while debugging a 32-bit
6149 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6151 tdesc_data_cleanup (tdesc_data
);
6158 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6161 elf_abi
= POWERPC_ELF_V1
;
6164 elf_abi
= POWERPC_ELF_V2
;
6171 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6173 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6174 Tag_GNU_Power_ABI_FP
) & 3)
6177 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6180 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6187 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6189 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6190 Tag_GNU_Power_ABI_FP
) >> 2)
6193 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6196 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6203 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6205 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6206 Tag_GNU_Power_ABI_Vector
))
6209 vector_abi
= POWERPC_VEC_GENERIC
;
6212 vector_abi
= POWERPC_VEC_ALTIVEC
;
6215 vector_abi
= POWERPC_VEC_SPE
;
6223 /* At this point, the only supported ELF-based 64-bit little-endian
6224 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6225 default. All other supported ELF-based operating systems use the
6226 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6227 e.g. because we run a legacy binary, or have attached to a process
6228 and have not found any associated binary file, set the default
6229 according to this heuristic. */
6230 if (elf_abi
== POWERPC_ELF_AUTO
)
6232 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6233 elf_abi
= POWERPC_ELF_V2
;
6235 elf_abi
= POWERPC_ELF_V1
;
6238 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6240 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6243 soft_float
= !have_fpu
;
6245 /* If we have a hard float binary or setting but no floating point
6246 registers, downgrade to soft float anyway. We're still somewhat
6247 useful in this scenario. */
6248 if (!soft_float
&& !have_fpu
)
6251 /* Similarly for vector registers. */
6252 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6253 vector_abi
= POWERPC_VEC_GENERIC
;
6255 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6256 vector_abi
= POWERPC_VEC_GENERIC
;
6258 if (vector_abi
== POWERPC_VEC_AUTO
)
6261 vector_abi
= POWERPC_VEC_ALTIVEC
;
6263 vector_abi
= POWERPC_VEC_SPE
;
6265 vector_abi
= POWERPC_VEC_GENERIC
;
6268 /* Do not limit the vector ABI based on available hardware, since we
6269 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6271 /* Find a candidate among extant architectures. */
6272 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6274 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6276 /* Word size in the various PowerPC bfd_arch_info structs isn't
6277 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6278 separate word size check. */
6279 tdep
= gdbarch_tdep (arches
->gdbarch
);
6280 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6282 if (tdep
&& tdep
->soft_float
!= soft_float
)
6284 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6286 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6288 if (tdep
&& tdep
->wordsize
== wordsize
)
6290 if (tdesc_data
!= NULL
)
6291 tdesc_data_cleanup (tdesc_data
);
6292 return arches
->gdbarch
;
6296 /* None found, create a new architecture from INFO, whose bfd_arch_info
6297 validity depends on the source:
6298 - executable useless
6299 - rs6000_host_arch() good
6301 - "set arch" trust blindly
6302 - GDB startup useless but harmless */
6304 tdep
= XCNEW (struct gdbarch_tdep
);
6305 tdep
->wordsize
= wordsize
;
6306 tdep
->elf_abi
= elf_abi
;
6307 tdep
->soft_float
= soft_float
;
6308 tdep
->long_double_abi
= long_double_abi
;
6309 tdep
->vector_abi
= vector_abi
;
6311 gdbarch
= gdbarch_alloc (&info
, tdep
);
6313 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6314 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6315 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6316 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6317 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6318 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6319 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6320 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6322 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6323 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6324 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6325 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6326 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6327 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6328 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6329 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6330 tdep
->ppc_ppr_regnum
= have_ppr
? PPC_PPR_REGNUM
: -1;
6331 tdep
->ppc_dscr_regnum
= have_dscr
? PPC_DSCR_REGNUM
: -1;
6333 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6334 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6335 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6336 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6338 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6339 GDB traditionally called it "ps", though, so let GDB add an
6341 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6344 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6346 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6348 /* Set lr_frame_offset. */
6350 tdep
->lr_frame_offset
= 16;
6352 tdep
->lr_frame_offset
= 4;
6354 if (have_spe
|| have_dfp
|| have_vsx
)
6356 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6357 set_gdbarch_pseudo_register_write (gdbarch
,
6358 rs6000_pseudo_register_write
);
6359 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6360 rs6000_ax_pseudo_register_collect
);
6363 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6365 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6367 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6370 num_pseudoregs
+= 32;
6372 num_pseudoregs
+= 16;
6374 /* Include both VSX and Extended FP registers. */
6375 num_pseudoregs
+= 96;
6377 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6379 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6380 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6381 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6382 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6383 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6384 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6385 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6386 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6387 set_gdbarch_char_signed (gdbarch
, 0);
6389 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6392 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6394 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6395 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6396 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6398 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6399 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6402 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6403 else if (wordsize
== 8)
6404 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6406 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6407 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6408 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6410 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6412 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6413 rs6000_breakpoint::kind_from_pc
);
6414 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6415 rs6000_breakpoint::bp_from_kind
);
6417 /* The value of symbols of type N_SO and N_FUN maybe null when
6419 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6421 /* Handles single stepping of atomic sequences. */
6422 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6424 /* Not sure on this. FIXMEmgo */
6425 set_gdbarch_frame_args_skip (gdbarch
, 8);
6427 /* Helpers for function argument information. */
6428 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6431 set_gdbarch_in_solib_return_trampoline
6432 (gdbarch
, rs6000_in_solib_return_trampoline
);
6433 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6435 /* Hook in the DWARF CFI frame unwinder. */
6436 dwarf2_append_unwinders (gdbarch
);
6437 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6439 /* Frame handling. */
6440 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6442 /* Setup displaced stepping. */
6443 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6444 ppc_displaced_step_copy_insn
);
6445 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6446 ppc_displaced_step_hw_singlestep
);
6447 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6448 set_gdbarch_displaced_step_location (gdbarch
,
6449 displaced_step_at_entry_point
);
6451 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6453 /* Hook in ABI-specific overrides, if they have been registered. */
6454 info
.target_desc
= tdesc
;
6455 info
.tdesc_data
= tdesc_data
;
6456 gdbarch_init_osabi (info
, gdbarch
);
6460 case GDB_OSABI_LINUX
:
6461 case GDB_OSABI_NETBSD
:
6462 case GDB_OSABI_UNKNOWN
:
6463 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6464 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6465 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6466 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6467 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6470 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6472 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6473 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6474 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6475 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6476 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6479 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6480 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6482 /* Override the normal target description method to make the SPE upper
6483 halves anonymous. */
6484 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6486 /* Choose register numbers for all supported pseudo-registers. */
6487 tdep
->ppc_ev0_regnum
= -1;
6488 tdep
->ppc_dl0_regnum
= -1;
6489 tdep
->ppc_vsr0_regnum
= -1;
6490 tdep
->ppc_efpr0_regnum
= -1;
6492 cur_reg
= gdbarch_num_regs (gdbarch
);
6496 tdep
->ppc_ev0_regnum
= cur_reg
;
6501 tdep
->ppc_dl0_regnum
= cur_reg
;
6506 tdep
->ppc_vsr0_regnum
= cur_reg
;
6508 tdep
->ppc_efpr0_regnum
= cur_reg
;
6512 gdb_assert (gdbarch_num_cooked_regs (gdbarch
) == cur_reg
);
6514 /* Register the ravenscar_arch_ops. */
6515 if (mach
== bfd_mach_ppc_e500
)
6516 register_e500_ravenscar_ops (gdbarch
);
6518 register_ppc_ravenscar_ops (gdbarch
);
6520 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
6521 set_gdbarch_valid_disassembler_options (gdbarch
,
6522 disassembler_options_powerpc ());
6528 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6530 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6535 /* FIXME: Dump gdbarch_tdep. */
6538 /* PowerPC-specific commands. */
6541 set_powerpc_command (const char *args
, int from_tty
)
6543 printf_unfiltered (_("\
6544 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6545 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6549 show_powerpc_command (const char *args
, int from_tty
)
6551 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6555 powerpc_set_soft_float (const char *args
, int from_tty
,
6556 struct cmd_list_element
*c
)
6558 struct gdbarch_info info
;
6560 /* Update the architecture. */
6561 gdbarch_info_init (&info
);
6562 if (!gdbarch_update_p (info
))
6563 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6567 powerpc_set_vector_abi (const char *args
, int from_tty
,
6568 struct cmd_list_element
*c
)
6570 struct gdbarch_info info
;
6573 for (vector_abi
= POWERPC_VEC_AUTO
;
6574 vector_abi
!= POWERPC_VEC_LAST
;
6576 if (strcmp (powerpc_vector_abi_string
,
6577 powerpc_vector_strings
[vector_abi
]) == 0)
6579 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6583 if (vector_abi
== POWERPC_VEC_LAST
)
6584 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6585 powerpc_vector_abi_string
);
6587 /* Update the architecture. */
6588 gdbarch_info_init (&info
);
6589 if (!gdbarch_update_p (info
))
6590 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6593 /* Show the current setting of the exact watchpoints flag. */
6596 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6597 struct cmd_list_element
*c
,
6600 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6603 /* Read a PPC instruction from memory. */
6606 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6608 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6609 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6611 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6614 /* Return non-zero if the instructions at PC match the series
6615 described in PATTERN, or zero otherwise. PATTERN is an array of
6616 'struct ppc_insn_pattern' objects, terminated by an entry whose
6619 When the match is successful, fill INSNS[i] with what PATTERN[i]
6620 matched. If PATTERN[i] is optional, and the instruction wasn't
6621 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
6622 INSNS should have as many elements as PATTERN, minus the terminator.
6623 Note that, if PATTERN contains optional instructions which aren't
6624 present in memory, then INSNS will have holes, so INSNS[i] isn't
6625 necessarily the i'th instruction in memory. */
6628 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6629 const struct ppc_insn_pattern
*pattern
,
6630 unsigned int *insns
)
6635 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6638 insn
= read_insn (frame
, pc
);
6640 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6646 else if (!pattern
[i
].optional
)
6653 /* Return the 'd' field of the d-form instruction INSN, properly
6657 ppc_insn_d_field (unsigned int insn
)
6659 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6662 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6663 zero bits concatenated at the right, and properly
6667 ppc_insn_ds_field (unsigned int insn
)
6669 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6672 /* Initialization code. */
6675 _initialize_rs6000_tdep (void)
6677 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6678 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6680 /* Initialize the standard target descriptions. */
6681 initialize_tdesc_powerpc_32 ();
6682 initialize_tdesc_powerpc_altivec32 ();
6683 initialize_tdesc_powerpc_vsx32 ();
6684 initialize_tdesc_powerpc_403 ();
6685 initialize_tdesc_powerpc_403gc ();
6686 initialize_tdesc_powerpc_405 ();
6687 initialize_tdesc_powerpc_505 ();
6688 initialize_tdesc_powerpc_601 ();
6689 initialize_tdesc_powerpc_602 ();
6690 initialize_tdesc_powerpc_603 ();
6691 initialize_tdesc_powerpc_604 ();
6692 initialize_tdesc_powerpc_64 ();
6693 initialize_tdesc_powerpc_altivec64 ();
6694 initialize_tdesc_powerpc_vsx64 ();
6695 initialize_tdesc_powerpc_7400 ();
6696 initialize_tdesc_powerpc_750 ();
6697 initialize_tdesc_powerpc_860 ();
6698 initialize_tdesc_powerpc_e500 ();
6699 initialize_tdesc_rs6000 ();
6701 /* Add root prefix command for all "set powerpc"/"show powerpc"
6703 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6704 _("Various PowerPC-specific commands."),
6705 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6707 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6708 _("Various PowerPC-specific commands."),
6709 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6711 /* Add a command to allow the user to force the ABI. */
6712 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6713 &powerpc_soft_float_global
,
6714 _("Set whether to use a soft-float ABI."),
6715 _("Show whether to use a soft-float ABI."),
6717 powerpc_set_soft_float
, NULL
,
6718 &setpowerpccmdlist
, &showpowerpccmdlist
);
6720 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6721 &powerpc_vector_abi_string
,
6722 _("Set the vector ABI."),
6723 _("Show the vector ABI."),
6724 NULL
, powerpc_set_vector_abi
, NULL
,
6725 &setpowerpccmdlist
, &showpowerpccmdlist
);
6727 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6728 &target_exact_watchpoints
,
6730 Set whether to use just one debug register for watchpoints on scalars."),
6732 Show whether to use just one debug register for watchpoints on scalars."),
6734 If true, GDB will use only one debug register when watching a variable of\n\
6735 scalar type, thus assuming that the variable is accessed through the address\n\
6736 of its first byte."),
6737 NULL
, show_powerpc_exact_watchpoints
,
6738 &setpowerpccmdlist
, &showpowerpccmdlist
);