1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
32 #include "arch-utils.h"
36 #include "parser-defs.h"
39 #include "libbfd.h" /* for bfd_default_set_arch_mach */
40 #include "coff/internal.h" /* for libcoff.h */
41 #include "libcoff.h" /* for xcoff_data */
42 #include "coff/xcoff.h"
47 #include "solib-svr4.h"
50 #include "gdb_assert.h"
53 #include "trad-frame.h"
54 #include "frame-unwind.h"
55 #include "frame-base.h"
57 /* If the kernel has to deliver a signal, it pushes a sigcontext
58 structure on the stack and then calls the signal handler, passing
59 the address of the sigcontext in an argument register. Usually
60 the signal handler doesn't save this register, so we have to
61 access the sigcontext structure via an offset from the signal handler
63 The following constants were determined by experimentation on AIX 3.2. */
64 #define SIG_FRAME_PC_OFFSET 96
65 #define SIG_FRAME_LR_OFFSET 108
66 #define SIG_FRAME_FP_OFFSET 284
68 /* To be used by skip_prologue. */
70 struct rs6000_framedata
72 int offset
; /* total size of frame --- the distance
73 by which we decrement sp to allocate
75 int saved_gpr
; /* smallest # of saved gpr */
76 int saved_fpr
; /* smallest # of saved fpr */
77 int saved_vr
; /* smallest # of saved vr */
78 int saved_ev
; /* smallest # of saved ev */
79 int alloca_reg
; /* alloca register number (frame ptr) */
80 char frameless
; /* true if frameless functions. */
81 char nosavedpc
; /* true if pc not saved. */
82 int gpr_offset
; /* offset of saved gprs from prev sp */
83 int fpr_offset
; /* offset of saved fprs from prev sp */
84 int vr_offset
; /* offset of saved vrs from prev sp */
85 int ev_offset
; /* offset of saved evs from prev sp */
86 int lr_offset
; /* offset of saved lr */
87 int cr_offset
; /* offset of saved cr */
88 int vrsave_offset
; /* offset of saved vrsave register */
91 /* Description of a single register. */
95 char *name
; /* name of register */
96 unsigned char sz32
; /* size on 32-bit arch, 0 if nonextant */
97 unsigned char sz64
; /* size on 64-bit arch, 0 if nonextant */
98 unsigned char fpr
; /* whether register is floating-point */
99 unsigned char pseudo
; /* whether register is pseudo */
102 /* Breakpoint shadows for the single step instructions will be kept here. */
104 static struct sstep_breaks
106 /* Address, or 0 if this is not in use. */
108 /* Shadow contents. */
113 /* Hook for determining the TOC address when calling functions in the
114 inferior under AIX. The initialization code in rs6000-nat.c sets
115 this hook to point to find_toc_address. */
117 CORE_ADDR (*rs6000_find_toc_address_hook
) (CORE_ADDR
) = NULL
;
119 /* Hook to set the current architecture when starting a child process.
120 rs6000-nat.c sets this. */
122 void (*rs6000_set_host_arch_hook
) (int) = NULL
;
124 /* Static function prototypes */
126 static CORE_ADDR
branch_dest (int opcode
, int instr
, CORE_ADDR pc
,
128 static CORE_ADDR
skip_prologue (CORE_ADDR
, CORE_ADDR
,
129 struct rs6000_framedata
*);
131 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
133 altivec_register_p (int regno
)
135 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
136 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
139 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
142 /* Use the architectures FP registers? */
144 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
146 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
147 if (info
->arch
== bfd_arch_powerpc
)
148 return (info
->mach
!= bfd_mach_ppc_e500
);
149 if (info
->arch
== bfd_arch_rs6000
)
154 /* Read a LEN-byte address from debugged memory address MEMADDR. */
157 read_memory_addr (CORE_ADDR memaddr
, int len
)
159 return read_memory_unsigned_integer (memaddr
, len
);
163 rs6000_skip_prologue (CORE_ADDR pc
)
165 struct rs6000_framedata frame
;
166 pc
= skip_prologue (pc
, 0, &frame
);
171 /* Fill in fi->saved_regs */
173 struct frame_extra_info
175 /* Functions calling alloca() change the value of the stack
176 pointer. We need to use initial stack pointer (which is saved in
177 r31 by gcc) in such cases. If a compiler emits traceback table,
178 then we should use the alloca register specified in traceback
180 CORE_ADDR initial_sp
; /* initial stack pointer. */
183 /* Get the ith function argument for the current function. */
185 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
189 get_frame_register (frame
, 3 + argi
, &addr
);
193 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
196 branch_dest (int opcode
, int instr
, CORE_ADDR pc
, CORE_ADDR safety
)
203 absolute
= (int) ((instr
>> 1) & 1);
208 immediate
= ((instr
& ~3) << 6) >> 6; /* br unconditional */
212 dest
= pc
+ immediate
;
216 immediate
= ((instr
& ~3) << 16) >> 16; /* br conditional */
220 dest
= pc
+ immediate
;
224 ext_op
= (instr
>> 1) & 0x3ff;
226 if (ext_op
== 16) /* br conditional register */
228 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
230 /* If we are about to return from a signal handler, dest is
231 something like 0x3c90. The current frame is a signal handler
232 caller frame, upon completion of the sigreturn system call
233 execution will return to the saved PC in the frame. */
234 if (dest
< TEXT_SEGMENT_BASE
)
236 struct frame_info
*fi
;
238 fi
= get_current_frame ();
240 dest
= read_memory_addr (get_frame_base (fi
) + SIG_FRAME_PC_OFFSET
,
241 gdbarch_tdep (current_gdbarch
)->wordsize
);
245 else if (ext_op
== 528) /* br cond to count reg */
247 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_ctr_regnum
) & ~3;
249 /* If we are about to execute a system call, dest is something
250 like 0x22fc or 0x3b00. Upon completion the system call
251 will return to the address in the link register. */
252 if (dest
< TEXT_SEGMENT_BASE
)
253 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
262 return (dest
< TEXT_SEGMENT_BASE
) ? safety
: dest
;
266 /* Sequence of bytes for breakpoint instruction. */
268 const static unsigned char *
269 rs6000_breakpoint_from_pc (CORE_ADDR
*bp_addr
, int *bp_size
)
271 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
272 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
274 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
275 return big_breakpoint
;
277 return little_breakpoint
;
281 /* AIX does not support PT_STEP. Simulate it. */
284 rs6000_software_single_step (enum target_signal signal
,
285 int insert_breakpoints_p
)
289 const char *breakp
= rs6000_breakpoint_from_pc (&dummy
, &breakp_sz
);
295 if (insert_breakpoints_p
)
300 insn
= read_memory_integer (loc
, 4);
302 breaks
[0] = loc
+ breakp_sz
;
304 breaks
[1] = branch_dest (opcode
, insn
, loc
, breaks
[0]);
306 /* Don't put two breakpoints on the same address. */
307 if (breaks
[1] == breaks
[0])
310 stepBreaks
[1].address
= 0;
312 for (ii
= 0; ii
< 2; ++ii
)
315 /* ignore invalid breakpoint. */
316 if (breaks
[ii
] == -1)
318 target_insert_breakpoint (breaks
[ii
], stepBreaks
[ii
].data
);
319 stepBreaks
[ii
].address
= breaks
[ii
];
326 /* remove step breakpoints. */
327 for (ii
= 0; ii
< 2; ++ii
)
328 if (stepBreaks
[ii
].address
!= 0)
329 target_remove_breakpoint (stepBreaks
[ii
].address
,
330 stepBreaks
[ii
].data
);
332 errno
= 0; /* FIXME, don't ignore errors! */
333 /* What errors? {read,write}_memory call error(). */
337 /* return pc value after skipping a function prologue and also return
338 information about a function frame.
340 in struct rs6000_framedata fdata:
341 - frameless is TRUE, if function does not have a frame.
342 - nosavedpc is TRUE, if function does not save %pc value in its frame.
343 - offset is the initial size of this stack frame --- the amount by
344 which we decrement the sp to allocate the frame.
345 - saved_gpr is the number of the first saved gpr.
346 - saved_fpr is the number of the first saved fpr.
347 - saved_vr is the number of the first saved vr.
348 - saved_ev is the number of the first saved ev.
349 - alloca_reg is the number of the register used for alloca() handling.
351 - gpr_offset is the offset of the first saved gpr from the previous frame.
352 - fpr_offset is the offset of the first saved fpr from the previous frame.
353 - vr_offset is the offset of the first saved vr from the previous frame.
354 - ev_offset is the offset of the first saved ev from the previous frame.
355 - lr_offset is the offset of the saved lr
356 - cr_offset is the offset of the saved cr
357 - vrsave_offset is the offset of the saved vrsave register
360 #define SIGNED_SHORT(x) \
361 ((sizeof (short) == 2) \
362 ? ((int)(short)(x)) \
363 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
365 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
367 /* Limit the number of skipped non-prologue instructions, as the examining
368 of the prologue is expensive. */
369 static int max_skip_non_prologue_insns
= 10;
371 /* Given PC representing the starting address of a function, and
372 LIM_PC which is the (sloppy) limit to which to scan when looking
373 for a prologue, attempt to further refine this limit by using
374 the line data in the symbol table. If successful, a better guess
375 on where the prologue ends is returned, otherwise the previous
376 value of lim_pc is returned. */
378 /* FIXME: cagney/2004-02-14: This function and logic have largely been
379 superseded by skip_prologue_using_sal. */
382 refine_prologue_limit (CORE_ADDR pc
, CORE_ADDR lim_pc
)
384 struct symtab_and_line prologue_sal
;
386 prologue_sal
= find_pc_line (pc
, 0);
387 if (prologue_sal
.line
!= 0)
390 CORE_ADDR addr
= prologue_sal
.end
;
392 /* Handle the case in which compiler's optimizer/scheduler
393 has moved instructions into the prologue. We scan ahead
394 in the function looking for address ranges whose corresponding
395 line number is less than or equal to the first one that we
396 found for the function. (It can be less than when the
397 scheduler puts a body instruction before the first prologue
399 for (i
= 2 * max_skip_non_prologue_insns
;
400 i
> 0 && (lim_pc
== 0 || addr
< lim_pc
);
403 struct symtab_and_line sal
;
405 sal
= find_pc_line (addr
, 0);
408 if (sal
.line
<= prologue_sal
.line
409 && sal
.symtab
== prologue_sal
.symtab
)
416 if (lim_pc
== 0 || prologue_sal
.end
< lim_pc
)
417 lim_pc
= prologue_sal
.end
;
424 skip_prologue (CORE_ADDR pc
, CORE_ADDR lim_pc
, struct rs6000_framedata
*fdata
)
426 CORE_ADDR orig_pc
= pc
;
427 CORE_ADDR last_prologue_pc
= pc
;
428 CORE_ADDR li_found_pc
= 0;
432 long vr_saved_offset
= 0;
441 int minimal_toc_loaded
= 0;
442 int prev_insn_was_prologue_insn
= 1;
443 int num_skip_non_prologue_insns
= 0;
444 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (current_gdbarch
);
445 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
447 /* Attempt to find the end of the prologue when no limit is specified.
448 Note that refine_prologue_limit() has been written so that it may
449 be used to "refine" the limits of non-zero PC values too, but this
450 is only safe if we 1) trust the line information provided by the
451 compiler and 2) iterate enough to actually find the end of the
454 It may become a good idea at some point (for both performance and
455 accuracy) to unconditionally call refine_prologue_limit(). But,
456 until we can make a clear determination that this is beneficial,
457 we'll play it safe and only use it to obtain a limit when none
458 has been specified. */
460 lim_pc
= refine_prologue_limit (pc
, lim_pc
);
462 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
463 fdata
->saved_gpr
= -1;
464 fdata
->saved_fpr
= -1;
465 fdata
->saved_vr
= -1;
466 fdata
->saved_ev
= -1;
467 fdata
->alloca_reg
= -1;
468 fdata
->frameless
= 1;
469 fdata
->nosavedpc
= 1;
473 /* Sometimes it isn't clear if an instruction is a prologue
474 instruction or not. When we encounter one of these ambiguous
475 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
476 Otherwise, we'll assume that it really is a prologue instruction. */
477 if (prev_insn_was_prologue_insn
)
478 last_prologue_pc
= pc
;
480 /* Stop scanning if we've hit the limit. */
481 if (lim_pc
!= 0 && pc
>= lim_pc
)
484 prev_insn_was_prologue_insn
= 1;
486 /* Fetch the instruction and convert it to an integer. */
487 if (target_read_memory (pc
, buf
, 4))
489 op
= extract_signed_integer (buf
, 4);
491 if ((op
& 0xfc1fffff) == 0x7c0802a6)
493 /* Since shared library / PIC code, which needs to get its
494 address at runtime, can appear to save more than one link
508 remember just the first one, but skip over additional
511 lr_reg
= (op
& 0x03e00000);
514 else if ((op
& 0xfc1fffff) == 0x7c000026)
516 cr_reg
= (op
& 0x03e00000);
520 else if ((op
& 0xfc1f0000) == 0xd8010000)
521 { /* stfd Rx,NUM(r1) */
522 reg
= GET_SRC_REG (op
);
523 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
525 fdata
->saved_fpr
= reg
;
526 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
531 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
532 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
533 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
534 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
537 reg
= GET_SRC_REG (op
);
538 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
540 fdata
->saved_gpr
= reg
;
541 if ((op
& 0xfc1f0003) == 0xf8010000)
543 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
548 else if ((op
& 0xffff0000) == 0x60000000)
551 /* Allow nops in the prologue, but do not consider them to
552 be part of the prologue unless followed by other prologue
554 prev_insn_was_prologue_insn
= 0;
558 else if ((op
& 0xffff0000) == 0x3c000000)
559 { /* addis 0,0,NUM, used
561 fdata
->offset
= (op
& 0x0000ffff) << 16;
562 fdata
->frameless
= 0;
566 else if ((op
& 0xffff0000) == 0x60000000)
567 { /* ori 0,0,NUM, 2nd ha
568 lf of >= 32k frames */
569 fdata
->offset
|= (op
& 0x0000ffff);
570 fdata
->frameless
= 0;
574 else if (lr_reg
!= -1 &&
575 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
576 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
577 /* stw Rx, NUM(r1) */
578 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
579 /* stwu Rx, NUM(r1) */
580 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
581 { /* where Rx == lr */
582 fdata
->lr_offset
= offset
;
583 fdata
->nosavedpc
= 0;
585 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
586 (op
& 0xfc000000) == 0x90000000) /* stw */
588 /* Does not update r1, so add displacement to lr_offset. */
589 fdata
->lr_offset
+= SIGNED_SHORT (op
);
594 else if (cr_reg
!= -1 &&
595 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
596 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
597 /* stw Rx, NUM(r1) */
598 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
599 /* stwu Rx, NUM(r1) */
600 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
601 { /* where Rx == cr */
602 fdata
->cr_offset
= offset
;
604 if ((op
& 0xfc000003) == 0xf8000000 ||
605 (op
& 0xfc000000) == 0x90000000)
607 /* Does not update r1, so add displacement to cr_offset. */
608 fdata
->cr_offset
+= SIGNED_SHORT (op
);
613 else if (op
== 0x48000005)
619 else if (op
== 0x48000004)
624 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
625 in V.4 -mminimal-toc */
626 (op
& 0xffff0000) == 0x3bde0000)
627 { /* addi 30,30,foo@l */
631 else if ((op
& 0xfc000001) == 0x48000001)
635 fdata
->frameless
= 0;
636 /* Don't skip over the subroutine call if it is not within
637 the first three instructions of the prologue. */
638 if ((pc
- orig_pc
) > 8)
641 op
= read_memory_integer (pc
+ 4, 4);
643 /* At this point, make sure this is not a trampoline
644 function (a function that simply calls another functions,
645 and nothing else). If the next is not a nop, this branch
646 was part of the function prologue. */
648 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
649 break; /* don't skip over
654 /* update stack pointer */
655 else if ((op
& 0xfc1f0000) == 0x94010000)
656 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
657 fdata
->frameless
= 0;
658 fdata
->offset
= SIGNED_SHORT (op
);
659 offset
= fdata
->offset
;
662 else if ((op
& 0xfc1f016a) == 0x7c01016e)
663 { /* stwux rX,r1,rY */
664 /* no way to figure out what r1 is going to be */
665 fdata
->frameless
= 0;
666 offset
= fdata
->offset
;
669 else if ((op
& 0xfc1f0003) == 0xf8010001)
670 { /* stdu rX,NUM(r1) */
671 fdata
->frameless
= 0;
672 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
673 offset
= fdata
->offset
;
676 else if ((op
& 0xfc1f016a) == 0x7c01016a)
677 { /* stdux rX,r1,rY */
678 /* no way to figure out what r1 is going to be */
679 fdata
->frameless
= 0;
680 offset
= fdata
->offset
;
683 /* Load up minimal toc pointer */
684 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
685 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
686 && !minimal_toc_loaded
)
688 minimal_toc_loaded
= 1;
691 /* move parameters from argument registers to local variable
694 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
695 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
696 (((op
>> 21) & 31) <= 10) &&
697 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
701 /* store parameters in stack */
703 /* Move parameters from argument registers to temporary register. */
704 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
705 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
706 (((op
>> 21) & 31) <= 10) &&
707 (((op
>> 16) & 31) == 0)) /* Rx: scratch register r0 */
711 else if ((op
& 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */
712 (op
& 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */
713 (op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
717 /* store parameters in stack via frame pointer */
720 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
721 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
722 (op
& 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r31) */
723 (op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
727 /* Set up frame pointer */
729 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
732 fdata
->frameless
= 0;
734 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
737 /* Another way to set up the frame pointer. */
739 else if ((op
& 0xfc1fffff) == 0x38010000)
740 { /* addi rX, r1, 0x0 */
741 fdata
->frameless
= 0;
743 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
744 + ((op
& ~0x38010000) >> 21));
747 /* AltiVec related instructions. */
748 /* Store the vrsave register (spr 256) in another register for
749 later manipulation, or load a register into the vrsave
750 register. 2 instructions are used: mfvrsave and
751 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
752 and mtspr SPR256, Rn. */
753 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
754 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
755 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
757 vrsave_reg
= GET_SRC_REG (op
);
760 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
764 /* Store the register where vrsave was saved to onto the stack:
765 rS is the register where vrsave was stored in a previous
767 /* 100100 sssss 00001 dddddddd dddddddd */
768 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
770 if (vrsave_reg
== GET_SRC_REG (op
))
772 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
777 /* Compute the new value of vrsave, by modifying the register
778 where vrsave was saved to. */
779 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
780 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
784 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
785 in a pair of insns to save the vector registers on the
787 /* 001110 00000 00000 iiii iiii iiii iiii */
788 /* 001110 01110 00000 iiii iiii iiii iiii */
789 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
790 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
793 vr_saved_offset
= SIGNED_SHORT (op
);
795 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
796 /* 011111 sssss 11111 00000 00111001110 */
797 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
799 if (pc
== (li_found_pc
+ 4))
801 vr_reg
= GET_SRC_REG (op
);
802 /* If this is the first vector reg to be saved, or if
803 it has a lower number than others previously seen,
804 reupdate the frame info. */
805 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
807 fdata
->saved_vr
= vr_reg
;
808 fdata
->vr_offset
= vr_saved_offset
+ offset
;
810 vr_saved_offset
= -1;
815 /* End AltiVec related instructions. */
817 /* Start BookE related instructions. */
818 /* Store gen register S at (r31+uimm).
819 Any register less than r13 is volatile, so we don't care. */
820 /* 000100 sssss 11111 iiiii 01100100001 */
821 else if (arch_info
->mach
== bfd_mach_ppc_e500
822 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
824 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
827 ev_reg
= GET_SRC_REG (op
);
828 imm
= (op
>> 11) & 0x1f;
830 /* If this is the first vector reg to be saved, or if
831 it has a lower number than others previously seen,
832 reupdate the frame info. */
833 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
835 fdata
->saved_ev
= ev_reg
;
836 fdata
->ev_offset
= ev_offset
+ offset
;
841 /* Store gen register rS at (r1+rB). */
842 /* 000100 sssss 00001 bbbbb 01100100000 */
843 else if (arch_info
->mach
== bfd_mach_ppc_e500
844 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
846 if (pc
== (li_found_pc
+ 4))
848 ev_reg
= GET_SRC_REG (op
);
849 /* If this is the first vector reg to be saved, or if
850 it has a lower number than others previously seen,
851 reupdate the frame info. */
852 /* We know the contents of rB from the previous instruction. */
853 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
855 fdata
->saved_ev
= ev_reg
;
856 fdata
->ev_offset
= vr_saved_offset
+ offset
;
858 vr_saved_offset
= -1;
864 /* Store gen register r31 at (rA+uimm). */
865 /* 000100 11111 aaaaa iiiii 01100100001 */
866 else if (arch_info
->mach
== bfd_mach_ppc_e500
867 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
869 /* Wwe know that the source register is 31 already, but
870 it can't hurt to compute it. */
871 ev_reg
= GET_SRC_REG (op
);
872 ev_offset
= ((op
>> 11) & 0x1f) * 8;
873 /* If this is the first vector reg to be saved, or if
874 it has a lower number than others previously seen,
875 reupdate the frame info. */
876 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
878 fdata
->saved_ev
= ev_reg
;
879 fdata
->ev_offset
= ev_offset
+ offset
;
884 /* Store gen register S at (r31+r0).
885 Store param on stack when offset from SP bigger than 4 bytes. */
886 /* 000100 sssss 11111 00000 01100100000 */
887 else if (arch_info
->mach
== bfd_mach_ppc_e500
888 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
890 if (pc
== (li_found_pc
+ 4))
892 if ((op
& 0x03e00000) >= 0x01a00000)
894 ev_reg
= GET_SRC_REG (op
);
895 /* If this is the first vector reg to be saved, or if
896 it has a lower number than others previously seen,
897 reupdate the frame info. */
898 /* We know the contents of r0 from the previous
900 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
902 fdata
->saved_ev
= ev_reg
;
903 fdata
->ev_offset
= vr_saved_offset
+ offset
;
907 vr_saved_offset
= -1;
912 /* End BookE related instructions. */
916 /* Not a recognized prologue instruction.
917 Handle optimizer code motions into the prologue by continuing
918 the search if we have no valid frame yet or if the return
919 address is not yet saved in the frame. */
920 if (fdata
->frameless
== 0
921 && (lr_reg
== -1 || fdata
->nosavedpc
== 0))
924 if (op
== 0x4e800020 /* blr */
925 || op
== 0x4e800420) /* bctr */
926 /* Do not scan past epilogue in frameless functions or
929 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
930 /* Never skip branches. */
933 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
934 /* Do not scan too many insns, scanning insns is expensive with
938 /* Continue scanning. */
939 prev_insn_was_prologue_insn
= 0;
945 /* I have problems with skipping over __main() that I need to address
946 * sometime. Previously, I used to use misc_function_vector which
947 * didn't work as well as I wanted to be. -MGO */
949 /* If the first thing after skipping a prolog is a branch to a function,
950 this might be a call to an initializer in main(), introduced by gcc2.
951 We'd like to skip over it as well. Fortunately, xlc does some extra
952 work before calling a function right after a prologue, thus we can
953 single out such gcc2 behaviour. */
956 if ((op
& 0xfc000001) == 0x48000001)
957 { /* bl foo, an initializer function? */
958 op
= read_memory_integer (pc
+ 4, 4);
960 if (op
== 0x4def7b82)
961 { /* cror 0xf, 0xf, 0xf (nop) */
963 /* Check and see if we are in main. If so, skip over this
964 initializer function as well. */
966 tmp
= find_pc_misc_function (pc
);
968 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
974 fdata
->offset
= -fdata
->offset
;
975 return last_prologue_pc
;
979 /*************************************************************************
980 Support for creating pushing a dummy frame into the stack, and popping
982 *************************************************************************/
985 /* All the ABI's require 16 byte alignment. */
987 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
992 /* Pass the arguments in either registers, or in the stack. In RS/6000,
993 the first eight words of the argument list (that might be less than
994 eight parameters if some parameters occupy more than one word) are
995 passed in r3..r10 registers. float and double parameters are
996 passed in fpr's, in addition to that. Rest of the parameters if any
997 are passed in user stack. There might be cases in which half of the
998 parameter is copied into registers, the other half is pushed into
1001 Stack must be aligned on 64-bit boundaries when synthesizing
1004 If the function is returning a structure, then the return address is passed
1005 in r3, then the first 7 words of the parameters can be passed in registers,
1006 starting from r4. */
1009 rs6000_push_dummy_call (struct gdbarch
*gdbarch
, CORE_ADDR func_addr
,
1010 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1011 int nargs
, struct value
**args
, CORE_ADDR sp
,
1012 int struct_return
, CORE_ADDR struct_addr
)
1014 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1017 int argno
; /* current argument number */
1018 int argbytes
; /* current argument byte */
1019 char tmp_buffer
[50];
1020 int f_argno
= 0; /* current floating point argno */
1021 int wordsize
= gdbarch_tdep (current_gdbarch
)->wordsize
;
1023 struct value
*arg
= 0;
1028 /* The first eight words of ther arguments are passed in registers.
1029 Copy them appropriately. */
1032 /* If the function is returning a `struct', then the first word
1033 (which will be passed in r3) is used for struct return address.
1034 In that case we should advance one word and start from r4
1035 register to copy parameters. */
1038 regcache_raw_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1044 effectively indirect call... gcc does...
1046 return_val example( float, int);
1049 float in fp0, int in r3
1050 offset of stack on overflow 8/16
1051 for varargs, must go by type.
1053 float in r3&r4, int in r5
1054 offset of stack on overflow different
1056 return in r3 or f0. If no float, must study how gcc emulates floats;
1057 pay attention to arg promotion.
1058 User may have to cast\args to handle promotion correctly
1059 since gdb won't know if prototype supplied or not.
1062 for (argno
= 0, argbytes
= 0; argno
< nargs
&& ii
< 8; ++ii
)
1064 int reg_size
= DEPRECATED_REGISTER_RAW_SIZE (ii
+ 3);
1067 type
= check_typedef (VALUE_TYPE (arg
));
1068 len
= TYPE_LENGTH (type
);
1070 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1073 /* Floating point arguments are passed in fpr's, as well as gpr's.
1074 There are 13 fpr's reserved for passing parameters. At this point
1075 there is no way we would run out of them. */
1079 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno
);
1081 memcpy (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (FP0_REGNUM
+ 1 + f_argno
)],
1082 VALUE_CONTENTS (arg
),
1090 /* Argument takes more than one register. */
1091 while (argbytes
< len
)
1093 memset (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)], 0,
1095 memcpy (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)],
1096 ((char *) VALUE_CONTENTS (arg
)) + argbytes
,
1097 (len
- argbytes
) > reg_size
1098 ? reg_size
: len
- argbytes
);
1099 ++ii
, argbytes
+= reg_size
;
1102 goto ran_out_of_registers_for_arguments
;
1109 /* Argument can fit in one register. No problem. */
1110 int adj
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? reg_size
- len
: 0;
1111 memset (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)], 0, reg_size
);
1112 memcpy ((char *)&deprecated_registers
[DEPRECATED_REGISTER_BYTE (ii
+ 3)] + adj
,
1113 VALUE_CONTENTS (arg
), len
);
1118 ran_out_of_registers_for_arguments
:
1120 saved_sp
= read_sp ();
1122 /* Location for 8 parameters are always reserved. */
1125 /* Another six words for back chain, TOC register, link register, etc. */
1128 /* Stack pointer must be quadword aligned. */
1131 /* If there are more arguments, allocate space for them in
1132 the stack, then push them starting from the ninth one. */
1134 if ((argno
< nargs
) || argbytes
)
1140 space
+= ((len
- argbytes
+ 3) & -4);
1146 for (; jj
< nargs
; ++jj
)
1148 struct value
*val
= args
[jj
];
1149 space
+= ((TYPE_LENGTH (VALUE_TYPE (val
))) + 3) & -4;
1152 /* Add location required for the rest of the parameters. */
1153 space
= (space
+ 15) & -16;
1156 /* This is another instance we need to be concerned about
1157 securing our stack space. If we write anything underneath %sp
1158 (r1), we might conflict with the kernel who thinks he is free
1159 to use this area. So, update %sp first before doing anything
1162 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1164 /* If the last argument copied into the registers didn't fit there
1165 completely, push the rest of it into stack. */
1169 write_memory (sp
+ 24 + (ii
* 4),
1170 ((char *) VALUE_CONTENTS (arg
)) + argbytes
,
1173 ii
+= ((len
- argbytes
+ 3) & -4) / 4;
1176 /* Push the rest of the arguments into stack. */
1177 for (; argno
< nargs
; ++argno
)
1181 type
= check_typedef (VALUE_TYPE (arg
));
1182 len
= TYPE_LENGTH (type
);
1185 /* Float types should be passed in fpr's, as well as in the
1187 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& f_argno
< 13)
1192 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno
);
1194 memcpy (&deprecated_registers
[DEPRECATED_REGISTER_BYTE (FP0_REGNUM
+ 1 + f_argno
)],
1195 VALUE_CONTENTS (arg
),
1200 write_memory (sp
+ 24 + (ii
* 4), (char *) VALUE_CONTENTS (arg
), len
);
1201 ii
+= ((len
+ 3) & -4) / 4;
1205 /* Set the stack pointer. According to the ABI, the SP is meant to
1206 be set _before_ the corresponding stack space is used. On AIX,
1207 this even applies when the target has been completely stopped!
1208 Not doing this can lead to conflicts with the kernel which thinks
1209 that it still has control over this not-yet-allocated stack
1211 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1213 /* Set back chain properly. */
1214 store_unsigned_integer (tmp_buffer
, 4, saved_sp
);
1215 write_memory (sp
, tmp_buffer
, 4);
1217 /* Point the inferior function call's return address at the dummy's
1219 regcache_raw_write_signed (regcache
, tdep
->ppc_lr_regnum
, bp_addr
);
1221 /* Set the TOC register, get the value from the objfile reader
1222 which, in turn, gets it from the VMAP table. */
1223 if (rs6000_find_toc_address_hook
!= NULL
)
1225 CORE_ADDR tocvalue
= (*rs6000_find_toc_address_hook
) (func_addr
);
1226 regcache_raw_write_signed (regcache
, tdep
->ppc_toc_regnum
, tocvalue
);
1229 target_store_registers (-1);
1233 /* PowerOpen always puts structures in memory. Vectors, which were
1234 added later, do get returned in a register though. */
1237 rs6000_use_struct_convention (int gcc_p
, struct type
*value_type
)
1239 if ((TYPE_LENGTH (value_type
) == 16 || TYPE_LENGTH (value_type
) == 8)
1240 && TYPE_VECTOR (value_type
))
1246 rs6000_extract_return_value (struct type
*valtype
, char *regbuf
, char *valbuf
)
1249 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1251 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
)
1256 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1257 We need to truncate the return value into float size (4 byte) if
1260 if (TYPE_LENGTH (valtype
) > 4) /* this is a double */
1262 ®buf
[DEPRECATED_REGISTER_BYTE (FP0_REGNUM
+ 1)],
1263 TYPE_LENGTH (valtype
));
1266 memcpy (&dd
, ®buf
[DEPRECATED_REGISTER_BYTE (FP0_REGNUM
+ 1)], 8);
1268 memcpy (valbuf
, &ff
, sizeof (float));
1271 else if (TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
1272 && TYPE_LENGTH (valtype
) == 16
1273 && TYPE_VECTOR (valtype
))
1275 memcpy (valbuf
, regbuf
+ DEPRECATED_REGISTER_BYTE (tdep
->ppc_vr0_regnum
+ 2),
1276 TYPE_LENGTH (valtype
));
1280 /* return value is copied starting from r3. */
1281 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
1282 && TYPE_LENGTH (valtype
) < DEPRECATED_REGISTER_RAW_SIZE (3))
1283 offset
= DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype
);
1286 regbuf
+ DEPRECATED_REGISTER_BYTE (3) + offset
,
1287 TYPE_LENGTH (valtype
));
1291 /* Return whether handle_inferior_event() should proceed through code
1292 starting at PC in function NAME when stepping.
1294 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1295 handle memory references that are too distant to fit in instructions
1296 generated by the compiler. For example, if 'foo' in the following
1301 is greater than 32767, the linker might replace the lwz with a branch to
1302 somewhere in @FIX1 that does the load in 2 instructions and then branches
1303 back to where execution should continue.
1305 GDB should silently step over @FIX code, just like AIX dbx does.
1306 Unfortunately, the linker uses the "b" instruction for the branches,
1307 meaning that the link register doesn't get set. Therefore, GDB's usual
1308 step_over_function() mechanism won't work.
1310 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
1311 in handle_inferior_event() to skip past @FIX code. */
1314 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
1316 return name
&& !strncmp (name
, "@FIX", 4);
1319 /* Skip code that the user doesn't want to see when stepping:
1321 1. Indirect function calls use a piece of trampoline code to do context
1322 switching, i.e. to set the new TOC table. Skip such code if we are on
1323 its first instruction (as when we have single-stepped to here).
1325 2. Skip shared library trampoline code (which is different from
1326 indirect function call trampolines).
1328 3. Skip bigtoc fixup code.
1330 Result is desired PC to step until, or NULL if we are not in
1331 code that should be skipped. */
1334 rs6000_skip_trampoline_code (CORE_ADDR pc
)
1336 unsigned int ii
, op
;
1338 CORE_ADDR solib_target_pc
;
1339 struct minimal_symbol
*msymbol
;
1341 static unsigned trampoline_code
[] =
1343 0x800b0000, /* l r0,0x0(r11) */
1344 0x90410014, /* st r2,0x14(r1) */
1345 0x7c0903a6, /* mtctr r0 */
1346 0x804b0004, /* l r2,0x4(r11) */
1347 0x816b0008, /* l r11,0x8(r11) */
1348 0x4e800420, /* bctr */
1349 0x4e800020, /* br */
1353 /* Check for bigtoc fixup code. */
1354 msymbol
= lookup_minimal_symbol_by_pc (pc
);
1355 if (msymbol
&& rs6000_in_solib_return_trampoline (pc
, DEPRECATED_SYMBOL_NAME (msymbol
)))
1357 /* Double-check that the third instruction from PC is relative "b". */
1358 op
= read_memory_integer (pc
+ 8, 4);
1359 if ((op
& 0xfc000003) == 0x48000000)
1361 /* Extract bits 6-29 as a signed 24-bit relative word address and
1362 add it to the containing PC. */
1363 rel
= ((int)(op
<< 6) >> 6);
1364 return pc
+ 8 + rel
;
1368 /* If pc is in a shared library trampoline, return its target. */
1369 solib_target_pc
= find_solib_trampoline_target (pc
);
1370 if (solib_target_pc
)
1371 return solib_target_pc
;
1373 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
1375 op
= read_memory_integer (pc
+ (ii
* 4), 4);
1376 if (op
!= trampoline_code
[ii
])
1379 ii
= read_register (11); /* r11 holds destination addr */
1380 pc
= read_memory_addr (ii
, gdbarch_tdep (current_gdbarch
)->wordsize
); /* (r11) value */
1384 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1385 isn't available with that word size, return 0. */
1388 regsize (const struct reg
*reg
, int wordsize
)
1390 return wordsize
== 8 ? reg
->sz64
: reg
->sz32
;
1393 /* Return the name of register number N, or null if no such register exists
1394 in the current architecture. */
1397 rs6000_register_name (int n
)
1399 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1400 const struct reg
*reg
= tdep
->regs
+ n
;
1402 if (!regsize (reg
, tdep
->wordsize
))
1407 /* Index within `registers' of the first byte of the space for
1411 rs6000_register_byte (int n
)
1413 return gdbarch_tdep (current_gdbarch
)->regoff
[n
];
1416 /* Return the number of bytes of storage in the actual machine representation
1417 for register N if that register is available, else return 0. */
1420 rs6000_register_raw_size (int n
)
1422 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1423 const struct reg
*reg
= tdep
->regs
+ n
;
1424 return regsize (reg
, tdep
->wordsize
);
1427 /* Return the GDB type object for the "standard" data type
1428 of data in register N. */
1430 static struct type
*
1431 rs6000_register_virtual_type (int n
)
1433 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1434 const struct reg
*reg
= tdep
->regs
+ n
;
1437 return builtin_type_double
;
1440 int size
= regsize (reg
, tdep
->wordsize
);
1444 return builtin_type_int0
;
1446 return builtin_type_uint32
;
1448 if (tdep
->ppc_ev0_regnum
<= n
&& n
<= tdep
->ppc_ev31_regnum
)
1449 return builtin_type_vec64
;
1451 return builtin_type_uint64
;
1454 return builtin_type_vec128
;
1457 internal_error (__FILE__
, __LINE__
, "Register %d size %d unknown",
1463 /* Return whether register N requires conversion when moving from raw format
1466 The register format for RS/6000 floating point registers is always
1467 double, we need a conversion if the memory format is float. */
1470 rs6000_register_convertible (int n
)
1472 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ n
;
1476 /* Convert data from raw format for register N in buffer FROM
1477 to virtual format with type TYPE in buffer TO. */
1480 rs6000_register_convert_to_virtual (int n
, struct type
*type
,
1481 char *from
, char *to
)
1483 if (TYPE_LENGTH (type
) != DEPRECATED_REGISTER_RAW_SIZE (n
))
1485 double val
= deprecated_extract_floating (from
, DEPRECATED_REGISTER_RAW_SIZE (n
));
1486 deprecated_store_floating (to
, TYPE_LENGTH (type
), val
);
1489 memcpy (to
, from
, DEPRECATED_REGISTER_RAW_SIZE (n
));
1492 /* Convert data from virtual format with type TYPE in buffer FROM
1493 to raw format for register N in buffer TO. */
1496 rs6000_register_convert_to_raw (struct type
*type
, int n
,
1497 const char *from
, char *to
)
1499 if (TYPE_LENGTH (type
) != DEPRECATED_REGISTER_RAW_SIZE (n
))
1501 double val
= deprecated_extract_floating (from
, TYPE_LENGTH (type
));
1502 deprecated_store_floating (to
, DEPRECATED_REGISTER_RAW_SIZE (n
), val
);
1505 memcpy (to
, from
, DEPRECATED_REGISTER_RAW_SIZE (n
));
1509 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1510 int reg_nr
, void *buffer
)
1514 char temp_buffer
[MAX_REGISTER_SIZE
];
1515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1517 if (reg_nr
>= tdep
->ppc_gp0_regnum
1518 && reg_nr
<= tdep
->ppc_gplast_regnum
)
1520 base_regnum
= reg_nr
- tdep
->ppc_gp0_regnum
+ tdep
->ppc_ev0_regnum
;
1522 /* Build the value in the provided buffer. */
1523 /* Read the raw register of which this one is the lower portion. */
1524 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1525 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1527 memcpy ((char *) buffer
, temp_buffer
+ offset
, 4);
1532 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1533 int reg_nr
, const void *buffer
)
1537 char temp_buffer
[MAX_REGISTER_SIZE
];
1538 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1540 if (reg_nr
>= tdep
->ppc_gp0_regnum
1541 && reg_nr
<= tdep
->ppc_gplast_regnum
)
1543 base_regnum
= reg_nr
- tdep
->ppc_gp0_regnum
+ tdep
->ppc_ev0_regnum
;
1544 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1545 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1548 /* Let's read the value of the base register into a temporary
1549 buffer, so that overwriting the last four bytes with the new
1550 value of the pseudo will leave the upper 4 bytes unchanged. */
1551 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
1553 /* Write as an 8 byte quantity. */
1554 memcpy (temp_buffer
+ offset
, (char *) buffer
, 4);
1555 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
1559 /* Convert a dbx stab or Dwarf 2 register number (from `r'
1560 declaration) to a gdb REGNUM. */
1562 rs6000_dwarf2_stab_reg_to_regnum (int num
)
1564 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1566 if (0 <= num
&& num
<= 31)
1567 return tdep
->ppc_gp0_regnum
+ num
;
1568 else if (32 <= num
&& num
<= 63)
1569 return FP0_REGNUM
+ (num
- 32);
1570 else if (1200 <= num
&& num
< 1200 + 32)
1571 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
1576 return tdep
->ppc_mq_regnum
;
1578 return tdep
->ppc_lr_regnum
;
1580 return tdep
->ppc_ctr_regnum
;
1582 return tdep
->ppc_xer_regnum
;
1584 return tdep
->ppc_vrsave_regnum
;
1589 /* FIXME: jimb/2004-03-28: Doesn't something need to be done here
1590 for the Altivec registers, too?
1592 Looking at GCC, the headers in config/rs6000 never define a
1593 DBX_REGISTER_NUMBER macro, so the debug info uses the same
1594 numbers GCC does internally. Then, looking at the REGISTER_NAMES
1595 macro defined in config/rs6000/rs6000.h, it seems that GCC gives
1596 v0 -- v31 the numbers 77 -- 108. But we number them 119 -- 150.
1598 I don't have a way to test this ready to hand, but I noticed it
1599 and thought I should include a note. */
1603 rs6000_store_return_value (struct type
*type
, char *valbuf
)
1605 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1607 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1609 /* Floating point values are returned starting from FPR1 and up.
1610 Say a double_double_double type could be returned in
1611 FPR1/FPR2/FPR3 triple. */
1613 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (FP0_REGNUM
+ 1), valbuf
,
1614 TYPE_LENGTH (type
));
1615 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
1617 if (TYPE_LENGTH (type
) == 16
1618 && TYPE_VECTOR (type
))
1619 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep
->ppc_vr0_regnum
+ 2),
1620 valbuf
, TYPE_LENGTH (type
));
1623 /* Everything else is returned in GPR3 and up. */
1624 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch
)->ppc_gp0_regnum
+ 3),
1625 valbuf
, TYPE_LENGTH (type
));
1628 /* Extract from an array REGBUF containing the (raw) register state
1629 the address in which a function should return its structure value,
1630 as a CORE_ADDR (or an expression that can be used as one). */
1633 rs6000_extract_struct_value_address (struct regcache
*regcache
)
1635 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
1636 function call GDB knows the address of the struct return value
1637 and hence, should not need to call this function. Unfortunately,
1638 the current call_function_by_hand() code only saves the most
1639 recent struct address leading to occasional calls. The code
1640 should instead maintain a stack of such addresses (in the dummy
1642 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
1643 really got no idea where the return value is being stored. While
1644 r3, on function entry, contained the address it will have since
1645 been reused (scratch) and hence wouldn't be valid */
1649 /* Hook called when a new child process is started. */
1652 rs6000_create_inferior (int pid
)
1654 if (rs6000_set_host_arch_hook
)
1655 rs6000_set_host_arch_hook (pid
);
1658 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
1660 Usually a function pointer's representation is simply the address
1661 of the function. On the RS/6000 however, a function pointer is
1662 represented by a pointer to a TOC entry. This TOC entry contains
1663 three words, the first word is the address of the function, the
1664 second word is the TOC pointer (r2), and the third word is the
1665 static chain value. Throughout GDB it is currently assumed that a
1666 function pointer contains the address of the function, which is not
1667 easy to fix. In addition, the conversion of a function address to
1668 a function pointer would require allocation of a TOC entry in the
1669 inferior's memory space, with all its drawbacks. To be able to
1670 call C++ virtual methods in the inferior (which are called via
1671 function pointers), find_function_addr uses this function to get the
1672 function address from a function pointer. */
1674 /* Return real function address if ADDR (a function pointer) is in the data
1675 space and is therefore a special function pointer. */
1678 rs6000_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
,
1680 struct target_ops
*targ
)
1682 struct obj_section
*s
;
1684 s
= find_pc_section (addr
);
1685 if (s
&& s
->the_bfd_section
->flags
& SEC_CODE
)
1688 /* ADDR is in the data space, so it's a special function pointer. */
1689 return read_memory_addr (addr
, gdbarch_tdep (current_gdbarch
)->wordsize
);
1693 /* Handling the various POWER/PowerPC variants. */
1696 /* The arrays here called registers_MUMBLE hold information about available
1699 For each family of PPC variants, I've tried to isolate out the
1700 common registers and put them up front, so that as long as you get
1701 the general family right, GDB will correctly identify the registers
1702 common to that family. The common register sets are:
1704 For the 60x family: hid0 hid1 iabr dabr pir
1706 For the 505 and 860 family: eie eid nri
1708 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
1709 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
1712 Most of these register groups aren't anything formal. I arrived at
1713 them by looking at the registers that occurred in more than one
1716 Note: kevinb/2002-04-30: Support for the fpscr register was added
1717 during April, 2002. Slot 70 is being used for PowerPC and slot 71
1718 for Power. For PowerPC, slot 70 was unused and was already in the
1719 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
1720 slot 70 was being used for "mq", so the next available slot (71)
1721 was chosen. It would have been nice to be able to make the
1722 register numbers the same across processor cores, but this wasn't
1723 possible without either 1) renumbering some registers for some
1724 processors or 2) assigning fpscr to a really high slot that's
1725 larger than any current register number. Doing (1) is bad because
1726 existing stubs would break. Doing (2) is undesirable because it
1727 would introduce a really large gap between fpscr and the rest of
1728 the registers for most processors. */
1730 /* Convenience macros for populating register arrays. */
1732 /* Within another macro, convert S to a string. */
1736 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
1737 and 64 bits on 64-bit systems. */
1738 #define R(name) { STR(name), 4, 8, 0, 0 }
1740 /* Return a struct reg defining register NAME that's 32 bits on all
1742 #define R4(name) { STR(name), 4, 4, 0, 0 }
1744 /* Return a struct reg defining register NAME that's 64 bits on all
1746 #define R8(name) { STR(name), 8, 8, 0, 0 }
1748 /* Return a struct reg defining register NAME that's 128 bits on all
1750 #define R16(name) { STR(name), 16, 16, 0, 0 }
1752 /* Return a struct reg defining floating-point register NAME. */
1753 #define F(name) { STR(name), 8, 8, 1, 0 }
1755 /* Return a struct reg defining a pseudo register NAME. */
1756 #define P(name) { STR(name), 4, 8, 0, 1}
1758 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
1759 systems and that doesn't exist on 64-bit systems. */
1760 #define R32(name) { STR(name), 4, 0, 0, 0 }
1762 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
1763 systems and that doesn't exist on 32-bit systems. */
1764 #define R64(name) { STR(name), 0, 8, 0, 0 }
1766 /* Return a struct reg placeholder for a register that doesn't exist. */
1767 #define R0 { 0, 0, 0, 0, 0 }
1769 /* UISA registers common across all architectures, including POWER. */
1771 #define COMMON_UISA_REGS \
1772 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
1773 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
1774 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
1775 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
1776 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
1777 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
1778 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
1779 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
1780 /* 64 */ R(pc), R(ps)
1782 #define COMMON_UISA_NOFP_REGS \
1783 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
1784 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
1785 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
1786 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
1787 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1788 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1789 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1790 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1791 /* 64 */ R(pc), R(ps)
1793 /* UISA-level SPRs for PowerPC. */
1794 #define PPC_UISA_SPRS \
1795 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
1797 /* UISA-level SPRs for PowerPC without floating point support. */
1798 #define PPC_UISA_NOFP_SPRS \
1799 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
1801 /* Segment registers, for PowerPC. */
1802 #define PPC_SEGMENT_REGS \
1803 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
1804 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
1805 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
1806 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
1808 /* OEA SPRs for PowerPC. */
1809 #define PPC_OEA_SPRS \
1811 /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
1812 /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
1813 /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
1814 /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
1815 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
1816 /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
1817 /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
1818 /* 116 */ R4(dec), R(dabr), R4(ear)
1820 /* AltiVec registers. */
1821 #define PPC_ALTIVEC_REGS \
1822 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
1823 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
1824 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
1825 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
1826 /*151*/R4(vscr), R4(vrsave)
1828 /* Vectors of hi-lo general purpose registers. */
1829 #define PPC_EV_REGS \
1830 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
1831 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
1832 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
1833 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
1835 /* Lower half of the EV registers. */
1836 #define PPC_GPRS_PSEUDO_REGS \
1837 /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \
1838 /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \
1839 /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \
1840 /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31)
1842 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
1843 user-level SPR's. */
1844 static const struct reg registers_power
[] =
1847 /* 66 */ R4(cnd
), R(lr
), R(cnt
), R4(xer
), R4(mq
),
1851 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
1852 view of the PowerPC. */
1853 static const struct reg registers_powerpc
[] =
1860 /* PowerPC UISA - a PPC processor as viewed by user-level
1861 code, but without floating point registers. */
1862 static const struct reg registers_powerpc_nofp
[] =
1864 COMMON_UISA_NOFP_REGS
,
1868 /* IBM PowerPC 403. */
1869 static const struct reg registers_403
[] =
1875 /* 119 */ R(icdbdr
), R(esr
), R(dear
), R(evpr
),
1876 /* 123 */ R(cdbcr
), R(tsr
), R(tcr
), R(pit
),
1877 /* 127 */ R(tbhi
), R(tblo
), R(srr2
), R(srr3
),
1878 /* 131 */ R(dbsr
), R(dbcr
), R(iac1
), R(iac2
),
1879 /* 135 */ R(dac1
), R(dac2
), R(dccr
), R(iccr
),
1880 /* 139 */ R(pbl1
), R(pbu1
), R(pbl2
), R(pbu2
)
1883 /* IBM PowerPC 403GC. */
1884 static const struct reg registers_403GC
[] =
1890 /* 119 */ R(icdbdr
), R(esr
), R(dear
), R(evpr
),
1891 /* 123 */ R(cdbcr
), R(tsr
), R(tcr
), R(pit
),
1892 /* 127 */ R(tbhi
), R(tblo
), R(srr2
), R(srr3
),
1893 /* 131 */ R(dbsr
), R(dbcr
), R(iac1
), R(iac2
),
1894 /* 135 */ R(dac1
), R(dac2
), R(dccr
), R(iccr
),
1895 /* 139 */ R(pbl1
), R(pbu1
), R(pbl2
), R(pbu2
),
1896 /* 143 */ R(zpr
), R(pid
), R(sgr
), R(dcwr
),
1897 /* 147 */ R(tbhu
), R(tblu
)
1900 /* Motorola PowerPC 505. */
1901 static const struct reg registers_505
[] =
1907 /* 119 */ R(eie
), R(eid
), R(nri
)
1910 /* Motorola PowerPC 860 or 850. */
1911 static const struct reg registers_860
[] =
1917 /* 119 */ R(eie
), R(eid
), R(nri
), R(cmpa
),
1918 /* 123 */ R(cmpb
), R(cmpc
), R(cmpd
), R(icr
),
1919 /* 127 */ R(der
), R(counta
), R(countb
), R(cmpe
),
1920 /* 131 */ R(cmpf
), R(cmpg
), R(cmph
), R(lctrl1
),
1921 /* 135 */ R(lctrl2
), R(ictrl
), R(bar
), R(ic_cst
),
1922 /* 139 */ R(ic_adr
), R(ic_dat
), R(dc_cst
), R(dc_adr
),
1923 /* 143 */ R(dc_dat
), R(dpdr
), R(dpir
), R(immr
),
1924 /* 147 */ R(mi_ctr
), R(mi_ap
), R(mi_epn
), R(mi_twc
),
1925 /* 151 */ R(mi_rpn
), R(md_ctr
), R(m_casid
), R(md_ap
),
1926 /* 155 */ R(md_epn
), R(md_twb
), R(md_twc
), R(md_rpn
),
1927 /* 159 */ R(m_tw
), R(mi_dbcam
), R(mi_dbram0
), R(mi_dbram1
),
1928 /* 163 */ R(md_dbcam
), R(md_dbram0
), R(md_dbram1
)
1931 /* Motorola PowerPC 601. Note that the 601 has different register numbers
1932 for reading and writing RTCU and RTCL. However, how one reads and writes a
1933 register is the stub's problem. */
1934 static const struct reg registers_601
[] =
1940 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R(dabr
),
1941 /* 123 */ R(pir
), R(mq
), R(rtcu
), R(rtcl
)
1944 /* Motorola PowerPC 602. */
1945 static const struct reg registers_602
[] =
1951 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R0
,
1952 /* 123 */ R0
, R(tcr
), R(ibr
), R(esassr
),
1953 /* 127 */ R(sebr
), R(ser
), R(sp
), R(lt
)
1956 /* Motorola/IBM PowerPC 603 or 603e. */
1957 static const struct reg registers_603
[] =
1963 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R0
,
1964 /* 123 */ R0
, R(dmiss
), R(dcmp
), R(hash1
),
1965 /* 127 */ R(hash2
), R(imiss
), R(icmp
), R(rpa
)
1968 /* Motorola PowerPC 604 or 604e. */
1969 static const struct reg registers_604
[] =
1975 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R(dabr
),
1976 /* 123 */ R(pir
), R(mmcr0
), R(pmc1
), R(pmc2
),
1977 /* 127 */ R(sia
), R(sda
)
1980 /* Motorola/IBM PowerPC 750 or 740. */
1981 static const struct reg registers_750
[] =
1987 /* 119 */ R(hid0
), R(hid1
), R(iabr
), R(dabr
),
1988 /* 123 */ R0
, R(ummcr0
), R(upmc1
), R(upmc2
),
1989 /* 127 */ R(usia
), R(ummcr1
), R(upmc3
), R(upmc4
),
1990 /* 131 */ R(mmcr0
), R(pmc1
), R(pmc2
), R(sia
),
1991 /* 135 */ R(mmcr1
), R(pmc3
), R(pmc4
), R(l2cr
),
1992 /* 139 */ R(ictc
), R(thrm1
), R(thrm2
), R(thrm3
)
1996 /* Motorola PowerPC 7400. */
1997 static const struct reg registers_7400
[] =
1999 /* gpr0-gpr31, fpr0-fpr31 */
2001 /* ctr, xre, lr, cr */
2006 /* vr0-vr31, vrsave, vscr */
2008 /* FIXME? Add more registers? */
2011 /* Motorola e500. */
2012 static const struct reg registers_e500
[] =
2015 /* cr, lr, ctr, xer, "" */
2019 R8(acc
), R(spefscr
),
2020 /* NOTE: Add new registers here the end of the raw register
2021 list and just before the first pseudo register. */
2023 PPC_GPRS_PSEUDO_REGS
2026 /* Information about a particular processor variant. */
2030 /* Name of this variant. */
2033 /* English description of the variant. */
2036 /* bfd_arch_info.arch corresponding to variant. */
2037 enum bfd_architecture arch
;
2039 /* bfd_arch_info.mach corresponding to variant. */
2042 /* Number of real registers. */
2045 /* Number of pseudo registers. */
2048 /* Number of total registers (the sum of nregs and npregs). */
2051 /* Table of register names; registers[R] is the name of the register
2053 const struct reg
*regs
;
2056 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2059 num_registers (const struct reg
*reg_list
, int num_tot_regs
)
2064 for (i
= 0; i
< num_tot_regs
; i
++)
2065 if (!reg_list
[i
].pseudo
)
2072 num_pseudo_registers (const struct reg
*reg_list
, int num_tot_regs
)
2077 for (i
= 0; i
< num_tot_regs
; i
++)
2078 if (reg_list
[i
].pseudo
)
2084 /* Information in this table comes from the following web sites:
2085 IBM: http://www.chips.ibm.com:80/products/embedded/
2086 Motorola: http://www.mot.com/SPS/PowerPC/
2088 I'm sure I've got some of the variant descriptions not quite right.
2089 Please report any inaccuracies you find to GDB's maintainer.
2091 If you add entries to this table, please be sure to allow the new
2092 value as an argument to the --with-cpu flag, in configure.in. */
2094 static struct variant variants
[] =
2097 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2098 bfd_mach_ppc
, -1, -1, tot_num_registers (registers_powerpc
),
2100 {"power", "POWER user-level", bfd_arch_rs6000
,
2101 bfd_mach_rs6k
, -1, -1, tot_num_registers (registers_power
),
2103 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2104 bfd_mach_ppc_403
, -1, -1, tot_num_registers (registers_403
),
2106 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2107 bfd_mach_ppc_601
, -1, -1, tot_num_registers (registers_601
),
2109 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2110 bfd_mach_ppc_602
, -1, -1, tot_num_registers (registers_602
),
2112 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2113 bfd_mach_ppc_603
, -1, -1, tot_num_registers (registers_603
),
2115 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2116 604, -1, -1, tot_num_registers (registers_604
),
2118 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2119 bfd_mach_ppc_403gc
, -1, -1, tot_num_registers (registers_403GC
),
2121 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2122 bfd_mach_ppc_505
, -1, -1, tot_num_registers (registers_505
),
2124 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2125 bfd_mach_ppc_860
, -1, -1, tot_num_registers (registers_860
),
2127 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2128 bfd_mach_ppc_750
, -1, -1, tot_num_registers (registers_750
),
2130 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2131 bfd_mach_ppc_7400
, -1, -1, tot_num_registers (registers_7400
),
2133 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2134 bfd_mach_ppc_e500
, -1, -1, tot_num_registers (registers_e500
),
2138 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2139 bfd_mach_ppc64
, -1, -1, tot_num_registers (registers_powerpc
),
2141 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2142 bfd_mach_ppc_620
, -1, -1, tot_num_registers (registers_powerpc
),
2144 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2145 bfd_mach_ppc_630
, -1, -1, tot_num_registers (registers_powerpc
),
2147 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2148 bfd_mach_ppc_a35
, -1, -1, tot_num_registers (registers_powerpc
),
2150 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2151 bfd_mach_ppc_rs64ii
, -1, -1, tot_num_registers (registers_powerpc
),
2153 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2154 bfd_mach_ppc_rs64iii
, -1, -1, tot_num_registers (registers_powerpc
),
2157 /* FIXME: I haven't checked the register sets of the following. */
2158 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2159 bfd_mach_rs6k_rs1
, -1, -1, tot_num_registers (registers_power
),
2161 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2162 bfd_mach_rs6k_rsc
, -1, -1, tot_num_registers (registers_power
),
2164 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2165 bfd_mach_rs6k_rs2
, -1, -1, tot_num_registers (registers_power
),
2168 {0, 0, 0, 0, 0, 0, 0, 0}
2171 /* Initialize the number of registers and pseudo registers in each variant. */
2174 init_variants (void)
2178 for (v
= variants
; v
->name
; v
++)
2181 v
->nregs
= num_registers (v
->regs
, v
->num_tot_regs
);
2182 if (v
->npregs
== -1)
2183 v
->npregs
= num_pseudo_registers (v
->regs
, v
->num_tot_regs
);
2187 /* Return the variant corresponding to architecture ARCH and machine number
2188 MACH. If no such variant exists, return null. */
2190 static const struct variant
*
2191 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
2193 const struct variant
*v
;
2195 for (v
= variants
; v
->name
; v
++)
2196 if (arch
== v
->arch
&& mach
== v
->mach
)
2203 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
2205 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2206 return print_insn_big_powerpc (memaddr
, info
);
2208 return print_insn_little_powerpc (memaddr
, info
);
2212 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2214 return frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
2217 static struct frame_id
2218 rs6000_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2220 return frame_id_build (frame_unwind_register_unsigned (next_frame
,
2222 frame_pc_unwind (next_frame
));
2225 struct rs6000_frame_cache
2228 CORE_ADDR initial_sp
;
2229 struct trad_frame_saved_reg
*saved_regs
;
2232 static struct rs6000_frame_cache
*
2233 rs6000_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2235 struct rs6000_frame_cache
*cache
;
2236 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2237 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2238 struct rs6000_framedata fdata
;
2239 int wordsize
= tdep
->wordsize
;
2241 if ((*this_cache
) != NULL
)
2242 return (*this_cache
);
2243 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
2244 (*this_cache
) = cache
;
2245 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2247 skip_prologue (frame_func_unwind (next_frame
), frame_pc_unwind (next_frame
),
2250 /* If there were any saved registers, figure out parent's stack
2252 /* The following is true only if the frame doesn't have a call to
2255 if (fdata
.saved_fpr
== 0
2256 && fdata
.saved_gpr
== 0
2257 && fdata
.saved_vr
== 0
2258 && fdata
.saved_ev
== 0
2259 && fdata
.lr_offset
== 0
2260 && fdata
.cr_offset
== 0
2261 && fdata
.vr_offset
== 0
2262 && fdata
.ev_offset
== 0)
2263 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2266 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2267 address of the current frame. Things might be easier if the
2268 ->frame pointed to the outer-most address of the frame. In
2269 the mean time, the address of the prev frame is used as the
2270 base address of this frame. */
2271 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2272 if (!fdata
.frameless
)
2273 /* Frameless really means stackless. */
2274 cache
->base
= read_memory_addr (cache
->base
, wordsize
);
2276 trad_frame_set_value (cache
->saved_regs
, SP_REGNUM
, cache
->base
);
2278 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2279 All fpr's from saved_fpr to fp31 are saved. */
2281 if (fdata
.saved_fpr
>= 0)
2284 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
2285 for (i
= fdata
.saved_fpr
; i
< 32; i
++)
2287 cache
->saved_regs
[FP0_REGNUM
+ i
].addr
= fpr_addr
;
2292 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2293 All gpr's from saved_gpr to gpr31 are saved. */
2295 if (fdata
.saved_gpr
>= 0)
2298 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
2299 for (i
= fdata
.saved_gpr
; i
< 32; i
++)
2301 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
2302 gpr_addr
+= wordsize
;
2306 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2307 All vr's from saved_vr to vr31 are saved. */
2308 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
2310 if (fdata
.saved_vr
>= 0)
2313 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
2314 for (i
= fdata
.saved_vr
; i
< 32; i
++)
2316 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
2317 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
2322 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2323 All vr's from saved_ev to ev31 are saved. ????? */
2324 if (tdep
->ppc_ev0_regnum
!= -1 && tdep
->ppc_ev31_regnum
!= -1)
2326 if (fdata
.saved_ev
>= 0)
2329 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
2330 for (i
= fdata
.saved_ev
; i
< 32; i
++)
2332 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
2333 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
2334 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
2339 /* If != 0, fdata.cr_offset is the offset from the frame that
2341 if (fdata
.cr_offset
!= 0)
2342 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
2344 /* If != 0, fdata.lr_offset is the offset from the frame that
2346 if (fdata
.lr_offset
!= 0)
2347 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
2348 /* The PC is found in the link register. */
2349 cache
->saved_regs
[PC_REGNUM
] = cache
->saved_regs
[tdep
->ppc_lr_regnum
];
2351 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2352 holds the VRSAVE. */
2353 if (fdata
.vrsave_offset
!= 0)
2354 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
2356 if (fdata
.alloca_reg
< 0)
2357 /* If no alloca register used, then fi->frame is the value of the
2358 %sp for this frame, and it is good enough. */
2359 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2361 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
,
2368 rs6000_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2369 struct frame_id
*this_id
)
2371 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2373 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
2377 rs6000_frame_prev_register (struct frame_info
*next_frame
,
2379 int regnum
, int *optimizedp
,
2380 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2381 int *realnump
, void *valuep
)
2383 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2385 trad_frame_prev_register (next_frame
, info
->saved_regs
, regnum
,
2386 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2389 static const struct frame_unwind rs6000_frame_unwind
=
2392 rs6000_frame_this_id
,
2393 rs6000_frame_prev_register
2396 static const struct frame_unwind
*
2397 rs6000_frame_sniffer (struct frame_info
*next_frame
)
2399 return &rs6000_frame_unwind
;
2405 rs6000_frame_base_address (struct frame_info
*next_frame
,
2408 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
2410 return info
->initial_sp
;
2413 static const struct frame_base rs6000_frame_base
= {
2414 &rs6000_frame_unwind
,
2415 rs6000_frame_base_address
,
2416 rs6000_frame_base_address
,
2417 rs6000_frame_base_address
2420 static const struct frame_base
*
2421 rs6000_frame_base_sniffer (struct frame_info
*next_frame
)
2423 return &rs6000_frame_base
;
2426 /* Initialize the current architecture based on INFO. If possible, re-use an
2427 architecture from ARCHES, which is a list of architectures already created
2428 during this debugging session.
2430 Called e.g. at program startup, when reading a core file, and when reading
2433 static struct gdbarch
*
2434 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2436 struct gdbarch
*gdbarch
;
2437 struct gdbarch_tdep
*tdep
;
2438 int wordsize
, from_xcoff_exec
, from_elf_exec
, power
, i
, off
;
2440 const struct variant
*v
;
2441 enum bfd_architecture arch
;
2447 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2448 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
2450 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2451 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2453 sysv_abi
= info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2455 /* Check word size. If INFO is from a binary file, infer it from
2456 that, else choose a likely default. */
2457 if (from_xcoff_exec
)
2459 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
2464 else if (from_elf_exec
)
2466 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
2473 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
2474 wordsize
= info
.bfd_arch_info
->bits_per_word
/
2475 info
.bfd_arch_info
->bits_per_byte
;
2480 /* Find a candidate among extant architectures. */
2481 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2483 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
2485 /* Word size in the various PowerPC bfd_arch_info structs isn't
2486 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
2487 separate word size check. */
2488 tdep
= gdbarch_tdep (arches
->gdbarch
);
2489 if (tdep
&& tdep
->wordsize
== wordsize
)
2490 return arches
->gdbarch
;
2493 /* None found, create a new architecture from INFO, whose bfd_arch_info
2494 validity depends on the source:
2495 - executable useless
2496 - rs6000_host_arch() good
2498 - "set arch" trust blindly
2499 - GDB startup useless but harmless */
2501 if (!from_xcoff_exec
)
2503 arch
= info
.bfd_arch_info
->arch
;
2504 mach
= info
.bfd_arch_info
->mach
;
2508 arch
= bfd_arch_powerpc
;
2509 bfd_default_set_arch_mach (&abfd
, arch
, 0);
2510 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2511 mach
= info
.bfd_arch_info
->mach
;
2513 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
2514 tdep
->wordsize
= wordsize
;
2516 /* For e500 executables, the apuinfo section is of help here. Such
2517 section contains the identifier and revision number of each
2518 Application-specific Processing Unit that is present on the
2519 chip. The content of the section is determined by the assembler
2520 which looks at each instruction and determines which unit (and
2521 which version of it) can execute it. In our case we just look for
2522 the existance of the section. */
2526 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
2529 arch
= info
.bfd_arch_info
->arch
;
2530 mach
= bfd_mach_ppc_e500
;
2531 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
2532 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2536 gdbarch
= gdbarch_alloc (&info
, tdep
);
2537 power
= arch
== bfd_arch_rs6000
;
2539 /* Initialize the number of real and pseudo registers in each variant. */
2542 /* Choose variant. */
2543 v
= find_variant_by_arch (arch
, mach
);
2547 tdep
->regs
= v
->regs
;
2549 tdep
->ppc_gp0_regnum
= 0;
2550 tdep
->ppc_gplast_regnum
= 31;
2551 tdep
->ppc_toc_regnum
= 2;
2552 tdep
->ppc_ps_regnum
= 65;
2553 tdep
->ppc_cr_regnum
= 66;
2554 tdep
->ppc_lr_regnum
= 67;
2555 tdep
->ppc_ctr_regnum
= 68;
2556 tdep
->ppc_xer_regnum
= 69;
2557 if (v
->mach
== bfd_mach_ppc_601
)
2558 tdep
->ppc_mq_regnum
= 124;
2560 tdep
->ppc_mq_regnum
= 70;
2562 tdep
->ppc_mq_regnum
= -1;
2563 tdep
->ppc_fpscr_regnum
= power
? 71 : 70;
2565 set_gdbarch_pc_regnum (gdbarch
, 64);
2566 set_gdbarch_sp_regnum (gdbarch
, 1);
2567 set_gdbarch_deprecated_fp_regnum (gdbarch
, 1);
2568 if (sysv_abi
&& wordsize
== 8)
2569 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
2570 else if (sysv_abi
&& wordsize
== 4)
2571 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
2574 set_gdbarch_deprecated_extract_return_value (gdbarch
, rs6000_extract_return_value
);
2575 set_gdbarch_deprecated_store_return_value (gdbarch
, rs6000_store_return_value
);
2578 if (v
->arch
== bfd_arch_powerpc
)
2582 tdep
->ppc_vr0_regnum
= 71;
2583 tdep
->ppc_vrsave_regnum
= 104;
2584 tdep
->ppc_ev0_regnum
= -1;
2585 tdep
->ppc_ev31_regnum
= -1;
2587 case bfd_mach_ppc_7400
:
2588 tdep
->ppc_vr0_regnum
= 119;
2589 tdep
->ppc_vrsave_regnum
= 152;
2590 tdep
->ppc_ev0_regnum
= -1;
2591 tdep
->ppc_ev31_regnum
= -1;
2593 case bfd_mach_ppc_e500
:
2594 tdep
->ppc_gp0_regnum
= 41;
2595 tdep
->ppc_gplast_regnum
= tdep
->ppc_gp0_regnum
+ 32 - 1;
2596 tdep
->ppc_toc_regnum
= -1;
2597 tdep
->ppc_ps_regnum
= 1;
2598 tdep
->ppc_cr_regnum
= 2;
2599 tdep
->ppc_lr_regnum
= 3;
2600 tdep
->ppc_ctr_regnum
= 4;
2601 tdep
->ppc_xer_regnum
= 5;
2602 tdep
->ppc_ev0_regnum
= 7;
2603 tdep
->ppc_ev31_regnum
= 38;
2604 set_gdbarch_pc_regnum (gdbarch
, 0);
2605 set_gdbarch_sp_regnum (gdbarch
, tdep
->ppc_gp0_regnum
+ 1);
2606 set_gdbarch_deprecated_fp_regnum (gdbarch
, tdep
->ppc_gp0_regnum
+ 1);
2607 set_gdbarch_pseudo_register_read (gdbarch
, e500_pseudo_register_read
);
2608 set_gdbarch_pseudo_register_write (gdbarch
, e500_pseudo_register_write
);
2611 tdep
->ppc_vr0_regnum
= -1;
2612 tdep
->ppc_vrsave_regnum
= -1;
2613 tdep
->ppc_ev0_regnum
= -1;
2614 tdep
->ppc_ev31_regnum
= -1;
2618 /* Sanity check on registers. */
2619 gdb_assert (strcmp (tdep
->regs
[tdep
->ppc_gp0_regnum
].name
, "r0") == 0);
2621 /* Set lr_frame_offset. */
2623 tdep
->lr_frame_offset
= 16;
2625 tdep
->lr_frame_offset
= 4;
2627 tdep
->lr_frame_offset
= 8;
2629 /* Calculate byte offsets in raw register array. */
2630 tdep
->regoff
= xmalloc (v
->num_tot_regs
* sizeof (int));
2631 for (i
= off
= 0; i
< v
->num_tot_regs
; i
++)
2633 tdep
->regoff
[i
] = off
;
2634 off
+= regsize (v
->regs
+ i
, wordsize
);
2637 /* Select instruction printer. */
2639 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
2641 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
2643 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
2645 set_gdbarch_num_regs (gdbarch
, v
->nregs
);
2646 set_gdbarch_num_pseudo_regs (gdbarch
, v
->npregs
);
2647 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
2648 set_gdbarch_deprecated_register_size (gdbarch
, wordsize
);
2649 set_gdbarch_deprecated_register_bytes (gdbarch
, off
);
2650 set_gdbarch_deprecated_register_byte (gdbarch
, rs6000_register_byte
);
2651 set_gdbarch_deprecated_register_raw_size (gdbarch
, rs6000_register_raw_size
);
2652 set_gdbarch_deprecated_register_virtual_type (gdbarch
, rs6000_register_virtual_type
);
2654 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
2655 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2656 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2657 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
2658 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2659 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2660 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2662 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
2664 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2665 set_gdbarch_char_signed (gdbarch
, 0);
2667 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
2668 if (sysv_abi
&& wordsize
== 8)
2670 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
2671 else if (!sysv_abi
&& wordsize
== 4)
2672 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
2673 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
2674 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
2676 set_gdbarch_frame_red_zone_size (gdbarch
, 224);
2678 set_gdbarch_deprecated_register_convertible (gdbarch
, rs6000_register_convertible
);
2679 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch
, rs6000_register_convert_to_virtual
);
2680 set_gdbarch_deprecated_register_convert_to_raw (gdbarch
, rs6000_register_convert_to_raw
);
2681 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_dwarf2_stab_reg_to_regnum
);
2682 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_stab_reg_to_regnum
);
2683 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
2684 is correct for the SysV ABI when the wordsize is 8, but I'm also
2685 fairly certain that ppc_sysv_abi_push_arguments() will give even
2686 worse results since it only works for 32-bit code. So, for the moment,
2687 we're better off calling rs6000_push_arguments() since it works for
2688 64-bit code. At some point in the future, this matter needs to be
2690 if (sysv_abi
&& wordsize
== 4)
2691 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
2692 else if (sysv_abi
&& wordsize
== 8)
2693 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
2695 set_gdbarch_push_dummy_call (gdbarch
, rs6000_push_dummy_call
);
2697 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, rs6000_extract_struct_value_address
);
2699 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
2700 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2701 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
2703 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
2704 for the descriptor and ".FN" for the entry-point -- a user
2705 specifying "break FN" will unexpectedly end up with a breakpoint
2706 on the descriptor and not the function. This architecture method
2707 transforms any breakpoints on descriptors into breakpoints on the
2708 corresponding entry point. */
2709 if (sysv_abi
&& wordsize
== 8)
2710 set_gdbarch_adjust_breakpoint_address (gdbarch
, ppc64_sysv_abi_adjust_breakpoint_address
);
2712 /* Not sure on this. FIXMEmgo */
2713 set_gdbarch_frame_args_skip (gdbarch
, 8);
2716 set_gdbarch_use_struct_convention (gdbarch
,
2717 rs6000_use_struct_convention
);
2721 /* Handle RS/6000 function pointers (which are really function
2723 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
2724 rs6000_convert_from_func_ptr_addr
);
2727 /* Helpers for function argument information. */
2728 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
2730 /* Hook in ABI-specific overrides, if they have been registered. */
2731 gdbarch_init_osabi (info
, gdbarch
);
2735 case GDB_OSABI_NETBSD_AOUT
:
2736 case GDB_OSABI_NETBSD_ELF
:
2737 case GDB_OSABI_UNKNOWN
:
2738 case GDB_OSABI_LINUX
:
2739 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
2740 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
2741 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
2742 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
2745 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch
, generic_save_dummy_frame_tos
);
2746 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2748 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
2749 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
2750 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
2751 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
2754 if (from_xcoff_exec
)
2756 /* NOTE: jimix/2003-06-09: This test should really check for
2757 GDB_OSABI_AIX when that is defined and becomes
2758 available. (Actually, once things are properly split apart,
2759 the test goes away.) */
2760 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
2761 set_gdbarch_software_single_step (gdbarch
, rs6000_software_single_step
);
2768 rs6000_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2770 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2775 /* FIXME: Dump gdbarch_tdep. */
2778 static struct cmd_list_element
*info_powerpc_cmdlist
= NULL
;
2781 rs6000_info_powerpc_command (char *args
, int from_tty
)
2783 help_list (info_powerpc_cmdlist
, "info powerpc ", class_info
, gdb_stdout
);
2786 /* Initialization code. */
2788 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
2791 _initialize_rs6000_tdep (void)
2793 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
2794 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
2796 /* Add root prefix command for "info powerpc" commands */
2797 add_prefix_cmd ("powerpc", class_info
, rs6000_info_powerpc_command
,
2798 "Various POWERPC info specific commands.",
2799 &info_powerpc_cmdlist
, "info powerpc ", 0, &infolist
);