1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "libbfd.h" /* for bfd_default_set_arch_mach */
47 #include "coff/internal.h" /* for libcoff.h */
48 #include "libcoff.h" /* for xcoff_data */
49 #include "coff/xcoff.h"
54 #include "elf/ppc64.h"
56 #include "solib-svr4.h"
58 #include "ppc-ravenscar-thread.h"
62 #include "trad-frame.h"
63 #include "frame-unwind.h"
64 #include "frame-base.h"
66 #include "features/rs6000/powerpc-32.c"
67 #include "features/rs6000/powerpc-altivec32.c"
68 #include "features/rs6000/powerpc-vsx32.c"
69 #include "features/rs6000/powerpc-403.c"
70 #include "features/rs6000/powerpc-403gc.c"
71 #include "features/rs6000/powerpc-405.c"
72 #include "features/rs6000/powerpc-505.c"
73 #include "features/rs6000/powerpc-601.c"
74 #include "features/rs6000/powerpc-602.c"
75 #include "features/rs6000/powerpc-603.c"
76 #include "features/rs6000/powerpc-604.c"
77 #include "features/rs6000/powerpc-64.c"
78 #include "features/rs6000/powerpc-altivec64.c"
79 #include "features/rs6000/powerpc-vsx64.c"
80 #include "features/rs6000/powerpc-7400.c"
81 #include "features/rs6000/powerpc-750.c"
82 #include "features/rs6000/powerpc-860.c"
83 #include "features/rs6000/powerpc-e500.c"
84 #include "features/rs6000/rs6000.c"
86 /* Determine if regnum is an SPE pseudo-register. */
87 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
88 && (regnum) >= (tdep)->ppc_ev0_regnum \
89 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
91 /* Determine if regnum is a decimal float pseudo-register. */
92 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
93 && (regnum) >= (tdep)->ppc_dl0_regnum \
94 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
96 /* Determine if regnum is a POWER7 VSX register. */
97 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
98 && (regnum) >= (tdep)->ppc_vsr0_regnum \
99 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
101 /* Determine if regnum is a POWER7 Extended FP register. */
102 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
103 && (regnum) >= (tdep)->ppc_efpr0_regnum \
104 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
106 /* The list of available "set powerpc ..." and "show powerpc ..."
108 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
109 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
111 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
113 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
114 static const char *const powerpc_vector_strings
[] =
123 /* A variable that can be configured by the user. */
124 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
125 static const char *powerpc_vector_abi_string
= "auto";
127 /* To be used by skip_prologue. */
129 struct rs6000_framedata
131 int offset
; /* total size of frame --- the distance
132 by which we decrement sp to allocate
134 int saved_gpr
; /* smallest # of saved gpr */
135 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
136 int saved_fpr
; /* smallest # of saved fpr */
137 int saved_vr
; /* smallest # of saved vr */
138 int saved_ev
; /* smallest # of saved ev */
139 int alloca_reg
; /* alloca register number (frame ptr) */
140 char frameless
; /* true if frameless functions. */
141 char nosavedpc
; /* true if pc not saved. */
142 char used_bl
; /* true if link register clobbered */
143 int gpr_offset
; /* offset of saved gprs from prev sp */
144 int fpr_offset
; /* offset of saved fprs from prev sp */
145 int vr_offset
; /* offset of saved vrs from prev sp */
146 int ev_offset
; /* offset of saved evs from prev sp */
147 int lr_offset
; /* offset of saved lr */
148 int lr_register
; /* register of saved lr, if trustworthy */
149 int cr_offset
; /* offset of saved cr */
150 int vrsave_offset
; /* offset of saved vrsave register */
154 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
156 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
159 if (tdep
->ppc_vsr0_regnum
< 0)
162 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
163 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
166 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
168 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
170 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
171 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
174 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
178 /* Return true if REGNO is an SPE register, false otherwise. */
180 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
182 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
184 /* Is it a reference to EV0 -- EV31, and do we have those? */
185 if (IS_SPE_PSEUDOREG (tdep
, regno
))
188 /* Is it a reference to one of the raw upper GPR halves? */
189 if (tdep
->ppc_ev0_upper_regnum
>= 0
190 && tdep
->ppc_ev0_upper_regnum
<= regno
191 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
194 /* Is it a reference to the 64-bit accumulator, and do we have that? */
195 if (tdep
->ppc_acc_regnum
>= 0
196 && tdep
->ppc_acc_regnum
== regno
)
199 /* Is it a reference to the SPE floating-point status and control register,
200 and do we have that? */
201 if (tdep
->ppc_spefscr_regnum
>= 0
202 && tdep
->ppc_spefscr_regnum
== regno
)
209 /* Return non-zero if the architecture described by GDBARCH has
210 floating-point registers (f0 --- f31 and fpscr). */
212 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
214 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
216 return (tdep
->ppc_fp0_regnum
>= 0
217 && tdep
->ppc_fpscr_regnum
>= 0);
220 /* Return non-zero if the architecture described by GDBARCH has
221 VSX registers (vsr0 --- vsr63). */
223 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
225 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
227 return tdep
->ppc_vsr0_regnum
>= 0;
230 /* Return non-zero if the architecture described by GDBARCH has
231 Altivec registers (vr0 --- vr31, vrsave and vscr). */
233 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
235 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
237 return (tdep
->ppc_vr0_regnum
>= 0
238 && tdep
->ppc_vrsave_regnum
>= 0);
241 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
244 This is a helper function for init_sim_regno_table, constructing
245 the table mapping GDB register numbers to sim register numbers; we
246 initialize every element in that table to -1 before we start
249 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
251 /* Make sure we don't try to assign any given GDB register a sim
252 register number more than once. */
253 gdb_assert (table
[gdb_regno
] == -1);
254 table
[gdb_regno
] = sim_regno
;
258 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
259 numbers to simulator register numbers, based on the values placed
260 in the ARCH->tdep->ppc_foo_regnum members. */
262 init_sim_regno_table (struct gdbarch
*arch
)
264 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
265 int total_regs
= gdbarch_num_regs (arch
);
266 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
268 static const char *const segment_regs
[] = {
269 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
270 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
273 /* Presume that all registers not explicitly mentioned below are
274 unavailable from the sim. */
275 for (i
= 0; i
< total_regs
; i
++)
278 /* General-purpose registers. */
279 for (i
= 0; i
< ppc_num_gprs
; i
++)
280 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
282 /* Floating-point registers. */
283 if (tdep
->ppc_fp0_regnum
>= 0)
284 for (i
= 0; i
< ppc_num_fprs
; i
++)
285 set_sim_regno (sim_regno
,
286 tdep
->ppc_fp0_regnum
+ i
,
287 sim_ppc_f0_regnum
+ i
);
288 if (tdep
->ppc_fpscr_regnum
>= 0)
289 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
291 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
292 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
293 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
295 /* Segment registers. */
296 for (i
= 0; i
< ppc_num_srs
; i
++)
300 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
302 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
305 /* Altivec registers. */
306 if (tdep
->ppc_vr0_regnum
>= 0)
308 for (i
= 0; i
< ppc_num_vrs
; i
++)
309 set_sim_regno (sim_regno
,
310 tdep
->ppc_vr0_regnum
+ i
,
311 sim_ppc_vr0_regnum
+ i
);
313 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
314 we can treat this more like the other cases. */
315 set_sim_regno (sim_regno
,
316 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
317 sim_ppc_vscr_regnum
);
319 /* vsave is a special-purpose register, so the code below handles it. */
321 /* SPE APU (E500) registers. */
322 if (tdep
->ppc_ev0_upper_regnum
>= 0)
323 for (i
= 0; i
< ppc_num_gprs
; i
++)
324 set_sim_regno (sim_regno
,
325 tdep
->ppc_ev0_upper_regnum
+ i
,
326 sim_ppc_rh0_regnum
+ i
);
327 if (tdep
->ppc_acc_regnum
>= 0)
328 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
329 /* spefscr is a special-purpose register, so the code below handles it. */
332 /* Now handle all special-purpose registers. Verify that they
333 haven't mistakenly been assigned numbers by any of the above
335 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
337 const char *spr_name
= sim_spr_register_name (i
);
340 if (spr_name
!= NULL
)
341 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
344 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
348 /* Drop the initialized array into place. */
349 tdep
->sim_regno
= sim_regno
;
353 /* Given a GDB register number REG, return the corresponding SIM
356 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
358 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
361 if (tdep
->sim_regno
== NULL
)
362 init_sim_regno_table (gdbarch
);
365 && reg
<= gdbarch_num_regs (gdbarch
)
366 + gdbarch_num_pseudo_regs (gdbarch
));
367 sim_regno
= tdep
->sim_regno
[reg
];
372 return LEGACY_SIM_REGNO_IGNORE
;
377 /* Register set support functions. */
379 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
380 Write the register to REGCACHE. */
383 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
384 const gdb_byte
*regs
, size_t offset
, int regsize
)
386 if (regnum
!= -1 && offset
!= -1)
390 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
391 int gdb_regsize
= register_size (gdbarch
, regnum
);
392 if (gdb_regsize
< regsize
393 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
394 offset
+= regsize
- gdb_regsize
;
396 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
400 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
401 in a field REGSIZE wide. Zero pad as necessary. */
404 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
405 gdb_byte
*regs
, size_t offset
, int regsize
)
407 if (regnum
!= -1 && offset
!= -1)
411 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
412 int gdb_regsize
= register_size (gdbarch
, regnum
);
413 if (gdb_regsize
< regsize
)
415 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
417 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
418 offset
+= regsize
- gdb_regsize
;
421 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
422 regsize
- gdb_regsize
);
425 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
430 ppc_greg_offset (struct gdbarch
*gdbarch
,
431 struct gdbarch_tdep
*tdep
,
432 const struct ppc_reg_offsets
*offsets
,
436 *regsize
= offsets
->gpr_size
;
437 if (regnum
>= tdep
->ppc_gp0_regnum
438 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
439 return (offsets
->r0_offset
440 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
442 if (regnum
== gdbarch_pc_regnum (gdbarch
))
443 return offsets
->pc_offset
;
445 if (regnum
== tdep
->ppc_ps_regnum
)
446 return offsets
->ps_offset
;
448 if (regnum
== tdep
->ppc_lr_regnum
)
449 return offsets
->lr_offset
;
451 if (regnum
== tdep
->ppc_ctr_regnum
)
452 return offsets
->ctr_offset
;
454 *regsize
= offsets
->xr_size
;
455 if (regnum
== tdep
->ppc_cr_regnum
)
456 return offsets
->cr_offset
;
458 if (regnum
== tdep
->ppc_xer_regnum
)
459 return offsets
->xer_offset
;
461 if (regnum
== tdep
->ppc_mq_regnum
)
462 return offsets
->mq_offset
;
468 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
469 const struct ppc_reg_offsets
*offsets
,
472 if (regnum
>= tdep
->ppc_fp0_regnum
473 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
474 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
476 if (regnum
== tdep
->ppc_fpscr_regnum
)
477 return offsets
->fpscr_offset
;
483 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
484 const struct ppc_reg_offsets
*offsets
,
487 if (regnum
>= tdep
->ppc_vr0_regnum
488 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
489 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
491 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
492 return offsets
->vscr_offset
;
494 if (regnum
== tdep
->ppc_vrsave_regnum
)
495 return offsets
->vrsave_offset
;
500 /* Supply register REGNUM in the general-purpose register set REGSET
501 from the buffer specified by GREGS and LEN to register cache
502 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
505 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
506 int regnum
, const void *gregs
, size_t len
)
508 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
509 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
510 const struct ppc_reg_offsets
*offsets
511 = (const struct ppc_reg_offsets
*) regset
->regmap
;
518 int gpr_size
= offsets
->gpr_size
;
520 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
521 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
522 i
++, offset
+= gpr_size
)
523 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
526 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
527 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
528 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
529 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
530 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
531 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
532 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
533 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
535 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
537 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
538 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
540 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
541 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
546 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
547 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
550 /* Supply register REGNUM in the floating-point register set REGSET
551 from the buffer specified by FPREGS and LEN to register cache
552 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
555 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
556 int regnum
, const void *fpregs
, size_t len
)
558 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
559 struct gdbarch_tdep
*tdep
;
560 const struct ppc_reg_offsets
*offsets
;
563 if (!ppc_floating_point_unit_p (gdbarch
))
566 tdep
= gdbarch_tdep (gdbarch
);
567 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
572 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
573 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
575 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
577 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
578 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
579 offsets
->fpscr_size
);
583 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
584 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
585 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
588 /* Supply register REGNUM in the VSX register set REGSET
589 from the buffer specified by VSXREGS and LEN to register cache
590 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
593 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
594 int regnum
, const void *vsxregs
, size_t len
)
596 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
597 struct gdbarch_tdep
*tdep
;
599 if (!ppc_vsx_support_p (gdbarch
))
602 tdep
= gdbarch_tdep (gdbarch
);
608 for (i
= tdep
->ppc_vsr0_upper_regnum
;
609 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
611 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vsxregs
, 0, 8);
616 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vsxregs
, 0, 8);
619 /* Supply register REGNUM in the Altivec register set REGSET
620 from the buffer specified by VRREGS and LEN to register cache
621 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
624 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
625 int regnum
, const void *vrregs
, size_t len
)
627 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
628 struct gdbarch_tdep
*tdep
;
629 const struct ppc_reg_offsets
*offsets
;
632 if (!ppc_altivec_support_p (gdbarch
))
635 tdep
= gdbarch_tdep (gdbarch
);
636 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
641 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
642 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
644 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vrregs
, offset
, 16);
646 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
647 (const gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
649 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
650 (const gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
654 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
655 if (regnum
!= tdep
->ppc_vrsave_regnum
656 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
657 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vrregs
, offset
, 16);
659 ppc_supply_reg (regcache
, regnum
,
660 (const gdb_byte
*) vrregs
, offset
, 4);
663 /* Collect register REGNUM in the general-purpose register set
664 REGSET from register cache REGCACHE into the buffer specified by
665 GREGS and LEN. If REGNUM is -1, do this for all registers in
669 ppc_collect_gregset (const struct regset
*regset
,
670 const struct regcache
*regcache
,
671 int regnum
, void *gregs
, size_t len
)
673 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
674 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
675 const struct ppc_reg_offsets
*offsets
676 = (const struct ppc_reg_offsets
*) regset
->regmap
;
683 int gpr_size
= offsets
->gpr_size
;
685 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
686 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
687 i
++, offset
+= gpr_size
)
688 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
690 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
691 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
692 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
693 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
694 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
695 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
696 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
697 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
698 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
699 (gdb_byte
*) gregs
, offsets
->cr_offset
,
701 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
702 (gdb_byte
*) gregs
, offsets
->xer_offset
,
704 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
705 (gdb_byte
*) gregs
, offsets
->mq_offset
,
710 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
711 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
714 /* Collect register REGNUM in the floating-point register set
715 REGSET from register cache REGCACHE into the buffer specified by
716 FPREGS and LEN. If REGNUM is -1, do this for all registers in
720 ppc_collect_fpregset (const struct regset
*regset
,
721 const struct regcache
*regcache
,
722 int regnum
, void *fpregs
, size_t len
)
724 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
725 struct gdbarch_tdep
*tdep
;
726 const struct ppc_reg_offsets
*offsets
;
729 if (!ppc_floating_point_unit_p (gdbarch
))
732 tdep
= gdbarch_tdep (gdbarch
);
733 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
738 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
739 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
741 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
743 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
744 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
745 offsets
->fpscr_size
);
749 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
750 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
751 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
754 /* Collect register REGNUM in the VSX register set
755 REGSET from register cache REGCACHE into the buffer specified by
756 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
760 ppc_collect_vsxregset (const struct regset
*regset
,
761 const struct regcache
*regcache
,
762 int regnum
, void *vsxregs
, size_t len
)
764 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
765 struct gdbarch_tdep
*tdep
;
767 if (!ppc_vsx_support_p (gdbarch
))
770 tdep
= gdbarch_tdep (gdbarch
);
776 for (i
= tdep
->ppc_vsr0_upper_regnum
;
777 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
779 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vsxregs
, 0, 8);
784 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vsxregs
, 0, 8);
788 /* Collect register REGNUM in the Altivec register set
789 REGSET from register cache REGCACHE into the buffer specified by
790 VRREGS and LEN. If REGNUM is -1, do this for all registers in
794 ppc_collect_vrregset (const struct regset
*regset
,
795 const struct regcache
*regcache
,
796 int regnum
, void *vrregs
, size_t len
)
798 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
799 struct gdbarch_tdep
*tdep
;
800 const struct ppc_reg_offsets
*offsets
;
803 if (!ppc_altivec_support_p (gdbarch
))
806 tdep
= gdbarch_tdep (gdbarch
);
807 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
812 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
813 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
815 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vrregs
, offset
, 16);
817 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
818 (gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
820 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
821 (gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
825 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
826 if (regnum
!= tdep
->ppc_vrsave_regnum
827 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
828 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vrregs
, offset
, 16);
830 ppc_collect_reg (regcache
, regnum
,
831 (gdb_byte
*) vrregs
, offset
, 4);
836 insn_changes_sp_or_jumps (unsigned long insn
)
838 int opcode
= (insn
>> 26) & 0x03f;
839 int sd
= (insn
>> 21) & 0x01f;
840 int a
= (insn
>> 16) & 0x01f;
841 int subcode
= (insn
>> 1) & 0x3ff;
843 /* Changes the stack pointer. */
845 /* NOTE: There are many ways to change the value of a given register.
846 The ways below are those used when the register is R1, the SP,
847 in a funtion's epilogue. */
849 if (opcode
== 31 && subcode
== 444 && a
== 1)
850 return 1; /* mr R1,Rn */
851 if (opcode
== 14 && sd
== 1)
852 return 1; /* addi R1,Rn,simm */
853 if (opcode
== 58 && sd
== 1)
854 return 1; /* ld R1,ds(Rn) */
856 /* Transfers control. */
862 if (opcode
== 19 && subcode
== 16)
864 if (opcode
== 19 && subcode
== 528)
865 return 1; /* bcctr */
870 /* Return true if we are in the function's epilogue, i.e. after the
871 instruction that destroyed the function's stack frame.
873 1) scan forward from the point of execution:
874 a) If you find an instruction that modifies the stack pointer
875 or transfers control (except a return), execution is not in
877 b) Stop scanning if you find a return instruction or reach the
878 end of the function or reach the hard limit for the size of
880 2) scan backward from the point of execution:
881 a) If you find an instruction that modifies the stack pointer,
882 execution *is* in an epilogue, return.
883 b) Stop scanning if you reach an instruction that transfers
884 control or the beginning of the function or reach the hard
885 limit for the size of an epilogue. */
888 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
889 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
891 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
892 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
893 bfd_byte insn_buf
[PPC_INSN_SIZE
];
894 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
897 /* Find the search limits based on function boundaries and hard limit. */
899 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
902 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
903 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
905 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
906 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
908 /* Scan forward until next 'blr'. */
910 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
912 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
914 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
915 if (insn
== 0x4e800020)
917 /* Assume a bctr is a tail call unless it points strictly within
919 if (insn
== 0x4e800420)
921 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
922 tdep
->ppc_ctr_regnum
);
923 if (ctr
> func_start
&& ctr
< func_end
)
928 if (insn_changes_sp_or_jumps (insn
))
932 /* Scan backward until adjustment to stack pointer (R1). */
934 for (scan_pc
= pc
- PPC_INSN_SIZE
;
935 scan_pc
>= epilogue_start
;
936 scan_pc
-= PPC_INSN_SIZE
)
938 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
940 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
941 if (insn_changes_sp_or_jumps (insn
))
948 /* Implement the stack_frame_destroyed_p gdbarch method. */
951 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
953 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
957 /* Get the ith function argument for the current function. */
959 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
962 return get_frame_register_unsigned (frame
, 3 + argi
);
965 /* Sequence of bytes for breakpoint instruction. */
967 static const unsigned char *
968 rs6000_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
971 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
972 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
974 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
975 return big_breakpoint
;
977 return little_breakpoint
;
980 /* Instruction masks for displaced stepping. */
981 #define BRANCH_MASK 0xfc000000
982 #define BP_MASK 0xFC0007FE
983 #define B_INSN 0x48000000
984 #define BC_INSN 0x40000000
985 #define BXL_INSN 0x4c000000
986 #define BP_INSN 0x7C000008
988 /* Instruction masks used during single-stepping of atomic
990 #define LWARX_MASK 0xfc0007fe
991 #define LWARX_INSTRUCTION 0x7c000028
992 #define LDARX_INSTRUCTION 0x7c0000A8
993 #define STWCX_MASK 0xfc0007ff
994 #define STWCX_INSTRUCTION 0x7c00012d
995 #define STDCX_INSTRUCTION 0x7c0001ad
997 /* We can't displaced step atomic sequences. Otherwise this is just
998 like simple_displaced_step_copy_insn. */
1000 static struct displaced_step_closure
*
1001 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1002 CORE_ADDR from
, CORE_ADDR to
,
1003 struct regcache
*regs
)
1005 size_t len
= gdbarch_max_insn_length (gdbarch
);
1006 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
);
1007 struct cleanup
*old_chain
= make_cleanup (xfree
, buf
);
1008 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1011 read_memory (from
, buf
, len
);
1013 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
1015 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1016 if ((insn
& LWARX_MASK
) == LWARX_INSTRUCTION
1017 || (insn
& LWARX_MASK
) == LDARX_INSTRUCTION
)
1019 if (debug_displaced
)
1021 fprintf_unfiltered (gdb_stdlog
,
1022 "displaced: can't displaced step "
1023 "atomic sequence at %s\n",
1024 paddress (gdbarch
, from
));
1026 do_cleanups (old_chain
);
1030 write_memory (to
, buf
, len
);
1032 if (debug_displaced
)
1034 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1035 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1036 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1039 discard_cleanups (old_chain
);
1040 return (struct displaced_step_closure
*) buf
;
1043 /* Fix up the state of registers and memory after having single-stepped
1044 a displaced instruction. */
1046 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
1047 struct displaced_step_closure
*closure
,
1048 CORE_ADDR from
, CORE_ADDR to
,
1049 struct regcache
*regs
)
1051 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1052 /* Our closure is a copy of the instruction. */
1053 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
1054 PPC_INSN_SIZE
, byte_order
);
1055 ULONGEST opcode
= 0;
1056 /* Offset for non PC-relative instructions. */
1057 LONGEST offset
= PPC_INSN_SIZE
;
1059 opcode
= insn
& BRANCH_MASK
;
1061 if (debug_displaced
)
1062 fprintf_unfiltered (gdb_stdlog
,
1063 "displaced: (ppc) fixup (%s, %s)\n",
1064 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1067 /* Handle PC-relative branch instructions. */
1068 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1070 ULONGEST current_pc
;
1072 /* Read the current PC value after the instruction has been executed
1073 in a displaced location. Calculate the offset to be applied to the
1074 original PC value before the displaced stepping. */
1075 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1077 offset
= current_pc
- to
;
1079 if (opcode
!= BXL_INSN
)
1081 /* Check for AA bit indicating whether this is an absolute
1082 addressing or PC-relative (1: absolute, 0: relative). */
1085 /* PC-relative addressing is being used in the branch. */
1086 if (debug_displaced
)
1089 "displaced: (ppc) branch instruction: %s\n"
1090 "displaced: (ppc) adjusted PC from %s to %s\n",
1091 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1092 paddress (gdbarch
, from
+ offset
));
1094 regcache_cooked_write_unsigned (regs
,
1095 gdbarch_pc_regnum (gdbarch
),
1101 /* If we're here, it means we have a branch to LR or CTR. If the
1102 branch was taken, the offset is probably greater than 4 (the next
1103 instruction), so it's safe to assume that an offset of 4 means we
1104 did not take the branch. */
1105 if (offset
== PPC_INSN_SIZE
)
1106 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1107 from
+ PPC_INSN_SIZE
);
1110 /* Check for LK bit indicating whether we should set the link
1111 register to point to the next instruction
1112 (1: Set, 0: Don't set). */
1115 /* Link register needs to be set to the next instruction's PC. */
1116 regcache_cooked_write_unsigned (regs
,
1117 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1118 from
+ PPC_INSN_SIZE
);
1119 if (debug_displaced
)
1120 fprintf_unfiltered (gdb_stdlog
,
1121 "displaced: (ppc) adjusted LR to %s\n",
1122 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1126 /* Check for breakpoints in the inferior. If we've found one, place the PC
1127 right at the breakpoint instruction. */
1128 else if ((insn
& BP_MASK
) == BP_INSN
)
1129 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1131 /* Handle any other instructions that do not fit in the categories above. */
1132 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1136 /* Always use hardware single-stepping to execute the
1137 displaced instruction. */
1139 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1140 struct displaced_step_closure
*closure
)
1145 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1146 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1147 is found, attempt to step through it. A breakpoint is placed at the end of
1151 ppc_deal_with_atomic_sequence (struct frame_info
*frame
)
1153 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1154 struct address_space
*aspace
= get_frame_address_space (frame
);
1155 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1156 CORE_ADDR pc
= get_frame_pc (frame
);
1157 CORE_ADDR breaks
[2] = {-1, -1};
1159 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1160 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1163 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1164 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1165 int opcode
; /* Branch instruction's OPcode. */
1166 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1168 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1169 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
1170 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
1173 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1175 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1177 loc
+= PPC_INSN_SIZE
;
1178 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1180 /* Assume that there is at most one conditional branch in the atomic
1181 sequence. If a conditional branch is found, put a breakpoint in
1182 its destination address. */
1183 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1185 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1186 int absolute
= insn
& 2;
1188 if (bc_insn_count
>= 1)
1189 return 0; /* More than one conditional branch found, fallback
1190 to the standard single-step code. */
1193 breaks
[1] = immediate
;
1195 breaks
[1] = loc
+ immediate
;
1201 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
1202 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
1206 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1207 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
1208 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
1212 loc
+= PPC_INSN_SIZE
;
1213 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1215 /* Insert a breakpoint right after the end of the atomic sequence. */
1218 /* Check for duplicated breakpoints. Check also for a breakpoint
1219 placed (branch instruction's destination) anywhere in sequence. */
1221 && (breaks
[1] == breaks
[0]
1222 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1223 last_breakpoint
= 0;
1225 /* Effectively inserts the breakpoints. */
1226 for (index
= 0; index
<= last_breakpoint
; index
++)
1227 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
1233 #define SIGNED_SHORT(x) \
1234 ((sizeof (short) == 2) \
1235 ? ((int)(short)(x)) \
1236 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1238 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1240 /* Limit the number of skipped non-prologue instructions, as the examining
1241 of the prologue is expensive. */
1242 static int max_skip_non_prologue_insns
= 10;
1244 /* Return nonzero if the given instruction OP can be part of the prologue
1245 of a function and saves a parameter on the stack. FRAMEP should be
1246 set if one of the previous instructions in the function has set the
1250 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1252 /* Move parameters from argument registers to temporary register. */
1253 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1255 /* Rx must be scratch register r0. */
1256 const int rx_regno
= (op
>> 16) & 31;
1257 /* Ry: Only r3 - r10 are used for parameter passing. */
1258 const int ry_regno
= GET_SRC_REG (op
);
1260 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1262 *r0_contains_arg
= 1;
1269 /* Save a General Purpose Register on stack. */
1271 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1272 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1274 /* Rx: Only r3 - r10 are used for parameter passing. */
1275 const int rx_regno
= GET_SRC_REG (op
);
1277 return (rx_regno
>= 3 && rx_regno
<= 10);
1280 /* Save a General Purpose Register on stack via the Frame Pointer. */
1283 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1284 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1285 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1287 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1288 However, the compiler sometimes uses r0 to hold an argument. */
1289 const int rx_regno
= GET_SRC_REG (op
);
1291 return ((rx_regno
>= 3 && rx_regno
<= 10)
1292 || (rx_regno
== 0 && *r0_contains_arg
));
1295 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1297 /* Only f2 - f8 are used for parameter passing. */
1298 const int src_regno
= GET_SRC_REG (op
);
1300 return (src_regno
>= 2 && src_regno
<= 8);
1303 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1305 /* Only f2 - f8 are used for parameter passing. */
1306 const int src_regno
= GET_SRC_REG (op
);
1308 return (src_regno
>= 2 && src_regno
<= 8);
1311 /* Not an insn that saves a parameter on stack. */
1315 /* Assuming that INSN is a "bl" instruction located at PC, return
1316 nonzero if the destination of the branch is a "blrl" instruction.
1318 This sequence is sometimes found in certain function prologues.
1319 It allows the function to load the LR register with a value that
1320 they can use to access PIC data using PC-relative offsets. */
1323 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1330 absolute
= (int) ((insn
>> 1) & 1);
1331 immediate
= ((insn
& ~3) << 6) >> 6;
1335 dest
= pc
+ immediate
;
1337 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1338 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1344 /* Masks for decoding a branch-and-link (bl) instruction.
1346 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1347 The former is anded with the opcode in question; if the result of
1348 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1349 question is a ``bl'' instruction.
1351 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1352 the branch displacement. */
1354 #define BL_MASK 0xfc000001
1355 #define BL_INSTRUCTION 0x48000001
1356 #define BL_DISPLACEMENT_MASK 0x03fffffc
1358 static unsigned long
1359 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1361 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1365 /* Fetch the instruction and convert it to an integer. */
1366 if (target_read_memory (pc
, buf
, 4))
1368 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1373 /* GCC generates several well-known sequences of instructions at the begining
1374 of each function prologue when compiling with -fstack-check. If one of
1375 such sequences starts at START_PC, then return the address of the
1376 instruction immediately past this sequence. Otherwise, return START_PC. */
1379 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1381 CORE_ADDR pc
= start_pc
;
1382 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1384 /* First possible sequence: A small number of probes.
1385 stw 0, -<some immediate>(1)
1386 [repeat this instruction any (small) number of times]. */
1388 if ((op
& 0xffff0000) == 0x90010000)
1390 while ((op
& 0xffff0000) == 0x90010000)
1393 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1398 /* Second sequence: A probing loop.
1399 addi 12,1,-<some immediate>
1400 lis 0,-<some immediate>
1401 [possibly ori 0,0,<some immediate>]
1405 addi 12,12,-<some immediate>
1408 [possibly one last probe: stw 0,<some immediate>(12)]. */
1412 /* addi 12,1,-<some immediate> */
1413 if ((op
& 0xffff0000) != 0x39810000)
1416 /* lis 0,-<some immediate> */
1418 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1419 if ((op
& 0xffff0000) != 0x3c000000)
1423 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1424 /* [possibly ori 0,0,<some immediate>] */
1425 if ((op
& 0xffff0000) == 0x60000000)
1428 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1431 if (op
!= 0x7c0c0214)
1436 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1437 if (op
!= 0x7c0c0000)
1442 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1443 if ((op
& 0xff9f0001) != 0x41820000)
1446 /* addi 12,12,-<some immediate> */
1448 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1449 if ((op
& 0xffff0000) != 0x398c0000)
1454 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1455 if (op
!= 0x900c0000)
1460 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1461 if ((op
& 0xfc000001) != 0x48000000)
1464 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1466 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1467 if ((op
& 0xffff0000) == 0x900c0000)
1470 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1473 /* We found a valid stack-check sequence, return the new PC. */
1477 /* Third sequence: No probe; instead, a comparizon between the stack size
1478 limit (saved in a run-time global variable) and the current stack
1481 addi 0,1,-<some immediate>
1482 lis 12,__gnat_stack_limit@ha
1483 lwz 12,__gnat_stack_limit@l(12)
1486 or, with a small variant in the case of a bigger stack frame:
1487 addis 0,1,<some immediate>
1488 addic 0,0,-<some immediate>
1489 lis 12,__gnat_stack_limit@ha
1490 lwz 12,__gnat_stack_limit@l(12)
1495 /* addi 0,1,-<some immediate> */
1496 if ((op
& 0xffff0000) != 0x38010000)
1498 /* small stack frame variant not recognized; try the
1499 big stack frame variant: */
1501 /* addis 0,1,<some immediate> */
1502 if ((op
& 0xffff0000) != 0x3c010000)
1505 /* addic 0,0,-<some immediate> */
1507 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1508 if ((op
& 0xffff0000) != 0x30000000)
1512 /* lis 12,<some immediate> */
1514 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1515 if ((op
& 0xffff0000) != 0x3d800000)
1518 /* lwz 12,<some immediate>(12) */
1520 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1521 if ((op
& 0xffff0000) != 0x818c0000)
1526 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1527 if ((op
& 0xfffffffe) != 0x7c406008)
1530 /* We found a valid stack-check sequence, return the new PC. */
1534 /* No stack check code in our prologue, return the start_pc. */
1538 /* return pc value after skipping a function prologue and also return
1539 information about a function frame.
1541 in struct rs6000_framedata fdata:
1542 - frameless is TRUE, if function does not have a frame.
1543 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1544 - offset is the initial size of this stack frame --- the amount by
1545 which we decrement the sp to allocate the frame.
1546 - saved_gpr is the number of the first saved gpr.
1547 - saved_fpr is the number of the first saved fpr.
1548 - saved_vr is the number of the first saved vr.
1549 - saved_ev is the number of the first saved ev.
1550 - alloca_reg is the number of the register used for alloca() handling.
1552 - gpr_offset is the offset of the first saved gpr from the previous frame.
1553 - fpr_offset is the offset of the first saved fpr from the previous frame.
1554 - vr_offset is the offset of the first saved vr from the previous frame.
1555 - ev_offset is the offset of the first saved ev from the previous frame.
1556 - lr_offset is the offset of the saved lr
1557 - cr_offset is the offset of the saved cr
1558 - vrsave_offset is the offset of the saved vrsave register. */
1561 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1562 struct rs6000_framedata
*fdata
)
1564 CORE_ADDR orig_pc
= pc
;
1565 CORE_ADDR last_prologue_pc
= pc
;
1566 CORE_ADDR li_found_pc
= 0;
1570 long vr_saved_offset
= 0;
1576 int vrsave_reg
= -1;
1579 int minimal_toc_loaded
= 0;
1580 int prev_insn_was_prologue_insn
= 1;
1581 int num_skip_non_prologue_insns
= 0;
1582 int r0_contains_arg
= 0;
1583 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1584 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1585 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1587 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1588 fdata
->saved_gpr
= -1;
1589 fdata
->saved_fpr
= -1;
1590 fdata
->saved_vr
= -1;
1591 fdata
->saved_ev
= -1;
1592 fdata
->alloca_reg
= -1;
1593 fdata
->frameless
= 1;
1594 fdata
->nosavedpc
= 1;
1595 fdata
->lr_register
= -1;
1597 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1603 /* Sometimes it isn't clear if an instruction is a prologue
1604 instruction or not. When we encounter one of these ambiguous
1605 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1606 Otherwise, we'll assume that it really is a prologue instruction. */
1607 if (prev_insn_was_prologue_insn
)
1608 last_prologue_pc
= pc
;
1610 /* Stop scanning if we've hit the limit. */
1614 prev_insn_was_prologue_insn
= 1;
1616 /* Fetch the instruction and convert it to an integer. */
1617 if (target_read_memory (pc
, buf
, 4))
1619 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1621 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1623 /* Since shared library / PIC code, which needs to get its
1624 address at runtime, can appear to save more than one link
1638 remember just the first one, but skip over additional
1641 lr_reg
= (op
& 0x03e00000) >> 21;
1643 r0_contains_arg
= 0;
1646 else if ((op
& 0xfc1fffff) == 0x7c000026)
1648 cr_reg
= (op
& 0x03e00000);
1650 r0_contains_arg
= 0;
1654 else if ((op
& 0xfc1f0000) == 0xd8010000)
1655 { /* stfd Rx,NUM(r1) */
1656 reg
= GET_SRC_REG (op
);
1657 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1659 fdata
->saved_fpr
= reg
;
1660 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1665 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1666 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1667 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1668 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1671 reg
= GET_SRC_REG (op
);
1672 if ((op
& 0xfc1f0000) == 0xbc010000)
1673 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1675 fdata
->gpr_mask
|= 1U << reg
;
1676 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1678 fdata
->saved_gpr
= reg
;
1679 if ((op
& 0xfc1f0003) == 0xf8010000)
1681 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1686 else if ((op
& 0xffff0000) == 0x3c4c0000
1687 || (op
& 0xffff0000) == 0x3c400000
1688 || (op
& 0xffff0000) == 0x38420000)
1690 /* . 0: addis 2,12,.TOC.-0b@ha
1691 . addi 2,2,.TOC.-0b@l
1695 used by ELFv2 global entry points to set up r2. */
1698 else if (op
== 0x60000000)
1701 /* Allow nops in the prologue, but do not consider them to
1702 be part of the prologue unless followed by other prologue
1704 prev_insn_was_prologue_insn
= 0;
1708 else if ((op
& 0xffff0000) == 0x3c000000)
1709 { /* addis 0,0,NUM, used for >= 32k frames */
1710 fdata
->offset
= (op
& 0x0000ffff) << 16;
1711 fdata
->frameless
= 0;
1712 r0_contains_arg
= 0;
1716 else if ((op
& 0xffff0000) == 0x60000000)
1717 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1718 fdata
->offset
|= (op
& 0x0000ffff);
1719 fdata
->frameless
= 0;
1720 r0_contains_arg
= 0;
1724 else if (lr_reg
>= 0 &&
1725 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1726 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1727 /* stw Rx, NUM(r1) */
1728 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1729 /* stwu Rx, NUM(r1) */
1730 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1731 { /* where Rx == lr */
1732 fdata
->lr_offset
= offset
;
1733 fdata
->nosavedpc
= 0;
1734 /* Invalidate lr_reg, but don't set it to -1.
1735 That would mean that it had never been set. */
1737 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1738 (op
& 0xfc000000) == 0x90000000) /* stw */
1740 /* Does not update r1, so add displacement to lr_offset. */
1741 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1746 else if (cr_reg
>= 0 &&
1747 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1748 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1749 /* stw Rx, NUM(r1) */
1750 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1751 /* stwu Rx, NUM(r1) */
1752 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1753 { /* where Rx == cr */
1754 fdata
->cr_offset
= offset
;
1755 /* Invalidate cr_reg, but don't set it to -1.
1756 That would mean that it had never been set. */
1758 if ((op
& 0xfc000003) == 0xf8000000 ||
1759 (op
& 0xfc000000) == 0x90000000)
1761 /* Does not update r1, so add displacement to cr_offset. */
1762 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1767 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1769 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1770 prediction bits. If the LR has already been saved, we can
1774 else if (op
== 0x48000005)
1781 else if (op
== 0x48000004)
1786 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1787 in V.4 -mminimal-toc */
1788 (op
& 0xffff0000) == 0x3bde0000)
1789 { /* addi 30,30,foo@l */
1793 else if ((op
& 0xfc000001) == 0x48000001)
1797 fdata
->frameless
= 0;
1799 /* If the return address has already been saved, we can skip
1800 calls to blrl (for PIC). */
1801 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1807 /* Don't skip over the subroutine call if it is not within
1808 the first three instructions of the prologue and either
1809 we have no line table information or the line info tells
1810 us that the subroutine call is not part of the line
1811 associated with the prologue. */
1812 if ((pc
- orig_pc
) > 8)
1814 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1815 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1817 if ((prologue_sal
.line
== 0)
1818 || (prologue_sal
.line
!= this_sal
.line
))
1822 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1824 /* At this point, make sure this is not a trampoline
1825 function (a function that simply calls another functions,
1826 and nothing else). If the next is not a nop, this branch
1827 was part of the function prologue. */
1829 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1830 break; /* Don't skip over
1836 /* update stack pointer */
1837 else if ((op
& 0xfc1f0000) == 0x94010000)
1838 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1839 fdata
->frameless
= 0;
1840 fdata
->offset
= SIGNED_SHORT (op
);
1841 offset
= fdata
->offset
;
1844 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1845 { /* stwux rX,r1,rY */
1846 /* No way to figure out what r1 is going to be. */
1847 fdata
->frameless
= 0;
1848 offset
= fdata
->offset
;
1851 else if ((op
& 0xfc1f0003) == 0xf8010001)
1852 { /* stdu rX,NUM(r1) */
1853 fdata
->frameless
= 0;
1854 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1855 offset
= fdata
->offset
;
1858 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1859 { /* stdux rX,r1,rY */
1860 /* No way to figure out what r1 is going to be. */
1861 fdata
->frameless
= 0;
1862 offset
= fdata
->offset
;
1865 else if ((op
& 0xffff0000) == 0x38210000)
1866 { /* addi r1,r1,SIMM */
1867 fdata
->frameless
= 0;
1868 fdata
->offset
+= SIGNED_SHORT (op
);
1869 offset
= fdata
->offset
;
1872 /* Load up minimal toc pointer. Do not treat an epilogue restore
1873 of r31 as a minimal TOC load. */
1874 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1875 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1877 && !minimal_toc_loaded
)
1879 minimal_toc_loaded
= 1;
1882 /* move parameters from argument registers to local variable
1885 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1886 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1887 (((op
>> 21) & 31) <= 10) &&
1888 ((long) ((op
>> 16) & 31)
1889 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1893 /* store parameters in stack */
1895 /* Move parameters from argument registers to temporary register. */
1896 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1900 /* Set up frame pointer */
1902 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1904 fdata
->frameless
= 0;
1906 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1909 /* Another way to set up the frame pointer. */
1911 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1912 || op
== 0x7c3f0b78)
1914 fdata
->frameless
= 0;
1916 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1919 /* Another way to set up the frame pointer. */
1921 else if ((op
& 0xfc1fffff) == 0x38010000)
1922 { /* addi rX, r1, 0x0 */
1923 fdata
->frameless
= 0;
1925 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1926 + ((op
& ~0x38010000) >> 21));
1929 /* AltiVec related instructions. */
1930 /* Store the vrsave register (spr 256) in another register for
1931 later manipulation, or load a register into the vrsave
1932 register. 2 instructions are used: mfvrsave and
1933 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1934 and mtspr SPR256, Rn. */
1935 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1936 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1937 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1939 vrsave_reg
= GET_SRC_REG (op
);
1942 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1946 /* Store the register where vrsave was saved to onto the stack:
1947 rS is the register where vrsave was stored in a previous
1949 /* 100100 sssss 00001 dddddddd dddddddd */
1950 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1952 if (vrsave_reg
== GET_SRC_REG (op
))
1954 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1959 /* Compute the new value of vrsave, by modifying the register
1960 where vrsave was saved to. */
1961 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1962 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1966 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1967 in a pair of insns to save the vector registers on the
1969 /* 001110 00000 00000 iiii iiii iiii iiii */
1970 /* 001110 01110 00000 iiii iiii iiii iiii */
1971 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1972 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1974 if ((op
& 0xffff0000) == 0x38000000)
1975 r0_contains_arg
= 0;
1977 vr_saved_offset
= SIGNED_SHORT (op
);
1979 /* This insn by itself is not part of the prologue, unless
1980 if part of the pair of insns mentioned above. So do not
1981 record this insn as part of the prologue yet. */
1982 prev_insn_was_prologue_insn
= 0;
1984 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1985 /* 011111 sssss 11111 00000 00111001110 */
1986 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1988 if (pc
== (li_found_pc
+ 4))
1990 vr_reg
= GET_SRC_REG (op
);
1991 /* If this is the first vector reg to be saved, or if
1992 it has a lower number than others previously seen,
1993 reupdate the frame info. */
1994 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1996 fdata
->saved_vr
= vr_reg
;
1997 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1999 vr_saved_offset
= -1;
2004 /* End AltiVec related instructions. */
2006 /* Start BookE related instructions. */
2007 /* Store gen register S at (r31+uimm).
2008 Any register less than r13 is volatile, so we don't care. */
2009 /* 000100 sssss 11111 iiiii 01100100001 */
2010 else if (arch_info
->mach
== bfd_mach_ppc_e500
2011 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2013 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2016 ev_reg
= GET_SRC_REG (op
);
2017 imm
= (op
>> 11) & 0x1f;
2018 ev_offset
= imm
* 8;
2019 /* If this is the first vector reg to be saved, or if
2020 it has a lower number than others previously seen,
2021 reupdate the frame info. */
2022 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2024 fdata
->saved_ev
= ev_reg
;
2025 fdata
->ev_offset
= ev_offset
+ offset
;
2030 /* Store gen register rS at (r1+rB). */
2031 /* 000100 sssss 00001 bbbbb 01100100000 */
2032 else if (arch_info
->mach
== bfd_mach_ppc_e500
2033 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2035 if (pc
== (li_found_pc
+ 4))
2037 ev_reg
= GET_SRC_REG (op
);
2038 /* If this is the first vector reg to be saved, or if
2039 it has a lower number than others previously seen,
2040 reupdate the frame info. */
2041 /* We know the contents of rB from the previous instruction. */
2042 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2044 fdata
->saved_ev
= ev_reg
;
2045 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2047 vr_saved_offset
= -1;
2053 /* Store gen register r31 at (rA+uimm). */
2054 /* 000100 11111 aaaaa iiiii 01100100001 */
2055 else if (arch_info
->mach
== bfd_mach_ppc_e500
2056 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2058 /* Wwe know that the source register is 31 already, but
2059 it can't hurt to compute it. */
2060 ev_reg
= GET_SRC_REG (op
);
2061 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2062 /* If this is the first vector reg to be saved, or if
2063 it has a lower number than others previously seen,
2064 reupdate the frame info. */
2065 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2067 fdata
->saved_ev
= ev_reg
;
2068 fdata
->ev_offset
= ev_offset
+ offset
;
2073 /* Store gen register S at (r31+r0).
2074 Store param on stack when offset from SP bigger than 4 bytes. */
2075 /* 000100 sssss 11111 00000 01100100000 */
2076 else if (arch_info
->mach
== bfd_mach_ppc_e500
2077 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2079 if (pc
== (li_found_pc
+ 4))
2081 if ((op
& 0x03e00000) >= 0x01a00000)
2083 ev_reg
= GET_SRC_REG (op
);
2084 /* If this is the first vector reg to be saved, or if
2085 it has a lower number than others previously seen,
2086 reupdate the frame info. */
2087 /* We know the contents of r0 from the previous
2089 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2091 fdata
->saved_ev
= ev_reg
;
2092 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2096 vr_saved_offset
= -1;
2101 /* End BookE related instructions. */
2105 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2107 /* Not a recognized prologue instruction.
2108 Handle optimizer code motions into the prologue by continuing
2109 the search if we have no valid frame yet or if the return
2110 address is not yet saved in the frame. Also skip instructions
2111 if some of the GPRs expected to be saved are not yet saved. */
2112 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2113 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2116 if (op
== 0x4e800020 /* blr */
2117 || op
== 0x4e800420) /* bctr */
2118 /* Do not scan past epilogue in frameless functions or
2121 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2122 /* Never skip branches. */
2125 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2126 /* Do not scan too many insns, scanning insns is expensive with
2130 /* Continue scanning. */
2131 prev_insn_was_prologue_insn
= 0;
2137 /* I have problems with skipping over __main() that I need to address
2138 * sometime. Previously, I used to use misc_function_vector which
2139 * didn't work as well as I wanted to be. -MGO */
2141 /* If the first thing after skipping a prolog is a branch to a function,
2142 this might be a call to an initializer in main(), introduced by gcc2.
2143 We'd like to skip over it as well. Fortunately, xlc does some extra
2144 work before calling a function right after a prologue, thus we can
2145 single out such gcc2 behaviour. */
2148 if ((op
& 0xfc000001) == 0x48000001)
2149 { /* bl foo, an initializer function? */
2150 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2152 if (op
== 0x4def7b82)
2153 { /* cror 0xf, 0xf, 0xf (nop) */
2155 /* Check and see if we are in main. If so, skip over this
2156 initializer function as well. */
2158 tmp
= find_pc_misc_function (pc
);
2160 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2166 if (pc
== lim_pc
&& lr_reg
>= 0)
2167 fdata
->lr_register
= lr_reg
;
2169 fdata
->offset
= -fdata
->offset
;
2170 return last_prologue_pc
;
2174 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2176 struct rs6000_framedata frame
;
2177 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2179 /* See if we can determine the end of the prologue via the symbol table.
2180 If so, then return either PC, or the PC after the prologue, whichever
2182 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2184 CORE_ADDR post_prologue_pc
2185 = skip_prologue_using_sal (gdbarch
, func_addr
);
2186 if (post_prologue_pc
!= 0)
2187 return max (pc
, post_prologue_pc
);
2190 /* Can't determine prologue from the symbol table, need to examine
2193 /* Find an upper limit on the function prologue using the debug
2194 information. If the debug information could not be used to provide
2195 that bound, then use an arbitrary large number as the upper bound. */
2196 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2198 limit_pc
= pc
+ 100; /* Magic. */
2200 /* Do not allow limit_pc to be past the function end, if we know
2201 where that end is... */
2202 if (func_end_addr
&& limit_pc
> func_end_addr
)
2203 limit_pc
= func_end_addr
;
2205 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2209 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2210 in the prologue of main().
2212 The function below examines the code pointed at by PC and checks to
2213 see if it corresponds to a call to __eabi. If so, it returns the
2214 address of the instruction following that call. Otherwise, it simply
2218 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2220 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2224 if (target_read_memory (pc
, buf
, 4))
2226 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2228 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2230 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2231 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2232 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2234 /* We check for ___eabi (three leading underscores) in addition
2235 to __eabi in case the GCC option "-fleading-underscore" was
2236 used to compile the program. */
2237 if (s
.minsym
!= NULL
2238 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2239 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2240 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2246 /* All the ABI's require 16 byte alignment. */
2248 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2250 return (addr
& -16);
2253 /* Return whether handle_inferior_event() should proceed through code
2254 starting at PC in function NAME when stepping.
2256 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2257 handle memory references that are too distant to fit in instructions
2258 generated by the compiler. For example, if 'foo' in the following
2263 is greater than 32767, the linker might replace the lwz with a branch to
2264 somewhere in @FIX1 that does the load in 2 instructions and then branches
2265 back to where execution should continue.
2267 GDB should silently step over @FIX code, just like AIX dbx does.
2268 Unfortunately, the linker uses the "b" instruction for the
2269 branches, meaning that the link register doesn't get set.
2270 Therefore, GDB's usual step_over_function () mechanism won't work.
2272 Instead, use the gdbarch_skip_trampoline_code and
2273 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2277 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2278 CORE_ADDR pc
, const char *name
)
2280 return name
&& startswith (name
, "@FIX");
2283 /* Skip code that the user doesn't want to see when stepping:
2285 1. Indirect function calls use a piece of trampoline code to do context
2286 switching, i.e. to set the new TOC table. Skip such code if we are on
2287 its first instruction (as when we have single-stepped to here).
2289 2. Skip shared library trampoline code (which is different from
2290 indirect function call trampolines).
2292 3. Skip bigtoc fixup code.
2294 Result is desired PC to step until, or NULL if we are not in
2295 code that should be skipped. */
2298 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2300 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2301 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2302 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2303 unsigned int ii
, op
;
2305 CORE_ADDR solib_target_pc
;
2306 struct bound_minimal_symbol msymbol
;
2308 static unsigned trampoline_code
[] =
2310 0x800b0000, /* l r0,0x0(r11) */
2311 0x90410014, /* st r2,0x14(r1) */
2312 0x7c0903a6, /* mtctr r0 */
2313 0x804b0004, /* l r2,0x4(r11) */
2314 0x816b0008, /* l r11,0x8(r11) */
2315 0x4e800420, /* bctr */
2316 0x4e800020, /* br */
2320 /* Check for bigtoc fixup code. */
2321 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2323 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2324 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2326 /* Double-check that the third instruction from PC is relative "b". */
2327 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2328 if ((op
& 0xfc000003) == 0x48000000)
2330 /* Extract bits 6-29 as a signed 24-bit relative word address and
2331 add it to the containing PC. */
2332 rel
= ((int)(op
<< 6) >> 6);
2333 return pc
+ 8 + rel
;
2337 /* If pc is in a shared library trampoline, return its target. */
2338 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2339 if (solib_target_pc
)
2340 return solib_target_pc
;
2342 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2344 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2345 if (op
!= trampoline_code
[ii
])
2348 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2350 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2354 /* ISA-specific vector types. */
2356 static struct type
*
2357 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2359 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2361 if (!tdep
->ppc_builtin_type_vec64
)
2363 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2365 /* The type we're building is this: */
2367 union __gdb_builtin_type_vec64
2371 int32_t v2_int32
[2];
2372 int16_t v4_int16
[4];
2379 t
= arch_composite_type (gdbarch
,
2380 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2381 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2382 append_composite_type_field (t
, "v2_float",
2383 init_vector_type (bt
->builtin_float
, 2));
2384 append_composite_type_field (t
, "v2_int32",
2385 init_vector_type (bt
->builtin_int32
, 2));
2386 append_composite_type_field (t
, "v4_int16",
2387 init_vector_type (bt
->builtin_int16
, 4));
2388 append_composite_type_field (t
, "v8_int8",
2389 init_vector_type (bt
->builtin_int8
, 8));
2391 TYPE_VECTOR (t
) = 1;
2392 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2393 tdep
->ppc_builtin_type_vec64
= t
;
2396 return tdep
->ppc_builtin_type_vec64
;
2399 /* Vector 128 type. */
2401 static struct type
*
2402 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2404 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2406 if (!tdep
->ppc_builtin_type_vec128
)
2408 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2410 /* The type we're building is this
2412 type = union __ppc_builtin_type_vec128 {
2414 double v2_double[2];
2416 int32_t v4_int32[4];
2417 int16_t v8_int16[8];
2418 int8_t v16_int8[16];
2424 t
= arch_composite_type (gdbarch
,
2425 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2426 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2427 append_composite_type_field (t
, "v2_double",
2428 init_vector_type (bt
->builtin_double
, 2));
2429 append_composite_type_field (t
, "v4_float",
2430 init_vector_type (bt
->builtin_float
, 4));
2431 append_composite_type_field (t
, "v4_int32",
2432 init_vector_type (bt
->builtin_int32
, 4));
2433 append_composite_type_field (t
, "v8_int16",
2434 init_vector_type (bt
->builtin_int16
, 8));
2435 append_composite_type_field (t
, "v16_int8",
2436 init_vector_type (bt
->builtin_int8
, 16));
2438 TYPE_VECTOR (t
) = 1;
2439 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2440 tdep
->ppc_builtin_type_vec128
= t
;
2443 return tdep
->ppc_builtin_type_vec128
;
2446 /* Return the name of register number REGNO, or the empty string if it
2447 is an anonymous register. */
2450 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2452 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2454 /* The upper half "registers" have names in the XML description,
2455 but we present only the low GPRs and the full 64-bit registers
2457 if (tdep
->ppc_ev0_upper_regnum
>= 0
2458 && tdep
->ppc_ev0_upper_regnum
<= regno
2459 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2462 /* Hide the upper halves of the vs0~vs31 registers. */
2463 if (tdep
->ppc_vsr0_regnum
>= 0
2464 && tdep
->ppc_vsr0_upper_regnum
<= regno
2465 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2468 /* Check if the SPE pseudo registers are available. */
2469 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2471 static const char *const spe_regnames
[] = {
2472 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2473 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2474 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2475 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2477 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2480 /* Check if the decimal128 pseudo-registers are available. */
2481 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2483 static const char *const dfp128_regnames
[] = {
2484 "dl0", "dl1", "dl2", "dl3",
2485 "dl4", "dl5", "dl6", "dl7",
2486 "dl8", "dl9", "dl10", "dl11",
2487 "dl12", "dl13", "dl14", "dl15"
2489 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2492 /* Check if this is a VSX pseudo-register. */
2493 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2495 static const char *const vsx_regnames
[] = {
2496 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2497 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2498 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2499 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2500 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2501 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2502 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2503 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2504 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2506 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2509 /* Check if the this is a Extended FP pseudo-register. */
2510 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2512 static const char *const efpr_regnames
[] = {
2513 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2514 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2515 "f46", "f47", "f48", "f49", "f50", "f51",
2516 "f52", "f53", "f54", "f55", "f56", "f57",
2517 "f58", "f59", "f60", "f61", "f62", "f63"
2519 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2522 return tdesc_register_name (gdbarch
, regno
);
2525 /* Return the GDB type object for the "standard" data type of data in
2528 static struct type
*
2529 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2531 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2533 /* These are the only pseudo-registers we support. */
2534 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2535 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2536 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2537 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2539 /* These are the e500 pseudo-registers. */
2540 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2541 return rs6000_builtin_type_vec64 (gdbarch
);
2542 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2543 /* PPC decimal128 pseudo-registers. */
2544 return builtin_type (gdbarch
)->builtin_declong
;
2545 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2546 /* POWER7 VSX pseudo-registers. */
2547 return rs6000_builtin_type_vec128 (gdbarch
);
2549 /* POWER7 Extended FP pseudo-registers. */
2550 return builtin_type (gdbarch
)->builtin_double
;
2553 /* Is REGNUM a member of REGGROUP? */
2555 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2556 struct reggroup
*group
)
2558 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2560 /* These are the only pseudo-registers we support. */
2561 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2562 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2563 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2564 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2566 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2567 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2568 return group
== all_reggroup
|| group
== vector_reggroup
;
2570 /* PPC decimal128 or Extended FP pseudo-registers. */
2571 return group
== all_reggroup
|| group
== float_reggroup
;
2574 /* The register format for RS/6000 floating point registers is always
2575 double, we need a conversion if the memory format is float. */
2578 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2581 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2583 return (tdep
->ppc_fp0_regnum
>= 0
2584 && regnum
>= tdep
->ppc_fp0_regnum
2585 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2586 && TYPE_CODE (type
) == TYPE_CODE_FLT
2587 && TYPE_LENGTH (type
)
2588 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2592 rs6000_register_to_value (struct frame_info
*frame
,
2596 int *optimizedp
, int *unavailablep
)
2598 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2599 gdb_byte from
[MAX_REGISTER_SIZE
];
2601 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2603 if (!get_frame_register_bytes (frame
, regnum
, 0,
2604 register_size (gdbarch
, regnum
),
2605 from
, optimizedp
, unavailablep
))
2608 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2610 *optimizedp
= *unavailablep
= 0;
2615 rs6000_value_to_register (struct frame_info
*frame
,
2618 const gdb_byte
*from
)
2620 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2621 gdb_byte to
[MAX_REGISTER_SIZE
];
2623 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2625 convert_typed_floating (from
, type
,
2626 to
, builtin_type (gdbarch
)->builtin_double
);
2627 put_frame_register (frame
, regnum
, to
);
2630 /* The type of a function that moves the value of REG between CACHE
2631 or BUF --- in either direction. */
2632 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2635 /* Move SPE vector register values between a 64-bit buffer and the two
2636 32-bit raw register halves in a regcache. This function handles
2637 both splitting a 64-bit value into two 32-bit halves, and joining
2638 two halves into a whole 64-bit value, depending on the function
2639 passed as the MOVE argument.
2641 EV_REG must be the number of an SPE evN vector register --- a
2642 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2645 Call MOVE once for each 32-bit half of that register, passing
2646 REGCACHE, the number of the raw register corresponding to that
2647 half, and the address of the appropriate half of BUFFER.
2649 For example, passing 'regcache_raw_read' as the MOVE function will
2650 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2651 'regcache_raw_supply' will supply the contents of BUFFER to the
2652 appropriate pair of raw registers in REGCACHE.
2654 You may need to cast away some 'const' qualifiers when passing
2655 MOVE, since this function can't tell at compile-time which of
2656 REGCACHE or BUFFER is acting as the source of the data. If C had
2657 co-variant type qualifiers, ... */
2659 static enum register_status
2660 e500_move_ev_register (move_ev_register_func move
,
2661 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2663 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2664 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2666 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2667 enum register_status status
;
2669 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2671 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2673 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2675 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2677 if (status
== REG_VALID
)
2678 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2683 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2684 if (status
== REG_VALID
)
2685 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2692 static enum register_status
2693 do_regcache_raw_read (struct regcache
*regcache
, int regnum
, void *buffer
)
2695 return regcache_raw_read (regcache
, regnum
, (gdb_byte
*) buffer
);
2698 static enum register_status
2699 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2701 regcache_raw_write (regcache
, regnum
, (const gdb_byte
*) buffer
);
2706 static enum register_status
2707 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2708 int reg_nr
, gdb_byte
*buffer
)
2710 return e500_move_ev_register (do_regcache_raw_read
, regcache
, reg_nr
, buffer
);
2714 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2715 int reg_nr
, const gdb_byte
*buffer
)
2717 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2718 reg_nr
, (void *) buffer
);
2721 /* Read method for DFP pseudo-registers. */
2722 static enum register_status
2723 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2724 int reg_nr
, gdb_byte
*buffer
)
2726 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2727 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2728 enum register_status status
;
2730 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2732 /* Read two FP registers to form a whole dl register. */
2733 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2734 2 * reg_index
, buffer
);
2735 if (status
== REG_VALID
)
2736 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2737 2 * reg_index
+ 1, buffer
+ 8);
2741 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2742 2 * reg_index
+ 1, buffer
);
2743 if (status
== REG_VALID
)
2744 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2745 2 * reg_index
, buffer
+ 8);
2751 /* Write method for DFP pseudo-registers. */
2753 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2754 int reg_nr
, const gdb_byte
*buffer
)
2756 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2757 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2759 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2761 /* Write each half of the dl register into a separate
2763 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2764 2 * reg_index
, buffer
);
2765 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2766 2 * reg_index
+ 1, buffer
+ 8);
2770 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2771 2 * reg_index
+ 1, buffer
);
2772 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2773 2 * reg_index
, buffer
+ 8);
2777 /* Read method for POWER7 VSX pseudo-registers. */
2778 static enum register_status
2779 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2780 int reg_nr
, gdb_byte
*buffer
)
2782 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2783 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2784 enum register_status status
;
2786 /* Read the portion that overlaps the VMX registers. */
2788 status
= regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2789 reg_index
- 32, buffer
);
2791 /* Read the portion that overlaps the FPR registers. */
2792 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2794 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2796 if (status
== REG_VALID
)
2797 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2798 reg_index
, buffer
+ 8);
2802 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2803 reg_index
, buffer
+ 8);
2804 if (status
== REG_VALID
)
2805 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2812 /* Write method for POWER7 VSX pseudo-registers. */
2814 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2815 int reg_nr
, const gdb_byte
*buffer
)
2817 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2818 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2820 /* Write the portion that overlaps the VMX registers. */
2822 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2823 reg_index
- 32, buffer
);
2825 /* Write the portion that overlaps the FPR registers. */
2826 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2828 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2830 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2831 reg_index
, buffer
+ 8);
2835 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2836 reg_index
, buffer
+ 8);
2837 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2842 /* Read method for POWER7 Extended FP pseudo-registers. */
2843 static enum register_status
2844 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2845 int reg_nr
, gdb_byte
*buffer
)
2847 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2848 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2849 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2851 /* Read the portion that overlaps the VMX register. */
2852 return regcache_raw_read_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2853 offset
, register_size (gdbarch
, reg_nr
),
2857 /* Write method for POWER7 Extended FP pseudo-registers. */
2859 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2860 int reg_nr
, const gdb_byte
*buffer
)
2862 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2863 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2864 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2866 /* Write the portion that overlaps the VMX register. */
2867 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2868 offset
, register_size (gdbarch
, reg_nr
),
2872 static enum register_status
2873 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2874 struct regcache
*regcache
,
2875 int reg_nr
, gdb_byte
*buffer
)
2877 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2878 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2880 gdb_assert (regcache_arch
== gdbarch
);
2882 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2883 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2884 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2885 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2886 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2887 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2888 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2889 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2891 internal_error (__FILE__
, __LINE__
,
2892 _("rs6000_pseudo_register_read: "
2893 "called on unexpected register '%s' (%d)"),
2894 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2898 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2899 struct regcache
*regcache
,
2900 int reg_nr
, const gdb_byte
*buffer
)
2902 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2903 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2905 gdb_assert (regcache_arch
== gdbarch
);
2907 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2908 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2909 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2910 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2911 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2912 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2913 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2914 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2916 internal_error (__FILE__
, __LINE__
,
2917 _("rs6000_pseudo_register_write: "
2918 "called on unexpected register '%s' (%d)"),
2919 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2922 /* Convert a DBX STABS register number to a GDB register number. */
2924 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2926 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2928 if (0 <= num
&& num
<= 31)
2929 return tdep
->ppc_gp0_regnum
+ num
;
2930 else if (32 <= num
&& num
<= 63)
2931 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2932 specifies registers the architecture doesn't have? Our
2933 callers don't check the value we return. */
2934 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2935 else if (77 <= num
&& num
<= 108)
2936 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2937 else if (1200 <= num
&& num
< 1200 + 32)
2938 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2943 return tdep
->ppc_mq_regnum
;
2945 return tdep
->ppc_lr_regnum
;
2947 return tdep
->ppc_ctr_regnum
;
2949 return tdep
->ppc_xer_regnum
;
2951 return tdep
->ppc_vrsave_regnum
;
2953 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2955 return tdep
->ppc_acc_regnum
;
2957 return tdep
->ppc_spefscr_regnum
;
2964 /* Convert a Dwarf 2 register number to a GDB register number. */
2966 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2968 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2970 if (0 <= num
&& num
<= 31)
2971 return tdep
->ppc_gp0_regnum
+ num
;
2972 else if (32 <= num
&& num
<= 63)
2973 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2974 specifies registers the architecture doesn't have? Our
2975 callers don't check the value we return. */
2976 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2977 else if (1124 <= num
&& num
< 1124 + 32)
2978 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2979 else if (1200 <= num
&& num
< 1200 + 32)
2980 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2985 return tdep
->ppc_cr_regnum
;
2987 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2989 return tdep
->ppc_acc_regnum
;
2991 return tdep
->ppc_mq_regnum
;
2993 return tdep
->ppc_xer_regnum
;
2995 return tdep
->ppc_lr_regnum
;
2997 return tdep
->ppc_ctr_regnum
;
2999 return tdep
->ppc_vrsave_regnum
;
3001 return tdep
->ppc_spefscr_regnum
;
3007 /* Translate a .eh_frame register to DWARF register, or adjust a
3008 .debug_frame register. */
3011 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3013 /* GCC releases before 3.4 use GCC internal register numbering in
3014 .debug_frame (and .debug_info, et cetera). The numbering is
3015 different from the standard SysV numbering for everything except
3016 for GPRs and FPRs. We can not detect this problem in most cases
3017 - to get accurate debug info for variables living in lr, ctr, v0,
3018 et cetera, use a newer version of GCC. But we must detect
3019 one important case - lr is in column 65 in .debug_frame output,
3022 GCC 3.4, and the "hammer" branch, have a related problem. They
3023 record lr register saves in .debug_frame as 108, but still record
3024 the return column as 65. We fix that up too.
3026 We can do this because 65 is assigned to fpsr, and GCC never
3027 generates debug info referring to it. To add support for
3028 handwritten debug info that restores fpsr, we would need to add a
3029 producer version check to this. */
3038 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3039 internal register numbering; translate that to the standard DWARF2
3040 register numbering. */
3041 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3043 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3044 return num
- 68 + 86;
3045 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3046 return num
- 77 + 1124;
3058 case 109: /* vrsave */
3060 case 110: /* vscr */
3062 case 111: /* spe_acc */
3064 case 112: /* spefscr */
3072 /* Handling the various POWER/PowerPC variants. */
3074 /* Information about a particular processor variant. */
3078 /* Name of this variant. */
3081 /* English description of the variant. */
3084 /* bfd_arch_info.arch corresponding to variant. */
3085 enum bfd_architecture arch
;
3087 /* bfd_arch_info.mach corresponding to variant. */
3090 /* Target description for this variant. */
3091 struct target_desc
**tdesc
;
3094 static struct variant variants
[] =
3096 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3097 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3098 {"power", "POWER user-level", bfd_arch_rs6000
,
3099 bfd_mach_rs6k
, &tdesc_rs6000
},
3100 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3101 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3102 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3103 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3104 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3105 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3106 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3107 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3108 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3109 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3110 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3111 604, &tdesc_powerpc_604
},
3112 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3113 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3114 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3115 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3116 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3117 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3118 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3119 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3120 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3121 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3122 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3123 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3126 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3127 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3128 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3129 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3130 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3131 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3132 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3133 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3134 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3135 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3136 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3137 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3139 /* FIXME: I haven't checked the register sets of the following. */
3140 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3141 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3142 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3143 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3144 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3145 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3147 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3150 /* Return the variant corresponding to architecture ARCH and machine number
3151 MACH. If no such variant exists, return null. */
3153 static const struct variant
*
3154 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3156 const struct variant
*v
;
3158 for (v
= variants
; v
->name
; v
++)
3159 if (arch
== v
->arch
&& mach
== v
->mach
)
3166 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3168 if (info
->endian
== BFD_ENDIAN_BIG
)
3169 return print_insn_big_powerpc (memaddr
, info
);
3171 return print_insn_little_powerpc (memaddr
, info
);
3175 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3177 return frame_unwind_register_unsigned (next_frame
,
3178 gdbarch_pc_regnum (gdbarch
));
3181 static struct frame_id
3182 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3184 return frame_id_build (get_frame_register_unsigned
3185 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3186 get_frame_pc (this_frame
));
3189 struct rs6000_frame_cache
3192 CORE_ADDR initial_sp
;
3193 struct trad_frame_saved_reg
*saved_regs
;
3195 /* Set BASE_P to true if this frame cache is properly initialized.
3196 Otherwise set to false because some registers or memory cannot
3199 /* Cache PC for building unavailable frame. */
3203 static struct rs6000_frame_cache
*
3204 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3206 struct rs6000_frame_cache
*cache
;
3207 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3208 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3209 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3210 struct rs6000_framedata fdata
;
3211 int wordsize
= tdep
->wordsize
;
3212 CORE_ADDR func
= 0, pc
= 0;
3214 if ((*this_cache
) != NULL
)
3215 return (struct rs6000_frame_cache
*) (*this_cache
);
3216 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3217 (*this_cache
) = cache
;
3219 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3223 func
= get_frame_func (this_frame
);
3225 pc
= get_frame_pc (this_frame
);
3226 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3228 /* Figure out the parent's stack pointer. */
3230 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3231 address of the current frame. Things might be easier if the
3232 ->frame pointed to the outer-most address of the frame. In
3233 the mean time, the address of the prev frame is used as the
3234 base address of this frame. */
3235 cache
->base
= get_frame_register_unsigned
3236 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3238 CATCH (ex
, RETURN_MASK_ERROR
)
3240 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3241 throw_exception (ex
);
3242 return (struct rs6000_frame_cache
*) (*this_cache
);
3246 /* If the function appears to be frameless, check a couple of likely
3247 indicators that we have simply failed to find the frame setup.
3248 Two common cases of this are missing symbols (i.e.
3249 get_frame_func returns the wrong address or 0), and assembly
3250 stubs which have a fast exit path but set up a frame on the slow
3253 If the LR appears to return to this function, then presume that
3254 we have an ABI compliant frame that we failed to find. */
3255 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3260 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3261 if (func
== 0 && saved_lr
== pc
)
3265 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3266 if (func
== saved_func
)
3272 fdata
.frameless
= 0;
3273 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3277 if (!fdata
.frameless
)
3279 /* Frameless really means stackless. */
3282 if (safe_read_memory_integer (cache
->base
, wordsize
,
3283 byte_order
, &backchain
))
3284 cache
->base
= (CORE_ADDR
) backchain
;
3287 trad_frame_set_value (cache
->saved_regs
,
3288 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3290 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3291 All fpr's from saved_fpr to fp31 are saved. */
3293 if (fdata
.saved_fpr
>= 0)
3296 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3298 /* If skip_prologue says floating-point registers were saved,
3299 but the current architecture has no floating-point registers,
3300 then that's strange. But we have no indices to even record
3301 the addresses under, so we just ignore it. */
3302 if (ppc_floating_point_unit_p (gdbarch
))
3303 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3305 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3310 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3311 All gpr's from saved_gpr to gpr31 are saved (except during the
3314 if (fdata
.saved_gpr
>= 0)
3317 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3318 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3320 if (fdata
.gpr_mask
& (1U << i
))
3321 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3322 gpr_addr
+= wordsize
;
3326 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3327 All vr's from saved_vr to vr31 are saved. */
3328 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3330 if (fdata
.saved_vr
>= 0)
3333 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3334 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3336 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3337 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3342 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3343 All vr's from saved_ev to ev31 are saved. ????? */
3344 if (tdep
->ppc_ev0_regnum
!= -1)
3346 if (fdata
.saved_ev
>= 0)
3349 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3350 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3352 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3354 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3355 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3356 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3361 /* If != 0, fdata.cr_offset is the offset from the frame that
3363 if (fdata
.cr_offset
!= 0)
3364 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3365 = cache
->base
+ fdata
.cr_offset
;
3367 /* If != 0, fdata.lr_offset is the offset from the frame that
3369 if (fdata
.lr_offset
!= 0)
3370 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3371 = cache
->base
+ fdata
.lr_offset
;
3372 else if (fdata
.lr_register
!= -1)
3373 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3374 /* The PC is found in the link register. */
3375 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3376 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3378 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3379 holds the VRSAVE. */
3380 if (fdata
.vrsave_offset
!= 0)
3381 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3382 = cache
->base
+ fdata
.vrsave_offset
;
3384 if (fdata
.alloca_reg
< 0)
3385 /* If no alloca register used, then fi->frame is the value of the
3386 %sp for this frame, and it is good enough. */
3388 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3391 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3398 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3399 struct frame_id
*this_id
)
3401 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3406 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3410 /* This marks the outermost frame. */
3411 if (info
->base
== 0)
3414 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3417 static struct value
*
3418 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3419 void **this_cache
, int regnum
)
3421 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3423 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3426 static const struct frame_unwind rs6000_frame_unwind
=
3429 default_frame_unwind_stop_reason
,
3430 rs6000_frame_this_id
,
3431 rs6000_frame_prev_register
,
3433 default_frame_sniffer
3436 /* Allocate and initialize a frame cache for an epilogue frame.
3437 SP is restored and prev-PC is stored in LR. */
3439 static struct rs6000_frame_cache
*
3440 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3442 struct rs6000_frame_cache
*cache
;
3443 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3444 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3447 return (struct rs6000_frame_cache
*) *this_cache
;
3449 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3450 (*this_cache
) = cache
;
3451 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3455 /* At this point the stack looks as if we just entered the
3456 function, and the return address is stored in LR. */
3459 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3460 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3463 cache
->initial_sp
= sp
;
3465 trad_frame_set_value (cache
->saved_regs
,
3466 gdbarch_pc_regnum (gdbarch
), lr
);
3468 CATCH (ex
, RETURN_MASK_ERROR
)
3470 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3471 throw_exception (ex
);
3478 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3479 Return the frame ID of an epilogue frame. */
3482 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3483 void **this_cache
, struct frame_id
*this_id
)
3486 struct rs6000_frame_cache
*info
=
3487 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3489 pc
= get_frame_func (this_frame
);
3490 if (info
->base
== 0)
3491 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3493 (*this_id
) = frame_id_build (info
->base
, pc
);
3496 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3497 Return the register value of REGNUM in previous frame. */
3499 static struct value
*
3500 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3501 void **this_cache
, int regnum
)
3503 struct rs6000_frame_cache
*info
=
3504 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3505 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3508 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3509 Check whether this an epilogue frame. */
3512 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3513 struct frame_info
*this_frame
,
3514 void **this_prologue_cache
)
3516 if (frame_relative_level (this_frame
) == 0)
3517 return rs6000_in_function_epilogue_frame_p (this_frame
,
3518 get_frame_arch (this_frame
),
3519 get_frame_pc (this_frame
));
3524 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3525 a function without debug information. */
3527 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3530 default_frame_unwind_stop_reason
,
3531 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3533 rs6000_epilogue_frame_sniffer
3538 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3540 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3542 return info
->initial_sp
;
3545 static const struct frame_base rs6000_frame_base
= {
3546 &rs6000_frame_unwind
,
3547 rs6000_frame_base_address
,
3548 rs6000_frame_base_address
,
3549 rs6000_frame_base_address
3552 static const struct frame_base
*
3553 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3555 return &rs6000_frame_base
;
3558 /* DWARF-2 frame support. Used to handle the detection of
3559 clobbered registers during function calls. */
3562 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3563 struct dwarf2_frame_state_reg
*reg
,
3564 struct frame_info
*this_frame
)
3566 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3568 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3569 non-volatile registers. We will use the same code for both. */
3571 /* Call-saved GP registers. */
3572 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3573 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3574 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3575 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3577 /* Call-clobbered GP registers. */
3578 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3579 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3580 || (regnum
== tdep
->ppc_gp0_regnum
))
3581 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3583 /* Deal with FP registers, if supported. */
3584 if (tdep
->ppc_fp0_regnum
>= 0)
3586 /* Call-saved FP registers. */
3587 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3588 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3589 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3591 /* Call-clobbered FP registers. */
3592 if ((regnum
>= tdep
->ppc_fp0_regnum
3593 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3594 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3597 /* Deal with ALTIVEC registers, if supported. */
3598 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3600 /* Call-saved Altivec registers. */
3601 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3602 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3603 || regnum
== tdep
->ppc_vrsave_regnum
)
3604 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3606 /* Call-clobbered Altivec registers. */
3607 if ((regnum
>= tdep
->ppc_vr0_regnum
3608 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3609 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3612 /* Handle PC register and Stack Pointer correctly. */
3613 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3614 reg
->how
= DWARF2_FRAME_REG_RA
;
3615 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3616 reg
->how
= DWARF2_FRAME_REG_CFA
;
3620 /* Return true if a .gnu_attributes section exists in BFD and it
3621 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3622 section exists in BFD and it indicates that SPE extensions are in
3623 use. Check the .gnu.attributes section first, as the binary might be
3624 compiled for SPE, but not actually using SPE instructions. */
3627 bfd_uses_spe_extensions (bfd
*abfd
)
3630 gdb_byte
*contents
= NULL
;
3640 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3641 could be using the SPE vector abi without actually using any spe
3642 bits whatsoever. But it's close enough for now. */
3643 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3644 Tag_GNU_Power_ABI_Vector
);
3645 if (vector_abi
== 3)
3649 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3653 size
= bfd_get_section_size (sect
);
3654 contents
= (gdb_byte
*) xmalloc (size
);
3655 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3661 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3667 char name[name_len rounded up to 4-byte alignment];
3668 char data[data_len];
3671 Technically, there's only supposed to be one such structure in a
3672 given apuinfo section, but the linker is not always vigilant about
3673 merging apuinfo sections from input files. Just go ahead and parse
3674 them all, exiting early when we discover the binary uses SPE
3677 It's not specified in what endianness the information in this
3678 section is stored. Assume that it's the endianness of the BFD. */
3682 unsigned int name_len
;
3683 unsigned int data_len
;
3686 /* If we can't read the first three fields, we're done. */
3690 name_len
= bfd_get_32 (abfd
, ptr
);
3691 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3692 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3693 type
= bfd_get_32 (abfd
, ptr
+ 8);
3696 /* The name must be "APUinfo\0". */
3698 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3702 /* The type must be 2. */
3706 /* The data is stored as a series of uint32. The upper half of
3707 each uint32 indicates the particular APU used and the lower
3708 half indicates the revision of that APU. We just care about
3711 /* Not 4-byte quantities. */
3717 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3718 unsigned int apu
= apuinfo
>> 16;
3722 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3724 if (apu
== 0x100 || apu
== 0x101)
3739 /* These are macros for parsing instruction fields (I.1.6.28) */
3741 #define PPC_FIELD(value, from, len) \
3742 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3743 #define PPC_SEXT(v, bs) \
3744 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3745 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3746 - ((CORE_ADDR) 1 << ((bs) - 1)))
3747 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3748 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3749 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3750 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3751 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3752 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3753 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3754 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3755 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3756 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3757 | (PPC_FIELD (insn, 16, 5) << 5))
3758 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3759 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3760 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3761 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3762 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3763 #define PPC_OE(insn) PPC_BIT (insn, 21)
3764 #define PPC_RC(insn) PPC_BIT (insn, 31)
3765 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3766 #define PPC_LK(insn) PPC_BIT (insn, 31)
3767 #define PPC_TX(insn) PPC_BIT (insn, 31)
3768 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3770 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3771 #define PPC_XER_NB(xer) (xer & 0x7f)
3773 /* Record Vector-Scalar Registers.
3774 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3775 Otherwise, it's just a VR register. Record them accordingly. */
3778 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3780 if (vsr
< 0 || vsr
>= 64)
3785 if (tdep
->ppc_vr0_regnum
>= 0)
3786 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3790 if (tdep
->ppc_fp0_regnum
>= 0)
3791 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3792 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3793 record_full_arch_list_add_reg (regcache
,
3794 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3800 /* Parse and record instructions primary opcode-4 at ADDR.
3801 Return 0 if successful. */
3804 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3805 CORE_ADDR addr
, uint32_t insn
)
3807 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3808 int ext
= PPC_FIELD (insn
, 21, 11);
3812 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3813 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3814 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3815 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3816 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3818 case 42: /* Vector Select */
3819 case 43: /* Vector Permute */
3820 case 44: /* Vector Shift Left Double by Octet Immediate */
3821 case 45: /* Vector Permute and Exclusive-OR */
3822 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3823 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3824 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3825 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3826 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3827 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3828 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3829 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3830 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3831 case 46: /* Vector Multiply-Add Single-Precision */
3832 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3833 record_full_arch_list_add_reg (regcache
,
3834 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3838 switch ((ext
& 0x1ff))
3840 /* 5.16 Decimal Integer Arithmetic Instructions */
3841 case 1: /* Decimal Add Modulo */
3842 case 65: /* Decimal Subtract Modulo */
3844 /* Bit-21 should be set. */
3845 if (!PPC_BIT (insn
, 21))
3848 record_full_arch_list_add_reg (regcache
,
3849 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3850 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3854 /* Bit-21 is used for RC */
3855 switch (ext
& 0x3ff)
3857 case 6: /* Vector Compare Equal To Unsigned Byte */
3858 case 70: /* Vector Compare Equal To Unsigned Halfword */
3859 case 134: /* Vector Compare Equal To Unsigned Word */
3860 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3861 case 774: /* Vector Compare Greater Than Signed Byte */
3862 case 838: /* Vector Compare Greater Than Signed Halfword */
3863 case 902: /* Vector Compare Greater Than Signed Word */
3864 case 967: /* Vector Compare Greater Than Signed Doubleword */
3865 case 518: /* Vector Compare Greater Than Unsigned Byte */
3866 case 646: /* Vector Compare Greater Than Unsigned Word */
3867 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3868 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3869 case 966: /* Vector Compare Bounds Single-Precision */
3870 case 198: /* Vector Compare Equal To Single-Precision */
3871 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3872 case 710: /* Vector Compare Greater Than Single-Precision */
3874 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3875 record_full_arch_list_add_reg (regcache
,
3876 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3882 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
3883 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
3884 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
3885 case 334: /* Vector Pack Signed Word Unsigned Saturate */
3886 case 398: /* Vector Pack Signed Halfword Signed Saturate */
3887 case 462: /* Vector Pack Signed Word Signed Saturate */
3888 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
3889 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
3890 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
3891 case 512: /* Vector Add Unsigned Byte Saturate */
3892 case 576: /* Vector Add Unsigned Halfword Saturate */
3893 case 640: /* Vector Add Unsigned Word Saturate */
3894 case 768: /* Vector Add Signed Byte Saturate */
3895 case 832: /* Vector Add Signed Halfword Saturate */
3896 case 896: /* Vector Add Signed Word Saturate */
3897 case 1536: /* Vector Subtract Unsigned Byte Saturate */
3898 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
3899 case 1664: /* Vector Subtract Unsigned Word Saturate */
3900 case 1792: /* Vector Subtract Signed Byte Saturate */
3901 case 1856: /* Vector Subtract Signed Halfword Saturate */
3902 case 1920: /* Vector Subtract Signed Word Saturate */
3904 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
3905 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
3906 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
3907 case 1672: /* Vector Sum across Half Signed Word Saturate */
3908 case 1928: /* Vector Sum across Signed Word Saturate */
3909 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
3910 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
3911 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3913 case 12: /* Vector Merge High Byte */
3914 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
3915 case 76: /* Vector Merge High Halfword */
3916 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
3917 case 140: /* Vector Merge High Word */
3918 case 268: /* Vector Merge Low Byte */
3919 case 332: /* Vector Merge Low Halfword */
3920 case 396: /* Vector Merge Low Word */
3921 case 526: /* Vector Unpack High Signed Byte */
3922 case 590: /* Vector Unpack High Signed Halfword */
3923 case 654: /* Vector Unpack Low Signed Byte */
3924 case 718: /* Vector Unpack Low Signed Halfword */
3925 case 782: /* Vector Pack Pixel */
3926 case 846: /* Vector Unpack High Pixel */
3927 case 974: /* Vector Unpack Low Pixel */
3928 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
3929 case 1614: /* Vector Unpack High Signed Word */
3930 case 1676: /* Vector Merge Odd Word */
3931 case 1742: /* Vector Unpack Low Signed Word */
3932 case 1932: /* Vector Merge Even Word */
3933 case 524: /* Vector Splat Byte */
3934 case 588: /* Vector Splat Halfword */
3935 case 652: /* Vector Splat Word */
3936 case 780: /* Vector Splat Immediate Signed Byte */
3937 case 844: /* Vector Splat Immediate Signed Halfword */
3938 case 908: /* Vector Splat Immediate Signed Word */
3939 case 452: /* Vector Shift Left */
3940 case 708: /* Vector Shift Right */
3941 case 1036: /* Vector Shift Left by Octet */
3942 case 1100: /* Vector Shift Right by Octet */
3943 case 0: /* Vector Add Unsigned Byte Modulo */
3944 case 64: /* Vector Add Unsigned Halfword Modulo */
3945 case 128: /* Vector Add Unsigned Word Modulo */
3946 case 192: /* Vector Add Unsigned Doubleword Modulo */
3947 case 256: /* Vector Add Unsigned Quadword Modulo */
3948 case 320: /* Vector Add & write Carry Unsigned Quadword */
3949 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
3950 case 8: /* Vector Multiply Odd Unsigned Byte */
3951 case 72: /* Vector Multiply Odd Unsigned Halfword */
3952 case 136: /* Vector Multiply Odd Unsigned Word */
3953 case 264: /* Vector Multiply Odd Signed Byte */
3954 case 328: /* Vector Multiply Odd Signed Halfword */
3955 case 392: /* Vector Multiply Odd Signed Word */
3956 case 520: /* Vector Multiply Even Unsigned Byte */
3957 case 584: /* Vector Multiply Even Unsigned Halfword */
3958 case 648: /* Vector Multiply Even Unsigned Word */
3959 case 776: /* Vector Multiply Even Signed Byte */
3960 case 840: /* Vector Multiply Even Signed Halfword */
3961 case 904: /* Vector Multiply Even Signed Word */
3962 case 137: /* Vector Multiply Unsigned Word Modulo */
3963 case 1024: /* Vector Subtract Unsigned Byte Modulo */
3964 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
3965 case 1152: /* Vector Subtract Unsigned Word Modulo */
3966 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
3967 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
3968 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
3969 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
3970 case 1282: /* Vector Average Signed Byte */
3971 case 1346: /* Vector Average Signed Halfword */
3972 case 1410: /* Vector Average Signed Word */
3973 case 1026: /* Vector Average Unsigned Byte */
3974 case 1090: /* Vector Average Unsigned Halfword */
3975 case 1154: /* Vector Average Unsigned Word */
3976 case 258: /* Vector Maximum Signed Byte */
3977 case 322: /* Vector Maximum Signed Halfword */
3978 case 386: /* Vector Maximum Signed Word */
3979 case 450: /* Vector Maximum Signed Doubleword */
3980 case 2: /* Vector Maximum Unsigned Byte */
3981 case 66: /* Vector Maximum Unsigned Halfword */
3982 case 130: /* Vector Maximum Unsigned Word */
3983 case 194: /* Vector Maximum Unsigned Doubleword */
3984 case 770: /* Vector Minimum Signed Byte */
3985 case 834: /* Vector Minimum Signed Halfword */
3986 case 898: /* Vector Minimum Signed Word */
3987 case 962: /* Vector Minimum Signed Doubleword */
3988 case 514: /* Vector Minimum Unsigned Byte */
3989 case 578: /* Vector Minimum Unsigned Halfword */
3990 case 642: /* Vector Minimum Unsigned Word */
3991 case 706: /* Vector Minimum Unsigned Doubleword */
3992 case 1028: /* Vector Logical AND */
3993 case 1668: /* Vector Logical Equivalent */
3994 case 1092: /* Vector Logical AND with Complement */
3995 case 1412: /* Vector Logical NAND */
3996 case 1348: /* Vector Logical OR with Complement */
3997 case 1156: /* Vector Logical OR */
3998 case 1284: /* Vector Logical NOR */
3999 case 1220: /* Vector Logical XOR */
4000 case 4: /* Vector Rotate Left Byte */
4001 case 132: /* Vector Rotate Left Word VX-form */
4002 case 68: /* Vector Rotate Left Halfword */
4003 case 196: /* Vector Rotate Left Doubleword */
4004 case 260: /* Vector Shift Left Byte */
4005 case 388: /* Vector Shift Left Word */
4006 case 324: /* Vector Shift Left Halfword */
4007 case 1476: /* Vector Shift Left Doubleword */
4008 case 516: /* Vector Shift Right Byte */
4009 case 644: /* Vector Shift Right Word */
4010 case 580: /* Vector Shift Right Halfword */
4011 case 1732: /* Vector Shift Right Doubleword */
4012 case 772: /* Vector Shift Right Algebraic Byte */
4013 case 900: /* Vector Shift Right Algebraic Word */
4014 case 836: /* Vector Shift Right Algebraic Halfword */
4015 case 964: /* Vector Shift Right Algebraic Doubleword */
4016 case 10: /* Vector Add Single-Precision */
4017 case 74: /* Vector Subtract Single-Precision */
4018 case 1034: /* Vector Maximum Single-Precision */
4019 case 1098: /* Vector Minimum Single-Precision */
4020 case 842: /* Vector Convert From Signed Fixed-Point Word */
4021 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4022 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4023 case 522: /* Vector Round to Single-Precision Integer Nearest */
4024 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4025 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4026 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4027 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4028 case 266: /* Vector Reciprocal Estimate Single-Precision */
4029 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4030 case 1288: /* Vector AES Cipher */
4031 case 1289: /* Vector AES Cipher Last */
4032 case 1352: /* Vector AES Inverse Cipher */
4033 case 1353: /* Vector AES Inverse Cipher Last */
4034 case 1480: /* Vector AES SubBytes */
4035 case 1730: /* Vector SHA-512 Sigma Doubleword */
4036 case 1666: /* Vector SHA-256 Sigma Word */
4037 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4038 case 1160: /* Vector Polynomial Multiply-Sum Word */
4039 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4040 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4041 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4042 case 1794: /* Vector Count Leading Zeros Byte */
4043 case 1858: /* Vector Count Leading Zeros Halfword */
4044 case 1922: /* Vector Count Leading Zeros Word */
4045 case 1986: /* Vector Count Leading Zeros Doubleword */
4046 case 1795: /* Vector Population Count Byte */
4047 case 1859: /* Vector Population Count Halfword */
4048 case 1923: /* Vector Population Count Word */
4049 case 1987: /* Vector Population Count Doubleword */
4050 case 1356: /* Vector Bit Permute Quadword */
4051 record_full_arch_list_add_reg (regcache
,
4052 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4055 case 1604: /* Move To Vector Status and Control Register */
4056 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4058 case 1540: /* Move From Vector Status and Control Register */
4059 record_full_arch_list_add_reg (regcache
,
4060 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4064 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4065 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4069 /* Parse and record instructions of primary opcode-19 at ADDR.
4070 Return 0 if successful. */
4073 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4074 CORE_ADDR addr
, uint32_t insn
)
4076 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4077 int ext
= PPC_EXTOP (insn
);
4081 case 0: /* Move Condition Register Field */
4082 case 33: /* Condition Register NOR */
4083 case 129: /* Condition Register AND with Complement */
4084 case 193: /* Condition Register XOR */
4085 case 225: /* Condition Register NAND */
4086 case 257: /* Condition Register AND */
4087 case 289: /* Condition Register Equivalent */
4088 case 417: /* Condition Register OR with Complement */
4089 case 449: /* Condition Register OR */
4090 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4093 case 16: /* Branch Conditional */
4094 case 560: /* Branch Conditional to Branch Target Address Register */
4095 if ((PPC_BO (insn
) & 0x4) == 0)
4096 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4098 case 528: /* Branch Conditional to Count Register */
4100 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4103 case 150: /* Instruction Synchronize */
4108 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4109 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4113 /* Parse and record instructions of primary opcode-31 at ADDR.
4114 Return 0 if successful. */
4117 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4118 CORE_ADDR addr
, uint32_t insn
)
4120 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4121 int ext
= PPC_EXTOP (insn
);
4123 CORE_ADDR at_dcsz
, ea
= 0;
4124 ULONGEST rb
, ra
, xer
;
4127 /* These instructions have OE bit. */
4128 switch (ext
& 0x1ff)
4130 /* These write RT and XER. Update CR if RC is set. */
4131 case 8: /* Subtract from carrying */
4132 case 10: /* Add carrying */
4133 case 136: /* Subtract from extended */
4134 case 138: /* Add extended */
4135 case 200: /* Subtract from zero extended */
4136 case 202: /* Add to zero extended */
4137 case 232: /* Subtract from minus one extended */
4138 case 234: /* Add to minus one extended */
4139 /* CA is always altered, but SO/OV are only altered when OE=1.
4140 In any case, XER is always altered. */
4141 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4143 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4144 record_full_arch_list_add_reg (regcache
,
4145 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4148 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4149 case 40: /* Subtract from */
4150 case 104: /* Negate */
4151 case 233: /* Multiply low doubleword */
4152 case 235: /* Multiply low word */
4154 case 393: /* Divide Doubleword Extended Unsigned */
4155 case 395: /* Divide Word Extended Unsigned */
4156 case 425: /* Divide Doubleword Extended */
4157 case 427: /* Divide Word Extended */
4158 case 457: /* Divide Doubleword Unsigned */
4159 case 459: /* Divide Word Unsigned */
4160 case 489: /* Divide Doubleword */
4161 case 491: /* Divide Word */
4163 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4165 case 9: /* Multiply High Doubleword Unsigned */
4166 case 11: /* Multiply High Word Unsigned */
4167 case 73: /* Multiply High Doubleword */
4168 case 75: /* Multiply High Word */
4170 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4171 record_full_arch_list_add_reg (regcache
,
4172 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4176 if ((ext
& 0x1f) == 15)
4178 /* Integer Select. bit[16:20] is used for BC. */
4179 record_full_arch_list_add_reg (regcache
,
4180 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4186 case 78: /* Determine Leftmost Zero Byte */
4188 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4189 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4190 record_full_arch_list_add_reg (regcache
,
4191 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4194 /* These only write RT. */
4195 case 19: /* Move from condition register */
4196 /* Move From One Condition Register Field */
4197 case 74: /* Add and Generate Sixes */
4198 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4199 case 302: /* Move From Branch History Rolling Buffer */
4200 case 339: /* Move From Special Purpose Register */
4201 case 371: /* Move From Time Base [Phased-Out] */
4202 record_full_arch_list_add_reg (regcache
,
4203 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4206 /* These only write to RA. */
4207 case 51: /* Move From VSR Doubleword */
4208 case 115: /* Move From VSR Word and Zero */
4209 case 122: /* Population count bytes */
4210 case 378: /* Population count words */
4211 case 506: /* Population count doublewords */
4212 case 154: /* Parity Word */
4213 case 186: /* Parity Doubleword */
4214 case 252: /* Bit Permute Doubleword */
4215 case 282: /* Convert Declets To Binary Coded Decimal */
4216 case 314: /* Convert Binary Coded Decimal To Declets */
4217 case 508: /* Compare bytes */
4218 record_full_arch_list_add_reg (regcache
,
4219 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4222 /* These write CR and optional RA. */
4223 case 792: /* Shift Right Algebraic Word */
4224 case 794: /* Shift Right Algebraic Doubleword */
4225 case 824: /* Shift Right Algebraic Word Immediate */
4226 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4227 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4228 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4229 record_full_arch_list_add_reg (regcache
,
4230 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4232 case 0: /* Compare */
4233 case 32: /* Compare logical */
4234 case 144: /* Move To Condition Register Fields */
4235 /* Move To One Condition Register Field */
4236 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4239 /* These write to RT. Update RA if 'update indexed.' */
4240 case 53: /* Load Doubleword with Update Indexed */
4241 case 119: /* Load Byte and Zero with Update Indexed */
4242 case 311: /* Load Halfword and Zero with Update Indexed */
4243 case 55: /* Load Word and Zero with Update Indexed */
4244 case 375: /* Load Halfword Algebraic with Update Indexed */
4245 case 373: /* Load Word Algebraic with Update Indexed */
4246 record_full_arch_list_add_reg (regcache
,
4247 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4249 case 21: /* Load Doubleword Indexed */
4250 case 52: /* Load Byte And Reserve Indexed */
4251 case 116: /* Load Halfword And Reserve Indexed */
4252 case 20: /* Load Word And Reserve Indexed */
4253 case 84: /* Load Doubleword And Reserve Indexed */
4254 case 87: /* Load Byte and Zero Indexed */
4255 case 279: /* Load Halfword and Zero Indexed */
4256 case 23: /* Load Word and Zero Indexed */
4257 case 343: /* Load Halfword Algebraic Indexed */
4258 case 341: /* Load Word Algebraic Indexed */
4259 case 790: /* Load Halfword Byte-Reverse Indexed */
4260 case 534: /* Load Word Byte-Reverse Indexed */
4261 case 532: /* Load Doubleword Byte-Reverse Indexed */
4262 record_full_arch_list_add_reg (regcache
,
4263 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4266 case 597: /* Load String Word Immediate */
4267 case 533: /* Load String Word Indexed */
4276 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4277 nr
= PPC_XER_NB (xer
);
4282 /* If n=0, the contents of register RT are undefined. */
4286 for (i
= 0; i
< nr
; i
++)
4287 record_full_arch_list_add_reg (regcache
,
4288 tdep
->ppc_gp0_regnum
4289 + ((PPC_RT (insn
) + i
) & 0x1f));
4292 case 276: /* Load Quadword And Reserve Indexed */
4293 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4294 record_full_arch_list_add_reg (regcache
, tmp
);
4295 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4298 /* These write VRT. */
4299 case 6: /* Load Vector for Shift Left Indexed */
4300 case 38: /* Load Vector for Shift Right Indexed */
4301 case 7: /* Load Vector Element Byte Indexed */
4302 case 39: /* Load Vector Element Halfword Indexed */
4303 case 71: /* Load Vector Element Word Indexed */
4304 case 103: /* Load Vector Indexed */
4305 case 359: /* Load Vector Indexed LRU */
4306 record_full_arch_list_add_reg (regcache
,
4307 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4310 /* These write FRT. Update RA if 'update indexed.' */
4311 case 567: /* Load Floating-Point Single with Update Indexed */
4312 case 631: /* Load Floating-Point Double with Update Indexed */
4313 record_full_arch_list_add_reg (regcache
,
4314 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4316 case 535: /* Load Floating-Point Single Indexed */
4317 case 599: /* Load Floating-Point Double Indexed */
4318 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4319 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4320 record_full_arch_list_add_reg (regcache
,
4321 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4324 case 791: /* Load Floating-Point Double Pair Indexed */
4325 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4326 record_full_arch_list_add_reg (regcache
, tmp
);
4327 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4330 case 179: /* Move To VSR Doubleword */
4331 case 211: /* Move To VSR Word Algebraic */
4332 case 243: /* Move To VSR Word and Zero */
4333 case 588: /* Load VSX Scalar Doubleword Indexed */
4334 case 524: /* Load VSX Scalar Single-Precision Indexed */
4335 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4336 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4337 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4338 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4339 case 780: /* Load VSX Vector Word*4 Indexed */
4340 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4343 /* These write RA. Update CR if RC is set. */
4344 case 24: /* Shift Left Word */
4345 case 26: /* Count Leading Zeros Word */
4346 case 27: /* Shift Left Doubleword */
4348 case 58: /* Count Leading Zeros Doubleword */
4349 case 60: /* AND with Complement */
4351 case 284: /* Equivalent */
4353 case 476: /* NAND */
4354 case 412: /* OR with Complement */
4356 case 536: /* Shift Right Word */
4357 case 539: /* Shift Right Doubleword */
4358 case 922: /* Extend Sign Halfword */
4359 case 954: /* Extend Sign Byte */
4360 case 986: /* Extend Sign Word */
4362 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4363 record_full_arch_list_add_reg (regcache
,
4364 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4368 case 181: /* Store Doubleword with Update Indexed */
4369 case 183: /* Store Word with Update Indexed */
4370 case 247: /* Store Byte with Update Indexed */
4371 case 439: /* Store Half Word with Update Indexed */
4372 case 695: /* Store Floating-Point Single with Update Indexed */
4373 case 759: /* Store Floating-Point Double with Update Indexed */
4374 record_full_arch_list_add_reg (regcache
,
4375 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4377 case 135: /* Store Vector Element Byte Indexed */
4378 case 167: /* Store Vector Element Halfword Indexed */
4379 case 199: /* Store Vector Element Word Indexed */
4380 case 231: /* Store Vector Indexed */
4381 case 487: /* Store Vector Indexed LRU */
4382 case 716: /* Store VSX Scalar Doubleword Indexed */
4383 case 140: /* Store VSX Scalar as Integer Word Indexed */
4384 case 652: /* Store VSX Scalar Single-Precision Indexed */
4385 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4386 case 908: /* Store VSX Vector Word*4 Indexed */
4387 case 149: /* Store Doubleword Indexed */
4388 case 151: /* Store Word Indexed */
4389 case 215: /* Store Byte Indexed */
4390 case 407: /* Store Half Word Indexed */
4391 case 694: /* Store Byte Conditional Indexed */
4392 case 726: /* Store Halfword Conditional Indexed */
4393 case 150: /* Store Word Conditional Indexed */
4394 case 214: /* Store Doubleword Conditional Indexed */
4395 case 182: /* Store Quadword Conditional Indexed */
4396 case 662: /* Store Word Byte-Reverse Indexed */
4397 case 918: /* Store Halfword Byte-Reverse Indexed */
4398 case 660: /* Store Doubleword Byte-Reverse Indexed */
4399 case 663: /* Store Floating-Point Single Indexed */
4400 case 727: /* Store Floating-Point Double Indexed */
4401 case 919: /* Store Floating-Point Double Pair Indexed */
4402 case 983: /* Store Floating-Point as Integer Word Indexed */
4403 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4404 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4407 if (PPC_RA (insn
) != 0)
4408 regcache_raw_read_unsigned (regcache
,
4409 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4410 regcache_raw_read_unsigned (regcache
,
4411 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4416 case 183: /* Store Word with Update Indexed */
4417 case 199: /* Store Vector Element Word Indexed */
4418 case 140: /* Store VSX Scalar as Integer Word Indexed */
4419 case 652: /* Store VSX Scalar Single-Precision Indexed */
4420 case 151: /* Store Word Indexed */
4421 case 150: /* Store Word Conditional Indexed */
4422 case 662: /* Store Word Byte-Reverse Indexed */
4423 case 663: /* Store Floating-Point Single Indexed */
4424 case 695: /* Store Floating-Point Single with Update Indexed */
4425 case 983: /* Store Floating-Point as Integer Word Indexed */
4428 case 247: /* Store Byte with Update Indexed */
4429 case 135: /* Store Vector Element Byte Indexed */
4430 case 215: /* Store Byte Indexed */
4431 case 694: /* Store Byte Conditional Indexed */
4434 case 439: /* Store Halfword with Update Indexed */
4435 case 167: /* Store Vector Element Halfword Indexed */
4436 case 407: /* Store Halfword Indexed */
4437 case 726: /* Store Halfword Conditional Indexed */
4438 case 918: /* Store Halfword Byte-Reverse Indexed */
4441 case 181: /* Store Doubleword with Update Indexed */
4442 case 716: /* Store VSX Scalar Doubleword Indexed */
4443 case 149: /* Store Doubleword Indexed */
4444 case 214: /* Store Doubleword Conditional Indexed */
4445 case 660: /* Store Doubleword Byte-Reverse Indexed */
4446 case 727: /* Store Floating-Point Double Indexed */
4447 case 759: /* Store Floating-Point Double with Update Indexed */
4450 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4451 case 908: /* Store VSX Vector Word*4 Indexed */
4452 case 182: /* Store Quadword Conditional Indexed */
4453 case 231: /* Store Vector Indexed */
4454 case 487: /* Store Vector Indexed LRU */
4455 case 919: /* Store Floating-Point Double Pair Indexed */
4462 /* Align address for Store Vector instructions. */
4465 case 167: /* Store Vector Element Halfword Indexed */
4466 addr
= addr
& ~0x1ULL
;
4469 case 199: /* Store Vector Element Word Indexed */
4470 addr
= addr
& ~0x3ULL
;
4473 case 231: /* Store Vector Indexed */
4474 case 487: /* Store Vector Indexed LRU */
4475 addr
= addr
& ~0xfULL
;
4479 record_full_arch_list_add_mem (addr
, size
);
4482 case 725: /* Store String Word Immediate */
4484 if (PPC_RA (insn
) != 0)
4485 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &ra
);
4492 record_full_arch_list_add_mem (ea
, nb
);
4496 case 661: /* Store String Word Indexed */
4498 if (PPC_RA (insn
) != 0)
4499 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &ra
);
4502 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4503 nb
= PPC_XER_NB (xer
);
4507 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &rb
);
4509 record_full_arch_list_add_mem (ea
, nb
);
4514 case 467: /* Move To Special Purpose Register */
4515 switch (PPC_SPR (insn
))
4518 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4521 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4524 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4526 case 256: /* VRSAVE */
4527 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4533 case 147: /* Move To Split Little Endian */
4534 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4537 case 512: /* Move to Condition Register from XER */
4538 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4539 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4542 case 4: /* Trap Word */
4543 case 68: /* Trap Doubleword */
4544 case 430: /* Clear BHRB */
4545 case 598: /* Synchronize */
4546 case 62: /* Wait for Interrupt */
4547 case 22: /* Instruction Cache Block Touch */
4548 case 854: /* Enforce In-order Execution of I/O */
4549 case 246: /* Data Cache Block Touch for Store */
4550 case 54: /* Data Cache Block Store */
4551 case 86: /* Data Cache Block Flush */
4552 case 278: /* Data Cache Block Touch */
4553 case 758: /* Data Cache Block Allocate */
4554 case 982: /* Instruction Cache Block Invalidate */
4557 case 654: /* Transaction Begin */
4558 case 686: /* Transaction End */
4559 case 718: /* Transaction Check */
4560 case 750: /* Transaction Suspend or Resume */
4561 case 782: /* Transaction Abort Word Conditional */
4562 case 814: /* Transaction Abort Doubleword Conditional */
4563 case 846: /* Transaction Abort Word Conditional Immediate */
4564 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4565 case 910: /* Transaction Abort */
4566 fprintf_unfiltered (gdb_stdlog
, "Cannot record Transaction instructions. "
4567 "%08x at %s, 31-%d.\n",
4568 insn
, paddress (gdbarch
, addr
), ext
);
4571 case 1014: /* Data Cache Block set to Zero */
4572 if (target_auxv_search (¤t_target
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4574 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4576 if (PPC_RA (insn
) != 0)
4577 regcache_raw_read_unsigned (regcache
,
4578 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4579 regcache_raw_read_unsigned (regcache
,
4580 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4581 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4582 record_full_arch_list_add_mem (ea
, at_dcsz
);
4587 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4588 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4592 /* Parse and record instructions of primary opcode-59 at ADDR.
4593 Return 0 if successful. */
4596 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4597 CORE_ADDR addr
, uint32_t insn
)
4599 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4600 int ext
= PPC_EXTOP (insn
);
4604 case 18: /* Floating Divide */
4605 case 20: /* Floating Subtract */
4606 case 21: /* Floating Add */
4607 case 22: /* Floating Square Root */
4608 case 24: /* Floating Reciprocal Estimate */
4609 case 25: /* Floating Multiply */
4610 case 26: /* Floating Reciprocal Square Root Estimate */
4611 case 28: /* Floating Multiply-Subtract */
4612 case 29: /* Floating Multiply-Add */
4613 case 30: /* Floating Negative Multiply-Subtract */
4614 case 31: /* Floating Negative Multiply-Add */
4615 record_full_arch_list_add_reg (regcache
,
4616 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4618 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4619 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4626 case 2: /* DFP Add */
4627 case 3: /* DFP Quantize */
4628 case 34: /* DFP Multiply */
4629 case 35: /* DFP Reround */
4630 case 67: /* DFP Quantize Immediate */
4631 case 99: /* DFP Round To FP Integer With Inexact */
4632 case 227: /* DFP Round To FP Integer Without Inexact */
4633 case 258: /* DFP Convert To DFP Long! */
4634 case 290: /* DFP Convert To Fixed */
4635 case 514: /* DFP Subtract */
4636 case 546: /* DFP Divide */
4637 case 770: /* DFP Round To DFP Short! */
4638 case 802: /* DFP Convert From Fixed */
4639 case 834: /* DFP Encode BCD To DPD */
4641 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4642 record_full_arch_list_add_reg (regcache
,
4643 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4644 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4647 case 130: /* DFP Compare Ordered */
4648 case 162: /* DFP Test Exponent */
4649 case 194: /* DFP Test Data Class */
4650 case 226: /* DFP Test Data Group */
4651 case 642: /* DFP Compare Unordered */
4652 case 674: /* DFP Test Significance */
4653 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4654 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4657 case 66: /* DFP Shift Significand Left Immediate */
4658 case 98: /* DFP Shift Significand Right Immediate */
4659 case 322: /* DFP Decode DPD To BCD */
4660 case 354: /* DFP Extract Biased Exponent */
4661 case 866: /* DFP Insert Biased Exponent */
4662 record_full_arch_list_add_reg (regcache
,
4663 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4665 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4668 case 846: /* Floating Convert From Integer Doubleword Single */
4669 case 974: /* Floating Convert From Integer Doubleword Unsigned
4671 record_full_arch_list_add_reg (regcache
,
4672 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4674 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4675 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4680 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4681 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4685 /* Parse and record instructions of primary opcode-60 at ADDR.
4686 Return 0 if successful. */
4689 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4690 CORE_ADDR addr
, uint32_t insn
)
4692 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4693 int ext
= PPC_EXTOP (insn
);
4697 case 0: /* VSX Scalar Add Single-Precision */
4698 case 32: /* VSX Scalar Add Double-Precision */
4699 case 24: /* VSX Scalar Divide Single-Precision */
4700 case 56: /* VSX Scalar Divide Double-Precision */
4701 case 176: /* VSX Scalar Copy Sign Double-Precision */
4702 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4703 case 41: /* ditto */
4704 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4706 case 160: /* VSX Scalar Maximum Double-Precision */
4707 case 168: /* VSX Scalar Minimum Double-Precision */
4708 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4709 case 57: /* ditto */
4710 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4711 case 25: /* ditto */
4712 case 48: /* VSX Scalar Multiply Double-Precision */
4713 case 16: /* VSX Scalar Multiply Single-Precision */
4714 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4715 case 169: /* ditto */
4716 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4717 case 137: /* ditto */
4718 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4719 case 185: /* ditto */
4720 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4721 case 153: /* ditto */
4722 case 40: /* VSX Scalar Subtract Double-Precision */
4723 case 8: /* VSX Scalar Subtract Single-Precision */
4724 case 96: /* VSX Vector Add Double-Precision */
4725 case 64: /* VSX Vector Add Single-Precision */
4726 case 120: /* VSX Vector Divide Double-Precision */
4727 case 88: /* VSX Vector Divide Single-Precision */
4728 case 97: /* VSX Vector Multiply-Add Double-Precision */
4729 case 105: /* ditto */
4730 case 65: /* VSX Vector Multiply-Add Single-Precision */
4731 case 73: /* ditto */
4732 case 224: /* VSX Vector Maximum Double-Precision */
4733 case 192: /* VSX Vector Maximum Single-Precision */
4734 case 232: /* VSX Vector Minimum Double-Precision */
4735 case 200: /* VSX Vector Minimum Single-Precision */
4736 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
4737 case 121: /* ditto */
4738 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
4739 case 89: /* ditto */
4740 case 112: /* VSX Vector Multiply Double-Precision */
4741 case 80: /* VSX Vector Multiply Single-Precision */
4742 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
4743 case 233: /* ditto */
4744 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
4745 case 201: /* ditto */
4746 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
4747 case 249: /* ditto */
4748 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
4749 case 217: /* ditto */
4750 case 104: /* VSX Vector Subtract Double-Precision */
4751 case 72: /* VSX Vector Subtract Single-Precision */
4752 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4753 case 240: /* VSX Vector Copy Sign Double-Precision */
4754 case 208: /* VSX Vector Copy Sign Single-Precision */
4755 case 130: /* VSX Logical AND */
4756 case 138: /* VSX Logical AND with Complement */
4757 case 186: /* VSX Logical Equivalence */
4758 case 178: /* VSX Logical NAND */
4759 case 170: /* VSX Logical OR with Complement */
4760 case 162: /* VSX Logical NOR */
4761 case 146: /* VSX Logical OR */
4762 case 154: /* VSX Logical XOR */
4763 case 18: /* VSX Merge High Word */
4764 case 50: /* VSX Merge Low Word */
4765 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
4766 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
4767 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
4768 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
4769 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
4770 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
4771 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
4772 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
4773 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4776 case 61: /* VSX Scalar Test for software Divide Double-Precision */
4777 case 125: /* VSX Vector Test for software Divide Double-Precision */
4778 case 93: /* VSX Vector Test for software Divide Single-Precision */
4779 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4782 case 35: /* VSX Scalar Compare Unordered Double-Precision */
4783 case 43: /* VSX Scalar Compare Ordered Double-Precision */
4784 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4785 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4789 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
4791 case 99: /* VSX Vector Compare Equal To Double-Precision */
4792 case 67: /* VSX Vector Compare Equal To Single-Precision */
4793 case 115: /* VSX Vector Compare Greater Than or
4794 Equal To Double-Precision */
4795 case 83: /* VSX Vector Compare Greater Than or
4796 Equal To Single-Precision */
4797 case 107: /* VSX Vector Compare Greater Than Double-Precision */
4798 case 75: /* VSX Vector Compare Greater Than Single-Precision */
4800 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4801 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4802 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4808 case 265: /* VSX Scalar round Double-Precision to
4809 Single-Precision and Convert to
4810 Single-Precision format */
4811 case 344: /* VSX Scalar truncate Double-Precision to
4812 Integer and Convert to Signed Integer
4813 Doubleword format with Saturate */
4814 case 88: /* VSX Scalar truncate Double-Precision to
4815 Integer and Convert to Signed Integer Word
4816 Format with Saturate */
4817 case 328: /* VSX Scalar truncate Double-Precision integer
4818 and Convert to Unsigned Integer Doubleword
4819 Format with Saturate */
4820 case 72: /* VSX Scalar truncate Double-Precision to
4821 Integer and Convert to Unsigned Integer Word
4822 Format with Saturate */
4823 case 329: /* VSX Scalar Convert Single-Precision to
4824 Double-Precision format */
4825 case 376: /* VSX Scalar Convert Signed Integer
4826 Doubleword to floating-point format and
4827 Round to Double-Precision format */
4828 case 312: /* VSX Scalar Convert Signed Integer
4829 Doubleword to floating-point format and
4830 round to Single-Precision */
4831 case 360: /* VSX Scalar Convert Unsigned Integer
4832 Doubleword to floating-point format and
4833 Round to Double-Precision format */
4834 case 296: /* VSX Scalar Convert Unsigned Integer
4835 Doubleword to floating-point format and
4836 Round to Single-Precision */
4837 case 73: /* VSX Scalar Round to Double-Precision Integer
4838 Using Round to Nearest Away */
4839 case 107: /* VSX Scalar Round to Double-Precision Integer
4840 Exact using Current rounding mode */
4841 case 121: /* VSX Scalar Round to Double-Precision Integer
4842 Using Round toward -Infinity */
4843 case 105: /* VSX Scalar Round to Double-Precision Integer
4844 Using Round toward +Infinity */
4845 case 89: /* VSX Scalar Round to Double-Precision Integer
4846 Using Round toward Zero */
4847 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
4848 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
4849 case 281: /* VSX Scalar Round to Single-Precision */
4850 case 74: /* VSX Scalar Reciprocal Square Root Estimate
4852 case 10: /* VSX Scalar Reciprocal Square Root Estimate
4854 case 75: /* VSX Scalar Square Root Double-Precision */
4855 case 11: /* VSX Scalar Square Root Single-Precision */
4856 case 393: /* VSX Vector round Double-Precision to
4857 Single-Precision and Convert to
4858 Single-Precision format */
4859 case 472: /* VSX Vector truncate Double-Precision to
4860 Integer and Convert to Signed Integer
4861 Doubleword format with Saturate */
4862 case 216: /* VSX Vector truncate Double-Precision to
4863 Integer and Convert to Signed Integer Word
4864 Format with Saturate */
4865 case 456: /* VSX Vector truncate Double-Precision to
4866 Integer and Convert to Unsigned Integer
4867 Doubleword format with Saturate */
4868 case 200: /* VSX Vector truncate Double-Precision to
4869 Integer and Convert to Unsigned Integer Word
4870 Format with Saturate */
4871 case 457: /* VSX Vector Convert Single-Precision to
4872 Double-Precision format */
4873 case 408: /* VSX Vector truncate Single-Precision to
4874 Integer and Convert to Signed Integer
4875 Doubleword format with Saturate */
4876 case 152: /* VSX Vector truncate Single-Precision to
4877 Integer and Convert to Signed Integer Word
4878 Format with Saturate */
4879 case 392: /* VSX Vector truncate Single-Precision to
4880 Integer and Convert to Unsigned Integer
4881 Doubleword format with Saturate */
4882 case 136: /* VSX Vector truncate Single-Precision to
4883 Integer and Convert to Unsigned Integer Word
4884 Format with Saturate */
4885 case 504: /* VSX Vector Convert and round Signed Integer
4886 Doubleword to Double-Precision format */
4887 case 440: /* VSX Vector Convert and round Signed Integer
4888 Doubleword to Single-Precision format */
4889 case 248: /* VSX Vector Convert Signed Integer Word to
4890 Double-Precision format */
4891 case 184: /* VSX Vector Convert and round Signed Integer
4892 Word to Single-Precision format */
4893 case 488: /* VSX Vector Convert and round Unsigned
4894 Integer Doubleword to Double-Precision format */
4895 case 424: /* VSX Vector Convert and round Unsigned
4896 Integer Doubleword to Single-Precision format */
4897 case 232: /* VSX Vector Convert and round Unsigned
4898 Integer Word to Double-Precision format */
4899 case 168: /* VSX Vector Convert and round Unsigned
4900 Integer Word to Single-Precision format */
4901 case 201: /* VSX Vector Round to Double-Precision
4902 Integer using round to Nearest Away */
4903 case 235: /* VSX Vector Round to Double-Precision
4904 Integer Exact using Current rounding mode */
4905 case 249: /* VSX Vector Round to Double-Precision
4906 Integer using round toward -Infinity */
4907 case 233: /* VSX Vector Round to Double-Precision
4908 Integer using round toward +Infinity */
4909 case 217: /* VSX Vector Round to Double-Precision
4910 Integer using round toward Zero */
4911 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
4912 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
4913 case 137: /* VSX Vector Round to Single-Precision Integer
4914 Using Round to Nearest Away */
4915 case 171: /* VSX Vector Round to Single-Precision Integer
4916 Exact Using Current rounding mode */
4917 case 185: /* VSX Vector Round to Single-Precision Integer
4918 Using Round toward -Infinity */
4919 case 169: /* VSX Vector Round to Single-Precision Integer
4920 Using Round toward +Infinity */
4921 case 153: /* VSX Vector Round to Single-Precision Integer
4922 Using round toward Zero */
4923 case 202: /* VSX Vector Reciprocal Square Root Estimate
4925 case 138: /* VSX Vector Reciprocal Square Root Estimate
4927 case 203: /* VSX Vector Square Root Double-Precision */
4928 case 139: /* VSX Vector Square Root Single-Precision */
4929 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4930 case 345: /* VSX Scalar Absolute Value Double-Precision */
4931 case 267: /* VSX Scalar Convert Scalar Single-Precision to
4932 Vector Single-Precision format Non-signalling */
4933 case 331: /* VSX Scalar Convert Single-Precision to
4934 Double-Precision format Non-signalling */
4935 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
4936 case 377: /* VSX Scalar Negate Double-Precision */
4937 case 473: /* VSX Vector Absolute Value Double-Precision */
4938 case 409: /* VSX Vector Absolute Value Single-Precision */
4939 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
4940 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
4941 case 505: /* VSX Vector Negate Double-Precision */
4942 case 441: /* VSX Vector Negate Single-Precision */
4943 case 164: /* VSX Splat Word */
4944 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4947 case 106: /* VSX Scalar Test for software Square Root
4949 case 234: /* VSX Vector Test for software Square Root
4951 case 170: /* VSX Vector Test for software Square Root
4953 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4957 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
4959 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4963 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4964 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4968 /* Parse and record instructions of primary opcode-63 at ADDR.
4969 Return 0 if successful. */
4972 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4973 CORE_ADDR addr
, uint32_t insn
)
4975 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4976 int ext
= PPC_EXTOP (insn
);
4981 case 18: /* Floating Divide */
4982 case 20: /* Floating Subtract */
4983 case 21: /* Floating Add */
4984 case 22: /* Floating Square Root */
4985 case 24: /* Floating Reciprocal Estimate */
4986 case 25: /* Floating Multiply */
4987 case 26: /* Floating Reciprocal Square Root Estimate */
4988 case 28: /* Floating Multiply-Subtract */
4989 case 29: /* Floating Multiply-Add */
4990 case 30: /* Floating Negative Multiply-Subtract */
4991 case 31: /* Floating Negative Multiply-Add */
4992 record_full_arch_list_add_reg (regcache
,
4993 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4995 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4996 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4999 case 23: /* Floating Select */
5000 record_full_arch_list_add_reg (regcache
,
5001 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5003 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5008 case 2: /* DFP Add Quad */
5009 case 3: /* DFP Quantize Quad */
5010 case 34: /* DFP Multiply Quad */
5011 case 35: /* DFP Reround Quad */
5012 case 67: /* DFP Quantize Immediate Quad */
5013 case 99: /* DFP Round To FP Integer With Inexact Quad */
5014 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5015 case 258: /* DFP Convert To DFP Extended Quad */
5016 case 514: /* DFP Subtract Quad */
5017 case 546: /* DFP Divide Quad */
5018 case 770: /* DFP Round To DFP Long Quad */
5019 case 802: /* DFP Convert From Fixed Quad */
5020 case 834: /* DFP Encode BCD To DPD Quad */
5022 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5023 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5024 record_full_arch_list_add_reg (regcache
, tmp
);
5025 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5026 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5029 case 130: /* DFP Compare Ordered Quad */
5030 case 162: /* DFP Test Exponent Quad */
5031 case 194: /* DFP Test Data Class Quad */
5032 case 226: /* DFP Test Data Group Quad */
5033 case 642: /* DFP Compare Unordered Quad */
5034 case 674: /* DFP Test Significance Quad */
5035 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5036 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5039 case 66: /* DFP Shift Significand Left Immediate Quad */
5040 case 98: /* DFP Shift Significand Right Immediate Quad */
5041 case 322: /* DFP Decode DPD To BCD Quad */
5042 case 866: /* DFP Insert Biased Exponent Quad */
5043 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5044 record_full_arch_list_add_reg (regcache
, tmp
);
5045 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5047 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5050 case 290: /* DFP Convert To Fixed Quad */
5051 record_full_arch_list_add_reg (regcache
,
5052 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5054 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5055 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5058 case 354: /* DFP Extract Biased Exponent Quad */
5059 record_full_arch_list_add_reg (regcache
,
5060 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5062 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5065 case 12: /* Floating Round to Single-Precision */
5066 case 14: /* Floating Convert To Integer Word */
5067 case 15: /* Floating Convert To Integer Word
5068 with round toward Zero */
5069 case 142: /* Floating Convert To Integer Word Unsigned */
5070 case 143: /* Floating Convert To Integer Word Unsigned
5071 with round toward Zero */
5072 case 392: /* Floating Round to Integer Nearest */
5073 case 424: /* Floating Round to Integer Toward Zero */
5074 case 456: /* Floating Round to Integer Plus */
5075 case 488: /* Floating Round to Integer Minus */
5076 case 814: /* Floating Convert To Integer Doubleword */
5077 case 815: /* Floating Convert To Integer Doubleword
5078 with round toward Zero */
5079 case 846: /* Floating Convert From Integer Doubleword */
5080 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5081 case 943: /* Floating Convert To Integer Doubleword Unsigned
5082 with round toward Zero */
5083 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5084 record_full_arch_list_add_reg (regcache
,
5085 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5087 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5088 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5091 case 583: /* Move From FPSCR */
5092 case 8: /* Floating Copy Sign */
5093 case 40: /* Floating Negate */
5094 case 72: /* Floating Move Register */
5095 case 136: /* Floating Negative Absolute Value */
5096 case 264: /* Floating Absolute Value */
5097 record_full_arch_list_add_reg (regcache
,
5098 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5100 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5103 case 838: /* Floating Merge Odd Word */
5104 case 966: /* Floating Merge Even Word */
5105 record_full_arch_list_add_reg (regcache
,
5106 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5109 case 38: /* Move To FPSCR Bit 1 */
5110 case 70: /* Move To FPSCR Bit 0 */
5111 case 134: /* Move To FPSCR Field Immediate */
5112 case 711: /* Move To FPSCR Fields */
5114 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5115 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5118 case 0: /* Floating Compare Unordered */
5119 case 32: /* Floating Compare Ordered */
5120 case 64: /* Move to Condition Register from FPSCR */
5121 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5123 case 128: /* Floating Test for software Divide */
5124 case 160: /* Floating Test for software Square Root */
5125 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5130 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5131 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5135 /* Parse the current instruction and record the values of the registers and
5136 memory that will be changed in current instruction to "record_arch_list".
5137 Return -1 if something wrong. */
5140 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5143 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5144 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5148 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5149 op6
= PPC_OP6 (insn
);
5153 case 2: /* Trap Doubleword Immediate */
5154 case 3: /* Trap Word Immediate */
5159 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5163 case 17: /* System call */
5164 if (PPC_LEV (insn
) != 0)
5167 if (tdep
->ppc_syscall_record
!= NULL
)
5169 if (tdep
->ppc_syscall_record (regcache
) != 0)
5174 printf_unfiltered (_("no syscall record support\n"));
5179 case 7: /* Multiply Low Immediate */
5180 record_full_arch_list_add_reg (regcache
,
5181 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5184 case 8: /* Subtract From Immediate Carrying */
5185 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5186 record_full_arch_list_add_reg (regcache
,
5187 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5190 case 10: /* Compare Logical Immediate */
5191 case 11: /* Compare Immediate */
5192 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5195 case 13: /* Add Immediate Carrying and Record */
5196 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5198 case 12: /* Add Immediate Carrying */
5199 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5201 case 14: /* Add Immediate */
5202 case 15: /* Add Immediate Shifted */
5203 record_full_arch_list_add_reg (regcache
,
5204 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5207 case 16: /* Branch Conditional */
5208 if ((PPC_BO (insn
) & 0x4) == 0)
5209 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5211 case 18: /* Branch */
5213 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5217 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5221 case 20: /* Rotate Left Word Immediate then Mask Insert */
5222 case 21: /* Rotate Left Word Immediate then AND with Mask */
5223 case 23: /* Rotate Left Word then AND with Mask */
5224 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5225 /* Rotate Left Doubleword Immediate then Clear Right */
5226 /* Rotate Left Doubleword Immediate then Clear */
5227 /* Rotate Left Doubleword then Clear Left */
5228 /* Rotate Left Doubleword then Clear Right */
5229 /* Rotate Left Doubleword Immediate then Mask Insert */
5231 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5232 record_full_arch_list_add_reg (regcache
,
5233 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5236 case 28: /* AND Immediate */
5237 case 29: /* AND Immediate Shifted */
5238 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5240 case 24: /* OR Immediate */
5241 case 25: /* OR Immediate Shifted */
5242 case 26: /* XOR Immediate */
5243 case 27: /* XOR Immediate Shifted */
5244 record_full_arch_list_add_reg (regcache
,
5245 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5249 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5253 case 33: /* Load Word and Zero with Update */
5254 case 35: /* Load Byte and Zero with Update */
5255 case 41: /* Load Halfword and Zero with Update */
5256 case 43: /* Load Halfword Algebraic with Update */
5257 record_full_arch_list_add_reg (regcache
,
5258 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5260 case 32: /* Load Word and Zero */
5261 case 34: /* Load Byte and Zero */
5262 case 40: /* Load Halfword and Zero */
5263 case 42: /* Load Halfword Algebraic */
5264 record_full_arch_list_add_reg (regcache
,
5265 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5268 case 46: /* Load Multiple Word */
5269 for (i
= PPC_RT (insn
); i
< 32; i
++)
5270 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5273 case 56: /* Load Quadword */
5274 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5275 record_full_arch_list_add_reg (regcache
, tmp
);
5276 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5279 case 49: /* Load Floating-Point Single with Update */
5280 case 51: /* Load Floating-Point Double with Update */
5281 record_full_arch_list_add_reg (regcache
,
5282 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5284 case 48: /* Load Floating-Point Single */
5285 case 50: /* Load Floating-Point Double */
5286 record_full_arch_list_add_reg (regcache
,
5287 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5290 case 47: /* Store Multiple Word */
5294 if (PPC_RA (insn
) != 0)
5295 regcache_raw_read_unsigned (regcache
,
5296 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5299 addr
+= PPC_D (insn
);
5300 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5304 case 37: /* Store Word with Update */
5305 case 39: /* Store Byte with Update */
5306 case 45: /* Store Halfword with Update */
5307 case 53: /* Store Floating-Point Single with Update */
5308 case 55: /* Store Floating-Point Double with Update */
5309 record_full_arch_list_add_reg (regcache
,
5310 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5312 case 36: /* Store Word */
5313 case 38: /* Store Byte */
5314 case 44: /* Store Halfword */
5315 case 52: /* Store Floating-Point Single */
5316 case 54: /* Store Floating-Point Double */
5321 if (PPC_RA (insn
) != 0)
5322 regcache_raw_read_unsigned (regcache
,
5323 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5325 addr
+= PPC_D (insn
);
5327 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5329 else if (op6
== 54 || op6
== 55)
5331 else if (op6
== 44 || op6
== 45)
5333 else if (op6
== 38 || op6
== 39)
5338 record_full_arch_list_add_mem (addr
, size
);
5342 case 57: /* Load Floating-Point Double Pair */
5343 if (PPC_FIELD (insn
, 30, 2) != 0)
5345 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5346 record_full_arch_list_add_reg (regcache
, tmp
);
5347 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5350 case 58: /* Load Doubleword */
5351 /* Load Doubleword with Update */
5352 /* Load Word Algebraic */
5353 if (PPC_FIELD (insn
, 30, 2) > 2)
5356 record_full_arch_list_add_reg (regcache
,
5357 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5358 if (PPC_BIT (insn
, 31))
5359 record_full_arch_list_add_reg (regcache
,
5360 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5364 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5369 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5373 case 61: /* Store Floating-Point Double Pair */
5374 case 62: /* Store Doubleword */
5375 /* Store Doubleword with Update */
5376 /* Store Quadword with Update */
5380 int sub2
= PPC_FIELD (insn
, 30, 2);
5382 if ((op6
== 61 && sub2
!= 0) || (op6
== 62 && sub2
> 2))
5385 if (PPC_RA (insn
) != 0)
5386 regcache_raw_read_unsigned (regcache
,
5387 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5390 size
= ((op6
== 61) || sub2
== 2) ? 16 : 8;
5392 addr
+= PPC_DS (insn
) << 2;
5393 record_full_arch_list_add_mem (addr
, size
);
5395 if (op6
== 62 && sub2
== 1)
5396 record_full_arch_list_add_reg (regcache
,
5397 tdep
->ppc_gp0_regnum
+
5404 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5410 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5411 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5415 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5417 if (record_full_arch_list_add_end ())
5422 /* Initialize the current architecture based on INFO. If possible, re-use an
5423 architecture from ARCHES, which is a list of architectures already created
5424 during this debugging session.
5426 Called e.g. at program startup, when reading a core file, and when reading
5429 static struct gdbarch
*
5430 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5432 struct gdbarch
*gdbarch
;
5433 struct gdbarch_tdep
*tdep
;
5434 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5435 enum bfd_architecture arch
;
5438 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5440 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5441 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5442 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
5444 int tdesc_wordsize
= -1;
5445 const struct target_desc
*tdesc
= info
.target_desc
;
5446 struct tdesc_arch_data
*tdesc_data
= NULL
;
5447 int num_pseudoregs
= 0;
5450 /* INFO may refer to a binary that is not of the PowerPC architecture,
5451 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5452 In this case, we must not attempt to infer properties of the (PowerPC
5453 side) of the target system from properties of that executable. Trust
5454 the target description instead. */
5456 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5457 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5460 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5461 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5463 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5464 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5466 /* Check word size. If INFO is from a binary file, infer it from
5467 that, else choose a likely default. */
5468 if (from_xcoff_exec
)
5470 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5475 else if (from_elf_exec
)
5477 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5482 else if (tdesc_has_registers (tdesc
))
5486 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
5487 wordsize
= (info
.bfd_arch_info
->bits_per_word
5488 / info
.bfd_arch_info
->bits_per_byte
);
5493 /* Get the architecture and machine from the BFD. */
5494 arch
= info
.bfd_arch_info
->arch
;
5495 mach
= info
.bfd_arch_info
->mach
;
5497 /* For e500 executables, the apuinfo section is of help here. Such
5498 section contains the identifier and revision number of each
5499 Application-specific Processing Unit that is present on the
5500 chip. The content of the section is determined by the assembler
5501 which looks at each instruction and determines which unit (and
5502 which version of it) can execute it. Grovel through the section
5503 looking for relevant e500 APUs. */
5505 if (bfd_uses_spe_extensions (info
.abfd
))
5507 arch
= info
.bfd_arch_info
->arch
;
5508 mach
= bfd_mach_ppc_e500
;
5509 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
5510 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
5513 /* Find a default target description which describes our register
5514 layout, if we do not already have one. */
5515 if (! tdesc_has_registers (tdesc
))
5517 const struct variant
*v
;
5519 /* Choose variant. */
5520 v
= find_variant_by_arch (arch
, mach
);
5527 gdb_assert (tdesc_has_registers (tdesc
));
5529 /* Check any target description for validity. */
5530 if (tdesc_has_registers (tdesc
))
5532 static const char *const gprs
[] = {
5533 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5534 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5535 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5536 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5538 const struct tdesc_feature
*feature
;
5540 static const char *const msr_names
[] = { "msr", "ps" };
5541 static const char *const cr_names
[] = { "cr", "cnd" };
5542 static const char *const ctr_names
[] = { "ctr", "cnt" };
5544 feature
= tdesc_find_feature (tdesc
,
5545 "org.gnu.gdb.power.core");
5546 if (feature
== NULL
)
5549 tdesc_data
= tdesc_data_alloc ();
5552 for (i
= 0; i
< ppc_num_gprs
; i
++)
5553 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
5554 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
5556 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
5558 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
5561 /* Allow alternate names for these registers, to accomodate GDB's
5563 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5564 PPC_MSR_REGNUM
, msr_names
);
5565 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5566 PPC_CR_REGNUM
, cr_names
);
5567 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
5568 PPC_CTR_REGNUM
, ctr_names
);
5572 tdesc_data_cleanup (tdesc_data
);
5576 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
5579 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
5581 wordsize
= tdesc_wordsize
;
5583 feature
= tdesc_find_feature (tdesc
,
5584 "org.gnu.gdb.power.fpu");
5585 if (feature
!= NULL
)
5587 static const char *const fprs
[] = {
5588 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5589 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5590 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5591 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
5594 for (i
= 0; i
< ppc_num_fprs
; i
++)
5595 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5596 PPC_F0_REGNUM
+ i
, fprs
[i
]);
5597 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5598 PPC_FPSCR_REGNUM
, "fpscr");
5602 tdesc_data_cleanup (tdesc_data
);
5610 /* The DFP pseudo-registers will be available when there are floating
5612 have_dfp
= have_fpu
;
5614 feature
= tdesc_find_feature (tdesc
,
5615 "org.gnu.gdb.power.altivec");
5616 if (feature
!= NULL
)
5618 static const char *const vector_regs
[] = {
5619 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
5620 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
5621 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
5622 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
5626 for (i
= 0; i
< ppc_num_gprs
; i
++)
5627 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5630 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5631 PPC_VSCR_REGNUM
, "vscr");
5632 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5633 PPC_VRSAVE_REGNUM
, "vrsave");
5635 if (have_spe
|| !valid_p
)
5637 tdesc_data_cleanup (tdesc_data
);
5645 /* Check for POWER7 VSX registers support. */
5646 feature
= tdesc_find_feature (tdesc
,
5647 "org.gnu.gdb.power.vsx");
5649 if (feature
!= NULL
)
5651 static const char *const vsx_regs
[] = {
5652 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
5653 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
5654 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
5655 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
5656 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
5662 for (i
= 0; i
< ppc_num_vshrs
; i
++)
5663 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5664 PPC_VSR0_UPPER_REGNUM
+ i
,
5668 tdesc_data_cleanup (tdesc_data
);
5677 /* On machines supporting the SPE APU, the general-purpose registers
5678 are 64 bits long. There are SIMD vector instructions to treat them
5679 as pairs of floats, but the rest of the instruction set treats them
5680 as 32-bit registers, and only operates on their lower halves.
5682 In the GDB regcache, we treat their high and low halves as separate
5683 registers. The low halves we present as the general-purpose
5684 registers, and then we have pseudo-registers that stitch together
5685 the upper and lower halves and present them as pseudo-registers.
5687 Thus, the target description is expected to supply the upper
5688 halves separately. */
5690 feature
= tdesc_find_feature (tdesc
,
5691 "org.gnu.gdb.power.spe");
5692 if (feature
!= NULL
)
5694 static const char *const upper_spe
[] = {
5695 "ev0h", "ev1h", "ev2h", "ev3h",
5696 "ev4h", "ev5h", "ev6h", "ev7h",
5697 "ev8h", "ev9h", "ev10h", "ev11h",
5698 "ev12h", "ev13h", "ev14h", "ev15h",
5699 "ev16h", "ev17h", "ev18h", "ev19h",
5700 "ev20h", "ev21h", "ev22h", "ev23h",
5701 "ev24h", "ev25h", "ev26h", "ev27h",
5702 "ev28h", "ev29h", "ev30h", "ev31h"
5706 for (i
= 0; i
< ppc_num_gprs
; i
++)
5707 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5708 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
5710 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5711 PPC_SPE_ACC_REGNUM
, "acc");
5712 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5713 PPC_SPE_FSCR_REGNUM
, "spefscr");
5715 if (have_mq
|| have_fpu
|| !valid_p
)
5717 tdesc_data_cleanup (tdesc_data
);
5726 /* If we have a 64-bit binary on a 32-bit target, complain. Also
5727 complain for a 32-bit binary on a 64-bit target; we do not yet
5728 support that. For instance, the 32-bit ABI routines expect
5731 As long as there isn't an explicit target description, we'll
5732 choose one based on the BFD architecture and get a word size
5733 matching the binary (probably powerpc:common or
5734 powerpc:common64). So there is only trouble if a 64-bit target
5735 supplies a 64-bit description while debugging a 32-bit
5737 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
5739 tdesc_data_cleanup (tdesc_data
);
5746 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
5749 elf_abi
= POWERPC_ELF_V1
;
5752 elf_abi
= POWERPC_ELF_V2
;
5759 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
5761 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5762 Tag_GNU_Power_ABI_FP
))
5765 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
5768 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
5775 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
5777 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5778 Tag_GNU_Power_ABI_Vector
))
5781 vector_abi
= POWERPC_VEC_GENERIC
;
5784 vector_abi
= POWERPC_VEC_ALTIVEC
;
5787 vector_abi
= POWERPC_VEC_SPE
;
5795 /* At this point, the only supported ELF-based 64-bit little-endian
5796 operating system is GNU/Linux, and this uses the ELFv2 ABI by
5797 default. All other supported ELF-based operating systems use the
5798 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
5799 e.g. because we run a legacy binary, or have attached to a process
5800 and have not found any associated binary file, set the default
5801 according to this heuristic. */
5802 if (elf_abi
== POWERPC_ELF_AUTO
)
5804 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
5805 elf_abi
= POWERPC_ELF_V2
;
5807 elf_abi
= POWERPC_ELF_V1
;
5810 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
5812 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
5815 soft_float
= !have_fpu
;
5817 /* If we have a hard float binary or setting but no floating point
5818 registers, downgrade to soft float anyway. We're still somewhat
5819 useful in this scenario. */
5820 if (!soft_float
&& !have_fpu
)
5823 /* Similarly for vector registers. */
5824 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
5825 vector_abi
= POWERPC_VEC_GENERIC
;
5827 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
5828 vector_abi
= POWERPC_VEC_GENERIC
;
5830 if (vector_abi
== POWERPC_VEC_AUTO
)
5833 vector_abi
= POWERPC_VEC_ALTIVEC
;
5835 vector_abi
= POWERPC_VEC_SPE
;
5837 vector_abi
= POWERPC_VEC_GENERIC
;
5840 /* Do not limit the vector ABI based on available hardware, since we
5841 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
5843 /* Find a candidate among extant architectures. */
5844 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5846 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5848 /* Word size in the various PowerPC bfd_arch_info structs isn't
5849 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
5850 separate word size check. */
5851 tdep
= gdbarch_tdep (arches
->gdbarch
);
5852 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
5854 if (tdep
&& tdep
->soft_float
!= soft_float
)
5856 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
5858 if (tdep
&& tdep
->wordsize
== wordsize
)
5860 if (tdesc_data
!= NULL
)
5861 tdesc_data_cleanup (tdesc_data
);
5862 return arches
->gdbarch
;
5866 /* None found, create a new architecture from INFO, whose bfd_arch_info
5867 validity depends on the source:
5868 - executable useless
5869 - rs6000_host_arch() good
5871 - "set arch" trust blindly
5872 - GDB startup useless but harmless */
5874 tdep
= XCNEW (struct gdbarch_tdep
);
5875 tdep
->wordsize
= wordsize
;
5876 tdep
->elf_abi
= elf_abi
;
5877 tdep
->soft_float
= soft_float
;
5878 tdep
->vector_abi
= vector_abi
;
5880 gdbarch
= gdbarch_alloc (&info
, tdep
);
5882 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
5883 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
5884 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
5885 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
5886 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
5887 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
5888 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
5889 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
5891 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
5892 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
5893 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
5894 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
5895 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
5896 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
5897 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
5898 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
5900 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
5901 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
5902 set_gdbarch_deprecated_fp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
5903 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
5904 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
5906 /* The XML specification for PowerPC sensibly calls the MSR "msr".
5907 GDB traditionally called it "ps", though, so let GDB add an
5909 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
5912 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
5914 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
5916 /* Set lr_frame_offset. */
5918 tdep
->lr_frame_offset
= 16;
5920 tdep
->lr_frame_offset
= 4;
5922 if (have_spe
|| have_dfp
|| have_vsx
)
5924 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
5925 set_gdbarch_pseudo_register_write (gdbarch
,
5926 rs6000_pseudo_register_write
);
5929 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5931 /* Select instruction printer. */
5932 if (arch
== bfd_arch_rs6000
)
5933 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
5935 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
5937 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
5940 num_pseudoregs
+= 32;
5942 num_pseudoregs
+= 16;
5944 /* Include both VSX and Extended FP registers. */
5945 num_pseudoregs
+= 96;
5947 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
5949 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
5950 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
5951 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
5952 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
5953 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
5954 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
5955 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
5956 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
5957 set_gdbarch_char_signed (gdbarch
, 0);
5959 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
5962 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
5964 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
5965 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
5966 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
5968 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
5969 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
5972 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
5973 else if (wordsize
== 8)
5974 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
5976 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
5977 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
5978 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
5980 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5981 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
5983 /* The value of symbols of type N_SO and N_FUN maybe null when
5985 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
5987 /* Handles single stepping of atomic sequences. */
5988 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
5990 /* Not sure on this. FIXMEmgo */
5991 set_gdbarch_frame_args_skip (gdbarch
, 8);
5993 /* Helpers for function argument information. */
5994 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
5997 set_gdbarch_in_solib_return_trampoline
5998 (gdbarch
, rs6000_in_solib_return_trampoline
);
5999 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6001 /* Hook in the DWARF CFI frame unwinder. */
6002 dwarf2_append_unwinders (gdbarch
);
6003 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6005 /* Frame handling. */
6006 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6008 /* Setup displaced stepping. */
6009 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6010 ppc_displaced_step_copy_insn
);
6011 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6012 ppc_displaced_step_hw_singlestep
);
6013 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6014 set_gdbarch_displaced_step_free_closure (gdbarch
,
6015 simple_displaced_step_free_closure
);
6016 set_gdbarch_displaced_step_location (gdbarch
,
6017 displaced_step_at_entry_point
);
6019 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6021 /* Hook in ABI-specific overrides, if they have been registered. */
6022 info
.target_desc
= tdesc
;
6023 info
.tdep_info
= tdesc_data
;
6024 gdbarch_init_osabi (info
, gdbarch
);
6028 case GDB_OSABI_LINUX
:
6029 case GDB_OSABI_NETBSD_AOUT
:
6030 case GDB_OSABI_NETBSD_ELF
:
6031 case GDB_OSABI_UNKNOWN
:
6032 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6033 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6034 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6035 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6036 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6039 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6041 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6042 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6043 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6044 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6045 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6048 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6049 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6050 rs6000_pseudo_register_reggroup_p
);
6051 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6053 /* Override the normal target description method to make the SPE upper
6054 halves anonymous. */
6055 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6057 /* Choose register numbers for all supported pseudo-registers. */
6058 tdep
->ppc_ev0_regnum
= -1;
6059 tdep
->ppc_dl0_regnum
= -1;
6060 tdep
->ppc_vsr0_regnum
= -1;
6061 tdep
->ppc_efpr0_regnum
= -1;
6063 cur_reg
= gdbarch_num_regs (gdbarch
);
6067 tdep
->ppc_ev0_regnum
= cur_reg
;
6072 tdep
->ppc_dl0_regnum
= cur_reg
;
6077 tdep
->ppc_vsr0_regnum
= cur_reg
;
6079 tdep
->ppc_efpr0_regnum
= cur_reg
;
6083 gdb_assert (gdbarch_num_regs (gdbarch
)
6084 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
6086 /* Register the ravenscar_arch_ops. */
6087 if (mach
== bfd_mach_ppc_e500
)
6088 register_e500_ravenscar_ops (gdbarch
);
6090 register_ppc_ravenscar_ops (gdbarch
);
6096 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6098 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6103 /* FIXME: Dump gdbarch_tdep. */
6106 /* PowerPC-specific commands. */
6109 set_powerpc_command (char *args
, int from_tty
)
6111 printf_unfiltered (_("\
6112 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6113 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6117 show_powerpc_command (char *args
, int from_tty
)
6119 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6123 powerpc_set_soft_float (char *args
, int from_tty
,
6124 struct cmd_list_element
*c
)
6126 struct gdbarch_info info
;
6128 /* Update the architecture. */
6129 gdbarch_info_init (&info
);
6130 if (!gdbarch_update_p (info
))
6131 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6135 powerpc_set_vector_abi (char *args
, int from_tty
,
6136 struct cmd_list_element
*c
)
6138 struct gdbarch_info info
;
6141 for (vector_abi
= POWERPC_VEC_AUTO
;
6142 vector_abi
!= POWERPC_VEC_LAST
;
6144 if (strcmp (powerpc_vector_abi_string
,
6145 powerpc_vector_strings
[vector_abi
]) == 0)
6147 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6151 if (vector_abi
== POWERPC_VEC_LAST
)
6152 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6153 powerpc_vector_abi_string
);
6155 /* Update the architecture. */
6156 gdbarch_info_init (&info
);
6157 if (!gdbarch_update_p (info
))
6158 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6161 /* Show the current setting of the exact watchpoints flag. */
6164 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6165 struct cmd_list_element
*c
,
6168 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6171 /* Read a PPC instruction from memory. */
6174 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6176 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6177 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6179 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6182 /* Return non-zero if the instructions at PC match the series
6183 described in PATTERN, or zero otherwise. PATTERN is an array of
6184 'struct ppc_insn_pattern' objects, terminated by an entry whose
6187 When the match is successful, fill INSN[i] with what PATTERN[i]
6188 matched. If PATTERN[i] is optional, and the instruction wasn't
6189 present, set INSN[i] to 0 (which is not a valid PPC instruction).
6190 INSN should have as many elements as PATTERN. Note that, if
6191 PATTERN contains optional instructions which aren't present in
6192 memory, then INSN will have holes, so INSN[i] isn't necessarily the
6193 i'th instruction in memory. */
6196 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6197 struct ppc_insn_pattern
*pattern
,
6198 unsigned int *insns
)
6203 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6206 insn
= read_insn (frame
, pc
);
6208 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6214 else if (!pattern
[i
].optional
)
6221 /* Return the 'd' field of the d-form instruction INSN, properly
6225 ppc_insn_d_field (unsigned int insn
)
6227 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6230 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6231 zero bits concatenated at the right, and properly
6235 ppc_insn_ds_field (unsigned int insn
)
6237 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6240 /* Initialization code. */
6242 /* -Wmissing-prototypes */
6243 extern initialize_file_ftype _initialize_rs6000_tdep
;
6246 _initialize_rs6000_tdep (void)
6248 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6249 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6251 /* Initialize the standard target descriptions. */
6252 initialize_tdesc_powerpc_32 ();
6253 initialize_tdesc_powerpc_altivec32 ();
6254 initialize_tdesc_powerpc_vsx32 ();
6255 initialize_tdesc_powerpc_403 ();
6256 initialize_tdesc_powerpc_403gc ();
6257 initialize_tdesc_powerpc_405 ();
6258 initialize_tdesc_powerpc_505 ();
6259 initialize_tdesc_powerpc_601 ();
6260 initialize_tdesc_powerpc_602 ();
6261 initialize_tdesc_powerpc_603 ();
6262 initialize_tdesc_powerpc_604 ();
6263 initialize_tdesc_powerpc_64 ();
6264 initialize_tdesc_powerpc_altivec64 ();
6265 initialize_tdesc_powerpc_vsx64 ();
6266 initialize_tdesc_powerpc_7400 ();
6267 initialize_tdesc_powerpc_750 ();
6268 initialize_tdesc_powerpc_860 ();
6269 initialize_tdesc_powerpc_e500 ();
6270 initialize_tdesc_rs6000 ();
6272 /* Add root prefix command for all "set powerpc"/"show powerpc"
6274 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6275 _("Various PowerPC-specific commands."),
6276 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6278 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6279 _("Various PowerPC-specific commands."),
6280 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6282 /* Add a command to allow the user to force the ABI. */
6283 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6284 &powerpc_soft_float_global
,
6285 _("Set whether to use a soft-float ABI."),
6286 _("Show whether to use a soft-float ABI."),
6288 powerpc_set_soft_float
, NULL
,
6289 &setpowerpccmdlist
, &showpowerpccmdlist
);
6291 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6292 &powerpc_vector_abi_string
,
6293 _("Set the vector ABI."),
6294 _("Show the vector ABI."),
6295 NULL
, powerpc_set_vector_abi
, NULL
,
6296 &setpowerpccmdlist
, &showpowerpccmdlist
);
6298 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6299 &target_exact_watchpoints
,
6301 Set whether to use just one debug register for watchpoints on scalars."),
6303 Show whether to use just one debug register for watchpoints on scalars."),
6305 If true, GDB will use only one debug register when watching a variable of\n\
6306 scalar type, thus assuming that the variable is accessed through the address\n\
6307 of its first byte."),
6308 NULL
, show_powerpc_exact_watchpoints
,
6309 &setpowerpccmdlist
, &showpowerpccmdlist
);