1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
42 #include "reggroups.h"
44 #include "libbfd.h" /* for bfd_default_set_arch_mach */
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
52 #include "solib-svr4.h"
55 #include "gdb_assert.h"
58 #include "trad-frame.h"
59 #include "frame-unwind.h"
60 #include "frame-base.h"
62 #include "reggroups.h"
63 #include "rs6000-tdep.h"
65 /* If the kernel has to deliver a signal, it pushes a sigcontext
66 structure on the stack and then calls the signal handler, passing
67 the address of the sigcontext in an argument register. Usually
68 the signal handler doesn't save this register, so we have to
69 access the sigcontext structure via an offset from the signal handler
71 The following constants were determined by experimentation on AIX 3.2. */
72 #define SIG_FRAME_PC_OFFSET 96
73 #define SIG_FRAME_LR_OFFSET 108
74 #define SIG_FRAME_FP_OFFSET 284
76 /* To be used by skip_prologue. */
78 struct rs6000_framedata
80 int offset
; /* total size of frame --- the distance
81 by which we decrement sp to allocate
83 int saved_gpr
; /* smallest # of saved gpr */
84 int saved_fpr
; /* smallest # of saved fpr */
85 int saved_vr
; /* smallest # of saved vr */
86 int saved_ev
; /* smallest # of saved ev */
87 int alloca_reg
; /* alloca register number (frame ptr) */
88 char frameless
; /* true if frameless functions. */
89 char nosavedpc
; /* true if pc not saved. */
90 int gpr_offset
; /* offset of saved gprs from prev sp */
91 int fpr_offset
; /* offset of saved fprs from prev sp */
92 int vr_offset
; /* offset of saved vrs from prev sp */
93 int ev_offset
; /* offset of saved evs from prev sp */
94 int lr_offset
; /* offset of saved lr */
95 int cr_offset
; /* offset of saved cr */
96 int vrsave_offset
; /* offset of saved vrsave register */
99 /* Description of a single register. */
103 char *name
; /* name of register */
104 unsigned char sz32
; /* size on 32-bit arch, 0 if nonexistent */
105 unsigned char sz64
; /* size on 64-bit arch, 0 if nonexistent */
106 unsigned char fpr
; /* whether register is floating-point */
107 unsigned char pseudo
; /* whether register is pseudo */
108 int spr_num
; /* PowerPC SPR number, or -1 if not an SPR.
109 This is an ISA SPR number, not a GDB
113 /* Breakpoint shadows for the single step instructions will be kept here. */
115 static struct sstep_breaks
117 /* Address, or 0 if this is not in use. */
119 /* Shadow contents. */
124 /* Hook for determining the TOC address when calling functions in the
125 inferior under AIX. The initialization code in rs6000-nat.c sets
126 this hook to point to find_toc_address. */
128 CORE_ADDR (*rs6000_find_toc_address_hook
) (CORE_ADDR
) = NULL
;
130 /* Hook to set the current architecture when starting a child process.
131 rs6000-nat.c sets this. */
133 void (*rs6000_set_host_arch_hook
) (int) = NULL
;
135 /* Static function prototypes */
137 static CORE_ADDR
branch_dest (int opcode
, int instr
, CORE_ADDR pc
,
139 static CORE_ADDR
skip_prologue (CORE_ADDR
, CORE_ADDR
,
140 struct rs6000_framedata
*);
142 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
144 altivec_register_p (int regno
)
146 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
147 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
150 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
154 /* Return true if REGNO is an SPE register, false otherwise. */
156 spe_register_p (int regno
)
158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
160 /* Is it a reference to EV0 -- EV31, and do we have those? */
161 if (tdep
->ppc_ev0_regnum
>= 0
162 && tdep
->ppc_ev31_regnum
>= 0
163 && tdep
->ppc_ev0_regnum
<= regno
&& regno
<= tdep
->ppc_ev31_regnum
)
166 /* Is it a reference to one of the raw upper GPR halves? */
167 if (tdep
->ppc_ev0_upper_regnum
>= 0
168 && tdep
->ppc_ev0_upper_regnum
<= regno
169 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
172 /* Is it a reference to the 64-bit accumulator, and do we have that? */
173 if (tdep
->ppc_acc_regnum
>= 0
174 && tdep
->ppc_acc_regnum
== regno
)
177 /* Is it a reference to the SPE floating-point status and control register,
178 and do we have that? */
179 if (tdep
->ppc_spefscr_regnum
>= 0
180 && tdep
->ppc_spefscr_regnum
== regno
)
187 /* Return non-zero if the architecture described by GDBARCH has
188 floating-point registers (f0 --- f31 and fpscr). */
190 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
192 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
194 return (tdep
->ppc_fp0_regnum
>= 0
195 && tdep
->ppc_fpscr_regnum
>= 0);
199 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
202 This is a helper function for init_sim_regno_table, constructing
203 the table mapping GDB register numbers to sim register numbers; we
204 initialize every element in that table to -1 before we start
207 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
209 /* Make sure we don't try to assign any given GDB register a sim
210 register number more than once. */
211 gdb_assert (table
[gdb_regno
] == -1);
212 table
[gdb_regno
] = sim_regno
;
216 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
217 numbers to simulator register numbers, based on the values placed
218 in the ARCH->tdep->ppc_foo_regnum members. */
220 init_sim_regno_table (struct gdbarch
*arch
)
222 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
223 int total_regs
= gdbarch_num_regs (arch
) + gdbarch_num_pseudo_regs (arch
);
224 const struct reg
*regs
= tdep
->regs
;
225 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
228 /* Presume that all registers not explicitly mentioned below are
229 unavailable from the sim. */
230 for (i
= 0; i
< total_regs
; i
++)
233 /* General-purpose registers. */
234 for (i
= 0; i
< ppc_num_gprs
; i
++)
235 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
237 /* Floating-point registers. */
238 if (tdep
->ppc_fp0_regnum
>= 0)
239 for (i
= 0; i
< ppc_num_fprs
; i
++)
240 set_sim_regno (sim_regno
,
241 tdep
->ppc_fp0_regnum
+ i
,
242 sim_ppc_f0_regnum
+ i
);
243 if (tdep
->ppc_fpscr_regnum
>= 0)
244 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
246 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
247 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
248 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
250 /* Segment registers. */
251 if (tdep
->ppc_sr0_regnum
>= 0)
252 for (i
= 0; i
< ppc_num_srs
; i
++)
253 set_sim_regno (sim_regno
,
254 tdep
->ppc_sr0_regnum
+ i
,
255 sim_ppc_sr0_regnum
+ i
);
257 /* Altivec registers. */
258 if (tdep
->ppc_vr0_regnum
>= 0)
260 for (i
= 0; i
< ppc_num_vrs
; i
++)
261 set_sim_regno (sim_regno
,
262 tdep
->ppc_vr0_regnum
+ i
,
263 sim_ppc_vr0_regnum
+ i
);
265 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
266 we can treat this more like the other cases. */
267 set_sim_regno (sim_regno
,
268 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
269 sim_ppc_vscr_regnum
);
271 /* vsave is a special-purpose register, so the code below handles it. */
273 /* SPE APU (E500) registers. */
274 if (tdep
->ppc_ev0_regnum
>= 0)
275 for (i
= 0; i
< ppc_num_gprs
; i
++)
276 set_sim_regno (sim_regno
,
277 tdep
->ppc_ev0_regnum
+ i
,
278 sim_ppc_ev0_regnum
+ i
);
279 if (tdep
->ppc_ev0_upper_regnum
>= 0)
280 for (i
= 0; i
< ppc_num_gprs
; i
++)
281 set_sim_regno (sim_regno
,
282 tdep
->ppc_ev0_upper_regnum
+ i
,
283 sim_ppc_rh0_regnum
+ i
);
284 if (tdep
->ppc_acc_regnum
>= 0)
285 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
286 /* spefscr is a special-purpose register, so the code below handles it. */
288 /* Now handle all special-purpose registers. Verify that they
289 haven't mistakenly been assigned numbers by any of the above
291 for (i
= 0; i
< total_regs
; i
++)
292 if (regs
[i
].spr_num
>= 0)
293 set_sim_regno (sim_regno
, i
, regs
[i
].spr_num
+ sim_ppc_spr0_regnum
);
295 /* Drop the initialized array into place. */
296 tdep
->sim_regno
= sim_regno
;
300 /* Given a GDB register number REG, return the corresponding SIM
303 rs6000_register_sim_regno (int reg
)
305 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
308 gdb_assert (0 <= reg
&& reg
<= NUM_REGS
+ NUM_PSEUDO_REGS
);
309 sim_regno
= tdep
->sim_regno
[reg
];
314 return LEGACY_SIM_REGNO_IGNORE
;
319 /* Register set support functions. */
322 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
323 const gdb_byte
*regs
, size_t offset
)
325 if (regnum
!= -1 && offset
!= -1)
326 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
330 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
331 gdb_byte
*regs
, size_t offset
)
333 if (regnum
!= -1 && offset
!= -1)
334 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
337 /* Supply register REGNUM in the general-purpose register set REGSET
338 from the buffer specified by GREGS and LEN to register cache
339 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
342 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
343 int regnum
, const void *gregs
, size_t len
)
345 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
346 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
347 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
351 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
352 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
355 if (regnum
== -1 || regnum
== i
)
356 ppc_supply_reg (regcache
, i
, gregs
, offset
);
359 if (regnum
== -1 || regnum
== PC_REGNUM
)
360 ppc_supply_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
361 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
362 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
363 gregs
, offsets
->ps_offset
);
364 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
365 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
366 gregs
, offsets
->cr_offset
);
367 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
368 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
369 gregs
, offsets
->lr_offset
);
370 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
371 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
372 gregs
, offsets
->ctr_offset
);
373 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
374 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
375 gregs
, offsets
->cr_offset
);
376 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
377 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
, gregs
, offsets
->mq_offset
);
380 /* Supply register REGNUM in the floating-point register set REGSET
381 from the buffer specified by FPREGS and LEN to register cache
382 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
385 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
386 int regnum
, const void *fpregs
, size_t len
)
388 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
389 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
390 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
394 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
396 offset
= offsets
->f0_offset
;
397 for (i
= tdep
->ppc_fp0_regnum
;
398 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
401 if (regnum
== -1 || regnum
== i
)
402 ppc_supply_reg (regcache
, i
, fpregs
, offset
);
405 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
406 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
407 fpregs
, offsets
->fpscr_offset
);
410 /* Collect register REGNUM in the general-purpose register set
411 REGSET. from register cache REGCACHE into the buffer specified by
412 GREGS and LEN. If REGNUM is -1, do this for all registers in
416 ppc_collect_gregset (const struct regset
*regset
,
417 const struct regcache
*regcache
,
418 int regnum
, void *gregs
, size_t len
)
420 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
421 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
422 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
426 offset
= offsets
->r0_offset
;
427 for (i
= tdep
->ppc_gp0_regnum
;
428 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
431 if (regnum
== -1 || regnum
== i
)
432 ppc_collect_reg (regcache
, i
, gregs
, offset
);
435 if (regnum
== -1 || regnum
== PC_REGNUM
)
436 ppc_collect_reg (regcache
, PC_REGNUM
, gregs
, offsets
->pc_offset
);
437 if (regnum
== -1 || regnum
== tdep
->ppc_ps_regnum
)
438 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
439 gregs
, offsets
->ps_offset
);
440 if (regnum
== -1 || regnum
== tdep
->ppc_cr_regnum
)
441 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
442 gregs
, offsets
->cr_offset
);
443 if (regnum
== -1 || regnum
== tdep
->ppc_lr_regnum
)
444 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
445 gregs
, offsets
->lr_offset
);
446 if (regnum
== -1 || regnum
== tdep
->ppc_ctr_regnum
)
447 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
448 gregs
, offsets
->ctr_offset
);
449 if (regnum
== -1 || regnum
== tdep
->ppc_xer_regnum
)
450 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
451 gregs
, offsets
->xer_offset
);
452 if (regnum
== -1 || regnum
== tdep
->ppc_mq_regnum
)
453 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
454 gregs
, offsets
->mq_offset
);
457 /* Collect register REGNUM in the floating-point register set
458 REGSET. from register cache REGCACHE into the buffer specified by
459 FPREGS and LEN. If REGNUM is -1, do this for all registers in
463 ppc_collect_fpregset (const struct regset
*regset
,
464 const struct regcache
*regcache
,
465 int regnum
, void *fpregs
, size_t len
)
467 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
468 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
469 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
473 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
475 offset
= offsets
->f0_offset
;
476 for (i
= tdep
->ppc_fp0_regnum
;
477 i
<= tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
480 if (regnum
== -1 || regnum
== i
)
481 ppc_collect_reg (regcache
, i
, fpregs
, offset
);
484 if (regnum
== -1 || regnum
== tdep
->ppc_fpscr_regnum
)
485 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
486 fpregs
, offsets
->fpscr_offset
);
490 /* Read a LEN-byte address from debugged memory address MEMADDR. */
493 read_memory_addr (CORE_ADDR memaddr
, int len
)
495 return read_memory_unsigned_integer (memaddr
, len
);
499 rs6000_skip_prologue (CORE_ADDR pc
)
501 struct rs6000_framedata frame
;
502 pc
= skip_prologue (pc
, 0, &frame
);
507 insn_changes_sp_or_jumps (unsigned long insn
)
509 int opcode
= (insn
>> 26) & 0x03f;
510 int sd
= (insn
>> 21) & 0x01f;
511 int a
= (insn
>> 16) & 0x01f;
512 int subcode
= (insn
>> 1) & 0x3ff;
514 /* Changes the stack pointer. */
516 /* NOTE: There are many ways to change the value of a given register.
517 The ways below are those used when the register is R1, the SP,
518 in a funtion's epilogue. */
520 if (opcode
== 31 && subcode
== 444 && a
== 1)
521 return 1; /* mr R1,Rn */
522 if (opcode
== 14 && sd
== 1)
523 return 1; /* addi R1,Rn,simm */
524 if (opcode
== 58 && sd
== 1)
525 return 1; /* ld R1,ds(Rn) */
527 /* Transfers control. */
533 if (opcode
== 19 && subcode
== 16)
535 if (opcode
== 19 && subcode
== 528)
536 return 1; /* bcctr */
541 /* Return true if we are in the function's epilogue, i.e. after the
542 instruction that destroyed the function's stack frame.
544 1) scan forward from the point of execution:
545 a) If you find an instruction that modifies the stack pointer
546 or transfers control (except a return), execution is not in
548 b) Stop scanning if you find a return instruction or reach the
549 end of the function or reach the hard limit for the size of
551 2) scan backward from the point of execution:
552 a) If you find an instruction that modifies the stack pointer,
553 execution *is* in an epilogue, return.
554 b) Stop scanning if you reach an instruction that transfers
555 control or the beginning of the function or reach the hard
556 limit for the size of an epilogue. */
559 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
561 bfd_byte insn_buf
[PPC_INSN_SIZE
];
562 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
564 struct frame_info
*curfrm
;
566 /* Find the search limits based on function boundaries and hard limit. */
568 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
571 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
572 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
574 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
575 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
577 curfrm
= get_current_frame ();
579 /* Scan forward until next 'blr'. */
581 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
583 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
585 insn
= extract_signed_integer (insn_buf
, PPC_INSN_SIZE
);
586 if (insn
== 0x4e800020)
588 if (insn_changes_sp_or_jumps (insn
))
592 /* Scan backward until adjustment to stack pointer (R1). */
594 for (scan_pc
= pc
- PPC_INSN_SIZE
;
595 scan_pc
>= epilogue_start
;
596 scan_pc
-= PPC_INSN_SIZE
)
598 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
600 insn
= extract_signed_integer (insn_buf
, PPC_INSN_SIZE
);
601 if (insn_changes_sp_or_jumps (insn
))
609 /* Fill in fi->saved_regs */
611 struct frame_extra_info
613 /* Functions calling alloca() change the value of the stack
614 pointer. We need to use initial stack pointer (which is saved in
615 r31 by gcc) in such cases. If a compiler emits traceback table,
616 then we should use the alloca register specified in traceback
618 CORE_ADDR initial_sp
; /* initial stack pointer. */
621 /* Get the ith function argument for the current function. */
623 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
626 return get_frame_register_unsigned (frame
, 3 + argi
);
629 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
632 branch_dest (int opcode
, int instr
, CORE_ADDR pc
, CORE_ADDR safety
)
639 absolute
= (int) ((instr
>> 1) & 1);
644 immediate
= ((instr
& ~3) << 6) >> 6; /* br unconditional */
648 dest
= pc
+ immediate
;
652 immediate
= ((instr
& ~3) << 16) >> 16; /* br conditional */
656 dest
= pc
+ immediate
;
660 ext_op
= (instr
>> 1) & 0x3ff;
662 if (ext_op
== 16) /* br conditional register */
664 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
666 /* If we are about to return from a signal handler, dest is
667 something like 0x3c90. The current frame is a signal handler
668 caller frame, upon completion of the sigreturn system call
669 execution will return to the saved PC in the frame. */
670 if (dest
< TEXT_SEGMENT_BASE
)
672 struct frame_info
*fi
;
674 fi
= get_current_frame ();
676 dest
= read_memory_addr (get_frame_base (fi
) + SIG_FRAME_PC_OFFSET
,
677 gdbarch_tdep (current_gdbarch
)->wordsize
);
681 else if (ext_op
== 528) /* br cond to count reg */
683 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_ctr_regnum
) & ~3;
685 /* If we are about to execute a system call, dest is something
686 like 0x22fc or 0x3b00. Upon completion the system call
687 will return to the address in the link register. */
688 if (dest
< TEXT_SEGMENT_BASE
)
689 dest
= read_register (gdbarch_tdep (current_gdbarch
)->ppc_lr_regnum
) & ~3;
698 return (dest
< TEXT_SEGMENT_BASE
) ? safety
: dest
;
702 /* Sequence of bytes for breakpoint instruction. */
704 const static unsigned char *
705 rs6000_breakpoint_from_pc (CORE_ADDR
*bp_addr
, int *bp_size
)
707 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
708 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
710 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
711 return big_breakpoint
;
713 return little_breakpoint
;
717 /* AIX does not support PT_STEP. Simulate it. */
720 rs6000_software_single_step (enum target_signal signal
,
721 int insert_breakpoints_p
)
725 const gdb_byte
*breakp
= rs6000_breakpoint_from_pc (&dummy
, &breakp_sz
);
731 if (insert_breakpoints_p
)
736 insn
= read_memory_integer (loc
, 4);
738 breaks
[0] = loc
+ breakp_sz
;
740 breaks
[1] = branch_dest (opcode
, insn
, loc
, breaks
[0]);
742 /* Don't put two breakpoints on the same address. */
743 if (breaks
[1] == breaks
[0])
746 stepBreaks
[1].address
= 0;
748 for (ii
= 0; ii
< 2; ++ii
)
751 /* ignore invalid breakpoint. */
752 if (breaks
[ii
] == -1)
754 target_insert_breakpoint (breaks
[ii
], stepBreaks
[ii
].data
);
755 stepBreaks
[ii
].address
= breaks
[ii
];
762 /* remove step breakpoints. */
763 for (ii
= 0; ii
< 2; ++ii
)
764 if (stepBreaks
[ii
].address
!= 0)
765 target_remove_breakpoint (stepBreaks
[ii
].address
,
766 stepBreaks
[ii
].data
);
768 errno
= 0; /* FIXME, don't ignore errors! */
769 /* What errors? {read,write}_memory call error(). */
773 /* return pc value after skipping a function prologue and also return
774 information about a function frame.
776 in struct rs6000_framedata fdata:
777 - frameless is TRUE, if function does not have a frame.
778 - nosavedpc is TRUE, if function does not save %pc value in its frame.
779 - offset is the initial size of this stack frame --- the amount by
780 which we decrement the sp to allocate the frame.
781 - saved_gpr is the number of the first saved gpr.
782 - saved_fpr is the number of the first saved fpr.
783 - saved_vr is the number of the first saved vr.
784 - saved_ev is the number of the first saved ev.
785 - alloca_reg is the number of the register used for alloca() handling.
787 - gpr_offset is the offset of the first saved gpr from the previous frame.
788 - fpr_offset is the offset of the first saved fpr from the previous frame.
789 - vr_offset is the offset of the first saved vr from the previous frame.
790 - ev_offset is the offset of the first saved ev from the previous frame.
791 - lr_offset is the offset of the saved lr
792 - cr_offset is the offset of the saved cr
793 - vrsave_offset is the offset of the saved vrsave register
796 #define SIGNED_SHORT(x) \
797 ((sizeof (short) == 2) \
798 ? ((int)(short)(x)) \
799 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
801 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
803 /* Limit the number of skipped non-prologue instructions, as the examining
804 of the prologue is expensive. */
805 static int max_skip_non_prologue_insns
= 10;
807 /* Given PC representing the starting address of a function, and
808 LIM_PC which is the (sloppy) limit to which to scan when looking
809 for a prologue, attempt to further refine this limit by using
810 the line data in the symbol table. If successful, a better guess
811 on where the prologue ends is returned, otherwise the previous
812 value of lim_pc is returned. */
814 /* FIXME: cagney/2004-02-14: This function and logic have largely been
815 superseded by skip_prologue_using_sal. */
818 refine_prologue_limit (CORE_ADDR pc
, CORE_ADDR lim_pc
)
820 struct symtab_and_line prologue_sal
;
822 prologue_sal
= find_pc_line (pc
, 0);
823 if (prologue_sal
.line
!= 0)
826 CORE_ADDR addr
= prologue_sal
.end
;
828 /* Handle the case in which compiler's optimizer/scheduler
829 has moved instructions into the prologue. We scan ahead
830 in the function looking for address ranges whose corresponding
831 line number is less than or equal to the first one that we
832 found for the function. (It can be less than when the
833 scheduler puts a body instruction before the first prologue
835 for (i
= 2 * max_skip_non_prologue_insns
;
836 i
> 0 && (lim_pc
== 0 || addr
< lim_pc
);
839 struct symtab_and_line sal
;
841 sal
= find_pc_line (addr
, 0);
844 if (sal
.line
<= prologue_sal
.line
845 && sal
.symtab
== prologue_sal
.symtab
)
852 if (lim_pc
== 0 || prologue_sal
.end
< lim_pc
)
853 lim_pc
= prologue_sal
.end
;
858 /* Return nonzero if the given instruction OP can be part of the prologue
859 of a function and saves a parameter on the stack. FRAMEP should be
860 set if one of the previous instructions in the function has set the
864 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
866 /* Move parameters from argument registers to temporary register. */
867 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
869 /* Rx must be scratch register r0. */
870 const int rx_regno
= (op
>> 16) & 31;
871 /* Ry: Only r3 - r10 are used for parameter passing. */
872 const int ry_regno
= GET_SRC_REG (op
);
874 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
876 *r0_contains_arg
= 1;
883 /* Save a General Purpose Register on stack. */
885 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
886 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
888 /* Rx: Only r3 - r10 are used for parameter passing. */
889 const int rx_regno
= GET_SRC_REG (op
);
891 return (rx_regno
>= 3 && rx_regno
<= 10);
894 /* Save a General Purpose Register on stack via the Frame Pointer. */
897 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
898 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
899 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
901 /* Rx: Usually, only r3 - r10 are used for parameter passing.
902 However, the compiler sometimes uses r0 to hold an argument. */
903 const int rx_regno
= GET_SRC_REG (op
);
905 return ((rx_regno
>= 3 && rx_regno
<= 10)
906 || (rx_regno
== 0 && *r0_contains_arg
));
909 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
911 /* Only f2 - f8 are used for parameter passing. */
912 const int src_regno
= GET_SRC_REG (op
);
914 return (src_regno
>= 2 && src_regno
<= 8);
917 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
919 /* Only f2 - f8 are used for parameter passing. */
920 const int src_regno
= GET_SRC_REG (op
);
922 return (src_regno
>= 2 && src_regno
<= 8);
925 /* Not an insn that saves a parameter on stack. */
930 skip_prologue (CORE_ADDR pc
, CORE_ADDR lim_pc
, struct rs6000_framedata
*fdata
)
932 CORE_ADDR orig_pc
= pc
;
933 CORE_ADDR last_prologue_pc
= pc
;
934 CORE_ADDR li_found_pc
= 0;
938 long vr_saved_offset
= 0;
947 int minimal_toc_loaded
= 0;
948 int prev_insn_was_prologue_insn
= 1;
949 int num_skip_non_prologue_insns
= 0;
950 int r0_contains_arg
= 0;
951 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (current_gdbarch
);
952 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
954 /* Attempt to find the end of the prologue when no limit is specified.
955 Note that refine_prologue_limit() has been written so that it may
956 be used to "refine" the limits of non-zero PC values too, but this
957 is only safe if we 1) trust the line information provided by the
958 compiler and 2) iterate enough to actually find the end of the
961 It may become a good idea at some point (for both performance and
962 accuracy) to unconditionally call refine_prologue_limit(). But,
963 until we can make a clear determination that this is beneficial,
964 we'll play it safe and only use it to obtain a limit when none
965 has been specified. */
967 lim_pc
= refine_prologue_limit (pc
, lim_pc
);
969 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
970 fdata
->saved_gpr
= -1;
971 fdata
->saved_fpr
= -1;
972 fdata
->saved_vr
= -1;
973 fdata
->saved_ev
= -1;
974 fdata
->alloca_reg
= -1;
975 fdata
->frameless
= 1;
976 fdata
->nosavedpc
= 1;
980 /* Sometimes it isn't clear if an instruction is a prologue
981 instruction or not. When we encounter one of these ambiguous
982 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
983 Otherwise, we'll assume that it really is a prologue instruction. */
984 if (prev_insn_was_prologue_insn
)
985 last_prologue_pc
= pc
;
987 /* Stop scanning if we've hit the limit. */
988 if (lim_pc
!= 0 && pc
>= lim_pc
)
991 prev_insn_was_prologue_insn
= 1;
993 /* Fetch the instruction and convert it to an integer. */
994 if (target_read_memory (pc
, buf
, 4))
996 op
= extract_signed_integer (buf
, 4);
998 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1000 /* Since shared library / PIC code, which needs to get its
1001 address at runtime, can appear to save more than one link
1015 remember just the first one, but skip over additional
1018 lr_reg
= (op
& 0x03e00000);
1020 r0_contains_arg
= 0;
1023 else if ((op
& 0xfc1fffff) == 0x7c000026)
1025 cr_reg
= (op
& 0x03e00000);
1027 r0_contains_arg
= 0;
1031 else if ((op
& 0xfc1f0000) == 0xd8010000)
1032 { /* stfd Rx,NUM(r1) */
1033 reg
= GET_SRC_REG (op
);
1034 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1036 fdata
->saved_fpr
= reg
;
1037 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1042 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1043 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1044 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1045 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1048 reg
= GET_SRC_REG (op
);
1049 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1051 fdata
->saved_gpr
= reg
;
1052 if ((op
& 0xfc1f0003) == 0xf8010000)
1054 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1059 else if ((op
& 0xffff0000) == 0x60000000)
1062 /* Allow nops in the prologue, but do not consider them to
1063 be part of the prologue unless followed by other prologue
1065 prev_insn_was_prologue_insn
= 0;
1069 else if ((op
& 0xffff0000) == 0x3c000000)
1070 { /* addis 0,0,NUM, used
1071 for >= 32k frames */
1072 fdata
->offset
= (op
& 0x0000ffff) << 16;
1073 fdata
->frameless
= 0;
1074 r0_contains_arg
= 0;
1078 else if ((op
& 0xffff0000) == 0x60000000)
1079 { /* ori 0,0,NUM, 2nd ha
1080 lf of >= 32k frames */
1081 fdata
->offset
|= (op
& 0x0000ffff);
1082 fdata
->frameless
= 0;
1083 r0_contains_arg
= 0;
1087 else if (lr_reg
>= 0 &&
1088 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1089 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1090 /* stw Rx, NUM(r1) */
1091 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1092 /* stwu Rx, NUM(r1) */
1093 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1094 { /* where Rx == lr */
1095 fdata
->lr_offset
= offset
;
1096 fdata
->nosavedpc
= 0;
1097 /* Invalidate lr_reg, but don't set it to -1.
1098 That would mean that it had never been set. */
1100 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1101 (op
& 0xfc000000) == 0x90000000) /* stw */
1103 /* Does not update r1, so add displacement to lr_offset. */
1104 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1109 else if (cr_reg
>= 0 &&
1110 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1111 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1112 /* stw Rx, NUM(r1) */
1113 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1114 /* stwu Rx, NUM(r1) */
1115 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1116 { /* where Rx == cr */
1117 fdata
->cr_offset
= offset
;
1118 /* Invalidate cr_reg, but don't set it to -1.
1119 That would mean that it had never been set. */
1121 if ((op
& 0xfc000003) == 0xf8000000 ||
1122 (op
& 0xfc000000) == 0x90000000)
1124 /* Does not update r1, so add displacement to cr_offset. */
1125 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1130 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1132 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1133 prediction bits. If the LR has already been saved, we can
1137 else if (op
== 0x48000005)
1143 else if (op
== 0x48000004)
1148 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1149 in V.4 -mminimal-toc */
1150 (op
& 0xffff0000) == 0x3bde0000)
1151 { /* addi 30,30,foo@l */
1155 else if ((op
& 0xfc000001) == 0x48000001)
1159 fdata
->frameless
= 0;
1160 /* Don't skip over the subroutine call if it is not within
1161 the first three instructions of the prologue and either
1162 we have no line table information or the line info tells
1163 us that the subroutine call is not part of the line
1164 associated with the prologue. */
1165 if ((pc
- orig_pc
) > 8)
1167 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1168 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1170 if ((prologue_sal
.line
== 0) || (prologue_sal
.line
!= this_sal
.line
))
1174 op
= read_memory_integer (pc
+ 4, 4);
1176 /* At this point, make sure this is not a trampoline
1177 function (a function that simply calls another functions,
1178 and nothing else). If the next is not a nop, this branch
1179 was part of the function prologue. */
1181 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1182 break; /* don't skip over
1187 /* update stack pointer */
1188 else if ((op
& 0xfc1f0000) == 0x94010000)
1189 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1190 fdata
->frameless
= 0;
1191 fdata
->offset
= SIGNED_SHORT (op
);
1192 offset
= fdata
->offset
;
1195 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1196 { /* stwux rX,r1,rY */
1197 /* no way to figure out what r1 is going to be */
1198 fdata
->frameless
= 0;
1199 offset
= fdata
->offset
;
1202 else if ((op
& 0xfc1f0003) == 0xf8010001)
1203 { /* stdu rX,NUM(r1) */
1204 fdata
->frameless
= 0;
1205 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1206 offset
= fdata
->offset
;
1209 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1210 { /* stdux rX,r1,rY */
1211 /* no way to figure out what r1 is going to be */
1212 fdata
->frameless
= 0;
1213 offset
= fdata
->offset
;
1216 /* Load up minimal toc pointer */
1217 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1218 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1219 && !minimal_toc_loaded
)
1221 minimal_toc_loaded
= 1;
1224 /* move parameters from argument registers to local variable
1227 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1228 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1229 (((op
>> 21) & 31) <= 10) &&
1230 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
1234 /* store parameters in stack */
1236 /* Move parameters from argument registers to temporary register. */
1237 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1241 /* Set up frame pointer */
1243 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1244 || op
== 0x7c3f0b78)
1246 fdata
->frameless
= 0;
1248 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1251 /* Another way to set up the frame pointer. */
1253 else if ((op
& 0xfc1fffff) == 0x38010000)
1254 { /* addi rX, r1, 0x0 */
1255 fdata
->frameless
= 0;
1257 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1258 + ((op
& ~0x38010000) >> 21));
1261 /* AltiVec related instructions. */
1262 /* Store the vrsave register (spr 256) in another register for
1263 later manipulation, or load a register into the vrsave
1264 register. 2 instructions are used: mfvrsave and
1265 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1266 and mtspr SPR256, Rn. */
1267 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1268 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1269 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1271 vrsave_reg
= GET_SRC_REG (op
);
1274 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1278 /* Store the register where vrsave was saved to onto the stack:
1279 rS is the register where vrsave was stored in a previous
1281 /* 100100 sssss 00001 dddddddd dddddddd */
1282 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1284 if (vrsave_reg
== GET_SRC_REG (op
))
1286 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1291 /* Compute the new value of vrsave, by modifying the register
1292 where vrsave was saved to. */
1293 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1294 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1298 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1299 in a pair of insns to save the vector registers on the
1301 /* 001110 00000 00000 iiii iiii iiii iiii */
1302 /* 001110 01110 00000 iiii iiii iiii iiii */
1303 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1304 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1306 if ((op
& 0xffff0000) == 0x38000000)
1307 r0_contains_arg
= 0;
1309 vr_saved_offset
= SIGNED_SHORT (op
);
1311 /* This insn by itself is not part of the prologue, unless
1312 if part of the pair of insns mentioned above. So do not
1313 record this insn as part of the prologue yet. */
1314 prev_insn_was_prologue_insn
= 0;
1316 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1317 /* 011111 sssss 11111 00000 00111001110 */
1318 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1320 if (pc
== (li_found_pc
+ 4))
1322 vr_reg
= GET_SRC_REG (op
);
1323 /* If this is the first vector reg to be saved, or if
1324 it has a lower number than others previously seen,
1325 reupdate the frame info. */
1326 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1328 fdata
->saved_vr
= vr_reg
;
1329 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1331 vr_saved_offset
= -1;
1336 /* End AltiVec related instructions. */
1338 /* Start BookE related instructions. */
1339 /* Store gen register S at (r31+uimm).
1340 Any register less than r13 is volatile, so we don't care. */
1341 /* 000100 sssss 11111 iiiii 01100100001 */
1342 else if (arch_info
->mach
== bfd_mach_ppc_e500
1343 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1345 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1348 ev_reg
= GET_SRC_REG (op
);
1349 imm
= (op
>> 11) & 0x1f;
1350 ev_offset
= imm
* 8;
1351 /* If this is the first vector reg to be saved, or if
1352 it has a lower number than others previously seen,
1353 reupdate the frame info. */
1354 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1356 fdata
->saved_ev
= ev_reg
;
1357 fdata
->ev_offset
= ev_offset
+ offset
;
1362 /* Store gen register rS at (r1+rB). */
1363 /* 000100 sssss 00001 bbbbb 01100100000 */
1364 else if (arch_info
->mach
== bfd_mach_ppc_e500
1365 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1367 if (pc
== (li_found_pc
+ 4))
1369 ev_reg
= GET_SRC_REG (op
);
1370 /* If this is the first vector reg to be saved, or if
1371 it has a lower number than others previously seen,
1372 reupdate the frame info. */
1373 /* We know the contents of rB from the previous instruction. */
1374 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1376 fdata
->saved_ev
= ev_reg
;
1377 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1379 vr_saved_offset
= -1;
1385 /* Store gen register r31 at (rA+uimm). */
1386 /* 000100 11111 aaaaa iiiii 01100100001 */
1387 else if (arch_info
->mach
== bfd_mach_ppc_e500
1388 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1390 /* Wwe know that the source register is 31 already, but
1391 it can't hurt to compute it. */
1392 ev_reg
= GET_SRC_REG (op
);
1393 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1394 /* If this is the first vector reg to be saved, or if
1395 it has a lower number than others previously seen,
1396 reupdate the frame info. */
1397 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1399 fdata
->saved_ev
= ev_reg
;
1400 fdata
->ev_offset
= ev_offset
+ offset
;
1405 /* Store gen register S at (r31+r0).
1406 Store param on stack when offset from SP bigger than 4 bytes. */
1407 /* 000100 sssss 11111 00000 01100100000 */
1408 else if (arch_info
->mach
== bfd_mach_ppc_e500
1409 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1411 if (pc
== (li_found_pc
+ 4))
1413 if ((op
& 0x03e00000) >= 0x01a00000)
1415 ev_reg
= GET_SRC_REG (op
);
1416 /* If this is the first vector reg to be saved, or if
1417 it has a lower number than others previously seen,
1418 reupdate the frame info. */
1419 /* We know the contents of r0 from the previous
1421 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1423 fdata
->saved_ev
= ev_reg
;
1424 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1428 vr_saved_offset
= -1;
1433 /* End BookE related instructions. */
1437 /* Not a recognized prologue instruction.
1438 Handle optimizer code motions into the prologue by continuing
1439 the search if we have no valid frame yet or if the return
1440 address is not yet saved in the frame. */
1441 if (fdata
->frameless
== 0
1442 && (lr_reg
== -1 || fdata
->nosavedpc
== 0))
1445 if (op
== 0x4e800020 /* blr */
1446 || op
== 0x4e800420) /* bctr */
1447 /* Do not scan past epilogue in frameless functions or
1450 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1451 /* Never skip branches. */
1454 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1455 /* Do not scan too many insns, scanning insns is expensive with
1459 /* Continue scanning. */
1460 prev_insn_was_prologue_insn
= 0;
1466 /* I have problems with skipping over __main() that I need to address
1467 * sometime. Previously, I used to use misc_function_vector which
1468 * didn't work as well as I wanted to be. -MGO */
1470 /* If the first thing after skipping a prolog is a branch to a function,
1471 this might be a call to an initializer in main(), introduced by gcc2.
1472 We'd like to skip over it as well. Fortunately, xlc does some extra
1473 work before calling a function right after a prologue, thus we can
1474 single out such gcc2 behaviour. */
1477 if ((op
& 0xfc000001) == 0x48000001)
1478 { /* bl foo, an initializer function? */
1479 op
= read_memory_integer (pc
+ 4, 4);
1481 if (op
== 0x4def7b82)
1482 { /* cror 0xf, 0xf, 0xf (nop) */
1484 /* Check and see if we are in main. If so, skip over this
1485 initializer function as well. */
1487 tmp
= find_pc_misc_function (pc
);
1489 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
1495 fdata
->offset
= -fdata
->offset
;
1496 return last_prologue_pc
;
1500 /*************************************************************************
1501 Support for creating pushing a dummy frame into the stack, and popping
1503 *************************************************************************/
1506 /* All the ABI's require 16 byte alignment. */
1508 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1510 return (addr
& -16);
1513 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1514 the first eight words of the argument list (that might be less than
1515 eight parameters if some parameters occupy more than one word) are
1516 passed in r3..r10 registers. float and double parameters are
1517 passed in fpr's, in addition to that. Rest of the parameters if any
1518 are passed in user stack. There might be cases in which half of the
1519 parameter is copied into registers, the other half is pushed into
1522 Stack must be aligned on 64-bit boundaries when synthesizing
1525 If the function is returning a structure, then the return address is passed
1526 in r3, then the first 7 words of the parameters can be passed in registers,
1527 starting from r4. */
1530 rs6000_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1531 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1532 int nargs
, struct value
**args
, CORE_ADDR sp
,
1533 int struct_return
, CORE_ADDR struct_addr
)
1535 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1538 int argno
; /* current argument number */
1539 int argbytes
; /* current argument byte */
1540 gdb_byte tmp_buffer
[50];
1541 int f_argno
= 0; /* current floating point argno */
1542 int wordsize
= gdbarch_tdep (current_gdbarch
)->wordsize
;
1543 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1545 struct value
*arg
= 0;
1550 /* The calling convention this function implements assumes the
1551 processor has floating-point registers. We shouldn't be using it
1552 on PPC variants that lack them. */
1553 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1555 /* The first eight words of ther arguments are passed in registers.
1556 Copy them appropriately. */
1559 /* If the function is returning a `struct', then the first word
1560 (which will be passed in r3) is used for struct return address.
1561 In that case we should advance one word and start from r4
1562 register to copy parameters. */
1565 regcache_raw_write_unsigned (regcache
, tdep
->ppc_gp0_regnum
+ 3,
1571 effectively indirect call... gcc does...
1573 return_val example( float, int);
1576 float in fp0, int in r3
1577 offset of stack on overflow 8/16
1578 for varargs, must go by type.
1580 float in r3&r4, int in r5
1581 offset of stack on overflow different
1583 return in r3 or f0. If no float, must study how gcc emulates floats;
1584 pay attention to arg promotion.
1585 User may have to cast\args to handle promotion correctly
1586 since gdb won't know if prototype supplied or not.
1589 for (argno
= 0, argbytes
= 0; argno
< nargs
&& ii
< 8; ++ii
)
1591 int reg_size
= register_size (current_gdbarch
, ii
+ 3);
1594 type
= check_typedef (value_type (arg
));
1595 len
= TYPE_LENGTH (type
);
1597 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1600 /* Floating point arguments are passed in fpr's, as well as gpr's.
1601 There are 13 fpr's reserved for passing parameters. At this point
1602 there is no way we would run out of them. */
1604 gdb_assert (len
<= 8);
1606 regcache_cooked_write (regcache
,
1607 tdep
->ppc_fp0_regnum
+ 1 + f_argno
,
1608 value_contents (arg
));
1615 /* Argument takes more than one register. */
1616 while (argbytes
< len
)
1618 gdb_byte word
[MAX_REGISTER_SIZE
];
1619 memset (word
, 0, reg_size
);
1621 ((char *) value_contents (arg
)) + argbytes
,
1622 (len
- argbytes
) > reg_size
1623 ? reg_size
: len
- argbytes
);
1624 regcache_cooked_write (regcache
,
1625 tdep
->ppc_gp0_regnum
+ 3 + ii
,
1627 ++ii
, argbytes
+= reg_size
;
1630 goto ran_out_of_registers_for_arguments
;
1637 /* Argument can fit in one register. No problem. */
1638 int adj
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? reg_size
- len
: 0;
1639 gdb_byte word
[MAX_REGISTER_SIZE
];
1641 memset (word
, 0, reg_size
);
1642 memcpy (word
, value_contents (arg
), len
);
1643 regcache_cooked_write (regcache
, tdep
->ppc_gp0_regnum
+ 3 +ii
, word
);
1648 ran_out_of_registers_for_arguments
:
1650 saved_sp
= read_sp ();
1652 /* Location for 8 parameters are always reserved. */
1655 /* Another six words for back chain, TOC register, link register, etc. */
1658 /* Stack pointer must be quadword aligned. */
1661 /* If there are more arguments, allocate space for them in
1662 the stack, then push them starting from the ninth one. */
1664 if ((argno
< nargs
) || argbytes
)
1670 space
+= ((len
- argbytes
+ 3) & -4);
1676 for (; jj
< nargs
; ++jj
)
1678 struct value
*val
= args
[jj
];
1679 space
+= ((TYPE_LENGTH (value_type (val
))) + 3) & -4;
1682 /* Add location required for the rest of the parameters. */
1683 space
= (space
+ 15) & -16;
1686 /* This is another instance we need to be concerned about
1687 securing our stack space. If we write anything underneath %sp
1688 (r1), we might conflict with the kernel who thinks he is free
1689 to use this area. So, update %sp first before doing anything
1692 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1694 /* If the last argument copied into the registers didn't fit there
1695 completely, push the rest of it into stack. */
1699 write_memory (sp
+ 24 + (ii
* 4),
1700 value_contents (arg
) + argbytes
,
1703 ii
+= ((len
- argbytes
+ 3) & -4) / 4;
1706 /* Push the rest of the arguments into stack. */
1707 for (; argno
< nargs
; ++argno
)
1711 type
= check_typedef (value_type (arg
));
1712 len
= TYPE_LENGTH (type
);
1715 /* Float types should be passed in fpr's, as well as in the
1717 if (TYPE_CODE (type
) == TYPE_CODE_FLT
&& f_argno
< 13)
1720 gdb_assert (len
<= 8);
1722 regcache_cooked_write (regcache
,
1723 tdep
->ppc_fp0_regnum
+ 1 + f_argno
,
1724 value_contents (arg
));
1728 write_memory (sp
+ 24 + (ii
* 4), value_contents (arg
), len
);
1729 ii
+= ((len
+ 3) & -4) / 4;
1733 /* Set the stack pointer. According to the ABI, the SP is meant to
1734 be set _before_ the corresponding stack space is used. On AIX,
1735 this even applies when the target has been completely stopped!
1736 Not doing this can lead to conflicts with the kernel which thinks
1737 that it still has control over this not-yet-allocated stack
1739 regcache_raw_write_signed (regcache
, SP_REGNUM
, sp
);
1741 /* Set back chain properly. */
1742 store_unsigned_integer (tmp_buffer
, wordsize
, saved_sp
);
1743 write_memory (sp
, tmp_buffer
, wordsize
);
1745 /* Point the inferior function call's return address at the dummy's
1747 regcache_raw_write_signed (regcache
, tdep
->ppc_lr_regnum
, bp_addr
);
1749 /* Set the TOC register, get the value from the objfile reader
1750 which, in turn, gets it from the VMAP table. */
1751 if (rs6000_find_toc_address_hook
!= NULL
)
1753 CORE_ADDR tocvalue
= (*rs6000_find_toc_address_hook
) (func_addr
);
1754 regcache_raw_write_signed (regcache
, tdep
->ppc_toc_regnum
, tocvalue
);
1757 target_store_registers (-1);
1761 /* PowerOpen always puts structures in memory. Vectors, which were
1762 added later, do get returned in a register though. */
1765 rs6000_use_struct_convention (int gcc_p
, struct type
*value_type
)
1767 if ((TYPE_LENGTH (value_type
) == 16 || TYPE_LENGTH (value_type
) == 8)
1768 && TYPE_VECTOR (value_type
))
1774 rs6000_extract_return_value (struct type
*valtype
, gdb_byte
*regbuf
,
1778 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1780 /* The calling convention this function implements assumes the
1781 processor has floating-point registers. We shouldn't be using it
1782 on PPC variants that lack them. */
1783 gdb_assert (ppc_floating_point_unit_p (current_gdbarch
));
1785 if (TYPE_CODE (valtype
) == TYPE_CODE_FLT
)
1788 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1789 We need to truncate the return value into float size (4 byte) if
1792 convert_typed_floating (®buf
[DEPRECATED_REGISTER_BYTE
1793 (tdep
->ppc_fp0_regnum
+ 1)],
1794 builtin_type_double
,
1798 else if (TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
1799 && TYPE_LENGTH (valtype
) == 16
1800 && TYPE_VECTOR (valtype
))
1802 memcpy (valbuf
, regbuf
+ DEPRECATED_REGISTER_BYTE (tdep
->ppc_vr0_regnum
+ 2),
1803 TYPE_LENGTH (valtype
));
1807 /* return value is copied starting from r3. */
1808 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
1809 && TYPE_LENGTH (valtype
) < register_size (current_gdbarch
, 3))
1810 offset
= register_size (current_gdbarch
, 3) - TYPE_LENGTH (valtype
);
1813 regbuf
+ DEPRECATED_REGISTER_BYTE (3) + offset
,
1814 TYPE_LENGTH (valtype
));
1818 /* Return whether handle_inferior_event() should proceed through code
1819 starting at PC in function NAME when stepping.
1821 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1822 handle memory references that are too distant to fit in instructions
1823 generated by the compiler. For example, if 'foo' in the following
1828 is greater than 32767, the linker might replace the lwz with a branch to
1829 somewhere in @FIX1 that does the load in 2 instructions and then branches
1830 back to where execution should continue.
1832 GDB should silently step over @FIX code, just like AIX dbx does.
1833 Unfortunately, the linker uses the "b" instruction for the
1834 branches, meaning that the link register doesn't get set.
1835 Therefore, GDB's usual step_over_function () mechanism won't work.
1837 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1838 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1842 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
1844 return name
&& !strncmp (name
, "@FIX", 4);
1847 /* Skip code that the user doesn't want to see when stepping:
1849 1. Indirect function calls use a piece of trampoline code to do context
1850 switching, i.e. to set the new TOC table. Skip such code if we are on
1851 its first instruction (as when we have single-stepped to here).
1853 2. Skip shared library trampoline code (which is different from
1854 indirect function call trampolines).
1856 3. Skip bigtoc fixup code.
1858 Result is desired PC to step until, or NULL if we are not in
1859 code that should be skipped. */
1862 rs6000_skip_trampoline_code (CORE_ADDR pc
)
1864 unsigned int ii
, op
;
1866 CORE_ADDR solib_target_pc
;
1867 struct minimal_symbol
*msymbol
;
1869 static unsigned trampoline_code
[] =
1871 0x800b0000, /* l r0,0x0(r11) */
1872 0x90410014, /* st r2,0x14(r1) */
1873 0x7c0903a6, /* mtctr r0 */
1874 0x804b0004, /* l r2,0x4(r11) */
1875 0x816b0008, /* l r11,0x8(r11) */
1876 0x4e800420, /* bctr */
1877 0x4e800020, /* br */
1881 /* Check for bigtoc fixup code. */
1882 msymbol
= lookup_minimal_symbol_by_pc (pc
);
1884 && rs6000_in_solib_return_trampoline (pc
,
1885 DEPRECATED_SYMBOL_NAME (msymbol
)))
1887 /* Double-check that the third instruction from PC is relative "b". */
1888 op
= read_memory_integer (pc
+ 8, 4);
1889 if ((op
& 0xfc000003) == 0x48000000)
1891 /* Extract bits 6-29 as a signed 24-bit relative word address and
1892 add it to the containing PC. */
1893 rel
= ((int)(op
<< 6) >> 6);
1894 return pc
+ 8 + rel
;
1898 /* If pc is in a shared library trampoline, return its target. */
1899 solib_target_pc
= find_solib_trampoline_target (pc
);
1900 if (solib_target_pc
)
1901 return solib_target_pc
;
1903 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
1905 op
= read_memory_integer (pc
+ (ii
* 4), 4);
1906 if (op
!= trampoline_code
[ii
])
1909 ii
= read_register (11); /* r11 holds destination addr */
1910 pc
= read_memory_addr (ii
, gdbarch_tdep (current_gdbarch
)->wordsize
); /* (r11) value */
1914 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1915 isn't available with that word size, return 0. */
1918 regsize (const struct reg
*reg
, int wordsize
)
1920 return wordsize
== 8 ? reg
->sz64
: reg
->sz32
;
1923 /* Return the name of register number N, or null if no such register exists
1924 in the current architecture. */
1927 rs6000_register_name (int n
)
1929 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1930 const struct reg
*reg
= tdep
->regs
+ n
;
1932 if (!regsize (reg
, tdep
->wordsize
))
1937 /* Return the GDB type object for the "standard" data type
1938 of data in register N. */
1940 static struct type
*
1941 rs6000_register_type (struct gdbarch
*gdbarch
, int n
)
1943 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1944 const struct reg
*reg
= tdep
->regs
+ n
;
1947 return builtin_type_double
;
1950 int size
= regsize (reg
, tdep
->wordsize
);
1954 return builtin_type_int0
;
1956 return builtin_type_uint32
;
1958 if (tdep
->ppc_ev0_regnum
<= n
&& n
<= tdep
->ppc_ev31_regnum
)
1959 return builtin_type_vec64
;
1961 return builtin_type_uint64
;
1964 return builtin_type_vec128
;
1967 internal_error (__FILE__
, __LINE__
, _("Register %d size %d unknown"),
1973 /* Is REGNUM a member of REGGROUP? */
1975 rs6000_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1976 struct reggroup
*group
)
1978 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1983 if (REGISTER_NAME (regnum
) == NULL
1984 || *REGISTER_NAME (regnum
) == '\0')
1986 if (group
== all_reggroup
)
1989 float_p
= (regnum
== tdep
->ppc_fpscr_regnum
1990 || (regnum
>= tdep
->ppc_fp0_regnum
1991 && regnum
< tdep
->ppc_fp0_regnum
+ 32));
1992 if (group
== float_reggroup
)
1995 vector_p
= ((tdep
->ppc_vr0_regnum
>= 0
1996 && regnum
>= tdep
->ppc_vr0_regnum
1997 && regnum
< tdep
->ppc_vr0_regnum
+ 32)
1998 || (tdep
->ppc_ev0_regnum
>= 0
1999 && regnum
>= tdep
->ppc_ev0_regnum
2000 && regnum
< tdep
->ppc_ev0_regnum
+ 32)
2001 || regnum
== tdep
->ppc_vrsave_regnum
- 1 /* vscr */
2002 || regnum
== tdep
->ppc_vrsave_regnum
2003 || regnum
== tdep
->ppc_acc_regnum
2004 || regnum
== tdep
->ppc_spefscr_regnum
);
2005 if (group
== vector_reggroup
)
2008 /* Note that PS aka MSR isn't included - it's a system register (and
2009 besides, due to GCC's CFI foobar you do not want to restore
2011 general_p
= ((regnum
>= tdep
->ppc_gp0_regnum
2012 && regnum
< tdep
->ppc_gp0_regnum
+ 32)
2013 || regnum
== tdep
->ppc_toc_regnum
2014 || regnum
== tdep
->ppc_cr_regnum
2015 || regnum
== tdep
->ppc_lr_regnum
2016 || regnum
== tdep
->ppc_ctr_regnum
2017 || regnum
== tdep
->ppc_xer_regnum
2018 || regnum
== PC_REGNUM
);
2019 if (group
== general_reggroup
)
2022 if (group
== save_reggroup
|| group
== restore_reggroup
)
2023 return general_p
|| vector_p
|| float_p
;
2028 /* The register format for RS/6000 floating point registers is always
2029 double, we need a conversion if the memory format is float. */
2032 rs6000_convert_register_p (int regnum
, struct type
*type
)
2034 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
2037 && TYPE_CODE (type
) == TYPE_CODE_FLT
2038 && TYPE_LENGTH (type
) != TYPE_LENGTH (builtin_type_double
));
2042 rs6000_register_to_value (struct frame_info
*frame
,
2047 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
2048 gdb_byte from
[MAX_REGISTER_SIZE
];
2050 gdb_assert (reg
->fpr
);
2051 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2053 get_frame_register (frame
, regnum
, from
);
2054 convert_typed_floating (from
, builtin_type_double
, to
, type
);
2058 rs6000_value_to_register (struct frame_info
*frame
,
2061 const gdb_byte
*from
)
2063 const struct reg
*reg
= gdbarch_tdep (current_gdbarch
)->regs
+ regnum
;
2064 gdb_byte to
[MAX_REGISTER_SIZE
];
2066 gdb_assert (reg
->fpr
);
2067 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2069 convert_typed_floating (from
, type
, to
, builtin_type_double
);
2070 put_frame_register (frame
, regnum
, to
);
2073 /* Move SPE vector register values between a 64-bit buffer and the two
2074 32-bit raw register halves in a regcache. This function handles
2075 both splitting a 64-bit value into two 32-bit halves, and joining
2076 two halves into a whole 64-bit value, depending on the function
2077 passed as the MOVE argument.
2079 EV_REG must be the number of an SPE evN vector register --- a
2080 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2083 Call MOVE once for each 32-bit half of that register, passing
2084 REGCACHE, the number of the raw register corresponding to that
2085 half, and the address of the appropriate half of BUFFER.
2087 For example, passing 'regcache_raw_read' as the MOVE function will
2088 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2089 'regcache_raw_supply' will supply the contents of BUFFER to the
2090 appropriate pair of raw registers in REGCACHE.
2092 You may need to cast away some 'const' qualifiers when passing
2093 MOVE, since this function can't tell at compile-time which of
2094 REGCACHE or BUFFER is acting as the source of the data. If C had
2095 co-variant type qualifiers, ... */
2097 e500_move_ev_register (void (*move
) (struct regcache
*regcache
,
2098 int regnum
, gdb_byte
*buf
),
2099 struct regcache
*regcache
, int ev_reg
,
2102 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2103 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2105 gdb_byte
*byte_buffer
= buffer
;
2107 gdb_assert (tdep
->ppc_ev0_regnum
<= ev_reg
2108 && ev_reg
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
);
2110 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2112 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2114 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
);
2115 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
+ 4);
2119 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2120 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
+ 4);
2125 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2126 int reg_nr
, gdb_byte
*buffer
)
2128 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2129 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2131 gdb_assert (regcache_arch
== gdbarch
);
2133 if (tdep
->ppc_ev0_regnum
<= reg_nr
2134 && reg_nr
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
)
2135 e500_move_ev_register (regcache_raw_read
, regcache
, reg_nr
, buffer
);
2137 internal_error (__FILE__
, __LINE__
,
2138 _("e500_pseudo_register_read: "
2139 "called on unexpected register '%s' (%d)"),
2140 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2144 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2145 int reg_nr
, const gdb_byte
*buffer
)
2147 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2148 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2150 gdb_assert (regcache_arch
== gdbarch
);
2152 if (tdep
->ppc_ev0_regnum
<= reg_nr
2153 && reg_nr
< tdep
->ppc_ev0_regnum
+ ppc_num_gprs
)
2154 e500_move_ev_register ((void (*) (struct regcache
*, int, gdb_byte
*))
2156 regcache
, reg_nr
, (gdb_byte
*) buffer
);
2158 internal_error (__FILE__
, __LINE__
,
2159 _("e500_pseudo_register_read: "
2160 "called on unexpected register '%s' (%d)"),
2161 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2164 /* The E500 needs a custom reggroup function: it has anonymous raw
2165 registers, and default_register_reggroup_p assumes that anonymous
2166 registers are not members of any reggroup. */
2168 e500_register_reggroup_p (struct gdbarch
*gdbarch
,
2170 struct reggroup
*group
)
2172 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2174 /* The save and restore register groups need to include the
2175 upper-half registers, even though they're anonymous. */
2176 if ((group
== save_reggroup
2177 || group
== restore_reggroup
)
2178 && (tdep
->ppc_ev0_upper_regnum
<= regnum
2179 && regnum
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
))
2182 /* In all other regards, the default reggroup definition is fine. */
2183 return default_register_reggroup_p (gdbarch
, regnum
, group
);
2186 /* Convert a DBX STABS register number to a GDB register number. */
2188 rs6000_stab_reg_to_regnum (int num
)
2190 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2192 if (0 <= num
&& num
<= 31)
2193 return tdep
->ppc_gp0_regnum
+ num
;
2194 else if (32 <= num
&& num
<= 63)
2195 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2196 specifies registers the architecture doesn't have? Our
2197 callers don't check the value we return. */
2198 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2199 else if (77 <= num
&& num
<= 108)
2200 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2201 else if (1200 <= num
&& num
< 1200 + 32)
2202 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2207 return tdep
->ppc_mq_regnum
;
2209 return tdep
->ppc_lr_regnum
;
2211 return tdep
->ppc_ctr_regnum
;
2213 return tdep
->ppc_xer_regnum
;
2215 return tdep
->ppc_vrsave_regnum
;
2217 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2219 return tdep
->ppc_acc_regnum
;
2221 return tdep
->ppc_spefscr_regnum
;
2228 /* Convert a Dwarf 2 register number to a GDB register number. */
2230 rs6000_dwarf2_reg_to_regnum (int num
)
2232 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2234 if (0 <= num
&& num
<= 31)
2235 return tdep
->ppc_gp0_regnum
+ num
;
2236 else if (32 <= num
&& num
<= 63)
2237 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2238 specifies registers the architecture doesn't have? Our
2239 callers don't check the value we return. */
2240 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2241 else if (1124 <= num
&& num
< 1124 + 32)
2242 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2243 else if (1200 <= num
&& num
< 1200 + 32)
2244 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2249 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2251 return tdep
->ppc_acc_regnum
;
2253 return tdep
->ppc_mq_regnum
;
2255 return tdep
->ppc_xer_regnum
;
2257 return tdep
->ppc_lr_regnum
;
2259 return tdep
->ppc_ctr_regnum
;
2261 return tdep
->ppc_vrsave_regnum
;
2263 return tdep
->ppc_spefscr_regnum
;
2271 rs6000_store_return_value (struct type
*type
,
2272 struct regcache
*regcache
,
2273 const gdb_byte
*valbuf
)
2275 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2276 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2279 /* The calling convention this function implements assumes the
2280 processor has floating-point registers. We shouldn't be using it
2281 on PPC variants that lack them. */
2282 gdb_assert (ppc_floating_point_unit_p (gdbarch
));
2284 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2285 /* Floating point values are returned starting from FPR1 and up.
2286 Say a double_double_double type could be returned in
2287 FPR1/FPR2/FPR3 triple. */
2288 regnum
= tdep
->ppc_fp0_regnum
+ 1;
2289 else if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
2291 if (TYPE_LENGTH (type
) == 16
2292 && TYPE_VECTOR (type
))
2293 regnum
= tdep
->ppc_vr0_regnum
+ 2;
2295 internal_error (__FILE__
, __LINE__
,
2296 _("rs6000_store_return_value: "
2297 "unexpected array return type"));
2300 /* Everything else is returned in GPR3 and up. */
2301 regnum
= tdep
->ppc_gp0_regnum
+ 3;
2304 size_t bytes_written
= 0;
2306 while (bytes_written
< TYPE_LENGTH (type
))
2308 /* How much of this value can we write to this register? */
2309 size_t bytes_to_write
= min (TYPE_LENGTH (type
) - bytes_written
,
2310 register_size (gdbarch
, regnum
));
2311 regcache_cooked_write_part (regcache
, regnum
,
2313 valbuf
+ bytes_written
);
2315 bytes_written
+= bytes_to_write
;
2321 /* Extract from an array REGBUF containing the (raw) register state
2322 the address in which a function should return its structure value,
2323 as a CORE_ADDR (or an expression that can be used as one). */
2326 rs6000_extract_struct_value_address (struct regcache
*regcache
)
2328 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
2329 function call GDB knows the address of the struct return value
2330 and hence, should not need to call this function. Unfortunately,
2331 the current call_function_by_hand() code only saves the most
2332 recent struct address leading to occasional calls. The code
2333 should instead maintain a stack of such addresses (in the dummy
2335 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
2336 really got no idea where the return value is being stored. While
2337 r3, on function entry, contained the address it will have since
2338 been reused (scratch) and hence wouldn't be valid */
2342 /* Hook called when a new child process is started. */
2345 rs6000_create_inferior (int pid
)
2347 if (rs6000_set_host_arch_hook
)
2348 rs6000_set_host_arch_hook (pid
);
2351 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2353 Usually a function pointer's representation is simply the address
2354 of the function. On the RS/6000 however, a function pointer is
2355 represented by a pointer to an OPD entry. This OPD entry contains
2356 three words, the first word is the address of the function, the
2357 second word is the TOC pointer (r2), and the third word is the
2358 static chain value. Throughout GDB it is currently assumed that a
2359 function pointer contains the address of the function, which is not
2360 easy to fix. In addition, the conversion of a function address to
2361 a function pointer would require allocation of an OPD entry in the
2362 inferior's memory space, with all its drawbacks. To be able to
2363 call C++ virtual methods in the inferior (which are called via
2364 function pointers), find_function_addr uses this function to get the
2365 function address from a function pointer. */
2367 /* Return real function address if ADDR (a function pointer) is in the data
2368 space and is therefore a special function pointer. */
2371 rs6000_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
,
2373 struct target_ops
*targ
)
2375 struct obj_section
*s
;
2377 s
= find_pc_section (addr
);
2378 if (s
&& s
->the_bfd_section
->flags
& SEC_CODE
)
2381 /* ADDR is in the data space, so it's a special function pointer. */
2382 return read_memory_addr (addr
, gdbarch_tdep (current_gdbarch
)->wordsize
);
2386 /* Handling the various POWER/PowerPC variants. */
2389 /* The arrays here called registers_MUMBLE hold information about available
2392 For each family of PPC variants, I've tried to isolate out the
2393 common registers and put them up front, so that as long as you get
2394 the general family right, GDB will correctly identify the registers
2395 common to that family. The common register sets are:
2397 For the 60x family: hid0 hid1 iabr dabr pir
2399 For the 505 and 860 family: eie eid nri
2401 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2402 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2405 Most of these register groups aren't anything formal. I arrived at
2406 them by looking at the registers that occurred in more than one
2409 Note: kevinb/2002-04-30: Support for the fpscr register was added
2410 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2411 for Power. For PowerPC, slot 70 was unused and was already in the
2412 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2413 slot 70 was being used for "mq", so the next available slot (71)
2414 was chosen. It would have been nice to be able to make the
2415 register numbers the same across processor cores, but this wasn't
2416 possible without either 1) renumbering some registers for some
2417 processors or 2) assigning fpscr to a really high slot that's
2418 larger than any current register number. Doing (1) is bad because
2419 existing stubs would break. Doing (2) is undesirable because it
2420 would introduce a really large gap between fpscr and the rest of
2421 the registers for most processors. */
2423 /* Convenience macros for populating register arrays. */
2425 /* Within another macro, convert S to a string. */
2429 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2430 and 64 bits on 64-bit systems. */
2431 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2433 /* Return a struct reg defining register NAME that's 32 bits on all
2435 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2437 /* Return a struct reg defining register NAME that's 64 bits on all
2439 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2441 /* Return a struct reg defining register NAME that's 128 bits on all
2443 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2445 /* Return a struct reg defining floating-point register NAME. */
2446 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2448 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2449 long on all systems. */
2450 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2452 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2453 systems and that doesn't exist on 64-bit systems. */
2454 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2456 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2457 systems and that doesn't exist on 32-bit systems. */
2458 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2460 /* Return a struct reg placeholder for a register that doesn't exist. */
2461 #define R0 { 0, 0, 0, 0, 0, -1 }
2463 /* Return a struct reg defining an anonymous raw register that's 32
2464 bits on all systems. */
2465 #define A4 { 0, 4, 4, 0, 0, -1 }
2467 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2468 32-bit systems and 64 bits on 64-bit systems. */
2469 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2471 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2473 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2475 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2476 all systems, and whose SPR number is NUMBER. */
2477 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2479 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2480 64-bit systems and that doesn't exist on 32-bit systems. */
2481 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2483 /* UISA registers common across all architectures, including POWER. */
2485 #define COMMON_UISA_REGS \
2486 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2487 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2488 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2489 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2490 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2491 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2492 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2493 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2494 /* 64 */ R(pc), R(ps)
2496 /* UISA-level SPRs for PowerPC. */
2497 #define PPC_UISA_SPRS \
2498 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2500 /* UISA-level SPRs for PowerPC without floating point support. */
2501 #define PPC_UISA_NOFP_SPRS \
2502 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2504 /* Segment registers, for PowerPC. */
2505 #define PPC_SEGMENT_REGS \
2506 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2507 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2508 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2509 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2511 /* OEA SPRs for PowerPC. */
2512 #define PPC_OEA_SPRS \
2514 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2515 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2516 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2517 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2518 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2519 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2520 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2521 /* 116 */ S4(dec), S(dabr), S4(ear)
2523 /* AltiVec registers. */
2524 #define PPC_ALTIVEC_REGS \
2525 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2526 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2527 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2528 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2529 /*151*/R4(vscr), R4(vrsave)
2532 /* On machines supporting the SPE APU, the general-purpose registers
2533 are 64 bits long. There are SIMD vector instructions to treat them
2534 as pairs of floats, but the rest of the instruction set treats them
2535 as 32-bit registers, and only operates on their lower halves.
2537 In the GDB regcache, we treat their high and low halves as separate
2538 registers. The low halves we present as the general-purpose
2539 registers, and then we have pseudo-registers that stitch together
2540 the upper and lower halves and present them as pseudo-registers. */
2542 /* SPE GPR lower halves --- raw registers. */
2543 #define PPC_SPE_GP_REGS \
2544 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2545 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2546 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2547 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2549 /* SPE GPR upper halves --- anonymous raw registers. */
2550 #define PPC_SPE_UPPER_GP_REGS \
2551 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2552 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2553 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2554 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2556 /* SPE GPR vector registers --- pseudo registers based on underlying
2557 gprs and the anonymous upper half raw registers. */
2558 #define PPC_EV_PSEUDO_REGS \
2559 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2560 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2561 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2562 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2564 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2565 user-level SPR's. */
2566 static const struct reg registers_power
[] =
2569 /* 66 */ R4(cnd
), S(lr
), S(cnt
), S4(xer
), S4(mq
),
2573 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2574 view of the PowerPC. */
2575 static const struct reg registers_powerpc
[] =
2584 Some notes about the "tcr" special-purpose register:
2585 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2586 403's programmable interval timer, fixed interval timer, and
2588 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2589 watchdog timer, and nothing else.
2591 Some of the fields are similar between the two, but they're not
2592 compatible with each other. Since the two variants have different
2593 registers, with different numbers, but the same name, we can't
2594 splice the register name to get the SPR number. */
2595 static const struct reg registers_403
[] =
2601 /* 119 */ S(icdbdr
), S(esr
), S(dear
), S(evpr
),
2602 /* 123 */ S(cdbcr
), S(tsr
), SN4(tcr
, ppc_spr_403_tcr
), S(pit
),
2603 /* 127 */ S(tbhi
), S(tblo
), S(srr2
), S(srr3
),
2604 /* 131 */ S(dbsr
), S(dbcr
), S(iac1
), S(iac2
),
2605 /* 135 */ S(dac1
), S(dac2
), S(dccr
), S(iccr
),
2606 /* 139 */ S(pbl1
), S(pbu1
), S(pbl2
), S(pbu2
)
2609 /* IBM PowerPC 403GC.
2610 See the comments about 'tcr' for the 403, above. */
2611 static const struct reg registers_403GC
[] =
2617 /* 119 */ S(icdbdr
), S(esr
), S(dear
), S(evpr
),
2618 /* 123 */ S(cdbcr
), S(tsr
), SN4(tcr
, ppc_spr_403_tcr
), S(pit
),
2619 /* 127 */ S(tbhi
), S(tblo
), S(srr2
), S(srr3
),
2620 /* 131 */ S(dbsr
), S(dbcr
), S(iac1
), S(iac2
),
2621 /* 135 */ S(dac1
), S(dac2
), S(dccr
), S(iccr
),
2622 /* 139 */ S(pbl1
), S(pbu1
), S(pbl2
), S(pbu2
),
2623 /* 143 */ S(zpr
), S(pid
), S(sgr
), S(dcwr
),
2624 /* 147 */ S(tbhu
), S(tblu
)
2627 /* Motorola PowerPC 505. */
2628 static const struct reg registers_505
[] =
2634 /* 119 */ S(eie
), S(eid
), S(nri
)
2637 /* Motorola PowerPC 860 or 850. */
2638 static const struct reg registers_860
[] =
2644 /* 119 */ S(eie
), S(eid
), S(nri
), S(cmpa
),
2645 /* 123 */ S(cmpb
), S(cmpc
), S(cmpd
), S(icr
),
2646 /* 127 */ S(der
), S(counta
), S(countb
), S(cmpe
),
2647 /* 131 */ S(cmpf
), S(cmpg
), S(cmph
), S(lctrl1
),
2648 /* 135 */ S(lctrl2
), S(ictrl
), S(bar
), S(ic_cst
),
2649 /* 139 */ S(ic_adr
), S(ic_dat
), S(dc_cst
), S(dc_adr
),
2650 /* 143 */ S(dc_dat
), S(dpdr
), S(dpir
), S(immr
),
2651 /* 147 */ S(mi_ctr
), S(mi_ap
), S(mi_epn
), S(mi_twc
),
2652 /* 151 */ S(mi_rpn
), S(md_ctr
), S(m_casid
), S(md_ap
),
2653 /* 155 */ S(md_epn
), S(m_twb
), S(md_twc
), S(md_rpn
),
2654 /* 159 */ S(m_tw
), S(mi_dbcam
), S(mi_dbram0
), S(mi_dbram1
),
2655 /* 163 */ S(md_dbcam
), S(md_dbram0
), S(md_dbram1
)
2658 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2659 for reading and writing RTCU and RTCL. However, how one reads and writes a
2660 register is the stub's problem. */
2661 static const struct reg registers_601
[] =
2667 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2668 /* 123 */ S(pir
), S(mq
), S(rtcu
), S(rtcl
)
2671 /* Motorola PowerPC 602.
2672 See the notes under the 403 about 'tcr'. */
2673 static const struct reg registers_602
[] =
2679 /* 119 */ S(hid0
), S(hid1
), S(iabr
), R0
,
2680 /* 123 */ R0
, SN4(tcr
, ppc_spr_602_tcr
), S(ibr
), S(esasrr
),
2681 /* 127 */ S(sebr
), S(ser
), S(sp
), S(lt
)
2684 /* Motorola/IBM PowerPC 603 or 603e. */
2685 static const struct reg registers_603
[] =
2691 /* 119 */ S(hid0
), S(hid1
), S(iabr
), R0
,
2692 /* 123 */ R0
, S(dmiss
), S(dcmp
), S(hash1
),
2693 /* 127 */ S(hash2
), S(imiss
), S(icmp
), S(rpa
)
2696 /* Motorola PowerPC 604 or 604e. */
2697 static const struct reg registers_604
[] =
2703 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2704 /* 123 */ S(pir
), S(mmcr0
), S(pmc1
), S(pmc2
),
2705 /* 127 */ S(sia
), S(sda
)
2708 /* Motorola/IBM PowerPC 750 or 740. */
2709 static const struct reg registers_750
[] =
2715 /* 119 */ S(hid0
), S(hid1
), S(iabr
), S(dabr
),
2716 /* 123 */ R0
, S(ummcr0
), S(upmc1
), S(upmc2
),
2717 /* 127 */ S(usia
), S(ummcr1
), S(upmc3
), S(upmc4
),
2718 /* 131 */ S(mmcr0
), S(pmc1
), S(pmc2
), S(sia
),
2719 /* 135 */ S(mmcr1
), S(pmc3
), S(pmc4
), S(l2cr
),
2720 /* 139 */ S(ictc
), S(thrm1
), S(thrm2
), S(thrm3
)
2724 /* Motorola PowerPC 7400. */
2725 static const struct reg registers_7400
[] =
2727 /* gpr0-gpr31, fpr0-fpr31 */
2729 /* cr, lr, ctr, xer, fpscr */
2734 /* vr0-vr31, vrsave, vscr */
2736 /* FIXME? Add more registers? */
2739 /* Motorola e500. */
2740 static const struct reg registers_e500
[] =
2742 /* 0 .. 31 */ PPC_SPE_GP_REGS
,
2743 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS
,
2744 /* 64 .. 65 */ R(pc
), R(ps
),
2745 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS
,
2746 /* 71 .. 72 */ R8(acc
), S4(spefscr
),
2747 /* NOTE: Add new registers here the end of the raw register
2748 list and just before the first pseudo register. */
2749 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2752 /* Information about a particular processor variant. */
2756 /* Name of this variant. */
2759 /* English description of the variant. */
2762 /* bfd_arch_info.arch corresponding to variant. */
2763 enum bfd_architecture arch
;
2765 /* bfd_arch_info.mach corresponding to variant. */
2768 /* Number of real registers. */
2771 /* Number of pseudo registers. */
2774 /* Number of total registers (the sum of nregs and npregs). */
2777 /* Table of register names; registers[R] is the name of the register
2779 const struct reg
*regs
;
2782 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2785 num_registers (const struct reg
*reg_list
, int num_tot_regs
)
2790 for (i
= 0; i
< num_tot_regs
; i
++)
2791 if (!reg_list
[i
].pseudo
)
2798 num_pseudo_registers (const struct reg
*reg_list
, int num_tot_regs
)
2803 for (i
= 0; i
< num_tot_regs
; i
++)
2804 if (reg_list
[i
].pseudo
)
2810 /* Information in this table comes from the following web sites:
2811 IBM: http://www.chips.ibm.com:80/products/embedded/
2812 Motorola: http://www.mot.com/SPS/PowerPC/
2814 I'm sure I've got some of the variant descriptions not quite right.
2815 Please report any inaccuracies you find to GDB's maintainer.
2817 If you add entries to this table, please be sure to allow the new
2818 value as an argument to the --with-cpu flag, in configure.in. */
2820 static struct variant variants
[] =
2823 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2824 bfd_mach_ppc
, -1, -1, tot_num_registers (registers_powerpc
),
2826 {"power", "POWER user-level", bfd_arch_rs6000
,
2827 bfd_mach_rs6k
, -1, -1, tot_num_registers (registers_power
),
2829 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2830 bfd_mach_ppc_403
, -1, -1, tot_num_registers (registers_403
),
2832 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2833 bfd_mach_ppc_601
, -1, -1, tot_num_registers (registers_601
),
2835 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2836 bfd_mach_ppc_602
, -1, -1, tot_num_registers (registers_602
),
2838 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2839 bfd_mach_ppc_603
, -1, -1, tot_num_registers (registers_603
),
2841 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2842 604, -1, -1, tot_num_registers (registers_604
),
2844 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2845 bfd_mach_ppc_403gc
, -1, -1, tot_num_registers (registers_403GC
),
2847 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2848 bfd_mach_ppc_505
, -1, -1, tot_num_registers (registers_505
),
2850 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2851 bfd_mach_ppc_860
, -1, -1, tot_num_registers (registers_860
),
2853 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2854 bfd_mach_ppc_750
, -1, -1, tot_num_registers (registers_750
),
2856 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2857 bfd_mach_ppc_7400
, -1, -1, tot_num_registers (registers_7400
),
2859 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2860 bfd_mach_ppc_e500
, -1, -1, tot_num_registers (registers_e500
),
2864 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2865 bfd_mach_ppc64
, -1, -1, tot_num_registers (registers_powerpc
),
2867 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2868 bfd_mach_ppc_620
, -1, -1, tot_num_registers (registers_powerpc
),
2870 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2871 bfd_mach_ppc_630
, -1, -1, tot_num_registers (registers_powerpc
),
2873 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2874 bfd_mach_ppc_a35
, -1, -1, tot_num_registers (registers_powerpc
),
2876 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2877 bfd_mach_ppc_rs64ii
, -1, -1, tot_num_registers (registers_powerpc
),
2879 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2880 bfd_mach_ppc_rs64iii
, -1, -1, tot_num_registers (registers_powerpc
),
2883 /* FIXME: I haven't checked the register sets of the following. */
2884 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2885 bfd_mach_rs6k_rs1
, -1, -1, tot_num_registers (registers_power
),
2887 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2888 bfd_mach_rs6k_rsc
, -1, -1, tot_num_registers (registers_power
),
2890 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2891 bfd_mach_rs6k_rs2
, -1, -1, tot_num_registers (registers_power
),
2894 {0, 0, 0, 0, 0, 0, 0, 0}
2897 /* Initialize the number of registers and pseudo registers in each variant. */
2900 init_variants (void)
2904 for (v
= variants
; v
->name
; v
++)
2907 v
->nregs
= num_registers (v
->regs
, v
->num_tot_regs
);
2908 if (v
->npregs
== -1)
2909 v
->npregs
= num_pseudo_registers (v
->regs
, v
->num_tot_regs
);
2913 /* Return the variant corresponding to architecture ARCH and machine number
2914 MACH. If no such variant exists, return null. */
2916 static const struct variant
*
2917 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
2919 const struct variant
*v
;
2921 for (v
= variants
; v
->name
; v
++)
2922 if (arch
== v
->arch
&& mach
== v
->mach
)
2929 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
2931 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2932 return print_insn_big_powerpc (memaddr
, info
);
2934 return print_insn_little_powerpc (memaddr
, info
);
2938 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2940 return frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
2943 static struct frame_id
2944 rs6000_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2946 return frame_id_build (frame_unwind_register_unsigned (next_frame
,
2948 frame_pc_unwind (next_frame
));
2951 struct rs6000_frame_cache
2954 CORE_ADDR initial_sp
;
2955 struct trad_frame_saved_reg
*saved_regs
;
2958 static struct rs6000_frame_cache
*
2959 rs6000_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2961 struct rs6000_frame_cache
*cache
;
2962 struct gdbarch
*gdbarch
= get_frame_arch (next_frame
);
2963 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2964 struct rs6000_framedata fdata
;
2965 int wordsize
= tdep
->wordsize
;
2968 if ((*this_cache
) != NULL
)
2969 return (*this_cache
);
2970 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
2971 (*this_cache
) = cache
;
2972 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2974 func
= frame_func_unwind (next_frame
);
2975 pc
= frame_pc_unwind (next_frame
);
2976 skip_prologue (func
, pc
, &fdata
);
2978 /* Figure out the parent's stack pointer. */
2980 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2981 address of the current frame. Things might be easier if the
2982 ->frame pointed to the outer-most address of the frame. In
2983 the mean time, the address of the prev frame is used as the
2984 base address of this frame. */
2985 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
2987 /* If the function appears to be frameless, check a couple of likely
2988 indicators that we have simply failed to find the frame setup.
2989 Two common cases of this are missing symbols (i.e.
2990 frame_func_unwind returns the wrong address or 0), and assembly
2991 stubs which have a fast exit path but set up a frame on the slow
2994 If the LR appears to return to this function, then presume that
2995 we have an ABI compliant frame that we failed to find. */
2996 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3001 saved_lr
= frame_unwind_register_unsigned (next_frame
,
3002 tdep
->ppc_lr_regnum
);
3003 if (func
== 0 && saved_lr
== pc
)
3007 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3008 if (func
== saved_func
)
3014 fdata
.frameless
= 0;
3015 fdata
.lr_offset
= wordsize
;
3019 if (!fdata
.frameless
)
3020 /* Frameless really means stackless. */
3021 cache
->base
= read_memory_addr (cache
->base
, wordsize
);
3023 trad_frame_set_value (cache
->saved_regs
, SP_REGNUM
, cache
->base
);
3025 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3026 All fpr's from saved_fpr to fp31 are saved. */
3028 if (fdata
.saved_fpr
>= 0)
3031 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3033 /* If skip_prologue says floating-point registers were saved,
3034 but the current architecture has no floating-point registers,
3035 then that's strange. But we have no indices to even record
3036 the addresses under, so we just ignore it. */
3037 if (ppc_floating_point_unit_p (gdbarch
))
3038 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3040 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3045 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3046 All gpr's from saved_gpr to gpr31 are saved. */
3048 if (fdata
.saved_gpr
>= 0)
3051 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3052 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3054 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3055 gpr_addr
+= wordsize
;
3059 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3060 All vr's from saved_vr to vr31 are saved. */
3061 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3063 if (fdata
.saved_vr
>= 0)
3066 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3067 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3069 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3070 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3075 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3076 All vr's from saved_ev to ev31 are saved. ????? */
3077 if (tdep
->ppc_ev0_regnum
!= -1 && tdep
->ppc_ev31_regnum
!= -1)
3079 if (fdata
.saved_ev
>= 0)
3082 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3083 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3085 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3086 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
3087 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3092 /* If != 0, fdata.cr_offset is the offset from the frame that
3094 if (fdata
.cr_offset
!= 0)
3095 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
3097 /* If != 0, fdata.lr_offset is the offset from the frame that
3099 if (fdata
.lr_offset
!= 0)
3100 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
3101 /* The PC is found in the link register. */
3102 cache
->saved_regs
[PC_REGNUM
] = cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3104 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3105 holds the VRSAVE. */
3106 if (fdata
.vrsave_offset
!= 0)
3107 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
3109 if (fdata
.alloca_reg
< 0)
3110 /* If no alloca register used, then fi->frame is the value of the
3111 %sp for this frame, and it is good enough. */
3112 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
3114 cache
->initial_sp
= frame_unwind_register_unsigned (next_frame
,
3121 rs6000_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
3122 struct frame_id
*this_id
)
3124 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3126 (*this_id
) = frame_id_build (info
->base
, frame_func_unwind (next_frame
));
3130 rs6000_frame_prev_register (struct frame_info
*next_frame
,
3132 int regnum
, int *optimizedp
,
3133 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
3134 int *realnump
, gdb_byte
*valuep
)
3136 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3138 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
3139 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
3142 static const struct frame_unwind rs6000_frame_unwind
=
3145 rs6000_frame_this_id
,
3146 rs6000_frame_prev_register
3149 static const struct frame_unwind
*
3150 rs6000_frame_sniffer (struct frame_info
*next_frame
)
3152 return &rs6000_frame_unwind
;
3158 rs6000_frame_base_address (struct frame_info
*next_frame
,
3161 struct rs6000_frame_cache
*info
= rs6000_frame_cache (next_frame
,
3163 return info
->initial_sp
;
3166 static const struct frame_base rs6000_frame_base
= {
3167 &rs6000_frame_unwind
,
3168 rs6000_frame_base_address
,
3169 rs6000_frame_base_address
,
3170 rs6000_frame_base_address
3173 static const struct frame_base
*
3174 rs6000_frame_base_sniffer (struct frame_info
*next_frame
)
3176 return &rs6000_frame_base
;
3179 /* Initialize the current architecture based on INFO. If possible, re-use an
3180 architecture from ARCHES, which is a list of architectures already created
3181 during this debugging session.
3183 Called e.g. at program startup, when reading a core file, and when reading
3186 static struct gdbarch
*
3187 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3189 struct gdbarch
*gdbarch
;
3190 struct gdbarch_tdep
*tdep
;
3191 int wordsize
, from_xcoff_exec
, from_elf_exec
, i
, off
;
3193 const struct variant
*v
;
3194 enum bfd_architecture arch
;
3200 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3201 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
3203 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3204 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3206 sysv_abi
= info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3208 /* Check word size. If INFO is from a binary file, infer it from
3209 that, else choose a likely default. */
3210 if (from_xcoff_exec
)
3212 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
3217 else if (from_elf_exec
)
3219 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
3226 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
3227 wordsize
= info
.bfd_arch_info
->bits_per_word
/
3228 info
.bfd_arch_info
->bits_per_byte
;
3233 /* Find a candidate among extant architectures. */
3234 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3236 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3238 /* Word size in the various PowerPC bfd_arch_info structs isn't
3239 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3240 separate word size check. */
3241 tdep
= gdbarch_tdep (arches
->gdbarch
);
3242 if (tdep
&& tdep
->wordsize
== wordsize
)
3243 return arches
->gdbarch
;
3246 /* None found, create a new architecture from INFO, whose bfd_arch_info
3247 validity depends on the source:
3248 - executable useless
3249 - rs6000_host_arch() good
3251 - "set arch" trust blindly
3252 - GDB startup useless but harmless */
3254 if (!from_xcoff_exec
)
3256 arch
= info
.bfd_arch_info
->arch
;
3257 mach
= info
.bfd_arch_info
->mach
;
3261 arch
= bfd_arch_powerpc
;
3262 bfd_default_set_arch_mach (&abfd
, arch
, 0);
3263 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3264 mach
= info
.bfd_arch_info
->mach
;
3266 tdep
= xmalloc (sizeof (struct gdbarch_tdep
));
3267 tdep
->wordsize
= wordsize
;
3269 /* For e500 executables, the apuinfo section is of help here. Such
3270 section contains the identifier and revision number of each
3271 Application-specific Processing Unit that is present on the
3272 chip. The content of the section is determined by the assembler
3273 which looks at each instruction and determines which unit (and
3274 which version of it) can execute it. In our case we just look for
3275 the existance of the section. */
3279 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
3282 arch
= info
.bfd_arch_info
->arch
;
3283 mach
= bfd_mach_ppc_e500
;
3284 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
3285 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3289 gdbarch
= gdbarch_alloc (&info
, tdep
);
3291 /* Initialize the number of real and pseudo registers in each variant. */
3294 /* Choose variant. */
3295 v
= find_variant_by_arch (arch
, mach
);
3299 tdep
->regs
= v
->regs
;
3301 tdep
->ppc_gp0_regnum
= 0;
3302 tdep
->ppc_toc_regnum
= 2;
3303 tdep
->ppc_ps_regnum
= 65;
3304 tdep
->ppc_cr_regnum
= 66;
3305 tdep
->ppc_lr_regnum
= 67;
3306 tdep
->ppc_ctr_regnum
= 68;
3307 tdep
->ppc_xer_regnum
= 69;
3308 if (v
->mach
== bfd_mach_ppc_601
)
3309 tdep
->ppc_mq_regnum
= 124;
3310 else if (arch
== bfd_arch_rs6000
)
3311 tdep
->ppc_mq_regnum
= 70;
3313 tdep
->ppc_mq_regnum
= -1;
3314 tdep
->ppc_fp0_regnum
= 32;
3315 tdep
->ppc_fpscr_regnum
= (arch
== bfd_arch_rs6000
) ? 71 : 70;
3316 tdep
->ppc_sr0_regnum
= 71;
3317 tdep
->ppc_vr0_regnum
= -1;
3318 tdep
->ppc_vrsave_regnum
= -1;
3319 tdep
->ppc_ev0_upper_regnum
= -1;
3320 tdep
->ppc_ev0_regnum
= -1;
3321 tdep
->ppc_ev31_regnum
= -1;
3322 tdep
->ppc_acc_regnum
= -1;
3323 tdep
->ppc_spefscr_regnum
= -1;
3325 set_gdbarch_pc_regnum (gdbarch
, 64);
3326 set_gdbarch_sp_regnum (gdbarch
, 1);
3327 set_gdbarch_deprecated_fp_regnum (gdbarch
, 1);
3328 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
3329 if (sysv_abi
&& wordsize
== 8)
3330 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
3331 else if (sysv_abi
&& wordsize
== 4)
3332 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
3335 set_gdbarch_deprecated_extract_return_value (gdbarch
, rs6000_extract_return_value
);
3336 set_gdbarch_store_return_value (gdbarch
, rs6000_store_return_value
);
3339 /* Set lr_frame_offset. */
3341 tdep
->lr_frame_offset
= 16;
3343 tdep
->lr_frame_offset
= 4;
3345 tdep
->lr_frame_offset
= 8;
3347 if (v
->arch
== bfd_arch_rs6000
)
3348 tdep
->ppc_sr0_regnum
= -1;
3349 else if (v
->arch
== bfd_arch_powerpc
)
3353 tdep
->ppc_sr0_regnum
= -1;
3354 tdep
->ppc_vr0_regnum
= 71;
3355 tdep
->ppc_vrsave_regnum
= 104;
3357 case bfd_mach_ppc_7400
:
3358 tdep
->ppc_vr0_regnum
= 119;
3359 tdep
->ppc_vrsave_regnum
= 152;
3361 case bfd_mach_ppc_e500
:
3362 tdep
->ppc_toc_regnum
= -1;
3363 tdep
->ppc_ev0_upper_regnum
= 32;
3364 tdep
->ppc_ev0_regnum
= 73;
3365 tdep
->ppc_ev31_regnum
= 104;
3366 tdep
->ppc_acc_regnum
= 71;
3367 tdep
->ppc_spefscr_regnum
= 72;
3368 tdep
->ppc_fp0_regnum
= -1;
3369 tdep
->ppc_fpscr_regnum
= -1;
3370 tdep
->ppc_sr0_regnum
= -1;
3371 set_gdbarch_pseudo_register_read (gdbarch
, e500_pseudo_register_read
);
3372 set_gdbarch_pseudo_register_write (gdbarch
, e500_pseudo_register_write
);
3373 set_gdbarch_register_reggroup_p (gdbarch
, e500_register_reggroup_p
);
3376 case bfd_mach_ppc64
:
3377 case bfd_mach_ppc_620
:
3378 case bfd_mach_ppc_630
:
3379 case bfd_mach_ppc_a35
:
3380 case bfd_mach_ppc_rs64ii
:
3381 case bfd_mach_ppc_rs64iii
:
3382 /* These processor's register sets don't have segment registers. */
3383 tdep
->ppc_sr0_regnum
= -1;
3387 internal_error (__FILE__
, __LINE__
,
3388 _("rs6000_gdbarch_init: "
3389 "received unexpected BFD 'arch' value"));
3391 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3393 /* Sanity check on registers. */
3394 gdb_assert (strcmp (tdep
->regs
[tdep
->ppc_gp0_regnum
].name
, "r0") == 0);
3396 /* Select instruction printer. */
3397 if (arch
== bfd_arch_rs6000
)
3398 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
3400 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
3402 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
3404 set_gdbarch_num_regs (gdbarch
, v
->nregs
);
3405 set_gdbarch_num_pseudo_regs (gdbarch
, v
->npregs
);
3406 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
3407 set_gdbarch_register_type (gdbarch
, rs6000_register_type
);
3408 set_gdbarch_register_reggroup_p (gdbarch
, rs6000_register_reggroup_p
);
3410 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3411 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3412 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3413 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3414 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3415 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3416 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3418 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3420 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3421 set_gdbarch_char_signed (gdbarch
, 0);
3423 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
3424 if (sysv_abi
&& wordsize
== 8)
3426 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
3427 else if (!sysv_abi
&& wordsize
== 4)
3428 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3429 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3430 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3432 set_gdbarch_frame_red_zone_size (gdbarch
, 224);
3434 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
3435 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
3436 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
3438 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
3439 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
3440 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
3441 is correct for the SysV ABI when the wordsize is 8, but I'm also
3442 fairly certain that ppc_sysv_abi_push_arguments() will give even
3443 worse results since it only works for 32-bit code. So, for the moment,
3444 we're better off calling rs6000_push_arguments() since it works for
3445 64-bit code. At some point in the future, this matter needs to be
3447 if (sysv_abi
&& wordsize
== 4)
3448 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
3449 else if (sysv_abi
&& wordsize
== 8)
3450 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
3452 set_gdbarch_push_dummy_call (gdbarch
, rs6000_push_dummy_call
);
3454 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, rs6000_extract_struct_value_address
);
3456 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
3457 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
3459 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3460 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
3462 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3463 for the descriptor and ".FN" for the entry-point -- a user
3464 specifying "break FN" will unexpectedly end up with a breakpoint
3465 on the descriptor and not the function. This architecture method
3466 transforms any breakpoints on descriptors into breakpoints on the
3467 corresponding entry point. */
3468 if (sysv_abi
&& wordsize
== 8)
3469 set_gdbarch_adjust_breakpoint_address (gdbarch
, ppc64_sysv_abi_adjust_breakpoint_address
);
3471 /* Not sure on this. FIXMEmgo */
3472 set_gdbarch_frame_args_skip (gdbarch
, 8);
3475 set_gdbarch_deprecated_use_struct_convention (gdbarch
, rs6000_use_struct_convention
);
3479 /* Handle RS/6000 function pointers (which are really function
3481 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
3482 rs6000_convert_from_func_ptr_addr
);
3485 /* Helpers for function argument information. */
3486 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
3488 /* Hook in ABI-specific overrides, if they have been registered. */
3489 gdbarch_init_osabi (info
, gdbarch
);
3493 case GDB_OSABI_LINUX
:
3494 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
3495 have altivec registers. If not, ptrace will fail the first time it's
3496 called to access one and will not be called again. This wart will
3497 be removed when Daniel Jacobowitz's proposal for autodetecting target
3498 registers is implemented. */
3499 if ((v
->arch
== bfd_arch_powerpc
) && ((v
->mach
)== bfd_mach_ppc64
))
3501 tdep
->ppc_vr0_regnum
= 71;
3502 tdep
->ppc_vrsave_regnum
= 104;
3505 case GDB_OSABI_NETBSD_AOUT
:
3506 case GDB_OSABI_NETBSD_ELF
:
3507 case GDB_OSABI_UNKNOWN
:
3508 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3509 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3510 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3511 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3514 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3516 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3517 frame_unwind_append_sniffer (gdbarch
, rs6000_frame_sniffer
);
3518 set_gdbarch_unwind_dummy_id (gdbarch
, rs6000_unwind_dummy_id
);
3519 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3522 init_sim_regno_table (gdbarch
);
3528 rs6000_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
3530 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3535 /* FIXME: Dump gdbarch_tdep. */
3538 /* Initialization code. */
3540 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
3543 _initialize_rs6000_tdep (void)
3545 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3546 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);