1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
54 #include "solib-svr4.h"
57 #include "gdb_assert.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "features/rs6000/powerpc-32.c"
65 #include "features/rs6000/powerpc-altivec32.c"
66 #include "features/rs6000/powerpc-403.c"
67 #include "features/rs6000/powerpc-403gc.c"
68 #include "features/rs6000/powerpc-505.c"
69 #include "features/rs6000/powerpc-601.c"
70 #include "features/rs6000/powerpc-602.c"
71 #include "features/rs6000/powerpc-603.c"
72 #include "features/rs6000/powerpc-604.c"
73 #include "features/rs6000/powerpc-64.c"
74 #include "features/rs6000/powerpc-altivec64.c"
75 #include "features/rs6000/powerpc-7400.c"
76 #include "features/rs6000/powerpc-750.c"
77 #include "features/rs6000/powerpc-860.c"
78 #include "features/rs6000/powerpc-e500.c"
79 #include "features/rs6000/rs6000.c"
81 /* Determine if regnum is an SPE pseudo-register. */
82 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
83 && (regnum) >= (tdep)->ppc_ev0_regnum \
84 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
86 /* Determine if regnum is a decimal float pseudo-register. */
87 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
88 && (regnum) >= (tdep)->ppc_dl0_regnum \
89 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
91 /* The list of available "set powerpc ..." and "show powerpc ..."
93 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
94 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
96 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
98 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
99 static const char *powerpc_vector_strings
[] =
108 /* A variable that can be configured by the user. */
109 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
110 static const char *powerpc_vector_abi_string
= "auto";
112 /* To be used by skip_prologue. */
114 struct rs6000_framedata
116 int offset
; /* total size of frame --- the distance
117 by which we decrement sp to allocate
119 int saved_gpr
; /* smallest # of saved gpr */
120 int saved_fpr
; /* smallest # of saved fpr */
121 int saved_vr
; /* smallest # of saved vr */
122 int saved_ev
; /* smallest # of saved ev */
123 int alloca_reg
; /* alloca register number (frame ptr) */
124 char frameless
; /* true if frameless functions. */
125 char nosavedpc
; /* true if pc not saved. */
126 int gpr_offset
; /* offset of saved gprs from prev sp */
127 int fpr_offset
; /* offset of saved fprs from prev sp */
128 int vr_offset
; /* offset of saved vrs from prev sp */
129 int ev_offset
; /* offset of saved evs from prev sp */
130 int lr_offset
; /* offset of saved lr */
131 int cr_offset
; /* offset of saved cr */
132 int vrsave_offset
; /* offset of saved vrsave register */
136 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
138 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
140 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
141 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
144 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
148 /* Return true if REGNO is an SPE register, false otherwise. */
150 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
154 /* Is it a reference to EV0 -- EV31, and do we have those? */
155 if (IS_SPE_PSEUDOREG (tdep
, regno
))
158 /* Is it a reference to one of the raw upper GPR halves? */
159 if (tdep
->ppc_ev0_upper_regnum
>= 0
160 && tdep
->ppc_ev0_upper_regnum
<= regno
161 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
164 /* Is it a reference to the 64-bit accumulator, and do we have that? */
165 if (tdep
->ppc_acc_regnum
>= 0
166 && tdep
->ppc_acc_regnum
== regno
)
169 /* Is it a reference to the SPE floating-point status and control register,
170 and do we have that? */
171 if (tdep
->ppc_spefscr_regnum
>= 0
172 && tdep
->ppc_spefscr_regnum
== regno
)
179 /* Return non-zero if the architecture described by GDBARCH has
180 floating-point registers (f0 --- f31 and fpscr). */
182 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
184 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
186 return (tdep
->ppc_fp0_regnum
>= 0
187 && tdep
->ppc_fpscr_regnum
>= 0);
190 /* Return non-zero if the architecture described by GDBARCH has
191 Altivec registers (vr0 --- vr31, vrsave and vscr). */
193 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
195 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
197 return (tdep
->ppc_vr0_regnum
>= 0
198 && tdep
->ppc_vrsave_regnum
>= 0);
201 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
204 This is a helper function for init_sim_regno_table, constructing
205 the table mapping GDB register numbers to sim register numbers; we
206 initialize every element in that table to -1 before we start
209 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
211 /* Make sure we don't try to assign any given GDB register a sim
212 register number more than once. */
213 gdb_assert (table
[gdb_regno
] == -1);
214 table
[gdb_regno
] = sim_regno
;
218 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
219 numbers to simulator register numbers, based on the values placed
220 in the ARCH->tdep->ppc_foo_regnum members. */
222 init_sim_regno_table (struct gdbarch
*arch
)
224 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
225 int total_regs
= gdbarch_num_regs (arch
);
226 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
228 static const char *const segment_regs
[] = {
229 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
230 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
233 /* Presume that all registers not explicitly mentioned below are
234 unavailable from the sim. */
235 for (i
= 0; i
< total_regs
; i
++)
238 /* General-purpose registers. */
239 for (i
= 0; i
< ppc_num_gprs
; i
++)
240 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
242 /* Floating-point registers. */
243 if (tdep
->ppc_fp0_regnum
>= 0)
244 for (i
= 0; i
< ppc_num_fprs
; i
++)
245 set_sim_regno (sim_regno
,
246 tdep
->ppc_fp0_regnum
+ i
,
247 sim_ppc_f0_regnum
+ i
);
248 if (tdep
->ppc_fpscr_regnum
>= 0)
249 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
251 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
252 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
253 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
255 /* Segment registers. */
256 for (i
= 0; i
< ppc_num_srs
; i
++)
260 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
262 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
265 /* Altivec registers. */
266 if (tdep
->ppc_vr0_regnum
>= 0)
268 for (i
= 0; i
< ppc_num_vrs
; i
++)
269 set_sim_regno (sim_regno
,
270 tdep
->ppc_vr0_regnum
+ i
,
271 sim_ppc_vr0_regnum
+ i
);
273 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
274 we can treat this more like the other cases. */
275 set_sim_regno (sim_regno
,
276 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
277 sim_ppc_vscr_regnum
);
279 /* vsave is a special-purpose register, so the code below handles it. */
281 /* SPE APU (E500) registers. */
282 if (tdep
->ppc_ev0_upper_regnum
>= 0)
283 for (i
= 0; i
< ppc_num_gprs
; i
++)
284 set_sim_regno (sim_regno
,
285 tdep
->ppc_ev0_upper_regnum
+ i
,
286 sim_ppc_rh0_regnum
+ i
);
287 if (tdep
->ppc_acc_regnum
>= 0)
288 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
289 /* spefscr is a special-purpose register, so the code below handles it. */
292 /* Now handle all special-purpose registers. Verify that they
293 haven't mistakenly been assigned numbers by any of the above
295 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
297 const char *spr_name
= sim_spr_register_name (i
);
300 if (spr_name
!= NULL
)
301 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
304 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
308 /* Drop the initialized array into place. */
309 tdep
->sim_regno
= sim_regno
;
313 /* Given a GDB register number REG, return the corresponding SIM
316 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
318 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
321 if (tdep
->sim_regno
== NULL
)
322 init_sim_regno_table (gdbarch
);
325 && reg
<= gdbarch_num_regs (gdbarch
)
326 + gdbarch_num_pseudo_regs (gdbarch
));
327 sim_regno
= tdep
->sim_regno
[reg
];
332 return LEGACY_SIM_REGNO_IGNORE
;
337 /* Register set support functions. */
339 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
340 Write the register to REGCACHE. */
343 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
344 const gdb_byte
*regs
, size_t offset
, int regsize
)
346 if (regnum
!= -1 && offset
!= -1)
350 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
351 int gdb_regsize
= register_size (gdbarch
, regnum
);
352 if (gdb_regsize
< regsize
353 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
354 offset
+= regsize
- gdb_regsize
;
356 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
360 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
361 in a field REGSIZE wide. Zero pad as necessary. */
364 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
365 gdb_byte
*regs
, size_t offset
, int regsize
)
367 if (regnum
!= -1 && offset
!= -1)
371 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
372 int gdb_regsize
= register_size (gdbarch
, regnum
);
373 if (gdb_regsize
< regsize
)
375 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
377 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
378 offset
+= regsize
- gdb_regsize
;
381 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
382 regsize
- gdb_regsize
);
385 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
390 ppc_greg_offset (struct gdbarch
*gdbarch
,
391 struct gdbarch_tdep
*tdep
,
392 const struct ppc_reg_offsets
*offsets
,
396 *regsize
= offsets
->gpr_size
;
397 if (regnum
>= tdep
->ppc_gp0_regnum
398 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
399 return (offsets
->r0_offset
400 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
402 if (regnum
== gdbarch_pc_regnum (gdbarch
))
403 return offsets
->pc_offset
;
405 if (regnum
== tdep
->ppc_ps_regnum
)
406 return offsets
->ps_offset
;
408 if (regnum
== tdep
->ppc_lr_regnum
)
409 return offsets
->lr_offset
;
411 if (regnum
== tdep
->ppc_ctr_regnum
)
412 return offsets
->ctr_offset
;
414 *regsize
= offsets
->xr_size
;
415 if (regnum
== tdep
->ppc_cr_regnum
)
416 return offsets
->cr_offset
;
418 if (regnum
== tdep
->ppc_xer_regnum
)
419 return offsets
->xer_offset
;
421 if (regnum
== tdep
->ppc_mq_regnum
)
422 return offsets
->mq_offset
;
428 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
429 const struct ppc_reg_offsets
*offsets
,
432 if (regnum
>= tdep
->ppc_fp0_regnum
433 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
434 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
436 if (regnum
== tdep
->ppc_fpscr_regnum
)
437 return offsets
->fpscr_offset
;
443 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
444 const struct ppc_reg_offsets
*offsets
,
447 if (regnum
>= tdep
->ppc_vr0_regnum
448 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
449 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
451 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
452 return offsets
->vscr_offset
;
454 if (regnum
== tdep
->ppc_vrsave_regnum
)
455 return offsets
->vrsave_offset
;
460 /* Supply register REGNUM in the general-purpose register set REGSET
461 from the buffer specified by GREGS and LEN to register cache
462 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
465 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
466 int regnum
, const void *gregs
, size_t len
)
468 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
469 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
470 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
477 int gpr_size
= offsets
->gpr_size
;
479 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
480 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
481 i
++, offset
+= gpr_size
)
482 ppc_supply_reg (regcache
, i
, gregs
, offset
, gpr_size
);
484 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
485 gregs
, offsets
->pc_offset
, gpr_size
);
486 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
487 gregs
, offsets
->ps_offset
, gpr_size
);
488 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
489 gregs
, offsets
->lr_offset
, gpr_size
);
490 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
491 gregs
, offsets
->ctr_offset
, gpr_size
);
492 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
493 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
494 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
495 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
496 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
497 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
501 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
502 ppc_supply_reg (regcache
, regnum
, gregs
, offset
, regsize
);
505 /* Supply register REGNUM in the floating-point register set REGSET
506 from the buffer specified by FPREGS and LEN to register cache
507 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
510 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
511 int regnum
, const void *fpregs
, size_t len
)
513 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
514 struct gdbarch_tdep
*tdep
;
515 const struct ppc_reg_offsets
*offsets
;
518 if (!ppc_floating_point_unit_p (gdbarch
))
521 tdep
= gdbarch_tdep (gdbarch
);
522 offsets
= regset
->descr
;
527 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
528 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
530 ppc_supply_reg (regcache
, i
, fpregs
, offset
, 8);
532 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
533 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
537 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
538 ppc_supply_reg (regcache
, regnum
, fpregs
, offset
,
539 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
542 /* Supply register REGNUM in the Altivec register set REGSET
543 from the buffer specified by VRREGS and LEN to register cache
544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
547 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
548 int regnum
, const void *vrregs
, size_t len
)
550 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
551 struct gdbarch_tdep
*tdep
;
552 const struct ppc_reg_offsets
*offsets
;
555 if (!ppc_altivec_support_p (gdbarch
))
558 tdep
= gdbarch_tdep (gdbarch
);
559 offsets
= regset
->descr
;
564 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
565 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
567 ppc_supply_reg (regcache
, i
, vrregs
, offset
, 16);
569 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
570 vrregs
, offsets
->vscr_offset
, 4);
572 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
573 vrregs
, offsets
->vrsave_offset
, 4);
577 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
578 if (regnum
!= tdep
->ppc_vrsave_regnum
579 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
580 ppc_supply_reg (regcache
, regnum
, vrregs
, offset
, 16);
582 ppc_supply_reg (regcache
, regnum
,
586 /* Collect register REGNUM in the general-purpose register set
587 REGSET from register cache REGCACHE into the buffer specified by
588 GREGS and LEN. If REGNUM is -1, do this for all registers in
592 ppc_collect_gregset (const struct regset
*regset
,
593 const struct regcache
*regcache
,
594 int regnum
, void *gregs
, size_t len
)
596 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
597 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
598 const struct ppc_reg_offsets
*offsets
= regset
->descr
;
605 int gpr_size
= offsets
->gpr_size
;
607 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
608 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
609 i
++, offset
+= gpr_size
)
610 ppc_collect_reg (regcache
, i
, gregs
, offset
, gpr_size
);
612 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
613 gregs
, offsets
->pc_offset
, gpr_size
);
614 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
615 gregs
, offsets
->ps_offset
, gpr_size
);
616 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
617 gregs
, offsets
->lr_offset
, gpr_size
);
618 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
619 gregs
, offsets
->ctr_offset
, gpr_size
);
620 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
621 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
622 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
623 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
624 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
625 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
629 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
630 ppc_collect_reg (regcache
, regnum
, gregs
, offset
, regsize
);
633 /* Collect register REGNUM in the floating-point register set
634 REGSET from register cache REGCACHE into the buffer specified by
635 FPREGS and LEN. If REGNUM is -1, do this for all registers in
639 ppc_collect_fpregset (const struct regset
*regset
,
640 const struct regcache
*regcache
,
641 int regnum
, void *fpregs
, size_t len
)
643 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
644 struct gdbarch_tdep
*tdep
;
645 const struct ppc_reg_offsets
*offsets
;
648 if (!ppc_floating_point_unit_p (gdbarch
))
651 tdep
= gdbarch_tdep (gdbarch
);
652 offsets
= regset
->descr
;
657 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
658 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
660 ppc_collect_reg (regcache
, i
, fpregs
, offset
, 8);
662 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
663 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
667 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
668 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
,
669 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
672 /* Collect register REGNUM in the Altivec register set
673 REGSET from register cache REGCACHE into the buffer specified by
674 VRREGS and LEN. If REGNUM is -1, do this for all registers in
678 ppc_collect_vrregset (const struct regset
*regset
,
679 const struct regcache
*regcache
,
680 int regnum
, void *vrregs
, size_t len
)
682 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
683 struct gdbarch_tdep
*tdep
;
684 const struct ppc_reg_offsets
*offsets
;
687 if (!ppc_altivec_support_p (gdbarch
))
690 tdep
= gdbarch_tdep (gdbarch
);
691 offsets
= regset
->descr
;
696 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
697 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
699 ppc_collect_reg (regcache
, i
, vrregs
, offset
, 16);
701 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
702 vrregs
, offsets
->vscr_offset
, 4);
704 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
705 vrregs
, offsets
->vrsave_offset
, 4);
709 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
710 if (regnum
!= tdep
->ppc_vrsave_regnum
711 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
712 ppc_collect_reg (regcache
, regnum
, vrregs
, offset
, 16);
714 ppc_collect_reg (regcache
, regnum
,
720 insn_changes_sp_or_jumps (unsigned long insn
)
722 int opcode
= (insn
>> 26) & 0x03f;
723 int sd
= (insn
>> 21) & 0x01f;
724 int a
= (insn
>> 16) & 0x01f;
725 int subcode
= (insn
>> 1) & 0x3ff;
727 /* Changes the stack pointer. */
729 /* NOTE: There are many ways to change the value of a given register.
730 The ways below are those used when the register is R1, the SP,
731 in a funtion's epilogue. */
733 if (opcode
== 31 && subcode
== 444 && a
== 1)
734 return 1; /* mr R1,Rn */
735 if (opcode
== 14 && sd
== 1)
736 return 1; /* addi R1,Rn,simm */
737 if (opcode
== 58 && sd
== 1)
738 return 1; /* ld R1,ds(Rn) */
740 /* Transfers control. */
746 if (opcode
== 19 && subcode
== 16)
748 if (opcode
== 19 && subcode
== 528)
749 return 1; /* bcctr */
754 /* Return true if we are in the function's epilogue, i.e. after the
755 instruction that destroyed the function's stack frame.
757 1) scan forward from the point of execution:
758 a) If you find an instruction that modifies the stack pointer
759 or transfers control (except a return), execution is not in
761 b) Stop scanning if you find a return instruction or reach the
762 end of the function or reach the hard limit for the size of
764 2) scan backward from the point of execution:
765 a) If you find an instruction that modifies the stack pointer,
766 execution *is* in an epilogue, return.
767 b) Stop scanning if you reach an instruction that transfers
768 control or the beginning of the function or reach the hard
769 limit for the size of an epilogue. */
772 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
774 bfd_byte insn_buf
[PPC_INSN_SIZE
];
775 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
777 struct frame_info
*curfrm
;
779 /* Find the search limits based on function boundaries and hard limit. */
781 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
784 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
785 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
787 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
788 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
790 curfrm
= get_current_frame ();
792 /* Scan forward until next 'blr'. */
794 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
796 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
798 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
);
799 if (insn
== 0x4e800020)
801 if (insn_changes_sp_or_jumps (insn
))
805 /* Scan backward until adjustment to stack pointer (R1). */
807 for (scan_pc
= pc
- PPC_INSN_SIZE
;
808 scan_pc
>= epilogue_start
;
809 scan_pc
-= PPC_INSN_SIZE
)
811 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
813 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
);
814 if (insn_changes_sp_or_jumps (insn
))
821 /* Get the ith function argument for the current function. */
823 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
826 return get_frame_register_unsigned (frame
, 3 + argi
);
829 /* Sequence of bytes for breakpoint instruction. */
831 const static unsigned char *
832 rs6000_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
835 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
836 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
838 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
839 return big_breakpoint
;
841 return little_breakpoint
;
844 /* Instruction masks for displaced stepping. */
845 #define BRANCH_MASK 0xfc000000
846 #define BP_MASK 0xFC0007FE
847 #define B_INSN 0x48000000
848 #define BC_INSN 0x40000000
849 #define BXL_INSN 0x4c000000
850 #define BP_INSN 0x7C000008
852 /* Fix up the state of registers and memory after having single-stepped
853 a displaced instruction. */
855 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
856 struct displaced_step_closure
*closure
,
857 CORE_ADDR from
, CORE_ADDR to
,
858 struct regcache
*regs
)
860 /* Since we use simple_displaced_step_copy_insn, our closure is a
861 copy of the instruction. */
862 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
865 /* Offset for non PC-relative instructions. */
866 LONGEST offset
= PPC_INSN_SIZE
;
868 opcode
= insn
& BRANCH_MASK
;
871 fprintf_unfiltered (gdb_stdlog
,
872 "displaced: (ppc) fixup (0x%s, 0x%s)\n",
873 paddr_nz (from
), paddr_nz (to
));
876 /* Handle PC-relative branch instructions. */
877 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
881 /* Read the current PC value after the instruction has been executed
882 in a displaced location. Calculate the offset to be applied to the
883 original PC value before the displaced stepping. */
884 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
886 offset
= current_pc
- to
;
888 if (opcode
!= BXL_INSN
)
890 /* Check for AA bit indicating whether this is an absolute
891 addressing or PC-relative (1: absolute, 0: relative). */
894 /* PC-relative addressing is being used in the branch. */
898 "displaced: (ppc) branch instruction: 0x%s\n"
899 "displaced: (ppc) adjusted PC from 0x%s to 0x%s\n",
900 paddr_nz (insn
), paddr_nz (current_pc
),
901 paddr_nz (from
+ offset
));
903 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
909 /* If we're here, it means we have a branch to LR or CTR. If the
910 branch was taken, the offset is probably greater than 4 (the next
911 instruction), so it's safe to assume that an offset of 4 means we
912 did not take the branch. */
913 if (offset
== PPC_INSN_SIZE
)
914 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
915 from
+ PPC_INSN_SIZE
);
918 /* Check for LK bit indicating whether we should set the link
919 register to point to the next instruction
920 (1: Set, 0: Don't set). */
923 /* Link register needs to be set to the next instruction's PC. */
924 regcache_cooked_write_unsigned (regs
,
925 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
926 from
+ PPC_INSN_SIZE
);
928 fprintf_unfiltered (gdb_stdlog
,
929 "displaced: (ppc) adjusted LR to 0x%s\n",
930 paddr_nz (from
+ PPC_INSN_SIZE
));
934 /* Check for breakpoints in the inferior. If we've found one, place the PC
935 right at the breakpoint instruction. */
936 else if ((insn
& BP_MASK
) == BP_INSN
)
937 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
939 /* Handle any other instructions that do not fit in the categories above. */
940 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
944 /* Instruction masks used during single-stepping of atomic sequences. */
945 #define LWARX_MASK 0xfc0007fe
946 #define LWARX_INSTRUCTION 0x7c000028
947 #define LDARX_INSTRUCTION 0x7c0000A8
948 #define STWCX_MASK 0xfc0007ff
949 #define STWCX_INSTRUCTION 0x7c00012d
950 #define STDCX_INSTRUCTION 0x7c0001ad
952 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
953 instruction and ending with a STWCX/STDCX instruction. If such a sequence
954 is found, attempt to step through it. A breakpoint is placed at the end of
958 ppc_deal_with_atomic_sequence (struct frame_info
*frame
)
960 CORE_ADDR pc
= get_frame_pc (frame
);
961 CORE_ADDR breaks
[2] = {-1, -1};
963 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
964 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
967 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
968 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
969 int opcode
; /* Branch instruction's OPcode. */
970 int bc_insn_count
= 0; /* Conditional branch instruction count. */
972 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
973 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
974 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
977 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
979 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
981 loc
+= PPC_INSN_SIZE
;
982 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
984 /* Assume that there is at most one conditional branch in the atomic
985 sequence. If a conditional branch is found, put a breakpoint in
986 its destination address. */
987 if ((insn
& BRANCH_MASK
) == BC_INSN
)
989 int immediate
= ((insn
& ~3) << 16) >> 16;
990 int absolute
= ((insn
>> 1) & 1);
992 if (bc_insn_count
>= 1)
993 return 0; /* More than one conditional branch found, fallback
994 to the standard single-step code. */
997 breaks
[1] = immediate
;
999 breaks
[1] = pc
+ immediate
;
1005 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
1006 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
1010 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1011 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
1012 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
1016 loc
+= PPC_INSN_SIZE
;
1017 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
);
1019 /* Insert a breakpoint right after the end of the atomic sequence. */
1022 /* Check for duplicated breakpoints. Check also for a breakpoint
1023 placed (branch instruction's destination) at the stwcx/stdcx
1024 instruction, this resets the reservation and take us back to the
1025 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1026 if (last_breakpoint
&& ((breaks
[1] == breaks
[0])
1027 || (breaks
[1] == closing_insn
)))
1028 last_breakpoint
= 0;
1030 /* Effectively inserts the breakpoints. */
1031 for (index
= 0; index
<= last_breakpoint
; index
++)
1032 insert_single_step_breakpoint (breaks
[index
]);
1038 #define SIGNED_SHORT(x) \
1039 ((sizeof (short) == 2) \
1040 ? ((int)(short)(x)) \
1041 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1043 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1045 /* Limit the number of skipped non-prologue instructions, as the examining
1046 of the prologue is expensive. */
1047 static int max_skip_non_prologue_insns
= 10;
1049 /* Return nonzero if the given instruction OP can be part of the prologue
1050 of a function and saves a parameter on the stack. FRAMEP should be
1051 set if one of the previous instructions in the function has set the
1055 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1057 /* Move parameters from argument registers to temporary register. */
1058 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1060 /* Rx must be scratch register r0. */
1061 const int rx_regno
= (op
>> 16) & 31;
1062 /* Ry: Only r3 - r10 are used for parameter passing. */
1063 const int ry_regno
= GET_SRC_REG (op
);
1065 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1067 *r0_contains_arg
= 1;
1074 /* Save a General Purpose Register on stack. */
1076 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1077 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1079 /* Rx: Only r3 - r10 are used for parameter passing. */
1080 const int rx_regno
= GET_SRC_REG (op
);
1082 return (rx_regno
>= 3 && rx_regno
<= 10);
1085 /* Save a General Purpose Register on stack via the Frame Pointer. */
1088 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1089 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1090 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1092 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1093 However, the compiler sometimes uses r0 to hold an argument. */
1094 const int rx_regno
= GET_SRC_REG (op
);
1096 return ((rx_regno
>= 3 && rx_regno
<= 10)
1097 || (rx_regno
== 0 && *r0_contains_arg
));
1100 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1102 /* Only f2 - f8 are used for parameter passing. */
1103 const int src_regno
= GET_SRC_REG (op
);
1105 return (src_regno
>= 2 && src_regno
<= 8);
1108 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1110 /* Only f2 - f8 are used for parameter passing. */
1111 const int src_regno
= GET_SRC_REG (op
);
1113 return (src_regno
>= 2 && src_regno
<= 8);
1116 /* Not an insn that saves a parameter on stack. */
1120 /* Assuming that INSN is a "bl" instruction located at PC, return
1121 nonzero if the destination of the branch is a "blrl" instruction.
1123 This sequence is sometimes found in certain function prologues.
1124 It allows the function to load the LR register with a value that
1125 they can use to access PIC data using PC-relative offsets. */
1128 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
)
1135 absolute
= (int) ((insn
>> 1) & 1);
1136 immediate
= ((insn
& ~3) << 6) >> 6;
1140 dest
= pc
+ immediate
;
1142 dest_insn
= read_memory_integer (dest
, 4);
1143 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1149 /* Masks for decoding a branch-and-link (bl) instruction.
1151 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1152 The former is anded with the opcode in question; if the result of
1153 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1154 question is a ``bl'' instruction.
1156 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1157 the branch displacement. */
1159 #define BL_MASK 0xfc000001
1160 #define BL_INSTRUCTION 0x48000001
1161 #define BL_DISPLACEMENT_MASK 0x03fffffc
1163 /* return pc value after skipping a function prologue and also return
1164 information about a function frame.
1166 in struct rs6000_framedata fdata:
1167 - frameless is TRUE, if function does not have a frame.
1168 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1169 - offset is the initial size of this stack frame --- the amount by
1170 which we decrement the sp to allocate the frame.
1171 - saved_gpr is the number of the first saved gpr.
1172 - saved_fpr is the number of the first saved fpr.
1173 - saved_vr is the number of the first saved vr.
1174 - saved_ev is the number of the first saved ev.
1175 - alloca_reg is the number of the register used for alloca() handling.
1177 - gpr_offset is the offset of the first saved gpr from the previous frame.
1178 - fpr_offset is the offset of the first saved fpr from the previous frame.
1179 - vr_offset is the offset of the first saved vr from the previous frame.
1180 - ev_offset is the offset of the first saved ev from the previous frame.
1181 - lr_offset is the offset of the saved lr
1182 - cr_offset is the offset of the saved cr
1183 - vrsave_offset is the offset of the saved vrsave register
1187 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1188 struct rs6000_framedata
*fdata
)
1190 CORE_ADDR orig_pc
= pc
;
1191 CORE_ADDR last_prologue_pc
= pc
;
1192 CORE_ADDR li_found_pc
= 0;
1196 long vr_saved_offset
= 0;
1202 int vrsave_reg
= -1;
1205 int minimal_toc_loaded
= 0;
1206 int prev_insn_was_prologue_insn
= 1;
1207 int num_skip_non_prologue_insns
= 0;
1208 int r0_contains_arg
= 0;
1209 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1210 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1212 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1213 fdata
->saved_gpr
= -1;
1214 fdata
->saved_fpr
= -1;
1215 fdata
->saved_vr
= -1;
1216 fdata
->saved_ev
= -1;
1217 fdata
->alloca_reg
= -1;
1218 fdata
->frameless
= 1;
1219 fdata
->nosavedpc
= 1;
1223 /* Sometimes it isn't clear if an instruction is a prologue
1224 instruction or not. When we encounter one of these ambiguous
1225 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1226 Otherwise, we'll assume that it really is a prologue instruction. */
1227 if (prev_insn_was_prologue_insn
)
1228 last_prologue_pc
= pc
;
1230 /* Stop scanning if we've hit the limit. */
1234 prev_insn_was_prologue_insn
= 1;
1236 /* Fetch the instruction and convert it to an integer. */
1237 if (target_read_memory (pc
, buf
, 4))
1239 op
= extract_unsigned_integer (buf
, 4);
1241 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1243 /* Since shared library / PIC code, which needs to get its
1244 address at runtime, can appear to save more than one link
1258 remember just the first one, but skip over additional
1261 lr_reg
= (op
& 0x03e00000);
1263 r0_contains_arg
= 0;
1266 else if ((op
& 0xfc1fffff) == 0x7c000026)
1268 cr_reg
= (op
& 0x03e00000);
1270 r0_contains_arg
= 0;
1274 else if ((op
& 0xfc1f0000) == 0xd8010000)
1275 { /* stfd Rx,NUM(r1) */
1276 reg
= GET_SRC_REG (op
);
1277 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1279 fdata
->saved_fpr
= reg
;
1280 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1285 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1286 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1287 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1288 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1291 reg
= GET_SRC_REG (op
);
1292 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1294 fdata
->saved_gpr
= reg
;
1295 if ((op
& 0xfc1f0003) == 0xf8010000)
1297 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1302 else if ((op
& 0xffff0000) == 0x60000000)
1305 /* Allow nops in the prologue, but do not consider them to
1306 be part of the prologue unless followed by other prologue
1308 prev_insn_was_prologue_insn
= 0;
1312 else if ((op
& 0xffff0000) == 0x3c000000)
1313 { /* addis 0,0,NUM, used
1314 for >= 32k frames */
1315 fdata
->offset
= (op
& 0x0000ffff) << 16;
1316 fdata
->frameless
= 0;
1317 r0_contains_arg
= 0;
1321 else if ((op
& 0xffff0000) == 0x60000000)
1322 { /* ori 0,0,NUM, 2nd ha
1323 lf of >= 32k frames */
1324 fdata
->offset
|= (op
& 0x0000ffff);
1325 fdata
->frameless
= 0;
1326 r0_contains_arg
= 0;
1330 else if (lr_reg
>= 0 &&
1331 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1332 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1333 /* stw Rx, NUM(r1) */
1334 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1335 /* stwu Rx, NUM(r1) */
1336 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1337 { /* where Rx == lr */
1338 fdata
->lr_offset
= offset
;
1339 fdata
->nosavedpc
= 0;
1340 /* Invalidate lr_reg, but don't set it to -1.
1341 That would mean that it had never been set. */
1343 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1344 (op
& 0xfc000000) == 0x90000000) /* stw */
1346 /* Does not update r1, so add displacement to lr_offset. */
1347 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1352 else if (cr_reg
>= 0 &&
1353 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1354 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1355 /* stw Rx, NUM(r1) */
1356 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1357 /* stwu Rx, NUM(r1) */
1358 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1359 { /* where Rx == cr */
1360 fdata
->cr_offset
= offset
;
1361 /* Invalidate cr_reg, but don't set it to -1.
1362 That would mean that it had never been set. */
1364 if ((op
& 0xfc000003) == 0xf8000000 ||
1365 (op
& 0xfc000000) == 0x90000000)
1367 /* Does not update r1, so add displacement to cr_offset. */
1368 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1373 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1375 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1376 prediction bits. If the LR has already been saved, we can
1380 else if (op
== 0x48000005)
1386 else if (op
== 0x48000004)
1391 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1392 in V.4 -mminimal-toc */
1393 (op
& 0xffff0000) == 0x3bde0000)
1394 { /* addi 30,30,foo@l */
1398 else if ((op
& 0xfc000001) == 0x48000001)
1402 fdata
->frameless
= 0;
1404 /* If the return address has already been saved, we can skip
1405 calls to blrl (for PIC). */
1406 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
))
1409 /* Don't skip over the subroutine call if it is not within
1410 the first three instructions of the prologue and either
1411 we have no line table information or the line info tells
1412 us that the subroutine call is not part of the line
1413 associated with the prologue. */
1414 if ((pc
- orig_pc
) > 8)
1416 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1417 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1419 if ((prologue_sal
.line
== 0) || (prologue_sal
.line
!= this_sal
.line
))
1423 op
= read_memory_integer (pc
+ 4, 4);
1425 /* At this point, make sure this is not a trampoline
1426 function (a function that simply calls another functions,
1427 and nothing else). If the next is not a nop, this branch
1428 was part of the function prologue. */
1430 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1431 break; /* don't skip over
1436 /* update stack pointer */
1437 else if ((op
& 0xfc1f0000) == 0x94010000)
1438 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1439 fdata
->frameless
= 0;
1440 fdata
->offset
= SIGNED_SHORT (op
);
1441 offset
= fdata
->offset
;
1444 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1445 { /* stwux rX,r1,rY */
1446 /* no way to figure out what r1 is going to be */
1447 fdata
->frameless
= 0;
1448 offset
= fdata
->offset
;
1451 else if ((op
& 0xfc1f0003) == 0xf8010001)
1452 { /* stdu rX,NUM(r1) */
1453 fdata
->frameless
= 0;
1454 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1455 offset
= fdata
->offset
;
1458 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1459 { /* stdux rX,r1,rY */
1460 /* no way to figure out what r1 is going to be */
1461 fdata
->frameless
= 0;
1462 offset
= fdata
->offset
;
1465 else if ((op
& 0xffff0000) == 0x38210000)
1466 { /* addi r1,r1,SIMM */
1467 fdata
->frameless
= 0;
1468 fdata
->offset
+= SIGNED_SHORT (op
);
1469 offset
= fdata
->offset
;
1472 /* Load up minimal toc pointer. Do not treat an epilogue restore
1473 of r31 as a minimal TOC load. */
1474 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1475 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1477 && !minimal_toc_loaded
)
1479 minimal_toc_loaded
= 1;
1482 /* move parameters from argument registers to local variable
1485 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1486 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1487 (((op
>> 21) & 31) <= 10) &&
1488 ((long) ((op
>> 16) & 31) >= fdata
->saved_gpr
)) /* Rx: local var reg */
1492 /* store parameters in stack */
1494 /* Move parameters from argument registers to temporary register. */
1495 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1499 /* Set up frame pointer */
1501 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1502 || op
== 0x7c3f0b78)
1504 fdata
->frameless
= 0;
1506 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1509 /* Another way to set up the frame pointer. */
1511 else if ((op
& 0xfc1fffff) == 0x38010000)
1512 { /* addi rX, r1, 0x0 */
1513 fdata
->frameless
= 0;
1515 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1516 + ((op
& ~0x38010000) >> 21));
1519 /* AltiVec related instructions. */
1520 /* Store the vrsave register (spr 256) in another register for
1521 later manipulation, or load a register into the vrsave
1522 register. 2 instructions are used: mfvrsave and
1523 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1524 and mtspr SPR256, Rn. */
1525 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1526 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1527 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1529 vrsave_reg
= GET_SRC_REG (op
);
1532 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1536 /* Store the register where vrsave was saved to onto the stack:
1537 rS is the register where vrsave was stored in a previous
1539 /* 100100 sssss 00001 dddddddd dddddddd */
1540 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1542 if (vrsave_reg
== GET_SRC_REG (op
))
1544 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1549 /* Compute the new value of vrsave, by modifying the register
1550 where vrsave was saved to. */
1551 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1552 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1556 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1557 in a pair of insns to save the vector registers on the
1559 /* 001110 00000 00000 iiii iiii iiii iiii */
1560 /* 001110 01110 00000 iiii iiii iiii iiii */
1561 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1562 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1564 if ((op
& 0xffff0000) == 0x38000000)
1565 r0_contains_arg
= 0;
1567 vr_saved_offset
= SIGNED_SHORT (op
);
1569 /* This insn by itself is not part of the prologue, unless
1570 if part of the pair of insns mentioned above. So do not
1571 record this insn as part of the prologue yet. */
1572 prev_insn_was_prologue_insn
= 0;
1574 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1575 /* 011111 sssss 11111 00000 00111001110 */
1576 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1578 if (pc
== (li_found_pc
+ 4))
1580 vr_reg
= GET_SRC_REG (op
);
1581 /* If this is the first vector reg to be saved, or if
1582 it has a lower number than others previously seen,
1583 reupdate the frame info. */
1584 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1586 fdata
->saved_vr
= vr_reg
;
1587 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1589 vr_saved_offset
= -1;
1594 /* End AltiVec related instructions. */
1596 /* Start BookE related instructions. */
1597 /* Store gen register S at (r31+uimm).
1598 Any register less than r13 is volatile, so we don't care. */
1599 /* 000100 sssss 11111 iiiii 01100100001 */
1600 else if (arch_info
->mach
== bfd_mach_ppc_e500
1601 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1603 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1606 ev_reg
= GET_SRC_REG (op
);
1607 imm
= (op
>> 11) & 0x1f;
1608 ev_offset
= imm
* 8;
1609 /* If this is the first vector reg to be saved, or if
1610 it has a lower number than others previously seen,
1611 reupdate the frame info. */
1612 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1614 fdata
->saved_ev
= ev_reg
;
1615 fdata
->ev_offset
= ev_offset
+ offset
;
1620 /* Store gen register rS at (r1+rB). */
1621 /* 000100 sssss 00001 bbbbb 01100100000 */
1622 else if (arch_info
->mach
== bfd_mach_ppc_e500
1623 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1625 if (pc
== (li_found_pc
+ 4))
1627 ev_reg
= GET_SRC_REG (op
);
1628 /* If this is the first vector reg to be saved, or if
1629 it has a lower number than others previously seen,
1630 reupdate the frame info. */
1631 /* We know the contents of rB from the previous instruction. */
1632 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1634 fdata
->saved_ev
= ev_reg
;
1635 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1637 vr_saved_offset
= -1;
1643 /* Store gen register r31 at (rA+uimm). */
1644 /* 000100 11111 aaaaa iiiii 01100100001 */
1645 else if (arch_info
->mach
== bfd_mach_ppc_e500
1646 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1648 /* Wwe know that the source register is 31 already, but
1649 it can't hurt to compute it. */
1650 ev_reg
= GET_SRC_REG (op
);
1651 ev_offset
= ((op
>> 11) & 0x1f) * 8;
1652 /* If this is the first vector reg to be saved, or if
1653 it has a lower number than others previously seen,
1654 reupdate the frame info. */
1655 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1657 fdata
->saved_ev
= ev_reg
;
1658 fdata
->ev_offset
= ev_offset
+ offset
;
1663 /* Store gen register S at (r31+r0).
1664 Store param on stack when offset from SP bigger than 4 bytes. */
1665 /* 000100 sssss 11111 00000 01100100000 */
1666 else if (arch_info
->mach
== bfd_mach_ppc_e500
1667 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1669 if (pc
== (li_found_pc
+ 4))
1671 if ((op
& 0x03e00000) >= 0x01a00000)
1673 ev_reg
= GET_SRC_REG (op
);
1674 /* If this is the first vector reg to be saved, or if
1675 it has a lower number than others previously seen,
1676 reupdate the frame info. */
1677 /* We know the contents of r0 from the previous
1679 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1681 fdata
->saved_ev
= ev_reg
;
1682 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1686 vr_saved_offset
= -1;
1691 /* End BookE related instructions. */
1695 /* Not a recognized prologue instruction.
1696 Handle optimizer code motions into the prologue by continuing
1697 the search if we have no valid frame yet or if the return
1698 address is not yet saved in the frame. */
1699 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0)
1702 if (op
== 0x4e800020 /* blr */
1703 || op
== 0x4e800420) /* bctr */
1704 /* Do not scan past epilogue in frameless functions or
1707 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
1708 /* Never skip branches. */
1711 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
1712 /* Do not scan too many insns, scanning insns is expensive with
1716 /* Continue scanning. */
1717 prev_insn_was_prologue_insn
= 0;
1723 /* I have problems with skipping over __main() that I need to address
1724 * sometime. Previously, I used to use misc_function_vector which
1725 * didn't work as well as I wanted to be. -MGO */
1727 /* If the first thing after skipping a prolog is a branch to a function,
1728 this might be a call to an initializer in main(), introduced by gcc2.
1729 We'd like to skip over it as well. Fortunately, xlc does some extra
1730 work before calling a function right after a prologue, thus we can
1731 single out such gcc2 behaviour. */
1734 if ((op
& 0xfc000001) == 0x48000001)
1735 { /* bl foo, an initializer function? */
1736 op
= read_memory_integer (pc
+ 4, 4);
1738 if (op
== 0x4def7b82)
1739 { /* cror 0xf, 0xf, 0xf (nop) */
1741 /* Check and see if we are in main. If so, skip over this
1742 initializer function as well. */
1744 tmp
= find_pc_misc_function (pc
);
1746 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
1752 fdata
->offset
= -fdata
->offset
;
1753 return last_prologue_pc
;
1757 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1759 struct rs6000_framedata frame
;
1760 CORE_ADDR limit_pc
, func_addr
;
1762 /* See if we can determine the end of the prologue via the symbol table.
1763 If so, then return either PC, or the PC after the prologue, whichever
1765 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
1767 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
1768 if (post_prologue_pc
!= 0)
1769 return max (pc
, post_prologue_pc
);
1772 /* Can't determine prologue from the symbol table, need to examine
1775 /* Find an upper limit on the function prologue using the debug
1776 information. If the debug information could not be used to provide
1777 that bound, then use an arbitrary large number as the upper bound. */
1778 limit_pc
= skip_prologue_using_sal (pc
);
1780 limit_pc
= pc
+ 100; /* Magic. */
1782 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
1786 /* When compiling for EABI, some versions of GCC emit a call to __eabi
1787 in the prologue of main().
1789 The function below examines the code pointed at by PC and checks to
1790 see if it corresponds to a call to __eabi. If so, it returns the
1791 address of the instruction following that call. Otherwise, it simply
1795 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1800 if (target_read_memory (pc
, buf
, 4))
1802 op
= extract_unsigned_integer (buf
, 4);
1804 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
1806 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
1807 CORE_ADDR call_dest
= pc
+ 4 + displ
;
1808 struct minimal_symbol
*s
= lookup_minimal_symbol_by_pc (call_dest
);
1810 /* We check for ___eabi (three leading underscores) in addition
1811 to __eabi in case the GCC option "-fleading-underscore" was
1812 used to compile the program. */
1814 && SYMBOL_LINKAGE_NAME (s
) != NULL
1815 && (strcmp (SYMBOL_LINKAGE_NAME (s
), "__eabi") == 0
1816 || strcmp (SYMBOL_LINKAGE_NAME (s
), "___eabi") == 0))
1822 /* All the ABI's require 16 byte alignment. */
1824 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1826 return (addr
& -16);
1829 /* Return whether handle_inferior_event() should proceed through code
1830 starting at PC in function NAME when stepping.
1832 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1833 handle memory references that are too distant to fit in instructions
1834 generated by the compiler. For example, if 'foo' in the following
1839 is greater than 32767, the linker might replace the lwz with a branch to
1840 somewhere in @FIX1 that does the load in 2 instructions and then branches
1841 back to where execution should continue.
1843 GDB should silently step over @FIX code, just like AIX dbx does.
1844 Unfortunately, the linker uses the "b" instruction for the
1845 branches, meaning that the link register doesn't get set.
1846 Therefore, GDB's usual step_over_function () mechanism won't work.
1848 Instead, use the gdbarch_skip_trampoline_code and
1849 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
1853 rs6000_in_solib_return_trampoline (CORE_ADDR pc
, char *name
)
1855 return name
&& !strncmp (name
, "@FIX", 4);
1858 /* Skip code that the user doesn't want to see when stepping:
1860 1. Indirect function calls use a piece of trampoline code to do context
1861 switching, i.e. to set the new TOC table. Skip such code if we are on
1862 its first instruction (as when we have single-stepped to here).
1864 2. Skip shared library trampoline code (which is different from
1865 indirect function call trampolines).
1867 3. Skip bigtoc fixup code.
1869 Result is desired PC to step until, or NULL if we are not in
1870 code that should be skipped. */
1873 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
1875 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (frame
));
1876 unsigned int ii
, op
;
1878 CORE_ADDR solib_target_pc
;
1879 struct minimal_symbol
*msymbol
;
1881 static unsigned trampoline_code
[] =
1883 0x800b0000, /* l r0,0x0(r11) */
1884 0x90410014, /* st r2,0x14(r1) */
1885 0x7c0903a6, /* mtctr r0 */
1886 0x804b0004, /* l r2,0x4(r11) */
1887 0x816b0008, /* l r11,0x8(r11) */
1888 0x4e800420, /* bctr */
1889 0x4e800020, /* br */
1893 /* Check for bigtoc fixup code. */
1894 msymbol
= lookup_minimal_symbol_by_pc (pc
);
1896 && rs6000_in_solib_return_trampoline (pc
, SYMBOL_LINKAGE_NAME (msymbol
)))
1898 /* Double-check that the third instruction from PC is relative "b". */
1899 op
= read_memory_integer (pc
+ 8, 4);
1900 if ((op
& 0xfc000003) == 0x48000000)
1902 /* Extract bits 6-29 as a signed 24-bit relative word address and
1903 add it to the containing PC. */
1904 rel
= ((int)(op
<< 6) >> 6);
1905 return pc
+ 8 + rel
;
1909 /* If pc is in a shared library trampoline, return its target. */
1910 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
1911 if (solib_target_pc
)
1912 return solib_target_pc
;
1914 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
1916 op
= read_memory_integer (pc
+ (ii
* 4), 4);
1917 if (op
!= trampoline_code
[ii
])
1920 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination addr */
1921 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
); /* (r11) value */
1925 /* ISA-specific vector types. */
1927 static struct type
*
1928 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
1930 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1932 if (!tdep
->ppc_builtin_type_vec64
)
1934 /* The type we're building is this: */
1936 union __gdb_builtin_type_vec64
1940 int32_t v2_int32
[2];
1941 int16_t v4_int16
[4];
1948 t
= init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
1949 append_composite_type_field (t
, "uint64", builtin_type_int64
);
1950 append_composite_type_field (t
, "v2_float",
1951 init_vector_type (builtin_type_float
, 2));
1952 append_composite_type_field (t
, "v2_int32",
1953 init_vector_type (builtin_type_int32
, 2));
1954 append_composite_type_field (t
, "v4_int16",
1955 init_vector_type (builtin_type_int16
, 4));
1956 append_composite_type_field (t
, "v8_int8",
1957 init_vector_type (builtin_type_int8
, 8));
1959 TYPE_FLAGS (t
) |= TYPE_FLAG_VECTOR
;
1960 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
1961 tdep
->ppc_builtin_type_vec64
= t
;
1964 return tdep
->ppc_builtin_type_vec64
;
1967 /* Return the name of register number REGNO, or the empty string if it
1968 is an anonymous register. */
1971 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
1973 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1975 /* The upper half "registers" have names in the XML description,
1976 but we present only the low GPRs and the full 64-bit registers
1978 if (tdep
->ppc_ev0_upper_regnum
>= 0
1979 && tdep
->ppc_ev0_upper_regnum
<= regno
1980 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
1983 /* Check if the SPE pseudo registers are available. */
1984 if (IS_SPE_PSEUDOREG (tdep
, regno
))
1986 static const char *const spe_regnames
[] = {
1987 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
1988 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
1989 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
1990 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
1992 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
1995 /* Check if the decimal128 pseudo-registers are available. */
1996 if (IS_DFP_PSEUDOREG (tdep
, regno
))
1998 static const char *const dfp128_regnames
[] = {
1999 "dl0", "dl1", "dl2", "dl3",
2000 "dl4", "dl5", "dl6", "dl7",
2001 "dl8", "dl9", "dl10", "dl11",
2002 "dl12", "dl13", "dl14", "dl15"
2004 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2007 return tdesc_register_name (gdbarch
, regno
);
2010 /* Return the GDB type object for the "standard" data type of data in
2013 static struct type
*
2014 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2016 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2018 /* These are the only pseudo-registers we support. */
2019 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2020 || IS_DFP_PSEUDOREG (tdep
, regnum
));
2022 /* These are the e500 pseudo-registers. */
2023 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2024 return rs6000_builtin_type_vec64 (gdbarch
);
2026 /* Could only be the ppc decimal128 pseudo-registers. */
2027 return builtin_type (gdbarch
)->builtin_declong
;
2030 /* Is REGNUM a member of REGGROUP? */
2032 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2033 struct reggroup
*group
)
2035 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2037 /* These are the only pseudo-registers we support. */
2038 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2039 || IS_DFP_PSEUDOREG (tdep
, regnum
));
2041 /* These are the e500 pseudo-registers. */
2042 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2043 return group
== all_reggroup
|| group
== vector_reggroup
;
2045 /* Could only be the ppc decimal128 pseudo-registers. */
2046 return group
== all_reggroup
|| group
== float_reggroup
;
2049 /* The register format for RS/6000 floating point registers is always
2050 double, we need a conversion if the memory format is float. */
2053 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2056 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2058 return (tdep
->ppc_fp0_regnum
>= 0
2059 && regnum
>= tdep
->ppc_fp0_regnum
2060 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2061 && TYPE_CODE (type
) == TYPE_CODE_FLT
2062 && TYPE_LENGTH (type
) != TYPE_LENGTH (builtin_type_double
));
2066 rs6000_register_to_value (struct frame_info
*frame
,
2071 gdb_byte from
[MAX_REGISTER_SIZE
];
2073 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2075 get_frame_register (frame
, regnum
, from
);
2076 convert_typed_floating (from
, builtin_type_double
, to
, type
);
2080 rs6000_value_to_register (struct frame_info
*frame
,
2083 const gdb_byte
*from
)
2085 gdb_byte to
[MAX_REGISTER_SIZE
];
2087 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2089 convert_typed_floating (from
, type
, to
, builtin_type_double
);
2090 put_frame_register (frame
, regnum
, to
);
2093 /* Move SPE vector register values between a 64-bit buffer and the two
2094 32-bit raw register halves in a regcache. This function handles
2095 both splitting a 64-bit value into two 32-bit halves, and joining
2096 two halves into a whole 64-bit value, depending on the function
2097 passed as the MOVE argument.
2099 EV_REG must be the number of an SPE evN vector register --- a
2100 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2103 Call MOVE once for each 32-bit half of that register, passing
2104 REGCACHE, the number of the raw register corresponding to that
2105 half, and the address of the appropriate half of BUFFER.
2107 For example, passing 'regcache_raw_read' as the MOVE function will
2108 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2109 'regcache_raw_supply' will supply the contents of BUFFER to the
2110 appropriate pair of raw registers in REGCACHE.
2112 You may need to cast away some 'const' qualifiers when passing
2113 MOVE, since this function can't tell at compile-time which of
2114 REGCACHE or BUFFER is acting as the source of the data. If C had
2115 co-variant type qualifiers, ... */
2117 e500_move_ev_register (void (*move
) (struct regcache
*regcache
,
2118 int regnum
, gdb_byte
*buf
),
2119 struct regcache
*regcache
, int ev_reg
,
2122 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2123 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2125 gdb_byte
*byte_buffer
= buffer
;
2127 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2129 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2131 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2133 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
);
2134 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
+ 4);
2138 move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2139 move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
, byte_buffer
+ 4);
2144 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2145 int reg_nr
, gdb_byte
*buffer
)
2147 e500_move_ev_register (regcache_raw_read
, regcache
, reg_nr
, buffer
);
2151 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2152 int reg_nr
, const gdb_byte
*buffer
)
2154 e500_move_ev_register ((void (*) (struct regcache
*, int, gdb_byte
*))
2156 regcache
, reg_nr
, (gdb_byte
*) buffer
);
2159 /* Read method for PPC pseudo-registers. Currently this is handling the
2160 16 decimal128 registers that map into 16 pairs of FP registers. */
2162 ppc_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2163 int reg_nr
, gdb_byte
*buffer
)
2165 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2166 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2168 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2170 /* Read two FP registers to form a whole dl register. */
2171 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2172 2 * reg_index
, buffer
);
2173 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2174 2 * reg_index
+ 1, buffer
+ 8);
2178 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2179 2 * reg_index
+ 1, buffer
+ 8);
2180 regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2181 2 * reg_index
, buffer
);
2185 /* Write method for PPC pseudo-registers. Currently this is handling the
2186 16 decimal128 registers that map into 16 pairs of FP registers. */
2188 ppc_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2189 int reg_nr
, const gdb_byte
*buffer
)
2191 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2192 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2194 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2196 /* Write each half of the dl register into a separate
2198 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2199 2 * reg_index
, buffer
);
2200 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2201 2 * reg_index
+ 1, buffer
+ 8);
2205 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2206 2 * reg_index
+ 1, buffer
+ 8);
2207 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2208 2 * reg_index
, buffer
);
2213 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2214 int reg_nr
, gdb_byte
*buffer
)
2216 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2217 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2219 gdb_assert (regcache_arch
== gdbarch
);
2221 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2222 e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2223 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2224 ppc_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2226 internal_error (__FILE__
, __LINE__
,
2227 _("rs6000_pseudo_register_read: "
2228 "called on unexpected register '%s' (%d)"),
2229 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2233 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2234 struct regcache
*regcache
,
2235 int reg_nr
, const gdb_byte
*buffer
)
2237 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2238 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2240 gdb_assert (regcache_arch
== gdbarch
);
2242 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2243 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2244 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2245 ppc_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2247 internal_error (__FILE__
, __LINE__
,
2248 _("rs6000_pseudo_register_write: "
2249 "called on unexpected register '%s' (%d)"),
2250 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2253 /* Convert a DBX STABS register number to a GDB register number. */
2255 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2257 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2259 if (0 <= num
&& num
<= 31)
2260 return tdep
->ppc_gp0_regnum
+ num
;
2261 else if (32 <= num
&& num
<= 63)
2262 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2263 specifies registers the architecture doesn't have? Our
2264 callers don't check the value we return. */
2265 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2266 else if (77 <= num
&& num
<= 108)
2267 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2268 else if (1200 <= num
&& num
< 1200 + 32)
2269 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2274 return tdep
->ppc_mq_regnum
;
2276 return tdep
->ppc_lr_regnum
;
2278 return tdep
->ppc_ctr_regnum
;
2280 return tdep
->ppc_xer_regnum
;
2282 return tdep
->ppc_vrsave_regnum
;
2284 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2286 return tdep
->ppc_acc_regnum
;
2288 return tdep
->ppc_spefscr_regnum
;
2295 /* Convert a Dwarf 2 register number to a GDB register number. */
2297 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2299 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2301 if (0 <= num
&& num
<= 31)
2302 return tdep
->ppc_gp0_regnum
+ num
;
2303 else if (32 <= num
&& num
<= 63)
2304 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2305 specifies registers the architecture doesn't have? Our
2306 callers don't check the value we return. */
2307 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2308 else if (1124 <= num
&& num
< 1124 + 32)
2309 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2310 else if (1200 <= num
&& num
< 1200 + 32)
2311 return tdep
->ppc_ev0_regnum
+ (num
- 1200);
2316 return tdep
->ppc_cr_regnum
;
2318 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2320 return tdep
->ppc_acc_regnum
;
2322 return tdep
->ppc_mq_regnum
;
2324 return tdep
->ppc_xer_regnum
;
2326 return tdep
->ppc_lr_regnum
;
2328 return tdep
->ppc_ctr_regnum
;
2330 return tdep
->ppc_vrsave_regnum
;
2332 return tdep
->ppc_spefscr_regnum
;
2338 /* Translate a .eh_frame register to DWARF register, or adjust a
2339 .debug_frame register. */
2342 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2344 /* GCC releases before 3.4 use GCC internal register numbering in
2345 .debug_frame (and .debug_info, et cetera). The numbering is
2346 different from the standard SysV numbering for everything except
2347 for GPRs and FPRs. We can not detect this problem in most cases
2348 - to get accurate debug info for variables living in lr, ctr, v0,
2349 et cetera, use a newer version of GCC. But we must detect
2350 one important case - lr is in column 65 in .debug_frame output,
2353 GCC 3.4, and the "hammer" branch, have a related problem. They
2354 record lr register saves in .debug_frame as 108, but still record
2355 the return column as 65. We fix that up too.
2357 We can do this because 65 is assigned to fpsr, and GCC never
2358 generates debug info referring to it. To add support for
2359 handwritten debug info that restores fpsr, we would need to add a
2360 producer version check to this. */
2369 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2370 internal register numbering; translate that to the standard DWARF2
2371 register numbering. */
2372 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2374 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2375 return num
- 68 + 86;
2376 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2377 return num
- 77 + 1124;
2389 case 109: /* vrsave */
2391 case 110: /* vscr */
2393 case 111: /* spe_acc */
2395 case 112: /* spefscr */
2403 /* Handling the various POWER/PowerPC variants. */
2405 /* Information about a particular processor variant. */
2409 /* Name of this variant. */
2412 /* English description of the variant. */
2415 /* bfd_arch_info.arch corresponding to variant. */
2416 enum bfd_architecture arch
;
2418 /* bfd_arch_info.mach corresponding to variant. */
2421 /* Target description for this variant. */
2422 struct target_desc
**tdesc
;
2425 static struct variant variants
[] =
2427 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
2428 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
2429 {"power", "POWER user-level", bfd_arch_rs6000
,
2430 bfd_mach_rs6k
, &tdesc_rs6000
},
2431 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
2432 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
2433 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
2434 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
2435 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
2436 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
2437 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
2438 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
2439 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
2440 604, &tdesc_powerpc_604
},
2441 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
2442 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
2443 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
2444 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
2445 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
2446 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
2447 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
2448 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
2449 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
2450 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
2451 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
2452 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
2455 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
2456 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
2457 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
2458 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
2459 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
2460 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
2461 {"a35", "PowerPC A35", bfd_arch_powerpc
,
2462 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
2463 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
2464 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
2465 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
2466 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
2468 /* FIXME: I haven't checked the register sets of the following. */
2469 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
2470 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
2471 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
2472 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
2473 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
2474 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
2479 /* Return the variant corresponding to architecture ARCH and machine number
2480 MACH. If no such variant exists, return null. */
2482 static const struct variant
*
2483 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
2485 const struct variant
*v
;
2487 for (v
= variants
; v
->name
; v
++)
2488 if (arch
== v
->arch
&& mach
== v
->mach
)
2495 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
2497 if (!info
->disassembler_options
)
2498 info
->disassembler_options
= "any";
2500 if (info
->endian
== BFD_ENDIAN_BIG
)
2501 return print_insn_big_powerpc (memaddr
, info
);
2503 return print_insn_little_powerpc (memaddr
, info
);
2507 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
2509 return frame_unwind_register_unsigned (next_frame
,
2510 gdbarch_pc_regnum (gdbarch
));
2513 static struct frame_id
2514 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2516 return frame_id_build (get_frame_register_unsigned
2517 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
2518 get_frame_pc (this_frame
));
2521 struct rs6000_frame_cache
2524 CORE_ADDR initial_sp
;
2525 struct trad_frame_saved_reg
*saved_regs
;
2528 static struct rs6000_frame_cache
*
2529 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2531 struct rs6000_frame_cache
*cache
;
2532 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2533 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2534 struct rs6000_framedata fdata
;
2535 int wordsize
= tdep
->wordsize
;
2538 if ((*this_cache
) != NULL
)
2539 return (*this_cache
);
2540 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
2541 (*this_cache
) = cache
;
2542 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2544 func
= get_frame_func (this_frame
);
2545 pc
= get_frame_pc (this_frame
);
2546 skip_prologue (gdbarch
, func
, pc
, &fdata
);
2548 /* Figure out the parent's stack pointer. */
2550 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2551 address of the current frame. Things might be easier if the
2552 ->frame pointed to the outer-most address of the frame. In
2553 the mean time, the address of the prev frame is used as the
2554 base address of this frame. */
2555 cache
->base
= get_frame_register_unsigned
2556 (this_frame
, gdbarch_sp_regnum (gdbarch
));
2558 /* If the function appears to be frameless, check a couple of likely
2559 indicators that we have simply failed to find the frame setup.
2560 Two common cases of this are missing symbols (i.e.
2561 get_frame_func returns the wrong address or 0), and assembly
2562 stubs which have a fast exit path but set up a frame on the slow
2565 If the LR appears to return to this function, then presume that
2566 we have an ABI compliant frame that we failed to find. */
2567 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
2572 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
2573 if (func
== 0 && saved_lr
== pc
)
2577 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
2578 if (func
== saved_func
)
2584 fdata
.frameless
= 0;
2585 fdata
.lr_offset
= tdep
->lr_frame_offset
;
2589 if (!fdata
.frameless
)
2590 /* Frameless really means stackless. */
2591 cache
->base
= read_memory_unsigned_integer (cache
->base
, wordsize
);
2593 trad_frame_set_value (cache
->saved_regs
,
2594 gdbarch_sp_regnum (gdbarch
), cache
->base
);
2596 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2597 All fpr's from saved_fpr to fp31 are saved. */
2599 if (fdata
.saved_fpr
>= 0)
2602 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
2604 /* If skip_prologue says floating-point registers were saved,
2605 but the current architecture has no floating-point registers,
2606 then that's strange. But we have no indices to even record
2607 the addresses under, so we just ignore it. */
2608 if (ppc_floating_point_unit_p (gdbarch
))
2609 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
2611 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
2616 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2617 All gpr's from saved_gpr to gpr31 are saved. */
2619 if (fdata
.saved_gpr
>= 0)
2622 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
2623 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
2625 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
2626 gpr_addr
+= wordsize
;
2630 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2631 All vr's from saved_vr to vr31 are saved. */
2632 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
2634 if (fdata
.saved_vr
>= 0)
2637 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
2638 for (i
= fdata
.saved_vr
; i
< 32; i
++)
2640 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
2641 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
2646 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2647 All vr's from saved_ev to ev31 are saved. ????? */
2648 if (tdep
->ppc_ev0_regnum
!= -1)
2650 if (fdata
.saved_ev
>= 0)
2653 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
2654 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
2656 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
2657 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ 4;
2658 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
2663 /* If != 0, fdata.cr_offset is the offset from the frame that
2665 if (fdata
.cr_offset
!= 0)
2666 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
= cache
->base
+ fdata
.cr_offset
;
2668 /* If != 0, fdata.lr_offset is the offset from the frame that
2670 if (fdata
.lr_offset
!= 0)
2671 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
= cache
->base
+ fdata
.lr_offset
;
2672 /* The PC is found in the link register. */
2673 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
2674 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
2676 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2677 holds the VRSAVE. */
2678 if (fdata
.vrsave_offset
!= 0)
2679 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
= cache
->base
+ fdata
.vrsave_offset
;
2681 if (fdata
.alloca_reg
< 0)
2682 /* If no alloca register used, then fi->frame is the value of the
2683 %sp for this frame, and it is good enough. */
2685 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
2688 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
2694 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2695 struct frame_id
*this_id
)
2697 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
2699 /* This marks the outermost frame. */
2700 if (info
->base
== 0)
2703 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2706 static struct value
*
2707 rs6000_frame_prev_register (struct frame_info
*this_frame
,
2708 void **this_cache
, int regnum
)
2710 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
2712 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2715 static const struct frame_unwind rs6000_frame_unwind
=
2718 rs6000_frame_this_id
,
2719 rs6000_frame_prev_register
,
2721 default_frame_sniffer
2726 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2728 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
2730 return info
->initial_sp
;
2733 static const struct frame_base rs6000_frame_base
= {
2734 &rs6000_frame_unwind
,
2735 rs6000_frame_base_address
,
2736 rs6000_frame_base_address
,
2737 rs6000_frame_base_address
2740 static const struct frame_base
*
2741 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
2743 return &rs6000_frame_base
;
2746 /* DWARF-2 frame support. Used to handle the detection of
2747 clobbered registers during function calls. */
2750 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
2751 struct dwarf2_frame_state_reg
*reg
,
2752 struct frame_info
*this_frame
)
2754 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2756 /* PPC32 and PPC64 ABI's are the same regarding volatile and
2757 non-volatile registers. We will use the same code for both. */
2759 /* Call-saved GP registers. */
2760 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
2761 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
2762 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
2763 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2765 /* Call-clobbered GP registers. */
2766 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
2767 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
2768 || (regnum
== tdep
->ppc_gp0_regnum
))
2769 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2771 /* Deal with FP registers, if supported. */
2772 if (tdep
->ppc_fp0_regnum
>= 0)
2774 /* Call-saved FP registers. */
2775 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
2776 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
2777 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2779 /* Call-clobbered FP registers. */
2780 if ((regnum
>= tdep
->ppc_fp0_regnum
2781 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
2782 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2785 /* Deal with ALTIVEC registers, if supported. */
2786 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
2788 /* Call-saved Altivec registers. */
2789 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
2790 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
2791 || regnum
== tdep
->ppc_vrsave_regnum
)
2792 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
2794 /* Call-clobbered Altivec registers. */
2795 if ((regnum
>= tdep
->ppc_vr0_regnum
2796 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
2797 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
2800 /* Handle PC register and Stack Pointer correctly. */
2801 if (regnum
== gdbarch_pc_regnum (gdbarch
))
2802 reg
->how
= DWARF2_FRAME_REG_RA
;
2803 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
2804 reg
->how
= DWARF2_FRAME_REG_CFA
;
2808 /* Initialize the current architecture based on INFO. If possible, re-use an
2809 architecture from ARCHES, which is a list of architectures already created
2810 during this debugging session.
2812 Called e.g. at program startup, when reading a core file, and when reading
2815 static struct gdbarch
*
2816 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2818 struct gdbarch
*gdbarch
;
2819 struct gdbarch_tdep
*tdep
;
2820 int wordsize
, from_xcoff_exec
, from_elf_exec
;
2821 enum bfd_architecture arch
;
2825 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
2827 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
2828 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0;
2829 int tdesc_wordsize
= -1;
2830 const struct target_desc
*tdesc
= info
.target_desc
;
2831 struct tdesc_arch_data
*tdesc_data
= NULL
;
2832 int num_pseudoregs
= 0;
2834 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2835 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
2837 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
2838 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
2840 /* Check word size. If INFO is from a binary file, infer it from
2841 that, else choose a likely default. */
2842 if (from_xcoff_exec
)
2844 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
2849 else if (from_elf_exec
)
2851 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
2856 else if (tdesc_has_registers (tdesc
))
2860 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
2861 wordsize
= info
.bfd_arch_info
->bits_per_word
/
2862 info
.bfd_arch_info
->bits_per_byte
;
2867 /* Get the architecture and machine from the BFD. */
2868 arch
= info
.bfd_arch_info
->arch
;
2869 mach
= info
.bfd_arch_info
->mach
;
2871 /* For e500 executables, the apuinfo section is of help here. Such
2872 section contains the identifier and revision number of each
2873 Application-specific Processing Unit that is present on the
2874 chip. The content of the section is determined by the assembler
2875 which looks at each instruction and determines which unit (and
2876 which version of it) can execute it. In our case we just look for
2877 the existance of the section. */
2881 sect
= bfd_get_section_by_name (info
.abfd
, ".PPC.EMB.apuinfo");
2884 arch
= info
.bfd_arch_info
->arch
;
2885 mach
= bfd_mach_ppc_e500
;
2886 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
2887 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
2891 /* Find a default target description which describes our register
2892 layout, if we do not already have one. */
2893 if (! tdesc_has_registers (tdesc
))
2895 const struct variant
*v
;
2897 /* Choose variant. */
2898 v
= find_variant_by_arch (arch
, mach
);
2905 gdb_assert (tdesc_has_registers (tdesc
));
2907 /* Check any target description for validity. */
2908 if (tdesc_has_registers (tdesc
))
2910 static const char *const gprs
[] = {
2911 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2912 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
2913 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
2914 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
2916 static const char *const segment_regs
[] = {
2917 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
2918 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
2920 const struct tdesc_feature
*feature
;
2922 static const char *const msr_names
[] = { "msr", "ps" };
2923 static const char *const cr_names
[] = { "cr", "cnd" };
2924 static const char *const ctr_names
[] = { "ctr", "cnt" };
2926 feature
= tdesc_find_feature (tdesc
,
2927 "org.gnu.gdb.power.core");
2928 if (feature
== NULL
)
2931 tdesc_data
= tdesc_data_alloc ();
2934 for (i
= 0; i
< ppc_num_gprs
; i
++)
2935 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
2936 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
2938 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
2940 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
2943 /* Allow alternate names for these registers, to accomodate GDB's
2945 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2946 PPC_MSR_REGNUM
, msr_names
);
2947 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2948 PPC_CR_REGNUM
, cr_names
);
2949 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
2950 PPC_CTR_REGNUM
, ctr_names
);
2954 tdesc_data_cleanup (tdesc_data
);
2958 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
2961 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
2963 wordsize
= tdesc_wordsize
;
2965 feature
= tdesc_find_feature (tdesc
,
2966 "org.gnu.gdb.power.fpu");
2967 if (feature
!= NULL
)
2969 static const char *const fprs
[] = {
2970 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2971 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
2972 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2973 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
2976 for (i
= 0; i
< ppc_num_fprs
; i
++)
2977 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2978 PPC_F0_REGNUM
+ i
, fprs
[i
]);
2979 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
2980 PPC_FPSCR_REGNUM
, "fpscr");
2984 tdesc_data_cleanup (tdesc_data
);
2992 /* The DFP pseudo-registers will be available when there are floating
2994 have_dfp
= have_fpu
;
2996 feature
= tdesc_find_feature (tdesc
,
2997 "org.gnu.gdb.power.altivec");
2998 if (feature
!= NULL
)
3000 static const char *const vector_regs
[] = {
3001 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3002 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3003 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3004 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3008 for (i
= 0; i
< ppc_num_gprs
; i
++)
3009 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3012 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3013 PPC_VSCR_REGNUM
, "vscr");
3014 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3015 PPC_VRSAVE_REGNUM
, "vrsave");
3017 if (have_spe
|| !valid_p
)
3019 tdesc_data_cleanup (tdesc_data
);
3027 /* On machines supporting the SPE APU, the general-purpose registers
3028 are 64 bits long. There are SIMD vector instructions to treat them
3029 as pairs of floats, but the rest of the instruction set treats them
3030 as 32-bit registers, and only operates on their lower halves.
3032 In the GDB regcache, we treat their high and low halves as separate
3033 registers. The low halves we present as the general-purpose
3034 registers, and then we have pseudo-registers that stitch together
3035 the upper and lower halves and present them as pseudo-registers.
3037 Thus, the target description is expected to supply the upper
3038 halves separately. */
3040 feature
= tdesc_find_feature (tdesc
,
3041 "org.gnu.gdb.power.spe");
3042 if (feature
!= NULL
)
3044 static const char *const upper_spe
[] = {
3045 "ev0h", "ev1h", "ev2h", "ev3h",
3046 "ev4h", "ev5h", "ev6h", "ev7h",
3047 "ev8h", "ev9h", "ev10h", "ev11h",
3048 "ev12h", "ev13h", "ev14h", "ev15h",
3049 "ev16h", "ev17h", "ev18h", "ev19h",
3050 "ev20h", "ev21h", "ev22h", "ev23h",
3051 "ev24h", "ev25h", "ev26h", "ev27h",
3052 "ev28h", "ev29h", "ev30h", "ev31h"
3056 for (i
= 0; i
< ppc_num_gprs
; i
++)
3057 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3058 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
3060 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3061 PPC_SPE_ACC_REGNUM
, "acc");
3062 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3063 PPC_SPE_FSCR_REGNUM
, "spefscr");
3065 if (have_mq
|| have_fpu
|| !valid_p
)
3067 tdesc_data_cleanup (tdesc_data
);
3076 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3077 complain for a 32-bit binary on a 64-bit target; we do not yet
3078 support that. For instance, the 32-bit ABI routines expect
3081 As long as there isn't an explicit target description, we'll
3082 choose one based on the BFD architecture and get a word size
3083 matching the binary (probably powerpc:common or
3084 powerpc:common64). So there is only trouble if a 64-bit target
3085 supplies a 64-bit description while debugging a 32-bit
3087 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
3089 tdesc_data_cleanup (tdesc_data
);
3094 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
3096 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3097 Tag_GNU_Power_ABI_FP
))
3100 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
3103 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
3110 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
3112 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3113 Tag_GNU_Power_ABI_Vector
))
3116 vector_abi
= POWERPC_VEC_GENERIC
;
3119 vector_abi
= POWERPC_VEC_ALTIVEC
;
3122 vector_abi
= POWERPC_VEC_SPE
;
3130 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
3132 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
3135 soft_float
= !have_fpu
;
3137 /* If we have a hard float binary or setting but no floating point
3138 registers, downgrade to soft float anyway. We're still somewhat
3139 useful in this scenario. */
3140 if (!soft_float
&& !have_fpu
)
3143 /* Similarly for vector registers. */
3144 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
3145 vector_abi
= POWERPC_VEC_GENERIC
;
3147 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
3148 vector_abi
= POWERPC_VEC_GENERIC
;
3150 if (vector_abi
== POWERPC_VEC_AUTO
)
3153 vector_abi
= POWERPC_VEC_ALTIVEC
;
3155 vector_abi
= POWERPC_VEC_SPE
;
3157 vector_abi
= POWERPC_VEC_GENERIC
;
3160 /* Do not limit the vector ABI based on available hardware, since we
3161 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3163 /* Find a candidate among extant architectures. */
3164 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
3166 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
3168 /* Word size in the various PowerPC bfd_arch_info structs isn't
3169 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3170 separate word size check. */
3171 tdep
= gdbarch_tdep (arches
->gdbarch
);
3172 if (tdep
&& tdep
->soft_float
!= soft_float
)
3174 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
3176 if (tdep
&& tdep
->wordsize
== wordsize
)
3178 if (tdesc_data
!= NULL
)
3179 tdesc_data_cleanup (tdesc_data
);
3180 return arches
->gdbarch
;
3184 /* None found, create a new architecture from INFO, whose bfd_arch_info
3185 validity depends on the source:
3186 - executable useless
3187 - rs6000_host_arch() good
3189 - "set arch" trust blindly
3190 - GDB startup useless but harmless */
3192 tdep
= XCALLOC (1, struct gdbarch_tdep
);
3193 tdep
->wordsize
= wordsize
;
3194 tdep
->soft_float
= soft_float
;
3195 tdep
->vector_abi
= vector_abi
;
3197 gdbarch
= gdbarch_alloc (&info
, tdep
);
3199 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
3200 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
3201 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
3202 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
3203 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
3204 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
3205 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
3206 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
3208 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
3209 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
3210 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
3211 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
3212 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
3213 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
3214 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
3216 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
3217 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3218 set_gdbarch_deprecated_fp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
3219 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
3220 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
3222 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3223 GDB traditionally called it "ps", though, so let GDB add an
3225 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
3228 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
3230 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
3232 /* Set lr_frame_offset. */
3234 tdep
->lr_frame_offset
= 16;
3236 tdep
->lr_frame_offset
= 4;
3238 if (have_spe
|| have_dfp
)
3240 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
3241 set_gdbarch_pseudo_register_write (gdbarch
, rs6000_pseudo_register_write
);
3244 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3246 /* Select instruction printer. */
3247 if (arch
== bfd_arch_rs6000
)
3248 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
3250 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
3252 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
3255 num_pseudoregs
+= 32;
3257 num_pseudoregs
+= 16;
3259 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
3261 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3262 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
3263 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3264 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
3265 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3266 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
3267 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
3268 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
3269 set_gdbarch_char_signed (gdbarch
, 0);
3271 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
3274 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
3276 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
3277 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
3278 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
3280 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
3281 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
3284 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
3285 else if (wordsize
== 8)
3286 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
3288 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
3289 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
3290 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
3292 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3293 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
3295 /* The value of symbols of type N_SO and N_FUN maybe null when
3297 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
3299 /* Handles single stepping of atomic sequences. */
3300 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
3302 /* Not sure on this. FIXMEmgo */
3303 set_gdbarch_frame_args_skip (gdbarch
, 8);
3305 /* Helpers for function argument information. */
3306 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
3309 set_gdbarch_in_solib_return_trampoline
3310 (gdbarch
, rs6000_in_solib_return_trampoline
);
3311 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
3313 /* Hook in the DWARF CFI frame unwinder. */
3314 dwarf2_append_unwinders (gdbarch
);
3315 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
3317 /* Frame handling. */
3318 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
3320 /* Hook in ABI-specific overrides, if they have been registered. */
3321 info
.target_desc
= tdesc
;
3322 info
.tdep_info
= (void *) tdesc_data
;
3323 gdbarch_init_osabi (info
, gdbarch
);
3327 case GDB_OSABI_LINUX
:
3328 case GDB_OSABI_NETBSD_AOUT
:
3329 case GDB_OSABI_NETBSD_ELF
:
3330 case GDB_OSABI_UNKNOWN
:
3331 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3332 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
3333 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
3334 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3337 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
3339 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
3340 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
3341 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
3342 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
3345 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
3346 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3347 rs6000_pseudo_register_reggroup_p
);
3348 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
3350 /* Override the normal target description method to make the SPE upper
3351 halves anonymous. */
3352 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
3354 /* Recording the numbering of pseudo registers. */
3355 tdep
->ppc_ev0_regnum
= have_spe
? gdbarch_num_regs (gdbarch
) : -1;
3357 /* Set the register number for _Decimal128 pseudo-registers. */
3358 tdep
->ppc_dl0_regnum
= have_dfp
? gdbarch_num_regs (gdbarch
) : -1;
3360 if (have_dfp
&& have_spe
)
3361 /* Put the _Decimal128 pseudo-registers after the SPE registers. */
3362 tdep
->ppc_dl0_regnum
+= 32;
3364 /* Setup displaced stepping. */
3365 set_gdbarch_displaced_step_copy_insn (gdbarch
,
3366 simple_displaced_step_copy_insn
);
3367 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
3368 set_gdbarch_displaced_step_free_closure (gdbarch
,
3369 simple_displaced_step_free_closure
);
3370 set_gdbarch_displaced_step_location (gdbarch
,
3371 displaced_step_at_entry_point
);
3373 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
3379 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3381 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3386 /* FIXME: Dump gdbarch_tdep. */
3389 /* PowerPC-specific commands. */
3392 set_powerpc_command (char *args
, int from_tty
)
3394 printf_unfiltered (_("\
3395 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
3396 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
3400 show_powerpc_command (char *args
, int from_tty
)
3402 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
3406 powerpc_set_soft_float (char *args
, int from_tty
,
3407 struct cmd_list_element
*c
)
3409 struct gdbarch_info info
;
3411 /* Update the architecture. */
3412 gdbarch_info_init (&info
);
3413 if (!gdbarch_update_p (info
))
3414 internal_error (__FILE__
, __LINE__
, "could not update architecture");
3418 powerpc_set_vector_abi (char *args
, int from_tty
,
3419 struct cmd_list_element
*c
)
3421 struct gdbarch_info info
;
3422 enum powerpc_vector_abi vector_abi
;
3424 for (vector_abi
= POWERPC_VEC_AUTO
;
3425 vector_abi
!= POWERPC_VEC_LAST
;
3427 if (strcmp (powerpc_vector_abi_string
,
3428 powerpc_vector_strings
[vector_abi
]) == 0)
3430 powerpc_vector_abi_global
= vector_abi
;
3434 if (vector_abi
== POWERPC_VEC_LAST
)
3435 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
3436 powerpc_vector_abi_string
);
3438 /* Update the architecture. */
3439 gdbarch_info_init (&info
);
3440 if (!gdbarch_update_p (info
))
3441 internal_error (__FILE__
, __LINE__
, "could not update architecture");
3444 /* Initialization code. */
3446 extern initialize_file_ftype _initialize_rs6000_tdep
; /* -Wmissing-prototypes */
3449 _initialize_rs6000_tdep (void)
3451 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3452 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
3454 /* Initialize the standard target descriptions. */
3455 initialize_tdesc_powerpc_32 ();
3456 initialize_tdesc_powerpc_altivec32 ();
3457 initialize_tdesc_powerpc_403 ();
3458 initialize_tdesc_powerpc_403gc ();
3459 initialize_tdesc_powerpc_505 ();
3460 initialize_tdesc_powerpc_601 ();
3461 initialize_tdesc_powerpc_602 ();
3462 initialize_tdesc_powerpc_603 ();
3463 initialize_tdesc_powerpc_604 ();
3464 initialize_tdesc_powerpc_64 ();
3465 initialize_tdesc_powerpc_altivec64 ();
3466 initialize_tdesc_powerpc_7400 ();
3467 initialize_tdesc_powerpc_750 ();
3468 initialize_tdesc_powerpc_860 ();
3469 initialize_tdesc_powerpc_e500 ();
3470 initialize_tdesc_rs6000 ();
3472 /* Add root prefix command for all "set powerpc"/"show powerpc"
3474 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
3475 _("Various PowerPC-specific commands."),
3476 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
3478 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
3479 _("Various PowerPC-specific commands."),
3480 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
3482 /* Add a command to allow the user to force the ABI. */
3483 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
3484 &powerpc_soft_float_global
,
3485 _("Set whether to use a soft-float ABI."),
3486 _("Show whether to use a soft-float ABI."),
3488 powerpc_set_soft_float
, NULL
,
3489 &setpowerpccmdlist
, &showpowerpccmdlist
);
3491 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
3492 &powerpc_vector_abi_string
,
3493 _("Set the vector ABI."),
3494 _("Show the vector ABI."),
3495 NULL
, powerpc_set_vector_abi
, NULL
,
3496 &setpowerpccmdlist
, &showpowerpccmdlist
);