1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* The list of available "set powerpc ..." and "show powerpc ..."
111 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
112 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
114 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
116 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
117 static const char *const powerpc_vector_strings
[] =
126 /* A variable that can be configured by the user. */
127 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
128 static const char *powerpc_vector_abi_string
= "auto";
130 /* To be used by skip_prologue. */
132 struct rs6000_framedata
134 int offset
; /* total size of frame --- the distance
135 by which we decrement sp to allocate
137 int saved_gpr
; /* smallest # of saved gpr */
138 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
139 int saved_fpr
; /* smallest # of saved fpr */
140 int saved_vr
; /* smallest # of saved vr */
141 int saved_ev
; /* smallest # of saved ev */
142 int alloca_reg
; /* alloca register number (frame ptr) */
143 char frameless
; /* true if frameless functions. */
144 char nosavedpc
; /* true if pc not saved. */
145 char used_bl
; /* true if link register clobbered */
146 int gpr_offset
; /* offset of saved gprs from prev sp */
147 int fpr_offset
; /* offset of saved fprs from prev sp */
148 int vr_offset
; /* offset of saved vrs from prev sp */
149 int ev_offset
; /* offset of saved evs from prev sp */
150 int lr_offset
; /* offset of saved lr */
151 int lr_register
; /* register of saved lr, if trustworthy */
152 int cr_offset
; /* offset of saved cr */
153 int vrsave_offset
; /* offset of saved vrsave register */
157 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
159 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
161 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
162 if (tdep
->ppc_vsr0_regnum
< 0)
165 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
166 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
169 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
171 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
173 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
174 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
177 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
181 /* Return true if REGNO is an SPE register, false otherwise. */
183 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
185 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
187 /* Is it a reference to EV0 -- EV31, and do we have those? */
188 if (IS_SPE_PSEUDOREG (tdep
, regno
))
191 /* Is it a reference to one of the raw upper GPR halves? */
192 if (tdep
->ppc_ev0_upper_regnum
>= 0
193 && tdep
->ppc_ev0_upper_regnum
<= regno
194 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
197 /* Is it a reference to the 64-bit accumulator, and do we have that? */
198 if (tdep
->ppc_acc_regnum
>= 0
199 && tdep
->ppc_acc_regnum
== regno
)
202 /* Is it a reference to the SPE floating-point status and control register,
203 and do we have that? */
204 if (tdep
->ppc_spefscr_regnum
>= 0
205 && tdep
->ppc_spefscr_regnum
== regno
)
212 /* Return non-zero if the architecture described by GDBARCH has
213 floating-point registers (f0 --- f31 and fpscr). */
215 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
217 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
219 return (tdep
->ppc_fp0_regnum
>= 0
220 && tdep
->ppc_fpscr_regnum
>= 0);
223 /* Return non-zero if the architecture described by GDBARCH has
224 VSX registers (vsr0 --- vsr63). */
226 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
230 return tdep
->ppc_vsr0_regnum
>= 0;
233 /* Return non-zero if the architecture described by GDBARCH has
234 Altivec registers (vr0 --- vr31, vrsave and vscr). */
236 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
238 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
240 return (tdep
->ppc_vr0_regnum
>= 0
241 && tdep
->ppc_vrsave_regnum
>= 0);
244 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
247 This is a helper function for init_sim_regno_table, constructing
248 the table mapping GDB register numbers to sim register numbers; we
249 initialize every element in that table to -1 before we start
252 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
254 /* Make sure we don't try to assign any given GDB register a sim
255 register number more than once. */
256 gdb_assert (table
[gdb_regno
] == -1);
257 table
[gdb_regno
] = sim_regno
;
261 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
262 numbers to simulator register numbers, based on the values placed
263 in the ARCH->tdep->ppc_foo_regnum members. */
265 init_sim_regno_table (struct gdbarch
*arch
)
267 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
268 int total_regs
= gdbarch_num_regs (arch
);
269 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
271 static const char *const segment_regs
[] = {
272 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
273 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
276 /* Presume that all registers not explicitly mentioned below are
277 unavailable from the sim. */
278 for (i
= 0; i
< total_regs
; i
++)
281 /* General-purpose registers. */
282 for (i
= 0; i
< ppc_num_gprs
; i
++)
283 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
285 /* Floating-point registers. */
286 if (tdep
->ppc_fp0_regnum
>= 0)
287 for (i
= 0; i
< ppc_num_fprs
; i
++)
288 set_sim_regno (sim_regno
,
289 tdep
->ppc_fp0_regnum
+ i
,
290 sim_ppc_f0_regnum
+ i
);
291 if (tdep
->ppc_fpscr_regnum
>= 0)
292 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
294 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
295 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
296 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
298 /* Segment registers. */
299 for (i
= 0; i
< ppc_num_srs
; i
++)
303 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
305 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
308 /* Altivec registers. */
309 if (tdep
->ppc_vr0_regnum
>= 0)
311 for (i
= 0; i
< ppc_num_vrs
; i
++)
312 set_sim_regno (sim_regno
,
313 tdep
->ppc_vr0_regnum
+ i
,
314 sim_ppc_vr0_regnum
+ i
);
316 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
317 we can treat this more like the other cases. */
318 set_sim_regno (sim_regno
,
319 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
320 sim_ppc_vscr_regnum
);
322 /* vsave is a special-purpose register, so the code below handles it. */
324 /* SPE APU (E500) registers. */
325 if (tdep
->ppc_ev0_upper_regnum
>= 0)
326 for (i
= 0; i
< ppc_num_gprs
; i
++)
327 set_sim_regno (sim_regno
,
328 tdep
->ppc_ev0_upper_regnum
+ i
,
329 sim_ppc_rh0_regnum
+ i
);
330 if (tdep
->ppc_acc_regnum
>= 0)
331 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
332 /* spefscr is a special-purpose register, so the code below handles it. */
335 /* Now handle all special-purpose registers. Verify that they
336 haven't mistakenly been assigned numbers by any of the above
338 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
340 const char *spr_name
= sim_spr_register_name (i
);
343 if (spr_name
!= NULL
)
344 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
347 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
351 /* Drop the initialized array into place. */
352 tdep
->sim_regno
= sim_regno
;
356 /* Given a GDB register number REG, return the corresponding SIM
359 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
361 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
364 if (tdep
->sim_regno
== NULL
)
365 init_sim_regno_table (gdbarch
);
368 && reg
<= gdbarch_num_regs (gdbarch
)
369 + gdbarch_num_pseudo_regs (gdbarch
));
370 sim_regno
= tdep
->sim_regno
[reg
];
375 return LEGACY_SIM_REGNO_IGNORE
;
380 /* Register set support functions. */
382 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
383 Write the register to REGCACHE. */
386 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
387 const gdb_byte
*regs
, size_t offset
, int regsize
)
389 if (regnum
!= -1 && offset
!= -1)
393 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
394 int gdb_regsize
= register_size (gdbarch
, regnum
);
395 if (gdb_regsize
< regsize
396 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
397 offset
+= regsize
- gdb_regsize
;
399 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
403 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
404 in a field REGSIZE wide. Zero pad as necessary. */
407 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
408 gdb_byte
*regs
, size_t offset
, int regsize
)
410 if (regnum
!= -1 && offset
!= -1)
414 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
415 int gdb_regsize
= register_size (gdbarch
, regnum
);
416 if (gdb_regsize
< regsize
)
418 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
420 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
421 offset
+= regsize
- gdb_regsize
;
424 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
425 regsize
- gdb_regsize
);
428 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
433 ppc_greg_offset (struct gdbarch
*gdbarch
,
434 struct gdbarch_tdep
*tdep
,
435 const struct ppc_reg_offsets
*offsets
,
439 *regsize
= offsets
->gpr_size
;
440 if (regnum
>= tdep
->ppc_gp0_regnum
441 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
442 return (offsets
->r0_offset
443 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
445 if (regnum
== gdbarch_pc_regnum (gdbarch
))
446 return offsets
->pc_offset
;
448 if (regnum
== tdep
->ppc_ps_regnum
)
449 return offsets
->ps_offset
;
451 if (regnum
== tdep
->ppc_lr_regnum
)
452 return offsets
->lr_offset
;
454 if (regnum
== tdep
->ppc_ctr_regnum
)
455 return offsets
->ctr_offset
;
457 *regsize
= offsets
->xr_size
;
458 if (regnum
== tdep
->ppc_cr_regnum
)
459 return offsets
->cr_offset
;
461 if (regnum
== tdep
->ppc_xer_regnum
)
462 return offsets
->xer_offset
;
464 if (regnum
== tdep
->ppc_mq_regnum
)
465 return offsets
->mq_offset
;
471 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
472 const struct ppc_reg_offsets
*offsets
,
475 if (regnum
>= tdep
->ppc_fp0_regnum
476 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
477 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
479 if (regnum
== tdep
->ppc_fpscr_regnum
)
480 return offsets
->fpscr_offset
;
486 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
487 const struct ppc_reg_offsets
*offsets
,
490 if (regnum
>= tdep
->ppc_vr0_regnum
491 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
492 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
494 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
495 return offsets
->vscr_offset
;
497 if (regnum
== tdep
->ppc_vrsave_regnum
)
498 return offsets
->vrsave_offset
;
503 /* Supply register REGNUM in the general-purpose register set REGSET
504 from the buffer specified by GREGS and LEN to register cache
505 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
508 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
509 int regnum
, const void *gregs
, size_t len
)
511 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
512 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
513 const struct ppc_reg_offsets
*offsets
514 = (const struct ppc_reg_offsets
*) regset
->regmap
;
521 int gpr_size
= offsets
->gpr_size
;
523 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
524 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
525 i
++, offset
+= gpr_size
)
526 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
529 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
530 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
531 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
532 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
533 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
534 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
535 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
536 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
537 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
538 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
540 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
541 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
543 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
544 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
549 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
550 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
553 /* Supply register REGNUM in the floating-point register set REGSET
554 from the buffer specified by FPREGS and LEN to register cache
555 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
558 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
559 int regnum
, const void *fpregs
, size_t len
)
561 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
562 struct gdbarch_tdep
*tdep
;
563 const struct ppc_reg_offsets
*offsets
;
566 if (!ppc_floating_point_unit_p (gdbarch
))
569 tdep
= gdbarch_tdep (gdbarch
);
570 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
575 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
576 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
578 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
580 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
581 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
582 offsets
->fpscr_size
);
586 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
587 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
588 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
591 /* Supply register REGNUM in the VSX register set REGSET
592 from the buffer specified by VSXREGS and LEN to register cache
593 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
596 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
597 int regnum
, const void *vsxregs
, size_t len
)
599 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
600 struct gdbarch_tdep
*tdep
;
602 if (!ppc_vsx_support_p (gdbarch
))
605 tdep
= gdbarch_tdep (gdbarch
);
611 for (i
= tdep
->ppc_vsr0_upper_regnum
;
612 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
614 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vsxregs
, 0, 8);
619 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vsxregs
, 0, 8);
622 /* Supply register REGNUM in the Altivec register set REGSET
623 from the buffer specified by VRREGS and LEN to register cache
624 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
627 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
628 int regnum
, const void *vrregs
, size_t len
)
630 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
631 struct gdbarch_tdep
*tdep
;
632 const struct ppc_reg_offsets
*offsets
;
635 if (!ppc_altivec_support_p (gdbarch
))
638 tdep
= gdbarch_tdep (gdbarch
);
639 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
644 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
645 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
647 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vrregs
, offset
, 16);
649 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
650 (const gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
652 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
653 (const gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
657 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
658 if (regnum
!= tdep
->ppc_vrsave_regnum
659 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
660 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vrregs
, offset
, 16);
662 ppc_supply_reg (regcache
, regnum
,
663 (const gdb_byte
*) vrregs
, offset
, 4);
666 /* Collect register REGNUM in the general-purpose register set
667 REGSET from register cache REGCACHE into the buffer specified by
668 GREGS and LEN. If REGNUM is -1, do this for all registers in
672 ppc_collect_gregset (const struct regset
*regset
,
673 const struct regcache
*regcache
,
674 int regnum
, void *gregs
, size_t len
)
676 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
677 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
678 const struct ppc_reg_offsets
*offsets
679 = (const struct ppc_reg_offsets
*) regset
->regmap
;
686 int gpr_size
= offsets
->gpr_size
;
688 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
689 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
690 i
++, offset
+= gpr_size
)
691 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
693 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
694 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
695 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
696 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
697 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
698 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
699 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
700 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
701 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
702 (gdb_byte
*) gregs
, offsets
->cr_offset
,
704 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
705 (gdb_byte
*) gregs
, offsets
->xer_offset
,
707 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
708 (gdb_byte
*) gregs
, offsets
->mq_offset
,
713 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
714 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
717 /* Collect register REGNUM in the floating-point register set
718 REGSET from register cache REGCACHE into the buffer specified by
719 FPREGS and LEN. If REGNUM is -1, do this for all registers in
723 ppc_collect_fpregset (const struct regset
*regset
,
724 const struct regcache
*regcache
,
725 int regnum
, void *fpregs
, size_t len
)
727 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
728 struct gdbarch_tdep
*tdep
;
729 const struct ppc_reg_offsets
*offsets
;
732 if (!ppc_floating_point_unit_p (gdbarch
))
735 tdep
= gdbarch_tdep (gdbarch
);
736 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
741 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
742 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
744 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
746 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
747 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
748 offsets
->fpscr_size
);
752 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
753 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
754 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
757 /* Collect register REGNUM in the VSX register set
758 REGSET from register cache REGCACHE into the buffer specified by
759 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
763 ppc_collect_vsxregset (const struct regset
*regset
,
764 const struct regcache
*regcache
,
765 int regnum
, void *vsxregs
, size_t len
)
767 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
768 struct gdbarch_tdep
*tdep
;
770 if (!ppc_vsx_support_p (gdbarch
))
773 tdep
= gdbarch_tdep (gdbarch
);
779 for (i
= tdep
->ppc_vsr0_upper_regnum
;
780 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
782 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vsxregs
, 0, 8);
787 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vsxregs
, 0, 8);
791 /* Collect register REGNUM in the Altivec register set
792 REGSET from register cache REGCACHE into the buffer specified by
793 VRREGS and LEN. If REGNUM is -1, do this for all registers in
797 ppc_collect_vrregset (const struct regset
*regset
,
798 const struct regcache
*regcache
,
799 int regnum
, void *vrregs
, size_t len
)
801 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
802 struct gdbarch_tdep
*tdep
;
803 const struct ppc_reg_offsets
*offsets
;
806 if (!ppc_altivec_support_p (gdbarch
))
809 tdep
= gdbarch_tdep (gdbarch
);
810 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
815 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
816 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
818 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vrregs
, offset
, 16);
820 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
821 (gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
823 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
824 (gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
828 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
829 if (regnum
!= tdep
->ppc_vrsave_regnum
830 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
831 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vrregs
, offset
, 16);
833 ppc_collect_reg (regcache
, regnum
,
834 (gdb_byte
*) vrregs
, offset
, 4);
839 insn_changes_sp_or_jumps (unsigned long insn
)
841 int opcode
= (insn
>> 26) & 0x03f;
842 int sd
= (insn
>> 21) & 0x01f;
843 int a
= (insn
>> 16) & 0x01f;
844 int subcode
= (insn
>> 1) & 0x3ff;
846 /* Changes the stack pointer. */
848 /* NOTE: There are many ways to change the value of a given register.
849 The ways below are those used when the register is R1, the SP,
850 in a funtion's epilogue. */
852 if (opcode
== 31 && subcode
== 444 && a
== 1)
853 return 1; /* mr R1,Rn */
854 if (opcode
== 14 && sd
== 1)
855 return 1; /* addi R1,Rn,simm */
856 if (opcode
== 58 && sd
== 1)
857 return 1; /* ld R1,ds(Rn) */
859 /* Transfers control. */
865 if (opcode
== 19 && subcode
== 16)
867 if (opcode
== 19 && subcode
== 528)
868 return 1; /* bcctr */
873 /* Return true if we are in the function's epilogue, i.e. after the
874 instruction that destroyed the function's stack frame.
876 1) scan forward from the point of execution:
877 a) If you find an instruction that modifies the stack pointer
878 or transfers control (except a return), execution is not in
880 b) Stop scanning if you find a return instruction or reach the
881 end of the function or reach the hard limit for the size of
883 2) scan backward from the point of execution:
884 a) If you find an instruction that modifies the stack pointer,
885 execution *is* in an epilogue, return.
886 b) Stop scanning if you reach an instruction that transfers
887 control or the beginning of the function or reach the hard
888 limit for the size of an epilogue. */
891 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
892 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
894 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
895 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
896 bfd_byte insn_buf
[PPC_INSN_SIZE
];
897 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
900 /* Find the search limits based on function boundaries and hard limit. */
902 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
905 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
906 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
908 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
909 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
911 /* Scan forward until next 'blr'. */
913 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
915 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
917 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
918 if (insn
== 0x4e800020)
920 /* Assume a bctr is a tail call unless it points strictly within
922 if (insn
== 0x4e800420)
924 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
925 tdep
->ppc_ctr_regnum
);
926 if (ctr
> func_start
&& ctr
< func_end
)
931 if (insn_changes_sp_or_jumps (insn
))
935 /* Scan backward until adjustment to stack pointer (R1). */
937 for (scan_pc
= pc
- PPC_INSN_SIZE
;
938 scan_pc
>= epilogue_start
;
939 scan_pc
-= PPC_INSN_SIZE
)
941 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
943 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
944 if (insn_changes_sp_or_jumps (insn
))
951 /* Implement the stack_frame_destroyed_p gdbarch method. */
954 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
956 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
960 /* Get the ith function argument for the current function. */
962 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
965 return get_frame_register_unsigned (frame
, 3 + argi
);
968 /* Sequence of bytes for breakpoint instruction. */
970 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
971 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
973 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
976 /* Instruction masks for displaced stepping. */
977 #define BRANCH_MASK 0xfc000000
978 #define BP_MASK 0xFC0007FE
979 #define B_INSN 0x48000000
980 #define BC_INSN 0x40000000
981 #define BXL_INSN 0x4c000000
982 #define BP_INSN 0x7C000008
984 /* Instruction masks used during single-stepping of atomic
986 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
987 #define LWARX_INSTRUCTION 0x7c000028
988 #define LDARX_INSTRUCTION 0x7c0000A8
989 #define LBARX_INSTRUCTION 0x7c000068
990 #define LHARX_INSTRUCTION 0x7c0000e8
991 #define LQARX_INSTRUCTION 0x7c000228
992 #define STORE_CONDITIONAL_MASK 0xfc0007ff
993 #define STWCX_INSTRUCTION 0x7c00012d
994 #define STDCX_INSTRUCTION 0x7c0001ad
995 #define STBCX_INSTRUCTION 0x7c00056d
996 #define STHCX_INSTRUCTION 0x7c0005ad
997 #define STQCX_INSTRUCTION 0x7c00016d
999 /* Check if insn is one of the Load And Reserve instructions used for atomic
1001 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
1002 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
1003 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
1004 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
1005 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
1006 /* Check if insn is one of the Store Conditional instructions used for atomic
1008 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
1009 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
1010 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
1011 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
1012 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
1014 /* We can't displaced step atomic sequences. Otherwise this is just
1015 like simple_displaced_step_copy_insn. */
1017 static struct displaced_step_closure
*
1018 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1019 CORE_ADDR from
, CORE_ADDR to
,
1020 struct regcache
*regs
)
1022 size_t len
= gdbarch_max_insn_length (gdbarch
);
1023 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
);
1024 struct cleanup
*old_chain
= make_cleanup (xfree
, buf
);
1025 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1028 read_memory (from
, buf
, len
);
1030 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
1032 /* Assume all atomic sequences start with a Load and Reserve instruction. */
1033 if (IS_LOAD_AND_RESERVE_INSN (insn
))
1035 if (debug_displaced
)
1037 fprintf_unfiltered (gdb_stdlog
,
1038 "displaced: can't displaced step "
1039 "atomic sequence at %s\n",
1040 paddress (gdbarch
, from
));
1042 do_cleanups (old_chain
);
1046 write_memory (to
, buf
, len
);
1048 if (debug_displaced
)
1050 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1051 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1052 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1055 discard_cleanups (old_chain
);
1056 return (struct displaced_step_closure
*) buf
;
1059 /* Fix up the state of registers and memory after having single-stepped
1060 a displaced instruction. */
1062 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
1063 struct displaced_step_closure
*closure
,
1064 CORE_ADDR from
, CORE_ADDR to
,
1065 struct regcache
*regs
)
1067 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1068 /* Our closure is a copy of the instruction. */
1069 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
1070 PPC_INSN_SIZE
, byte_order
);
1071 ULONGEST opcode
= 0;
1072 /* Offset for non PC-relative instructions. */
1073 LONGEST offset
= PPC_INSN_SIZE
;
1075 opcode
= insn
& BRANCH_MASK
;
1077 if (debug_displaced
)
1078 fprintf_unfiltered (gdb_stdlog
,
1079 "displaced: (ppc) fixup (%s, %s)\n",
1080 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1083 /* Handle PC-relative branch instructions. */
1084 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1086 ULONGEST current_pc
;
1088 /* Read the current PC value after the instruction has been executed
1089 in a displaced location. Calculate the offset to be applied to the
1090 original PC value before the displaced stepping. */
1091 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1093 offset
= current_pc
- to
;
1095 if (opcode
!= BXL_INSN
)
1097 /* Check for AA bit indicating whether this is an absolute
1098 addressing or PC-relative (1: absolute, 0: relative). */
1101 /* PC-relative addressing is being used in the branch. */
1102 if (debug_displaced
)
1105 "displaced: (ppc) branch instruction: %s\n"
1106 "displaced: (ppc) adjusted PC from %s to %s\n",
1107 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1108 paddress (gdbarch
, from
+ offset
));
1110 regcache_cooked_write_unsigned (regs
,
1111 gdbarch_pc_regnum (gdbarch
),
1117 /* If we're here, it means we have a branch to LR or CTR. If the
1118 branch was taken, the offset is probably greater than 4 (the next
1119 instruction), so it's safe to assume that an offset of 4 means we
1120 did not take the branch. */
1121 if (offset
== PPC_INSN_SIZE
)
1122 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1123 from
+ PPC_INSN_SIZE
);
1126 /* Check for LK bit indicating whether we should set the link
1127 register to point to the next instruction
1128 (1: Set, 0: Don't set). */
1131 /* Link register needs to be set to the next instruction's PC. */
1132 regcache_cooked_write_unsigned (regs
,
1133 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1134 from
+ PPC_INSN_SIZE
);
1135 if (debug_displaced
)
1136 fprintf_unfiltered (gdb_stdlog
,
1137 "displaced: (ppc) adjusted LR to %s\n",
1138 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1142 /* Check for breakpoints in the inferior. If we've found one, place the PC
1143 right at the breakpoint instruction. */
1144 else if ((insn
& BP_MASK
) == BP_INSN
)
1145 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1147 /* Handle any other instructions that do not fit in the categories above. */
1148 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1152 /* Always use hardware single-stepping to execute the
1153 displaced instruction. */
1155 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1156 struct displaced_step_closure
*closure
)
1161 /* Checks for an atomic sequence of instructions beginning with a
1162 Load And Reserve instruction and ending with a Store Conditional
1163 instruction. If such a sequence is found, attempt to step through it.
1164 A breakpoint is placed at the end of the sequence. */
1166 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1168 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1169 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1170 CORE_ADDR pc
= regcache_read_pc (regcache
);
1171 CORE_ADDR breaks
[2] = {-1, -1};
1173 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1174 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1177 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1178 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1179 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1180 VEC (CORE_ADDR
) *next_pcs
= NULL
;
1182 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1183 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1186 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1188 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1190 loc
+= PPC_INSN_SIZE
;
1191 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1193 /* Assume that there is at most one conditional branch in the atomic
1194 sequence. If a conditional branch is found, put a breakpoint in
1195 its destination address. */
1196 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1198 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1199 int absolute
= insn
& 2;
1201 if (bc_insn_count
>= 1)
1202 return 0; /* More than one conditional branch found, fallback
1203 to the standard single-step code. */
1206 breaks
[1] = immediate
;
1208 breaks
[1] = loc
+ immediate
;
1214 if (IS_STORE_CONDITIONAL_INSN (insn
))
1218 /* Assume that the atomic sequence ends with a Store Conditional
1220 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1224 loc
+= PPC_INSN_SIZE
;
1225 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1227 /* Insert a breakpoint right after the end of the atomic sequence. */
1230 /* Check for duplicated breakpoints. Check also for a breakpoint
1231 placed (branch instruction's destination) anywhere in sequence. */
1233 && (breaks
[1] == breaks
[0]
1234 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1235 last_breakpoint
= 0;
1237 for (index
= 0; index
<= last_breakpoint
; index
++)
1238 VEC_safe_push (CORE_ADDR
, next_pcs
, breaks
[index
]);
1244 #define SIGNED_SHORT(x) \
1245 ((sizeof (short) == 2) \
1246 ? ((int)(short)(x)) \
1247 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1249 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1251 /* Limit the number of skipped non-prologue instructions, as the examining
1252 of the prologue is expensive. */
1253 static int max_skip_non_prologue_insns
= 10;
1255 /* Return nonzero if the given instruction OP can be part of the prologue
1256 of a function and saves a parameter on the stack. FRAMEP should be
1257 set if one of the previous instructions in the function has set the
1261 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1263 /* Move parameters from argument registers to temporary register. */
1264 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1266 /* Rx must be scratch register r0. */
1267 const int rx_regno
= (op
>> 16) & 31;
1268 /* Ry: Only r3 - r10 are used for parameter passing. */
1269 const int ry_regno
= GET_SRC_REG (op
);
1271 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1273 *r0_contains_arg
= 1;
1280 /* Save a General Purpose Register on stack. */
1282 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1283 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1285 /* Rx: Only r3 - r10 are used for parameter passing. */
1286 const int rx_regno
= GET_SRC_REG (op
);
1288 return (rx_regno
>= 3 && rx_regno
<= 10);
1291 /* Save a General Purpose Register on stack via the Frame Pointer. */
1294 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1295 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1296 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1298 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1299 However, the compiler sometimes uses r0 to hold an argument. */
1300 const int rx_regno
= GET_SRC_REG (op
);
1302 return ((rx_regno
>= 3 && rx_regno
<= 10)
1303 || (rx_regno
== 0 && *r0_contains_arg
));
1306 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1308 /* Only f2 - f8 are used for parameter passing. */
1309 const int src_regno
= GET_SRC_REG (op
);
1311 return (src_regno
>= 2 && src_regno
<= 8);
1314 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1316 /* Only f2 - f8 are used for parameter passing. */
1317 const int src_regno
= GET_SRC_REG (op
);
1319 return (src_regno
>= 2 && src_regno
<= 8);
1322 /* Not an insn that saves a parameter on stack. */
1326 /* Assuming that INSN is a "bl" instruction located at PC, return
1327 nonzero if the destination of the branch is a "blrl" instruction.
1329 This sequence is sometimes found in certain function prologues.
1330 It allows the function to load the LR register with a value that
1331 they can use to access PIC data using PC-relative offsets. */
1334 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1341 absolute
= (int) ((insn
>> 1) & 1);
1342 immediate
= ((insn
& ~3) << 6) >> 6;
1346 dest
= pc
+ immediate
;
1348 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1349 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1355 /* Masks for decoding a branch-and-link (bl) instruction.
1357 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1358 The former is anded with the opcode in question; if the result of
1359 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1360 question is a ``bl'' instruction.
1362 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1363 the branch displacement. */
1365 #define BL_MASK 0xfc000001
1366 #define BL_INSTRUCTION 0x48000001
1367 #define BL_DISPLACEMENT_MASK 0x03fffffc
1369 static unsigned long
1370 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1372 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1376 /* Fetch the instruction and convert it to an integer. */
1377 if (target_read_memory (pc
, buf
, 4))
1379 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1384 /* GCC generates several well-known sequences of instructions at the begining
1385 of each function prologue when compiling with -fstack-check. If one of
1386 such sequences starts at START_PC, then return the address of the
1387 instruction immediately past this sequence. Otherwise, return START_PC. */
1390 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1392 CORE_ADDR pc
= start_pc
;
1393 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1395 /* First possible sequence: A small number of probes.
1396 stw 0, -<some immediate>(1)
1397 [repeat this instruction any (small) number of times]. */
1399 if ((op
& 0xffff0000) == 0x90010000)
1401 while ((op
& 0xffff0000) == 0x90010000)
1404 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1409 /* Second sequence: A probing loop.
1410 addi 12,1,-<some immediate>
1411 lis 0,-<some immediate>
1412 [possibly ori 0,0,<some immediate>]
1416 addi 12,12,-<some immediate>
1419 [possibly one last probe: stw 0,<some immediate>(12)]. */
1423 /* addi 12,1,-<some immediate> */
1424 if ((op
& 0xffff0000) != 0x39810000)
1427 /* lis 0,-<some immediate> */
1429 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1430 if ((op
& 0xffff0000) != 0x3c000000)
1434 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1435 /* [possibly ori 0,0,<some immediate>] */
1436 if ((op
& 0xffff0000) == 0x60000000)
1439 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1442 if (op
!= 0x7c0c0214)
1447 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1448 if (op
!= 0x7c0c0000)
1453 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1454 if ((op
& 0xff9f0001) != 0x41820000)
1457 /* addi 12,12,-<some immediate> */
1459 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1460 if ((op
& 0xffff0000) != 0x398c0000)
1465 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1466 if (op
!= 0x900c0000)
1471 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1472 if ((op
& 0xfc000001) != 0x48000000)
1475 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1477 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1478 if ((op
& 0xffff0000) == 0x900c0000)
1481 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1484 /* We found a valid stack-check sequence, return the new PC. */
1488 /* Third sequence: No probe; instead, a comparizon between the stack size
1489 limit (saved in a run-time global variable) and the current stack
1492 addi 0,1,-<some immediate>
1493 lis 12,__gnat_stack_limit@ha
1494 lwz 12,__gnat_stack_limit@l(12)
1497 or, with a small variant in the case of a bigger stack frame:
1498 addis 0,1,<some immediate>
1499 addic 0,0,-<some immediate>
1500 lis 12,__gnat_stack_limit@ha
1501 lwz 12,__gnat_stack_limit@l(12)
1506 /* addi 0,1,-<some immediate> */
1507 if ((op
& 0xffff0000) != 0x38010000)
1509 /* small stack frame variant not recognized; try the
1510 big stack frame variant: */
1512 /* addis 0,1,<some immediate> */
1513 if ((op
& 0xffff0000) != 0x3c010000)
1516 /* addic 0,0,-<some immediate> */
1518 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1519 if ((op
& 0xffff0000) != 0x30000000)
1523 /* lis 12,<some immediate> */
1525 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1526 if ((op
& 0xffff0000) != 0x3d800000)
1529 /* lwz 12,<some immediate>(12) */
1531 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1532 if ((op
& 0xffff0000) != 0x818c0000)
1537 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1538 if ((op
& 0xfffffffe) != 0x7c406008)
1541 /* We found a valid stack-check sequence, return the new PC. */
1545 /* No stack check code in our prologue, return the start_pc. */
1549 /* return pc value after skipping a function prologue and also return
1550 information about a function frame.
1552 in struct rs6000_framedata fdata:
1553 - frameless is TRUE, if function does not have a frame.
1554 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1555 - offset is the initial size of this stack frame --- the amount by
1556 which we decrement the sp to allocate the frame.
1557 - saved_gpr is the number of the first saved gpr.
1558 - saved_fpr is the number of the first saved fpr.
1559 - saved_vr is the number of the first saved vr.
1560 - saved_ev is the number of the first saved ev.
1561 - alloca_reg is the number of the register used for alloca() handling.
1563 - gpr_offset is the offset of the first saved gpr from the previous frame.
1564 - fpr_offset is the offset of the first saved fpr from the previous frame.
1565 - vr_offset is the offset of the first saved vr from the previous frame.
1566 - ev_offset is the offset of the first saved ev from the previous frame.
1567 - lr_offset is the offset of the saved lr
1568 - cr_offset is the offset of the saved cr
1569 - vrsave_offset is the offset of the saved vrsave register. */
1572 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1573 struct rs6000_framedata
*fdata
)
1575 CORE_ADDR orig_pc
= pc
;
1576 CORE_ADDR last_prologue_pc
= pc
;
1577 CORE_ADDR li_found_pc
= 0;
1581 long vr_saved_offset
= 0;
1587 int vrsave_reg
= -1;
1590 int minimal_toc_loaded
= 0;
1591 int prev_insn_was_prologue_insn
= 1;
1592 int num_skip_non_prologue_insns
= 0;
1593 int r0_contains_arg
= 0;
1594 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1595 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1596 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1598 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1599 fdata
->saved_gpr
= -1;
1600 fdata
->saved_fpr
= -1;
1601 fdata
->saved_vr
= -1;
1602 fdata
->saved_ev
= -1;
1603 fdata
->alloca_reg
= -1;
1604 fdata
->frameless
= 1;
1605 fdata
->nosavedpc
= 1;
1606 fdata
->lr_register
= -1;
1608 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1614 /* Sometimes it isn't clear if an instruction is a prologue
1615 instruction or not. When we encounter one of these ambiguous
1616 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1617 Otherwise, we'll assume that it really is a prologue instruction. */
1618 if (prev_insn_was_prologue_insn
)
1619 last_prologue_pc
= pc
;
1621 /* Stop scanning if we've hit the limit. */
1625 prev_insn_was_prologue_insn
= 1;
1627 /* Fetch the instruction and convert it to an integer. */
1628 if (target_read_memory (pc
, buf
, 4))
1630 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1632 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1634 /* Since shared library / PIC code, which needs to get its
1635 address at runtime, can appear to save more than one link
1649 remember just the first one, but skip over additional
1652 lr_reg
= (op
& 0x03e00000) >> 21;
1654 r0_contains_arg
= 0;
1657 else if ((op
& 0xfc1fffff) == 0x7c000026)
1659 cr_reg
= (op
& 0x03e00000);
1661 r0_contains_arg
= 0;
1665 else if ((op
& 0xfc1f0000) == 0xd8010000)
1666 { /* stfd Rx,NUM(r1) */
1667 reg
= GET_SRC_REG (op
);
1668 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1670 fdata
->saved_fpr
= reg
;
1671 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1676 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1677 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1678 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1679 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1682 reg
= GET_SRC_REG (op
);
1683 if ((op
& 0xfc1f0000) == 0xbc010000)
1684 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1686 fdata
->gpr_mask
|= 1U << reg
;
1687 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1689 fdata
->saved_gpr
= reg
;
1690 if ((op
& 0xfc1f0003) == 0xf8010000)
1692 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1697 else if ((op
& 0xffff0000) == 0x3c4c0000
1698 || (op
& 0xffff0000) == 0x3c400000
1699 || (op
& 0xffff0000) == 0x38420000)
1701 /* . 0: addis 2,12,.TOC.-0b@ha
1702 . addi 2,2,.TOC.-0b@l
1706 used by ELFv2 global entry points to set up r2. */
1709 else if (op
== 0x60000000)
1712 /* Allow nops in the prologue, but do not consider them to
1713 be part of the prologue unless followed by other prologue
1715 prev_insn_was_prologue_insn
= 0;
1719 else if ((op
& 0xffff0000) == 0x3c000000)
1720 { /* addis 0,0,NUM, used for >= 32k frames */
1721 fdata
->offset
= (op
& 0x0000ffff) << 16;
1722 fdata
->frameless
= 0;
1723 r0_contains_arg
= 0;
1727 else if ((op
& 0xffff0000) == 0x60000000)
1728 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1729 fdata
->offset
|= (op
& 0x0000ffff);
1730 fdata
->frameless
= 0;
1731 r0_contains_arg
= 0;
1735 else if (lr_reg
>= 0 &&
1736 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1737 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1738 /* stw Rx, NUM(r1) */
1739 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1740 /* stwu Rx, NUM(r1) */
1741 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1742 { /* where Rx == lr */
1743 fdata
->lr_offset
= offset
;
1744 fdata
->nosavedpc
= 0;
1745 /* Invalidate lr_reg, but don't set it to -1.
1746 That would mean that it had never been set. */
1748 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1749 (op
& 0xfc000000) == 0x90000000) /* stw */
1751 /* Does not update r1, so add displacement to lr_offset. */
1752 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1757 else if (cr_reg
>= 0 &&
1758 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1759 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1760 /* stw Rx, NUM(r1) */
1761 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1762 /* stwu Rx, NUM(r1) */
1763 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1764 { /* where Rx == cr */
1765 fdata
->cr_offset
= offset
;
1766 /* Invalidate cr_reg, but don't set it to -1.
1767 That would mean that it had never been set. */
1769 if ((op
& 0xfc000003) == 0xf8000000 ||
1770 (op
& 0xfc000000) == 0x90000000)
1772 /* Does not update r1, so add displacement to cr_offset. */
1773 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1778 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1780 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1781 prediction bits. If the LR has already been saved, we can
1785 else if (op
== 0x48000005)
1792 else if (op
== 0x48000004)
1797 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1798 in V.4 -mminimal-toc */
1799 (op
& 0xffff0000) == 0x3bde0000)
1800 { /* addi 30,30,foo@l */
1804 else if ((op
& 0xfc000001) == 0x48000001)
1808 fdata
->frameless
= 0;
1810 /* If the return address has already been saved, we can skip
1811 calls to blrl (for PIC). */
1812 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1818 /* Don't skip over the subroutine call if it is not within
1819 the first three instructions of the prologue and either
1820 we have no line table information or the line info tells
1821 us that the subroutine call is not part of the line
1822 associated with the prologue. */
1823 if ((pc
- orig_pc
) > 8)
1825 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1826 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1828 if ((prologue_sal
.line
== 0)
1829 || (prologue_sal
.line
!= this_sal
.line
))
1833 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1835 /* At this point, make sure this is not a trampoline
1836 function (a function that simply calls another functions,
1837 and nothing else). If the next is not a nop, this branch
1838 was part of the function prologue. */
1840 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1841 break; /* Don't skip over
1847 /* update stack pointer */
1848 else if ((op
& 0xfc1f0000) == 0x94010000)
1849 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1850 fdata
->frameless
= 0;
1851 fdata
->offset
= SIGNED_SHORT (op
);
1852 offset
= fdata
->offset
;
1855 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1856 { /* stwux rX,r1,rY */
1857 /* No way to figure out what r1 is going to be. */
1858 fdata
->frameless
= 0;
1859 offset
= fdata
->offset
;
1862 else if ((op
& 0xfc1f0003) == 0xf8010001)
1863 { /* stdu rX,NUM(r1) */
1864 fdata
->frameless
= 0;
1865 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1866 offset
= fdata
->offset
;
1869 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1870 { /* stdux rX,r1,rY */
1871 /* No way to figure out what r1 is going to be. */
1872 fdata
->frameless
= 0;
1873 offset
= fdata
->offset
;
1876 else if ((op
& 0xffff0000) == 0x38210000)
1877 { /* addi r1,r1,SIMM */
1878 fdata
->frameless
= 0;
1879 fdata
->offset
+= SIGNED_SHORT (op
);
1880 offset
= fdata
->offset
;
1883 /* Load up minimal toc pointer. Do not treat an epilogue restore
1884 of r31 as a minimal TOC load. */
1885 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1886 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1888 && !minimal_toc_loaded
)
1890 minimal_toc_loaded
= 1;
1893 /* move parameters from argument registers to local variable
1896 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1897 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1898 (((op
>> 21) & 31) <= 10) &&
1899 ((long) ((op
>> 16) & 31)
1900 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1904 /* store parameters in stack */
1906 /* Move parameters from argument registers to temporary register. */
1907 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1911 /* Set up frame pointer */
1913 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1915 fdata
->frameless
= 0;
1917 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1920 /* Another way to set up the frame pointer. */
1922 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1923 || op
== 0x7c3f0b78)
1925 fdata
->frameless
= 0;
1927 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1930 /* Another way to set up the frame pointer. */
1932 else if ((op
& 0xfc1fffff) == 0x38010000)
1933 { /* addi rX, r1, 0x0 */
1934 fdata
->frameless
= 0;
1936 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1937 + ((op
& ~0x38010000) >> 21));
1940 /* AltiVec related instructions. */
1941 /* Store the vrsave register (spr 256) in another register for
1942 later manipulation, or load a register into the vrsave
1943 register. 2 instructions are used: mfvrsave and
1944 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1945 and mtspr SPR256, Rn. */
1946 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1947 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1948 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1950 vrsave_reg
= GET_SRC_REG (op
);
1953 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1957 /* Store the register where vrsave was saved to onto the stack:
1958 rS is the register where vrsave was stored in a previous
1960 /* 100100 sssss 00001 dddddddd dddddddd */
1961 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1963 if (vrsave_reg
== GET_SRC_REG (op
))
1965 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1970 /* Compute the new value of vrsave, by modifying the register
1971 where vrsave was saved to. */
1972 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1973 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1977 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1978 in a pair of insns to save the vector registers on the
1980 /* 001110 00000 00000 iiii iiii iiii iiii */
1981 /* 001110 01110 00000 iiii iiii iiii iiii */
1982 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1983 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1985 if ((op
& 0xffff0000) == 0x38000000)
1986 r0_contains_arg
= 0;
1988 vr_saved_offset
= SIGNED_SHORT (op
);
1990 /* This insn by itself is not part of the prologue, unless
1991 if part of the pair of insns mentioned above. So do not
1992 record this insn as part of the prologue yet. */
1993 prev_insn_was_prologue_insn
= 0;
1995 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1996 /* 011111 sssss 11111 00000 00111001110 */
1997 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1999 if (pc
== (li_found_pc
+ 4))
2001 vr_reg
= GET_SRC_REG (op
);
2002 /* If this is the first vector reg to be saved, or if
2003 it has a lower number than others previously seen,
2004 reupdate the frame info. */
2005 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
2007 fdata
->saved_vr
= vr_reg
;
2008 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2010 vr_saved_offset
= -1;
2015 /* End AltiVec related instructions. */
2017 /* Start BookE related instructions. */
2018 /* Store gen register S at (r31+uimm).
2019 Any register less than r13 is volatile, so we don't care. */
2020 /* 000100 sssss 11111 iiiii 01100100001 */
2021 else if (arch_info
->mach
== bfd_mach_ppc_e500
2022 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2024 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2027 ev_reg
= GET_SRC_REG (op
);
2028 imm
= (op
>> 11) & 0x1f;
2029 ev_offset
= imm
* 8;
2030 /* If this is the first vector reg to be saved, or if
2031 it has a lower number than others previously seen,
2032 reupdate the frame info. */
2033 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2035 fdata
->saved_ev
= ev_reg
;
2036 fdata
->ev_offset
= ev_offset
+ offset
;
2041 /* Store gen register rS at (r1+rB). */
2042 /* 000100 sssss 00001 bbbbb 01100100000 */
2043 else if (arch_info
->mach
== bfd_mach_ppc_e500
2044 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2046 if (pc
== (li_found_pc
+ 4))
2048 ev_reg
= GET_SRC_REG (op
);
2049 /* If this is the first vector reg to be saved, or if
2050 it has a lower number than others previously seen,
2051 reupdate the frame info. */
2052 /* We know the contents of rB from the previous instruction. */
2053 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2055 fdata
->saved_ev
= ev_reg
;
2056 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2058 vr_saved_offset
= -1;
2064 /* Store gen register r31 at (rA+uimm). */
2065 /* 000100 11111 aaaaa iiiii 01100100001 */
2066 else if (arch_info
->mach
== bfd_mach_ppc_e500
2067 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2069 /* Wwe know that the source register is 31 already, but
2070 it can't hurt to compute it. */
2071 ev_reg
= GET_SRC_REG (op
);
2072 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2073 /* If this is the first vector reg to be saved, or if
2074 it has a lower number than others previously seen,
2075 reupdate the frame info. */
2076 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2078 fdata
->saved_ev
= ev_reg
;
2079 fdata
->ev_offset
= ev_offset
+ offset
;
2084 /* Store gen register S at (r31+r0).
2085 Store param on stack when offset from SP bigger than 4 bytes. */
2086 /* 000100 sssss 11111 00000 01100100000 */
2087 else if (arch_info
->mach
== bfd_mach_ppc_e500
2088 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2090 if (pc
== (li_found_pc
+ 4))
2092 if ((op
& 0x03e00000) >= 0x01a00000)
2094 ev_reg
= GET_SRC_REG (op
);
2095 /* If this is the first vector reg to be saved, or if
2096 it has a lower number than others previously seen,
2097 reupdate the frame info. */
2098 /* We know the contents of r0 from the previous
2100 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2102 fdata
->saved_ev
= ev_reg
;
2103 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2107 vr_saved_offset
= -1;
2112 /* End BookE related instructions. */
2116 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2118 /* Not a recognized prologue instruction.
2119 Handle optimizer code motions into the prologue by continuing
2120 the search if we have no valid frame yet or if the return
2121 address is not yet saved in the frame. Also skip instructions
2122 if some of the GPRs expected to be saved are not yet saved. */
2123 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2124 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2127 if (op
== 0x4e800020 /* blr */
2128 || op
== 0x4e800420) /* bctr */
2129 /* Do not scan past epilogue in frameless functions or
2132 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2133 /* Never skip branches. */
2136 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2137 /* Do not scan too many insns, scanning insns is expensive with
2141 /* Continue scanning. */
2142 prev_insn_was_prologue_insn
= 0;
2148 /* I have problems with skipping over __main() that I need to address
2149 * sometime. Previously, I used to use misc_function_vector which
2150 * didn't work as well as I wanted to be. -MGO */
2152 /* If the first thing after skipping a prolog is a branch to a function,
2153 this might be a call to an initializer in main(), introduced by gcc2.
2154 We'd like to skip over it as well. Fortunately, xlc does some extra
2155 work before calling a function right after a prologue, thus we can
2156 single out such gcc2 behaviour. */
2159 if ((op
& 0xfc000001) == 0x48000001)
2160 { /* bl foo, an initializer function? */
2161 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2163 if (op
== 0x4def7b82)
2164 { /* cror 0xf, 0xf, 0xf (nop) */
2166 /* Check and see if we are in main. If so, skip over this
2167 initializer function as well. */
2169 tmp
= find_pc_misc_function (pc
);
2171 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2177 if (pc
== lim_pc
&& lr_reg
>= 0)
2178 fdata
->lr_register
= lr_reg
;
2180 fdata
->offset
= -fdata
->offset
;
2181 return last_prologue_pc
;
2185 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2187 struct rs6000_framedata frame
;
2188 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2190 /* See if we can determine the end of the prologue via the symbol table.
2191 If so, then return either PC, or the PC after the prologue, whichever
2193 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2195 CORE_ADDR post_prologue_pc
2196 = skip_prologue_using_sal (gdbarch
, func_addr
);
2197 if (post_prologue_pc
!= 0)
2198 return std::max (pc
, post_prologue_pc
);
2201 /* Can't determine prologue from the symbol table, need to examine
2204 /* Find an upper limit on the function prologue using the debug
2205 information. If the debug information could not be used to provide
2206 that bound, then use an arbitrary large number as the upper bound. */
2207 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2209 limit_pc
= pc
+ 100; /* Magic. */
2211 /* Do not allow limit_pc to be past the function end, if we know
2212 where that end is... */
2213 if (func_end_addr
&& limit_pc
> func_end_addr
)
2214 limit_pc
= func_end_addr
;
2216 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2220 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2221 in the prologue of main().
2223 The function below examines the code pointed at by PC and checks to
2224 see if it corresponds to a call to __eabi. If so, it returns the
2225 address of the instruction following that call. Otherwise, it simply
2229 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2231 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2235 if (target_read_memory (pc
, buf
, 4))
2237 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2239 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2241 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2242 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2243 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2245 /* We check for ___eabi (three leading underscores) in addition
2246 to __eabi in case the GCC option "-fleading-underscore" was
2247 used to compile the program. */
2248 if (s
.minsym
!= NULL
2249 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2250 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2251 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2257 /* All the ABI's require 16 byte alignment. */
2259 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2261 return (addr
& -16);
2264 /* Return whether handle_inferior_event() should proceed through code
2265 starting at PC in function NAME when stepping.
2267 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2268 handle memory references that are too distant to fit in instructions
2269 generated by the compiler. For example, if 'foo' in the following
2274 is greater than 32767, the linker might replace the lwz with a branch to
2275 somewhere in @FIX1 that does the load in 2 instructions and then branches
2276 back to where execution should continue.
2278 GDB should silently step over @FIX code, just like AIX dbx does.
2279 Unfortunately, the linker uses the "b" instruction for the
2280 branches, meaning that the link register doesn't get set.
2281 Therefore, GDB's usual step_over_function () mechanism won't work.
2283 Instead, use the gdbarch_skip_trampoline_code and
2284 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2288 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2289 CORE_ADDR pc
, const char *name
)
2291 return name
&& startswith (name
, "@FIX");
2294 /* Skip code that the user doesn't want to see when stepping:
2296 1. Indirect function calls use a piece of trampoline code to do context
2297 switching, i.e. to set the new TOC table. Skip such code if we are on
2298 its first instruction (as when we have single-stepped to here).
2300 2. Skip shared library trampoline code (which is different from
2301 indirect function call trampolines).
2303 3. Skip bigtoc fixup code.
2305 Result is desired PC to step until, or NULL if we are not in
2306 code that should be skipped. */
2309 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2311 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2313 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2314 unsigned int ii
, op
;
2316 CORE_ADDR solib_target_pc
;
2317 struct bound_minimal_symbol msymbol
;
2319 static unsigned trampoline_code
[] =
2321 0x800b0000, /* l r0,0x0(r11) */
2322 0x90410014, /* st r2,0x14(r1) */
2323 0x7c0903a6, /* mtctr r0 */
2324 0x804b0004, /* l r2,0x4(r11) */
2325 0x816b0008, /* l r11,0x8(r11) */
2326 0x4e800420, /* bctr */
2327 0x4e800020, /* br */
2331 /* Check for bigtoc fixup code. */
2332 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2334 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2335 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2337 /* Double-check that the third instruction from PC is relative "b". */
2338 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2339 if ((op
& 0xfc000003) == 0x48000000)
2341 /* Extract bits 6-29 as a signed 24-bit relative word address and
2342 add it to the containing PC. */
2343 rel
= ((int)(op
<< 6) >> 6);
2344 return pc
+ 8 + rel
;
2348 /* If pc is in a shared library trampoline, return its target. */
2349 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2350 if (solib_target_pc
)
2351 return solib_target_pc
;
2353 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2355 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2356 if (op
!= trampoline_code
[ii
])
2359 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2361 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2365 /* ISA-specific vector types. */
2367 static struct type
*
2368 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2370 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2372 if (!tdep
->ppc_builtin_type_vec64
)
2374 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2376 /* The type we're building is this: */
2378 union __gdb_builtin_type_vec64
2382 int32_t v2_int32
[2];
2383 int16_t v4_int16
[4];
2390 t
= arch_composite_type (gdbarch
,
2391 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2392 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2393 append_composite_type_field (t
, "v2_float",
2394 init_vector_type (bt
->builtin_float
, 2));
2395 append_composite_type_field (t
, "v2_int32",
2396 init_vector_type (bt
->builtin_int32
, 2));
2397 append_composite_type_field (t
, "v4_int16",
2398 init_vector_type (bt
->builtin_int16
, 4));
2399 append_composite_type_field (t
, "v8_int8",
2400 init_vector_type (bt
->builtin_int8
, 8));
2402 TYPE_VECTOR (t
) = 1;
2403 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2404 tdep
->ppc_builtin_type_vec64
= t
;
2407 return tdep
->ppc_builtin_type_vec64
;
2410 /* Vector 128 type. */
2412 static struct type
*
2413 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2415 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2417 if (!tdep
->ppc_builtin_type_vec128
)
2419 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2421 /* The type we're building is this
2423 type = union __ppc_builtin_type_vec128 {
2425 double v2_double[2];
2427 int32_t v4_int32[4];
2428 int16_t v8_int16[8];
2429 int8_t v16_int8[16];
2435 t
= arch_composite_type (gdbarch
,
2436 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2437 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2438 append_composite_type_field (t
, "v2_double",
2439 init_vector_type (bt
->builtin_double
, 2));
2440 append_composite_type_field (t
, "v4_float",
2441 init_vector_type (bt
->builtin_float
, 4));
2442 append_composite_type_field (t
, "v4_int32",
2443 init_vector_type (bt
->builtin_int32
, 4));
2444 append_composite_type_field (t
, "v8_int16",
2445 init_vector_type (bt
->builtin_int16
, 8));
2446 append_composite_type_field (t
, "v16_int8",
2447 init_vector_type (bt
->builtin_int8
, 16));
2449 TYPE_VECTOR (t
) = 1;
2450 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2451 tdep
->ppc_builtin_type_vec128
= t
;
2454 return tdep
->ppc_builtin_type_vec128
;
2457 /* Return the name of register number REGNO, or the empty string if it
2458 is an anonymous register. */
2461 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2463 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2465 /* The upper half "registers" have names in the XML description,
2466 but we present only the low GPRs and the full 64-bit registers
2468 if (tdep
->ppc_ev0_upper_regnum
>= 0
2469 && tdep
->ppc_ev0_upper_regnum
<= regno
2470 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2473 /* Hide the upper halves of the vs0~vs31 registers. */
2474 if (tdep
->ppc_vsr0_regnum
>= 0
2475 && tdep
->ppc_vsr0_upper_regnum
<= regno
2476 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2479 /* Check if the SPE pseudo registers are available. */
2480 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2482 static const char *const spe_regnames
[] = {
2483 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2484 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2485 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2486 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2488 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2491 /* Check if the decimal128 pseudo-registers are available. */
2492 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2494 static const char *const dfp128_regnames
[] = {
2495 "dl0", "dl1", "dl2", "dl3",
2496 "dl4", "dl5", "dl6", "dl7",
2497 "dl8", "dl9", "dl10", "dl11",
2498 "dl12", "dl13", "dl14", "dl15"
2500 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2503 /* Check if this is a VSX pseudo-register. */
2504 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2506 static const char *const vsx_regnames
[] = {
2507 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2508 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2509 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2510 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2511 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2512 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2513 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2514 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2515 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2517 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2520 /* Check if the this is a Extended FP pseudo-register. */
2521 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2523 static const char *const efpr_regnames
[] = {
2524 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2525 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2526 "f46", "f47", "f48", "f49", "f50", "f51",
2527 "f52", "f53", "f54", "f55", "f56", "f57",
2528 "f58", "f59", "f60", "f61", "f62", "f63"
2530 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2533 return tdesc_register_name (gdbarch
, regno
);
2536 /* Return the GDB type object for the "standard" data type of data in
2539 static struct type
*
2540 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2542 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2544 /* These are the only pseudo-registers we support. */
2545 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2546 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2547 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2548 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2550 /* These are the e500 pseudo-registers. */
2551 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2552 return rs6000_builtin_type_vec64 (gdbarch
);
2553 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2554 /* PPC decimal128 pseudo-registers. */
2555 return builtin_type (gdbarch
)->builtin_declong
;
2556 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2557 /* POWER7 VSX pseudo-registers. */
2558 return rs6000_builtin_type_vec128 (gdbarch
);
2560 /* POWER7 Extended FP pseudo-registers. */
2561 return builtin_type (gdbarch
)->builtin_double
;
2564 /* Is REGNUM a member of REGGROUP? */
2566 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2567 struct reggroup
*group
)
2569 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2571 /* These are the only pseudo-registers we support. */
2572 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2573 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2574 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2575 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2577 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2578 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2579 return group
== all_reggroup
|| group
== vector_reggroup
;
2581 /* PPC decimal128 or Extended FP pseudo-registers. */
2582 return group
== all_reggroup
|| group
== float_reggroup
;
2585 /* The register format for RS/6000 floating point registers is always
2586 double, we need a conversion if the memory format is float. */
2589 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2592 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2594 return (tdep
->ppc_fp0_regnum
>= 0
2595 && regnum
>= tdep
->ppc_fp0_regnum
2596 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2597 && TYPE_CODE (type
) == TYPE_CODE_FLT
2598 && TYPE_LENGTH (type
)
2599 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2603 rs6000_register_to_value (struct frame_info
*frame
,
2607 int *optimizedp
, int *unavailablep
)
2609 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2610 gdb_byte from
[MAX_REGISTER_SIZE
];
2612 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2614 if (!get_frame_register_bytes (frame
, regnum
, 0,
2615 register_size (gdbarch
, regnum
),
2616 from
, optimizedp
, unavailablep
))
2619 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2621 *optimizedp
= *unavailablep
= 0;
2626 rs6000_value_to_register (struct frame_info
*frame
,
2629 const gdb_byte
*from
)
2631 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2632 gdb_byte to
[MAX_REGISTER_SIZE
];
2634 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2636 convert_typed_floating (from
, type
,
2637 to
, builtin_type (gdbarch
)->builtin_double
);
2638 put_frame_register (frame
, regnum
, to
);
2641 /* The type of a function that moves the value of REG between CACHE
2642 or BUF --- in either direction. */
2643 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2646 /* Move SPE vector register values between a 64-bit buffer and the two
2647 32-bit raw register halves in a regcache. This function handles
2648 both splitting a 64-bit value into two 32-bit halves, and joining
2649 two halves into a whole 64-bit value, depending on the function
2650 passed as the MOVE argument.
2652 EV_REG must be the number of an SPE evN vector register --- a
2653 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2656 Call MOVE once for each 32-bit half of that register, passing
2657 REGCACHE, the number of the raw register corresponding to that
2658 half, and the address of the appropriate half of BUFFER.
2660 For example, passing 'regcache_raw_read' as the MOVE function will
2661 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2662 'regcache_raw_supply' will supply the contents of BUFFER to the
2663 appropriate pair of raw registers in REGCACHE.
2665 You may need to cast away some 'const' qualifiers when passing
2666 MOVE, since this function can't tell at compile-time which of
2667 REGCACHE or BUFFER is acting as the source of the data. If C had
2668 co-variant type qualifiers, ... */
2670 static enum register_status
2671 e500_move_ev_register (move_ev_register_func move
,
2672 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2674 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2675 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2677 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2678 enum register_status status
;
2680 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2682 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2684 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2686 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2688 if (status
== REG_VALID
)
2689 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2694 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2695 if (status
== REG_VALID
)
2696 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2703 static enum register_status
2704 do_regcache_raw_read (struct regcache
*regcache
, int regnum
, void *buffer
)
2706 return regcache_raw_read (regcache
, regnum
, (gdb_byte
*) buffer
);
2709 static enum register_status
2710 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2712 regcache_raw_write (regcache
, regnum
, (const gdb_byte
*) buffer
);
2717 static enum register_status
2718 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2719 int reg_nr
, gdb_byte
*buffer
)
2721 return e500_move_ev_register (do_regcache_raw_read
, regcache
, reg_nr
, buffer
);
2725 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2726 int reg_nr
, const gdb_byte
*buffer
)
2728 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2729 reg_nr
, (void *) buffer
);
2732 /* Read method for DFP pseudo-registers. */
2733 static enum register_status
2734 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2735 int reg_nr
, gdb_byte
*buffer
)
2737 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2738 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2739 enum register_status status
;
2741 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2743 /* Read two FP registers to form a whole dl register. */
2744 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2745 2 * reg_index
, buffer
);
2746 if (status
== REG_VALID
)
2747 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2748 2 * reg_index
+ 1, buffer
+ 8);
2752 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2753 2 * reg_index
+ 1, buffer
);
2754 if (status
== REG_VALID
)
2755 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2756 2 * reg_index
, buffer
+ 8);
2762 /* Write method for DFP pseudo-registers. */
2764 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2765 int reg_nr
, const gdb_byte
*buffer
)
2767 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2768 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2770 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2772 /* Write each half of the dl register into a separate
2774 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2775 2 * reg_index
, buffer
);
2776 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2777 2 * reg_index
+ 1, buffer
+ 8);
2781 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2782 2 * reg_index
+ 1, buffer
);
2783 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2784 2 * reg_index
, buffer
+ 8);
2788 /* Read method for POWER7 VSX pseudo-registers. */
2789 static enum register_status
2790 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2791 int reg_nr
, gdb_byte
*buffer
)
2793 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2794 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2795 enum register_status status
;
2797 /* Read the portion that overlaps the VMX registers. */
2799 status
= regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2800 reg_index
- 32, buffer
);
2802 /* Read the portion that overlaps the FPR registers. */
2803 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2805 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2807 if (status
== REG_VALID
)
2808 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2809 reg_index
, buffer
+ 8);
2813 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2814 reg_index
, buffer
+ 8);
2815 if (status
== REG_VALID
)
2816 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2823 /* Write method for POWER7 VSX pseudo-registers. */
2825 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2826 int reg_nr
, const gdb_byte
*buffer
)
2828 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2829 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2831 /* Write the portion that overlaps the VMX registers. */
2833 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2834 reg_index
- 32, buffer
);
2836 /* Write the portion that overlaps the FPR registers. */
2837 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2839 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2841 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2842 reg_index
, buffer
+ 8);
2846 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2847 reg_index
, buffer
+ 8);
2848 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2853 /* Read method for POWER7 Extended FP pseudo-registers. */
2854 static enum register_status
2855 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2856 int reg_nr
, gdb_byte
*buffer
)
2858 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2859 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2860 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2862 /* Read the portion that overlaps the VMX register. */
2863 return regcache_raw_read_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2864 offset
, register_size (gdbarch
, reg_nr
),
2868 /* Write method for POWER7 Extended FP pseudo-registers. */
2870 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2871 int reg_nr
, const gdb_byte
*buffer
)
2873 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2874 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2875 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2877 /* Write the portion that overlaps the VMX register. */
2878 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2879 offset
, register_size (gdbarch
, reg_nr
),
2883 static enum register_status
2884 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2885 struct regcache
*regcache
,
2886 int reg_nr
, gdb_byte
*buffer
)
2888 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2889 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2891 gdb_assert (regcache_arch
== gdbarch
);
2893 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2894 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2895 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2896 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2897 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2898 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2899 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2900 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2902 internal_error (__FILE__
, __LINE__
,
2903 _("rs6000_pseudo_register_read: "
2904 "called on unexpected register '%s' (%d)"),
2905 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2909 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2910 struct regcache
*regcache
,
2911 int reg_nr
, const gdb_byte
*buffer
)
2913 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2914 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2916 gdb_assert (regcache_arch
== gdbarch
);
2918 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2919 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2920 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2921 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2922 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2923 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2924 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2925 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2927 internal_error (__FILE__
, __LINE__
,
2928 _("rs6000_pseudo_register_write: "
2929 "called on unexpected register '%s' (%d)"),
2930 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2934 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2935 struct agent_expr
*ax
, int reg_nr
)
2937 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2938 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2940 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
2941 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
2942 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
2944 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2946 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2947 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
);
2948 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
+ 1);
2950 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2952 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2955 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
- 32);
2959 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ reg_index
);
2960 ax_reg_mask (ax
, tdep
->ppc_vsr0_upper_regnum
+ reg_index
);
2963 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2965 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2966 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
);
2969 internal_error (__FILE__
, __LINE__
,
2970 _("rs6000_pseudo_register_collect: "
2971 "called on unexpected register '%s' (%d)"),
2972 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2978 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
2979 struct agent_expr
*ax
, struct axs_value
*value
,
2982 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2983 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
2984 value
->kind
= axs_lvalue_register
;
2985 value
->u
.reg
= tdep
->ppc_lr_regnum
;
2989 /* Convert a DBX STABS register number to a GDB register number. */
2991 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2993 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2995 if (0 <= num
&& num
<= 31)
2996 return tdep
->ppc_gp0_regnum
+ num
;
2997 else if (32 <= num
&& num
<= 63)
2998 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2999 specifies registers the architecture doesn't have? Our
3000 callers don't check the value we return. */
3001 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3002 else if (77 <= num
&& num
<= 108)
3003 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3004 else if (1200 <= num
&& num
< 1200 + 32)
3005 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3010 return tdep
->ppc_mq_regnum
;
3012 return tdep
->ppc_lr_regnum
;
3014 return tdep
->ppc_ctr_regnum
;
3016 return tdep
->ppc_xer_regnum
;
3018 return tdep
->ppc_vrsave_regnum
;
3020 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3022 return tdep
->ppc_acc_regnum
;
3024 return tdep
->ppc_spefscr_regnum
;
3031 /* Convert a Dwarf 2 register number to a GDB register number. */
3033 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3035 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3037 if (0 <= num
&& num
<= 31)
3038 return tdep
->ppc_gp0_regnum
+ num
;
3039 else if (32 <= num
&& num
<= 63)
3040 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3041 specifies registers the architecture doesn't have? Our
3042 callers don't check the value we return. */
3043 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3044 else if (1124 <= num
&& num
< 1124 + 32)
3045 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3046 else if (1200 <= num
&& num
< 1200 + 32)
3047 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3052 return tdep
->ppc_cr_regnum
;
3054 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3056 return tdep
->ppc_acc_regnum
;
3058 return tdep
->ppc_mq_regnum
;
3060 return tdep
->ppc_xer_regnum
;
3062 return tdep
->ppc_lr_regnum
;
3064 return tdep
->ppc_ctr_regnum
;
3066 return tdep
->ppc_vrsave_regnum
;
3068 return tdep
->ppc_spefscr_regnum
;
3074 /* Translate a .eh_frame register to DWARF register, or adjust a
3075 .debug_frame register. */
3078 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3080 /* GCC releases before 3.4 use GCC internal register numbering in
3081 .debug_frame (and .debug_info, et cetera). The numbering is
3082 different from the standard SysV numbering for everything except
3083 for GPRs and FPRs. We can not detect this problem in most cases
3084 - to get accurate debug info for variables living in lr, ctr, v0,
3085 et cetera, use a newer version of GCC. But we must detect
3086 one important case - lr is in column 65 in .debug_frame output,
3089 GCC 3.4, and the "hammer" branch, have a related problem. They
3090 record lr register saves in .debug_frame as 108, but still record
3091 the return column as 65. We fix that up too.
3093 We can do this because 65 is assigned to fpsr, and GCC never
3094 generates debug info referring to it. To add support for
3095 handwritten debug info that restores fpsr, we would need to add a
3096 producer version check to this. */
3105 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3106 internal register numbering; translate that to the standard DWARF2
3107 register numbering. */
3108 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3110 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3111 return num
- 68 + 86;
3112 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3113 return num
- 77 + 1124;
3125 case 109: /* vrsave */
3127 case 110: /* vscr */
3129 case 111: /* spe_acc */
3131 case 112: /* spefscr */
3139 /* Handling the various POWER/PowerPC variants. */
3141 /* Information about a particular processor variant. */
3145 /* Name of this variant. */
3148 /* English description of the variant. */
3151 /* bfd_arch_info.arch corresponding to variant. */
3152 enum bfd_architecture arch
;
3154 /* bfd_arch_info.mach corresponding to variant. */
3157 /* Target description for this variant. */
3158 struct target_desc
**tdesc
;
3161 static struct variant variants
[] =
3163 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3164 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3165 {"power", "POWER user-level", bfd_arch_rs6000
,
3166 bfd_mach_rs6k
, &tdesc_rs6000
},
3167 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3168 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3169 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3170 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3171 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3172 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3173 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3174 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3175 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3176 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3177 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3178 604, &tdesc_powerpc_604
},
3179 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3180 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3181 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3182 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3183 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3184 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3185 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3186 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3187 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3188 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3189 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3190 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3193 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3194 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3195 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3196 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3197 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3198 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3199 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3200 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3201 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3202 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3203 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3204 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3206 /* FIXME: I haven't checked the register sets of the following. */
3207 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3208 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3209 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3210 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3211 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3212 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3214 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3217 /* Return the variant corresponding to architecture ARCH and machine number
3218 MACH. If no such variant exists, return null. */
3220 static const struct variant
*
3221 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3223 const struct variant
*v
;
3225 for (v
= variants
; v
->name
; v
++)
3226 if (arch
== v
->arch
&& mach
== v
->mach
)
3233 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3235 if (info
->endian
== BFD_ENDIAN_BIG
)
3236 return print_insn_big_powerpc (memaddr
, info
);
3238 return print_insn_little_powerpc (memaddr
, info
);
3242 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3244 return frame_unwind_register_unsigned (next_frame
,
3245 gdbarch_pc_regnum (gdbarch
));
3248 static struct frame_id
3249 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3251 return frame_id_build (get_frame_register_unsigned
3252 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3253 get_frame_pc (this_frame
));
3256 struct rs6000_frame_cache
3259 CORE_ADDR initial_sp
;
3260 struct trad_frame_saved_reg
*saved_regs
;
3262 /* Set BASE_P to true if this frame cache is properly initialized.
3263 Otherwise set to false because some registers or memory cannot
3266 /* Cache PC for building unavailable frame. */
3270 static struct rs6000_frame_cache
*
3271 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3273 struct rs6000_frame_cache
*cache
;
3274 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3275 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3276 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3277 struct rs6000_framedata fdata
;
3278 int wordsize
= tdep
->wordsize
;
3279 CORE_ADDR func
= 0, pc
= 0;
3281 if ((*this_cache
) != NULL
)
3282 return (struct rs6000_frame_cache
*) (*this_cache
);
3283 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3284 (*this_cache
) = cache
;
3286 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3290 func
= get_frame_func (this_frame
);
3292 pc
= get_frame_pc (this_frame
);
3293 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3295 /* Figure out the parent's stack pointer. */
3297 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3298 address of the current frame. Things might be easier if the
3299 ->frame pointed to the outer-most address of the frame. In
3300 the mean time, the address of the prev frame is used as the
3301 base address of this frame. */
3302 cache
->base
= get_frame_register_unsigned
3303 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3305 CATCH (ex
, RETURN_MASK_ERROR
)
3307 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3308 throw_exception (ex
);
3309 return (struct rs6000_frame_cache
*) (*this_cache
);
3313 /* If the function appears to be frameless, check a couple of likely
3314 indicators that we have simply failed to find the frame setup.
3315 Two common cases of this are missing symbols (i.e.
3316 get_frame_func returns the wrong address or 0), and assembly
3317 stubs which have a fast exit path but set up a frame on the slow
3320 If the LR appears to return to this function, then presume that
3321 we have an ABI compliant frame that we failed to find. */
3322 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3327 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3328 if (func
== 0 && saved_lr
== pc
)
3332 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3333 if (func
== saved_func
)
3339 fdata
.frameless
= 0;
3340 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3344 if (!fdata
.frameless
)
3346 /* Frameless really means stackless. */
3349 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3350 byte_order
, &backchain
))
3351 cache
->base
= (CORE_ADDR
) backchain
;
3354 trad_frame_set_value (cache
->saved_regs
,
3355 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3357 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3358 All fpr's from saved_fpr to fp31 are saved. */
3360 if (fdata
.saved_fpr
>= 0)
3363 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3365 /* If skip_prologue says floating-point registers were saved,
3366 but the current architecture has no floating-point registers,
3367 then that's strange. But we have no indices to even record
3368 the addresses under, so we just ignore it. */
3369 if (ppc_floating_point_unit_p (gdbarch
))
3370 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3372 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3377 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3378 All gpr's from saved_gpr to gpr31 are saved (except during the
3381 if (fdata
.saved_gpr
>= 0)
3384 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3385 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3387 if (fdata
.gpr_mask
& (1U << i
))
3388 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3389 gpr_addr
+= wordsize
;
3393 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3394 All vr's from saved_vr to vr31 are saved. */
3395 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3397 if (fdata
.saved_vr
>= 0)
3400 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3401 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3403 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3404 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3409 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3410 All vr's from saved_ev to ev31 are saved. ????? */
3411 if (tdep
->ppc_ev0_regnum
!= -1)
3413 if (fdata
.saved_ev
>= 0)
3416 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3417 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3419 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3421 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3422 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3423 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3428 /* If != 0, fdata.cr_offset is the offset from the frame that
3430 if (fdata
.cr_offset
!= 0)
3431 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3432 = cache
->base
+ fdata
.cr_offset
;
3434 /* If != 0, fdata.lr_offset is the offset from the frame that
3436 if (fdata
.lr_offset
!= 0)
3437 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3438 = cache
->base
+ fdata
.lr_offset
;
3439 else if (fdata
.lr_register
!= -1)
3440 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3441 /* The PC is found in the link register. */
3442 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3443 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3445 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3446 holds the VRSAVE. */
3447 if (fdata
.vrsave_offset
!= 0)
3448 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3449 = cache
->base
+ fdata
.vrsave_offset
;
3451 if (fdata
.alloca_reg
< 0)
3452 /* If no alloca register used, then fi->frame is the value of the
3453 %sp for this frame, and it is good enough. */
3455 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3458 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3465 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3466 struct frame_id
*this_id
)
3468 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3473 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3477 /* This marks the outermost frame. */
3478 if (info
->base
== 0)
3481 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3484 static struct value
*
3485 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3486 void **this_cache
, int regnum
)
3488 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3490 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3493 static const struct frame_unwind rs6000_frame_unwind
=
3496 default_frame_unwind_stop_reason
,
3497 rs6000_frame_this_id
,
3498 rs6000_frame_prev_register
,
3500 default_frame_sniffer
3503 /* Allocate and initialize a frame cache for an epilogue frame.
3504 SP is restored and prev-PC is stored in LR. */
3506 static struct rs6000_frame_cache
*
3507 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3509 struct rs6000_frame_cache
*cache
;
3510 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3511 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3514 return (struct rs6000_frame_cache
*) *this_cache
;
3516 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3517 (*this_cache
) = cache
;
3518 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3522 /* At this point the stack looks as if we just entered the
3523 function, and the return address is stored in LR. */
3526 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3527 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3530 cache
->initial_sp
= sp
;
3532 trad_frame_set_value (cache
->saved_regs
,
3533 gdbarch_pc_regnum (gdbarch
), lr
);
3535 CATCH (ex
, RETURN_MASK_ERROR
)
3537 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3538 throw_exception (ex
);
3545 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3546 Return the frame ID of an epilogue frame. */
3549 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3550 void **this_cache
, struct frame_id
*this_id
)
3553 struct rs6000_frame_cache
*info
=
3554 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3556 pc
= get_frame_func (this_frame
);
3557 if (info
->base
== 0)
3558 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3560 (*this_id
) = frame_id_build (info
->base
, pc
);
3563 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3564 Return the register value of REGNUM in previous frame. */
3566 static struct value
*
3567 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3568 void **this_cache
, int regnum
)
3570 struct rs6000_frame_cache
*info
=
3571 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3572 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3575 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3576 Check whether this an epilogue frame. */
3579 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3580 struct frame_info
*this_frame
,
3581 void **this_prologue_cache
)
3583 if (frame_relative_level (this_frame
) == 0)
3584 return rs6000_in_function_epilogue_frame_p (this_frame
,
3585 get_frame_arch (this_frame
),
3586 get_frame_pc (this_frame
));
3591 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3592 a function without debug information. */
3594 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3597 default_frame_unwind_stop_reason
,
3598 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3600 rs6000_epilogue_frame_sniffer
3605 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3607 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3609 return info
->initial_sp
;
3612 static const struct frame_base rs6000_frame_base
= {
3613 &rs6000_frame_unwind
,
3614 rs6000_frame_base_address
,
3615 rs6000_frame_base_address
,
3616 rs6000_frame_base_address
3619 static const struct frame_base
*
3620 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3622 return &rs6000_frame_base
;
3625 /* DWARF-2 frame support. Used to handle the detection of
3626 clobbered registers during function calls. */
3629 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3630 struct dwarf2_frame_state_reg
*reg
,
3631 struct frame_info
*this_frame
)
3633 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3635 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3636 non-volatile registers. We will use the same code for both. */
3638 /* Call-saved GP registers. */
3639 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3640 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3641 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3642 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3644 /* Call-clobbered GP registers. */
3645 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3646 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3647 || (regnum
== tdep
->ppc_gp0_regnum
))
3648 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3650 /* Deal with FP registers, if supported. */
3651 if (tdep
->ppc_fp0_regnum
>= 0)
3653 /* Call-saved FP registers. */
3654 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3655 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3656 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3658 /* Call-clobbered FP registers. */
3659 if ((regnum
>= tdep
->ppc_fp0_regnum
3660 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3661 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3664 /* Deal with ALTIVEC registers, if supported. */
3665 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3667 /* Call-saved Altivec registers. */
3668 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3669 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3670 || regnum
== tdep
->ppc_vrsave_regnum
)
3671 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3673 /* Call-clobbered Altivec registers. */
3674 if ((regnum
>= tdep
->ppc_vr0_regnum
3675 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3676 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3679 /* Handle PC register and Stack Pointer correctly. */
3680 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3681 reg
->how
= DWARF2_FRAME_REG_RA
;
3682 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3683 reg
->how
= DWARF2_FRAME_REG_CFA
;
3687 /* Return true if a .gnu_attributes section exists in BFD and it
3688 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3689 section exists in BFD and it indicates that SPE extensions are in
3690 use. Check the .gnu.attributes section first, as the binary might be
3691 compiled for SPE, but not actually using SPE instructions. */
3694 bfd_uses_spe_extensions (bfd
*abfd
)
3697 gdb_byte
*contents
= NULL
;
3707 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3708 could be using the SPE vector abi without actually using any spe
3709 bits whatsoever. But it's close enough for now. */
3710 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3711 Tag_GNU_Power_ABI_Vector
);
3712 if (vector_abi
== 3)
3716 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3720 size
= bfd_get_section_size (sect
);
3721 contents
= (gdb_byte
*) xmalloc (size
);
3722 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3728 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3734 char name[name_len rounded up to 4-byte alignment];
3735 char data[data_len];
3738 Technically, there's only supposed to be one such structure in a
3739 given apuinfo section, but the linker is not always vigilant about
3740 merging apuinfo sections from input files. Just go ahead and parse
3741 them all, exiting early when we discover the binary uses SPE
3744 It's not specified in what endianness the information in this
3745 section is stored. Assume that it's the endianness of the BFD. */
3749 unsigned int name_len
;
3750 unsigned int data_len
;
3753 /* If we can't read the first three fields, we're done. */
3757 name_len
= bfd_get_32 (abfd
, ptr
);
3758 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3759 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3760 type
= bfd_get_32 (abfd
, ptr
+ 8);
3763 /* The name must be "APUinfo\0". */
3765 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3769 /* The type must be 2. */
3773 /* The data is stored as a series of uint32. The upper half of
3774 each uint32 indicates the particular APU used and the lower
3775 half indicates the revision of that APU. We just care about
3778 /* Not 4-byte quantities. */
3784 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3785 unsigned int apu
= apuinfo
>> 16;
3789 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3791 if (apu
== 0x100 || apu
== 0x101)
3806 /* These are macros for parsing instruction fields (I.1.6.28) */
3808 #define PPC_FIELD(value, from, len) \
3809 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3810 #define PPC_SEXT(v, bs) \
3811 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3812 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3813 - ((CORE_ADDR) 1 << ((bs) - 1)))
3814 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3815 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3816 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3817 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3818 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3819 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3820 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3821 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3822 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3823 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3824 | (PPC_FIELD (insn, 16, 5) << 5))
3825 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3826 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3827 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3828 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3829 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3830 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3831 #define PPC_OE(insn) PPC_BIT (insn, 21)
3832 #define PPC_RC(insn) PPC_BIT (insn, 31)
3833 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3834 #define PPC_LK(insn) PPC_BIT (insn, 31)
3835 #define PPC_TX(insn) PPC_BIT (insn, 31)
3836 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3838 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3839 #define PPC_XER_NB(xer) (xer & 0x7f)
3841 /* Record Vector-Scalar Registers.
3842 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3843 Otherwise, it's just a VR register. Record them accordingly. */
3846 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3848 if (vsr
< 0 || vsr
>= 64)
3853 if (tdep
->ppc_vr0_regnum
>= 0)
3854 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3858 if (tdep
->ppc_fp0_regnum
>= 0)
3859 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3860 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3861 record_full_arch_list_add_reg (regcache
,
3862 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3868 /* Parse and record instructions primary opcode-4 at ADDR.
3869 Return 0 if successful. */
3872 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3873 CORE_ADDR addr
, uint32_t insn
)
3875 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3876 int ext
= PPC_FIELD (insn
, 21, 11);
3877 int vra
= PPC_FIELD (insn
, 11, 5);
3881 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3882 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3883 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3884 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3885 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3887 case 42: /* Vector Select */
3888 case 43: /* Vector Permute */
3889 case 59: /* Vector Permute Right-indexed */
3890 case 44: /* Vector Shift Left Double by Octet Immediate */
3891 case 45: /* Vector Permute and Exclusive-OR */
3892 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3893 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3894 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3895 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3896 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3897 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3898 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3899 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3900 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3901 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3902 case 46: /* Vector Multiply-Add Single-Precision */
3903 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3904 record_full_arch_list_add_reg (regcache
,
3905 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3908 case 48: /* Multiply-Add High Doubleword */
3909 case 49: /* Multiply-Add High Doubleword Unsigned */
3910 case 51: /* Multiply-Add Low Doubleword */
3911 record_full_arch_list_add_reg (regcache
,
3912 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3916 switch ((ext
& 0x1ff))
3919 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
3920 && vra
!= 2 /* Decimal Convert From Signed Quadword */
3921 && vra
!= 4 /* Decimal Convert To Zoned */
3922 && vra
!= 5 /* Decimal Convert To National */
3923 && vra
!= 6 /* Decimal Convert From Zoned */
3924 && vra
!= 7 /* Decimal Convert From National */
3925 && vra
!= 31) /* Decimal Set Sign */
3927 /* 5.16 Decimal Integer Arithmetic Instructions */
3928 case 1: /* Decimal Add Modulo */
3929 case 65: /* Decimal Subtract Modulo */
3931 case 193: /* Decimal Shift */
3932 case 129: /* Decimal Unsigned Shift */
3933 case 449: /* Decimal Shift and Round */
3935 case 257: /* Decimal Truncate */
3936 case 321: /* Decimal Unsigned Truncate */
3938 /* Bit-21 should be set. */
3939 if (!PPC_BIT (insn
, 21))
3942 record_full_arch_list_add_reg (regcache
,
3943 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3944 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3948 /* Bit-21 is used for RC */
3949 switch (ext
& 0x3ff)
3951 case 6: /* Vector Compare Equal To Unsigned Byte */
3952 case 70: /* Vector Compare Equal To Unsigned Halfword */
3953 case 134: /* Vector Compare Equal To Unsigned Word */
3954 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3955 case 774: /* Vector Compare Greater Than Signed Byte */
3956 case 838: /* Vector Compare Greater Than Signed Halfword */
3957 case 902: /* Vector Compare Greater Than Signed Word */
3958 case 967: /* Vector Compare Greater Than Signed Doubleword */
3959 case 518: /* Vector Compare Greater Than Unsigned Byte */
3960 case 646: /* Vector Compare Greater Than Unsigned Word */
3961 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3962 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3963 case 966: /* Vector Compare Bounds Single-Precision */
3964 case 198: /* Vector Compare Equal To Single-Precision */
3965 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3966 case 710: /* Vector Compare Greater Than Single-Precision */
3967 case 7: /* Vector Compare Not Equal Byte */
3968 case 71: /* Vector Compare Not Equal Halfword */
3969 case 135: /* Vector Compare Not Equal Word */
3970 case 263: /* Vector Compare Not Equal or Zero Byte */
3971 case 327: /* Vector Compare Not Equal or Zero Halfword */
3972 case 391: /* Vector Compare Not Equal or Zero Word */
3974 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
3975 record_full_arch_list_add_reg (regcache
,
3976 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3984 case 0: /* Vector Count Leading Zero Least-Significant Bits
3986 case 1: /* Vector Count Trailing Zero Least-Significant Bits
3988 record_full_arch_list_add_reg (regcache
,
3989 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3992 case 6: /* Vector Negate Word */
3993 case 7: /* Vector Negate Doubleword */
3994 case 8: /* Vector Parity Byte Word */
3995 case 9: /* Vector Parity Byte Doubleword */
3996 case 10: /* Vector Parity Byte Quadword */
3997 case 16: /* Vector Extend Sign Byte To Word */
3998 case 17: /* Vector Extend Sign Halfword To Word */
3999 case 24: /* Vector Extend Sign Byte To Doubleword */
4000 case 25: /* Vector Extend Sign Halfword To Doubleword */
4001 case 26: /* Vector Extend Sign Word To Doubleword */
4002 case 28: /* Vector Count Trailing Zeros Byte */
4003 case 29: /* Vector Count Trailing Zeros Halfword */
4004 case 30: /* Vector Count Trailing Zeros Word */
4005 case 31: /* Vector Count Trailing Zeros Doubleword */
4006 record_full_arch_list_add_reg (regcache
,
4007 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4014 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4015 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4016 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4017 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4018 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4019 case 462: /* Vector Pack Signed Word Signed Saturate */
4020 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4021 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4022 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4023 case 512: /* Vector Add Unsigned Byte Saturate */
4024 case 576: /* Vector Add Unsigned Halfword Saturate */
4025 case 640: /* Vector Add Unsigned Word Saturate */
4026 case 768: /* Vector Add Signed Byte Saturate */
4027 case 832: /* Vector Add Signed Halfword Saturate */
4028 case 896: /* Vector Add Signed Word Saturate */
4029 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4030 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4031 case 1664: /* Vector Subtract Unsigned Word Saturate */
4032 case 1792: /* Vector Subtract Signed Byte Saturate */
4033 case 1856: /* Vector Subtract Signed Halfword Saturate */
4034 case 1920: /* Vector Subtract Signed Word Saturate */
4036 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4037 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4038 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4039 case 1672: /* Vector Sum across Half Signed Word Saturate */
4040 case 1928: /* Vector Sum across Signed Word Saturate */
4041 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4042 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4043 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4045 case 12: /* Vector Merge High Byte */
4046 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4047 case 76: /* Vector Merge High Halfword */
4048 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4049 case 140: /* Vector Merge High Word */
4050 case 268: /* Vector Merge Low Byte */
4051 case 332: /* Vector Merge Low Halfword */
4052 case 396: /* Vector Merge Low Word */
4053 case 526: /* Vector Unpack High Signed Byte */
4054 case 590: /* Vector Unpack High Signed Halfword */
4055 case 654: /* Vector Unpack Low Signed Byte */
4056 case 718: /* Vector Unpack Low Signed Halfword */
4057 case 782: /* Vector Pack Pixel */
4058 case 846: /* Vector Unpack High Pixel */
4059 case 974: /* Vector Unpack Low Pixel */
4060 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4061 case 1614: /* Vector Unpack High Signed Word */
4062 case 1676: /* Vector Merge Odd Word */
4063 case 1742: /* Vector Unpack Low Signed Word */
4064 case 1932: /* Vector Merge Even Word */
4065 case 524: /* Vector Splat Byte */
4066 case 588: /* Vector Splat Halfword */
4067 case 652: /* Vector Splat Word */
4068 case 780: /* Vector Splat Immediate Signed Byte */
4069 case 844: /* Vector Splat Immediate Signed Halfword */
4070 case 908: /* Vector Splat Immediate Signed Word */
4071 case 452: /* Vector Shift Left */
4072 case 708: /* Vector Shift Right */
4073 case 1036: /* Vector Shift Left by Octet */
4074 case 1100: /* Vector Shift Right by Octet */
4075 case 0: /* Vector Add Unsigned Byte Modulo */
4076 case 64: /* Vector Add Unsigned Halfword Modulo */
4077 case 128: /* Vector Add Unsigned Word Modulo */
4078 case 192: /* Vector Add Unsigned Doubleword Modulo */
4079 case 256: /* Vector Add Unsigned Quadword Modulo */
4080 case 320: /* Vector Add & write Carry Unsigned Quadword */
4081 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4082 case 8: /* Vector Multiply Odd Unsigned Byte */
4083 case 72: /* Vector Multiply Odd Unsigned Halfword */
4084 case 136: /* Vector Multiply Odd Unsigned Word */
4085 case 264: /* Vector Multiply Odd Signed Byte */
4086 case 328: /* Vector Multiply Odd Signed Halfword */
4087 case 392: /* Vector Multiply Odd Signed Word */
4088 case 520: /* Vector Multiply Even Unsigned Byte */
4089 case 584: /* Vector Multiply Even Unsigned Halfword */
4090 case 648: /* Vector Multiply Even Unsigned Word */
4091 case 776: /* Vector Multiply Even Signed Byte */
4092 case 840: /* Vector Multiply Even Signed Halfword */
4093 case 904: /* Vector Multiply Even Signed Word */
4094 case 137: /* Vector Multiply Unsigned Word Modulo */
4095 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4096 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4097 case 1152: /* Vector Subtract Unsigned Word Modulo */
4098 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4099 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4100 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4101 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4102 case 1282: /* Vector Average Signed Byte */
4103 case 1346: /* Vector Average Signed Halfword */
4104 case 1410: /* Vector Average Signed Word */
4105 case 1026: /* Vector Average Unsigned Byte */
4106 case 1090: /* Vector Average Unsigned Halfword */
4107 case 1154: /* Vector Average Unsigned Word */
4108 case 258: /* Vector Maximum Signed Byte */
4109 case 322: /* Vector Maximum Signed Halfword */
4110 case 386: /* Vector Maximum Signed Word */
4111 case 450: /* Vector Maximum Signed Doubleword */
4112 case 2: /* Vector Maximum Unsigned Byte */
4113 case 66: /* Vector Maximum Unsigned Halfword */
4114 case 130: /* Vector Maximum Unsigned Word */
4115 case 194: /* Vector Maximum Unsigned Doubleword */
4116 case 770: /* Vector Minimum Signed Byte */
4117 case 834: /* Vector Minimum Signed Halfword */
4118 case 898: /* Vector Minimum Signed Word */
4119 case 962: /* Vector Minimum Signed Doubleword */
4120 case 514: /* Vector Minimum Unsigned Byte */
4121 case 578: /* Vector Minimum Unsigned Halfword */
4122 case 642: /* Vector Minimum Unsigned Word */
4123 case 706: /* Vector Minimum Unsigned Doubleword */
4124 case 1028: /* Vector Logical AND */
4125 case 1668: /* Vector Logical Equivalent */
4126 case 1092: /* Vector Logical AND with Complement */
4127 case 1412: /* Vector Logical NAND */
4128 case 1348: /* Vector Logical OR with Complement */
4129 case 1156: /* Vector Logical OR */
4130 case 1284: /* Vector Logical NOR */
4131 case 1220: /* Vector Logical XOR */
4132 case 4: /* Vector Rotate Left Byte */
4133 case 132: /* Vector Rotate Left Word VX-form */
4134 case 68: /* Vector Rotate Left Halfword */
4135 case 196: /* Vector Rotate Left Doubleword */
4136 case 260: /* Vector Shift Left Byte */
4137 case 388: /* Vector Shift Left Word */
4138 case 324: /* Vector Shift Left Halfword */
4139 case 1476: /* Vector Shift Left Doubleword */
4140 case 516: /* Vector Shift Right Byte */
4141 case 644: /* Vector Shift Right Word */
4142 case 580: /* Vector Shift Right Halfword */
4143 case 1732: /* Vector Shift Right Doubleword */
4144 case 772: /* Vector Shift Right Algebraic Byte */
4145 case 900: /* Vector Shift Right Algebraic Word */
4146 case 836: /* Vector Shift Right Algebraic Halfword */
4147 case 964: /* Vector Shift Right Algebraic Doubleword */
4148 case 10: /* Vector Add Single-Precision */
4149 case 74: /* Vector Subtract Single-Precision */
4150 case 1034: /* Vector Maximum Single-Precision */
4151 case 1098: /* Vector Minimum Single-Precision */
4152 case 842: /* Vector Convert From Signed Fixed-Point Word */
4153 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4154 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4155 case 522: /* Vector Round to Single-Precision Integer Nearest */
4156 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4157 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4158 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4159 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4160 case 266: /* Vector Reciprocal Estimate Single-Precision */
4161 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4162 case 1288: /* Vector AES Cipher */
4163 case 1289: /* Vector AES Cipher Last */
4164 case 1352: /* Vector AES Inverse Cipher */
4165 case 1353: /* Vector AES Inverse Cipher Last */
4166 case 1480: /* Vector AES SubBytes */
4167 case 1730: /* Vector SHA-512 Sigma Doubleword */
4168 case 1666: /* Vector SHA-256 Sigma Word */
4169 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4170 case 1160: /* Vector Polynomial Multiply-Sum Word */
4171 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4172 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4173 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4174 case 1794: /* Vector Count Leading Zeros Byte */
4175 case 1858: /* Vector Count Leading Zeros Halfword */
4176 case 1922: /* Vector Count Leading Zeros Word */
4177 case 1986: /* Vector Count Leading Zeros Doubleword */
4178 case 1795: /* Vector Population Count Byte */
4179 case 1859: /* Vector Population Count Halfword */
4180 case 1923: /* Vector Population Count Word */
4181 case 1987: /* Vector Population Count Doubleword */
4182 case 1356: /* Vector Bit Permute Quadword */
4183 case 1484: /* Vector Bit Permute Doubleword */
4184 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4185 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4187 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4188 case 65: /* Vector Multiply-by-10 Extended & write Carry
4189 Unsigned Quadword */
4190 case 1027: /* Vector Absolute Difference Unsigned Byte */
4191 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4192 case 1155: /* Vector Absolute Difference Unsigned Word */
4193 case 1796: /* Vector Shift Right Variable */
4194 case 1860: /* Vector Shift Left Variable */
4195 case 133: /* Vector Rotate Left Word then Mask Insert */
4196 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4197 case 389: /* Vector Rotate Left Word then AND with Mask */
4198 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4199 case 525: /* Vector Extract Unsigned Byte */
4200 case 589: /* Vector Extract Unsigned Halfword */
4201 case 653: /* Vector Extract Unsigned Word */
4202 case 717: /* Vector Extract Doubleword */
4203 case 781: /* Vector Insert Byte */
4204 case 845: /* Vector Insert Halfword */
4205 case 909: /* Vector Insert Word */
4206 case 973: /* Vector Insert Doubleword */
4207 record_full_arch_list_add_reg (regcache
,
4208 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4211 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4212 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4213 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4214 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4215 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4216 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4217 record_full_arch_list_add_reg (regcache
,
4218 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4221 case 1604: /* Move To Vector Status and Control Register */
4222 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4224 case 1540: /* Move From Vector Status and Control Register */
4225 record_full_arch_list_add_reg (regcache
,
4226 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4228 case 833: /* Decimal Copy Sign */
4229 record_full_arch_list_add_reg (regcache
,
4230 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4231 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4235 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4236 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4240 /* Parse and record instructions of primary opcode-19 at ADDR.
4241 Return 0 if successful. */
4244 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4245 CORE_ADDR addr
, uint32_t insn
)
4247 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4248 int ext
= PPC_EXTOP (insn
);
4250 switch (ext
& 0x01f)
4252 case 2: /* Add PC Immediate Shifted */
4253 record_full_arch_list_add_reg (regcache
,
4254 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4260 case 0: /* Move Condition Register Field */
4261 case 33: /* Condition Register NOR */
4262 case 129: /* Condition Register AND with Complement */
4263 case 193: /* Condition Register XOR */
4264 case 225: /* Condition Register NAND */
4265 case 257: /* Condition Register AND */
4266 case 289: /* Condition Register Equivalent */
4267 case 417: /* Condition Register OR with Complement */
4268 case 449: /* Condition Register OR */
4269 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4272 case 16: /* Branch Conditional */
4273 case 560: /* Branch Conditional to Branch Target Address Register */
4274 if ((PPC_BO (insn
) & 0x4) == 0)
4275 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4277 case 528: /* Branch Conditional to Count Register */
4279 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4282 case 150: /* Instruction Synchronize */
4287 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4288 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4292 /* Parse and record instructions of primary opcode-31 at ADDR.
4293 Return 0 if successful. */
4296 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4297 CORE_ADDR addr
, uint32_t insn
)
4299 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4300 int ext
= PPC_EXTOP (insn
);
4302 CORE_ADDR at_dcsz
, ea
= 0;
4303 ULONGEST rb
, ra
, xer
;
4306 /* These instructions have OE bit. */
4307 switch (ext
& 0x1ff)
4309 /* These write RT and XER. Update CR if RC is set. */
4310 case 8: /* Subtract from carrying */
4311 case 10: /* Add carrying */
4312 case 136: /* Subtract from extended */
4313 case 138: /* Add extended */
4314 case 200: /* Subtract from zero extended */
4315 case 202: /* Add to zero extended */
4316 case 232: /* Subtract from minus one extended */
4317 case 234: /* Add to minus one extended */
4318 /* CA is always altered, but SO/OV are only altered when OE=1.
4319 In any case, XER is always altered. */
4320 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4322 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4323 record_full_arch_list_add_reg (regcache
,
4324 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4327 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4328 case 40: /* Subtract from */
4329 case 104: /* Negate */
4330 case 233: /* Multiply low doubleword */
4331 case 235: /* Multiply low word */
4333 case 393: /* Divide Doubleword Extended Unsigned */
4334 case 395: /* Divide Word Extended Unsigned */
4335 case 425: /* Divide Doubleword Extended */
4336 case 427: /* Divide Word Extended */
4337 case 457: /* Divide Doubleword Unsigned */
4338 case 459: /* Divide Word Unsigned */
4339 case 489: /* Divide Doubleword */
4340 case 491: /* Divide Word */
4342 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4344 case 9: /* Multiply High Doubleword Unsigned */
4345 case 11: /* Multiply High Word Unsigned */
4346 case 73: /* Multiply High Doubleword */
4347 case 75: /* Multiply High Word */
4349 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4350 record_full_arch_list_add_reg (regcache
,
4351 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4355 if ((ext
& 0x1f) == 15)
4357 /* Integer Select. bit[16:20] is used for BC. */
4358 record_full_arch_list_add_reg (regcache
,
4359 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4363 if ((ext
& 0xff) == 170)
4365 /* Add Extended using alternate carry bits */
4366 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4367 record_full_arch_list_add_reg (regcache
,
4368 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4374 case 78: /* Determine Leftmost Zero Byte */
4376 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4377 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4378 record_full_arch_list_add_reg (regcache
,
4379 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4382 /* These only write RT. */
4383 case 19: /* Move from condition register */
4384 /* Move From One Condition Register Field */
4385 case 74: /* Add and Generate Sixes */
4386 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4387 case 302: /* Move From Branch History Rolling Buffer */
4388 case 339: /* Move From Special Purpose Register */
4389 case 371: /* Move From Time Base [Phased-Out] */
4390 case 309: /* Load Doubleword Monitored Indexed */
4391 case 128: /* Set Boolean */
4392 case 755: /* Deliver A Random Number */
4393 record_full_arch_list_add_reg (regcache
,
4394 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4397 /* These only write to RA. */
4398 case 51: /* Move From VSR Doubleword */
4399 case 115: /* Move From VSR Word and Zero */
4400 case 122: /* Population count bytes */
4401 case 378: /* Population count words */
4402 case 506: /* Population count doublewords */
4403 case 154: /* Parity Word */
4404 case 186: /* Parity Doubleword */
4405 case 252: /* Bit Permute Doubleword */
4406 case 282: /* Convert Declets To Binary Coded Decimal */
4407 case 314: /* Convert Binary Coded Decimal To Declets */
4408 case 508: /* Compare bytes */
4409 case 307: /* Move From VSR Lower Doubleword */
4410 record_full_arch_list_add_reg (regcache
,
4411 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4414 /* These write CR and optional RA. */
4415 case 792: /* Shift Right Algebraic Word */
4416 case 794: /* Shift Right Algebraic Doubleword */
4417 case 824: /* Shift Right Algebraic Word Immediate */
4418 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4419 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4420 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4421 record_full_arch_list_add_reg (regcache
,
4422 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4424 case 0: /* Compare */
4425 case 32: /* Compare logical */
4426 case 144: /* Move To Condition Register Fields */
4427 /* Move To One Condition Register Field */
4428 case 192: /* Compare Ranged Byte */
4429 case 224: /* Compare Equal Byte */
4430 case 576: /* Move XER to CR Extended */
4431 case 902: /* Paste (should always fail due to single-stepping and
4432 the memory location might not be accessible, so
4434 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4437 /* These write to RT. Update RA if 'update indexed.' */
4438 case 53: /* Load Doubleword with Update Indexed */
4439 case 119: /* Load Byte and Zero with Update Indexed */
4440 case 311: /* Load Halfword and Zero with Update Indexed */
4441 case 55: /* Load Word and Zero with Update Indexed */
4442 case 375: /* Load Halfword Algebraic with Update Indexed */
4443 case 373: /* Load Word Algebraic with Update Indexed */
4444 record_full_arch_list_add_reg (regcache
,
4445 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4447 case 21: /* Load Doubleword Indexed */
4448 case 52: /* Load Byte And Reserve Indexed */
4449 case 116: /* Load Halfword And Reserve Indexed */
4450 case 20: /* Load Word And Reserve Indexed */
4451 case 84: /* Load Doubleword And Reserve Indexed */
4452 case 87: /* Load Byte and Zero Indexed */
4453 case 279: /* Load Halfword and Zero Indexed */
4454 case 23: /* Load Word and Zero Indexed */
4455 case 343: /* Load Halfword Algebraic Indexed */
4456 case 341: /* Load Word Algebraic Indexed */
4457 case 790: /* Load Halfword Byte-Reverse Indexed */
4458 case 534: /* Load Word Byte-Reverse Indexed */
4459 case 532: /* Load Doubleword Byte-Reverse Indexed */
4460 case 582: /* Load Word Atomic */
4461 case 614: /* Load Doubleword Atomic */
4462 case 265: /* Modulo Unsigned Doubleword */
4463 case 777: /* Modulo Signed Doubleword */
4464 case 267: /* Modulo Unsigned Word */
4465 case 779: /* Modulo Signed Word */
4466 record_full_arch_list_add_reg (regcache
,
4467 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4470 case 597: /* Load String Word Immediate */
4471 case 533: /* Load String Word Indexed */
4480 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4481 nr
= PPC_XER_NB (xer
);
4486 /* If n=0, the contents of register RT are undefined. */
4490 for (i
= 0; i
< nr
; i
++)
4491 record_full_arch_list_add_reg (regcache
,
4492 tdep
->ppc_gp0_regnum
4493 + ((PPC_RT (insn
) + i
) & 0x1f));
4496 case 276: /* Load Quadword And Reserve Indexed */
4497 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4498 record_full_arch_list_add_reg (regcache
, tmp
);
4499 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4502 /* These write VRT. */
4503 case 6: /* Load Vector for Shift Left Indexed */
4504 case 38: /* Load Vector for Shift Right Indexed */
4505 case 7: /* Load Vector Element Byte Indexed */
4506 case 39: /* Load Vector Element Halfword Indexed */
4507 case 71: /* Load Vector Element Word Indexed */
4508 case 103: /* Load Vector Indexed */
4509 case 359: /* Load Vector Indexed LRU */
4510 record_full_arch_list_add_reg (regcache
,
4511 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4514 /* These write FRT. Update RA if 'update indexed.' */
4515 case 567: /* Load Floating-Point Single with Update Indexed */
4516 case 631: /* Load Floating-Point Double with Update Indexed */
4517 record_full_arch_list_add_reg (regcache
,
4518 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4520 case 535: /* Load Floating-Point Single Indexed */
4521 case 599: /* Load Floating-Point Double Indexed */
4522 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4523 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4524 record_full_arch_list_add_reg (regcache
,
4525 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4528 case 791: /* Load Floating-Point Double Pair Indexed */
4529 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4530 record_full_arch_list_add_reg (regcache
, tmp
);
4531 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4534 case 179: /* Move To VSR Doubleword */
4535 case 211: /* Move To VSR Word Algebraic */
4536 case 243: /* Move To VSR Word and Zero */
4537 case 588: /* Load VSX Scalar Doubleword Indexed */
4538 case 524: /* Load VSX Scalar Single-Precision Indexed */
4539 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4540 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4541 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4542 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4543 case 780: /* Load VSX Vector Word*4 Indexed */
4544 case 268: /* Load VSX Vector Indexed */
4545 case 364: /* Load VSX Vector Word & Splat Indexed */
4546 case 812: /* Load VSX Vector Halfword*8 Indexed */
4547 case 876: /* Load VSX Vector Byte*16 Indexed */
4548 case 269: /* Load VSX Vector with Length */
4549 case 301: /* Load VSX Vector Left-justified with Length */
4550 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4551 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4552 case 403: /* Move To VSR Word & Splat */
4553 case 435: /* Move To VSR Double Doubleword */
4554 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4557 /* These write RA. Update CR if RC is set. */
4558 case 24: /* Shift Left Word */
4559 case 26: /* Count Leading Zeros Word */
4560 case 27: /* Shift Left Doubleword */
4562 case 58: /* Count Leading Zeros Doubleword */
4563 case 60: /* AND with Complement */
4565 case 284: /* Equivalent */
4567 case 476: /* NAND */
4568 case 412: /* OR with Complement */
4570 case 536: /* Shift Right Word */
4571 case 539: /* Shift Right Doubleword */
4572 case 922: /* Extend Sign Halfword */
4573 case 954: /* Extend Sign Byte */
4574 case 986: /* Extend Sign Word */
4575 case 538: /* Count Trailing Zeros Word */
4576 case 570: /* Count Trailing Zeros Doubleword */
4577 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4578 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4580 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4581 record_full_arch_list_add_reg (regcache
,
4582 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4586 case 181: /* Store Doubleword with Update Indexed */
4587 case 183: /* Store Word with Update Indexed */
4588 case 247: /* Store Byte with Update Indexed */
4589 case 439: /* Store Half Word with Update Indexed */
4590 case 695: /* Store Floating-Point Single with Update Indexed */
4591 case 759: /* Store Floating-Point Double with Update Indexed */
4592 record_full_arch_list_add_reg (regcache
,
4593 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4595 case 135: /* Store Vector Element Byte Indexed */
4596 case 167: /* Store Vector Element Halfword Indexed */
4597 case 199: /* Store Vector Element Word Indexed */
4598 case 231: /* Store Vector Indexed */
4599 case 487: /* Store Vector Indexed LRU */
4600 case 716: /* Store VSX Scalar Doubleword Indexed */
4601 case 140: /* Store VSX Scalar as Integer Word Indexed */
4602 case 652: /* Store VSX Scalar Single-Precision Indexed */
4603 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4604 case 908: /* Store VSX Vector Word*4 Indexed */
4605 case 149: /* Store Doubleword Indexed */
4606 case 151: /* Store Word Indexed */
4607 case 215: /* Store Byte Indexed */
4608 case 407: /* Store Half Word Indexed */
4609 case 694: /* Store Byte Conditional Indexed */
4610 case 726: /* Store Halfword Conditional Indexed */
4611 case 150: /* Store Word Conditional Indexed */
4612 case 214: /* Store Doubleword Conditional Indexed */
4613 case 182: /* Store Quadword Conditional Indexed */
4614 case 662: /* Store Word Byte-Reverse Indexed */
4615 case 918: /* Store Halfword Byte-Reverse Indexed */
4616 case 660: /* Store Doubleword Byte-Reverse Indexed */
4617 case 663: /* Store Floating-Point Single Indexed */
4618 case 727: /* Store Floating-Point Double Indexed */
4619 case 919: /* Store Floating-Point Double Pair Indexed */
4620 case 983: /* Store Floating-Point as Integer Word Indexed */
4621 case 396: /* Store VSX Vector Indexed */
4622 case 940: /* Store VSX Vector Halfword*8 Indexed */
4623 case 1004: /* Store VSX Vector Byte*16 Indexed */
4624 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4625 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4626 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4627 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4630 if (PPC_RA (insn
) != 0)
4631 regcache_raw_read_unsigned (regcache
,
4632 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4633 regcache_raw_read_unsigned (regcache
,
4634 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4639 case 183: /* Store Word with Update Indexed */
4640 case 199: /* Store Vector Element Word Indexed */
4641 case 140: /* Store VSX Scalar as Integer Word Indexed */
4642 case 652: /* Store VSX Scalar Single-Precision Indexed */
4643 case 151: /* Store Word Indexed */
4644 case 150: /* Store Word Conditional Indexed */
4645 case 662: /* Store Word Byte-Reverse Indexed */
4646 case 663: /* Store Floating-Point Single Indexed */
4647 case 695: /* Store Floating-Point Single with Update Indexed */
4648 case 983: /* Store Floating-Point as Integer Word Indexed */
4651 case 247: /* Store Byte with Update Indexed */
4652 case 135: /* Store Vector Element Byte Indexed */
4653 case 215: /* Store Byte Indexed */
4654 case 694: /* Store Byte Conditional Indexed */
4655 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4658 case 439: /* Store Halfword with Update Indexed */
4659 case 167: /* Store Vector Element Halfword Indexed */
4660 case 407: /* Store Halfword Indexed */
4661 case 726: /* Store Halfword Conditional Indexed */
4662 case 918: /* Store Halfword Byte-Reverse Indexed */
4663 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4666 case 181: /* Store Doubleword with Update Indexed */
4667 case 716: /* Store VSX Scalar Doubleword Indexed */
4668 case 149: /* Store Doubleword Indexed */
4669 case 214: /* Store Doubleword Conditional Indexed */
4670 case 660: /* Store Doubleword Byte-Reverse Indexed */
4671 case 727: /* Store Floating-Point Double Indexed */
4672 case 759: /* Store Floating-Point Double with Update Indexed */
4675 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4676 case 908: /* Store VSX Vector Word*4 Indexed */
4677 case 182: /* Store Quadword Conditional Indexed */
4678 case 231: /* Store Vector Indexed */
4679 case 487: /* Store Vector Indexed LRU */
4680 case 919: /* Store Floating-Point Double Pair Indexed */
4681 case 396: /* Store VSX Vector Indexed */
4682 case 940: /* Store VSX Vector Halfword*8 Indexed */
4683 case 1004: /* Store VSX Vector Byte*16 Indexed */
4690 /* Align address for Store Vector instructions. */
4693 case 167: /* Store Vector Element Halfword Indexed */
4694 addr
= addr
& ~0x1ULL
;
4697 case 199: /* Store Vector Element Word Indexed */
4698 addr
= addr
& ~0x3ULL
;
4701 case 231: /* Store Vector Indexed */
4702 case 487: /* Store Vector Indexed LRU */
4703 addr
= addr
& ~0xfULL
;
4707 record_full_arch_list_add_mem (addr
, size
);
4710 case 397: /* Store VSX Vector with Length */
4711 case 429: /* Store VSX Vector Left-justified with Length */
4713 if (PPC_RA (insn
) != 0)
4714 regcache_raw_read_unsigned (regcache
,
4715 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4717 regcache_raw_read_unsigned (regcache
,
4718 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4719 /* Store up to 16 bytes. */
4720 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4722 record_full_arch_list_add_mem (ea
, nb
);
4725 case 710: /* Store Word Atomic */
4726 case 742: /* Store Doubleword Atomic */
4728 if (PPC_RA (insn
) != 0)
4729 regcache_raw_read_unsigned (regcache
,
4730 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4734 case 710: /* Store Word Atomic */
4737 case 742: /* Store Doubleword Atomic */
4743 record_full_arch_list_add_mem (ea
, size
);
4746 case 725: /* Store String Word Immediate */
4748 if (PPC_RA (insn
) != 0)
4749 regcache_raw_read_unsigned (regcache
,
4750 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4757 record_full_arch_list_add_mem (ea
, nb
);
4761 case 661: /* Store String Word Indexed */
4763 if (PPC_RA (insn
) != 0)
4764 regcache_raw_read_unsigned (regcache
,
4765 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4768 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4769 nb
= PPC_XER_NB (xer
);
4773 regcache_raw_read_unsigned (regcache
,
4774 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4777 record_full_arch_list_add_mem (ea
, nb
);
4782 case 467: /* Move To Special Purpose Register */
4783 switch (PPC_SPR (insn
))
4786 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4789 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4792 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4794 case 256: /* VRSAVE */
4795 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4801 case 147: /* Move To Split Little Endian */
4802 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4805 case 512: /* Move to Condition Register from XER */
4806 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4807 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4810 case 4: /* Trap Word */
4811 case 68: /* Trap Doubleword */
4812 case 430: /* Clear BHRB */
4813 case 598: /* Synchronize */
4814 case 62: /* Wait for Interrupt */
4816 case 22: /* Instruction Cache Block Touch */
4817 case 854: /* Enforce In-order Execution of I/O */
4818 case 246: /* Data Cache Block Touch for Store */
4819 case 54: /* Data Cache Block Store */
4820 case 86: /* Data Cache Block Flush */
4821 case 278: /* Data Cache Block Touch */
4822 case 758: /* Data Cache Block Allocate */
4823 case 982: /* Instruction Cache Block Invalidate */
4824 case 774: /* Copy */
4825 case 838: /* CP_Abort */
4828 case 654: /* Transaction Begin */
4829 case 686: /* Transaction End */
4830 case 750: /* Transaction Suspend or Resume */
4831 case 782: /* Transaction Abort Word Conditional */
4832 case 814: /* Transaction Abort Doubleword Conditional */
4833 case 846: /* Transaction Abort Word Conditional Immediate */
4834 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4835 case 910: /* Transaction Abort */
4836 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4838 case 718: /* Transaction Check */
4839 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4842 case 1014: /* Data Cache Block set to Zero */
4843 if (target_auxv_search (¤t_target
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4845 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4848 if (PPC_RA (insn
) != 0)
4849 regcache_raw_read_unsigned (regcache
,
4850 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4851 regcache_raw_read_unsigned (regcache
,
4852 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4853 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4854 record_full_arch_list_add_mem (ea
, at_dcsz
);
4859 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4860 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4864 /* Parse and record instructions of primary opcode-59 at ADDR.
4865 Return 0 if successful. */
4868 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4869 CORE_ADDR addr
, uint32_t insn
)
4871 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4872 int ext
= PPC_EXTOP (insn
);
4876 case 18: /* Floating Divide */
4877 case 20: /* Floating Subtract */
4878 case 21: /* Floating Add */
4879 case 22: /* Floating Square Root */
4880 case 24: /* Floating Reciprocal Estimate */
4881 case 25: /* Floating Multiply */
4882 case 26: /* Floating Reciprocal Square Root Estimate */
4883 case 28: /* Floating Multiply-Subtract */
4884 case 29: /* Floating Multiply-Add */
4885 case 30: /* Floating Negative Multiply-Subtract */
4886 case 31: /* Floating Negative Multiply-Add */
4887 record_full_arch_list_add_reg (regcache
,
4888 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4890 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4891 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4898 case 2: /* DFP Add */
4899 case 3: /* DFP Quantize */
4900 case 34: /* DFP Multiply */
4901 case 35: /* DFP Reround */
4902 case 67: /* DFP Quantize Immediate */
4903 case 99: /* DFP Round To FP Integer With Inexact */
4904 case 227: /* DFP Round To FP Integer Without Inexact */
4905 case 258: /* DFP Convert To DFP Long! */
4906 case 290: /* DFP Convert To Fixed */
4907 case 514: /* DFP Subtract */
4908 case 546: /* DFP Divide */
4909 case 770: /* DFP Round To DFP Short! */
4910 case 802: /* DFP Convert From Fixed */
4911 case 834: /* DFP Encode BCD To DPD */
4913 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4914 record_full_arch_list_add_reg (regcache
,
4915 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4916 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4919 case 130: /* DFP Compare Ordered */
4920 case 162: /* DFP Test Exponent */
4921 case 194: /* DFP Test Data Class */
4922 case 226: /* DFP Test Data Group */
4923 case 642: /* DFP Compare Unordered */
4924 case 674: /* DFP Test Significance */
4925 case 675: /* DFP Test Significance Immediate */
4926 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4927 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4930 case 66: /* DFP Shift Significand Left Immediate */
4931 case 98: /* DFP Shift Significand Right Immediate */
4932 case 322: /* DFP Decode DPD To BCD */
4933 case 354: /* DFP Extract Biased Exponent */
4934 case 866: /* DFP Insert Biased Exponent */
4935 record_full_arch_list_add_reg (regcache
,
4936 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4938 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4941 case 846: /* Floating Convert From Integer Doubleword Single */
4942 case 974: /* Floating Convert From Integer Doubleword Unsigned
4944 record_full_arch_list_add_reg (regcache
,
4945 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4947 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4948 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4953 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4954 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4958 /* Parse and record instructions of primary opcode-60 at ADDR.
4959 Return 0 if successful. */
4962 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4963 CORE_ADDR addr
, uint32_t insn
)
4965 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4966 int ext
= PPC_EXTOP (insn
);
4970 case 0: /* VSX Scalar Add Single-Precision */
4971 case 32: /* VSX Scalar Add Double-Precision */
4972 case 24: /* VSX Scalar Divide Single-Precision */
4973 case 56: /* VSX Scalar Divide Double-Precision */
4974 case 176: /* VSX Scalar Copy Sign Double-Precision */
4975 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4976 case 41: /* ditto */
4977 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4979 case 160: /* VSX Scalar Maximum Double-Precision */
4980 case 168: /* VSX Scalar Minimum Double-Precision */
4981 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4982 case 57: /* ditto */
4983 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4984 case 25: /* ditto */
4985 case 48: /* VSX Scalar Multiply Double-Precision */
4986 case 16: /* VSX Scalar Multiply Single-Precision */
4987 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4988 case 169: /* ditto */
4989 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4990 case 137: /* ditto */
4991 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4992 case 185: /* ditto */
4993 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4994 case 153: /* ditto */
4995 case 40: /* VSX Scalar Subtract Double-Precision */
4996 case 8: /* VSX Scalar Subtract Single-Precision */
4997 case 96: /* VSX Vector Add Double-Precision */
4998 case 64: /* VSX Vector Add Single-Precision */
4999 case 120: /* VSX Vector Divide Double-Precision */
5000 case 88: /* VSX Vector Divide Single-Precision */
5001 case 97: /* VSX Vector Multiply-Add Double-Precision */
5002 case 105: /* ditto */
5003 case 65: /* VSX Vector Multiply-Add Single-Precision */
5004 case 73: /* ditto */
5005 case 224: /* VSX Vector Maximum Double-Precision */
5006 case 192: /* VSX Vector Maximum Single-Precision */
5007 case 232: /* VSX Vector Minimum Double-Precision */
5008 case 200: /* VSX Vector Minimum Single-Precision */
5009 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5010 case 121: /* ditto */
5011 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5012 case 89: /* ditto */
5013 case 112: /* VSX Vector Multiply Double-Precision */
5014 case 80: /* VSX Vector Multiply Single-Precision */
5015 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5016 case 233: /* ditto */
5017 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5018 case 201: /* ditto */
5019 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5020 case 249: /* ditto */
5021 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5022 case 217: /* ditto */
5023 case 104: /* VSX Vector Subtract Double-Precision */
5024 case 72: /* VSX Vector Subtract Single-Precision */
5025 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5026 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5027 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5028 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5029 case 3: /* VSX Scalar Compare Equal Double-Precision */
5030 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5031 case 19: /* VSX Scalar Compare Greater Than or Equal
5033 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5035 case 240: /* VSX Vector Copy Sign Double-Precision */
5036 case 208: /* VSX Vector Copy Sign Single-Precision */
5037 case 130: /* VSX Logical AND */
5038 case 138: /* VSX Logical AND with Complement */
5039 case 186: /* VSX Logical Equivalence */
5040 case 178: /* VSX Logical NAND */
5041 case 170: /* VSX Logical OR with Complement */
5042 case 162: /* VSX Logical NOR */
5043 case 146: /* VSX Logical OR */
5044 case 154: /* VSX Logical XOR */
5045 case 18: /* VSX Merge High Word */
5046 case 50: /* VSX Merge Low Word */
5047 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5048 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5049 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5050 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5051 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5052 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5053 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5054 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5055 case 216: /* VSX Vector Insert Exponent Single-Precision */
5056 case 248: /* VSX Vector Insert Exponent Double-Precision */
5057 case 26: /* VSX Vector Permute */
5058 case 58: /* VSX Vector Permute Right-indexed */
5059 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5060 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5061 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5062 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5063 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5066 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5067 case 125: /* VSX Vector Test for software Divide Double-Precision */
5068 case 93: /* VSX Vector Test for software Divide Single-Precision */
5069 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5072 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5073 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5074 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5075 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5076 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5080 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5082 case 99: /* VSX Vector Compare Equal To Double-Precision */
5083 case 67: /* VSX Vector Compare Equal To Single-Precision */
5084 case 115: /* VSX Vector Compare Greater Than or
5085 Equal To Double-Precision */
5086 case 83: /* VSX Vector Compare Greater Than or
5087 Equal To Single-Precision */
5088 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5089 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5091 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5092 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5093 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5099 case 265: /* VSX Scalar round Double-Precision to
5100 Single-Precision and Convert to
5101 Single-Precision format */
5102 case 344: /* VSX Scalar truncate Double-Precision to
5103 Integer and Convert to Signed Integer
5104 Doubleword format with Saturate */
5105 case 88: /* VSX Scalar truncate Double-Precision to
5106 Integer and Convert to Signed Integer Word
5107 Format with Saturate */
5108 case 328: /* VSX Scalar truncate Double-Precision integer
5109 and Convert to Unsigned Integer Doubleword
5110 Format with Saturate */
5111 case 72: /* VSX Scalar truncate Double-Precision to
5112 Integer and Convert to Unsigned Integer Word
5113 Format with Saturate */
5114 case 329: /* VSX Scalar Convert Single-Precision to
5115 Double-Precision format */
5116 case 376: /* VSX Scalar Convert Signed Integer
5117 Doubleword to floating-point format and
5118 Round to Double-Precision format */
5119 case 312: /* VSX Scalar Convert Signed Integer
5120 Doubleword to floating-point format and
5121 round to Single-Precision */
5122 case 360: /* VSX Scalar Convert Unsigned Integer
5123 Doubleword to floating-point format and
5124 Round to Double-Precision format */
5125 case 296: /* VSX Scalar Convert Unsigned Integer
5126 Doubleword to floating-point format and
5127 Round to Single-Precision */
5128 case 73: /* VSX Scalar Round to Double-Precision Integer
5129 Using Round to Nearest Away */
5130 case 107: /* VSX Scalar Round to Double-Precision Integer
5131 Exact using Current rounding mode */
5132 case 121: /* VSX Scalar Round to Double-Precision Integer
5133 Using Round toward -Infinity */
5134 case 105: /* VSX Scalar Round to Double-Precision Integer
5135 Using Round toward +Infinity */
5136 case 89: /* VSX Scalar Round to Double-Precision Integer
5137 Using Round toward Zero */
5138 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5139 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5140 case 281: /* VSX Scalar Round to Single-Precision */
5141 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5143 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5145 case 75: /* VSX Scalar Square Root Double-Precision */
5146 case 11: /* VSX Scalar Square Root Single-Precision */
5147 case 393: /* VSX Vector round Double-Precision to
5148 Single-Precision and Convert to
5149 Single-Precision format */
5150 case 472: /* VSX Vector truncate Double-Precision to
5151 Integer and Convert to Signed Integer
5152 Doubleword format with Saturate */
5153 case 216: /* VSX Vector truncate Double-Precision to
5154 Integer and Convert to Signed Integer Word
5155 Format with Saturate */
5156 case 456: /* VSX Vector truncate Double-Precision to
5157 Integer and Convert to Unsigned Integer
5158 Doubleword format with Saturate */
5159 case 200: /* VSX Vector truncate Double-Precision to
5160 Integer and Convert to Unsigned Integer Word
5161 Format with Saturate */
5162 case 457: /* VSX Vector Convert Single-Precision to
5163 Double-Precision format */
5164 case 408: /* VSX Vector truncate Single-Precision to
5165 Integer and Convert to Signed Integer
5166 Doubleword format with Saturate */
5167 case 152: /* VSX Vector truncate Single-Precision to
5168 Integer and Convert to Signed Integer Word
5169 Format with Saturate */
5170 case 392: /* VSX Vector truncate Single-Precision to
5171 Integer and Convert to Unsigned Integer
5172 Doubleword format with Saturate */
5173 case 136: /* VSX Vector truncate Single-Precision to
5174 Integer and Convert to Unsigned Integer Word
5175 Format with Saturate */
5176 case 504: /* VSX Vector Convert and round Signed Integer
5177 Doubleword to Double-Precision format */
5178 case 440: /* VSX Vector Convert and round Signed Integer
5179 Doubleword to Single-Precision format */
5180 case 248: /* VSX Vector Convert Signed Integer Word to
5181 Double-Precision format */
5182 case 184: /* VSX Vector Convert and round Signed Integer
5183 Word to Single-Precision format */
5184 case 488: /* VSX Vector Convert and round Unsigned
5185 Integer Doubleword to Double-Precision format */
5186 case 424: /* VSX Vector Convert and round Unsigned
5187 Integer Doubleword to Single-Precision format */
5188 case 232: /* VSX Vector Convert and round Unsigned
5189 Integer Word to Double-Precision format */
5190 case 168: /* VSX Vector Convert and round Unsigned
5191 Integer Word to Single-Precision format */
5192 case 201: /* VSX Vector Round to Double-Precision
5193 Integer using round to Nearest Away */
5194 case 235: /* VSX Vector Round to Double-Precision
5195 Integer Exact using Current rounding mode */
5196 case 249: /* VSX Vector Round to Double-Precision
5197 Integer using round toward -Infinity */
5198 case 233: /* VSX Vector Round to Double-Precision
5199 Integer using round toward +Infinity */
5200 case 217: /* VSX Vector Round to Double-Precision
5201 Integer using round toward Zero */
5202 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5203 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5204 case 137: /* VSX Vector Round to Single-Precision Integer
5205 Using Round to Nearest Away */
5206 case 171: /* VSX Vector Round to Single-Precision Integer
5207 Exact Using Current rounding mode */
5208 case 185: /* VSX Vector Round to Single-Precision Integer
5209 Using Round toward -Infinity */
5210 case 169: /* VSX Vector Round to Single-Precision Integer
5211 Using Round toward +Infinity */
5212 case 153: /* VSX Vector Round to Single-Precision Integer
5213 Using round toward Zero */
5214 case 202: /* VSX Vector Reciprocal Square Root Estimate
5216 case 138: /* VSX Vector Reciprocal Square Root Estimate
5218 case 203: /* VSX Vector Square Root Double-Precision */
5219 case 139: /* VSX Vector Square Root Single-Precision */
5220 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5222 case 345: /* VSX Scalar Absolute Value Double-Precision */
5223 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5224 Vector Single-Precision format Non-signalling */
5225 case 331: /* VSX Scalar Convert Single-Precision to
5226 Double-Precision format Non-signalling */
5227 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5228 case 377: /* VSX Scalar Negate Double-Precision */
5229 case 473: /* VSX Vector Absolute Value Double-Precision */
5230 case 409: /* VSX Vector Absolute Value Single-Precision */
5231 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5232 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5233 case 505: /* VSX Vector Negate Double-Precision */
5234 case 441: /* VSX Vector Negate Single-Precision */
5235 case 164: /* VSX Splat Word */
5236 case 165: /* VSX Vector Extract Unsigned Word */
5237 case 181: /* VSX Vector Insert Word */
5238 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5241 case 298: /* VSX Scalar Test Data Class Single-Precision */
5242 case 362: /* VSX Scalar Test Data Class Double-Precision */
5243 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5245 case 106: /* VSX Scalar Test for software Square Root
5247 case 234: /* VSX Vector Test for software Square Root
5249 case 170: /* VSX Vector Test for software Square Root
5251 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5255 switch (PPC_FIELD (insn
, 11, 5))
5257 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5258 case 1: /* VSX Scalar Extract Significand Double-Precision */
5259 record_full_arch_list_add_reg (regcache
,
5260 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5262 case 16: /* VSX Scalar Convert Half-Precision format to
5263 Double-Precision format */
5264 case 17: /* VSX Scalar round & Convert Double-Precision format
5265 to Half-Precision format */
5266 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5267 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5273 switch (PPC_FIELD (insn
, 11, 5))
5275 case 24: /* VSX Vector Convert Half-Precision format to
5276 Single-Precision format */
5277 case 25: /* VSX Vector round and Convert Single-Precision format
5278 to Half-Precision format */
5279 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5281 case 0: /* VSX Vector Extract Exponent Double-Precision */
5282 case 1: /* VSX Vector Extract Significand Double-Precision */
5283 case 7: /* VSX Vector Byte-Reverse Halfword */
5284 case 8: /* VSX Vector Extract Exponent Single-Precision */
5285 case 9: /* VSX Vector Extract Significand Single-Precision */
5286 case 15: /* VSX Vector Byte-Reverse Word */
5287 case 23: /* VSX Vector Byte-Reverse Doubleword */
5288 case 31: /* VSX Vector Byte-Reverse Quadword */
5289 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5297 case 360: /* VSX Vector Splat Immediate Byte */
5298 if (PPC_FIELD (insn
, 11, 2) == 0)
5300 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5304 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5305 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5309 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5311 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5315 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5316 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5320 /* Parse and record instructions of primary opcode-61 at ADDR.
5321 Return 0 if successful. */
5324 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5325 CORE_ADDR addr
, uint32_t insn
)
5327 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5333 case 0: /* Store Floating-Point Double Pair */
5334 case 2: /* Store VSX Scalar Doubleword */
5335 case 3: /* Store VSX Scalar Single */
5336 if (PPC_RA (insn
) != 0)
5337 regcache_raw_read_unsigned (regcache
,
5338 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5340 ea
+= PPC_DS (insn
) << 2;
5343 case 0: /* Store Floating-Point Double Pair */
5346 case 2: /* Store VSX Scalar Doubleword */
5349 case 3: /* Store VSX Scalar Single */
5355 record_full_arch_list_add_mem (ea
, size
);
5361 case 1: /* Load VSX Vector */
5362 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5364 case 5: /* Store VSX Vector */
5365 if (PPC_RA (insn
) != 0)
5366 regcache_raw_read_unsigned (regcache
,
5367 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5369 ea
+= PPC_DQ (insn
) << 4;
5370 record_full_arch_list_add_mem (ea
, 16);
5374 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5375 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5379 /* Parse and record instructions of primary opcode-63 at ADDR.
5380 Return 0 if successful. */
5383 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5384 CORE_ADDR addr
, uint32_t insn
)
5386 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5387 int ext
= PPC_EXTOP (insn
);
5392 case 18: /* Floating Divide */
5393 case 20: /* Floating Subtract */
5394 case 21: /* Floating Add */
5395 case 22: /* Floating Square Root */
5396 case 24: /* Floating Reciprocal Estimate */
5397 case 25: /* Floating Multiply */
5398 case 26: /* Floating Reciprocal Square Root Estimate */
5399 case 28: /* Floating Multiply-Subtract */
5400 case 29: /* Floating Multiply-Add */
5401 case 30: /* Floating Negative Multiply-Subtract */
5402 case 31: /* Floating Negative Multiply-Add */
5403 record_full_arch_list_add_reg (regcache
,
5404 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5406 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5407 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5410 case 23: /* Floating Select */
5411 record_full_arch_list_add_reg (regcache
,
5412 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5414 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5420 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5421 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5423 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5424 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5430 case 2: /* DFP Add Quad */
5431 case 3: /* DFP Quantize Quad */
5432 case 34: /* DFP Multiply Quad */
5433 case 35: /* DFP Reround Quad */
5434 case 67: /* DFP Quantize Immediate Quad */
5435 case 99: /* DFP Round To FP Integer With Inexact Quad */
5436 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5437 case 258: /* DFP Convert To DFP Extended Quad */
5438 case 514: /* DFP Subtract Quad */
5439 case 546: /* DFP Divide Quad */
5440 case 770: /* DFP Round To DFP Long Quad */
5441 case 802: /* DFP Convert From Fixed Quad */
5442 case 834: /* DFP Encode BCD To DPD Quad */
5444 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5445 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5446 record_full_arch_list_add_reg (regcache
, tmp
);
5447 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5448 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5451 case 130: /* DFP Compare Ordered Quad */
5452 case 162: /* DFP Test Exponent Quad */
5453 case 194: /* DFP Test Data Class Quad */
5454 case 226: /* DFP Test Data Group Quad */
5455 case 642: /* DFP Compare Unordered Quad */
5456 case 674: /* DFP Test Significance Quad */
5457 case 675: /* DFP Test Significance Immediate Quad */
5458 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5459 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5462 case 66: /* DFP Shift Significand Left Immediate Quad */
5463 case 98: /* DFP Shift Significand Right Immediate Quad */
5464 case 322: /* DFP Decode DPD To BCD Quad */
5465 case 866: /* DFP Insert Biased Exponent Quad */
5466 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5467 record_full_arch_list_add_reg (regcache
, tmp
);
5468 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5470 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5473 case 290: /* DFP Convert To Fixed Quad */
5474 record_full_arch_list_add_reg (regcache
,
5475 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5477 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5478 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5481 case 354: /* DFP Extract Biased Exponent Quad */
5482 record_full_arch_list_add_reg (regcache
,
5483 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5485 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5488 case 12: /* Floating Round to Single-Precision */
5489 case 14: /* Floating Convert To Integer Word */
5490 case 15: /* Floating Convert To Integer Word
5491 with round toward Zero */
5492 case 142: /* Floating Convert To Integer Word Unsigned */
5493 case 143: /* Floating Convert To Integer Word Unsigned
5494 with round toward Zero */
5495 case 392: /* Floating Round to Integer Nearest */
5496 case 424: /* Floating Round to Integer Toward Zero */
5497 case 456: /* Floating Round to Integer Plus */
5498 case 488: /* Floating Round to Integer Minus */
5499 case 814: /* Floating Convert To Integer Doubleword */
5500 case 815: /* Floating Convert To Integer Doubleword
5501 with round toward Zero */
5502 case 846: /* Floating Convert From Integer Doubleword */
5503 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5504 case 943: /* Floating Convert To Integer Doubleword Unsigned
5505 with round toward Zero */
5506 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5507 record_full_arch_list_add_reg (regcache
,
5508 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5510 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5511 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5515 switch (PPC_FIELD (insn
, 11, 5))
5517 case 1: /* Move From FPSCR & Clear Enables */
5518 case 20: /* Move From FPSCR Control & set DRN */
5519 case 21: /* Move From FPSCR Control & set DRN Immediate */
5520 case 22: /* Move From FPSCR Control & set RN */
5521 case 23: /* Move From FPSCR Control & set RN Immediate */
5522 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5523 case 0: /* Move From FPSCR */
5524 case 24: /* Move From FPSCR Lightweight */
5525 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5526 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5527 record_full_arch_list_add_reg (regcache
,
5528 tdep
->ppc_fp0_regnum
5534 case 8: /* Floating Copy Sign */
5535 case 40: /* Floating Negate */
5536 case 72: /* Floating Move Register */
5537 case 136: /* Floating Negative Absolute Value */
5538 case 264: /* Floating Absolute Value */
5539 record_full_arch_list_add_reg (regcache
,
5540 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5542 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5545 case 838: /* Floating Merge Odd Word */
5546 case 966: /* Floating Merge Even Word */
5547 record_full_arch_list_add_reg (regcache
,
5548 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5551 case 38: /* Move To FPSCR Bit 1 */
5552 case 70: /* Move To FPSCR Bit 0 */
5553 case 134: /* Move To FPSCR Field Immediate */
5554 case 711: /* Move To FPSCR Fields */
5556 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5557 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5560 case 0: /* Floating Compare Unordered */
5561 case 32: /* Floating Compare Ordered */
5562 case 64: /* Move to Condition Register from FPSCR */
5563 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5564 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5565 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5566 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5567 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5569 case 128: /* Floating Test for software Divide */
5570 case 160: /* Floating Test for software Square Root */
5571 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5574 case 4: /* VSX Scalar Add Quad-Precision */
5575 case 36: /* VSX Scalar Multiply Quad-Precision */
5576 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5577 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5578 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5579 case 484: /* VSX Scalar Negative Multiply-Subtract
5581 case 516: /* VSX Scalar Subtract Quad-Precision */
5582 case 548: /* VSX Scalar Divide Quad-Precision */
5583 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5585 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5586 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5587 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5591 switch (PPC_FIELD (insn
, 11, 5))
5593 case 27: /* VSX Scalar Square Root Quad-Precision */
5594 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5596 case 0: /* VSX Scalar Absolute Quad-Precision */
5597 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5598 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5599 case 16: /* VSX Scalar Negate Quad-Precision */
5600 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5601 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5607 switch (PPC_FIELD (insn
, 11, 5))
5609 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5610 to Unsigned Word format */
5611 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5612 Quad-Precision format */
5613 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5614 to Signed Word format */
5615 case 10: /* VSX Scalar Convert Signed Doubleword format to
5616 Quad-Precision format */
5617 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5618 to Unsigned Doubleword format */
5619 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5620 Double-Precision format */
5621 case 22: /* VSX Scalar Convert Double-Precision format to
5622 Quad-Precision format */
5623 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5624 to Signed Doubleword format */
5625 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5626 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5631 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5632 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5636 /* Parse the current instruction and record the values of the registers and
5637 memory that will be changed in current instruction to "record_arch_list".
5638 Return -1 if something wrong. */
5641 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5644 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5645 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5649 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5650 op6
= PPC_OP6 (insn
);
5654 case 2: /* Trap Doubleword Immediate */
5655 case 3: /* Trap Word Immediate */
5660 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5664 case 17: /* System call */
5665 if (PPC_LEV (insn
) != 0)
5668 if (tdep
->ppc_syscall_record
!= NULL
)
5670 if (tdep
->ppc_syscall_record (regcache
) != 0)
5675 printf_unfiltered (_("no syscall record support\n"));
5680 case 7: /* Multiply Low Immediate */
5681 record_full_arch_list_add_reg (regcache
,
5682 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5685 case 8: /* Subtract From Immediate Carrying */
5686 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5687 record_full_arch_list_add_reg (regcache
,
5688 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5691 case 10: /* Compare Logical Immediate */
5692 case 11: /* Compare Immediate */
5693 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5696 case 13: /* Add Immediate Carrying and Record */
5697 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5699 case 12: /* Add Immediate Carrying */
5700 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5702 case 14: /* Add Immediate */
5703 case 15: /* Add Immediate Shifted */
5704 record_full_arch_list_add_reg (regcache
,
5705 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5708 case 16: /* Branch Conditional */
5709 if ((PPC_BO (insn
) & 0x4) == 0)
5710 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5712 case 18: /* Branch */
5714 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5718 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5722 case 20: /* Rotate Left Word Immediate then Mask Insert */
5723 case 21: /* Rotate Left Word Immediate then AND with Mask */
5724 case 23: /* Rotate Left Word then AND with Mask */
5725 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5726 /* Rotate Left Doubleword Immediate then Clear Right */
5727 /* Rotate Left Doubleword Immediate then Clear */
5728 /* Rotate Left Doubleword then Clear Left */
5729 /* Rotate Left Doubleword then Clear Right */
5730 /* Rotate Left Doubleword Immediate then Mask Insert */
5732 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5733 record_full_arch_list_add_reg (regcache
,
5734 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5737 case 28: /* AND Immediate */
5738 case 29: /* AND Immediate Shifted */
5739 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5741 case 24: /* OR Immediate */
5742 case 25: /* OR Immediate Shifted */
5743 case 26: /* XOR Immediate */
5744 case 27: /* XOR Immediate Shifted */
5745 record_full_arch_list_add_reg (regcache
,
5746 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5750 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5754 case 33: /* Load Word and Zero with Update */
5755 case 35: /* Load Byte and Zero with Update */
5756 case 41: /* Load Halfword and Zero with Update */
5757 case 43: /* Load Halfword Algebraic with Update */
5758 record_full_arch_list_add_reg (regcache
,
5759 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5761 case 32: /* Load Word and Zero */
5762 case 34: /* Load Byte and Zero */
5763 case 40: /* Load Halfword and Zero */
5764 case 42: /* Load Halfword Algebraic */
5765 record_full_arch_list_add_reg (regcache
,
5766 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5769 case 46: /* Load Multiple Word */
5770 for (i
= PPC_RT (insn
); i
< 32; i
++)
5771 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5774 case 56: /* Load Quadword */
5775 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5776 record_full_arch_list_add_reg (regcache
, tmp
);
5777 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5780 case 49: /* Load Floating-Point Single with Update */
5781 case 51: /* Load Floating-Point Double with Update */
5782 record_full_arch_list_add_reg (regcache
,
5783 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5785 case 48: /* Load Floating-Point Single */
5786 case 50: /* Load Floating-Point Double */
5787 record_full_arch_list_add_reg (regcache
,
5788 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5791 case 47: /* Store Multiple Word */
5795 if (PPC_RA (insn
) != 0)
5796 regcache_raw_read_unsigned (regcache
,
5797 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5800 addr
+= PPC_D (insn
);
5801 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5805 case 37: /* Store Word with Update */
5806 case 39: /* Store Byte with Update */
5807 case 45: /* Store Halfword with Update */
5808 case 53: /* Store Floating-Point Single with Update */
5809 case 55: /* Store Floating-Point Double with Update */
5810 record_full_arch_list_add_reg (regcache
,
5811 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5813 case 36: /* Store Word */
5814 case 38: /* Store Byte */
5815 case 44: /* Store Halfword */
5816 case 52: /* Store Floating-Point Single */
5817 case 54: /* Store Floating-Point Double */
5822 if (PPC_RA (insn
) != 0)
5823 regcache_raw_read_unsigned (regcache
,
5824 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5826 addr
+= PPC_D (insn
);
5828 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5830 else if (op6
== 54 || op6
== 55)
5832 else if (op6
== 44 || op6
== 45)
5834 else if (op6
== 38 || op6
== 39)
5839 record_full_arch_list_add_mem (addr
, size
);
5846 case 0: /* Load Floating-Point Double Pair */
5847 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5848 record_full_arch_list_add_reg (regcache
, tmp
);
5849 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5851 case 2: /* Load VSX Scalar Doubleword */
5852 case 3: /* Load VSX Scalar Single */
5853 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5860 case 58: /* Load Doubleword */
5861 /* Load Doubleword with Update */
5862 /* Load Word Algebraic */
5863 if (PPC_FIELD (insn
, 30, 2) > 2)
5866 record_full_arch_list_add_reg (regcache
,
5867 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5868 if (PPC_BIT (insn
, 31))
5869 record_full_arch_list_add_reg (regcache
,
5870 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5874 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5879 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5884 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
5888 case 62: /* Store Doubleword */
5889 /* Store Doubleword with Update */
5890 /* Store Quadword with Update */
5894 int sub2
= PPC_FIELD (insn
, 30, 2);
5899 if (PPC_RA (insn
) != 0)
5900 regcache_raw_read_unsigned (regcache
,
5901 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5904 size
= (sub2
== 2) ? 16 : 8;
5906 addr
+= PPC_DS (insn
) << 2;
5907 record_full_arch_list_add_mem (addr
, size
);
5909 if (op6
== 62 && sub2
== 1)
5910 record_full_arch_list_add_reg (regcache
,
5911 tdep
->ppc_gp0_regnum
+
5918 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5924 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5925 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5929 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5931 if (record_full_arch_list_add_end ())
5936 /* Initialize the current architecture based on INFO. If possible, re-use an
5937 architecture from ARCHES, which is a list of architectures already created
5938 during this debugging session.
5940 Called e.g. at program startup, when reading a core file, and when reading
5943 static struct gdbarch
*
5944 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5946 struct gdbarch
*gdbarch
;
5947 struct gdbarch_tdep
*tdep
;
5948 int wordsize
, from_xcoff_exec
, from_elf_exec
;
5949 enum bfd_architecture arch
;
5952 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
5954 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
5955 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
5956 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
5958 int tdesc_wordsize
= -1;
5959 const struct target_desc
*tdesc
= info
.target_desc
;
5960 struct tdesc_arch_data
*tdesc_data
= NULL
;
5961 int num_pseudoregs
= 0;
5964 /* INFO may refer to a binary that is not of the PowerPC architecture,
5965 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5966 In this case, we must not attempt to infer properties of the (PowerPC
5967 side) of the target system from properties of that executable. Trust
5968 the target description instead. */
5970 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
5971 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
5974 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5975 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
5977 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
5978 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
5980 /* Check word size. If INFO is from a binary file, infer it from
5981 that, else choose a likely default. */
5982 if (from_xcoff_exec
)
5984 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
5989 else if (from_elf_exec
)
5991 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5996 else if (tdesc_has_registers (tdesc
))
6000 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6001 wordsize
= (info
.bfd_arch_info
->bits_per_word
6002 / info
.bfd_arch_info
->bits_per_byte
);
6007 /* Get the architecture and machine from the BFD. */
6008 arch
= info
.bfd_arch_info
->arch
;
6009 mach
= info
.bfd_arch_info
->mach
;
6011 /* For e500 executables, the apuinfo section is of help here. Such
6012 section contains the identifier and revision number of each
6013 Application-specific Processing Unit that is present on the
6014 chip. The content of the section is determined by the assembler
6015 which looks at each instruction and determines which unit (and
6016 which version of it) can execute it. Grovel through the section
6017 looking for relevant e500 APUs. */
6019 if (bfd_uses_spe_extensions (info
.abfd
))
6021 arch
= info
.bfd_arch_info
->arch
;
6022 mach
= bfd_mach_ppc_e500
;
6023 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6024 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6027 /* Find a default target description which describes our register
6028 layout, if we do not already have one. */
6029 if (! tdesc_has_registers (tdesc
))
6031 const struct variant
*v
;
6033 /* Choose variant. */
6034 v
= find_variant_by_arch (arch
, mach
);
6041 gdb_assert (tdesc_has_registers (tdesc
));
6043 /* Check any target description for validity. */
6044 if (tdesc_has_registers (tdesc
))
6046 static const char *const gprs
[] = {
6047 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6048 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6049 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6050 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6052 const struct tdesc_feature
*feature
;
6054 static const char *const msr_names
[] = { "msr", "ps" };
6055 static const char *const cr_names
[] = { "cr", "cnd" };
6056 static const char *const ctr_names
[] = { "ctr", "cnt" };
6058 feature
= tdesc_find_feature (tdesc
,
6059 "org.gnu.gdb.power.core");
6060 if (feature
== NULL
)
6063 tdesc_data
= tdesc_data_alloc ();
6066 for (i
= 0; i
< ppc_num_gprs
; i
++)
6067 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
6068 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
6070 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
6072 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
6075 /* Allow alternate names for these registers, to accomodate GDB's
6077 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6078 PPC_MSR_REGNUM
, msr_names
);
6079 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6080 PPC_CR_REGNUM
, cr_names
);
6081 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6082 PPC_CTR_REGNUM
, ctr_names
);
6086 tdesc_data_cleanup (tdesc_data
);
6090 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
6093 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
6095 wordsize
= tdesc_wordsize
;
6097 feature
= tdesc_find_feature (tdesc
,
6098 "org.gnu.gdb.power.fpu");
6099 if (feature
!= NULL
)
6101 static const char *const fprs
[] = {
6102 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6103 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6104 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6105 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6108 for (i
= 0; i
< ppc_num_fprs
; i
++)
6109 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6110 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6111 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6112 PPC_FPSCR_REGNUM
, "fpscr");
6116 tdesc_data_cleanup (tdesc_data
);
6124 /* The DFP pseudo-registers will be available when there are floating
6126 have_dfp
= have_fpu
;
6128 feature
= tdesc_find_feature (tdesc
,
6129 "org.gnu.gdb.power.altivec");
6130 if (feature
!= NULL
)
6132 static const char *const vector_regs
[] = {
6133 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6134 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6135 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6136 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6140 for (i
= 0; i
< ppc_num_gprs
; i
++)
6141 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6144 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6145 PPC_VSCR_REGNUM
, "vscr");
6146 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6147 PPC_VRSAVE_REGNUM
, "vrsave");
6149 if (have_spe
|| !valid_p
)
6151 tdesc_data_cleanup (tdesc_data
);
6159 /* Check for POWER7 VSX registers support. */
6160 feature
= tdesc_find_feature (tdesc
,
6161 "org.gnu.gdb.power.vsx");
6163 if (feature
!= NULL
)
6165 static const char *const vsx_regs
[] = {
6166 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6167 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6168 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6169 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6170 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6176 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6177 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6178 PPC_VSR0_UPPER_REGNUM
+ i
,
6182 tdesc_data_cleanup (tdesc_data
);
6191 /* On machines supporting the SPE APU, the general-purpose registers
6192 are 64 bits long. There are SIMD vector instructions to treat them
6193 as pairs of floats, but the rest of the instruction set treats them
6194 as 32-bit registers, and only operates on their lower halves.
6196 In the GDB regcache, we treat their high and low halves as separate
6197 registers. The low halves we present as the general-purpose
6198 registers, and then we have pseudo-registers that stitch together
6199 the upper and lower halves and present them as pseudo-registers.
6201 Thus, the target description is expected to supply the upper
6202 halves separately. */
6204 feature
= tdesc_find_feature (tdesc
,
6205 "org.gnu.gdb.power.spe");
6206 if (feature
!= NULL
)
6208 static const char *const upper_spe
[] = {
6209 "ev0h", "ev1h", "ev2h", "ev3h",
6210 "ev4h", "ev5h", "ev6h", "ev7h",
6211 "ev8h", "ev9h", "ev10h", "ev11h",
6212 "ev12h", "ev13h", "ev14h", "ev15h",
6213 "ev16h", "ev17h", "ev18h", "ev19h",
6214 "ev20h", "ev21h", "ev22h", "ev23h",
6215 "ev24h", "ev25h", "ev26h", "ev27h",
6216 "ev28h", "ev29h", "ev30h", "ev31h"
6220 for (i
= 0; i
< ppc_num_gprs
; i
++)
6221 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6222 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6224 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6225 PPC_SPE_ACC_REGNUM
, "acc");
6226 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6227 PPC_SPE_FSCR_REGNUM
, "spefscr");
6229 if (have_mq
|| have_fpu
|| !valid_p
)
6231 tdesc_data_cleanup (tdesc_data
);
6240 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6241 complain for a 32-bit binary on a 64-bit target; we do not yet
6242 support that. For instance, the 32-bit ABI routines expect
6245 As long as there isn't an explicit target description, we'll
6246 choose one based on the BFD architecture and get a word size
6247 matching the binary (probably powerpc:common or
6248 powerpc:common64). So there is only trouble if a 64-bit target
6249 supplies a 64-bit description while debugging a 32-bit
6251 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6253 tdesc_data_cleanup (tdesc_data
);
6260 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6263 elf_abi
= POWERPC_ELF_V1
;
6266 elf_abi
= POWERPC_ELF_V2
;
6273 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6275 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6276 Tag_GNU_Power_ABI_FP
))
6279 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6282 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6289 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6291 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6292 Tag_GNU_Power_ABI_Vector
))
6295 vector_abi
= POWERPC_VEC_GENERIC
;
6298 vector_abi
= POWERPC_VEC_ALTIVEC
;
6301 vector_abi
= POWERPC_VEC_SPE
;
6309 /* At this point, the only supported ELF-based 64-bit little-endian
6310 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6311 default. All other supported ELF-based operating systems use the
6312 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6313 e.g. because we run a legacy binary, or have attached to a process
6314 and have not found any associated binary file, set the default
6315 according to this heuristic. */
6316 if (elf_abi
== POWERPC_ELF_AUTO
)
6318 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6319 elf_abi
= POWERPC_ELF_V2
;
6321 elf_abi
= POWERPC_ELF_V1
;
6324 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6326 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6329 soft_float
= !have_fpu
;
6331 /* If we have a hard float binary or setting but no floating point
6332 registers, downgrade to soft float anyway. We're still somewhat
6333 useful in this scenario. */
6334 if (!soft_float
&& !have_fpu
)
6337 /* Similarly for vector registers. */
6338 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6339 vector_abi
= POWERPC_VEC_GENERIC
;
6341 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6342 vector_abi
= POWERPC_VEC_GENERIC
;
6344 if (vector_abi
== POWERPC_VEC_AUTO
)
6347 vector_abi
= POWERPC_VEC_ALTIVEC
;
6349 vector_abi
= POWERPC_VEC_SPE
;
6351 vector_abi
= POWERPC_VEC_GENERIC
;
6354 /* Do not limit the vector ABI based on available hardware, since we
6355 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6357 /* Find a candidate among extant architectures. */
6358 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6360 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6362 /* Word size in the various PowerPC bfd_arch_info structs isn't
6363 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6364 separate word size check. */
6365 tdep
= gdbarch_tdep (arches
->gdbarch
);
6366 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6368 if (tdep
&& tdep
->soft_float
!= soft_float
)
6370 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6372 if (tdep
&& tdep
->wordsize
== wordsize
)
6374 if (tdesc_data
!= NULL
)
6375 tdesc_data_cleanup (tdesc_data
);
6376 return arches
->gdbarch
;
6380 /* None found, create a new architecture from INFO, whose bfd_arch_info
6381 validity depends on the source:
6382 - executable useless
6383 - rs6000_host_arch() good
6385 - "set arch" trust blindly
6386 - GDB startup useless but harmless */
6388 tdep
= XCNEW (struct gdbarch_tdep
);
6389 tdep
->wordsize
= wordsize
;
6390 tdep
->elf_abi
= elf_abi
;
6391 tdep
->soft_float
= soft_float
;
6392 tdep
->vector_abi
= vector_abi
;
6394 gdbarch
= gdbarch_alloc (&info
, tdep
);
6396 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6397 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6398 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6399 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6400 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6401 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6402 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6403 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6405 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6406 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6407 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6408 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6409 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6410 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6411 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6412 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6414 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6415 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6416 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6417 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6419 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6420 GDB traditionally called it "ps", though, so let GDB add an
6422 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6425 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6427 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6429 /* Set lr_frame_offset. */
6431 tdep
->lr_frame_offset
= 16;
6433 tdep
->lr_frame_offset
= 4;
6435 if (have_spe
|| have_dfp
|| have_vsx
)
6437 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6438 set_gdbarch_pseudo_register_write (gdbarch
,
6439 rs6000_pseudo_register_write
);
6440 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6441 rs6000_ax_pseudo_register_collect
);
6444 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6446 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6448 /* Select instruction printer. */
6449 if (arch
== bfd_arch_rs6000
)
6450 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
6452 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
6454 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6457 num_pseudoregs
+= 32;
6459 num_pseudoregs
+= 16;
6461 /* Include both VSX and Extended FP registers. */
6462 num_pseudoregs
+= 96;
6464 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6466 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6467 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6468 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6469 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6470 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6471 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6472 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6473 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6474 set_gdbarch_char_signed (gdbarch
, 0);
6476 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6479 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6481 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6482 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6483 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6485 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6486 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6489 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6490 else if (wordsize
== 8)
6491 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6493 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6494 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6495 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6497 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6499 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6500 rs6000_breakpoint::kind_from_pc
);
6501 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6502 rs6000_breakpoint::bp_from_kind
);
6504 /* The value of symbols of type N_SO and N_FUN maybe null when
6506 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6508 /* Handles single stepping of atomic sequences. */
6509 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6511 /* Not sure on this. FIXMEmgo */
6512 set_gdbarch_frame_args_skip (gdbarch
, 8);
6514 /* Helpers for function argument information. */
6515 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6518 set_gdbarch_in_solib_return_trampoline
6519 (gdbarch
, rs6000_in_solib_return_trampoline
);
6520 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6522 /* Hook in the DWARF CFI frame unwinder. */
6523 dwarf2_append_unwinders (gdbarch
);
6524 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6526 /* Frame handling. */
6527 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6529 /* Setup displaced stepping. */
6530 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6531 ppc_displaced_step_copy_insn
);
6532 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6533 ppc_displaced_step_hw_singlestep
);
6534 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6535 set_gdbarch_displaced_step_free_closure (gdbarch
,
6536 simple_displaced_step_free_closure
);
6537 set_gdbarch_displaced_step_location (gdbarch
,
6538 displaced_step_at_entry_point
);
6540 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6542 /* Hook in ABI-specific overrides, if they have been registered. */
6543 info
.target_desc
= tdesc
;
6544 info
.tdep_info
= tdesc_data
;
6545 gdbarch_init_osabi (info
, gdbarch
);
6549 case GDB_OSABI_LINUX
:
6550 case GDB_OSABI_NETBSD
:
6551 case GDB_OSABI_UNKNOWN
:
6552 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6553 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6554 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6555 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6556 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6559 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6561 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6562 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6563 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6564 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6565 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6568 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6569 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6570 rs6000_pseudo_register_reggroup_p
);
6571 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6573 /* Override the normal target description method to make the SPE upper
6574 halves anonymous. */
6575 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6577 /* Choose register numbers for all supported pseudo-registers. */
6578 tdep
->ppc_ev0_regnum
= -1;
6579 tdep
->ppc_dl0_regnum
= -1;
6580 tdep
->ppc_vsr0_regnum
= -1;
6581 tdep
->ppc_efpr0_regnum
= -1;
6583 cur_reg
= gdbarch_num_regs (gdbarch
);
6587 tdep
->ppc_ev0_regnum
= cur_reg
;
6592 tdep
->ppc_dl0_regnum
= cur_reg
;
6597 tdep
->ppc_vsr0_regnum
= cur_reg
;
6599 tdep
->ppc_efpr0_regnum
= cur_reg
;
6603 gdb_assert (gdbarch_num_regs (gdbarch
)
6604 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
6606 /* Register the ravenscar_arch_ops. */
6607 if (mach
== bfd_mach_ppc_e500
)
6608 register_e500_ravenscar_ops (gdbarch
);
6610 register_ppc_ravenscar_ops (gdbarch
);
6616 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6618 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6623 /* FIXME: Dump gdbarch_tdep. */
6626 /* PowerPC-specific commands. */
6629 set_powerpc_command (char *args
, int from_tty
)
6631 printf_unfiltered (_("\
6632 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6633 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6637 show_powerpc_command (char *args
, int from_tty
)
6639 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6643 powerpc_set_soft_float (char *args
, int from_tty
,
6644 struct cmd_list_element
*c
)
6646 struct gdbarch_info info
;
6648 /* Update the architecture. */
6649 gdbarch_info_init (&info
);
6650 if (!gdbarch_update_p (info
))
6651 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6655 powerpc_set_vector_abi (char *args
, int from_tty
,
6656 struct cmd_list_element
*c
)
6658 struct gdbarch_info info
;
6661 for (vector_abi
= POWERPC_VEC_AUTO
;
6662 vector_abi
!= POWERPC_VEC_LAST
;
6664 if (strcmp (powerpc_vector_abi_string
,
6665 powerpc_vector_strings
[vector_abi
]) == 0)
6667 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6671 if (vector_abi
== POWERPC_VEC_LAST
)
6672 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6673 powerpc_vector_abi_string
);
6675 /* Update the architecture. */
6676 gdbarch_info_init (&info
);
6677 if (!gdbarch_update_p (info
))
6678 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6681 /* Show the current setting of the exact watchpoints flag. */
6684 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6685 struct cmd_list_element
*c
,
6688 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6691 /* Read a PPC instruction from memory. */
6694 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6696 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6697 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6699 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6702 /* Return non-zero if the instructions at PC match the series
6703 described in PATTERN, or zero otherwise. PATTERN is an array of
6704 'struct ppc_insn_pattern' objects, terminated by an entry whose
6707 When the match is successful, fill INSN[i] with what PATTERN[i]
6708 matched. If PATTERN[i] is optional, and the instruction wasn't
6709 present, set INSN[i] to 0 (which is not a valid PPC instruction).
6710 INSN should have as many elements as PATTERN. Note that, if
6711 PATTERN contains optional instructions which aren't present in
6712 memory, then INSN will have holes, so INSN[i] isn't necessarily the
6713 i'th instruction in memory. */
6716 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6717 struct ppc_insn_pattern
*pattern
,
6718 unsigned int *insns
)
6723 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6726 insn
= read_insn (frame
, pc
);
6728 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6734 else if (!pattern
[i
].optional
)
6741 /* Return the 'd' field of the d-form instruction INSN, properly
6745 ppc_insn_d_field (unsigned int insn
)
6747 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6750 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6751 zero bits concatenated at the right, and properly
6755 ppc_insn_ds_field (unsigned int insn
)
6757 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6760 /* Initialization code. */
6762 /* -Wmissing-prototypes */
6763 extern initialize_file_ftype _initialize_rs6000_tdep
;
6766 _initialize_rs6000_tdep (void)
6768 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6769 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6771 /* Initialize the standard target descriptions. */
6772 initialize_tdesc_powerpc_32 ();
6773 initialize_tdesc_powerpc_altivec32 ();
6774 initialize_tdesc_powerpc_vsx32 ();
6775 initialize_tdesc_powerpc_403 ();
6776 initialize_tdesc_powerpc_403gc ();
6777 initialize_tdesc_powerpc_405 ();
6778 initialize_tdesc_powerpc_505 ();
6779 initialize_tdesc_powerpc_601 ();
6780 initialize_tdesc_powerpc_602 ();
6781 initialize_tdesc_powerpc_603 ();
6782 initialize_tdesc_powerpc_604 ();
6783 initialize_tdesc_powerpc_64 ();
6784 initialize_tdesc_powerpc_altivec64 ();
6785 initialize_tdesc_powerpc_vsx64 ();
6786 initialize_tdesc_powerpc_7400 ();
6787 initialize_tdesc_powerpc_750 ();
6788 initialize_tdesc_powerpc_860 ();
6789 initialize_tdesc_powerpc_e500 ();
6790 initialize_tdesc_rs6000 ();
6792 /* Add root prefix command for all "set powerpc"/"show powerpc"
6794 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6795 _("Various PowerPC-specific commands."),
6796 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6798 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6799 _("Various PowerPC-specific commands."),
6800 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6802 /* Add a command to allow the user to force the ABI. */
6803 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6804 &powerpc_soft_float_global
,
6805 _("Set whether to use a soft-float ABI."),
6806 _("Show whether to use a soft-float ABI."),
6808 powerpc_set_soft_float
, NULL
,
6809 &setpowerpccmdlist
, &showpowerpccmdlist
);
6811 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6812 &powerpc_vector_abi_string
,
6813 _("Set the vector ABI."),
6814 _("Show the vector ABI."),
6815 NULL
, powerpc_set_vector_abi
, NULL
,
6816 &setpowerpccmdlist
, &showpowerpccmdlist
);
6818 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6819 &target_exact_watchpoints
,
6821 Set whether to use just one debug register for watchpoints on scalars."),
6823 Show whether to use just one debug register for watchpoints on scalars."),
6825 If true, GDB will use only one debug register when watching a variable of\n\
6826 scalar type, thus assuming that the variable is accessed through the address\n\
6827 of its first byte."),
6828 NULL
, show_powerpc_exact_watchpoints
,
6829 &setpowerpccmdlist
, &showpowerpccmdlist
);