1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2015 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
44 #include "libbfd.h" /* for bfd_default_set_arch_mach */
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
52 #include "elf/ppc64.h"
54 #include "solib-svr4.h"
56 #include "ppc-ravenscar-thread.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "features/rs6000/powerpc-32.c"
65 #include "features/rs6000/powerpc-altivec32.c"
66 #include "features/rs6000/powerpc-vsx32.c"
67 #include "features/rs6000/powerpc-403.c"
68 #include "features/rs6000/powerpc-403gc.c"
69 #include "features/rs6000/powerpc-405.c"
70 #include "features/rs6000/powerpc-505.c"
71 #include "features/rs6000/powerpc-601.c"
72 #include "features/rs6000/powerpc-602.c"
73 #include "features/rs6000/powerpc-603.c"
74 #include "features/rs6000/powerpc-604.c"
75 #include "features/rs6000/powerpc-64.c"
76 #include "features/rs6000/powerpc-altivec64.c"
77 #include "features/rs6000/powerpc-vsx64.c"
78 #include "features/rs6000/powerpc-7400.c"
79 #include "features/rs6000/powerpc-750.c"
80 #include "features/rs6000/powerpc-860.c"
81 #include "features/rs6000/powerpc-e500.c"
82 #include "features/rs6000/rs6000.c"
84 /* Determine if regnum is an SPE pseudo-register. */
85 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
86 && (regnum) >= (tdep)->ppc_ev0_regnum \
87 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
89 /* Determine if regnum is a decimal float pseudo-register. */
90 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_dl0_regnum \
92 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
94 /* Determine if regnum is a POWER7 VSX register. */
95 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_vsr0_regnum \
97 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
99 /* Determine if regnum is a POWER7 Extended FP register. */
100 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_efpr0_regnum \
102 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
104 /* The list of available "set powerpc ..." and "show powerpc ..."
106 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
107 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
109 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
111 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
112 static const char *const powerpc_vector_strings
[] =
121 /* A variable that can be configured by the user. */
122 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
123 static const char *powerpc_vector_abi_string
= "auto";
125 /* To be used by skip_prologue. */
127 struct rs6000_framedata
129 int offset
; /* total size of frame --- the distance
130 by which we decrement sp to allocate
132 int saved_gpr
; /* smallest # of saved gpr */
133 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
134 int saved_fpr
; /* smallest # of saved fpr */
135 int saved_vr
; /* smallest # of saved vr */
136 int saved_ev
; /* smallest # of saved ev */
137 int alloca_reg
; /* alloca register number (frame ptr) */
138 char frameless
; /* true if frameless functions. */
139 char nosavedpc
; /* true if pc not saved. */
140 char used_bl
; /* true if link register clobbered */
141 int gpr_offset
; /* offset of saved gprs from prev sp */
142 int fpr_offset
; /* offset of saved fprs from prev sp */
143 int vr_offset
; /* offset of saved vrs from prev sp */
144 int ev_offset
; /* offset of saved evs from prev sp */
145 int lr_offset
; /* offset of saved lr */
146 int lr_register
; /* register of saved lr, if trustworthy */
147 int cr_offset
; /* offset of saved cr */
148 int vrsave_offset
; /* offset of saved vrsave register */
152 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
154 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
156 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
157 if (tdep
->ppc_vsr0_regnum
< 0)
160 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
161 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
164 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
166 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
168 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
169 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
172 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
176 /* Return true if REGNO is an SPE register, false otherwise. */
178 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
180 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
182 /* Is it a reference to EV0 -- EV31, and do we have those? */
183 if (IS_SPE_PSEUDOREG (tdep
, regno
))
186 /* Is it a reference to one of the raw upper GPR halves? */
187 if (tdep
->ppc_ev0_upper_regnum
>= 0
188 && tdep
->ppc_ev0_upper_regnum
<= regno
189 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
192 /* Is it a reference to the 64-bit accumulator, and do we have that? */
193 if (tdep
->ppc_acc_regnum
>= 0
194 && tdep
->ppc_acc_regnum
== regno
)
197 /* Is it a reference to the SPE floating-point status and control register,
198 and do we have that? */
199 if (tdep
->ppc_spefscr_regnum
>= 0
200 && tdep
->ppc_spefscr_regnum
== regno
)
207 /* Return non-zero if the architecture described by GDBARCH has
208 floating-point registers (f0 --- f31 and fpscr). */
210 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
214 return (tdep
->ppc_fp0_regnum
>= 0
215 && tdep
->ppc_fpscr_regnum
>= 0);
218 /* Return non-zero if the architecture described by GDBARCH has
219 VSX registers (vsr0 --- vsr63). */
221 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
223 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
225 return tdep
->ppc_vsr0_regnum
>= 0;
228 /* Return non-zero if the architecture described by GDBARCH has
229 Altivec registers (vr0 --- vr31, vrsave and vscr). */
231 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
233 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
235 return (tdep
->ppc_vr0_regnum
>= 0
236 && tdep
->ppc_vrsave_regnum
>= 0);
239 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
242 This is a helper function for init_sim_regno_table, constructing
243 the table mapping GDB register numbers to sim register numbers; we
244 initialize every element in that table to -1 before we start
247 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
249 /* Make sure we don't try to assign any given GDB register a sim
250 register number more than once. */
251 gdb_assert (table
[gdb_regno
] == -1);
252 table
[gdb_regno
] = sim_regno
;
256 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
257 numbers to simulator register numbers, based on the values placed
258 in the ARCH->tdep->ppc_foo_regnum members. */
260 init_sim_regno_table (struct gdbarch
*arch
)
262 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
263 int total_regs
= gdbarch_num_regs (arch
);
264 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
266 static const char *const segment_regs
[] = {
267 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
268 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
271 /* Presume that all registers not explicitly mentioned below are
272 unavailable from the sim. */
273 for (i
= 0; i
< total_regs
; i
++)
276 /* General-purpose registers. */
277 for (i
= 0; i
< ppc_num_gprs
; i
++)
278 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
280 /* Floating-point registers. */
281 if (tdep
->ppc_fp0_regnum
>= 0)
282 for (i
= 0; i
< ppc_num_fprs
; i
++)
283 set_sim_regno (sim_regno
,
284 tdep
->ppc_fp0_regnum
+ i
,
285 sim_ppc_f0_regnum
+ i
);
286 if (tdep
->ppc_fpscr_regnum
>= 0)
287 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
289 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
290 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
291 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
293 /* Segment registers. */
294 for (i
= 0; i
< ppc_num_srs
; i
++)
298 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
300 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
303 /* Altivec registers. */
304 if (tdep
->ppc_vr0_regnum
>= 0)
306 for (i
= 0; i
< ppc_num_vrs
; i
++)
307 set_sim_regno (sim_regno
,
308 tdep
->ppc_vr0_regnum
+ i
,
309 sim_ppc_vr0_regnum
+ i
);
311 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
312 we can treat this more like the other cases. */
313 set_sim_regno (sim_regno
,
314 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
315 sim_ppc_vscr_regnum
);
317 /* vsave is a special-purpose register, so the code below handles it. */
319 /* SPE APU (E500) registers. */
320 if (tdep
->ppc_ev0_upper_regnum
>= 0)
321 for (i
= 0; i
< ppc_num_gprs
; i
++)
322 set_sim_regno (sim_regno
,
323 tdep
->ppc_ev0_upper_regnum
+ i
,
324 sim_ppc_rh0_regnum
+ i
);
325 if (tdep
->ppc_acc_regnum
>= 0)
326 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
327 /* spefscr is a special-purpose register, so the code below handles it. */
330 /* Now handle all special-purpose registers. Verify that they
331 haven't mistakenly been assigned numbers by any of the above
333 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
335 const char *spr_name
= sim_spr_register_name (i
);
338 if (spr_name
!= NULL
)
339 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
342 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
346 /* Drop the initialized array into place. */
347 tdep
->sim_regno
= sim_regno
;
351 /* Given a GDB register number REG, return the corresponding SIM
354 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
356 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
359 if (tdep
->sim_regno
== NULL
)
360 init_sim_regno_table (gdbarch
);
363 && reg
<= gdbarch_num_regs (gdbarch
)
364 + gdbarch_num_pseudo_regs (gdbarch
));
365 sim_regno
= tdep
->sim_regno
[reg
];
370 return LEGACY_SIM_REGNO_IGNORE
;
375 /* Register set support functions. */
377 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
378 Write the register to REGCACHE. */
381 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
382 const gdb_byte
*regs
, size_t offset
, int regsize
)
384 if (regnum
!= -1 && offset
!= -1)
388 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
389 int gdb_regsize
= register_size (gdbarch
, regnum
);
390 if (gdb_regsize
< regsize
391 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
392 offset
+= regsize
- gdb_regsize
;
394 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
398 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
399 in a field REGSIZE wide. Zero pad as necessary. */
402 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
403 gdb_byte
*regs
, size_t offset
, int regsize
)
405 if (regnum
!= -1 && offset
!= -1)
409 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
410 int gdb_regsize
= register_size (gdbarch
, regnum
);
411 if (gdb_regsize
< regsize
)
413 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
415 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
416 offset
+= regsize
- gdb_regsize
;
419 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
420 regsize
- gdb_regsize
);
423 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
428 ppc_greg_offset (struct gdbarch
*gdbarch
,
429 struct gdbarch_tdep
*tdep
,
430 const struct ppc_reg_offsets
*offsets
,
434 *regsize
= offsets
->gpr_size
;
435 if (regnum
>= tdep
->ppc_gp0_regnum
436 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
437 return (offsets
->r0_offset
438 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
440 if (regnum
== gdbarch_pc_regnum (gdbarch
))
441 return offsets
->pc_offset
;
443 if (regnum
== tdep
->ppc_ps_regnum
)
444 return offsets
->ps_offset
;
446 if (regnum
== tdep
->ppc_lr_regnum
)
447 return offsets
->lr_offset
;
449 if (regnum
== tdep
->ppc_ctr_regnum
)
450 return offsets
->ctr_offset
;
452 *regsize
= offsets
->xr_size
;
453 if (regnum
== tdep
->ppc_cr_regnum
)
454 return offsets
->cr_offset
;
456 if (regnum
== tdep
->ppc_xer_regnum
)
457 return offsets
->xer_offset
;
459 if (regnum
== tdep
->ppc_mq_regnum
)
460 return offsets
->mq_offset
;
466 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
467 const struct ppc_reg_offsets
*offsets
,
470 if (regnum
>= tdep
->ppc_fp0_regnum
471 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
472 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
474 if (regnum
== tdep
->ppc_fpscr_regnum
)
475 return offsets
->fpscr_offset
;
481 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
482 const struct ppc_reg_offsets
*offsets
,
485 if (regnum
>= tdep
->ppc_vr0_regnum
486 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
487 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
489 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
490 return offsets
->vscr_offset
;
492 if (regnum
== tdep
->ppc_vrsave_regnum
)
493 return offsets
->vrsave_offset
;
498 /* Supply register REGNUM in the general-purpose register set REGSET
499 from the buffer specified by GREGS and LEN to register cache
500 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
503 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
504 int regnum
, const void *gregs
, size_t len
)
506 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
507 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
508 const struct ppc_reg_offsets
*offsets
= regset
->regmap
;
515 int gpr_size
= offsets
->gpr_size
;
517 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
518 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
519 i
++, offset
+= gpr_size
)
520 ppc_supply_reg (regcache
, i
, gregs
, offset
, gpr_size
);
522 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
523 gregs
, offsets
->pc_offset
, gpr_size
);
524 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
525 gregs
, offsets
->ps_offset
, gpr_size
);
526 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
527 gregs
, offsets
->lr_offset
, gpr_size
);
528 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
529 gregs
, offsets
->ctr_offset
, gpr_size
);
530 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
531 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
532 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
533 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
535 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
539 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
540 ppc_supply_reg (regcache
, regnum
, gregs
, offset
, regsize
);
543 /* Supply register REGNUM in the floating-point register set REGSET
544 from the buffer specified by FPREGS and LEN to register cache
545 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
548 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
549 int regnum
, const void *fpregs
, size_t len
)
551 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
552 struct gdbarch_tdep
*tdep
;
553 const struct ppc_reg_offsets
*offsets
;
556 if (!ppc_floating_point_unit_p (gdbarch
))
559 tdep
= gdbarch_tdep (gdbarch
);
560 offsets
= regset
->regmap
;
565 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
566 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
568 ppc_supply_reg (regcache
, i
, fpregs
, offset
, 8);
570 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
571 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
575 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
576 ppc_supply_reg (regcache
, regnum
, fpregs
, offset
,
577 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
580 /* Supply register REGNUM in the VSX register set REGSET
581 from the buffer specified by VSXREGS and LEN to register cache
582 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
585 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
586 int regnum
, const void *vsxregs
, size_t len
)
588 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
589 struct gdbarch_tdep
*tdep
;
591 if (!ppc_vsx_support_p (gdbarch
))
594 tdep
= gdbarch_tdep (gdbarch
);
600 for (i
= tdep
->ppc_vsr0_upper_regnum
;
601 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
603 ppc_supply_reg (regcache
, i
, vsxregs
, 0, 8);
608 ppc_supply_reg (regcache
, regnum
, vsxregs
, 0, 8);
611 /* Supply register REGNUM in the Altivec register set REGSET
612 from the buffer specified by VRREGS and LEN to register cache
613 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
616 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
617 int regnum
, const void *vrregs
, size_t len
)
619 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
620 struct gdbarch_tdep
*tdep
;
621 const struct ppc_reg_offsets
*offsets
;
624 if (!ppc_altivec_support_p (gdbarch
))
627 tdep
= gdbarch_tdep (gdbarch
);
628 offsets
= regset
->regmap
;
633 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
634 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
636 ppc_supply_reg (regcache
, i
, vrregs
, offset
, 16);
638 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
639 vrregs
, offsets
->vscr_offset
, 4);
641 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
642 vrregs
, offsets
->vrsave_offset
, 4);
646 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
647 if (regnum
!= tdep
->ppc_vrsave_regnum
648 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
649 ppc_supply_reg (regcache
, regnum
, vrregs
, offset
, 16);
651 ppc_supply_reg (regcache
, regnum
,
655 /* Collect register REGNUM in the general-purpose register set
656 REGSET from register cache REGCACHE into the buffer specified by
657 GREGS and LEN. If REGNUM is -1, do this for all registers in
661 ppc_collect_gregset (const struct regset
*regset
,
662 const struct regcache
*regcache
,
663 int regnum
, void *gregs
, size_t len
)
665 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
666 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
667 const struct ppc_reg_offsets
*offsets
= regset
->regmap
;
674 int gpr_size
= offsets
->gpr_size
;
676 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
677 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
678 i
++, offset
+= gpr_size
)
679 ppc_collect_reg (regcache
, i
, gregs
, offset
, gpr_size
);
681 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
682 gregs
, offsets
->pc_offset
, gpr_size
);
683 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
684 gregs
, offsets
->ps_offset
, gpr_size
);
685 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
686 gregs
, offsets
->lr_offset
, gpr_size
);
687 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
688 gregs
, offsets
->ctr_offset
, gpr_size
);
689 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
690 gregs
, offsets
->cr_offset
, offsets
->xr_size
);
691 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
692 gregs
, offsets
->xer_offset
, offsets
->xr_size
);
693 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
694 gregs
, offsets
->mq_offset
, offsets
->xr_size
);
698 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
699 ppc_collect_reg (regcache
, regnum
, gregs
, offset
, regsize
);
702 /* Collect register REGNUM in the floating-point register set
703 REGSET from register cache REGCACHE into the buffer specified by
704 FPREGS and LEN. If REGNUM is -1, do this for all registers in
708 ppc_collect_fpregset (const struct regset
*regset
,
709 const struct regcache
*regcache
,
710 int regnum
, void *fpregs
, size_t len
)
712 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
713 struct gdbarch_tdep
*tdep
;
714 const struct ppc_reg_offsets
*offsets
;
717 if (!ppc_floating_point_unit_p (gdbarch
))
720 tdep
= gdbarch_tdep (gdbarch
);
721 offsets
= regset
->regmap
;
726 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
727 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
729 ppc_collect_reg (regcache
, i
, fpregs
, offset
, 8);
731 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
732 fpregs
, offsets
->fpscr_offset
, offsets
->fpscr_size
);
736 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
737 ppc_collect_reg (regcache
, regnum
, fpregs
, offset
,
738 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
741 /* Collect register REGNUM in the VSX register set
742 REGSET from register cache REGCACHE into the buffer specified by
743 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
747 ppc_collect_vsxregset (const struct regset
*regset
,
748 const struct regcache
*regcache
,
749 int regnum
, void *vsxregs
, size_t len
)
751 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
752 struct gdbarch_tdep
*tdep
;
754 if (!ppc_vsx_support_p (gdbarch
))
757 tdep
= gdbarch_tdep (gdbarch
);
763 for (i
= tdep
->ppc_vsr0_upper_regnum
;
764 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
766 ppc_collect_reg (regcache
, i
, vsxregs
, 0, 8);
771 ppc_collect_reg (regcache
, regnum
, vsxregs
, 0, 8);
775 /* Collect register REGNUM in the Altivec register set
776 REGSET from register cache REGCACHE into the buffer specified by
777 VRREGS and LEN. If REGNUM is -1, do this for all registers in
781 ppc_collect_vrregset (const struct regset
*regset
,
782 const struct regcache
*regcache
,
783 int regnum
, void *vrregs
, size_t len
)
785 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
786 struct gdbarch_tdep
*tdep
;
787 const struct ppc_reg_offsets
*offsets
;
790 if (!ppc_altivec_support_p (gdbarch
))
793 tdep
= gdbarch_tdep (gdbarch
);
794 offsets
= regset
->regmap
;
799 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
800 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
802 ppc_collect_reg (regcache
, i
, vrregs
, offset
, 16);
804 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
805 vrregs
, offsets
->vscr_offset
, 4);
807 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
808 vrregs
, offsets
->vrsave_offset
, 4);
812 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
813 if (regnum
!= tdep
->ppc_vrsave_regnum
814 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
815 ppc_collect_reg (regcache
, regnum
, vrregs
, offset
, 16);
817 ppc_collect_reg (regcache
, regnum
,
823 insn_changes_sp_or_jumps (unsigned long insn
)
825 int opcode
= (insn
>> 26) & 0x03f;
826 int sd
= (insn
>> 21) & 0x01f;
827 int a
= (insn
>> 16) & 0x01f;
828 int subcode
= (insn
>> 1) & 0x3ff;
830 /* Changes the stack pointer. */
832 /* NOTE: There are many ways to change the value of a given register.
833 The ways below are those used when the register is R1, the SP,
834 in a funtion's epilogue. */
836 if (opcode
== 31 && subcode
== 444 && a
== 1)
837 return 1; /* mr R1,Rn */
838 if (opcode
== 14 && sd
== 1)
839 return 1; /* addi R1,Rn,simm */
840 if (opcode
== 58 && sd
== 1)
841 return 1; /* ld R1,ds(Rn) */
843 /* Transfers control. */
849 if (opcode
== 19 && subcode
== 16)
851 if (opcode
== 19 && subcode
== 528)
852 return 1; /* bcctr */
857 /* Return true if we are in the function's epilogue, i.e. after the
858 instruction that destroyed the function's stack frame.
860 1) scan forward from the point of execution:
861 a) If you find an instruction that modifies the stack pointer
862 or transfers control (except a return), execution is not in
864 b) Stop scanning if you find a return instruction or reach the
865 end of the function or reach the hard limit for the size of
867 2) scan backward from the point of execution:
868 a) If you find an instruction that modifies the stack pointer,
869 execution *is* in an epilogue, return.
870 b) Stop scanning if you reach an instruction that transfers
871 control or the beginning of the function or reach the hard
872 limit for the size of an epilogue. */
875 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
876 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
878 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
879 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
880 bfd_byte insn_buf
[PPC_INSN_SIZE
];
881 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
884 /* Find the search limits based on function boundaries and hard limit. */
886 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
889 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
890 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
892 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
893 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
895 /* Scan forward until next 'blr'. */
897 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
899 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
901 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
902 if (insn
== 0x4e800020)
904 /* Assume a bctr is a tail call unless it points strictly within
906 if (insn
== 0x4e800420)
908 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
909 tdep
->ppc_ctr_regnum
);
910 if (ctr
> func_start
&& ctr
< func_end
)
915 if (insn_changes_sp_or_jumps (insn
))
919 /* Scan backward until adjustment to stack pointer (R1). */
921 for (scan_pc
= pc
- PPC_INSN_SIZE
;
922 scan_pc
>= epilogue_start
;
923 scan_pc
-= PPC_INSN_SIZE
)
925 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
927 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
928 if (insn_changes_sp_or_jumps (insn
))
935 /* Implementation of gdbarch_in_function_epilogue_p. */
938 rs6000_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
940 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
944 /* Get the ith function argument for the current function. */
946 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
949 return get_frame_register_unsigned (frame
, 3 + argi
);
952 /* Sequence of bytes for breakpoint instruction. */
954 static const unsigned char *
955 rs6000_breakpoint_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*bp_addr
,
958 static unsigned char big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
959 static unsigned char little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
961 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
962 return big_breakpoint
;
964 return little_breakpoint
;
967 /* Instruction masks for displaced stepping. */
968 #define BRANCH_MASK 0xfc000000
969 #define BP_MASK 0xFC0007FE
970 #define B_INSN 0x48000000
971 #define BC_INSN 0x40000000
972 #define BXL_INSN 0x4c000000
973 #define BP_INSN 0x7C000008
975 /* Fix up the state of registers and memory after having single-stepped
976 a displaced instruction. */
978 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
979 struct displaced_step_closure
*closure
,
980 CORE_ADDR from
, CORE_ADDR to
,
981 struct regcache
*regs
)
983 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
984 /* Since we use simple_displaced_step_copy_insn, our closure is a
985 copy of the instruction. */
986 ULONGEST insn
= extract_unsigned_integer ((gdb_byte
*) closure
,
987 PPC_INSN_SIZE
, byte_order
);
989 /* Offset for non PC-relative instructions. */
990 LONGEST offset
= PPC_INSN_SIZE
;
992 opcode
= insn
& BRANCH_MASK
;
995 fprintf_unfiltered (gdb_stdlog
,
996 "displaced: (ppc) fixup (%s, %s)\n",
997 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1000 /* Handle PC-relative branch instructions. */
1001 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1003 ULONGEST current_pc
;
1005 /* Read the current PC value after the instruction has been executed
1006 in a displaced location. Calculate the offset to be applied to the
1007 original PC value before the displaced stepping. */
1008 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1010 offset
= current_pc
- to
;
1012 if (opcode
!= BXL_INSN
)
1014 /* Check for AA bit indicating whether this is an absolute
1015 addressing or PC-relative (1: absolute, 0: relative). */
1018 /* PC-relative addressing is being used in the branch. */
1019 if (debug_displaced
)
1022 "displaced: (ppc) branch instruction: %s\n"
1023 "displaced: (ppc) adjusted PC from %s to %s\n",
1024 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1025 paddress (gdbarch
, from
+ offset
));
1027 regcache_cooked_write_unsigned (regs
,
1028 gdbarch_pc_regnum (gdbarch
),
1034 /* If we're here, it means we have a branch to LR or CTR. If the
1035 branch was taken, the offset is probably greater than 4 (the next
1036 instruction), so it's safe to assume that an offset of 4 means we
1037 did not take the branch. */
1038 if (offset
== PPC_INSN_SIZE
)
1039 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1040 from
+ PPC_INSN_SIZE
);
1043 /* Check for LK bit indicating whether we should set the link
1044 register to point to the next instruction
1045 (1: Set, 0: Don't set). */
1048 /* Link register needs to be set to the next instruction's PC. */
1049 regcache_cooked_write_unsigned (regs
,
1050 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1051 from
+ PPC_INSN_SIZE
);
1052 if (debug_displaced
)
1053 fprintf_unfiltered (gdb_stdlog
,
1054 "displaced: (ppc) adjusted LR to %s\n",
1055 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1059 /* Check for breakpoints in the inferior. If we've found one, place the PC
1060 right at the breakpoint instruction. */
1061 else if ((insn
& BP_MASK
) == BP_INSN
)
1062 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1064 /* Handle any other instructions that do not fit in the categories above. */
1065 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1069 /* Always use hardware single-stepping to execute the
1070 displaced instruction. */
1072 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1073 struct displaced_step_closure
*closure
)
1078 /* Instruction masks used during single-stepping of atomic sequences. */
1079 #define LWARX_MASK 0xfc0007fe
1080 #define LWARX_INSTRUCTION 0x7c000028
1081 #define LDARX_INSTRUCTION 0x7c0000A8
1082 #define STWCX_MASK 0xfc0007ff
1083 #define STWCX_INSTRUCTION 0x7c00012d
1084 #define STDCX_INSTRUCTION 0x7c0001ad
1086 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1087 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1088 is found, attempt to step through it. A breakpoint is placed at the end of
1092 ppc_deal_with_atomic_sequence (struct frame_info
*frame
)
1094 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
1095 struct address_space
*aspace
= get_frame_address_space (frame
);
1096 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1097 CORE_ADDR pc
= get_frame_pc (frame
);
1098 CORE_ADDR breaks
[2] = {-1, -1};
1100 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1101 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1104 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1105 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1106 int opcode
; /* Branch instruction's OPcode. */
1107 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1109 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1110 if ((insn
& LWARX_MASK
) != LWARX_INSTRUCTION
1111 && (insn
& LWARX_MASK
) != LDARX_INSTRUCTION
)
1114 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1116 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1118 loc
+= PPC_INSN_SIZE
;
1119 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1121 /* Assume that there is at most one conditional branch in the atomic
1122 sequence. If a conditional branch is found, put a breakpoint in
1123 its destination address. */
1124 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1126 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1127 int absolute
= insn
& 2;
1129 if (bc_insn_count
>= 1)
1130 return 0; /* More than one conditional branch found, fallback
1131 to the standard single-step code. */
1134 breaks
[1] = immediate
;
1136 breaks
[1] = loc
+ immediate
;
1142 if ((insn
& STWCX_MASK
) == STWCX_INSTRUCTION
1143 || (insn
& STWCX_MASK
) == STDCX_INSTRUCTION
)
1147 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1148 if ((insn
& STWCX_MASK
) != STWCX_INSTRUCTION
1149 && (insn
& STWCX_MASK
) != STDCX_INSTRUCTION
)
1153 loc
+= PPC_INSN_SIZE
;
1154 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1156 /* Insert a breakpoint right after the end of the atomic sequence. */
1159 /* Check for duplicated breakpoints. Check also for a breakpoint
1160 placed (branch instruction's destination) anywhere in sequence. */
1162 && (breaks
[1] == breaks
[0]
1163 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1164 last_breakpoint
= 0;
1166 /* Effectively inserts the breakpoints. */
1167 for (index
= 0; index
<= last_breakpoint
; index
++)
1168 insert_single_step_breakpoint (gdbarch
, aspace
, breaks
[index
]);
1174 #define SIGNED_SHORT(x) \
1175 ((sizeof (short) == 2) \
1176 ? ((int)(short)(x)) \
1177 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1179 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1181 /* Limit the number of skipped non-prologue instructions, as the examining
1182 of the prologue is expensive. */
1183 static int max_skip_non_prologue_insns
= 10;
1185 /* Return nonzero if the given instruction OP can be part of the prologue
1186 of a function and saves a parameter on the stack. FRAMEP should be
1187 set if one of the previous instructions in the function has set the
1191 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1193 /* Move parameters from argument registers to temporary register. */
1194 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1196 /* Rx must be scratch register r0. */
1197 const int rx_regno
= (op
>> 16) & 31;
1198 /* Ry: Only r3 - r10 are used for parameter passing. */
1199 const int ry_regno
= GET_SRC_REG (op
);
1201 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1203 *r0_contains_arg
= 1;
1210 /* Save a General Purpose Register on stack. */
1212 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1213 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1215 /* Rx: Only r3 - r10 are used for parameter passing. */
1216 const int rx_regno
= GET_SRC_REG (op
);
1218 return (rx_regno
>= 3 && rx_regno
<= 10);
1221 /* Save a General Purpose Register on stack via the Frame Pointer. */
1224 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1225 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1226 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1228 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1229 However, the compiler sometimes uses r0 to hold an argument. */
1230 const int rx_regno
= GET_SRC_REG (op
);
1232 return ((rx_regno
>= 3 && rx_regno
<= 10)
1233 || (rx_regno
== 0 && *r0_contains_arg
));
1236 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1238 /* Only f2 - f8 are used for parameter passing. */
1239 const int src_regno
= GET_SRC_REG (op
);
1241 return (src_regno
>= 2 && src_regno
<= 8);
1244 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1246 /* Only f2 - f8 are used for parameter passing. */
1247 const int src_regno
= GET_SRC_REG (op
);
1249 return (src_regno
>= 2 && src_regno
<= 8);
1252 /* Not an insn that saves a parameter on stack. */
1256 /* Assuming that INSN is a "bl" instruction located at PC, return
1257 nonzero if the destination of the branch is a "blrl" instruction.
1259 This sequence is sometimes found in certain function prologues.
1260 It allows the function to load the LR register with a value that
1261 they can use to access PIC data using PC-relative offsets. */
1264 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1271 absolute
= (int) ((insn
>> 1) & 1);
1272 immediate
= ((insn
& ~3) << 6) >> 6;
1276 dest
= pc
+ immediate
;
1278 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1279 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1285 /* Masks for decoding a branch-and-link (bl) instruction.
1287 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1288 The former is anded with the opcode in question; if the result of
1289 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1290 question is a ``bl'' instruction.
1292 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1293 the branch displacement. */
1295 #define BL_MASK 0xfc000001
1296 #define BL_INSTRUCTION 0x48000001
1297 #define BL_DISPLACEMENT_MASK 0x03fffffc
1299 static unsigned long
1300 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1302 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1306 /* Fetch the instruction and convert it to an integer. */
1307 if (target_read_memory (pc
, buf
, 4))
1309 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1314 /* GCC generates several well-known sequences of instructions at the begining
1315 of each function prologue when compiling with -fstack-check. If one of
1316 such sequences starts at START_PC, then return the address of the
1317 instruction immediately past this sequence. Otherwise, return START_PC. */
1320 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1322 CORE_ADDR pc
= start_pc
;
1323 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1325 /* First possible sequence: A small number of probes.
1326 stw 0, -<some immediate>(1)
1327 [repeat this instruction any (small) number of times]. */
1329 if ((op
& 0xffff0000) == 0x90010000)
1331 while ((op
& 0xffff0000) == 0x90010000)
1334 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1339 /* Second sequence: A probing loop.
1340 addi 12,1,-<some immediate>
1341 lis 0,-<some immediate>
1342 [possibly ori 0,0,<some immediate>]
1346 addi 12,12,-<some immediate>
1349 [possibly one last probe: stw 0,<some immediate>(12)]. */
1353 /* addi 12,1,-<some immediate> */
1354 if ((op
& 0xffff0000) != 0x39810000)
1357 /* lis 0,-<some immediate> */
1359 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1360 if ((op
& 0xffff0000) != 0x3c000000)
1364 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1365 /* [possibly ori 0,0,<some immediate>] */
1366 if ((op
& 0xffff0000) == 0x60000000)
1369 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1372 if (op
!= 0x7c0c0214)
1377 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1378 if (op
!= 0x7c0c0000)
1383 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1384 if ((op
& 0xff9f0001) != 0x41820000)
1387 /* addi 12,12,-<some immediate> */
1389 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1390 if ((op
& 0xffff0000) != 0x398c0000)
1395 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1396 if (op
!= 0x900c0000)
1401 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1402 if ((op
& 0xfc000001) != 0x48000000)
1405 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1407 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1408 if ((op
& 0xffff0000) == 0x900c0000)
1411 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1414 /* We found a valid stack-check sequence, return the new PC. */
1418 /* Third sequence: No probe; instead, a comparizon between the stack size
1419 limit (saved in a run-time global variable) and the current stack
1422 addi 0,1,-<some immediate>
1423 lis 12,__gnat_stack_limit@ha
1424 lwz 12,__gnat_stack_limit@l(12)
1427 or, with a small variant in the case of a bigger stack frame:
1428 addis 0,1,<some immediate>
1429 addic 0,0,-<some immediate>
1430 lis 12,__gnat_stack_limit@ha
1431 lwz 12,__gnat_stack_limit@l(12)
1436 /* addi 0,1,-<some immediate> */
1437 if ((op
& 0xffff0000) != 0x38010000)
1439 /* small stack frame variant not recognized; try the
1440 big stack frame variant: */
1442 /* addis 0,1,<some immediate> */
1443 if ((op
& 0xffff0000) != 0x3c010000)
1446 /* addic 0,0,-<some immediate> */
1448 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1449 if ((op
& 0xffff0000) != 0x30000000)
1453 /* lis 12,<some immediate> */
1455 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1456 if ((op
& 0xffff0000) != 0x3d800000)
1459 /* lwz 12,<some immediate>(12) */
1461 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1462 if ((op
& 0xffff0000) != 0x818c0000)
1467 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1468 if ((op
& 0xfffffffe) != 0x7c406008)
1471 /* We found a valid stack-check sequence, return the new PC. */
1475 /* No stack check code in our prologue, return the start_pc. */
1479 /* return pc value after skipping a function prologue and also return
1480 information about a function frame.
1482 in struct rs6000_framedata fdata:
1483 - frameless is TRUE, if function does not have a frame.
1484 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1485 - offset is the initial size of this stack frame --- the amount by
1486 which we decrement the sp to allocate the frame.
1487 - saved_gpr is the number of the first saved gpr.
1488 - saved_fpr is the number of the first saved fpr.
1489 - saved_vr is the number of the first saved vr.
1490 - saved_ev is the number of the first saved ev.
1491 - alloca_reg is the number of the register used for alloca() handling.
1493 - gpr_offset is the offset of the first saved gpr from the previous frame.
1494 - fpr_offset is the offset of the first saved fpr from the previous frame.
1495 - vr_offset is the offset of the first saved vr from the previous frame.
1496 - ev_offset is the offset of the first saved ev from the previous frame.
1497 - lr_offset is the offset of the saved lr
1498 - cr_offset is the offset of the saved cr
1499 - vrsave_offset is the offset of the saved vrsave register. */
1502 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1503 struct rs6000_framedata
*fdata
)
1505 CORE_ADDR orig_pc
= pc
;
1506 CORE_ADDR last_prologue_pc
= pc
;
1507 CORE_ADDR li_found_pc
= 0;
1511 long vr_saved_offset
= 0;
1517 int vrsave_reg
= -1;
1520 int minimal_toc_loaded
= 0;
1521 int prev_insn_was_prologue_insn
= 1;
1522 int num_skip_non_prologue_insns
= 0;
1523 int r0_contains_arg
= 0;
1524 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1525 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1526 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1528 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1529 fdata
->saved_gpr
= -1;
1530 fdata
->saved_fpr
= -1;
1531 fdata
->saved_vr
= -1;
1532 fdata
->saved_ev
= -1;
1533 fdata
->alloca_reg
= -1;
1534 fdata
->frameless
= 1;
1535 fdata
->nosavedpc
= 1;
1536 fdata
->lr_register
= -1;
1538 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1544 /* Sometimes it isn't clear if an instruction is a prologue
1545 instruction or not. When we encounter one of these ambiguous
1546 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1547 Otherwise, we'll assume that it really is a prologue instruction. */
1548 if (prev_insn_was_prologue_insn
)
1549 last_prologue_pc
= pc
;
1551 /* Stop scanning if we've hit the limit. */
1555 prev_insn_was_prologue_insn
= 1;
1557 /* Fetch the instruction and convert it to an integer. */
1558 if (target_read_memory (pc
, buf
, 4))
1560 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1562 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1564 /* Since shared library / PIC code, which needs to get its
1565 address at runtime, can appear to save more than one link
1579 remember just the first one, but skip over additional
1582 lr_reg
= (op
& 0x03e00000) >> 21;
1584 r0_contains_arg
= 0;
1587 else if ((op
& 0xfc1fffff) == 0x7c000026)
1589 cr_reg
= (op
& 0x03e00000);
1591 r0_contains_arg
= 0;
1595 else if ((op
& 0xfc1f0000) == 0xd8010000)
1596 { /* stfd Rx,NUM(r1) */
1597 reg
= GET_SRC_REG (op
);
1598 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1600 fdata
->saved_fpr
= reg
;
1601 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1606 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1607 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1608 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1609 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1612 reg
= GET_SRC_REG (op
);
1613 if ((op
& 0xfc1f0000) == 0xbc010000)
1614 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1616 fdata
->gpr_mask
|= 1U << reg
;
1617 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1619 fdata
->saved_gpr
= reg
;
1620 if ((op
& 0xfc1f0003) == 0xf8010000)
1622 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1627 else if ((op
& 0xffff0000) == 0x3c4c0000
1628 || (op
& 0xffff0000) == 0x3c400000
1629 || (op
& 0xffff0000) == 0x38420000)
1631 /* . 0: addis 2,12,.TOC.-0b@ha
1632 . addi 2,2,.TOC.-0b@l
1636 used by ELFv2 global entry points to set up r2. */
1639 else if (op
== 0x60000000)
1642 /* Allow nops in the prologue, but do not consider them to
1643 be part of the prologue unless followed by other prologue
1645 prev_insn_was_prologue_insn
= 0;
1649 else if ((op
& 0xffff0000) == 0x3c000000)
1650 { /* addis 0,0,NUM, used for >= 32k frames */
1651 fdata
->offset
= (op
& 0x0000ffff) << 16;
1652 fdata
->frameless
= 0;
1653 r0_contains_arg
= 0;
1657 else if ((op
& 0xffff0000) == 0x60000000)
1658 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1659 fdata
->offset
|= (op
& 0x0000ffff);
1660 fdata
->frameless
= 0;
1661 r0_contains_arg
= 0;
1665 else if (lr_reg
>= 0 &&
1666 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1667 (((op
& 0xffff0000) == (lr_reg
| 0xf8010000)) ||
1668 /* stw Rx, NUM(r1) */
1669 ((op
& 0xffff0000) == (lr_reg
| 0x90010000)) ||
1670 /* stwu Rx, NUM(r1) */
1671 ((op
& 0xffff0000) == (lr_reg
| 0x94010000))))
1672 { /* where Rx == lr */
1673 fdata
->lr_offset
= offset
;
1674 fdata
->nosavedpc
= 0;
1675 /* Invalidate lr_reg, but don't set it to -1.
1676 That would mean that it had never been set. */
1678 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1679 (op
& 0xfc000000) == 0x90000000) /* stw */
1681 /* Does not update r1, so add displacement to lr_offset. */
1682 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1687 else if (cr_reg
>= 0 &&
1688 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1689 (((op
& 0xffff0000) == (cr_reg
| 0xf8010000)) ||
1690 /* stw Rx, NUM(r1) */
1691 ((op
& 0xffff0000) == (cr_reg
| 0x90010000)) ||
1692 /* stwu Rx, NUM(r1) */
1693 ((op
& 0xffff0000) == (cr_reg
| 0x94010000))))
1694 { /* where Rx == cr */
1695 fdata
->cr_offset
= offset
;
1696 /* Invalidate cr_reg, but don't set it to -1.
1697 That would mean that it had never been set. */
1699 if ((op
& 0xfc000003) == 0xf8000000 ||
1700 (op
& 0xfc000000) == 0x90000000)
1702 /* Does not update r1, so add displacement to cr_offset. */
1703 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1708 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1710 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1711 prediction bits. If the LR has already been saved, we can
1715 else if (op
== 0x48000005)
1722 else if (op
== 0x48000004)
1727 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1728 in V.4 -mminimal-toc */
1729 (op
& 0xffff0000) == 0x3bde0000)
1730 { /* addi 30,30,foo@l */
1734 else if ((op
& 0xfc000001) == 0x48000001)
1738 fdata
->frameless
= 0;
1740 /* If the return address has already been saved, we can skip
1741 calls to blrl (for PIC). */
1742 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1748 /* Don't skip over the subroutine call if it is not within
1749 the first three instructions of the prologue and either
1750 we have no line table information or the line info tells
1751 us that the subroutine call is not part of the line
1752 associated with the prologue. */
1753 if ((pc
- orig_pc
) > 8)
1755 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1756 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1758 if ((prologue_sal
.line
== 0)
1759 || (prologue_sal
.line
!= this_sal
.line
))
1763 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1765 /* At this point, make sure this is not a trampoline
1766 function (a function that simply calls another functions,
1767 and nothing else). If the next is not a nop, this branch
1768 was part of the function prologue. */
1770 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1771 break; /* Don't skip over
1777 /* update stack pointer */
1778 else if ((op
& 0xfc1f0000) == 0x94010000)
1779 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1780 fdata
->frameless
= 0;
1781 fdata
->offset
= SIGNED_SHORT (op
);
1782 offset
= fdata
->offset
;
1785 else if ((op
& 0xfc1f016a) == 0x7c01016e)
1786 { /* stwux rX,r1,rY */
1787 /* No way to figure out what r1 is going to be. */
1788 fdata
->frameless
= 0;
1789 offset
= fdata
->offset
;
1792 else if ((op
& 0xfc1f0003) == 0xf8010001)
1793 { /* stdu rX,NUM(r1) */
1794 fdata
->frameless
= 0;
1795 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1796 offset
= fdata
->offset
;
1799 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1800 { /* stdux rX,r1,rY */
1801 /* No way to figure out what r1 is going to be. */
1802 fdata
->frameless
= 0;
1803 offset
= fdata
->offset
;
1806 else if ((op
& 0xffff0000) == 0x38210000)
1807 { /* addi r1,r1,SIMM */
1808 fdata
->frameless
= 0;
1809 fdata
->offset
+= SIGNED_SHORT (op
);
1810 offset
= fdata
->offset
;
1813 /* Load up minimal toc pointer. Do not treat an epilogue restore
1814 of r31 as a minimal TOC load. */
1815 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1816 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1818 && !minimal_toc_loaded
)
1820 minimal_toc_loaded
= 1;
1823 /* move parameters from argument registers to local variable
1826 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1827 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1828 (((op
>> 21) & 31) <= 10) &&
1829 ((long) ((op
>> 16) & 31)
1830 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1834 /* store parameters in stack */
1836 /* Move parameters from argument registers to temporary register. */
1837 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1841 /* Set up frame pointer */
1843 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1845 fdata
->frameless
= 0;
1847 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1850 /* Another way to set up the frame pointer. */
1852 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1853 || op
== 0x7c3f0b78)
1855 fdata
->frameless
= 0;
1857 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1860 /* Another way to set up the frame pointer. */
1862 else if ((op
& 0xfc1fffff) == 0x38010000)
1863 { /* addi rX, r1, 0x0 */
1864 fdata
->frameless
= 0;
1866 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1867 + ((op
& ~0x38010000) >> 21));
1870 /* AltiVec related instructions. */
1871 /* Store the vrsave register (spr 256) in another register for
1872 later manipulation, or load a register into the vrsave
1873 register. 2 instructions are used: mfvrsave and
1874 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1875 and mtspr SPR256, Rn. */
1876 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1877 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1878 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1880 vrsave_reg
= GET_SRC_REG (op
);
1883 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1887 /* Store the register where vrsave was saved to onto the stack:
1888 rS is the register where vrsave was stored in a previous
1890 /* 100100 sssss 00001 dddddddd dddddddd */
1891 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1893 if (vrsave_reg
== GET_SRC_REG (op
))
1895 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
1900 /* Compute the new value of vrsave, by modifying the register
1901 where vrsave was saved to. */
1902 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1903 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1907 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1908 in a pair of insns to save the vector registers on the
1910 /* 001110 00000 00000 iiii iiii iiii iiii */
1911 /* 001110 01110 00000 iiii iiii iiii iiii */
1912 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
1913 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1915 if ((op
& 0xffff0000) == 0x38000000)
1916 r0_contains_arg
= 0;
1918 vr_saved_offset
= SIGNED_SHORT (op
);
1920 /* This insn by itself is not part of the prologue, unless
1921 if part of the pair of insns mentioned above. So do not
1922 record this insn as part of the prologue yet. */
1923 prev_insn_was_prologue_insn
= 0;
1925 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1926 /* 011111 sssss 11111 00000 00111001110 */
1927 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1929 if (pc
== (li_found_pc
+ 4))
1931 vr_reg
= GET_SRC_REG (op
);
1932 /* If this is the first vector reg to be saved, or if
1933 it has a lower number than others previously seen,
1934 reupdate the frame info. */
1935 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
1937 fdata
->saved_vr
= vr_reg
;
1938 fdata
->vr_offset
= vr_saved_offset
+ offset
;
1940 vr_saved_offset
= -1;
1945 /* End AltiVec related instructions. */
1947 /* Start BookE related instructions. */
1948 /* Store gen register S at (r31+uimm).
1949 Any register less than r13 is volatile, so we don't care. */
1950 /* 000100 sssss 11111 iiiii 01100100001 */
1951 else if (arch_info
->mach
== bfd_mach_ppc_e500
1952 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1954 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1957 ev_reg
= GET_SRC_REG (op
);
1958 imm
= (op
>> 11) & 0x1f;
1959 ev_offset
= imm
* 8;
1960 /* If this is the first vector reg to be saved, or if
1961 it has a lower number than others previously seen,
1962 reupdate the frame info. */
1963 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1965 fdata
->saved_ev
= ev_reg
;
1966 fdata
->ev_offset
= ev_offset
+ offset
;
1971 /* Store gen register rS at (r1+rB). */
1972 /* 000100 sssss 00001 bbbbb 01100100000 */
1973 else if (arch_info
->mach
== bfd_mach_ppc_e500
1974 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1976 if (pc
== (li_found_pc
+ 4))
1978 ev_reg
= GET_SRC_REG (op
);
1979 /* If this is the first vector reg to be saved, or if
1980 it has a lower number than others previously seen,
1981 reupdate the frame info. */
1982 /* We know the contents of rB from the previous instruction. */
1983 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
1985 fdata
->saved_ev
= ev_reg
;
1986 fdata
->ev_offset
= vr_saved_offset
+ offset
;
1988 vr_saved_offset
= -1;
1994 /* Store gen register r31 at (rA+uimm). */
1995 /* 000100 11111 aaaaa iiiii 01100100001 */
1996 else if (arch_info
->mach
== bfd_mach_ppc_e500
1997 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1999 /* Wwe know that the source register is 31 already, but
2000 it can't hurt to compute it. */
2001 ev_reg
= GET_SRC_REG (op
);
2002 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2003 /* If this is the first vector reg to be saved, or if
2004 it has a lower number than others previously seen,
2005 reupdate the frame info. */
2006 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2008 fdata
->saved_ev
= ev_reg
;
2009 fdata
->ev_offset
= ev_offset
+ offset
;
2014 /* Store gen register S at (r31+r0).
2015 Store param on stack when offset from SP bigger than 4 bytes. */
2016 /* 000100 sssss 11111 00000 01100100000 */
2017 else if (arch_info
->mach
== bfd_mach_ppc_e500
2018 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2020 if (pc
== (li_found_pc
+ 4))
2022 if ((op
& 0x03e00000) >= 0x01a00000)
2024 ev_reg
= GET_SRC_REG (op
);
2025 /* If this is the first vector reg to be saved, or if
2026 it has a lower number than others previously seen,
2027 reupdate the frame info. */
2028 /* We know the contents of r0 from the previous
2030 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2032 fdata
->saved_ev
= ev_reg
;
2033 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2037 vr_saved_offset
= -1;
2042 /* End BookE related instructions. */
2046 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2048 /* Not a recognized prologue instruction.
2049 Handle optimizer code motions into the prologue by continuing
2050 the search if we have no valid frame yet or if the return
2051 address is not yet saved in the frame. Also skip instructions
2052 if some of the GPRs expected to be saved are not yet saved. */
2053 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2054 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2057 if (op
== 0x4e800020 /* blr */
2058 || op
== 0x4e800420) /* bctr */
2059 /* Do not scan past epilogue in frameless functions or
2062 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2063 /* Never skip branches. */
2066 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2067 /* Do not scan too many insns, scanning insns is expensive with
2071 /* Continue scanning. */
2072 prev_insn_was_prologue_insn
= 0;
2078 /* I have problems with skipping over __main() that I need to address
2079 * sometime. Previously, I used to use misc_function_vector which
2080 * didn't work as well as I wanted to be. -MGO */
2082 /* If the first thing after skipping a prolog is a branch to a function,
2083 this might be a call to an initializer in main(), introduced by gcc2.
2084 We'd like to skip over it as well. Fortunately, xlc does some extra
2085 work before calling a function right after a prologue, thus we can
2086 single out such gcc2 behaviour. */
2089 if ((op
& 0xfc000001) == 0x48000001)
2090 { /* bl foo, an initializer function? */
2091 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2093 if (op
== 0x4def7b82)
2094 { /* cror 0xf, 0xf, 0xf (nop) */
2096 /* Check and see if we are in main. If so, skip over this
2097 initializer function as well. */
2099 tmp
= find_pc_misc_function (pc
);
2101 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2107 if (pc
== lim_pc
&& lr_reg
>= 0)
2108 fdata
->lr_register
= lr_reg
;
2110 fdata
->offset
= -fdata
->offset
;
2111 return last_prologue_pc
;
2115 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2117 struct rs6000_framedata frame
;
2118 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2120 /* See if we can determine the end of the prologue via the symbol table.
2121 If so, then return either PC, or the PC after the prologue, whichever
2123 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2125 CORE_ADDR post_prologue_pc
2126 = skip_prologue_using_sal (gdbarch
, func_addr
);
2127 if (post_prologue_pc
!= 0)
2128 return max (pc
, post_prologue_pc
);
2131 /* Can't determine prologue from the symbol table, need to examine
2134 /* Find an upper limit on the function prologue using the debug
2135 information. If the debug information could not be used to provide
2136 that bound, then use an arbitrary large number as the upper bound. */
2137 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2139 limit_pc
= pc
+ 100; /* Magic. */
2141 /* Do not allow limit_pc to be past the function end, if we know
2142 where that end is... */
2143 if (func_end_addr
&& limit_pc
> func_end_addr
)
2144 limit_pc
= func_end_addr
;
2146 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2150 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2151 in the prologue of main().
2153 The function below examines the code pointed at by PC and checks to
2154 see if it corresponds to a call to __eabi. If so, it returns the
2155 address of the instruction following that call. Otherwise, it simply
2159 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2161 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2165 if (target_read_memory (pc
, buf
, 4))
2167 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2169 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2171 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2172 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2173 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2175 /* We check for ___eabi (three leading underscores) in addition
2176 to __eabi in case the GCC option "-fleading-underscore" was
2177 used to compile the program. */
2178 if (s
.minsym
!= NULL
2179 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2180 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2181 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2187 /* All the ABI's require 16 byte alignment. */
2189 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2191 return (addr
& -16);
2194 /* Return whether handle_inferior_event() should proceed through code
2195 starting at PC in function NAME when stepping.
2197 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2198 handle memory references that are too distant to fit in instructions
2199 generated by the compiler. For example, if 'foo' in the following
2204 is greater than 32767, the linker might replace the lwz with a branch to
2205 somewhere in @FIX1 that does the load in 2 instructions and then branches
2206 back to where execution should continue.
2208 GDB should silently step over @FIX code, just like AIX dbx does.
2209 Unfortunately, the linker uses the "b" instruction for the
2210 branches, meaning that the link register doesn't get set.
2211 Therefore, GDB's usual step_over_function () mechanism won't work.
2213 Instead, use the gdbarch_skip_trampoline_code and
2214 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2218 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2219 CORE_ADDR pc
, const char *name
)
2221 return name
&& !strncmp (name
, "@FIX", 4);
2224 /* Skip code that the user doesn't want to see when stepping:
2226 1. Indirect function calls use a piece of trampoline code to do context
2227 switching, i.e. to set the new TOC table. Skip such code if we are on
2228 its first instruction (as when we have single-stepped to here).
2230 2. Skip shared library trampoline code (which is different from
2231 indirect function call trampolines).
2233 3. Skip bigtoc fixup code.
2235 Result is desired PC to step until, or NULL if we are not in
2236 code that should be skipped. */
2239 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2241 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2242 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2243 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2244 unsigned int ii
, op
;
2246 CORE_ADDR solib_target_pc
;
2247 struct bound_minimal_symbol msymbol
;
2249 static unsigned trampoline_code
[] =
2251 0x800b0000, /* l r0,0x0(r11) */
2252 0x90410014, /* st r2,0x14(r1) */
2253 0x7c0903a6, /* mtctr r0 */
2254 0x804b0004, /* l r2,0x4(r11) */
2255 0x816b0008, /* l r11,0x8(r11) */
2256 0x4e800420, /* bctr */
2257 0x4e800020, /* br */
2261 /* Check for bigtoc fixup code. */
2262 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2264 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2265 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2267 /* Double-check that the third instruction from PC is relative "b". */
2268 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2269 if ((op
& 0xfc000003) == 0x48000000)
2271 /* Extract bits 6-29 as a signed 24-bit relative word address and
2272 add it to the containing PC. */
2273 rel
= ((int)(op
<< 6) >> 6);
2274 return pc
+ 8 + rel
;
2278 /* If pc is in a shared library trampoline, return its target. */
2279 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2280 if (solib_target_pc
)
2281 return solib_target_pc
;
2283 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2285 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2286 if (op
!= trampoline_code
[ii
])
2289 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2291 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2295 /* ISA-specific vector types. */
2297 static struct type
*
2298 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2300 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2302 if (!tdep
->ppc_builtin_type_vec64
)
2304 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2306 /* The type we're building is this: */
2308 union __gdb_builtin_type_vec64
2312 int32_t v2_int32
[2];
2313 int16_t v4_int16
[4];
2320 t
= arch_composite_type (gdbarch
,
2321 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2322 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2323 append_composite_type_field (t
, "v2_float",
2324 init_vector_type (bt
->builtin_float
, 2));
2325 append_composite_type_field (t
, "v2_int32",
2326 init_vector_type (bt
->builtin_int32
, 2));
2327 append_composite_type_field (t
, "v4_int16",
2328 init_vector_type (bt
->builtin_int16
, 4));
2329 append_composite_type_field (t
, "v8_int8",
2330 init_vector_type (bt
->builtin_int8
, 8));
2332 TYPE_VECTOR (t
) = 1;
2333 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2334 tdep
->ppc_builtin_type_vec64
= t
;
2337 return tdep
->ppc_builtin_type_vec64
;
2340 /* Vector 128 type. */
2342 static struct type
*
2343 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2345 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2347 if (!tdep
->ppc_builtin_type_vec128
)
2349 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2351 /* The type we're building is this
2353 type = union __ppc_builtin_type_vec128 {
2355 double v2_double[2];
2357 int32_t v4_int32[4];
2358 int16_t v8_int16[8];
2359 int8_t v16_int8[16];
2365 t
= arch_composite_type (gdbarch
,
2366 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2367 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2368 append_composite_type_field (t
, "v2_double",
2369 init_vector_type (bt
->builtin_double
, 2));
2370 append_composite_type_field (t
, "v4_float",
2371 init_vector_type (bt
->builtin_float
, 4));
2372 append_composite_type_field (t
, "v4_int32",
2373 init_vector_type (bt
->builtin_int32
, 4));
2374 append_composite_type_field (t
, "v8_int16",
2375 init_vector_type (bt
->builtin_int16
, 8));
2376 append_composite_type_field (t
, "v16_int8",
2377 init_vector_type (bt
->builtin_int8
, 16));
2379 TYPE_VECTOR (t
) = 1;
2380 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2381 tdep
->ppc_builtin_type_vec128
= t
;
2384 return tdep
->ppc_builtin_type_vec128
;
2387 /* Return the name of register number REGNO, or the empty string if it
2388 is an anonymous register. */
2391 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2393 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2395 /* The upper half "registers" have names in the XML description,
2396 but we present only the low GPRs and the full 64-bit registers
2398 if (tdep
->ppc_ev0_upper_regnum
>= 0
2399 && tdep
->ppc_ev0_upper_regnum
<= regno
2400 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2403 /* Hide the upper halves of the vs0~vs31 registers. */
2404 if (tdep
->ppc_vsr0_regnum
>= 0
2405 && tdep
->ppc_vsr0_upper_regnum
<= regno
2406 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2409 /* Check if the SPE pseudo registers are available. */
2410 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2412 static const char *const spe_regnames
[] = {
2413 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2414 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2415 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2416 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2418 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2421 /* Check if the decimal128 pseudo-registers are available. */
2422 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2424 static const char *const dfp128_regnames
[] = {
2425 "dl0", "dl1", "dl2", "dl3",
2426 "dl4", "dl5", "dl6", "dl7",
2427 "dl8", "dl9", "dl10", "dl11",
2428 "dl12", "dl13", "dl14", "dl15"
2430 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2433 /* Check if this is a VSX pseudo-register. */
2434 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2436 static const char *const vsx_regnames
[] = {
2437 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2438 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2439 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2440 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2441 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2442 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2443 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2444 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2445 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2447 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2450 /* Check if the this is a Extended FP pseudo-register. */
2451 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2453 static const char *const efpr_regnames
[] = {
2454 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2455 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2456 "f46", "f47", "f48", "f49", "f50", "f51",
2457 "f52", "f53", "f54", "f55", "f56", "f57",
2458 "f58", "f59", "f60", "f61", "f62", "f63"
2460 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2463 return tdesc_register_name (gdbarch
, regno
);
2466 /* Return the GDB type object for the "standard" data type of data in
2469 static struct type
*
2470 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2472 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2474 /* These are the only pseudo-registers we support. */
2475 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2476 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2477 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2478 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2480 /* These are the e500 pseudo-registers. */
2481 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2482 return rs6000_builtin_type_vec64 (gdbarch
);
2483 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2484 /* PPC decimal128 pseudo-registers. */
2485 return builtin_type (gdbarch
)->builtin_declong
;
2486 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2487 /* POWER7 VSX pseudo-registers. */
2488 return rs6000_builtin_type_vec128 (gdbarch
);
2490 /* POWER7 Extended FP pseudo-registers. */
2491 return builtin_type (gdbarch
)->builtin_double
;
2494 /* Is REGNUM a member of REGGROUP? */
2496 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2497 struct reggroup
*group
)
2499 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2501 /* These are the only pseudo-registers we support. */
2502 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2503 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2504 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2505 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2507 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2508 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2509 return group
== all_reggroup
|| group
== vector_reggroup
;
2511 /* PPC decimal128 or Extended FP pseudo-registers. */
2512 return group
== all_reggroup
|| group
== float_reggroup
;
2515 /* The register format for RS/6000 floating point registers is always
2516 double, we need a conversion if the memory format is float. */
2519 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2522 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2524 return (tdep
->ppc_fp0_regnum
>= 0
2525 && regnum
>= tdep
->ppc_fp0_regnum
2526 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2527 && TYPE_CODE (type
) == TYPE_CODE_FLT
2528 && TYPE_LENGTH (type
)
2529 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2533 rs6000_register_to_value (struct frame_info
*frame
,
2537 int *optimizedp
, int *unavailablep
)
2539 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2540 gdb_byte from
[MAX_REGISTER_SIZE
];
2542 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2544 if (!get_frame_register_bytes (frame
, regnum
, 0,
2545 register_size (gdbarch
, regnum
),
2546 from
, optimizedp
, unavailablep
))
2549 convert_typed_floating (from
, builtin_type (gdbarch
)->builtin_double
,
2551 *optimizedp
= *unavailablep
= 0;
2556 rs6000_value_to_register (struct frame_info
*frame
,
2559 const gdb_byte
*from
)
2561 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2562 gdb_byte to
[MAX_REGISTER_SIZE
];
2564 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2566 convert_typed_floating (from
, type
,
2567 to
, builtin_type (gdbarch
)->builtin_double
);
2568 put_frame_register (frame
, regnum
, to
);
2571 /* The type of a function that moves the value of REG between CACHE
2572 or BUF --- in either direction. */
2573 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2576 /* Move SPE vector register values between a 64-bit buffer and the two
2577 32-bit raw register halves in a regcache. This function handles
2578 both splitting a 64-bit value into two 32-bit halves, and joining
2579 two halves into a whole 64-bit value, depending on the function
2580 passed as the MOVE argument.
2582 EV_REG must be the number of an SPE evN vector register --- a
2583 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2586 Call MOVE once for each 32-bit half of that register, passing
2587 REGCACHE, the number of the raw register corresponding to that
2588 half, and the address of the appropriate half of BUFFER.
2590 For example, passing 'regcache_raw_read' as the MOVE function will
2591 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2592 'regcache_raw_supply' will supply the contents of BUFFER to the
2593 appropriate pair of raw registers in REGCACHE.
2595 You may need to cast away some 'const' qualifiers when passing
2596 MOVE, since this function can't tell at compile-time which of
2597 REGCACHE or BUFFER is acting as the source of the data. If C had
2598 co-variant type qualifiers, ... */
2600 static enum register_status
2601 e500_move_ev_register (move_ev_register_func move
,
2602 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2604 struct gdbarch
*arch
= get_regcache_arch (regcache
);
2605 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2607 gdb_byte
*byte_buffer
= buffer
;
2608 enum register_status status
;
2610 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2612 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2614 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2616 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2618 if (status
== REG_VALID
)
2619 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2624 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2625 if (status
== REG_VALID
)
2626 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2633 static enum register_status
2634 do_regcache_raw_read (struct regcache
*regcache
, int regnum
, void *buffer
)
2636 return regcache_raw_read (regcache
, regnum
, buffer
);
2639 static enum register_status
2640 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2642 regcache_raw_write (regcache
, regnum
, buffer
);
2647 static enum register_status
2648 e500_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2649 int reg_nr
, gdb_byte
*buffer
)
2651 return e500_move_ev_register (do_regcache_raw_read
, regcache
, reg_nr
, buffer
);
2655 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2656 int reg_nr
, const gdb_byte
*buffer
)
2658 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2659 reg_nr
, (void *) buffer
);
2662 /* Read method for DFP pseudo-registers. */
2663 static enum register_status
2664 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2665 int reg_nr
, gdb_byte
*buffer
)
2667 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2668 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2669 enum register_status status
;
2671 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2673 /* Read two FP registers to form a whole dl register. */
2674 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2675 2 * reg_index
, buffer
);
2676 if (status
== REG_VALID
)
2677 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2678 2 * reg_index
+ 1, buffer
+ 8);
2682 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2683 2 * reg_index
+ 1, buffer
);
2684 if (status
== REG_VALID
)
2685 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2686 2 * reg_index
, buffer
+ 8);
2692 /* Write method for DFP pseudo-registers. */
2694 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2695 int reg_nr
, const gdb_byte
*buffer
)
2697 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2698 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2700 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2702 /* Write each half of the dl register into a separate
2704 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2705 2 * reg_index
, buffer
);
2706 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2707 2 * reg_index
+ 1, buffer
+ 8);
2711 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2712 2 * reg_index
+ 1, buffer
);
2713 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2714 2 * reg_index
, buffer
+ 8);
2718 /* Read method for POWER7 VSX pseudo-registers. */
2719 static enum register_status
2720 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2721 int reg_nr
, gdb_byte
*buffer
)
2723 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2724 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2725 enum register_status status
;
2727 /* Read the portion that overlaps the VMX registers. */
2729 status
= regcache_raw_read (regcache
, tdep
->ppc_vr0_regnum
+
2730 reg_index
- 32, buffer
);
2732 /* Read the portion that overlaps the FPR registers. */
2733 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2735 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2737 if (status
== REG_VALID
)
2738 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2739 reg_index
, buffer
+ 8);
2743 status
= regcache_raw_read (regcache
, tdep
->ppc_fp0_regnum
+
2744 reg_index
, buffer
+ 8);
2745 if (status
== REG_VALID
)
2746 status
= regcache_raw_read (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2753 /* Write method for POWER7 VSX pseudo-registers. */
2755 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2756 int reg_nr
, const gdb_byte
*buffer
)
2758 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2759 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2761 /* Write the portion that overlaps the VMX registers. */
2763 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2764 reg_index
- 32, buffer
);
2766 /* Write the portion that overlaps the FPR registers. */
2767 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2769 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2771 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2772 reg_index
, buffer
+ 8);
2776 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2777 reg_index
, buffer
+ 8);
2778 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2783 /* Read method for POWER7 Extended FP pseudo-registers. */
2784 static enum register_status
2785 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2786 int reg_nr
, gdb_byte
*buffer
)
2788 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2789 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2790 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2792 /* Read the portion that overlaps the VMX register. */
2793 return regcache_raw_read_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2794 offset
, register_size (gdbarch
, reg_nr
),
2798 /* Write method for POWER7 Extended FP pseudo-registers. */
2800 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2801 int reg_nr
, const gdb_byte
*buffer
)
2803 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2804 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2805 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2807 /* Write the portion that overlaps the VMX register. */
2808 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2809 offset
, register_size (gdbarch
, reg_nr
),
2813 static enum register_status
2814 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2815 struct regcache
*regcache
,
2816 int reg_nr
, gdb_byte
*buffer
)
2818 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2819 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2821 gdb_assert (regcache_arch
== gdbarch
);
2823 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2824 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2825 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2826 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2827 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2828 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2829 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2830 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2832 internal_error (__FILE__
, __LINE__
,
2833 _("rs6000_pseudo_register_read: "
2834 "called on unexpected register '%s' (%d)"),
2835 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2839 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2840 struct regcache
*regcache
,
2841 int reg_nr
, const gdb_byte
*buffer
)
2843 struct gdbarch
*regcache_arch
= get_regcache_arch (regcache
);
2844 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2846 gdb_assert (regcache_arch
== gdbarch
);
2848 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2849 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2850 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2851 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2852 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2853 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2854 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2855 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2857 internal_error (__FILE__
, __LINE__
,
2858 _("rs6000_pseudo_register_write: "
2859 "called on unexpected register '%s' (%d)"),
2860 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2863 /* Convert a DBX STABS register number to a GDB register number. */
2865 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2867 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2869 if (0 <= num
&& num
<= 31)
2870 return tdep
->ppc_gp0_regnum
+ num
;
2871 else if (32 <= num
&& num
<= 63)
2872 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2873 specifies registers the architecture doesn't have? Our
2874 callers don't check the value we return. */
2875 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2876 else if (77 <= num
&& num
<= 108)
2877 return tdep
->ppc_vr0_regnum
+ (num
- 77);
2878 else if (1200 <= num
&& num
< 1200 + 32)
2879 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2884 return tdep
->ppc_mq_regnum
;
2886 return tdep
->ppc_lr_regnum
;
2888 return tdep
->ppc_ctr_regnum
;
2890 return tdep
->ppc_xer_regnum
;
2892 return tdep
->ppc_vrsave_regnum
;
2894 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2896 return tdep
->ppc_acc_regnum
;
2898 return tdep
->ppc_spefscr_regnum
;
2905 /* Convert a Dwarf 2 register number to a GDB register number. */
2907 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
2909 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2911 if (0 <= num
&& num
<= 31)
2912 return tdep
->ppc_gp0_regnum
+ num
;
2913 else if (32 <= num
&& num
<= 63)
2914 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2915 specifies registers the architecture doesn't have? Our
2916 callers don't check the value we return. */
2917 return tdep
->ppc_fp0_regnum
+ (num
- 32);
2918 else if (1124 <= num
&& num
< 1124 + 32)
2919 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
2920 else if (1200 <= num
&& num
< 1200 + 32)
2921 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
2926 return tdep
->ppc_cr_regnum
;
2928 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
2930 return tdep
->ppc_acc_regnum
;
2932 return tdep
->ppc_mq_regnum
;
2934 return tdep
->ppc_xer_regnum
;
2936 return tdep
->ppc_lr_regnum
;
2938 return tdep
->ppc_ctr_regnum
;
2940 return tdep
->ppc_vrsave_regnum
;
2942 return tdep
->ppc_spefscr_regnum
;
2948 /* Translate a .eh_frame register to DWARF register, or adjust a
2949 .debug_frame register. */
2952 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
2954 /* GCC releases before 3.4 use GCC internal register numbering in
2955 .debug_frame (and .debug_info, et cetera). The numbering is
2956 different from the standard SysV numbering for everything except
2957 for GPRs and FPRs. We can not detect this problem in most cases
2958 - to get accurate debug info for variables living in lr, ctr, v0,
2959 et cetera, use a newer version of GCC. But we must detect
2960 one important case - lr is in column 65 in .debug_frame output,
2963 GCC 3.4, and the "hammer" branch, have a related problem. They
2964 record lr register saves in .debug_frame as 108, but still record
2965 the return column as 65. We fix that up too.
2967 We can do this because 65 is assigned to fpsr, and GCC never
2968 generates debug info referring to it. To add support for
2969 handwritten debug info that restores fpsr, we would need to add a
2970 producer version check to this. */
2979 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2980 internal register numbering; translate that to the standard DWARF2
2981 register numbering. */
2982 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
2984 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
2985 return num
- 68 + 86;
2986 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
2987 return num
- 77 + 1124;
2999 case 109: /* vrsave */
3001 case 110: /* vscr */
3003 case 111: /* spe_acc */
3005 case 112: /* spefscr */
3013 /* Handling the various POWER/PowerPC variants. */
3015 /* Information about a particular processor variant. */
3019 /* Name of this variant. */
3022 /* English description of the variant. */
3025 /* bfd_arch_info.arch corresponding to variant. */
3026 enum bfd_architecture arch
;
3028 /* bfd_arch_info.mach corresponding to variant. */
3031 /* Target description for this variant. */
3032 struct target_desc
**tdesc
;
3035 static struct variant variants
[] =
3037 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3038 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3039 {"power", "POWER user-level", bfd_arch_rs6000
,
3040 bfd_mach_rs6k
, &tdesc_rs6000
},
3041 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3042 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3043 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3044 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3045 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3046 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3047 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3048 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3049 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3050 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3051 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3052 604, &tdesc_powerpc_604
},
3053 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3054 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3055 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3056 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3057 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3058 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3059 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3060 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3061 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3062 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3063 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3064 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3067 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3068 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3069 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3070 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3071 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3072 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3073 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3074 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3075 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3076 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3077 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3078 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3080 /* FIXME: I haven't checked the register sets of the following. */
3081 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3082 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3083 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3084 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3085 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3086 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3091 /* Return the variant corresponding to architecture ARCH and machine number
3092 MACH. If no such variant exists, return null. */
3094 static const struct variant
*
3095 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3097 const struct variant
*v
;
3099 for (v
= variants
; v
->name
; v
++)
3100 if (arch
== v
->arch
&& mach
== v
->mach
)
3107 gdb_print_insn_powerpc (bfd_vma memaddr
, disassemble_info
*info
)
3109 if (info
->endian
== BFD_ENDIAN_BIG
)
3110 return print_insn_big_powerpc (memaddr
, info
);
3112 return print_insn_little_powerpc (memaddr
, info
);
3116 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3118 return frame_unwind_register_unsigned (next_frame
,
3119 gdbarch_pc_regnum (gdbarch
));
3122 static struct frame_id
3123 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3125 return frame_id_build (get_frame_register_unsigned
3126 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3127 get_frame_pc (this_frame
));
3130 struct rs6000_frame_cache
3133 CORE_ADDR initial_sp
;
3134 struct trad_frame_saved_reg
*saved_regs
;
3137 static struct rs6000_frame_cache
*
3138 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3140 struct rs6000_frame_cache
*cache
;
3141 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3142 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3143 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3144 struct rs6000_framedata fdata
;
3145 int wordsize
= tdep
->wordsize
;
3148 if ((*this_cache
) != NULL
)
3149 return (*this_cache
);
3150 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3151 (*this_cache
) = cache
;
3152 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3154 func
= get_frame_func (this_frame
);
3155 pc
= get_frame_pc (this_frame
);
3156 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3158 /* Figure out the parent's stack pointer. */
3160 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3161 address of the current frame. Things might be easier if the
3162 ->frame pointed to the outer-most address of the frame. In
3163 the mean time, the address of the prev frame is used as the
3164 base address of this frame. */
3165 cache
->base
= get_frame_register_unsigned
3166 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3168 /* If the function appears to be frameless, check a couple of likely
3169 indicators that we have simply failed to find the frame setup.
3170 Two common cases of this are missing symbols (i.e.
3171 get_frame_func returns the wrong address or 0), and assembly
3172 stubs which have a fast exit path but set up a frame on the slow
3175 If the LR appears to return to this function, then presume that
3176 we have an ABI compliant frame that we failed to find. */
3177 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3182 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3183 if (func
== 0 && saved_lr
== pc
)
3187 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3188 if (func
== saved_func
)
3194 fdata
.frameless
= 0;
3195 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3199 if (!fdata
.frameless
)
3201 /* Frameless really means stackless. */
3204 if (safe_read_memory_integer (cache
->base
, wordsize
,
3205 byte_order
, &backchain
))
3206 cache
->base
= (CORE_ADDR
) backchain
;
3209 trad_frame_set_value (cache
->saved_regs
,
3210 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3212 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3213 All fpr's from saved_fpr to fp31 are saved. */
3215 if (fdata
.saved_fpr
>= 0)
3218 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3220 /* If skip_prologue says floating-point registers were saved,
3221 but the current architecture has no floating-point registers,
3222 then that's strange. But we have no indices to even record
3223 the addresses under, so we just ignore it. */
3224 if (ppc_floating_point_unit_p (gdbarch
))
3225 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3227 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3232 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3233 All gpr's from saved_gpr to gpr31 are saved (except during the
3236 if (fdata
.saved_gpr
>= 0)
3239 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3240 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3242 if (fdata
.gpr_mask
& (1U << i
))
3243 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3244 gpr_addr
+= wordsize
;
3248 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3249 All vr's from saved_vr to vr31 are saved. */
3250 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3252 if (fdata
.saved_vr
>= 0)
3255 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3256 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3258 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3259 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3264 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3265 All vr's from saved_ev to ev31 are saved. ????? */
3266 if (tdep
->ppc_ev0_regnum
!= -1)
3268 if (fdata
.saved_ev
>= 0)
3271 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3272 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3274 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3276 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3277 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3278 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3283 /* If != 0, fdata.cr_offset is the offset from the frame that
3285 if (fdata
.cr_offset
!= 0)
3286 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3287 = cache
->base
+ fdata
.cr_offset
;
3289 /* If != 0, fdata.lr_offset is the offset from the frame that
3291 if (fdata
.lr_offset
!= 0)
3292 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3293 = cache
->base
+ fdata
.lr_offset
;
3294 else if (fdata
.lr_register
!= -1)
3295 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3296 /* The PC is found in the link register. */
3297 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3298 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3300 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3301 holds the VRSAVE. */
3302 if (fdata
.vrsave_offset
!= 0)
3303 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3304 = cache
->base
+ fdata
.vrsave_offset
;
3306 if (fdata
.alloca_reg
< 0)
3307 /* If no alloca register used, then fi->frame is the value of the
3308 %sp for this frame, and it is good enough. */
3310 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3313 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3319 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3320 struct frame_id
*this_id
)
3322 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3324 /* This marks the outermost frame. */
3325 if (info
->base
== 0)
3328 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3331 static struct value
*
3332 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3333 void **this_cache
, int regnum
)
3335 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3337 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3340 static const struct frame_unwind rs6000_frame_unwind
=
3343 default_frame_unwind_stop_reason
,
3344 rs6000_frame_this_id
,
3345 rs6000_frame_prev_register
,
3347 default_frame_sniffer
3350 static struct rs6000_frame_cache
*
3351 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3353 volatile struct gdb_exception ex
;
3354 struct rs6000_frame_cache
*cache
;
3355 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3356 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3362 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3363 (*this_cache
) = cache
;
3364 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3366 TRY_CATCH (ex
, RETURN_MASK_ERROR
)
3368 /* At this point the stack looks as if we just entered the
3369 function, and the return address is stored in LR. */
3372 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3373 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3376 cache
->initial_sp
= sp
;
3378 trad_frame_set_value (cache
->saved_regs
,
3379 gdbarch_pc_regnum (gdbarch
), lr
);
3381 if (ex
.reason
< 0 && ex
.error
!= NOT_AVAILABLE_ERROR
)
3382 throw_exception (ex
);
3388 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3389 void **this_cache
, struct frame_id
*this_id
)
3392 struct rs6000_frame_cache
*info
=
3393 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3395 pc
= get_frame_func (this_frame
);
3396 if (info
->base
== 0)
3397 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3399 (*this_id
) = frame_id_build (info
->base
, pc
);
3402 static struct value
*
3403 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3404 void **this_cache
, int regnum
)
3406 struct rs6000_frame_cache
*info
=
3407 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3408 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3412 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3413 struct frame_info
*this_frame
,
3414 void **this_prologue_cache
)
3416 if (frame_relative_level (this_frame
) == 0)
3417 return rs6000_in_function_epilogue_frame_p (this_frame
,
3418 get_frame_arch (this_frame
),
3419 get_frame_pc (this_frame
));
3424 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3427 default_frame_unwind_stop_reason
,
3428 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3430 rs6000_epilogue_frame_sniffer
3435 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3437 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3439 return info
->initial_sp
;
3442 static const struct frame_base rs6000_frame_base
= {
3443 &rs6000_frame_unwind
,
3444 rs6000_frame_base_address
,
3445 rs6000_frame_base_address
,
3446 rs6000_frame_base_address
3449 static const struct frame_base
*
3450 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3452 return &rs6000_frame_base
;
3455 /* DWARF-2 frame support. Used to handle the detection of
3456 clobbered registers during function calls. */
3459 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3460 struct dwarf2_frame_state_reg
*reg
,
3461 struct frame_info
*this_frame
)
3463 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3465 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3466 non-volatile registers. We will use the same code for both. */
3468 /* Call-saved GP registers. */
3469 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3470 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3471 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3472 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3474 /* Call-clobbered GP registers. */
3475 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3476 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3477 || (regnum
== tdep
->ppc_gp0_regnum
))
3478 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3480 /* Deal with FP registers, if supported. */
3481 if (tdep
->ppc_fp0_regnum
>= 0)
3483 /* Call-saved FP registers. */
3484 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3485 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3486 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3488 /* Call-clobbered FP registers. */
3489 if ((regnum
>= tdep
->ppc_fp0_regnum
3490 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3491 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3494 /* Deal with ALTIVEC registers, if supported. */
3495 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3497 /* Call-saved Altivec registers. */
3498 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3499 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3500 || regnum
== tdep
->ppc_vrsave_regnum
)
3501 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3503 /* Call-clobbered Altivec registers. */
3504 if ((regnum
>= tdep
->ppc_vr0_regnum
3505 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3506 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3509 /* Handle PC register and Stack Pointer correctly. */
3510 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3511 reg
->how
= DWARF2_FRAME_REG_RA
;
3512 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3513 reg
->how
= DWARF2_FRAME_REG_CFA
;
3517 /* Return true if a .gnu_attributes section exists in BFD and it
3518 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3519 section exists in BFD and it indicates that SPE extensions are in
3520 use. Check the .gnu.attributes section first, as the binary might be
3521 compiled for SPE, but not actually using SPE instructions. */
3524 bfd_uses_spe_extensions (bfd
*abfd
)
3527 gdb_byte
*contents
= NULL
;
3537 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3538 could be using the SPE vector abi without actually using any spe
3539 bits whatsoever. But it's close enough for now. */
3540 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3541 Tag_GNU_Power_ABI_Vector
);
3542 if (vector_abi
== 3)
3546 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3550 size
= bfd_get_section_size (sect
);
3551 contents
= xmalloc (size
);
3552 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3558 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3564 char name[name_len rounded up to 4-byte alignment];
3565 char data[data_len];
3568 Technically, there's only supposed to be one such structure in a
3569 given apuinfo section, but the linker is not always vigilant about
3570 merging apuinfo sections from input files. Just go ahead and parse
3571 them all, exiting early when we discover the binary uses SPE
3574 It's not specified in what endianness the information in this
3575 section is stored. Assume that it's the endianness of the BFD. */
3579 unsigned int name_len
;
3580 unsigned int data_len
;
3583 /* If we can't read the first three fields, we're done. */
3587 name_len
= bfd_get_32 (abfd
, ptr
);
3588 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3589 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3590 type
= bfd_get_32 (abfd
, ptr
+ 8);
3593 /* The name must be "APUinfo\0". */
3595 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3599 /* The type must be 2. */
3603 /* The data is stored as a series of uint32. The upper half of
3604 each uint32 indicates the particular APU used and the lower
3605 half indicates the revision of that APU. We just care about
3608 /* Not 4-byte quantities. */
3614 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3615 unsigned int apu
= apuinfo
>> 16;
3619 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3621 if (apu
== 0x100 || apu
== 0x101)
3636 /* Initialize the current architecture based on INFO. If possible, re-use an
3637 architecture from ARCHES, which is a list of architectures already created
3638 during this debugging session.
3640 Called e.g. at program startup, when reading a core file, and when reading
3643 static struct gdbarch
*
3644 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3646 struct gdbarch
*gdbarch
;
3647 struct gdbarch_tdep
*tdep
;
3648 int wordsize
, from_xcoff_exec
, from_elf_exec
;
3649 enum bfd_architecture arch
;
3652 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
3654 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
3655 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
3656 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
3658 int tdesc_wordsize
= -1;
3659 const struct target_desc
*tdesc
= info
.target_desc
;
3660 struct tdesc_arch_data
*tdesc_data
= NULL
;
3661 int num_pseudoregs
= 0;
3664 /* INFO may refer to a binary that is not of the PowerPC architecture,
3665 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3666 In this case, we must not attempt to infer properties of the (PowerPC
3667 side) of the target system from properties of that executable. Trust
3668 the target description instead. */
3670 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
3671 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
3674 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3675 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
3677 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
3678 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
3680 /* Check word size. If INFO is from a binary file, infer it from
3681 that, else choose a likely default. */
3682 if (from_xcoff_exec
)
3684 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
3689 else if (from_elf_exec
)
3691 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
3696 else if (tdesc_has_registers (tdesc
))
3700 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
3701 wordsize
= info
.bfd_arch_info
->bits_per_word
/
3702 info
.bfd_arch_info
->bits_per_byte
;
3707 /* Get the architecture and machine from the BFD. */
3708 arch
= info
.bfd_arch_info
->arch
;
3709 mach
= info
.bfd_arch_info
->mach
;
3711 /* For e500 executables, the apuinfo section is of help here. Such
3712 section contains the identifier and revision number of each
3713 Application-specific Processing Unit that is present on the
3714 chip. The content of the section is determined by the assembler
3715 which looks at each instruction and determines which unit (and
3716 which version of it) can execute it. Grovel through the section
3717 looking for relevant e500 APUs. */
3719 if (bfd_uses_spe_extensions (info
.abfd
))
3721 arch
= info
.bfd_arch_info
->arch
;
3722 mach
= bfd_mach_ppc_e500
;
3723 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
3724 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
3727 /* Find a default target description which describes our register
3728 layout, if we do not already have one. */
3729 if (! tdesc_has_registers (tdesc
))
3731 const struct variant
*v
;
3733 /* Choose variant. */
3734 v
= find_variant_by_arch (arch
, mach
);
3741 gdb_assert (tdesc_has_registers (tdesc
));
3743 /* Check any target description for validity. */
3744 if (tdesc_has_registers (tdesc
))
3746 static const char *const gprs
[] = {
3747 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3748 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3749 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3750 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3752 const struct tdesc_feature
*feature
;
3754 static const char *const msr_names
[] = { "msr", "ps" };
3755 static const char *const cr_names
[] = { "cr", "cnd" };
3756 static const char *const ctr_names
[] = { "ctr", "cnt" };
3758 feature
= tdesc_find_feature (tdesc
,
3759 "org.gnu.gdb.power.core");
3760 if (feature
== NULL
)
3763 tdesc_data
= tdesc_data_alloc ();
3766 for (i
= 0; i
< ppc_num_gprs
; i
++)
3767 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
3768 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
3770 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
3772 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
3775 /* Allow alternate names for these registers, to accomodate GDB's
3777 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3778 PPC_MSR_REGNUM
, msr_names
);
3779 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3780 PPC_CR_REGNUM
, cr_names
);
3781 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
3782 PPC_CTR_REGNUM
, ctr_names
);
3786 tdesc_data_cleanup (tdesc_data
);
3790 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
3793 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
3795 wordsize
= tdesc_wordsize
;
3797 feature
= tdesc_find_feature (tdesc
,
3798 "org.gnu.gdb.power.fpu");
3799 if (feature
!= NULL
)
3801 static const char *const fprs
[] = {
3802 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3803 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3804 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3805 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3808 for (i
= 0; i
< ppc_num_fprs
; i
++)
3809 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3810 PPC_F0_REGNUM
+ i
, fprs
[i
]);
3811 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3812 PPC_FPSCR_REGNUM
, "fpscr");
3816 tdesc_data_cleanup (tdesc_data
);
3824 /* The DFP pseudo-registers will be available when there are floating
3826 have_dfp
= have_fpu
;
3828 feature
= tdesc_find_feature (tdesc
,
3829 "org.gnu.gdb.power.altivec");
3830 if (feature
!= NULL
)
3832 static const char *const vector_regs
[] = {
3833 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3834 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3835 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3836 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3840 for (i
= 0; i
< ppc_num_gprs
; i
++)
3841 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3844 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3845 PPC_VSCR_REGNUM
, "vscr");
3846 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3847 PPC_VRSAVE_REGNUM
, "vrsave");
3849 if (have_spe
|| !valid_p
)
3851 tdesc_data_cleanup (tdesc_data
);
3859 /* Check for POWER7 VSX registers support. */
3860 feature
= tdesc_find_feature (tdesc
,
3861 "org.gnu.gdb.power.vsx");
3863 if (feature
!= NULL
)
3865 static const char *const vsx_regs
[] = {
3866 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3867 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3868 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3869 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3870 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3876 for (i
= 0; i
< ppc_num_vshrs
; i
++)
3877 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3878 PPC_VSR0_UPPER_REGNUM
+ i
,
3882 tdesc_data_cleanup (tdesc_data
);
3891 /* On machines supporting the SPE APU, the general-purpose registers
3892 are 64 bits long. There are SIMD vector instructions to treat them
3893 as pairs of floats, but the rest of the instruction set treats them
3894 as 32-bit registers, and only operates on their lower halves.
3896 In the GDB regcache, we treat their high and low halves as separate
3897 registers. The low halves we present as the general-purpose
3898 registers, and then we have pseudo-registers that stitch together
3899 the upper and lower halves and present them as pseudo-registers.
3901 Thus, the target description is expected to supply the upper
3902 halves separately. */
3904 feature
= tdesc_find_feature (tdesc
,
3905 "org.gnu.gdb.power.spe");
3906 if (feature
!= NULL
)
3908 static const char *const upper_spe
[] = {
3909 "ev0h", "ev1h", "ev2h", "ev3h",
3910 "ev4h", "ev5h", "ev6h", "ev7h",
3911 "ev8h", "ev9h", "ev10h", "ev11h",
3912 "ev12h", "ev13h", "ev14h", "ev15h",
3913 "ev16h", "ev17h", "ev18h", "ev19h",
3914 "ev20h", "ev21h", "ev22h", "ev23h",
3915 "ev24h", "ev25h", "ev26h", "ev27h",
3916 "ev28h", "ev29h", "ev30h", "ev31h"
3920 for (i
= 0; i
< ppc_num_gprs
; i
++)
3921 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3922 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
3924 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3925 PPC_SPE_ACC_REGNUM
, "acc");
3926 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
3927 PPC_SPE_FSCR_REGNUM
, "spefscr");
3929 if (have_mq
|| have_fpu
|| !valid_p
)
3931 tdesc_data_cleanup (tdesc_data
);
3940 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3941 complain for a 32-bit binary on a 64-bit target; we do not yet
3942 support that. For instance, the 32-bit ABI routines expect
3945 As long as there isn't an explicit target description, we'll
3946 choose one based on the BFD architecture and get a word size
3947 matching the binary (probably powerpc:common or
3948 powerpc:common64). So there is only trouble if a 64-bit target
3949 supplies a 64-bit description while debugging a 32-bit
3951 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
3953 tdesc_data_cleanup (tdesc_data
);
3960 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
3963 elf_abi
= POWERPC_ELF_V1
;
3966 elf_abi
= POWERPC_ELF_V2
;
3973 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
3975 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3976 Tag_GNU_Power_ABI_FP
))
3979 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
3982 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
3989 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
3991 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
3992 Tag_GNU_Power_ABI_Vector
))
3995 vector_abi
= POWERPC_VEC_GENERIC
;
3998 vector_abi
= POWERPC_VEC_ALTIVEC
;
4001 vector_abi
= POWERPC_VEC_SPE
;
4009 /* At this point, the only supported ELF-based 64-bit little-endian
4010 operating system is GNU/Linux, and this uses the ELFv2 ABI by
4011 default. All other supported ELF-based operating systems use the
4012 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
4013 e.g. because we run a legacy binary, or have attached to a process
4014 and have not found any associated binary file, set the default
4015 according to this heuristic. */
4016 if (elf_abi
== POWERPC_ELF_AUTO
)
4018 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
4019 elf_abi
= POWERPC_ELF_V2
;
4021 elf_abi
= POWERPC_ELF_V1
;
4024 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
4026 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
4029 soft_float
= !have_fpu
;
4031 /* If we have a hard float binary or setting but no floating point
4032 registers, downgrade to soft float anyway. We're still somewhat
4033 useful in this scenario. */
4034 if (!soft_float
&& !have_fpu
)
4037 /* Similarly for vector registers. */
4038 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
4039 vector_abi
= POWERPC_VEC_GENERIC
;
4041 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
4042 vector_abi
= POWERPC_VEC_GENERIC
;
4044 if (vector_abi
== POWERPC_VEC_AUTO
)
4047 vector_abi
= POWERPC_VEC_ALTIVEC
;
4049 vector_abi
= POWERPC_VEC_SPE
;
4051 vector_abi
= POWERPC_VEC_GENERIC
;
4054 /* Do not limit the vector ABI based on available hardware, since we
4055 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
4057 /* Find a candidate among extant architectures. */
4058 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4060 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
4062 /* Word size in the various PowerPC bfd_arch_info structs isn't
4063 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
4064 separate word size check. */
4065 tdep
= gdbarch_tdep (arches
->gdbarch
);
4066 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
4068 if (tdep
&& tdep
->soft_float
!= soft_float
)
4070 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
4072 if (tdep
&& tdep
->wordsize
== wordsize
)
4074 if (tdesc_data
!= NULL
)
4075 tdesc_data_cleanup (tdesc_data
);
4076 return arches
->gdbarch
;
4080 /* None found, create a new architecture from INFO, whose bfd_arch_info
4081 validity depends on the source:
4082 - executable useless
4083 - rs6000_host_arch() good
4085 - "set arch" trust blindly
4086 - GDB startup useless but harmless */
4088 tdep
= XCNEW (struct gdbarch_tdep
);
4089 tdep
->wordsize
= wordsize
;
4090 tdep
->elf_abi
= elf_abi
;
4091 tdep
->soft_float
= soft_float
;
4092 tdep
->vector_abi
= vector_abi
;
4094 gdbarch
= gdbarch_alloc (&info
, tdep
);
4096 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
4097 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
4098 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
4099 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
4100 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
4101 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
4102 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
4103 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
4105 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
4106 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
4107 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
4108 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
4109 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
4110 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
4111 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
4112 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
4114 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
4115 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
4116 set_gdbarch_deprecated_fp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
4117 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
4118 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
4120 /* The XML specification for PowerPC sensibly calls the MSR "msr".
4121 GDB traditionally called it "ps", though, so let GDB add an
4123 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
4126 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
4128 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
4130 /* Set lr_frame_offset. */
4132 tdep
->lr_frame_offset
= 16;
4134 tdep
->lr_frame_offset
= 4;
4136 if (have_spe
|| have_dfp
|| have_vsx
)
4138 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
4139 set_gdbarch_pseudo_register_write (gdbarch
,
4140 rs6000_pseudo_register_write
);
4143 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
4145 /* Select instruction printer. */
4146 if (arch
== bfd_arch_rs6000
)
4147 set_gdbarch_print_insn (gdbarch
, print_insn_rs6000
);
4149 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_powerpc
);
4151 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
4154 num_pseudoregs
+= 32;
4156 num_pseudoregs
+= 16;
4158 /* Include both VSX and Extended FP registers. */
4159 num_pseudoregs
+= 96;
4161 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
4163 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
4164 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
4165 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4166 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
4167 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4168 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4169 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4170 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
4171 set_gdbarch_char_signed (gdbarch
, 0);
4173 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
4176 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
4178 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
4179 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
4180 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
4182 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
4183 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
4186 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
4187 else if (wordsize
== 8)
4188 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
4190 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
4191 set_gdbarch_in_function_epilogue_p (gdbarch
, rs6000_in_function_epilogue_p
);
4192 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
4194 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4195 set_gdbarch_breakpoint_from_pc (gdbarch
, rs6000_breakpoint_from_pc
);
4197 /* The value of symbols of type N_SO and N_FUN maybe null when
4199 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
4201 /* Handles single stepping of atomic sequences. */
4202 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
4204 /* Not sure on this. FIXMEmgo */
4205 set_gdbarch_frame_args_skip (gdbarch
, 8);
4207 /* Helpers for function argument information. */
4208 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
4211 set_gdbarch_in_solib_return_trampoline
4212 (gdbarch
, rs6000_in_solib_return_trampoline
);
4213 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
4215 /* Hook in the DWARF CFI frame unwinder. */
4216 dwarf2_append_unwinders (gdbarch
);
4217 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
4219 /* Frame handling. */
4220 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
4222 /* Setup displaced stepping. */
4223 set_gdbarch_displaced_step_copy_insn (gdbarch
,
4224 simple_displaced_step_copy_insn
);
4225 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
4226 ppc_displaced_step_hw_singlestep
);
4227 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
4228 set_gdbarch_displaced_step_free_closure (gdbarch
,
4229 simple_displaced_step_free_closure
);
4230 set_gdbarch_displaced_step_location (gdbarch
,
4231 displaced_step_at_entry_point
);
4233 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
4235 /* Hook in ABI-specific overrides, if they have been registered. */
4236 info
.target_desc
= tdesc
;
4237 info
.tdep_info
= (void *) tdesc_data
;
4238 gdbarch_init_osabi (info
, gdbarch
);
4242 case GDB_OSABI_LINUX
:
4243 case GDB_OSABI_NETBSD_AOUT
:
4244 case GDB_OSABI_NETBSD_ELF
:
4245 case GDB_OSABI_UNKNOWN
:
4246 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
4247 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
4248 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
4249 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
4250 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
4253 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
4255 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
4256 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
4257 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
4258 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
4259 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
4262 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
4263 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
4264 rs6000_pseudo_register_reggroup_p
);
4265 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
4267 /* Override the normal target description method to make the SPE upper
4268 halves anonymous. */
4269 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
4271 /* Choose register numbers for all supported pseudo-registers. */
4272 tdep
->ppc_ev0_regnum
= -1;
4273 tdep
->ppc_dl0_regnum
= -1;
4274 tdep
->ppc_vsr0_regnum
= -1;
4275 tdep
->ppc_efpr0_regnum
= -1;
4277 cur_reg
= gdbarch_num_regs (gdbarch
);
4281 tdep
->ppc_ev0_regnum
= cur_reg
;
4286 tdep
->ppc_dl0_regnum
= cur_reg
;
4291 tdep
->ppc_vsr0_regnum
= cur_reg
;
4293 tdep
->ppc_efpr0_regnum
= cur_reg
;
4297 gdb_assert (gdbarch_num_regs (gdbarch
)
4298 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
4300 /* Register the ravenscar_arch_ops. */
4301 if (mach
== bfd_mach_ppc_e500
)
4302 register_e500_ravenscar_ops (gdbarch
);
4304 register_ppc_ravenscar_ops (gdbarch
);
4310 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
4312 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4317 /* FIXME: Dump gdbarch_tdep. */
4320 /* PowerPC-specific commands. */
4323 set_powerpc_command (char *args
, int from_tty
)
4325 printf_unfiltered (_("\
4326 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
4327 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
4331 show_powerpc_command (char *args
, int from_tty
)
4333 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
4337 powerpc_set_soft_float (char *args
, int from_tty
,
4338 struct cmd_list_element
*c
)
4340 struct gdbarch_info info
;
4342 /* Update the architecture. */
4343 gdbarch_info_init (&info
);
4344 if (!gdbarch_update_p (info
))
4345 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
4349 powerpc_set_vector_abi (char *args
, int from_tty
,
4350 struct cmd_list_element
*c
)
4352 struct gdbarch_info info
;
4353 enum powerpc_vector_abi vector_abi
;
4355 for (vector_abi
= POWERPC_VEC_AUTO
;
4356 vector_abi
!= POWERPC_VEC_LAST
;
4358 if (strcmp (powerpc_vector_abi_string
,
4359 powerpc_vector_strings
[vector_abi
]) == 0)
4361 powerpc_vector_abi_global
= vector_abi
;
4365 if (vector_abi
== POWERPC_VEC_LAST
)
4366 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
4367 powerpc_vector_abi_string
);
4369 /* Update the architecture. */
4370 gdbarch_info_init (&info
);
4371 if (!gdbarch_update_p (info
))
4372 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
4375 /* Show the current setting of the exact watchpoints flag. */
4378 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
4379 struct cmd_list_element
*c
,
4382 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
4385 /* Read a PPC instruction from memory. */
4388 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
4390 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4391 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4393 return read_memory_unsigned_integer (pc
, 4, byte_order
);
4396 /* Return non-zero if the instructions at PC match the series
4397 described in PATTERN, or zero otherwise. PATTERN is an array of
4398 'struct ppc_insn_pattern' objects, terminated by an entry whose
4401 When the match is successful, fill INSN[i] with what PATTERN[i]
4402 matched. If PATTERN[i] is optional, and the instruction wasn't
4403 present, set INSN[i] to 0 (which is not a valid PPC instruction).
4404 INSN should have as many elements as PATTERN. Note that, if
4405 PATTERN contains optional instructions which aren't present in
4406 memory, then INSN will have holes, so INSN[i] isn't necessarily the
4407 i'th instruction in memory. */
4410 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
4411 struct ppc_insn_pattern
*pattern
,
4412 unsigned int *insns
)
4417 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
4420 insn
= read_insn (frame
, pc
);
4422 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
4428 else if (!pattern
[i
].optional
)
4435 /* Return the 'd' field of the d-form instruction INSN, properly
4439 ppc_insn_d_field (unsigned int insn
)
4441 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
4444 /* Return the 'ds' field of the ds-form instruction INSN, with the two
4445 zero bits concatenated at the right, and properly
4449 ppc_insn_ds_field (unsigned int insn
)
4451 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
4454 /* Initialization code. */
4456 /* -Wmissing-prototypes */
4457 extern initialize_file_ftype _initialize_rs6000_tdep
;
4460 _initialize_rs6000_tdep (void)
4462 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
4463 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
4465 /* Initialize the standard target descriptions. */
4466 initialize_tdesc_powerpc_32 ();
4467 initialize_tdesc_powerpc_altivec32 ();
4468 initialize_tdesc_powerpc_vsx32 ();
4469 initialize_tdesc_powerpc_403 ();
4470 initialize_tdesc_powerpc_403gc ();
4471 initialize_tdesc_powerpc_405 ();
4472 initialize_tdesc_powerpc_505 ();
4473 initialize_tdesc_powerpc_601 ();
4474 initialize_tdesc_powerpc_602 ();
4475 initialize_tdesc_powerpc_603 ();
4476 initialize_tdesc_powerpc_604 ();
4477 initialize_tdesc_powerpc_64 ();
4478 initialize_tdesc_powerpc_altivec64 ();
4479 initialize_tdesc_powerpc_vsx64 ();
4480 initialize_tdesc_powerpc_7400 ();
4481 initialize_tdesc_powerpc_750 ();
4482 initialize_tdesc_powerpc_860 ();
4483 initialize_tdesc_powerpc_e500 ();
4484 initialize_tdesc_rs6000 ();
4486 /* Add root prefix command for all "set powerpc"/"show powerpc"
4488 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
4489 _("Various PowerPC-specific commands."),
4490 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
4492 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
4493 _("Various PowerPC-specific commands."),
4494 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
4496 /* Add a command to allow the user to force the ABI. */
4497 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
4498 &powerpc_soft_float_global
,
4499 _("Set whether to use a soft-float ABI."),
4500 _("Show whether to use a soft-float ABI."),
4502 powerpc_set_soft_float
, NULL
,
4503 &setpowerpccmdlist
, &showpowerpccmdlist
);
4505 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
4506 &powerpc_vector_abi_string
,
4507 _("Set the vector ABI."),
4508 _("Show the vector ABI."),
4509 NULL
, powerpc_set_vector_abi
, NULL
,
4510 &setpowerpccmdlist
, &showpowerpccmdlist
);
4512 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
4513 &target_exact_watchpoints
,
4515 Set whether to use just one debug register for watchpoints on scalars."),
4517 Show whether to use just one debug register for watchpoints on scalars."),
4519 If true, GDB will use only one debug register when watching a variable of\n\
4520 scalar type, thus assuming that the variable is accessed through the address\n\
4521 of its first byte."),
4522 NULL
, show_powerpc_exact_watchpoints
,
4523 &setpowerpccmdlist
, &showpowerpccmdlist
);