1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* Holds the current set of options to be passed to the disassembler. */
110 static char *powerpc_disassembler_options
;
112 /* The list of available "set powerpc ..." and "show powerpc ..."
114 static struct cmd_list_element
*setpowerpccmdlist
= NULL
;
115 static struct cmd_list_element
*showpowerpccmdlist
= NULL
;
117 static enum auto_boolean powerpc_soft_float_global
= AUTO_BOOLEAN_AUTO
;
119 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
120 static const char *const powerpc_vector_strings
[] =
129 /* A variable that can be configured by the user. */
130 static enum powerpc_vector_abi powerpc_vector_abi_global
= POWERPC_VEC_AUTO
;
131 static const char *powerpc_vector_abi_string
= "auto";
133 /* To be used by skip_prologue. */
135 struct rs6000_framedata
137 int offset
; /* total size of frame --- the distance
138 by which we decrement sp to allocate
140 int saved_gpr
; /* smallest # of saved gpr */
141 unsigned int gpr_mask
; /* Each bit is an individual saved GPR. */
142 int saved_fpr
; /* smallest # of saved fpr */
143 int saved_vr
; /* smallest # of saved vr */
144 int saved_ev
; /* smallest # of saved ev */
145 int alloca_reg
; /* alloca register number (frame ptr) */
146 char frameless
; /* true if frameless functions. */
147 char nosavedpc
; /* true if pc not saved. */
148 char used_bl
; /* true if link register clobbered */
149 int gpr_offset
; /* offset of saved gprs from prev sp */
150 int fpr_offset
; /* offset of saved fprs from prev sp */
151 int vr_offset
; /* offset of saved vrs from prev sp */
152 int ev_offset
; /* offset of saved evs from prev sp */
153 int lr_offset
; /* offset of saved lr */
154 int lr_register
; /* register of saved lr, if trustworthy */
155 int cr_offset
; /* offset of saved cr */
156 int vrsave_offset
; /* offset of saved vrsave register */
160 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
162 vsx_register_p (struct gdbarch
*gdbarch
, int regno
)
164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
165 if (tdep
->ppc_vsr0_regnum
< 0)
168 return (regno
>= tdep
->ppc_vsr0_upper_regnum
&& regno
169 <= tdep
->ppc_vsr0_upper_regnum
+ 31);
172 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
174 altivec_register_p (struct gdbarch
*gdbarch
, int regno
)
176 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
177 if (tdep
->ppc_vr0_regnum
< 0 || tdep
->ppc_vrsave_regnum
< 0)
180 return (regno
>= tdep
->ppc_vr0_regnum
&& regno
<= tdep
->ppc_vrsave_regnum
);
184 /* Return true if REGNO is an SPE register, false otherwise. */
186 spe_register_p (struct gdbarch
*gdbarch
, int regno
)
188 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
190 /* Is it a reference to EV0 -- EV31, and do we have those? */
191 if (IS_SPE_PSEUDOREG (tdep
, regno
))
194 /* Is it a reference to one of the raw upper GPR halves? */
195 if (tdep
->ppc_ev0_upper_regnum
>= 0
196 && tdep
->ppc_ev0_upper_regnum
<= regno
197 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
200 /* Is it a reference to the 64-bit accumulator, and do we have that? */
201 if (tdep
->ppc_acc_regnum
>= 0
202 && tdep
->ppc_acc_regnum
== regno
)
205 /* Is it a reference to the SPE floating-point status and control register,
206 and do we have that? */
207 if (tdep
->ppc_spefscr_regnum
>= 0
208 && tdep
->ppc_spefscr_regnum
== regno
)
215 /* Return non-zero if the architecture described by GDBARCH has
216 floating-point registers (f0 --- f31 and fpscr). */
218 ppc_floating_point_unit_p (struct gdbarch
*gdbarch
)
220 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
222 return (tdep
->ppc_fp0_regnum
>= 0
223 && tdep
->ppc_fpscr_regnum
>= 0);
226 /* Return non-zero if the architecture described by GDBARCH has
227 VSX registers (vsr0 --- vsr63). */
229 ppc_vsx_support_p (struct gdbarch
*gdbarch
)
231 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
233 return tdep
->ppc_vsr0_regnum
>= 0;
236 /* Return non-zero if the architecture described by GDBARCH has
237 Altivec registers (vr0 --- vr31, vrsave and vscr). */
239 ppc_altivec_support_p (struct gdbarch
*gdbarch
)
241 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
243 return (tdep
->ppc_vr0_regnum
>= 0
244 && tdep
->ppc_vrsave_regnum
>= 0);
247 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
250 This is a helper function for init_sim_regno_table, constructing
251 the table mapping GDB register numbers to sim register numbers; we
252 initialize every element in that table to -1 before we start
255 set_sim_regno (int *table
, int gdb_regno
, int sim_regno
)
257 /* Make sure we don't try to assign any given GDB register a sim
258 register number more than once. */
259 gdb_assert (table
[gdb_regno
] == -1);
260 table
[gdb_regno
] = sim_regno
;
264 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
265 numbers to simulator register numbers, based on the values placed
266 in the ARCH->tdep->ppc_foo_regnum members. */
268 init_sim_regno_table (struct gdbarch
*arch
)
270 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
271 int total_regs
= gdbarch_num_regs (arch
);
272 int *sim_regno
= GDBARCH_OBSTACK_CALLOC (arch
, total_regs
, int);
274 static const char *const segment_regs
[] = {
275 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
276 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
279 /* Presume that all registers not explicitly mentioned below are
280 unavailable from the sim. */
281 for (i
= 0; i
< total_regs
; i
++)
284 /* General-purpose registers. */
285 for (i
= 0; i
< ppc_num_gprs
; i
++)
286 set_sim_regno (sim_regno
, tdep
->ppc_gp0_regnum
+ i
, sim_ppc_r0_regnum
+ i
);
288 /* Floating-point registers. */
289 if (tdep
->ppc_fp0_regnum
>= 0)
290 for (i
= 0; i
< ppc_num_fprs
; i
++)
291 set_sim_regno (sim_regno
,
292 tdep
->ppc_fp0_regnum
+ i
,
293 sim_ppc_f0_regnum
+ i
);
294 if (tdep
->ppc_fpscr_regnum
>= 0)
295 set_sim_regno (sim_regno
, tdep
->ppc_fpscr_regnum
, sim_ppc_fpscr_regnum
);
297 set_sim_regno (sim_regno
, gdbarch_pc_regnum (arch
), sim_ppc_pc_regnum
);
298 set_sim_regno (sim_regno
, tdep
->ppc_ps_regnum
, sim_ppc_ps_regnum
);
299 set_sim_regno (sim_regno
, tdep
->ppc_cr_regnum
, sim_ppc_cr_regnum
);
301 /* Segment registers. */
302 for (i
= 0; i
< ppc_num_srs
; i
++)
306 gdb_regno
= user_reg_map_name_to_regnum (arch
, segment_regs
[i
], -1);
308 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_sr0_regnum
+ i
);
311 /* Altivec registers. */
312 if (tdep
->ppc_vr0_regnum
>= 0)
314 for (i
= 0; i
< ppc_num_vrs
; i
++)
315 set_sim_regno (sim_regno
,
316 tdep
->ppc_vr0_regnum
+ i
,
317 sim_ppc_vr0_regnum
+ i
);
319 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
320 we can treat this more like the other cases. */
321 set_sim_regno (sim_regno
,
322 tdep
->ppc_vr0_regnum
+ ppc_num_vrs
,
323 sim_ppc_vscr_regnum
);
325 /* vsave is a special-purpose register, so the code below handles it. */
327 /* SPE APU (E500) registers. */
328 if (tdep
->ppc_ev0_upper_regnum
>= 0)
329 for (i
= 0; i
< ppc_num_gprs
; i
++)
330 set_sim_regno (sim_regno
,
331 tdep
->ppc_ev0_upper_regnum
+ i
,
332 sim_ppc_rh0_regnum
+ i
);
333 if (tdep
->ppc_acc_regnum
>= 0)
334 set_sim_regno (sim_regno
, tdep
->ppc_acc_regnum
, sim_ppc_acc_regnum
);
335 /* spefscr is a special-purpose register, so the code below handles it. */
338 /* Now handle all special-purpose registers. Verify that they
339 haven't mistakenly been assigned numbers by any of the above
341 for (i
= 0; i
< sim_ppc_num_sprs
; i
++)
343 const char *spr_name
= sim_spr_register_name (i
);
346 if (spr_name
!= NULL
)
347 gdb_regno
= user_reg_map_name_to_regnum (arch
, spr_name
, -1);
350 set_sim_regno (sim_regno
, gdb_regno
, sim_ppc_spr0_regnum
+ i
);
354 /* Drop the initialized array into place. */
355 tdep
->sim_regno
= sim_regno
;
359 /* Given a GDB register number REG, return the corresponding SIM
362 rs6000_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
364 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
367 if (tdep
->sim_regno
== NULL
)
368 init_sim_regno_table (gdbarch
);
371 && reg
<= gdbarch_num_regs (gdbarch
)
372 + gdbarch_num_pseudo_regs (gdbarch
));
373 sim_regno
= tdep
->sim_regno
[reg
];
378 return LEGACY_SIM_REGNO_IGNORE
;
383 /* Register set support functions. */
385 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
386 Write the register to REGCACHE. */
389 ppc_supply_reg (struct regcache
*regcache
, int regnum
,
390 const gdb_byte
*regs
, size_t offset
, int regsize
)
392 if (regnum
!= -1 && offset
!= -1)
396 struct gdbarch
*gdbarch
= regcache
->arch ();
397 int gdb_regsize
= register_size (gdbarch
, regnum
);
398 if (gdb_regsize
< regsize
399 && gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
400 offset
+= regsize
- gdb_regsize
;
402 regcache_raw_supply (regcache
, regnum
, regs
+ offset
);
406 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
407 in a field REGSIZE wide. Zero pad as necessary. */
410 ppc_collect_reg (const struct regcache
*regcache
, int regnum
,
411 gdb_byte
*regs
, size_t offset
, int regsize
)
413 if (regnum
!= -1 && offset
!= -1)
417 struct gdbarch
*gdbarch
= regcache
->arch ();
418 int gdb_regsize
= register_size (gdbarch
, regnum
);
419 if (gdb_regsize
< regsize
)
421 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
423 memset (regs
+ offset
, 0, regsize
- gdb_regsize
);
424 offset
+= regsize
- gdb_regsize
;
427 memset (regs
+ offset
+ regsize
- gdb_regsize
, 0,
428 regsize
- gdb_regsize
);
431 regcache_raw_collect (regcache
, regnum
, regs
+ offset
);
436 ppc_greg_offset (struct gdbarch
*gdbarch
,
437 struct gdbarch_tdep
*tdep
,
438 const struct ppc_reg_offsets
*offsets
,
442 *regsize
= offsets
->gpr_size
;
443 if (regnum
>= tdep
->ppc_gp0_regnum
444 && regnum
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
)
445 return (offsets
->r0_offset
446 + (regnum
- tdep
->ppc_gp0_regnum
) * offsets
->gpr_size
);
448 if (regnum
== gdbarch_pc_regnum (gdbarch
))
449 return offsets
->pc_offset
;
451 if (regnum
== tdep
->ppc_ps_regnum
)
452 return offsets
->ps_offset
;
454 if (regnum
== tdep
->ppc_lr_regnum
)
455 return offsets
->lr_offset
;
457 if (regnum
== tdep
->ppc_ctr_regnum
)
458 return offsets
->ctr_offset
;
460 *regsize
= offsets
->xr_size
;
461 if (regnum
== tdep
->ppc_cr_regnum
)
462 return offsets
->cr_offset
;
464 if (regnum
== tdep
->ppc_xer_regnum
)
465 return offsets
->xer_offset
;
467 if (regnum
== tdep
->ppc_mq_regnum
)
468 return offsets
->mq_offset
;
474 ppc_fpreg_offset (struct gdbarch_tdep
*tdep
,
475 const struct ppc_reg_offsets
*offsets
,
478 if (regnum
>= tdep
->ppc_fp0_regnum
479 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
)
480 return offsets
->f0_offset
+ (regnum
- tdep
->ppc_fp0_regnum
) * 8;
482 if (regnum
== tdep
->ppc_fpscr_regnum
)
483 return offsets
->fpscr_offset
;
489 ppc_vrreg_offset (struct gdbarch_tdep
*tdep
,
490 const struct ppc_reg_offsets
*offsets
,
493 if (regnum
>= tdep
->ppc_vr0_regnum
494 && regnum
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
)
495 return offsets
->vr0_offset
+ (regnum
- tdep
->ppc_vr0_regnum
) * 16;
497 if (regnum
== tdep
->ppc_vrsave_regnum
- 1)
498 return offsets
->vscr_offset
;
500 if (regnum
== tdep
->ppc_vrsave_regnum
)
501 return offsets
->vrsave_offset
;
506 /* Supply register REGNUM in the general-purpose register set REGSET
507 from the buffer specified by GREGS and LEN to register cache
508 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
511 ppc_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
512 int regnum
, const void *gregs
, size_t len
)
514 struct gdbarch
*gdbarch
= regcache
->arch ();
515 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
516 const struct ppc_reg_offsets
*offsets
517 = (const struct ppc_reg_offsets
*) regset
->regmap
;
524 int gpr_size
= offsets
->gpr_size
;
526 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
527 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
528 i
++, offset
+= gpr_size
)
529 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) gregs
, offset
,
532 ppc_supply_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
533 (const gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
534 ppc_supply_reg (regcache
, tdep
->ppc_ps_regnum
,
535 (const gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
536 ppc_supply_reg (regcache
, tdep
->ppc_lr_regnum
,
537 (const gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
538 ppc_supply_reg (regcache
, tdep
->ppc_ctr_regnum
,
539 (const gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
540 ppc_supply_reg (regcache
, tdep
->ppc_cr_regnum
,
541 (const gdb_byte
*) gregs
, offsets
->cr_offset
,
543 ppc_supply_reg (regcache
, tdep
->ppc_xer_regnum
,
544 (const gdb_byte
*) gregs
, offsets
->xer_offset
,
546 ppc_supply_reg (regcache
, tdep
->ppc_mq_regnum
,
547 (const gdb_byte
*) gregs
, offsets
->mq_offset
,
552 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
553 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) gregs
, offset
, regsize
);
556 /* Supply register REGNUM in the floating-point register set REGSET
557 from the buffer specified by FPREGS and LEN to register cache
558 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
561 ppc_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
562 int regnum
, const void *fpregs
, size_t len
)
564 struct gdbarch
*gdbarch
= regcache
->arch ();
565 struct gdbarch_tdep
*tdep
;
566 const struct ppc_reg_offsets
*offsets
;
569 if (!ppc_floating_point_unit_p (gdbarch
))
572 tdep
= gdbarch_tdep (gdbarch
);
573 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
578 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
579 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
581 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) fpregs
, offset
, 8);
583 ppc_supply_reg (regcache
, tdep
->ppc_fpscr_regnum
,
584 (const gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
585 offsets
->fpscr_size
);
589 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
590 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) fpregs
, offset
,
591 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
594 /* Supply register REGNUM in the VSX register set REGSET
595 from the buffer specified by VSXREGS and LEN to register cache
596 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
599 ppc_supply_vsxregset (const struct regset
*regset
, struct regcache
*regcache
,
600 int regnum
, const void *vsxregs
, size_t len
)
602 struct gdbarch
*gdbarch
= regcache
->arch ();
603 struct gdbarch_tdep
*tdep
;
605 if (!ppc_vsx_support_p (gdbarch
))
608 tdep
= gdbarch_tdep (gdbarch
);
614 for (i
= tdep
->ppc_vsr0_upper_regnum
;
615 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
617 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vsxregs
, 0, 8);
622 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vsxregs
, 0, 8);
625 /* Supply register REGNUM in the Altivec register set REGSET
626 from the buffer specified by VRREGS and LEN to register cache
627 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
630 ppc_supply_vrregset (const struct regset
*regset
, struct regcache
*regcache
,
631 int regnum
, const void *vrregs
, size_t len
)
633 struct gdbarch
*gdbarch
= regcache
->arch ();
634 struct gdbarch_tdep
*tdep
;
635 const struct ppc_reg_offsets
*offsets
;
638 if (!ppc_altivec_support_p (gdbarch
))
641 tdep
= gdbarch_tdep (gdbarch
);
642 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
647 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
648 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
650 ppc_supply_reg (regcache
, i
, (const gdb_byte
*) vrregs
, offset
, 16);
652 ppc_supply_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
653 (const gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
655 ppc_supply_reg (regcache
, tdep
->ppc_vrsave_regnum
,
656 (const gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
660 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
661 if (regnum
!= tdep
->ppc_vrsave_regnum
662 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
663 ppc_supply_reg (regcache
, regnum
, (const gdb_byte
*) vrregs
, offset
, 16);
665 ppc_supply_reg (regcache
, regnum
,
666 (const gdb_byte
*) vrregs
, offset
, 4);
669 /* Collect register REGNUM in the general-purpose register set
670 REGSET from register cache REGCACHE into the buffer specified by
671 GREGS and LEN. If REGNUM is -1, do this for all registers in
675 ppc_collect_gregset (const struct regset
*regset
,
676 const struct regcache
*regcache
,
677 int regnum
, void *gregs
, size_t len
)
679 struct gdbarch
*gdbarch
= regcache
->arch ();
680 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
681 const struct ppc_reg_offsets
*offsets
682 = (const struct ppc_reg_offsets
*) regset
->regmap
;
689 int gpr_size
= offsets
->gpr_size
;
691 for (i
= tdep
->ppc_gp0_regnum
, offset
= offsets
->r0_offset
;
692 i
< tdep
->ppc_gp0_regnum
+ ppc_num_gprs
;
693 i
++, offset
+= gpr_size
)
694 ppc_collect_reg (regcache
, i
, (gdb_byte
*) gregs
, offset
, gpr_size
);
696 ppc_collect_reg (regcache
, gdbarch_pc_regnum (gdbarch
),
697 (gdb_byte
*) gregs
, offsets
->pc_offset
, gpr_size
);
698 ppc_collect_reg (regcache
, tdep
->ppc_ps_regnum
,
699 (gdb_byte
*) gregs
, offsets
->ps_offset
, gpr_size
);
700 ppc_collect_reg (regcache
, tdep
->ppc_lr_regnum
,
701 (gdb_byte
*) gregs
, offsets
->lr_offset
, gpr_size
);
702 ppc_collect_reg (regcache
, tdep
->ppc_ctr_regnum
,
703 (gdb_byte
*) gregs
, offsets
->ctr_offset
, gpr_size
);
704 ppc_collect_reg (regcache
, tdep
->ppc_cr_regnum
,
705 (gdb_byte
*) gregs
, offsets
->cr_offset
,
707 ppc_collect_reg (regcache
, tdep
->ppc_xer_regnum
,
708 (gdb_byte
*) gregs
, offsets
->xer_offset
,
710 ppc_collect_reg (regcache
, tdep
->ppc_mq_regnum
,
711 (gdb_byte
*) gregs
, offsets
->mq_offset
,
716 offset
= ppc_greg_offset (gdbarch
, tdep
, offsets
, regnum
, ®size
);
717 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) gregs
, offset
, regsize
);
720 /* Collect register REGNUM in the floating-point register set
721 REGSET from register cache REGCACHE into the buffer specified by
722 FPREGS and LEN. If REGNUM is -1, do this for all registers in
726 ppc_collect_fpregset (const struct regset
*regset
,
727 const struct regcache
*regcache
,
728 int regnum
, void *fpregs
, size_t len
)
730 struct gdbarch
*gdbarch
= regcache
->arch ();
731 struct gdbarch_tdep
*tdep
;
732 const struct ppc_reg_offsets
*offsets
;
735 if (!ppc_floating_point_unit_p (gdbarch
))
738 tdep
= gdbarch_tdep (gdbarch
);
739 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
744 for (i
= tdep
->ppc_fp0_regnum
, offset
= offsets
->f0_offset
;
745 i
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
;
747 ppc_collect_reg (regcache
, i
, (gdb_byte
*) fpregs
, offset
, 8);
749 ppc_collect_reg (regcache
, tdep
->ppc_fpscr_regnum
,
750 (gdb_byte
*) fpregs
, offsets
->fpscr_offset
,
751 offsets
->fpscr_size
);
755 offset
= ppc_fpreg_offset (tdep
, offsets
, regnum
);
756 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) fpregs
, offset
,
757 regnum
== tdep
->ppc_fpscr_regnum
? offsets
->fpscr_size
: 8);
760 /* Collect register REGNUM in the VSX register set
761 REGSET from register cache REGCACHE into the buffer specified by
762 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
766 ppc_collect_vsxregset (const struct regset
*regset
,
767 const struct regcache
*regcache
,
768 int regnum
, void *vsxregs
, size_t len
)
770 struct gdbarch
*gdbarch
= regcache
->arch ();
771 struct gdbarch_tdep
*tdep
;
773 if (!ppc_vsx_support_p (gdbarch
))
776 tdep
= gdbarch_tdep (gdbarch
);
782 for (i
= tdep
->ppc_vsr0_upper_regnum
;
783 i
< tdep
->ppc_vsr0_upper_regnum
+ 32;
785 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vsxregs
, 0, 8);
790 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vsxregs
, 0, 8);
794 /* Collect register REGNUM in the Altivec register set
795 REGSET from register cache REGCACHE into the buffer specified by
796 VRREGS and LEN. If REGNUM is -1, do this for all registers in
800 ppc_collect_vrregset (const struct regset
*regset
,
801 const struct regcache
*regcache
,
802 int regnum
, void *vrregs
, size_t len
)
804 struct gdbarch
*gdbarch
= regcache
->arch ();
805 struct gdbarch_tdep
*tdep
;
806 const struct ppc_reg_offsets
*offsets
;
809 if (!ppc_altivec_support_p (gdbarch
))
812 tdep
= gdbarch_tdep (gdbarch
);
813 offsets
= (const struct ppc_reg_offsets
*) regset
->regmap
;
818 for (i
= tdep
->ppc_vr0_regnum
, offset
= offsets
->vr0_offset
;
819 i
< tdep
->ppc_vr0_regnum
+ ppc_num_vrs
;
821 ppc_collect_reg (regcache
, i
, (gdb_byte
*) vrregs
, offset
, 16);
823 ppc_collect_reg (regcache
, (tdep
->ppc_vrsave_regnum
- 1),
824 (gdb_byte
*) vrregs
, offsets
->vscr_offset
, 4);
826 ppc_collect_reg (regcache
, tdep
->ppc_vrsave_regnum
,
827 (gdb_byte
*) vrregs
, offsets
->vrsave_offset
, 4);
831 offset
= ppc_vrreg_offset (tdep
, offsets
, regnum
);
832 if (regnum
!= tdep
->ppc_vrsave_regnum
833 && regnum
!= tdep
->ppc_vrsave_regnum
- 1)
834 ppc_collect_reg (regcache
, regnum
, (gdb_byte
*) vrregs
, offset
, 16);
836 ppc_collect_reg (regcache
, regnum
,
837 (gdb_byte
*) vrregs
, offset
, 4);
842 insn_changes_sp_or_jumps (unsigned long insn
)
844 int opcode
= (insn
>> 26) & 0x03f;
845 int sd
= (insn
>> 21) & 0x01f;
846 int a
= (insn
>> 16) & 0x01f;
847 int subcode
= (insn
>> 1) & 0x3ff;
849 /* Changes the stack pointer. */
851 /* NOTE: There are many ways to change the value of a given register.
852 The ways below are those used when the register is R1, the SP,
853 in a funtion's epilogue. */
855 if (opcode
== 31 && subcode
== 444 && a
== 1)
856 return 1; /* mr R1,Rn */
857 if (opcode
== 14 && sd
== 1)
858 return 1; /* addi R1,Rn,simm */
859 if (opcode
== 58 && sd
== 1)
860 return 1; /* ld R1,ds(Rn) */
862 /* Transfers control. */
868 if (opcode
== 19 && subcode
== 16)
870 if (opcode
== 19 && subcode
== 528)
871 return 1; /* bcctr */
876 /* Return true if we are in the function's epilogue, i.e. after the
877 instruction that destroyed the function's stack frame.
879 1) scan forward from the point of execution:
880 a) If you find an instruction that modifies the stack pointer
881 or transfers control (except a return), execution is not in
883 b) Stop scanning if you find a return instruction or reach the
884 end of the function or reach the hard limit for the size of
886 2) scan backward from the point of execution:
887 a) If you find an instruction that modifies the stack pointer,
888 execution *is* in an epilogue, return.
889 b) Stop scanning if you reach an instruction that transfers
890 control or the beginning of the function or reach the hard
891 limit for the size of an epilogue. */
894 rs6000_in_function_epilogue_frame_p (struct frame_info
*curfrm
,
895 struct gdbarch
*gdbarch
, CORE_ADDR pc
)
897 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
898 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
899 bfd_byte insn_buf
[PPC_INSN_SIZE
];
900 CORE_ADDR scan_pc
, func_start
, func_end
, epilogue_start
, epilogue_end
;
903 /* Find the search limits based on function boundaries and hard limit. */
905 if (!find_pc_partial_function (pc
, NULL
, &func_start
, &func_end
))
908 epilogue_start
= pc
- PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
909 if (epilogue_start
< func_start
) epilogue_start
= func_start
;
911 epilogue_end
= pc
+ PPC_MAX_EPILOGUE_INSTRUCTIONS
* PPC_INSN_SIZE
;
912 if (epilogue_end
> func_end
) epilogue_end
= func_end
;
914 /* Scan forward until next 'blr'. */
916 for (scan_pc
= pc
; scan_pc
< epilogue_end
; scan_pc
+= PPC_INSN_SIZE
)
918 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
920 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
921 if (insn
== 0x4e800020)
923 /* Assume a bctr is a tail call unless it points strictly within
925 if (insn
== 0x4e800420)
927 CORE_ADDR ctr
= get_frame_register_unsigned (curfrm
,
928 tdep
->ppc_ctr_regnum
);
929 if (ctr
> func_start
&& ctr
< func_end
)
934 if (insn_changes_sp_or_jumps (insn
))
938 /* Scan backward until adjustment to stack pointer (R1). */
940 for (scan_pc
= pc
- PPC_INSN_SIZE
;
941 scan_pc
>= epilogue_start
;
942 scan_pc
-= PPC_INSN_SIZE
)
944 if (!safe_frame_unwind_memory (curfrm
, scan_pc
, insn_buf
, PPC_INSN_SIZE
))
946 insn
= extract_unsigned_integer (insn_buf
, PPC_INSN_SIZE
, byte_order
);
947 if (insn_changes_sp_or_jumps (insn
))
954 /* Implement the stack_frame_destroyed_p gdbarch method. */
957 rs6000_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
959 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
963 /* Get the ith function argument for the current function. */
965 rs6000_fetch_pointer_argument (struct frame_info
*frame
, int argi
,
968 return get_frame_register_unsigned (frame
, 3 + argi
);
971 /* Sequence of bytes for breakpoint instruction. */
973 constexpr gdb_byte big_breakpoint
[] = { 0x7d, 0x82, 0x10, 0x08 };
974 constexpr gdb_byte little_breakpoint
[] = { 0x08, 0x10, 0x82, 0x7d };
976 typedef BP_MANIPULATION_ENDIAN (little_breakpoint
, big_breakpoint
)
979 /* Instruction masks for displaced stepping. */
980 #define BRANCH_MASK 0xfc000000
981 #define BP_MASK 0xFC0007FE
982 #define B_INSN 0x48000000
983 #define BC_INSN 0x40000000
984 #define BXL_INSN 0x4c000000
985 #define BP_INSN 0x7C000008
987 /* Instruction masks used during single-stepping of atomic
989 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
990 #define LWARX_INSTRUCTION 0x7c000028
991 #define LDARX_INSTRUCTION 0x7c0000A8
992 #define LBARX_INSTRUCTION 0x7c000068
993 #define LHARX_INSTRUCTION 0x7c0000e8
994 #define LQARX_INSTRUCTION 0x7c000228
995 #define STORE_CONDITIONAL_MASK 0xfc0007ff
996 #define STWCX_INSTRUCTION 0x7c00012d
997 #define STDCX_INSTRUCTION 0x7c0001ad
998 #define STBCX_INSTRUCTION 0x7c00056d
999 #define STHCX_INSTRUCTION 0x7c0005ad
1000 #define STQCX_INSTRUCTION 0x7c00016d
1002 /* Check if insn is one of the Load And Reserve instructions used for atomic
1004 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
1005 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
1006 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
1007 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
1008 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
1009 /* Check if insn is one of the Store Conditional instructions used for atomic
1011 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
1012 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
1013 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
1014 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
1015 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
1017 typedef buf_displaced_step_closure ppc_displaced_step_closure
;
1019 /* We can't displaced step atomic sequences. */
1021 static struct displaced_step_closure
*
1022 ppc_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1023 CORE_ADDR from
, CORE_ADDR to
,
1024 struct regcache
*regs
)
1026 size_t len
= gdbarch_max_insn_length (gdbarch
);
1027 std::unique_ptr
<ppc_displaced_step_closure
> closure
1028 (new ppc_displaced_step_closure (len
));
1029 gdb_byte
*buf
= closure
->buf
.data ();
1030 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1033 read_memory (from
, buf
, len
);
1035 insn
= extract_signed_integer (buf
, PPC_INSN_SIZE
, byte_order
);
1037 /* Assume all atomic sequences start with a Load and Reserve instruction. */
1038 if (IS_LOAD_AND_RESERVE_INSN (insn
))
1040 if (debug_displaced
)
1042 fprintf_unfiltered (gdb_stdlog
,
1043 "displaced: can't displaced step "
1044 "atomic sequence at %s\n",
1045 paddress (gdbarch
, from
));
1051 write_memory (to
, buf
, len
);
1053 if (debug_displaced
)
1055 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1056 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1057 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1060 return closure
.release ();
1063 /* Fix up the state of registers and memory after having single-stepped
1064 a displaced instruction. */
1066 ppc_displaced_step_fixup (struct gdbarch
*gdbarch
,
1067 struct displaced_step_closure
*closure_
,
1068 CORE_ADDR from
, CORE_ADDR to
,
1069 struct regcache
*regs
)
1071 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1072 /* Our closure is a copy of the instruction. */
1073 ppc_displaced_step_closure
*closure
= (ppc_displaced_step_closure
*) closure_
;
1074 ULONGEST insn
= extract_unsigned_integer (closure
->buf
.data (),
1075 PPC_INSN_SIZE
, byte_order
);
1076 ULONGEST opcode
= 0;
1077 /* Offset for non PC-relative instructions. */
1078 LONGEST offset
= PPC_INSN_SIZE
;
1080 opcode
= insn
& BRANCH_MASK
;
1082 if (debug_displaced
)
1083 fprintf_unfiltered (gdb_stdlog
,
1084 "displaced: (ppc) fixup (%s, %s)\n",
1085 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1088 /* Handle PC-relative branch instructions. */
1089 if (opcode
== B_INSN
|| opcode
== BC_INSN
|| opcode
== BXL_INSN
)
1091 ULONGEST current_pc
;
1093 /* Read the current PC value after the instruction has been executed
1094 in a displaced location. Calculate the offset to be applied to the
1095 original PC value before the displaced stepping. */
1096 regcache_cooked_read_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1098 offset
= current_pc
- to
;
1100 if (opcode
!= BXL_INSN
)
1102 /* Check for AA bit indicating whether this is an absolute
1103 addressing or PC-relative (1: absolute, 0: relative). */
1106 /* PC-relative addressing is being used in the branch. */
1107 if (debug_displaced
)
1110 "displaced: (ppc) branch instruction: %s\n"
1111 "displaced: (ppc) adjusted PC from %s to %s\n",
1112 paddress (gdbarch
, insn
), paddress (gdbarch
, current_pc
),
1113 paddress (gdbarch
, from
+ offset
));
1115 regcache_cooked_write_unsigned (regs
,
1116 gdbarch_pc_regnum (gdbarch
),
1122 /* If we're here, it means we have a branch to LR or CTR. If the
1123 branch was taken, the offset is probably greater than 4 (the next
1124 instruction), so it's safe to assume that an offset of 4 means we
1125 did not take the branch. */
1126 if (offset
== PPC_INSN_SIZE
)
1127 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1128 from
+ PPC_INSN_SIZE
);
1131 /* Check for LK bit indicating whether we should set the link
1132 register to point to the next instruction
1133 (1: Set, 0: Don't set). */
1136 /* Link register needs to be set to the next instruction's PC. */
1137 regcache_cooked_write_unsigned (regs
,
1138 gdbarch_tdep (gdbarch
)->ppc_lr_regnum
,
1139 from
+ PPC_INSN_SIZE
);
1140 if (debug_displaced
)
1141 fprintf_unfiltered (gdb_stdlog
,
1142 "displaced: (ppc) adjusted LR to %s\n",
1143 paddress (gdbarch
, from
+ PPC_INSN_SIZE
));
1147 /* Check for breakpoints in the inferior. If we've found one, place the PC
1148 right at the breakpoint instruction. */
1149 else if ((insn
& BP_MASK
) == BP_INSN
)
1150 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
), from
);
1152 /* Handle any other instructions that do not fit in the categories above. */
1153 regcache_cooked_write_unsigned (regs
, gdbarch_pc_regnum (gdbarch
),
1157 /* Always use hardware single-stepping to execute the
1158 displaced instruction. */
1160 ppc_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
,
1161 struct displaced_step_closure
*closure
)
1166 /* Checks for an atomic sequence of instructions beginning with a
1167 Load And Reserve instruction and ending with a Store Conditional
1168 instruction. If such a sequence is found, attempt to step through it.
1169 A breakpoint is placed at the end of the sequence. */
1170 std::vector
<CORE_ADDR
>
1171 ppc_deal_with_atomic_sequence (struct regcache
*regcache
)
1173 struct gdbarch
*gdbarch
= regcache
->arch ();
1174 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1175 CORE_ADDR pc
= regcache_read_pc (regcache
);
1176 CORE_ADDR breaks
[2] = {-1, -1};
1178 CORE_ADDR closing_insn
; /* Instruction that closes the atomic sequence. */
1179 int insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1182 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
1183 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
1184 int bc_insn_count
= 0; /* Conditional branch instruction count. */
1186 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1187 if (!IS_LOAD_AND_RESERVE_INSN (insn
))
1190 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1192 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
1194 loc
+= PPC_INSN_SIZE
;
1195 insn
= read_memory_integer (loc
, PPC_INSN_SIZE
, byte_order
);
1197 /* Assume that there is at most one conditional branch in the atomic
1198 sequence. If a conditional branch is found, put a breakpoint in
1199 its destination address. */
1200 if ((insn
& BRANCH_MASK
) == BC_INSN
)
1202 int immediate
= ((insn
& 0xfffc) ^ 0x8000) - 0x8000;
1203 int absolute
= insn
& 2;
1205 if (bc_insn_count
>= 1)
1206 return {}; /* More than one conditional branch found, fallback
1207 to the standard single-step code. */
1210 breaks
[1] = immediate
;
1212 breaks
[1] = loc
+ immediate
;
1218 if (IS_STORE_CONDITIONAL_INSN (insn
))
1222 /* Assume that the atomic sequence ends with a Store Conditional
1224 if (!IS_STORE_CONDITIONAL_INSN (insn
))
1228 loc
+= PPC_INSN_SIZE
;
1230 /* Insert a breakpoint right after the end of the atomic sequence. */
1233 /* Check for duplicated breakpoints. Check also for a breakpoint
1234 placed (branch instruction's destination) anywhere in sequence. */
1236 && (breaks
[1] == breaks
[0]
1237 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
1238 last_breakpoint
= 0;
1240 std::vector
<CORE_ADDR
> next_pcs
;
1242 for (index
= 0; index
<= last_breakpoint
; index
++)
1243 next_pcs
.push_back (breaks
[index
]);
1249 #define SIGNED_SHORT(x) \
1250 ((sizeof (short) == 2) \
1251 ? ((int)(short)(x)) \
1252 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1254 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1256 /* Limit the number of skipped non-prologue instructions, as the examining
1257 of the prologue is expensive. */
1258 static int max_skip_non_prologue_insns
= 10;
1260 /* Return nonzero if the given instruction OP can be part of the prologue
1261 of a function and saves a parameter on the stack. FRAMEP should be
1262 set if one of the previous instructions in the function has set the
1266 store_param_on_stack_p (unsigned long op
, int framep
, int *r0_contains_arg
)
1268 /* Move parameters from argument registers to temporary register. */
1269 if ((op
& 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1271 /* Rx must be scratch register r0. */
1272 const int rx_regno
= (op
>> 16) & 31;
1273 /* Ry: Only r3 - r10 are used for parameter passing. */
1274 const int ry_regno
= GET_SRC_REG (op
);
1276 if (rx_regno
== 0 && ry_regno
>= 3 && ry_regno
<= 10)
1278 *r0_contains_arg
= 1;
1285 /* Save a General Purpose Register on stack. */
1287 if ((op
& 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1288 (op
& 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1290 /* Rx: Only r3 - r10 are used for parameter passing. */
1291 const int rx_regno
= GET_SRC_REG (op
);
1293 return (rx_regno
>= 3 && rx_regno
<= 10);
1296 /* Save a General Purpose Register on stack via the Frame Pointer. */
1299 ((op
& 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1300 (op
& 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1301 (op
& 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1303 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1304 However, the compiler sometimes uses r0 to hold an argument. */
1305 const int rx_regno
= GET_SRC_REG (op
);
1307 return ((rx_regno
>= 3 && rx_regno
<= 10)
1308 || (rx_regno
== 0 && *r0_contains_arg
));
1311 if ((op
& 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1313 /* Only f2 - f8 are used for parameter passing. */
1314 const int src_regno
= GET_SRC_REG (op
);
1316 return (src_regno
>= 2 && src_regno
<= 8);
1319 if (framep
&& ((op
& 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1321 /* Only f2 - f8 are used for parameter passing. */
1322 const int src_regno
= GET_SRC_REG (op
);
1324 return (src_regno
>= 2 && src_regno
<= 8);
1327 /* Not an insn that saves a parameter on stack. */
1331 /* Assuming that INSN is a "bl" instruction located at PC, return
1332 nonzero if the destination of the branch is a "blrl" instruction.
1334 This sequence is sometimes found in certain function prologues.
1335 It allows the function to load the LR register with a value that
1336 they can use to access PIC data using PC-relative offsets. */
1339 bl_to_blrl_insn_p (CORE_ADDR pc
, int insn
, enum bfd_endian byte_order
)
1346 absolute
= (int) ((insn
>> 1) & 1);
1347 immediate
= ((insn
& ~3) << 6) >> 6;
1351 dest
= pc
+ immediate
;
1353 dest_insn
= read_memory_integer (dest
, 4, byte_order
);
1354 if ((dest_insn
& 0xfc00ffff) == 0x4c000021) /* blrl */
1360 /* Return true if OP is a stw or std instruction with
1361 register operands RS and RA and any immediate offset.
1363 If WITH_UPDATE is true, also return true if OP is
1364 a stwu or stdu instruction with the same operands.
1366 Return false otherwise.
1369 store_insn_p (unsigned long op
, unsigned long rs
,
1370 unsigned long ra
, bool with_update
)
1375 if (/* std RS, SIMM(RA) */
1376 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000000)) ||
1377 /* stw RS, SIMM(RA) */
1378 ((op
& 0xffff0000) == (rs
| ra
| 0x90000000)))
1383 if (/* stdu RS, SIMM(RA) */
1384 ((op
& 0xffff0003) == (rs
| ra
| 0xf8000001)) ||
1385 /* stwu RS, SIMM(RA) */
1386 ((op
& 0xffff0000) == (rs
| ra
| 0x94000000)))
1393 /* Masks for decoding a branch-and-link (bl) instruction.
1395 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1396 The former is anded with the opcode in question; if the result of
1397 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1398 question is a ``bl'' instruction.
1400 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1401 the branch displacement. */
1403 #define BL_MASK 0xfc000001
1404 #define BL_INSTRUCTION 0x48000001
1405 #define BL_DISPLACEMENT_MASK 0x03fffffc
1407 static unsigned long
1408 rs6000_fetch_instruction (struct gdbarch
*gdbarch
, const CORE_ADDR pc
)
1410 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1414 /* Fetch the instruction and convert it to an integer. */
1415 if (target_read_memory (pc
, buf
, 4))
1417 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1422 /* GCC generates several well-known sequences of instructions at the begining
1423 of each function prologue when compiling with -fstack-check. If one of
1424 such sequences starts at START_PC, then return the address of the
1425 instruction immediately past this sequence. Otherwise, return START_PC. */
1428 rs6000_skip_stack_check (struct gdbarch
*gdbarch
, const CORE_ADDR start_pc
)
1430 CORE_ADDR pc
= start_pc
;
1431 unsigned long op
= rs6000_fetch_instruction (gdbarch
, pc
);
1433 /* First possible sequence: A small number of probes.
1434 stw 0, -<some immediate>(1)
1435 [repeat this instruction any (small) number of times]. */
1437 if ((op
& 0xffff0000) == 0x90010000)
1439 while ((op
& 0xffff0000) == 0x90010000)
1442 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1447 /* Second sequence: A probing loop.
1448 addi 12,1,-<some immediate>
1449 lis 0,-<some immediate>
1450 [possibly ori 0,0,<some immediate>]
1454 addi 12,12,-<some immediate>
1457 [possibly one last probe: stw 0,<some immediate>(12)]. */
1461 /* addi 12,1,-<some immediate> */
1462 if ((op
& 0xffff0000) != 0x39810000)
1465 /* lis 0,-<some immediate> */
1467 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1468 if ((op
& 0xffff0000) != 0x3c000000)
1472 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1473 /* [possibly ori 0,0,<some immediate>] */
1474 if ((op
& 0xffff0000) == 0x60000000)
1477 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1480 if (op
!= 0x7c0c0214)
1485 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1486 if (op
!= 0x7c0c0000)
1491 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1492 if ((op
& 0xff9f0001) != 0x41820000)
1495 /* addi 12,12,-<some immediate> */
1497 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1498 if ((op
& 0xffff0000) != 0x398c0000)
1503 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1504 if (op
!= 0x900c0000)
1509 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1510 if ((op
& 0xfc000001) != 0x48000000)
1513 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1515 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1516 if ((op
& 0xffff0000) == 0x900c0000)
1519 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1522 /* We found a valid stack-check sequence, return the new PC. */
1526 /* Third sequence: No probe; instead, a comparizon between the stack size
1527 limit (saved in a run-time global variable) and the current stack
1530 addi 0,1,-<some immediate>
1531 lis 12,__gnat_stack_limit@ha
1532 lwz 12,__gnat_stack_limit@l(12)
1535 or, with a small variant in the case of a bigger stack frame:
1536 addis 0,1,<some immediate>
1537 addic 0,0,-<some immediate>
1538 lis 12,__gnat_stack_limit@ha
1539 lwz 12,__gnat_stack_limit@l(12)
1544 /* addi 0,1,-<some immediate> */
1545 if ((op
& 0xffff0000) != 0x38010000)
1547 /* small stack frame variant not recognized; try the
1548 big stack frame variant: */
1550 /* addis 0,1,<some immediate> */
1551 if ((op
& 0xffff0000) != 0x3c010000)
1554 /* addic 0,0,-<some immediate> */
1556 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1557 if ((op
& 0xffff0000) != 0x30000000)
1561 /* lis 12,<some immediate> */
1563 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1564 if ((op
& 0xffff0000) != 0x3d800000)
1567 /* lwz 12,<some immediate>(12) */
1569 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1570 if ((op
& 0xffff0000) != 0x818c0000)
1575 op
= rs6000_fetch_instruction (gdbarch
, pc
);
1576 if ((op
& 0xfffffffe) != 0x7c406008)
1579 /* We found a valid stack-check sequence, return the new PC. */
1583 /* No stack check code in our prologue, return the start_pc. */
1587 /* return pc value after skipping a function prologue and also return
1588 information about a function frame.
1590 in struct rs6000_framedata fdata:
1591 - frameless is TRUE, if function does not have a frame.
1592 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1593 - offset is the initial size of this stack frame --- the amount by
1594 which we decrement the sp to allocate the frame.
1595 - saved_gpr is the number of the first saved gpr.
1596 - saved_fpr is the number of the first saved fpr.
1597 - saved_vr is the number of the first saved vr.
1598 - saved_ev is the number of the first saved ev.
1599 - alloca_reg is the number of the register used for alloca() handling.
1601 - gpr_offset is the offset of the first saved gpr from the previous frame.
1602 - fpr_offset is the offset of the first saved fpr from the previous frame.
1603 - vr_offset is the offset of the first saved vr from the previous frame.
1604 - ev_offset is the offset of the first saved ev from the previous frame.
1605 - lr_offset is the offset of the saved lr
1606 - cr_offset is the offset of the saved cr
1607 - vrsave_offset is the offset of the saved vrsave register. */
1610 skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
, CORE_ADDR lim_pc
,
1611 struct rs6000_framedata
*fdata
)
1613 CORE_ADDR orig_pc
= pc
;
1614 CORE_ADDR last_prologue_pc
= pc
;
1615 CORE_ADDR li_found_pc
= 0;
1619 long alloca_reg_offset
= 0;
1620 long vr_saved_offset
= 0;
1626 int vrsave_reg
= -1;
1629 int minimal_toc_loaded
= 0;
1630 int prev_insn_was_prologue_insn
= 1;
1631 int num_skip_non_prologue_insns
= 0;
1632 int r0_contains_arg
= 0;
1633 const struct bfd_arch_info
*arch_info
= gdbarch_bfd_arch_info (gdbarch
);
1634 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1635 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1637 memset (fdata
, 0, sizeof (struct rs6000_framedata
));
1638 fdata
->saved_gpr
= -1;
1639 fdata
->saved_fpr
= -1;
1640 fdata
->saved_vr
= -1;
1641 fdata
->saved_ev
= -1;
1642 fdata
->alloca_reg
= -1;
1643 fdata
->frameless
= 1;
1644 fdata
->nosavedpc
= 1;
1645 fdata
->lr_register
= -1;
1647 pc
= rs6000_skip_stack_check (gdbarch
, pc
);
1653 /* Sometimes it isn't clear if an instruction is a prologue
1654 instruction or not. When we encounter one of these ambiguous
1655 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1656 Otherwise, we'll assume that it really is a prologue instruction. */
1657 if (prev_insn_was_prologue_insn
)
1658 last_prologue_pc
= pc
;
1660 /* Stop scanning if we've hit the limit. */
1664 prev_insn_was_prologue_insn
= 1;
1666 /* Fetch the instruction and convert it to an integer. */
1667 if (target_read_memory (pc
, buf
, 4))
1669 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1671 if ((op
& 0xfc1fffff) == 0x7c0802a6)
1673 /* Since shared library / PIC code, which needs to get its
1674 address at runtime, can appear to save more than one link
1688 remember just the first one, but skip over additional
1691 lr_reg
= (op
& 0x03e00000) >> 21;
1693 r0_contains_arg
= 0;
1696 else if ((op
& 0xfc1fffff) == 0x7c000026)
1698 cr_reg
= (op
& 0x03e00000) >> 21;
1700 r0_contains_arg
= 0;
1704 else if ((op
& 0xfc1f0000) == 0xd8010000)
1705 { /* stfd Rx,NUM(r1) */
1706 reg
= GET_SRC_REG (op
);
1707 if (fdata
->saved_fpr
== -1 || fdata
->saved_fpr
> reg
)
1709 fdata
->saved_fpr
= reg
;
1710 fdata
->fpr_offset
= SIGNED_SHORT (op
) + offset
;
1715 else if (((op
& 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1716 (((op
& 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1717 (op
& 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1718 (op
& 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1721 reg
= GET_SRC_REG (op
);
1722 if ((op
& 0xfc1f0000) == 0xbc010000)
1723 fdata
->gpr_mask
|= ~((1U << reg
) - 1);
1725 fdata
->gpr_mask
|= 1U << reg
;
1726 if (fdata
->saved_gpr
== -1 || fdata
->saved_gpr
> reg
)
1728 fdata
->saved_gpr
= reg
;
1729 if ((op
& 0xfc1f0003) == 0xf8010000)
1731 fdata
->gpr_offset
= SIGNED_SHORT (op
) + offset
;
1736 else if ((op
& 0xffff0000) == 0x3c4c0000
1737 || (op
& 0xffff0000) == 0x3c400000
1738 || (op
& 0xffff0000) == 0x38420000)
1740 /* . 0: addis 2,12,.TOC.-0b@ha
1741 . addi 2,2,.TOC.-0b@l
1745 used by ELFv2 global entry points to set up r2. */
1748 else if (op
== 0x60000000)
1751 /* Allow nops in the prologue, but do not consider them to
1752 be part of the prologue unless followed by other prologue
1754 prev_insn_was_prologue_insn
= 0;
1758 else if ((op
& 0xffff0000) == 0x3c000000)
1759 { /* addis 0,0,NUM, used for >= 32k frames */
1760 fdata
->offset
= (op
& 0x0000ffff) << 16;
1761 fdata
->frameless
= 0;
1762 r0_contains_arg
= 0;
1766 else if ((op
& 0xffff0000) == 0x60000000)
1767 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1768 fdata
->offset
|= (op
& 0x0000ffff);
1769 fdata
->frameless
= 0;
1770 r0_contains_arg
= 0;
1774 else if (lr_reg
>= 0 &&
1775 ((store_insn_p (op
, lr_reg
, 1, true)) ||
1777 (store_insn_p (op
, lr_reg
,
1778 fdata
->alloca_reg
- tdep
->ppc_gp0_regnum
,
1781 if (store_insn_p (op
, lr_reg
, 1, true))
1782 fdata
->lr_offset
= offset
;
1783 else /* LR save through frame pointer. */
1784 fdata
->lr_offset
= alloca_reg_offset
;
1786 fdata
->nosavedpc
= 0;
1787 /* Invalidate lr_reg, but don't set it to -1.
1788 That would mean that it had never been set. */
1790 if ((op
& 0xfc000003) == 0xf8000000 || /* std */
1791 (op
& 0xfc000000) == 0x90000000) /* stw */
1793 /* Does not update r1, so add displacement to lr_offset. */
1794 fdata
->lr_offset
+= SIGNED_SHORT (op
);
1799 else if (cr_reg
>= 0 &&
1800 (store_insn_p (op
, cr_reg
, 1, true)))
1802 fdata
->cr_offset
= offset
;
1803 /* Invalidate cr_reg, but don't set it to -1.
1804 That would mean that it had never been set. */
1806 if ((op
& 0xfc000003) == 0xf8000000 ||
1807 (op
& 0xfc000000) == 0x90000000)
1809 /* Does not update r1, so add displacement to cr_offset. */
1810 fdata
->cr_offset
+= SIGNED_SHORT (op
);
1815 else if ((op
& 0xfe80ffff) == 0x42800005 && lr_reg
!= -1)
1817 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1818 prediction bits. If the LR has already been saved, we can
1822 else if (op
== 0x48000005)
1829 else if (op
== 0x48000004)
1834 else if ((op
& 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1835 in V.4 -mminimal-toc */
1836 (op
& 0xffff0000) == 0x3bde0000)
1837 { /* addi 30,30,foo@l */
1841 else if ((op
& 0xfc000001) == 0x48000001)
1845 fdata
->frameless
= 0;
1847 /* If the return address has already been saved, we can skip
1848 calls to blrl (for PIC). */
1849 if (lr_reg
!= -1 && bl_to_blrl_insn_p (pc
, op
, byte_order
))
1855 /* Don't skip over the subroutine call if it is not within
1856 the first three instructions of the prologue and either
1857 we have no line table information or the line info tells
1858 us that the subroutine call is not part of the line
1859 associated with the prologue. */
1860 if ((pc
- orig_pc
) > 8)
1862 struct symtab_and_line prologue_sal
= find_pc_line (orig_pc
, 0);
1863 struct symtab_and_line this_sal
= find_pc_line (pc
, 0);
1865 if ((prologue_sal
.line
== 0)
1866 || (prologue_sal
.line
!= this_sal
.line
))
1870 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
1872 /* At this point, make sure this is not a trampoline
1873 function (a function that simply calls another functions,
1874 and nothing else). If the next is not a nop, this branch
1875 was part of the function prologue. */
1877 if (op
== 0x4def7b82 || op
== 0) /* crorc 15, 15, 15 */
1878 break; /* Don't skip over
1884 /* update stack pointer */
1885 else if ((op
& 0xfc1f0000) == 0x94010000)
1886 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1887 fdata
->frameless
= 0;
1888 fdata
->offset
= SIGNED_SHORT (op
);
1889 offset
= fdata
->offset
;
1892 else if ((op
& 0xfc1f016e) == 0x7c01016e)
1893 { /* stwux rX,r1,rY */
1894 /* No way to figure out what r1 is going to be. */
1895 fdata
->frameless
= 0;
1896 offset
= fdata
->offset
;
1899 else if ((op
& 0xfc1f0003) == 0xf8010001)
1900 { /* stdu rX,NUM(r1) */
1901 fdata
->frameless
= 0;
1902 fdata
->offset
= SIGNED_SHORT (op
& ~3UL);
1903 offset
= fdata
->offset
;
1906 else if ((op
& 0xfc1f016a) == 0x7c01016a)
1907 { /* stdux rX,r1,rY */
1908 /* No way to figure out what r1 is going to be. */
1909 fdata
->frameless
= 0;
1910 offset
= fdata
->offset
;
1913 else if ((op
& 0xffff0000) == 0x38210000)
1914 { /* addi r1,r1,SIMM */
1915 fdata
->frameless
= 0;
1916 fdata
->offset
+= SIGNED_SHORT (op
);
1917 offset
= fdata
->offset
;
1920 /* Load up minimal toc pointer. Do not treat an epilogue restore
1921 of r31 as a minimal TOC load. */
1922 else if (((op
>> 22) == 0x20f || /* l r31,... or l r30,... */
1923 (op
>> 22) == 0x3af) /* ld r31,... or ld r30,... */
1925 && !minimal_toc_loaded
)
1927 minimal_toc_loaded
= 1;
1930 /* move parameters from argument registers to local variable
1933 else if ((op
& 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1934 (((op
>> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1935 (((op
>> 21) & 31) <= 10) &&
1936 ((long) ((op
>> 16) & 31)
1937 >= fdata
->saved_gpr
)) /* Rx: local var reg */
1941 /* store parameters in stack */
1943 /* Move parameters from argument registers to temporary register. */
1944 else if (store_param_on_stack_p (op
, framep
, &r0_contains_arg
))
1948 /* Set up frame pointer */
1950 else if (op
== 0x603d0000) /* oril r29, r1, 0x0 */
1952 fdata
->frameless
= 0;
1954 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 29);
1955 alloca_reg_offset
= offset
;
1958 /* Another way to set up the frame pointer. */
1960 else if (op
== 0x603f0000 /* oril r31, r1, 0x0 */
1961 || op
== 0x7c3f0b78)
1963 fdata
->frameless
= 0;
1965 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
+ 31);
1966 alloca_reg_offset
= offset
;
1969 /* Another way to set up the frame pointer. */
1971 else if ((op
& 0xfc1fffff) == 0x38010000)
1972 { /* addi rX, r1, 0x0 */
1973 fdata
->frameless
= 0;
1975 fdata
->alloca_reg
= (tdep
->ppc_gp0_regnum
1976 + ((op
& ~0x38010000) >> 21));
1977 alloca_reg_offset
= offset
;
1980 /* AltiVec related instructions. */
1981 /* Store the vrsave register (spr 256) in another register for
1982 later manipulation, or load a register into the vrsave
1983 register. 2 instructions are used: mfvrsave and
1984 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1985 and mtspr SPR256, Rn. */
1986 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1987 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1988 else if ((op
& 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1990 vrsave_reg
= GET_SRC_REG (op
);
1993 else if ((op
& 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1997 /* Store the register where vrsave was saved to onto the stack:
1998 rS is the register where vrsave was stored in a previous
2000 /* 100100 sssss 00001 dddddddd dddddddd */
2001 else if ((op
& 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
2003 if (vrsave_reg
== GET_SRC_REG (op
))
2005 fdata
->vrsave_offset
= SIGNED_SHORT (op
) + offset
;
2010 /* Compute the new value of vrsave, by modifying the register
2011 where vrsave was saved to. */
2012 else if (((op
& 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
2013 || ((op
& 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
2017 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
2018 in a pair of insns to save the vector registers on the
2020 /* 001110 00000 00000 iiii iiii iiii iiii */
2021 /* 001110 01110 00000 iiii iiii iiii iiii */
2022 else if ((op
& 0xffff0000) == 0x38000000 /* li r0, SIMM */
2023 || (op
& 0xffff0000) == 0x39c00000) /* li r14, SIMM */
2025 if ((op
& 0xffff0000) == 0x38000000)
2026 r0_contains_arg
= 0;
2028 vr_saved_offset
= SIGNED_SHORT (op
);
2030 /* This insn by itself is not part of the prologue, unless
2031 if part of the pair of insns mentioned above. So do not
2032 record this insn as part of the prologue yet. */
2033 prev_insn_was_prologue_insn
= 0;
2035 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
2036 /* 011111 sssss 11111 00000 00111001110 */
2037 else if ((op
& 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
2039 if (pc
== (li_found_pc
+ 4))
2041 vr_reg
= GET_SRC_REG (op
);
2042 /* If this is the first vector reg to be saved, or if
2043 it has a lower number than others previously seen,
2044 reupdate the frame info. */
2045 if (fdata
->saved_vr
== -1 || fdata
->saved_vr
> vr_reg
)
2047 fdata
->saved_vr
= vr_reg
;
2048 fdata
->vr_offset
= vr_saved_offset
+ offset
;
2050 vr_saved_offset
= -1;
2055 /* End AltiVec related instructions. */
2057 /* Start BookE related instructions. */
2058 /* Store gen register S at (r31+uimm).
2059 Any register less than r13 is volatile, so we don't care. */
2060 /* 000100 sssss 11111 iiiii 01100100001 */
2061 else if (arch_info
->mach
== bfd_mach_ppc_e500
2062 && (op
& 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2064 if ((op
& 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2067 ev_reg
= GET_SRC_REG (op
);
2068 imm
= (op
>> 11) & 0x1f;
2069 ev_offset
= imm
* 8;
2070 /* If this is the first vector reg to be saved, or if
2071 it has a lower number than others previously seen,
2072 reupdate the frame info. */
2073 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2075 fdata
->saved_ev
= ev_reg
;
2076 fdata
->ev_offset
= ev_offset
+ offset
;
2081 /* Store gen register rS at (r1+rB). */
2082 /* 000100 sssss 00001 bbbbb 01100100000 */
2083 else if (arch_info
->mach
== bfd_mach_ppc_e500
2084 && (op
& 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2086 if (pc
== (li_found_pc
+ 4))
2088 ev_reg
= GET_SRC_REG (op
);
2089 /* If this is the first vector reg to be saved, or if
2090 it has a lower number than others previously seen,
2091 reupdate the frame info. */
2092 /* We know the contents of rB from the previous instruction. */
2093 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2095 fdata
->saved_ev
= ev_reg
;
2096 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2098 vr_saved_offset
= -1;
2104 /* Store gen register r31 at (rA+uimm). */
2105 /* 000100 11111 aaaaa iiiii 01100100001 */
2106 else if (arch_info
->mach
== bfd_mach_ppc_e500
2107 && (op
& 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2109 /* Wwe know that the source register is 31 already, but
2110 it can't hurt to compute it. */
2111 ev_reg
= GET_SRC_REG (op
);
2112 ev_offset
= ((op
>> 11) & 0x1f) * 8;
2113 /* If this is the first vector reg to be saved, or if
2114 it has a lower number than others previously seen,
2115 reupdate the frame info. */
2116 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2118 fdata
->saved_ev
= ev_reg
;
2119 fdata
->ev_offset
= ev_offset
+ offset
;
2124 /* Store gen register S at (r31+r0).
2125 Store param on stack when offset from SP bigger than 4 bytes. */
2126 /* 000100 sssss 11111 00000 01100100000 */
2127 else if (arch_info
->mach
== bfd_mach_ppc_e500
2128 && (op
& 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2130 if (pc
== (li_found_pc
+ 4))
2132 if ((op
& 0x03e00000) >= 0x01a00000)
2134 ev_reg
= GET_SRC_REG (op
);
2135 /* If this is the first vector reg to be saved, or if
2136 it has a lower number than others previously seen,
2137 reupdate the frame info. */
2138 /* We know the contents of r0 from the previous
2140 if (fdata
->saved_ev
== -1 || fdata
->saved_ev
> ev_reg
)
2142 fdata
->saved_ev
= ev_reg
;
2143 fdata
->ev_offset
= vr_saved_offset
+ offset
;
2147 vr_saved_offset
= -1;
2152 /* End BookE related instructions. */
2156 unsigned int all_mask
= ~((1U << fdata
->saved_gpr
) - 1);
2158 /* Not a recognized prologue instruction.
2159 Handle optimizer code motions into the prologue by continuing
2160 the search if we have no valid frame yet or if the return
2161 address is not yet saved in the frame. Also skip instructions
2162 if some of the GPRs expected to be saved are not yet saved. */
2163 if (fdata
->frameless
== 0 && fdata
->nosavedpc
== 0
2164 && (fdata
->gpr_mask
& all_mask
) == all_mask
)
2167 if (op
== 0x4e800020 /* blr */
2168 || op
== 0x4e800420) /* bctr */
2169 /* Do not scan past epilogue in frameless functions or
2172 if ((op
& 0xf4000000) == 0x40000000) /* bxx */
2173 /* Never skip branches. */
2176 if (num_skip_non_prologue_insns
++ > max_skip_non_prologue_insns
)
2177 /* Do not scan too many insns, scanning insns is expensive with
2181 /* Continue scanning. */
2182 prev_insn_was_prologue_insn
= 0;
2188 /* I have problems with skipping over __main() that I need to address
2189 * sometime. Previously, I used to use misc_function_vector which
2190 * didn't work as well as I wanted to be. -MGO */
2192 /* If the first thing after skipping a prolog is a branch to a function,
2193 this might be a call to an initializer in main(), introduced by gcc2.
2194 We'd like to skip over it as well. Fortunately, xlc does some extra
2195 work before calling a function right after a prologue, thus we can
2196 single out such gcc2 behaviour. */
2199 if ((op
& 0xfc000001) == 0x48000001)
2200 { /* bl foo, an initializer function? */
2201 op
= read_memory_integer (pc
+ 4, 4, byte_order
);
2203 if (op
== 0x4def7b82)
2204 { /* cror 0xf, 0xf, 0xf (nop) */
2206 /* Check and see if we are in main. If so, skip over this
2207 initializer function as well. */
2209 tmp
= find_pc_misc_function (pc
);
2211 && strcmp (misc_function_vector
[tmp
].name
, main_name ()) == 0)
2217 if (pc
== lim_pc
&& lr_reg
>= 0)
2218 fdata
->lr_register
= lr_reg
;
2220 fdata
->offset
= -fdata
->offset
;
2221 return last_prologue_pc
;
2225 rs6000_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2227 struct rs6000_framedata frame
;
2228 CORE_ADDR limit_pc
, func_addr
, func_end_addr
= 0;
2230 /* See if we can determine the end of the prologue via the symbol table.
2231 If so, then return either PC, or the PC after the prologue, whichever
2233 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
2235 CORE_ADDR post_prologue_pc
2236 = skip_prologue_using_sal (gdbarch
, func_addr
);
2237 if (post_prologue_pc
!= 0)
2238 return std::max (pc
, post_prologue_pc
);
2241 /* Can't determine prologue from the symbol table, need to examine
2244 /* Find an upper limit on the function prologue using the debug
2245 information. If the debug information could not be used to provide
2246 that bound, then use an arbitrary large number as the upper bound. */
2247 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
2249 limit_pc
= pc
+ 100; /* Magic. */
2251 /* Do not allow limit_pc to be past the function end, if we know
2252 where that end is... */
2253 if (func_end_addr
&& limit_pc
> func_end_addr
)
2254 limit_pc
= func_end_addr
;
2256 pc
= skip_prologue (gdbarch
, pc
, limit_pc
, &frame
);
2260 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2261 in the prologue of main().
2263 The function below examines the code pointed at by PC and checks to
2264 see if it corresponds to a call to __eabi. If so, it returns the
2265 address of the instruction following that call. Otherwise, it simply
2269 rs6000_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2271 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2275 if (target_read_memory (pc
, buf
, 4))
2277 op
= extract_unsigned_integer (buf
, 4, byte_order
);
2279 if ((op
& BL_MASK
) == BL_INSTRUCTION
)
2281 CORE_ADDR displ
= op
& BL_DISPLACEMENT_MASK
;
2282 CORE_ADDR call_dest
= pc
+ 4 + displ
;
2283 struct bound_minimal_symbol s
= lookup_minimal_symbol_by_pc (call_dest
);
2285 /* We check for ___eabi (three leading underscores) in addition
2286 to __eabi in case the GCC option "-fleading-underscore" was
2287 used to compile the program. */
2288 if (s
.minsym
!= NULL
2289 && MSYMBOL_LINKAGE_NAME (s
.minsym
) != NULL
2290 && (strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "__eabi") == 0
2291 || strcmp (MSYMBOL_LINKAGE_NAME (s
.minsym
), "___eabi") == 0))
2297 /* All the ABI's require 16 byte alignment. */
2299 rs6000_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2301 return (addr
& -16);
2304 /* Return whether handle_inferior_event() should proceed through code
2305 starting at PC in function NAME when stepping.
2307 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2308 handle memory references that are too distant to fit in instructions
2309 generated by the compiler. For example, if 'foo' in the following
2314 is greater than 32767, the linker might replace the lwz with a branch to
2315 somewhere in @FIX1 that does the load in 2 instructions and then branches
2316 back to where execution should continue.
2318 GDB should silently step over @FIX code, just like AIX dbx does.
2319 Unfortunately, the linker uses the "b" instruction for the
2320 branches, meaning that the link register doesn't get set.
2321 Therefore, GDB's usual step_over_function () mechanism won't work.
2323 Instead, use the gdbarch_skip_trampoline_code and
2324 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2328 rs6000_in_solib_return_trampoline (struct gdbarch
*gdbarch
,
2329 CORE_ADDR pc
, const char *name
)
2331 return name
&& startswith (name
, "@FIX");
2334 /* Skip code that the user doesn't want to see when stepping:
2336 1. Indirect function calls use a piece of trampoline code to do context
2337 switching, i.e. to set the new TOC table. Skip such code if we are on
2338 its first instruction (as when we have single-stepped to here).
2340 2. Skip shared library trampoline code (which is different from
2341 indirect function call trampolines).
2343 3. Skip bigtoc fixup code.
2345 Result is desired PC to step until, or NULL if we are not in
2346 code that should be skipped. */
2349 rs6000_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
2351 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2352 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2353 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2354 unsigned int ii
, op
;
2356 CORE_ADDR solib_target_pc
;
2357 struct bound_minimal_symbol msymbol
;
2359 static unsigned trampoline_code
[] =
2361 0x800b0000, /* l r0,0x0(r11) */
2362 0x90410014, /* st r2,0x14(r1) */
2363 0x7c0903a6, /* mtctr r0 */
2364 0x804b0004, /* l r2,0x4(r11) */
2365 0x816b0008, /* l r11,0x8(r11) */
2366 0x4e800420, /* bctr */
2367 0x4e800020, /* br */
2371 /* Check for bigtoc fixup code. */
2372 msymbol
= lookup_minimal_symbol_by_pc (pc
);
2374 && rs6000_in_solib_return_trampoline (gdbarch
, pc
,
2375 MSYMBOL_LINKAGE_NAME (msymbol
.minsym
)))
2377 /* Double-check that the third instruction from PC is relative "b". */
2378 op
= read_memory_integer (pc
+ 8, 4, byte_order
);
2379 if ((op
& 0xfc000003) == 0x48000000)
2381 /* Extract bits 6-29 as a signed 24-bit relative word address and
2382 add it to the containing PC. */
2383 rel
= ((int)(op
<< 6) >> 6);
2384 return pc
+ 8 + rel
;
2388 /* If pc is in a shared library trampoline, return its target. */
2389 solib_target_pc
= find_solib_trampoline_target (frame
, pc
);
2390 if (solib_target_pc
)
2391 return solib_target_pc
;
2393 for (ii
= 0; trampoline_code
[ii
]; ++ii
)
2395 op
= read_memory_integer (pc
+ (ii
* 4), 4, byte_order
);
2396 if (op
!= trampoline_code
[ii
])
2399 ii
= get_frame_register_unsigned (frame
, 11); /* r11 holds destination
2401 pc
= read_memory_unsigned_integer (ii
, tdep
->wordsize
, byte_order
);
2405 /* ISA-specific vector types. */
2407 static struct type
*
2408 rs6000_builtin_type_vec64 (struct gdbarch
*gdbarch
)
2410 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2412 if (!tdep
->ppc_builtin_type_vec64
)
2414 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2416 /* The type we're building is this: */
2418 union __gdb_builtin_type_vec64
2422 int32_t v2_int32
[2];
2423 int16_t v4_int16
[4];
2430 t
= arch_composite_type (gdbarch
,
2431 "__ppc_builtin_type_vec64", TYPE_CODE_UNION
);
2432 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
2433 append_composite_type_field (t
, "v2_float",
2434 init_vector_type (bt
->builtin_float
, 2));
2435 append_composite_type_field (t
, "v2_int32",
2436 init_vector_type (bt
->builtin_int32
, 2));
2437 append_composite_type_field (t
, "v4_int16",
2438 init_vector_type (bt
->builtin_int16
, 4));
2439 append_composite_type_field (t
, "v8_int8",
2440 init_vector_type (bt
->builtin_int8
, 8));
2442 TYPE_VECTOR (t
) = 1;
2443 TYPE_NAME (t
) = "ppc_builtin_type_vec64";
2444 tdep
->ppc_builtin_type_vec64
= t
;
2447 return tdep
->ppc_builtin_type_vec64
;
2450 /* Vector 128 type. */
2452 static struct type
*
2453 rs6000_builtin_type_vec128 (struct gdbarch
*gdbarch
)
2455 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2457 if (!tdep
->ppc_builtin_type_vec128
)
2459 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2461 /* The type we're building is this
2463 type = union __ppc_builtin_type_vec128 {
2465 double v2_double[2];
2467 int32_t v4_int32[4];
2468 int16_t v8_int16[8];
2469 int8_t v16_int8[16];
2475 t
= arch_composite_type (gdbarch
,
2476 "__ppc_builtin_type_vec128", TYPE_CODE_UNION
);
2477 append_composite_type_field (t
, "uint128", bt
->builtin_uint128
);
2478 append_composite_type_field (t
, "v2_double",
2479 init_vector_type (bt
->builtin_double
, 2));
2480 append_composite_type_field (t
, "v4_float",
2481 init_vector_type (bt
->builtin_float
, 4));
2482 append_composite_type_field (t
, "v4_int32",
2483 init_vector_type (bt
->builtin_int32
, 4));
2484 append_composite_type_field (t
, "v8_int16",
2485 init_vector_type (bt
->builtin_int16
, 8));
2486 append_composite_type_field (t
, "v16_int8",
2487 init_vector_type (bt
->builtin_int8
, 16));
2489 TYPE_VECTOR (t
) = 1;
2490 TYPE_NAME (t
) = "ppc_builtin_type_vec128";
2491 tdep
->ppc_builtin_type_vec128
= t
;
2494 return tdep
->ppc_builtin_type_vec128
;
2497 /* Return the name of register number REGNO, or the empty string if it
2498 is an anonymous register. */
2501 rs6000_register_name (struct gdbarch
*gdbarch
, int regno
)
2503 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2505 /* The upper half "registers" have names in the XML description,
2506 but we present only the low GPRs and the full 64-bit registers
2508 if (tdep
->ppc_ev0_upper_regnum
>= 0
2509 && tdep
->ppc_ev0_upper_regnum
<= regno
2510 && regno
< tdep
->ppc_ev0_upper_regnum
+ ppc_num_gprs
)
2513 /* Hide the upper halves of the vs0~vs31 registers. */
2514 if (tdep
->ppc_vsr0_regnum
>= 0
2515 && tdep
->ppc_vsr0_upper_regnum
<= regno
2516 && regno
< tdep
->ppc_vsr0_upper_regnum
+ ppc_num_gprs
)
2519 /* Check if the SPE pseudo registers are available. */
2520 if (IS_SPE_PSEUDOREG (tdep
, regno
))
2522 static const char *const spe_regnames
[] = {
2523 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2524 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2525 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2526 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2528 return spe_regnames
[regno
- tdep
->ppc_ev0_regnum
];
2531 /* Check if the decimal128 pseudo-registers are available. */
2532 if (IS_DFP_PSEUDOREG (tdep
, regno
))
2534 static const char *const dfp128_regnames
[] = {
2535 "dl0", "dl1", "dl2", "dl3",
2536 "dl4", "dl5", "dl6", "dl7",
2537 "dl8", "dl9", "dl10", "dl11",
2538 "dl12", "dl13", "dl14", "dl15"
2540 return dfp128_regnames
[regno
- tdep
->ppc_dl0_regnum
];
2543 /* Check if this is a VSX pseudo-register. */
2544 if (IS_VSX_PSEUDOREG (tdep
, regno
))
2546 static const char *const vsx_regnames
[] = {
2547 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2548 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2549 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2550 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2551 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2552 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2553 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2554 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2555 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2557 return vsx_regnames
[regno
- tdep
->ppc_vsr0_regnum
];
2560 /* Check if the this is a Extended FP pseudo-register. */
2561 if (IS_EFP_PSEUDOREG (tdep
, regno
))
2563 static const char *const efpr_regnames
[] = {
2564 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2565 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2566 "f46", "f47", "f48", "f49", "f50", "f51",
2567 "f52", "f53", "f54", "f55", "f56", "f57",
2568 "f58", "f59", "f60", "f61", "f62", "f63"
2570 return efpr_regnames
[regno
- tdep
->ppc_efpr0_regnum
];
2573 return tdesc_register_name (gdbarch
, regno
);
2576 /* Return the GDB type object for the "standard" data type of data in
2579 static struct type
*
2580 rs6000_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2582 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2584 /* These are the only pseudo-registers we support. */
2585 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2586 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2587 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2588 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2590 /* These are the e500 pseudo-registers. */
2591 if (IS_SPE_PSEUDOREG (tdep
, regnum
))
2592 return rs6000_builtin_type_vec64 (gdbarch
);
2593 else if (IS_DFP_PSEUDOREG (tdep
, regnum
))
2594 /* PPC decimal128 pseudo-registers. */
2595 return builtin_type (gdbarch
)->builtin_declong
;
2596 else if (IS_VSX_PSEUDOREG (tdep
, regnum
))
2597 /* POWER7 VSX pseudo-registers. */
2598 return rs6000_builtin_type_vec128 (gdbarch
);
2600 /* POWER7 Extended FP pseudo-registers. */
2601 return builtin_type (gdbarch
)->builtin_double
;
2604 /* Is REGNUM a member of REGGROUP? */
2606 rs6000_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2607 struct reggroup
*group
)
2609 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2611 /* These are the only pseudo-registers we support. */
2612 gdb_assert (IS_SPE_PSEUDOREG (tdep
, regnum
)
2613 || IS_DFP_PSEUDOREG (tdep
, regnum
)
2614 || IS_VSX_PSEUDOREG (tdep
, regnum
)
2615 || IS_EFP_PSEUDOREG (tdep
, regnum
));
2617 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2618 if (IS_SPE_PSEUDOREG (tdep
, regnum
) || IS_VSX_PSEUDOREG (tdep
, regnum
))
2619 return group
== all_reggroup
|| group
== vector_reggroup
;
2621 /* PPC decimal128 or Extended FP pseudo-registers. */
2622 return group
== all_reggroup
|| group
== float_reggroup
;
2625 /* The register format for RS/6000 floating point registers is always
2626 double, we need a conversion if the memory format is float. */
2629 rs6000_convert_register_p (struct gdbarch
*gdbarch
, int regnum
,
2632 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2634 return (tdep
->ppc_fp0_regnum
>= 0
2635 && regnum
>= tdep
->ppc_fp0_regnum
2636 && regnum
< tdep
->ppc_fp0_regnum
+ ppc_num_fprs
2637 && TYPE_CODE (type
) == TYPE_CODE_FLT
2638 && TYPE_LENGTH (type
)
2639 != TYPE_LENGTH (builtin_type (gdbarch
)->builtin_double
));
2643 rs6000_register_to_value (struct frame_info
*frame
,
2647 int *optimizedp
, int *unavailablep
)
2649 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2650 gdb_byte from
[PPC_MAX_REGISTER_SIZE
];
2652 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2654 if (!get_frame_register_bytes (frame
, regnum
, 0,
2655 register_size (gdbarch
, regnum
),
2656 from
, optimizedp
, unavailablep
))
2659 target_float_convert (from
, builtin_type (gdbarch
)->builtin_double
,
2661 *optimizedp
= *unavailablep
= 0;
2666 rs6000_value_to_register (struct frame_info
*frame
,
2669 const gdb_byte
*from
)
2671 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2672 gdb_byte to
[PPC_MAX_REGISTER_SIZE
];
2674 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_FLT
);
2676 target_float_convert (from
, type
,
2677 to
, builtin_type (gdbarch
)->builtin_double
);
2678 put_frame_register (frame
, regnum
, to
);
2681 /* The type of a function that moves the value of REG between CACHE
2682 or BUF --- in either direction. */
2683 typedef enum register_status (*move_ev_register_func
) (struct regcache
*,
2686 /* Move SPE vector register values between a 64-bit buffer and the two
2687 32-bit raw register halves in a regcache. This function handles
2688 both splitting a 64-bit value into two 32-bit halves, and joining
2689 two halves into a whole 64-bit value, depending on the function
2690 passed as the MOVE argument.
2692 EV_REG must be the number of an SPE evN vector register --- a
2693 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2696 Call MOVE once for each 32-bit half of that register, passing
2697 REGCACHE, the number of the raw register corresponding to that
2698 half, and the address of the appropriate half of BUFFER.
2700 For example, passing 'regcache_raw_read' as the MOVE function will
2701 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2702 'regcache_raw_supply' will supply the contents of BUFFER to the
2703 appropriate pair of raw registers in REGCACHE.
2705 You may need to cast away some 'const' qualifiers when passing
2706 MOVE, since this function can't tell at compile-time which of
2707 REGCACHE or BUFFER is acting as the source of the data. If C had
2708 co-variant type qualifiers, ... */
2710 static enum register_status
2711 e500_move_ev_register (move_ev_register_func move
,
2712 struct regcache
*regcache
, int ev_reg
, void *buffer
)
2714 struct gdbarch
*arch
= regcache
->arch ();
2715 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2717 gdb_byte
*byte_buffer
= (gdb_byte
*) buffer
;
2718 enum register_status status
;
2720 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2722 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2724 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2726 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2728 if (status
== REG_VALID
)
2729 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
,
2734 status
= move (regcache
, tdep
->ppc_gp0_regnum
+ reg_index
, byte_buffer
);
2735 if (status
== REG_VALID
)
2736 status
= move (regcache
, tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2743 static enum register_status
2744 do_regcache_raw_write (struct regcache
*regcache
, int regnum
, void *buffer
)
2746 regcache_raw_write (regcache
, regnum
, (const gdb_byte
*) buffer
);
2751 static enum register_status
2752 e500_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2753 int ev_reg
, gdb_byte
*buffer
)
2755 struct gdbarch
*arch
= regcache
->arch ();
2756 struct gdbarch_tdep
*tdep
= gdbarch_tdep (arch
);
2758 enum register_status status
;
2760 gdb_assert (IS_SPE_PSEUDOREG (tdep
, ev_reg
));
2762 reg_index
= ev_reg
- tdep
->ppc_ev0_regnum
;
2764 if (gdbarch_byte_order (arch
) == BFD_ENDIAN_BIG
)
2766 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2768 if (status
== REG_VALID
)
2769 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
,
2774 status
= regcache
->raw_read (tdep
->ppc_gp0_regnum
+ reg_index
, buffer
);
2775 if (status
== REG_VALID
)
2776 status
= regcache
->raw_read (tdep
->ppc_ev0_upper_regnum
+ reg_index
,
2785 e500_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2786 int reg_nr
, const gdb_byte
*buffer
)
2788 e500_move_ev_register (do_regcache_raw_write
, regcache
,
2789 reg_nr
, (void *) buffer
);
2792 /* Read method for DFP pseudo-registers. */
2793 static enum register_status
2794 dfp_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2795 int reg_nr
, gdb_byte
*buffer
)
2797 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2798 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2799 enum register_status status
;
2801 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2803 /* Read two FP registers to form a whole dl register. */
2804 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2805 2 * reg_index
, buffer
);
2806 if (status
== REG_VALID
)
2807 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2808 2 * reg_index
+ 1, buffer
+ 8);
2812 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2813 2 * reg_index
+ 1, buffer
);
2814 if (status
== REG_VALID
)
2815 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2816 2 * reg_index
, buffer
+ 8);
2822 /* Write method for DFP pseudo-registers. */
2824 dfp_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2825 int reg_nr
, const gdb_byte
*buffer
)
2827 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2828 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
2830 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2832 /* Write each half of the dl register into a separate
2834 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2835 2 * reg_index
, buffer
);
2836 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2837 2 * reg_index
+ 1, buffer
+ 8);
2841 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2842 2 * reg_index
+ 1, buffer
);
2843 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2844 2 * reg_index
, buffer
+ 8);
2848 /* Read method for POWER7 VSX pseudo-registers. */
2849 static enum register_status
2850 vsx_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2851 int reg_nr
, gdb_byte
*buffer
)
2853 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2854 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2855 enum register_status status
;
2857 /* Read the portion that overlaps the VMX registers. */
2859 status
= regcache
->raw_read (tdep
->ppc_vr0_regnum
+
2860 reg_index
- 32, buffer
);
2862 /* Read the portion that overlaps the FPR registers. */
2863 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2865 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2867 if (status
== REG_VALID
)
2868 status
= regcache
->raw_read (tdep
->ppc_vsr0_upper_regnum
+
2869 reg_index
, buffer
+ 8);
2873 status
= regcache
->raw_read (tdep
->ppc_fp0_regnum
+
2874 reg_index
, buffer
+ 8);
2875 if (status
== REG_VALID
)
2876 status
= regcache
->raw_read (tdep
->ppc_vsr0_upper_regnum
+
2883 /* Write method for POWER7 VSX pseudo-registers. */
2885 vsx_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2886 int reg_nr
, const gdb_byte
*buffer
)
2888 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2889 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
2891 /* Write the portion that overlaps the VMX registers. */
2893 regcache_raw_write (regcache
, tdep
->ppc_vr0_regnum
+
2894 reg_index
- 32, buffer
);
2896 /* Write the portion that overlaps the FPR registers. */
2897 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
2899 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2901 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2902 reg_index
, buffer
+ 8);
2906 regcache_raw_write (regcache
, tdep
->ppc_fp0_regnum
+
2907 reg_index
, buffer
+ 8);
2908 regcache_raw_write (regcache
, tdep
->ppc_vsr0_upper_regnum
+
2913 /* Read method for POWER7 Extended FP pseudo-registers. */
2914 static enum register_status
2915 efpr_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2916 int reg_nr
, gdb_byte
*buffer
)
2918 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2919 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2920 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2922 /* Read the portion that overlaps the VMX register. */
2923 return regcache
->raw_read_part (tdep
->ppc_vr0_regnum
+ reg_index
,
2924 offset
, register_size (gdbarch
, reg_nr
),
2928 /* Write method for POWER7 Extended FP pseudo-registers. */
2930 efpr_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2931 int reg_nr
, const gdb_byte
*buffer
)
2933 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2934 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
2935 int offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 0 : 8;
2937 /* Write the portion that overlaps the VMX register. */
2938 regcache_raw_write_part (regcache
, tdep
->ppc_vr0_regnum
+ reg_index
,
2939 offset
, register_size (gdbarch
, reg_nr
),
2943 static enum register_status
2944 rs6000_pseudo_register_read (struct gdbarch
*gdbarch
,
2945 readable_regcache
*regcache
,
2946 int reg_nr
, gdb_byte
*buffer
)
2948 struct gdbarch
*regcache_arch
= regcache
->arch ();
2949 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2951 gdb_assert (regcache_arch
== gdbarch
);
2953 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2954 return e500_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2955 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2956 return dfp_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2957 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2958 return vsx_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2959 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2960 return efpr_pseudo_register_read (gdbarch
, regcache
, reg_nr
, buffer
);
2962 internal_error (__FILE__
, __LINE__
,
2963 _("rs6000_pseudo_register_read: "
2964 "called on unexpected register '%s' (%d)"),
2965 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2969 rs6000_pseudo_register_write (struct gdbarch
*gdbarch
,
2970 struct regcache
*regcache
,
2971 int reg_nr
, const gdb_byte
*buffer
)
2973 struct gdbarch
*regcache_arch
= regcache
->arch ();
2974 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2976 gdb_assert (regcache_arch
== gdbarch
);
2978 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
2979 e500_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2980 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
2981 dfp_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2982 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
2983 vsx_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2984 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
2985 efpr_pseudo_register_write (gdbarch
, regcache
, reg_nr
, buffer
);
2987 internal_error (__FILE__
, __LINE__
,
2988 _("rs6000_pseudo_register_write: "
2989 "called on unexpected register '%s' (%d)"),
2990 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
2994 rs6000_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
2995 struct agent_expr
*ax
, int reg_nr
)
2997 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2998 if (IS_SPE_PSEUDOREG (tdep
, reg_nr
))
3000 int reg_index
= reg_nr
- tdep
->ppc_ev0_regnum
;
3001 ax_reg_mask (ax
, tdep
->ppc_gp0_regnum
+ reg_index
);
3002 ax_reg_mask (ax
, tdep
->ppc_ev0_upper_regnum
+ reg_index
);
3004 else if (IS_DFP_PSEUDOREG (tdep
, reg_nr
))
3006 int reg_index
= reg_nr
- tdep
->ppc_dl0_regnum
;
3007 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
);
3008 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ 2 * reg_index
+ 1);
3010 else if (IS_VSX_PSEUDOREG (tdep
, reg_nr
))
3012 int reg_index
= reg_nr
- tdep
->ppc_vsr0_regnum
;
3015 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
- 32);
3019 ax_reg_mask (ax
, tdep
->ppc_fp0_regnum
+ reg_index
);
3020 ax_reg_mask (ax
, tdep
->ppc_vsr0_upper_regnum
+ reg_index
);
3023 else if (IS_EFP_PSEUDOREG (tdep
, reg_nr
))
3025 int reg_index
= reg_nr
- tdep
->ppc_efpr0_regnum
;
3026 ax_reg_mask (ax
, tdep
->ppc_vr0_regnum
+ reg_index
);
3029 internal_error (__FILE__
, __LINE__
,
3030 _("rs6000_pseudo_register_collect: "
3031 "called on unexpected register '%s' (%d)"),
3032 gdbarch_register_name (gdbarch
, reg_nr
), reg_nr
);
3038 rs6000_gen_return_address (struct gdbarch
*gdbarch
,
3039 struct agent_expr
*ax
, struct axs_value
*value
,
3042 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3043 value
->type
= register_type (gdbarch
, tdep
->ppc_lr_regnum
);
3044 value
->kind
= axs_lvalue_register
;
3045 value
->u
.reg
= tdep
->ppc_lr_regnum
;
3049 /* Convert a DBX STABS register number to a GDB register number. */
3051 rs6000_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3053 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3055 if (0 <= num
&& num
<= 31)
3056 return tdep
->ppc_gp0_regnum
+ num
;
3057 else if (32 <= num
&& num
<= 63)
3058 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3059 specifies registers the architecture doesn't have? Our
3060 callers don't check the value we return. */
3061 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3062 else if (77 <= num
&& num
<= 108)
3063 return tdep
->ppc_vr0_regnum
+ (num
- 77);
3064 else if (1200 <= num
&& num
< 1200 + 32)
3065 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3070 return tdep
->ppc_mq_regnum
;
3072 return tdep
->ppc_lr_regnum
;
3074 return tdep
->ppc_ctr_regnum
;
3076 return tdep
->ppc_xer_regnum
;
3078 return tdep
->ppc_vrsave_regnum
;
3080 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3082 return tdep
->ppc_acc_regnum
;
3084 return tdep
->ppc_spefscr_regnum
;
3091 /* Convert a Dwarf 2 register number to a GDB register number. */
3093 rs6000_dwarf2_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
3095 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3097 if (0 <= num
&& num
<= 31)
3098 return tdep
->ppc_gp0_regnum
+ num
;
3099 else if (32 <= num
&& num
<= 63)
3100 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3101 specifies registers the architecture doesn't have? Our
3102 callers don't check the value we return. */
3103 return tdep
->ppc_fp0_regnum
+ (num
- 32);
3104 else if (1124 <= num
&& num
< 1124 + 32)
3105 return tdep
->ppc_vr0_regnum
+ (num
- 1124);
3106 else if (1200 <= num
&& num
< 1200 + 32)
3107 return tdep
->ppc_ev0_upper_regnum
+ (num
- 1200);
3112 return tdep
->ppc_cr_regnum
;
3114 return tdep
->ppc_vrsave_regnum
- 1; /* vscr */
3116 return tdep
->ppc_acc_regnum
;
3118 return tdep
->ppc_mq_regnum
;
3120 return tdep
->ppc_xer_regnum
;
3122 return tdep
->ppc_lr_regnum
;
3124 return tdep
->ppc_ctr_regnum
;
3126 return tdep
->ppc_vrsave_regnum
;
3128 return tdep
->ppc_spefscr_regnum
;
3134 /* Translate a .eh_frame register to DWARF register, or adjust a
3135 .debug_frame register. */
3138 rs6000_adjust_frame_regnum (struct gdbarch
*gdbarch
, int num
, int eh_frame_p
)
3140 /* GCC releases before 3.4 use GCC internal register numbering in
3141 .debug_frame (and .debug_info, et cetera). The numbering is
3142 different from the standard SysV numbering for everything except
3143 for GPRs and FPRs. We can not detect this problem in most cases
3144 - to get accurate debug info for variables living in lr, ctr, v0,
3145 et cetera, use a newer version of GCC. But we must detect
3146 one important case - lr is in column 65 in .debug_frame output,
3149 GCC 3.4, and the "hammer" branch, have a related problem. They
3150 record lr register saves in .debug_frame as 108, but still record
3151 the return column as 65. We fix that up too.
3153 We can do this because 65 is assigned to fpsr, and GCC never
3154 generates debug info referring to it. To add support for
3155 handwritten debug info that restores fpsr, we would need to add a
3156 producer version check to this. */
3165 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3166 internal register numbering; translate that to the standard DWARF2
3167 register numbering. */
3168 if (0 <= num
&& num
<= 63) /* r0-r31,fp0-fp31 */
3170 else if (68 <= num
&& num
<= 75) /* cr0-cr8 */
3171 return num
- 68 + 86;
3172 else if (77 <= num
&& num
<= 108) /* vr0-vr31 */
3173 return num
- 77 + 1124;
3185 case 109: /* vrsave */
3187 case 110: /* vscr */
3189 case 111: /* spe_acc */
3191 case 112: /* spefscr */
3199 /* Handling the various POWER/PowerPC variants. */
3201 /* Information about a particular processor variant. */
3205 /* Name of this variant. */
3208 /* English description of the variant. */
3209 const char *description
;
3211 /* bfd_arch_info.arch corresponding to variant. */
3212 enum bfd_architecture arch
;
3214 /* bfd_arch_info.mach corresponding to variant. */
3217 /* Target description for this variant. */
3218 struct target_desc
**tdesc
;
3221 static struct variant variants
[] =
3223 {"powerpc", "PowerPC user-level", bfd_arch_powerpc
,
3224 bfd_mach_ppc
, &tdesc_powerpc_altivec32
},
3225 {"power", "POWER user-level", bfd_arch_rs6000
,
3226 bfd_mach_rs6k
, &tdesc_rs6000
},
3227 {"403", "IBM PowerPC 403", bfd_arch_powerpc
,
3228 bfd_mach_ppc_403
, &tdesc_powerpc_403
},
3229 {"405", "IBM PowerPC 405", bfd_arch_powerpc
,
3230 bfd_mach_ppc_405
, &tdesc_powerpc_405
},
3231 {"601", "Motorola PowerPC 601", bfd_arch_powerpc
,
3232 bfd_mach_ppc_601
, &tdesc_powerpc_601
},
3233 {"602", "Motorola PowerPC 602", bfd_arch_powerpc
,
3234 bfd_mach_ppc_602
, &tdesc_powerpc_602
},
3235 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc
,
3236 bfd_mach_ppc_603
, &tdesc_powerpc_603
},
3237 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc
,
3238 604, &tdesc_powerpc_604
},
3239 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc
,
3240 bfd_mach_ppc_403gc
, &tdesc_powerpc_403gc
},
3241 {"505", "Motorola PowerPC 505", bfd_arch_powerpc
,
3242 bfd_mach_ppc_505
, &tdesc_powerpc_505
},
3243 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc
,
3244 bfd_mach_ppc_860
, &tdesc_powerpc_860
},
3245 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc
,
3246 bfd_mach_ppc_750
, &tdesc_powerpc_750
},
3247 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc
,
3248 bfd_mach_ppc_7400
, &tdesc_powerpc_7400
},
3249 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc
,
3250 bfd_mach_ppc_e500
, &tdesc_powerpc_e500
},
3253 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc
,
3254 bfd_mach_ppc64
, &tdesc_powerpc_altivec64
},
3255 {"620", "Motorola PowerPC 620", bfd_arch_powerpc
,
3256 bfd_mach_ppc_620
, &tdesc_powerpc_64
},
3257 {"630", "Motorola PowerPC 630", bfd_arch_powerpc
,
3258 bfd_mach_ppc_630
, &tdesc_powerpc_64
},
3259 {"a35", "PowerPC A35", bfd_arch_powerpc
,
3260 bfd_mach_ppc_a35
, &tdesc_powerpc_64
},
3261 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc
,
3262 bfd_mach_ppc_rs64ii
, &tdesc_powerpc_64
},
3263 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc
,
3264 bfd_mach_ppc_rs64iii
, &tdesc_powerpc_64
},
3266 /* FIXME: I haven't checked the register sets of the following. */
3267 {"rs1", "IBM POWER RS1", bfd_arch_rs6000
,
3268 bfd_mach_rs6k_rs1
, &tdesc_rs6000
},
3269 {"rsc", "IBM POWER RSC", bfd_arch_rs6000
,
3270 bfd_mach_rs6k_rsc
, &tdesc_rs6000
},
3271 {"rs2", "IBM POWER RS2", bfd_arch_rs6000
,
3272 bfd_mach_rs6k_rs2
, &tdesc_rs6000
},
3274 {0, 0, (enum bfd_architecture
) 0, 0, 0}
3277 /* Return the variant corresponding to architecture ARCH and machine number
3278 MACH. If no such variant exists, return null. */
3280 static const struct variant
*
3281 find_variant_by_arch (enum bfd_architecture arch
, unsigned long mach
)
3283 const struct variant
*v
;
3285 for (v
= variants
; v
->name
; v
++)
3286 if (arch
== v
->arch
&& mach
== v
->mach
)
3294 rs6000_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
3296 return frame_unwind_register_unsigned (next_frame
,
3297 gdbarch_pc_regnum (gdbarch
));
3300 static struct frame_id
3301 rs6000_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
3303 return frame_id_build (get_frame_register_unsigned
3304 (this_frame
, gdbarch_sp_regnum (gdbarch
)),
3305 get_frame_pc (this_frame
));
3308 struct rs6000_frame_cache
3311 CORE_ADDR initial_sp
;
3312 struct trad_frame_saved_reg
*saved_regs
;
3314 /* Set BASE_P to true if this frame cache is properly initialized.
3315 Otherwise set to false because some registers or memory cannot
3318 /* Cache PC for building unavailable frame. */
3322 static struct rs6000_frame_cache
*
3323 rs6000_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3325 struct rs6000_frame_cache
*cache
;
3326 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3327 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3328 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
3329 struct rs6000_framedata fdata
;
3330 int wordsize
= tdep
->wordsize
;
3331 CORE_ADDR func
= 0, pc
= 0;
3333 if ((*this_cache
) != NULL
)
3334 return (struct rs6000_frame_cache
*) (*this_cache
);
3335 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3336 (*this_cache
) = cache
;
3338 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3342 func
= get_frame_func (this_frame
);
3344 pc
= get_frame_pc (this_frame
);
3345 skip_prologue (gdbarch
, func
, pc
, &fdata
);
3347 /* Figure out the parent's stack pointer. */
3349 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3350 address of the current frame. Things might be easier if the
3351 ->frame pointed to the outer-most address of the frame. In
3352 the mean time, the address of the prev frame is used as the
3353 base address of this frame. */
3354 cache
->base
= get_frame_register_unsigned
3355 (this_frame
, gdbarch_sp_regnum (gdbarch
));
3357 CATCH (ex
, RETURN_MASK_ERROR
)
3359 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3360 throw_exception (ex
);
3361 return (struct rs6000_frame_cache
*) (*this_cache
);
3365 /* If the function appears to be frameless, check a couple of likely
3366 indicators that we have simply failed to find the frame setup.
3367 Two common cases of this are missing symbols (i.e.
3368 get_frame_func returns the wrong address or 0), and assembly
3369 stubs which have a fast exit path but set up a frame on the slow
3372 If the LR appears to return to this function, then presume that
3373 we have an ABI compliant frame that we failed to find. */
3374 if (fdata
.frameless
&& fdata
.lr_offset
== 0)
3379 saved_lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3380 if (func
== 0 && saved_lr
== pc
)
3384 CORE_ADDR saved_func
= get_pc_function_start (saved_lr
);
3385 if (func
== saved_func
)
3391 fdata
.frameless
= 0;
3392 fdata
.lr_offset
= tdep
->lr_frame_offset
;
3396 if (!fdata
.frameless
)
3398 /* Frameless really means stackless. */
3401 if (safe_read_memory_unsigned_integer (cache
->base
, wordsize
,
3402 byte_order
, &backchain
))
3403 cache
->base
= (CORE_ADDR
) backchain
;
3406 trad_frame_set_value (cache
->saved_regs
,
3407 gdbarch_sp_regnum (gdbarch
), cache
->base
);
3409 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3410 All fpr's from saved_fpr to fp31 are saved. */
3412 if (fdata
.saved_fpr
>= 0)
3415 CORE_ADDR fpr_addr
= cache
->base
+ fdata
.fpr_offset
;
3417 /* If skip_prologue says floating-point registers were saved,
3418 but the current architecture has no floating-point registers,
3419 then that's strange. But we have no indices to even record
3420 the addresses under, so we just ignore it. */
3421 if (ppc_floating_point_unit_p (gdbarch
))
3422 for (i
= fdata
.saved_fpr
; i
< ppc_num_fprs
; i
++)
3424 cache
->saved_regs
[tdep
->ppc_fp0_regnum
+ i
].addr
= fpr_addr
;
3429 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3430 All gpr's from saved_gpr to gpr31 are saved (except during the
3433 if (fdata
.saved_gpr
>= 0)
3436 CORE_ADDR gpr_addr
= cache
->base
+ fdata
.gpr_offset
;
3437 for (i
= fdata
.saved_gpr
; i
< ppc_num_gprs
; i
++)
3439 if (fdata
.gpr_mask
& (1U << i
))
3440 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= gpr_addr
;
3441 gpr_addr
+= wordsize
;
3445 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3446 All vr's from saved_vr to vr31 are saved. */
3447 if (tdep
->ppc_vr0_regnum
!= -1 && tdep
->ppc_vrsave_regnum
!= -1)
3449 if (fdata
.saved_vr
>= 0)
3452 CORE_ADDR vr_addr
= cache
->base
+ fdata
.vr_offset
;
3453 for (i
= fdata
.saved_vr
; i
< 32; i
++)
3455 cache
->saved_regs
[tdep
->ppc_vr0_regnum
+ i
].addr
= vr_addr
;
3456 vr_addr
+= register_size (gdbarch
, tdep
->ppc_vr0_regnum
);
3461 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3462 All vr's from saved_ev to ev31 are saved. ????? */
3463 if (tdep
->ppc_ev0_regnum
!= -1)
3465 if (fdata
.saved_ev
>= 0)
3468 CORE_ADDR ev_addr
= cache
->base
+ fdata
.ev_offset
;
3469 CORE_ADDR off
= (byte_order
== BFD_ENDIAN_BIG
? 4 : 0);
3471 for (i
= fdata
.saved_ev
; i
< ppc_num_gprs
; i
++)
3473 cache
->saved_regs
[tdep
->ppc_ev0_regnum
+ i
].addr
= ev_addr
;
3474 cache
->saved_regs
[tdep
->ppc_gp0_regnum
+ i
].addr
= ev_addr
+ off
;
3475 ev_addr
+= register_size (gdbarch
, tdep
->ppc_ev0_regnum
);
3480 /* If != 0, fdata.cr_offset is the offset from the frame that
3482 if (fdata
.cr_offset
!= 0)
3483 cache
->saved_regs
[tdep
->ppc_cr_regnum
].addr
3484 = cache
->base
+ fdata
.cr_offset
;
3486 /* If != 0, fdata.lr_offset is the offset from the frame that
3488 if (fdata
.lr_offset
!= 0)
3489 cache
->saved_regs
[tdep
->ppc_lr_regnum
].addr
3490 = cache
->base
+ fdata
.lr_offset
;
3491 else if (fdata
.lr_register
!= -1)
3492 cache
->saved_regs
[tdep
->ppc_lr_regnum
].realreg
= fdata
.lr_register
;
3493 /* The PC is found in the link register. */
3494 cache
->saved_regs
[gdbarch_pc_regnum (gdbarch
)] =
3495 cache
->saved_regs
[tdep
->ppc_lr_regnum
];
3497 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3498 holds the VRSAVE. */
3499 if (fdata
.vrsave_offset
!= 0)
3500 cache
->saved_regs
[tdep
->ppc_vrsave_regnum
].addr
3501 = cache
->base
+ fdata
.vrsave_offset
;
3503 if (fdata
.alloca_reg
< 0)
3504 /* If no alloca register used, then fi->frame is the value of the
3505 %sp for this frame, and it is good enough. */
3507 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3510 = get_frame_register_unsigned (this_frame
, fdata
.alloca_reg
);
3517 rs6000_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3518 struct frame_id
*this_id
)
3520 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3525 (*this_id
) = frame_id_build_unavailable_stack (info
->pc
);
3529 /* This marks the outermost frame. */
3530 if (info
->base
== 0)
3533 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3536 static struct value
*
3537 rs6000_frame_prev_register (struct frame_info
*this_frame
,
3538 void **this_cache
, int regnum
)
3540 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3542 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3545 static const struct frame_unwind rs6000_frame_unwind
=
3548 default_frame_unwind_stop_reason
,
3549 rs6000_frame_this_id
,
3550 rs6000_frame_prev_register
,
3552 default_frame_sniffer
3555 /* Allocate and initialize a frame cache for an epilogue frame.
3556 SP is restored and prev-PC is stored in LR. */
3558 static struct rs6000_frame_cache
*
3559 rs6000_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3561 struct rs6000_frame_cache
*cache
;
3562 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3563 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3566 return (struct rs6000_frame_cache
*) *this_cache
;
3568 cache
= FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache
);
3569 (*this_cache
) = cache
;
3570 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3574 /* At this point the stack looks as if we just entered the
3575 function, and the return address is stored in LR. */
3578 sp
= get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
3579 lr
= get_frame_register_unsigned (this_frame
, tdep
->ppc_lr_regnum
);
3582 cache
->initial_sp
= sp
;
3584 trad_frame_set_value (cache
->saved_regs
,
3585 gdbarch_pc_regnum (gdbarch
), lr
);
3587 CATCH (ex
, RETURN_MASK_ERROR
)
3589 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
3590 throw_exception (ex
);
3597 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3598 Return the frame ID of an epilogue frame. */
3601 rs6000_epilogue_frame_this_id (struct frame_info
*this_frame
,
3602 void **this_cache
, struct frame_id
*this_id
)
3605 struct rs6000_frame_cache
*info
=
3606 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3608 pc
= get_frame_func (this_frame
);
3609 if (info
->base
== 0)
3610 (*this_id
) = frame_id_build_unavailable_stack (pc
);
3612 (*this_id
) = frame_id_build (info
->base
, pc
);
3615 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3616 Return the register value of REGNUM in previous frame. */
3618 static struct value
*
3619 rs6000_epilogue_frame_prev_register (struct frame_info
*this_frame
,
3620 void **this_cache
, int regnum
)
3622 struct rs6000_frame_cache
*info
=
3623 rs6000_epilogue_frame_cache (this_frame
, this_cache
);
3624 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3627 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3628 Check whether this an epilogue frame. */
3631 rs6000_epilogue_frame_sniffer (const struct frame_unwind
*self
,
3632 struct frame_info
*this_frame
,
3633 void **this_prologue_cache
)
3635 if (frame_relative_level (this_frame
) == 0)
3636 return rs6000_in_function_epilogue_frame_p (this_frame
,
3637 get_frame_arch (this_frame
),
3638 get_frame_pc (this_frame
));
3643 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3644 a function without debug information. */
3646 static const struct frame_unwind rs6000_epilogue_frame_unwind
=
3649 default_frame_unwind_stop_reason
,
3650 rs6000_epilogue_frame_this_id
, rs6000_epilogue_frame_prev_register
,
3652 rs6000_epilogue_frame_sniffer
3657 rs6000_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
3659 struct rs6000_frame_cache
*info
= rs6000_frame_cache (this_frame
,
3661 return info
->initial_sp
;
3664 static const struct frame_base rs6000_frame_base
= {
3665 &rs6000_frame_unwind
,
3666 rs6000_frame_base_address
,
3667 rs6000_frame_base_address
,
3668 rs6000_frame_base_address
3671 static const struct frame_base
*
3672 rs6000_frame_base_sniffer (struct frame_info
*this_frame
)
3674 return &rs6000_frame_base
;
3677 /* DWARF-2 frame support. Used to handle the detection of
3678 clobbered registers during function calls. */
3681 ppc_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
3682 struct dwarf2_frame_state_reg
*reg
,
3683 struct frame_info
*this_frame
)
3685 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3687 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3688 non-volatile registers. We will use the same code for both. */
3690 /* Call-saved GP registers. */
3691 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 14
3692 && regnum
<= tdep
->ppc_gp0_regnum
+ 31)
3693 || (regnum
== tdep
->ppc_gp0_regnum
+ 1))
3694 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3696 /* Call-clobbered GP registers. */
3697 if ((regnum
>= tdep
->ppc_gp0_regnum
+ 3
3698 && regnum
<= tdep
->ppc_gp0_regnum
+ 12)
3699 || (regnum
== tdep
->ppc_gp0_regnum
))
3700 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3702 /* Deal with FP registers, if supported. */
3703 if (tdep
->ppc_fp0_regnum
>= 0)
3705 /* Call-saved FP registers. */
3706 if ((regnum
>= tdep
->ppc_fp0_regnum
+ 14
3707 && regnum
<= tdep
->ppc_fp0_regnum
+ 31))
3708 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3710 /* Call-clobbered FP registers. */
3711 if ((regnum
>= tdep
->ppc_fp0_regnum
3712 && regnum
<= tdep
->ppc_fp0_regnum
+ 13))
3713 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3716 /* Deal with ALTIVEC registers, if supported. */
3717 if (tdep
->ppc_vr0_regnum
> 0 && tdep
->ppc_vrsave_regnum
> 0)
3719 /* Call-saved Altivec registers. */
3720 if ((regnum
>= tdep
->ppc_vr0_regnum
+ 20
3721 && regnum
<= tdep
->ppc_vr0_regnum
+ 31)
3722 || regnum
== tdep
->ppc_vrsave_regnum
)
3723 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
3725 /* Call-clobbered Altivec registers. */
3726 if ((regnum
>= tdep
->ppc_vr0_regnum
3727 && regnum
<= tdep
->ppc_vr0_regnum
+ 19))
3728 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
3731 /* Handle PC register and Stack Pointer correctly. */
3732 if (regnum
== gdbarch_pc_regnum (gdbarch
))
3733 reg
->how
= DWARF2_FRAME_REG_RA
;
3734 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
3735 reg
->how
= DWARF2_FRAME_REG_CFA
;
3739 /* Return true if a .gnu_attributes section exists in BFD and it
3740 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3741 section exists in BFD and it indicates that SPE extensions are in
3742 use. Check the .gnu.attributes section first, as the binary might be
3743 compiled for SPE, but not actually using SPE instructions. */
3746 bfd_uses_spe_extensions (bfd
*abfd
)
3749 gdb_byte
*contents
= NULL
;
3759 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3760 could be using the SPE vector abi without actually using any spe
3761 bits whatsoever. But it's close enough for now. */
3762 vector_abi
= bfd_elf_get_obj_attr_int (abfd
, OBJ_ATTR_GNU
,
3763 Tag_GNU_Power_ABI_Vector
);
3764 if (vector_abi
== 3)
3768 sect
= bfd_get_section_by_name (abfd
, ".PPC.EMB.apuinfo");
3772 size
= bfd_get_section_size (sect
);
3773 contents
= (gdb_byte
*) xmalloc (size
);
3774 if (!bfd_get_section_contents (abfd
, sect
, contents
, 0, size
))
3780 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3786 char name[name_len rounded up to 4-byte alignment];
3787 char data[data_len];
3790 Technically, there's only supposed to be one such structure in a
3791 given apuinfo section, but the linker is not always vigilant about
3792 merging apuinfo sections from input files. Just go ahead and parse
3793 them all, exiting early when we discover the binary uses SPE
3796 It's not specified in what endianness the information in this
3797 section is stored. Assume that it's the endianness of the BFD. */
3801 unsigned int name_len
;
3802 unsigned int data_len
;
3805 /* If we can't read the first three fields, we're done. */
3809 name_len
= bfd_get_32 (abfd
, ptr
);
3810 name_len
= (name_len
+ 3) & ~3U; /* Round to 4 bytes. */
3811 data_len
= bfd_get_32 (abfd
, ptr
+ 4);
3812 type
= bfd_get_32 (abfd
, ptr
+ 8);
3815 /* The name must be "APUinfo\0". */
3817 && strcmp ((const char *) ptr
, "APUinfo") != 0)
3821 /* The type must be 2. */
3825 /* The data is stored as a series of uint32. The upper half of
3826 each uint32 indicates the particular APU used and the lower
3827 half indicates the revision of that APU. We just care about
3830 /* Not 4-byte quantities. */
3836 unsigned int apuinfo
= bfd_get_32 (abfd
, ptr
);
3837 unsigned int apu
= apuinfo
>> 16;
3841 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3843 if (apu
== 0x100 || apu
== 0x101)
3858 /* These are macros for parsing instruction fields (I.1.6.28) */
3860 #define PPC_FIELD(value, from, len) \
3861 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3862 #define PPC_SEXT(v, bs) \
3863 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3864 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3865 - ((CORE_ADDR) 1 << ((bs) - 1)))
3866 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3867 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3868 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3869 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3870 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3871 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3872 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3873 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3874 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3875 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3876 | (PPC_FIELD (insn, 16, 5) << 5))
3877 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3878 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3879 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3880 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3881 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3882 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3883 #define PPC_OE(insn) PPC_BIT (insn, 21)
3884 #define PPC_RC(insn) PPC_BIT (insn, 31)
3885 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3886 #define PPC_LK(insn) PPC_BIT (insn, 31)
3887 #define PPC_TX(insn) PPC_BIT (insn, 31)
3888 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3890 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3891 #define PPC_XER_NB(xer) (xer & 0x7f)
3893 /* Record Vector-Scalar Registers.
3894 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3895 Otherwise, it's just a VR register. Record them accordingly. */
3898 ppc_record_vsr (struct regcache
*regcache
, struct gdbarch_tdep
*tdep
, int vsr
)
3900 if (vsr
< 0 || vsr
>= 64)
3905 if (tdep
->ppc_vr0_regnum
>= 0)
3906 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vr0_regnum
+ vsr
- 32);
3910 if (tdep
->ppc_fp0_regnum
>= 0)
3911 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fp0_regnum
+ vsr
);
3912 if (tdep
->ppc_vsr0_upper_regnum
>= 0)
3913 record_full_arch_list_add_reg (regcache
,
3914 tdep
->ppc_vsr0_upper_regnum
+ vsr
);
3920 /* Parse and record instructions primary opcode-4 at ADDR.
3921 Return 0 if successful. */
3924 ppc_process_record_op4 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3925 CORE_ADDR addr
, uint32_t insn
)
3927 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3928 int ext
= PPC_FIELD (insn
, 21, 11);
3929 int vra
= PPC_FIELD (insn
, 11, 5);
3933 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3934 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3935 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3936 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3937 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
3939 case 42: /* Vector Select */
3940 case 43: /* Vector Permute */
3941 case 59: /* Vector Permute Right-indexed */
3942 case 44: /* Vector Shift Left Double by Octet Immediate */
3943 case 45: /* Vector Permute and Exclusive-OR */
3944 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3945 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3946 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3947 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3948 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3949 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3950 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3951 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3952 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3953 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3954 case 46: /* Vector Multiply-Add Single-Precision */
3955 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3956 record_full_arch_list_add_reg (regcache
,
3957 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3960 case 48: /* Multiply-Add High Doubleword */
3961 case 49: /* Multiply-Add High Doubleword Unsigned */
3962 case 51: /* Multiply-Add Low Doubleword */
3963 record_full_arch_list_add_reg (regcache
,
3964 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
3968 switch ((ext
& 0x1ff))
3971 if (vra
!= 0 /* Decimal Convert To Signed Quadword */
3972 && vra
!= 2 /* Decimal Convert From Signed Quadword */
3973 && vra
!= 4 /* Decimal Convert To Zoned */
3974 && vra
!= 5 /* Decimal Convert To National */
3975 && vra
!= 6 /* Decimal Convert From Zoned */
3976 && vra
!= 7 /* Decimal Convert From National */
3977 && vra
!= 31) /* Decimal Set Sign */
3979 /* 5.16 Decimal Integer Arithmetic Instructions */
3980 case 1: /* Decimal Add Modulo */
3981 case 65: /* Decimal Subtract Modulo */
3983 case 193: /* Decimal Shift */
3984 case 129: /* Decimal Unsigned Shift */
3985 case 449: /* Decimal Shift and Round */
3987 case 257: /* Decimal Truncate */
3988 case 321: /* Decimal Unsigned Truncate */
3990 /* Bit-21 should be set. */
3991 if (!PPC_BIT (insn
, 21))
3994 record_full_arch_list_add_reg (regcache
,
3995 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
3996 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4000 /* Bit-21 is used for RC */
4001 switch (ext
& 0x3ff)
4003 case 6: /* Vector Compare Equal To Unsigned Byte */
4004 case 70: /* Vector Compare Equal To Unsigned Halfword */
4005 case 134: /* Vector Compare Equal To Unsigned Word */
4006 case 199: /* Vector Compare Equal To Unsigned Doubleword */
4007 case 774: /* Vector Compare Greater Than Signed Byte */
4008 case 838: /* Vector Compare Greater Than Signed Halfword */
4009 case 902: /* Vector Compare Greater Than Signed Word */
4010 case 967: /* Vector Compare Greater Than Signed Doubleword */
4011 case 518: /* Vector Compare Greater Than Unsigned Byte */
4012 case 646: /* Vector Compare Greater Than Unsigned Word */
4013 case 582: /* Vector Compare Greater Than Unsigned Halfword */
4014 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
4015 case 966: /* Vector Compare Bounds Single-Precision */
4016 case 198: /* Vector Compare Equal To Single-Precision */
4017 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
4018 case 710: /* Vector Compare Greater Than Single-Precision */
4019 case 7: /* Vector Compare Not Equal Byte */
4020 case 71: /* Vector Compare Not Equal Halfword */
4021 case 135: /* Vector Compare Not Equal Word */
4022 case 263: /* Vector Compare Not Equal or Zero Byte */
4023 case 327: /* Vector Compare Not Equal or Zero Halfword */
4024 case 391: /* Vector Compare Not Equal or Zero Word */
4026 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4027 record_full_arch_list_add_reg (regcache
,
4028 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4036 case 0: /* Vector Count Leading Zero Least-Significant Bits
4038 case 1: /* Vector Count Trailing Zero Least-Significant Bits
4040 record_full_arch_list_add_reg (regcache
,
4041 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4044 case 6: /* Vector Negate Word */
4045 case 7: /* Vector Negate Doubleword */
4046 case 8: /* Vector Parity Byte Word */
4047 case 9: /* Vector Parity Byte Doubleword */
4048 case 10: /* Vector Parity Byte Quadword */
4049 case 16: /* Vector Extend Sign Byte To Word */
4050 case 17: /* Vector Extend Sign Halfword To Word */
4051 case 24: /* Vector Extend Sign Byte To Doubleword */
4052 case 25: /* Vector Extend Sign Halfword To Doubleword */
4053 case 26: /* Vector Extend Sign Word To Doubleword */
4054 case 28: /* Vector Count Trailing Zeros Byte */
4055 case 29: /* Vector Count Trailing Zeros Halfword */
4056 case 30: /* Vector Count Trailing Zeros Word */
4057 case 31: /* Vector Count Trailing Zeros Doubleword */
4058 record_full_arch_list_add_reg (regcache
,
4059 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4066 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4067 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4068 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4069 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4070 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4071 case 462: /* Vector Pack Signed Word Signed Saturate */
4072 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4073 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4074 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4075 case 512: /* Vector Add Unsigned Byte Saturate */
4076 case 576: /* Vector Add Unsigned Halfword Saturate */
4077 case 640: /* Vector Add Unsigned Word Saturate */
4078 case 768: /* Vector Add Signed Byte Saturate */
4079 case 832: /* Vector Add Signed Halfword Saturate */
4080 case 896: /* Vector Add Signed Word Saturate */
4081 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4082 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4083 case 1664: /* Vector Subtract Unsigned Word Saturate */
4084 case 1792: /* Vector Subtract Signed Byte Saturate */
4085 case 1856: /* Vector Subtract Signed Halfword Saturate */
4086 case 1920: /* Vector Subtract Signed Word Saturate */
4088 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4089 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4090 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4091 case 1672: /* Vector Sum across Half Signed Word Saturate */
4092 case 1928: /* Vector Sum across Signed Word Saturate */
4093 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4094 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4095 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4097 case 12: /* Vector Merge High Byte */
4098 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4099 case 76: /* Vector Merge High Halfword */
4100 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4101 case 140: /* Vector Merge High Word */
4102 case 268: /* Vector Merge Low Byte */
4103 case 332: /* Vector Merge Low Halfword */
4104 case 396: /* Vector Merge Low Word */
4105 case 526: /* Vector Unpack High Signed Byte */
4106 case 590: /* Vector Unpack High Signed Halfword */
4107 case 654: /* Vector Unpack Low Signed Byte */
4108 case 718: /* Vector Unpack Low Signed Halfword */
4109 case 782: /* Vector Pack Pixel */
4110 case 846: /* Vector Unpack High Pixel */
4111 case 974: /* Vector Unpack Low Pixel */
4112 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4113 case 1614: /* Vector Unpack High Signed Word */
4114 case 1676: /* Vector Merge Odd Word */
4115 case 1742: /* Vector Unpack Low Signed Word */
4116 case 1932: /* Vector Merge Even Word */
4117 case 524: /* Vector Splat Byte */
4118 case 588: /* Vector Splat Halfword */
4119 case 652: /* Vector Splat Word */
4120 case 780: /* Vector Splat Immediate Signed Byte */
4121 case 844: /* Vector Splat Immediate Signed Halfword */
4122 case 908: /* Vector Splat Immediate Signed Word */
4123 case 452: /* Vector Shift Left */
4124 case 708: /* Vector Shift Right */
4125 case 1036: /* Vector Shift Left by Octet */
4126 case 1100: /* Vector Shift Right by Octet */
4127 case 0: /* Vector Add Unsigned Byte Modulo */
4128 case 64: /* Vector Add Unsigned Halfword Modulo */
4129 case 128: /* Vector Add Unsigned Word Modulo */
4130 case 192: /* Vector Add Unsigned Doubleword Modulo */
4131 case 256: /* Vector Add Unsigned Quadword Modulo */
4132 case 320: /* Vector Add & write Carry Unsigned Quadword */
4133 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4134 case 8: /* Vector Multiply Odd Unsigned Byte */
4135 case 72: /* Vector Multiply Odd Unsigned Halfword */
4136 case 136: /* Vector Multiply Odd Unsigned Word */
4137 case 264: /* Vector Multiply Odd Signed Byte */
4138 case 328: /* Vector Multiply Odd Signed Halfword */
4139 case 392: /* Vector Multiply Odd Signed Word */
4140 case 520: /* Vector Multiply Even Unsigned Byte */
4141 case 584: /* Vector Multiply Even Unsigned Halfword */
4142 case 648: /* Vector Multiply Even Unsigned Word */
4143 case 776: /* Vector Multiply Even Signed Byte */
4144 case 840: /* Vector Multiply Even Signed Halfword */
4145 case 904: /* Vector Multiply Even Signed Word */
4146 case 137: /* Vector Multiply Unsigned Word Modulo */
4147 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4148 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4149 case 1152: /* Vector Subtract Unsigned Word Modulo */
4150 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4151 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4152 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4153 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4154 case 1282: /* Vector Average Signed Byte */
4155 case 1346: /* Vector Average Signed Halfword */
4156 case 1410: /* Vector Average Signed Word */
4157 case 1026: /* Vector Average Unsigned Byte */
4158 case 1090: /* Vector Average Unsigned Halfword */
4159 case 1154: /* Vector Average Unsigned Word */
4160 case 258: /* Vector Maximum Signed Byte */
4161 case 322: /* Vector Maximum Signed Halfword */
4162 case 386: /* Vector Maximum Signed Word */
4163 case 450: /* Vector Maximum Signed Doubleword */
4164 case 2: /* Vector Maximum Unsigned Byte */
4165 case 66: /* Vector Maximum Unsigned Halfword */
4166 case 130: /* Vector Maximum Unsigned Word */
4167 case 194: /* Vector Maximum Unsigned Doubleword */
4168 case 770: /* Vector Minimum Signed Byte */
4169 case 834: /* Vector Minimum Signed Halfword */
4170 case 898: /* Vector Minimum Signed Word */
4171 case 962: /* Vector Minimum Signed Doubleword */
4172 case 514: /* Vector Minimum Unsigned Byte */
4173 case 578: /* Vector Minimum Unsigned Halfword */
4174 case 642: /* Vector Minimum Unsigned Word */
4175 case 706: /* Vector Minimum Unsigned Doubleword */
4176 case 1028: /* Vector Logical AND */
4177 case 1668: /* Vector Logical Equivalent */
4178 case 1092: /* Vector Logical AND with Complement */
4179 case 1412: /* Vector Logical NAND */
4180 case 1348: /* Vector Logical OR with Complement */
4181 case 1156: /* Vector Logical OR */
4182 case 1284: /* Vector Logical NOR */
4183 case 1220: /* Vector Logical XOR */
4184 case 4: /* Vector Rotate Left Byte */
4185 case 132: /* Vector Rotate Left Word VX-form */
4186 case 68: /* Vector Rotate Left Halfword */
4187 case 196: /* Vector Rotate Left Doubleword */
4188 case 260: /* Vector Shift Left Byte */
4189 case 388: /* Vector Shift Left Word */
4190 case 324: /* Vector Shift Left Halfword */
4191 case 1476: /* Vector Shift Left Doubleword */
4192 case 516: /* Vector Shift Right Byte */
4193 case 644: /* Vector Shift Right Word */
4194 case 580: /* Vector Shift Right Halfword */
4195 case 1732: /* Vector Shift Right Doubleword */
4196 case 772: /* Vector Shift Right Algebraic Byte */
4197 case 900: /* Vector Shift Right Algebraic Word */
4198 case 836: /* Vector Shift Right Algebraic Halfword */
4199 case 964: /* Vector Shift Right Algebraic Doubleword */
4200 case 10: /* Vector Add Single-Precision */
4201 case 74: /* Vector Subtract Single-Precision */
4202 case 1034: /* Vector Maximum Single-Precision */
4203 case 1098: /* Vector Minimum Single-Precision */
4204 case 842: /* Vector Convert From Signed Fixed-Point Word */
4205 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4206 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4207 case 522: /* Vector Round to Single-Precision Integer Nearest */
4208 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4209 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4210 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4211 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4212 case 266: /* Vector Reciprocal Estimate Single-Precision */
4213 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4214 case 1288: /* Vector AES Cipher */
4215 case 1289: /* Vector AES Cipher Last */
4216 case 1352: /* Vector AES Inverse Cipher */
4217 case 1353: /* Vector AES Inverse Cipher Last */
4218 case 1480: /* Vector AES SubBytes */
4219 case 1730: /* Vector SHA-512 Sigma Doubleword */
4220 case 1666: /* Vector SHA-256 Sigma Word */
4221 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4222 case 1160: /* Vector Polynomial Multiply-Sum Word */
4223 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4224 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4225 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4226 case 1794: /* Vector Count Leading Zeros Byte */
4227 case 1858: /* Vector Count Leading Zeros Halfword */
4228 case 1922: /* Vector Count Leading Zeros Word */
4229 case 1986: /* Vector Count Leading Zeros Doubleword */
4230 case 1795: /* Vector Population Count Byte */
4231 case 1859: /* Vector Population Count Halfword */
4232 case 1923: /* Vector Population Count Word */
4233 case 1987: /* Vector Population Count Doubleword */
4234 case 1356: /* Vector Bit Permute Quadword */
4235 case 1484: /* Vector Bit Permute Doubleword */
4236 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4237 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4239 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4240 case 65: /* Vector Multiply-by-10 Extended & write Carry
4241 Unsigned Quadword */
4242 case 1027: /* Vector Absolute Difference Unsigned Byte */
4243 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4244 case 1155: /* Vector Absolute Difference Unsigned Word */
4245 case 1796: /* Vector Shift Right Variable */
4246 case 1860: /* Vector Shift Left Variable */
4247 case 133: /* Vector Rotate Left Word then Mask Insert */
4248 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4249 case 389: /* Vector Rotate Left Word then AND with Mask */
4250 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4251 case 525: /* Vector Extract Unsigned Byte */
4252 case 589: /* Vector Extract Unsigned Halfword */
4253 case 653: /* Vector Extract Unsigned Word */
4254 case 717: /* Vector Extract Doubleword */
4255 case 781: /* Vector Insert Byte */
4256 case 845: /* Vector Insert Halfword */
4257 case 909: /* Vector Insert Word */
4258 case 973: /* Vector Insert Doubleword */
4259 record_full_arch_list_add_reg (regcache
,
4260 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4263 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4264 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4265 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4266 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4267 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4268 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4269 record_full_arch_list_add_reg (regcache
,
4270 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4273 case 1604: /* Move To Vector Status and Control Register */
4274 record_full_arch_list_add_reg (regcache
, PPC_VSCR_REGNUM
);
4276 case 1540: /* Move From Vector Status and Control Register */
4277 record_full_arch_list_add_reg (regcache
,
4278 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4280 case 833: /* Decimal Copy Sign */
4281 record_full_arch_list_add_reg (regcache
,
4282 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4283 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4287 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4288 "at %s, 4-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4292 /* Parse and record instructions of primary opcode-19 at ADDR.
4293 Return 0 if successful. */
4296 ppc_process_record_op19 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4297 CORE_ADDR addr
, uint32_t insn
)
4299 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4300 int ext
= PPC_EXTOP (insn
);
4302 switch (ext
& 0x01f)
4304 case 2: /* Add PC Immediate Shifted */
4305 record_full_arch_list_add_reg (regcache
,
4306 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4312 case 0: /* Move Condition Register Field */
4313 case 33: /* Condition Register NOR */
4314 case 129: /* Condition Register AND with Complement */
4315 case 193: /* Condition Register XOR */
4316 case 225: /* Condition Register NAND */
4317 case 257: /* Condition Register AND */
4318 case 289: /* Condition Register Equivalent */
4319 case 417: /* Condition Register OR with Complement */
4320 case 449: /* Condition Register OR */
4321 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4324 case 16: /* Branch Conditional */
4325 case 560: /* Branch Conditional to Branch Target Address Register */
4326 if ((PPC_BO (insn
) & 0x4) == 0)
4327 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4329 case 528: /* Branch Conditional to Count Register */
4331 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4334 case 150: /* Instruction Synchronize */
4339 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4340 "at %s, 19-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4344 /* Parse and record instructions of primary opcode-31 at ADDR.
4345 Return 0 if successful. */
4348 ppc_process_record_op31 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4349 CORE_ADDR addr
, uint32_t insn
)
4351 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4352 int ext
= PPC_EXTOP (insn
);
4354 CORE_ADDR at_dcsz
, ea
= 0;
4355 ULONGEST rb
, ra
, xer
;
4358 /* These instructions have OE bit. */
4359 switch (ext
& 0x1ff)
4361 /* These write RT and XER. Update CR if RC is set. */
4362 case 8: /* Subtract from carrying */
4363 case 10: /* Add carrying */
4364 case 136: /* Subtract from extended */
4365 case 138: /* Add extended */
4366 case 200: /* Subtract from zero extended */
4367 case 202: /* Add to zero extended */
4368 case 232: /* Subtract from minus one extended */
4369 case 234: /* Add to minus one extended */
4370 /* CA is always altered, but SO/OV are only altered when OE=1.
4371 In any case, XER is always altered. */
4372 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4374 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4375 record_full_arch_list_add_reg (regcache
,
4376 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4379 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4380 case 40: /* Subtract from */
4381 case 104: /* Negate */
4382 case 233: /* Multiply low doubleword */
4383 case 235: /* Multiply low word */
4385 case 393: /* Divide Doubleword Extended Unsigned */
4386 case 395: /* Divide Word Extended Unsigned */
4387 case 425: /* Divide Doubleword Extended */
4388 case 427: /* Divide Word Extended */
4389 case 457: /* Divide Doubleword Unsigned */
4390 case 459: /* Divide Word Unsigned */
4391 case 489: /* Divide Doubleword */
4392 case 491: /* Divide Word */
4394 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4396 case 9: /* Multiply High Doubleword Unsigned */
4397 case 11: /* Multiply High Word Unsigned */
4398 case 73: /* Multiply High Doubleword */
4399 case 75: /* Multiply High Word */
4401 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4402 record_full_arch_list_add_reg (regcache
,
4403 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4407 if ((ext
& 0x1f) == 15)
4409 /* Integer Select. bit[16:20] is used for BC. */
4410 record_full_arch_list_add_reg (regcache
,
4411 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4415 if ((ext
& 0xff) == 170)
4417 /* Add Extended using alternate carry bits */
4418 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4419 record_full_arch_list_add_reg (regcache
,
4420 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4426 case 78: /* Determine Leftmost Zero Byte */
4428 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4429 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4430 record_full_arch_list_add_reg (regcache
,
4431 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4434 /* These only write RT. */
4435 case 19: /* Move from condition register */
4436 /* Move From One Condition Register Field */
4437 case 74: /* Add and Generate Sixes */
4438 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4439 case 302: /* Move From Branch History Rolling Buffer */
4440 case 339: /* Move From Special Purpose Register */
4441 case 371: /* Move From Time Base [Phased-Out] */
4442 case 309: /* Load Doubleword Monitored Indexed */
4443 case 128: /* Set Boolean */
4444 case 755: /* Deliver A Random Number */
4445 record_full_arch_list_add_reg (regcache
,
4446 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4449 /* These only write to RA. */
4450 case 51: /* Move From VSR Doubleword */
4451 case 115: /* Move From VSR Word and Zero */
4452 case 122: /* Population count bytes */
4453 case 378: /* Population count words */
4454 case 506: /* Population count doublewords */
4455 case 154: /* Parity Word */
4456 case 186: /* Parity Doubleword */
4457 case 252: /* Bit Permute Doubleword */
4458 case 282: /* Convert Declets To Binary Coded Decimal */
4459 case 314: /* Convert Binary Coded Decimal To Declets */
4460 case 508: /* Compare bytes */
4461 case 307: /* Move From VSR Lower Doubleword */
4462 record_full_arch_list_add_reg (regcache
,
4463 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4466 /* These write CR and optional RA. */
4467 case 792: /* Shift Right Algebraic Word */
4468 case 794: /* Shift Right Algebraic Doubleword */
4469 case 824: /* Shift Right Algebraic Word Immediate */
4470 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4471 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4472 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4473 record_full_arch_list_add_reg (regcache
,
4474 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4476 case 0: /* Compare */
4477 case 32: /* Compare logical */
4478 case 144: /* Move To Condition Register Fields */
4479 /* Move To One Condition Register Field */
4480 case 192: /* Compare Ranged Byte */
4481 case 224: /* Compare Equal Byte */
4482 case 576: /* Move XER to CR Extended */
4483 case 902: /* Paste (should always fail due to single-stepping and
4484 the memory location might not be accessible, so
4486 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4489 /* These write to RT. Update RA if 'update indexed.' */
4490 case 53: /* Load Doubleword with Update Indexed */
4491 case 119: /* Load Byte and Zero with Update Indexed */
4492 case 311: /* Load Halfword and Zero with Update Indexed */
4493 case 55: /* Load Word and Zero with Update Indexed */
4494 case 375: /* Load Halfword Algebraic with Update Indexed */
4495 case 373: /* Load Word Algebraic with Update Indexed */
4496 record_full_arch_list_add_reg (regcache
,
4497 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4499 case 21: /* Load Doubleword Indexed */
4500 case 52: /* Load Byte And Reserve Indexed */
4501 case 116: /* Load Halfword And Reserve Indexed */
4502 case 20: /* Load Word And Reserve Indexed */
4503 case 84: /* Load Doubleword And Reserve Indexed */
4504 case 87: /* Load Byte and Zero Indexed */
4505 case 279: /* Load Halfword and Zero Indexed */
4506 case 23: /* Load Word and Zero Indexed */
4507 case 343: /* Load Halfword Algebraic Indexed */
4508 case 341: /* Load Word Algebraic Indexed */
4509 case 790: /* Load Halfword Byte-Reverse Indexed */
4510 case 534: /* Load Word Byte-Reverse Indexed */
4511 case 532: /* Load Doubleword Byte-Reverse Indexed */
4512 case 582: /* Load Word Atomic */
4513 case 614: /* Load Doubleword Atomic */
4514 case 265: /* Modulo Unsigned Doubleword */
4515 case 777: /* Modulo Signed Doubleword */
4516 case 267: /* Modulo Unsigned Word */
4517 case 779: /* Modulo Signed Word */
4518 record_full_arch_list_add_reg (regcache
,
4519 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
4522 case 597: /* Load String Word Immediate */
4523 case 533: /* Load String Word Indexed */
4532 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4533 nr
= PPC_XER_NB (xer
);
4538 /* If n=0, the contents of register RT are undefined. */
4542 for (i
= 0; i
< nr
; i
++)
4543 record_full_arch_list_add_reg (regcache
,
4544 tdep
->ppc_gp0_regnum
4545 + ((PPC_RT (insn
) + i
) & 0x1f));
4548 case 276: /* Load Quadword And Reserve Indexed */
4549 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
4550 record_full_arch_list_add_reg (regcache
, tmp
);
4551 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4554 /* These write VRT. */
4555 case 6: /* Load Vector for Shift Left Indexed */
4556 case 38: /* Load Vector for Shift Right Indexed */
4557 case 7: /* Load Vector Element Byte Indexed */
4558 case 39: /* Load Vector Element Halfword Indexed */
4559 case 71: /* Load Vector Element Word Indexed */
4560 case 103: /* Load Vector Indexed */
4561 case 359: /* Load Vector Indexed LRU */
4562 record_full_arch_list_add_reg (regcache
,
4563 tdep
->ppc_vr0_regnum
+ PPC_VRT (insn
));
4566 /* These write FRT. Update RA if 'update indexed.' */
4567 case 567: /* Load Floating-Point Single with Update Indexed */
4568 case 631: /* Load Floating-Point Double with Update Indexed */
4569 record_full_arch_list_add_reg (regcache
,
4570 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4572 case 535: /* Load Floating-Point Single Indexed */
4573 case 599: /* Load Floating-Point Double Indexed */
4574 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4575 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4576 record_full_arch_list_add_reg (regcache
,
4577 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4580 case 791: /* Load Floating-Point Double Pair Indexed */
4581 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
4582 record_full_arch_list_add_reg (regcache
, tmp
);
4583 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
4586 case 179: /* Move To VSR Doubleword */
4587 case 211: /* Move To VSR Word Algebraic */
4588 case 243: /* Move To VSR Word and Zero */
4589 case 588: /* Load VSX Scalar Doubleword Indexed */
4590 case 524: /* Load VSX Scalar Single-Precision Indexed */
4591 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4592 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4593 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4594 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4595 case 780: /* Load VSX Vector Word*4 Indexed */
4596 case 268: /* Load VSX Vector Indexed */
4597 case 364: /* Load VSX Vector Word & Splat Indexed */
4598 case 812: /* Load VSX Vector Halfword*8 Indexed */
4599 case 876: /* Load VSX Vector Byte*16 Indexed */
4600 case 269: /* Load VSX Vector with Length */
4601 case 301: /* Load VSX Vector Left-justified with Length */
4602 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4603 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4604 case 403: /* Move To VSR Word & Splat */
4605 case 435: /* Move To VSR Double Doubleword */
4606 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
4609 /* These write RA. Update CR if RC is set. */
4610 case 24: /* Shift Left Word */
4611 case 26: /* Count Leading Zeros Word */
4612 case 27: /* Shift Left Doubleword */
4614 case 58: /* Count Leading Zeros Doubleword */
4615 case 60: /* AND with Complement */
4617 case 284: /* Equivalent */
4619 case 476: /* NAND */
4620 case 412: /* OR with Complement */
4622 case 536: /* Shift Right Word */
4623 case 539: /* Shift Right Doubleword */
4624 case 922: /* Extend Sign Halfword */
4625 case 954: /* Extend Sign Byte */
4626 case 986: /* Extend Sign Word */
4627 case 538: /* Count Trailing Zeros Word */
4628 case 570: /* Count Trailing Zeros Doubleword */
4629 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4630 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4632 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4633 record_full_arch_list_add_reg (regcache
,
4634 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4638 case 181: /* Store Doubleword with Update Indexed */
4639 case 183: /* Store Word with Update Indexed */
4640 case 247: /* Store Byte with Update Indexed */
4641 case 439: /* Store Half Word with Update Indexed */
4642 case 695: /* Store Floating-Point Single with Update Indexed */
4643 case 759: /* Store Floating-Point Double with Update Indexed */
4644 record_full_arch_list_add_reg (regcache
,
4645 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
4647 case 135: /* Store Vector Element Byte Indexed */
4648 case 167: /* Store Vector Element Halfword Indexed */
4649 case 199: /* Store Vector Element Word Indexed */
4650 case 231: /* Store Vector Indexed */
4651 case 487: /* Store Vector Indexed LRU */
4652 case 716: /* Store VSX Scalar Doubleword Indexed */
4653 case 140: /* Store VSX Scalar as Integer Word Indexed */
4654 case 652: /* Store VSX Scalar Single-Precision Indexed */
4655 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4656 case 908: /* Store VSX Vector Word*4 Indexed */
4657 case 149: /* Store Doubleword Indexed */
4658 case 151: /* Store Word Indexed */
4659 case 215: /* Store Byte Indexed */
4660 case 407: /* Store Half Word Indexed */
4661 case 694: /* Store Byte Conditional Indexed */
4662 case 726: /* Store Halfword Conditional Indexed */
4663 case 150: /* Store Word Conditional Indexed */
4664 case 214: /* Store Doubleword Conditional Indexed */
4665 case 182: /* Store Quadword Conditional Indexed */
4666 case 662: /* Store Word Byte-Reverse Indexed */
4667 case 918: /* Store Halfword Byte-Reverse Indexed */
4668 case 660: /* Store Doubleword Byte-Reverse Indexed */
4669 case 663: /* Store Floating-Point Single Indexed */
4670 case 727: /* Store Floating-Point Double Indexed */
4671 case 919: /* Store Floating-Point Double Pair Indexed */
4672 case 983: /* Store Floating-Point as Integer Word Indexed */
4673 case 396: /* Store VSX Vector Indexed */
4674 case 940: /* Store VSX Vector Halfword*8 Indexed */
4675 case 1004: /* Store VSX Vector Byte*16 Indexed */
4676 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4677 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4678 if (ext
== 694 || ext
== 726 || ext
== 150 || ext
== 214 || ext
== 182)
4679 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4682 if (PPC_RA (insn
) != 0)
4683 regcache_raw_read_unsigned (regcache
,
4684 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4685 regcache_raw_read_unsigned (regcache
,
4686 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4691 case 183: /* Store Word with Update Indexed */
4692 case 199: /* Store Vector Element Word Indexed */
4693 case 140: /* Store VSX Scalar as Integer Word Indexed */
4694 case 652: /* Store VSX Scalar Single-Precision Indexed */
4695 case 151: /* Store Word Indexed */
4696 case 150: /* Store Word Conditional Indexed */
4697 case 662: /* Store Word Byte-Reverse Indexed */
4698 case 663: /* Store Floating-Point Single Indexed */
4699 case 695: /* Store Floating-Point Single with Update Indexed */
4700 case 983: /* Store Floating-Point as Integer Word Indexed */
4703 case 247: /* Store Byte with Update Indexed */
4704 case 135: /* Store Vector Element Byte Indexed */
4705 case 215: /* Store Byte Indexed */
4706 case 694: /* Store Byte Conditional Indexed */
4707 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4710 case 439: /* Store Halfword with Update Indexed */
4711 case 167: /* Store Vector Element Halfword Indexed */
4712 case 407: /* Store Halfword Indexed */
4713 case 726: /* Store Halfword Conditional Indexed */
4714 case 918: /* Store Halfword Byte-Reverse Indexed */
4715 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4718 case 181: /* Store Doubleword with Update Indexed */
4719 case 716: /* Store VSX Scalar Doubleword Indexed */
4720 case 149: /* Store Doubleword Indexed */
4721 case 214: /* Store Doubleword Conditional Indexed */
4722 case 660: /* Store Doubleword Byte-Reverse Indexed */
4723 case 727: /* Store Floating-Point Double Indexed */
4724 case 759: /* Store Floating-Point Double with Update Indexed */
4727 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4728 case 908: /* Store VSX Vector Word*4 Indexed */
4729 case 182: /* Store Quadword Conditional Indexed */
4730 case 231: /* Store Vector Indexed */
4731 case 487: /* Store Vector Indexed LRU */
4732 case 919: /* Store Floating-Point Double Pair Indexed */
4733 case 396: /* Store VSX Vector Indexed */
4734 case 940: /* Store VSX Vector Halfword*8 Indexed */
4735 case 1004: /* Store VSX Vector Byte*16 Indexed */
4742 /* Align address for Store Vector instructions. */
4745 case 167: /* Store Vector Element Halfword Indexed */
4746 addr
= addr
& ~0x1ULL
;
4749 case 199: /* Store Vector Element Word Indexed */
4750 addr
= addr
& ~0x3ULL
;
4753 case 231: /* Store Vector Indexed */
4754 case 487: /* Store Vector Indexed LRU */
4755 addr
= addr
& ~0xfULL
;
4759 record_full_arch_list_add_mem (addr
, size
);
4762 case 397: /* Store VSX Vector with Length */
4763 case 429: /* Store VSX Vector Left-justified with Length */
4765 if (PPC_RA (insn
) != 0)
4766 regcache_raw_read_unsigned (regcache
,
4767 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4769 regcache_raw_read_unsigned (regcache
,
4770 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4771 /* Store up to 16 bytes. */
4772 nb
= (rb
& 0xff) > 16 ? 16 : (rb
& 0xff);
4774 record_full_arch_list_add_mem (ea
, nb
);
4777 case 710: /* Store Word Atomic */
4778 case 742: /* Store Doubleword Atomic */
4780 if (PPC_RA (insn
) != 0)
4781 regcache_raw_read_unsigned (regcache
,
4782 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4786 case 710: /* Store Word Atomic */
4789 case 742: /* Store Doubleword Atomic */
4795 record_full_arch_list_add_mem (ea
, size
);
4798 case 725: /* Store String Word Immediate */
4800 if (PPC_RA (insn
) != 0)
4801 regcache_raw_read_unsigned (regcache
,
4802 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4809 record_full_arch_list_add_mem (ea
, nb
);
4813 case 661: /* Store String Word Indexed */
4815 if (PPC_RA (insn
) != 0)
4816 regcache_raw_read_unsigned (regcache
,
4817 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4820 regcache_raw_read_unsigned (regcache
, tdep
->ppc_xer_regnum
, &xer
);
4821 nb
= PPC_XER_NB (xer
);
4825 regcache_raw_read_unsigned (regcache
,
4826 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
),
4829 record_full_arch_list_add_mem (ea
, nb
);
4834 case 467: /* Move To Special Purpose Register */
4835 switch (PPC_SPR (insn
))
4838 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4841 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
4844 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
4846 case 256: /* VRSAVE */
4847 record_full_arch_list_add_reg (regcache
, tdep
->ppc_vrsave_regnum
);
4853 case 147: /* Move To Split Little Endian */
4854 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4857 case 512: /* Move to Condition Register from XER */
4858 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4859 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
4862 case 4: /* Trap Word */
4863 case 68: /* Trap Doubleword */
4864 case 430: /* Clear BHRB */
4865 case 598: /* Synchronize */
4866 case 62: /* Wait for Interrupt */
4868 case 22: /* Instruction Cache Block Touch */
4869 case 854: /* Enforce In-order Execution of I/O */
4870 case 246: /* Data Cache Block Touch for Store */
4871 case 54: /* Data Cache Block Store */
4872 case 86: /* Data Cache Block Flush */
4873 case 278: /* Data Cache Block Touch */
4874 case 758: /* Data Cache Block Allocate */
4875 case 982: /* Instruction Cache Block Invalidate */
4876 case 774: /* Copy */
4877 case 838: /* CP_Abort */
4880 case 654: /* Transaction Begin */
4881 case 686: /* Transaction End */
4882 case 750: /* Transaction Suspend or Resume */
4883 case 782: /* Transaction Abort Word Conditional */
4884 case 814: /* Transaction Abort Doubleword Conditional */
4885 case 846: /* Transaction Abort Word Conditional Immediate */
4886 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4887 case 910: /* Transaction Abort */
4888 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ps_regnum
);
4890 case 718: /* Transaction Check */
4891 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4894 case 1014: /* Data Cache Block set to Zero */
4895 if (target_auxv_search (¤t_target
, AT_DCACHEBSIZE
, &at_dcsz
) <= 0
4897 at_dcsz
= 128; /* Assume 128-byte cache line size (POWER8) */
4900 if (PPC_RA (insn
) != 0)
4901 regcache_raw_read_unsigned (regcache
,
4902 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
), &ra
);
4903 regcache_raw_read_unsigned (regcache
,
4904 tdep
->ppc_gp0_regnum
+ PPC_RB (insn
), &rb
);
4905 ea
= (ra
+ rb
) & ~((ULONGEST
) (at_dcsz
- 1));
4906 record_full_arch_list_add_mem (ea
, at_dcsz
);
4911 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
4912 "at %s, 31-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
4916 /* Parse and record instructions of primary opcode-59 at ADDR.
4917 Return 0 if successful. */
4920 ppc_process_record_op59 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4921 CORE_ADDR addr
, uint32_t insn
)
4923 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4924 int ext
= PPC_EXTOP (insn
);
4928 case 18: /* Floating Divide */
4929 case 20: /* Floating Subtract */
4930 case 21: /* Floating Add */
4931 case 22: /* Floating Square Root */
4932 case 24: /* Floating Reciprocal Estimate */
4933 case 25: /* Floating Multiply */
4934 case 26: /* Floating Reciprocal Square Root Estimate */
4935 case 28: /* Floating Multiply-Subtract */
4936 case 29: /* Floating Multiply-Add */
4937 case 30: /* Floating Negative Multiply-Subtract */
4938 case 31: /* Floating Negative Multiply-Add */
4939 record_full_arch_list_add_reg (regcache
,
4940 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4942 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4943 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4950 case 2: /* DFP Add */
4951 case 3: /* DFP Quantize */
4952 case 34: /* DFP Multiply */
4953 case 35: /* DFP Reround */
4954 case 67: /* DFP Quantize Immediate */
4955 case 99: /* DFP Round To FP Integer With Inexact */
4956 case 227: /* DFP Round To FP Integer Without Inexact */
4957 case 258: /* DFP Convert To DFP Long! */
4958 case 290: /* DFP Convert To Fixed */
4959 case 514: /* DFP Subtract */
4960 case 546: /* DFP Divide */
4961 case 770: /* DFP Round To DFP Short! */
4962 case 802: /* DFP Convert From Fixed */
4963 case 834: /* DFP Encode BCD To DPD */
4965 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4966 record_full_arch_list_add_reg (regcache
,
4967 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4968 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4971 case 130: /* DFP Compare Ordered */
4972 case 162: /* DFP Test Exponent */
4973 case 194: /* DFP Test Data Class */
4974 case 226: /* DFP Test Data Group */
4975 case 642: /* DFP Compare Unordered */
4976 case 674: /* DFP Test Significance */
4977 case 675: /* DFP Test Significance Immediate */
4978 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4979 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
4982 case 66: /* DFP Shift Significand Left Immediate */
4983 case 98: /* DFP Shift Significand Right Immediate */
4984 case 322: /* DFP Decode DPD To BCD */
4985 case 354: /* DFP Extract Biased Exponent */
4986 case 866: /* DFP Insert Biased Exponent */
4987 record_full_arch_list_add_reg (regcache
,
4988 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4990 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
4993 case 846: /* Floating Convert From Integer Doubleword Single */
4994 case 974: /* Floating Convert From Integer Doubleword Unsigned
4996 record_full_arch_list_add_reg (regcache
,
4997 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
4999 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5000 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5005 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5006 "at %s, 59-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5010 /* Parse and record instructions of primary opcode-60 at ADDR.
5011 Return 0 if successful. */
5014 ppc_process_record_op60 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5015 CORE_ADDR addr
, uint32_t insn
)
5017 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5018 int ext
= PPC_EXTOP (insn
);
5022 case 0: /* VSX Scalar Add Single-Precision */
5023 case 32: /* VSX Scalar Add Double-Precision */
5024 case 24: /* VSX Scalar Divide Single-Precision */
5025 case 56: /* VSX Scalar Divide Double-Precision */
5026 case 176: /* VSX Scalar Copy Sign Double-Precision */
5027 case 33: /* VSX Scalar Multiply-Add Double-Precision */
5028 case 41: /* ditto */
5029 case 1: /* VSX Scalar Multiply-Add Single-Precision */
5031 case 160: /* VSX Scalar Maximum Double-Precision */
5032 case 168: /* VSX Scalar Minimum Double-Precision */
5033 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
5034 case 57: /* ditto */
5035 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
5036 case 25: /* ditto */
5037 case 48: /* VSX Scalar Multiply Double-Precision */
5038 case 16: /* VSX Scalar Multiply Single-Precision */
5039 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
5040 case 169: /* ditto */
5041 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
5042 case 137: /* ditto */
5043 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
5044 case 185: /* ditto */
5045 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
5046 case 153: /* ditto */
5047 case 40: /* VSX Scalar Subtract Double-Precision */
5048 case 8: /* VSX Scalar Subtract Single-Precision */
5049 case 96: /* VSX Vector Add Double-Precision */
5050 case 64: /* VSX Vector Add Single-Precision */
5051 case 120: /* VSX Vector Divide Double-Precision */
5052 case 88: /* VSX Vector Divide Single-Precision */
5053 case 97: /* VSX Vector Multiply-Add Double-Precision */
5054 case 105: /* ditto */
5055 case 65: /* VSX Vector Multiply-Add Single-Precision */
5056 case 73: /* ditto */
5057 case 224: /* VSX Vector Maximum Double-Precision */
5058 case 192: /* VSX Vector Maximum Single-Precision */
5059 case 232: /* VSX Vector Minimum Double-Precision */
5060 case 200: /* VSX Vector Minimum Single-Precision */
5061 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5062 case 121: /* ditto */
5063 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5064 case 89: /* ditto */
5065 case 112: /* VSX Vector Multiply Double-Precision */
5066 case 80: /* VSX Vector Multiply Single-Precision */
5067 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5068 case 233: /* ditto */
5069 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5070 case 201: /* ditto */
5071 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5072 case 249: /* ditto */
5073 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5074 case 217: /* ditto */
5075 case 104: /* VSX Vector Subtract Double-Precision */
5076 case 72: /* VSX Vector Subtract Single-Precision */
5077 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5078 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5079 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5080 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5081 case 3: /* VSX Scalar Compare Equal Double-Precision */
5082 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5083 case 19: /* VSX Scalar Compare Greater Than or Equal
5085 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5087 case 240: /* VSX Vector Copy Sign Double-Precision */
5088 case 208: /* VSX Vector Copy Sign Single-Precision */
5089 case 130: /* VSX Logical AND */
5090 case 138: /* VSX Logical AND with Complement */
5091 case 186: /* VSX Logical Equivalence */
5092 case 178: /* VSX Logical NAND */
5093 case 170: /* VSX Logical OR with Complement */
5094 case 162: /* VSX Logical NOR */
5095 case 146: /* VSX Logical OR */
5096 case 154: /* VSX Logical XOR */
5097 case 18: /* VSX Merge High Word */
5098 case 50: /* VSX Merge Low Word */
5099 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5100 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5101 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5102 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5103 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5104 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5105 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5106 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5107 case 216: /* VSX Vector Insert Exponent Single-Precision */
5108 case 248: /* VSX Vector Insert Exponent Double-Precision */
5109 case 26: /* VSX Vector Permute */
5110 case 58: /* VSX Vector Permute Right-indexed */
5111 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5112 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5113 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5114 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5115 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5118 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5119 case 125: /* VSX Vector Test for software Divide Double-Precision */
5120 case 93: /* VSX Vector Test for software Divide Single-Precision */
5121 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5124 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5125 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5126 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5127 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5128 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5132 switch ((ext
>> 2) & 0x7f) /* Mask out Rc-bit. */
5134 case 99: /* VSX Vector Compare Equal To Double-Precision */
5135 case 67: /* VSX Vector Compare Equal To Single-Precision */
5136 case 115: /* VSX Vector Compare Greater Than or
5137 Equal To Double-Precision */
5138 case 83: /* VSX Vector Compare Greater Than or
5139 Equal To Single-Precision */
5140 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5141 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5143 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5144 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5145 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5151 case 265: /* VSX Scalar round Double-Precision to
5152 Single-Precision and Convert to
5153 Single-Precision format */
5154 case 344: /* VSX Scalar truncate Double-Precision to
5155 Integer and Convert to Signed Integer
5156 Doubleword format with Saturate */
5157 case 88: /* VSX Scalar truncate Double-Precision to
5158 Integer and Convert to Signed Integer Word
5159 Format with Saturate */
5160 case 328: /* VSX Scalar truncate Double-Precision integer
5161 and Convert to Unsigned Integer Doubleword
5162 Format with Saturate */
5163 case 72: /* VSX Scalar truncate Double-Precision to
5164 Integer and Convert to Unsigned Integer Word
5165 Format with Saturate */
5166 case 329: /* VSX Scalar Convert Single-Precision to
5167 Double-Precision format */
5168 case 376: /* VSX Scalar Convert Signed Integer
5169 Doubleword to floating-point format and
5170 Round to Double-Precision format */
5171 case 312: /* VSX Scalar Convert Signed Integer
5172 Doubleword to floating-point format and
5173 round to Single-Precision */
5174 case 360: /* VSX Scalar Convert Unsigned Integer
5175 Doubleword to floating-point format and
5176 Round to Double-Precision format */
5177 case 296: /* VSX Scalar Convert Unsigned Integer
5178 Doubleword to floating-point format and
5179 Round to Single-Precision */
5180 case 73: /* VSX Scalar Round to Double-Precision Integer
5181 Using Round to Nearest Away */
5182 case 107: /* VSX Scalar Round to Double-Precision Integer
5183 Exact using Current rounding mode */
5184 case 121: /* VSX Scalar Round to Double-Precision Integer
5185 Using Round toward -Infinity */
5186 case 105: /* VSX Scalar Round to Double-Precision Integer
5187 Using Round toward +Infinity */
5188 case 89: /* VSX Scalar Round to Double-Precision Integer
5189 Using Round toward Zero */
5190 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5191 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5192 case 281: /* VSX Scalar Round to Single-Precision */
5193 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5195 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5197 case 75: /* VSX Scalar Square Root Double-Precision */
5198 case 11: /* VSX Scalar Square Root Single-Precision */
5199 case 393: /* VSX Vector round Double-Precision to
5200 Single-Precision and Convert to
5201 Single-Precision format */
5202 case 472: /* VSX Vector truncate Double-Precision to
5203 Integer and Convert to Signed Integer
5204 Doubleword format with Saturate */
5205 case 216: /* VSX Vector truncate Double-Precision to
5206 Integer and Convert to Signed Integer Word
5207 Format with Saturate */
5208 case 456: /* VSX Vector truncate Double-Precision to
5209 Integer and Convert to Unsigned Integer
5210 Doubleword format with Saturate */
5211 case 200: /* VSX Vector truncate Double-Precision to
5212 Integer and Convert to Unsigned Integer Word
5213 Format with Saturate */
5214 case 457: /* VSX Vector Convert Single-Precision to
5215 Double-Precision format */
5216 case 408: /* VSX Vector truncate Single-Precision to
5217 Integer and Convert to Signed Integer
5218 Doubleword format with Saturate */
5219 case 152: /* VSX Vector truncate Single-Precision to
5220 Integer and Convert to Signed Integer Word
5221 Format with Saturate */
5222 case 392: /* VSX Vector truncate Single-Precision to
5223 Integer and Convert to Unsigned Integer
5224 Doubleword format with Saturate */
5225 case 136: /* VSX Vector truncate Single-Precision to
5226 Integer and Convert to Unsigned Integer Word
5227 Format with Saturate */
5228 case 504: /* VSX Vector Convert and round Signed Integer
5229 Doubleword to Double-Precision format */
5230 case 440: /* VSX Vector Convert and round Signed Integer
5231 Doubleword to Single-Precision format */
5232 case 248: /* VSX Vector Convert Signed Integer Word to
5233 Double-Precision format */
5234 case 184: /* VSX Vector Convert and round Signed Integer
5235 Word to Single-Precision format */
5236 case 488: /* VSX Vector Convert and round Unsigned
5237 Integer Doubleword to Double-Precision format */
5238 case 424: /* VSX Vector Convert and round Unsigned
5239 Integer Doubleword to Single-Precision format */
5240 case 232: /* VSX Vector Convert and round Unsigned
5241 Integer Word to Double-Precision format */
5242 case 168: /* VSX Vector Convert and round Unsigned
5243 Integer Word to Single-Precision format */
5244 case 201: /* VSX Vector Round to Double-Precision
5245 Integer using round to Nearest Away */
5246 case 235: /* VSX Vector Round to Double-Precision
5247 Integer Exact using Current rounding mode */
5248 case 249: /* VSX Vector Round to Double-Precision
5249 Integer using round toward -Infinity */
5250 case 233: /* VSX Vector Round to Double-Precision
5251 Integer using round toward +Infinity */
5252 case 217: /* VSX Vector Round to Double-Precision
5253 Integer using round toward Zero */
5254 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5255 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5256 case 137: /* VSX Vector Round to Single-Precision Integer
5257 Using Round to Nearest Away */
5258 case 171: /* VSX Vector Round to Single-Precision Integer
5259 Exact Using Current rounding mode */
5260 case 185: /* VSX Vector Round to Single-Precision Integer
5261 Using Round toward -Infinity */
5262 case 169: /* VSX Vector Round to Single-Precision Integer
5263 Using Round toward +Infinity */
5264 case 153: /* VSX Vector Round to Single-Precision Integer
5265 Using round toward Zero */
5266 case 202: /* VSX Vector Reciprocal Square Root Estimate
5268 case 138: /* VSX Vector Reciprocal Square Root Estimate
5270 case 203: /* VSX Vector Square Root Double-Precision */
5271 case 139: /* VSX Vector Square Root Single-Precision */
5272 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5274 case 345: /* VSX Scalar Absolute Value Double-Precision */
5275 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5276 Vector Single-Precision format Non-signalling */
5277 case 331: /* VSX Scalar Convert Single-Precision to
5278 Double-Precision format Non-signalling */
5279 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5280 case 377: /* VSX Scalar Negate Double-Precision */
5281 case 473: /* VSX Vector Absolute Value Double-Precision */
5282 case 409: /* VSX Vector Absolute Value Single-Precision */
5283 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5284 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5285 case 505: /* VSX Vector Negate Double-Precision */
5286 case 441: /* VSX Vector Negate Single-Precision */
5287 case 164: /* VSX Splat Word */
5288 case 165: /* VSX Vector Extract Unsigned Word */
5289 case 181: /* VSX Vector Insert Word */
5290 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5293 case 298: /* VSX Scalar Test Data Class Single-Precision */
5294 case 362: /* VSX Scalar Test Data Class Double-Precision */
5295 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5297 case 106: /* VSX Scalar Test for software Square Root
5299 case 234: /* VSX Vector Test for software Square Root
5301 case 170: /* VSX Vector Test for software Square Root
5303 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5307 switch (PPC_FIELD (insn
, 11, 5))
5309 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5310 case 1: /* VSX Scalar Extract Significand Double-Precision */
5311 record_full_arch_list_add_reg (regcache
,
5312 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5314 case 16: /* VSX Scalar Convert Half-Precision format to
5315 Double-Precision format */
5316 case 17: /* VSX Scalar round & Convert Double-Precision format
5317 to Half-Precision format */
5318 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5319 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5325 switch (PPC_FIELD (insn
, 11, 5))
5327 case 24: /* VSX Vector Convert Half-Precision format to
5328 Single-Precision format */
5329 case 25: /* VSX Vector round and Convert Single-Precision format
5330 to Half-Precision format */
5331 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5333 case 0: /* VSX Vector Extract Exponent Double-Precision */
5334 case 1: /* VSX Vector Extract Significand Double-Precision */
5335 case 7: /* VSX Vector Byte-Reverse Halfword */
5336 case 8: /* VSX Vector Extract Exponent Single-Precision */
5337 case 9: /* VSX Vector Extract Significand Single-Precision */
5338 case 15: /* VSX Vector Byte-Reverse Word */
5339 case 23: /* VSX Vector Byte-Reverse Doubleword */
5340 case 31: /* VSX Vector Byte-Reverse Quadword */
5341 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5349 case 360: /* VSX Vector Splat Immediate Byte */
5350 if (PPC_FIELD (insn
, 11, 2) == 0)
5352 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5356 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5357 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5361 if (((ext
>> 3) & 0x3) == 3) /* VSX Select */
5363 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5367 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5368 "at %s, 60-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5372 /* Parse and record instructions of primary opcode-61 at ADDR.
5373 Return 0 if successful. */
5376 ppc_process_record_op61 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5377 CORE_ADDR addr
, uint32_t insn
)
5379 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5385 case 0: /* Store Floating-Point Double Pair */
5386 case 2: /* Store VSX Scalar Doubleword */
5387 case 3: /* Store VSX Scalar Single */
5388 if (PPC_RA (insn
) != 0)
5389 regcache_raw_read_unsigned (regcache
,
5390 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5392 ea
+= PPC_DS (insn
) << 2;
5395 case 0: /* Store Floating-Point Double Pair */
5398 case 2: /* Store VSX Scalar Doubleword */
5401 case 3: /* Store VSX Scalar Single */
5407 record_full_arch_list_add_mem (ea
, size
);
5413 case 1: /* Load VSX Vector */
5414 ppc_record_vsr (regcache
, tdep
, PPC_XT (insn
));
5416 case 5: /* Store VSX Vector */
5417 if (PPC_RA (insn
) != 0)
5418 regcache_raw_read_unsigned (regcache
,
5419 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5421 ea
+= PPC_DQ (insn
) << 4;
5422 record_full_arch_list_add_mem (ea
, 16);
5426 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5427 "at %s.\n", insn
, paddress (gdbarch
, addr
));
5431 /* Parse and record instructions of primary opcode-63 at ADDR.
5432 Return 0 if successful. */
5435 ppc_process_record_op63 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5436 CORE_ADDR addr
, uint32_t insn
)
5438 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5439 int ext
= PPC_EXTOP (insn
);
5444 case 18: /* Floating Divide */
5445 case 20: /* Floating Subtract */
5446 case 21: /* Floating Add */
5447 case 22: /* Floating Square Root */
5448 case 24: /* Floating Reciprocal Estimate */
5449 case 25: /* Floating Multiply */
5450 case 26: /* Floating Reciprocal Square Root Estimate */
5451 case 28: /* Floating Multiply-Subtract */
5452 case 29: /* Floating Multiply-Add */
5453 case 30: /* Floating Negative Multiply-Subtract */
5454 case 31: /* Floating Negative Multiply-Add */
5455 record_full_arch_list_add_reg (regcache
,
5456 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5458 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5459 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5462 case 23: /* Floating Select */
5463 record_full_arch_list_add_reg (regcache
,
5464 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5466 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5472 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5473 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5475 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5476 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5482 case 2: /* DFP Add Quad */
5483 case 3: /* DFP Quantize Quad */
5484 case 34: /* DFP Multiply Quad */
5485 case 35: /* DFP Reround Quad */
5486 case 67: /* DFP Quantize Immediate Quad */
5487 case 99: /* DFP Round To FP Integer With Inexact Quad */
5488 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5489 case 258: /* DFP Convert To DFP Extended Quad */
5490 case 514: /* DFP Subtract Quad */
5491 case 546: /* DFP Divide Quad */
5492 case 770: /* DFP Round To DFP Long Quad */
5493 case 802: /* DFP Convert From Fixed Quad */
5494 case 834: /* DFP Encode BCD To DPD Quad */
5496 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5497 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5498 record_full_arch_list_add_reg (regcache
, tmp
);
5499 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5500 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5503 case 130: /* DFP Compare Ordered Quad */
5504 case 162: /* DFP Test Exponent Quad */
5505 case 194: /* DFP Test Data Class Quad */
5506 case 226: /* DFP Test Data Group Quad */
5507 case 642: /* DFP Compare Unordered Quad */
5508 case 674: /* DFP Test Significance Quad */
5509 case 675: /* DFP Test Significance Immediate Quad */
5510 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5511 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5514 case 66: /* DFP Shift Significand Left Immediate Quad */
5515 case 98: /* DFP Shift Significand Right Immediate Quad */
5516 case 322: /* DFP Decode DPD To BCD Quad */
5517 case 866: /* DFP Insert Biased Exponent Quad */
5518 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_FRT (insn
) & ~1);
5519 record_full_arch_list_add_reg (regcache
, tmp
);
5520 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5522 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5525 case 290: /* DFP Convert To Fixed Quad */
5526 record_full_arch_list_add_reg (regcache
,
5527 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5529 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5530 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5533 case 354: /* DFP Extract Biased Exponent Quad */
5534 record_full_arch_list_add_reg (regcache
,
5535 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5537 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5540 case 12: /* Floating Round to Single-Precision */
5541 case 14: /* Floating Convert To Integer Word */
5542 case 15: /* Floating Convert To Integer Word
5543 with round toward Zero */
5544 case 142: /* Floating Convert To Integer Word Unsigned */
5545 case 143: /* Floating Convert To Integer Word Unsigned
5546 with round toward Zero */
5547 case 392: /* Floating Round to Integer Nearest */
5548 case 424: /* Floating Round to Integer Toward Zero */
5549 case 456: /* Floating Round to Integer Plus */
5550 case 488: /* Floating Round to Integer Minus */
5551 case 814: /* Floating Convert To Integer Doubleword */
5552 case 815: /* Floating Convert To Integer Doubleword
5553 with round toward Zero */
5554 case 846: /* Floating Convert From Integer Doubleword */
5555 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5556 case 943: /* Floating Convert To Integer Doubleword Unsigned
5557 with round toward Zero */
5558 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5559 record_full_arch_list_add_reg (regcache
,
5560 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5562 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5563 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5567 switch (PPC_FIELD (insn
, 11, 5))
5569 case 1: /* Move From FPSCR & Clear Enables */
5570 case 20: /* Move From FPSCR Control & set DRN */
5571 case 21: /* Move From FPSCR Control & set DRN Immediate */
5572 case 22: /* Move From FPSCR Control & set RN */
5573 case 23: /* Move From FPSCR Control & set RN Immediate */
5574 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5575 case 0: /* Move From FPSCR */
5576 case 24: /* Move From FPSCR Lightweight */
5577 if (PPC_FIELD (insn
, 11, 5) == 0 && PPC_RC (insn
))
5578 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5579 record_full_arch_list_add_reg (regcache
,
5580 tdep
->ppc_fp0_regnum
5586 case 8: /* Floating Copy Sign */
5587 case 40: /* Floating Negate */
5588 case 72: /* Floating Move Register */
5589 case 136: /* Floating Negative Absolute Value */
5590 case 264: /* Floating Absolute Value */
5591 record_full_arch_list_add_reg (regcache
,
5592 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5594 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5597 case 838: /* Floating Merge Odd Word */
5598 case 966: /* Floating Merge Even Word */
5599 record_full_arch_list_add_reg (regcache
,
5600 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5603 case 38: /* Move To FPSCR Bit 1 */
5604 case 70: /* Move To FPSCR Bit 0 */
5605 case 134: /* Move To FPSCR Field Immediate */
5606 case 711: /* Move To FPSCR Fields */
5608 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5609 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5612 case 0: /* Floating Compare Unordered */
5613 case 32: /* Floating Compare Ordered */
5614 case 64: /* Move to Condition Register from FPSCR */
5615 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5616 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5617 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5618 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5619 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5621 case 128: /* Floating Test for software Divide */
5622 case 160: /* Floating Test for software Square Root */
5623 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5626 case 4: /* VSX Scalar Add Quad-Precision */
5627 case 36: /* VSX Scalar Multiply Quad-Precision */
5628 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5629 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5630 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5631 case 484: /* VSX Scalar Negative Multiply-Subtract
5633 case 516: /* VSX Scalar Subtract Quad-Precision */
5634 case 548: /* VSX Scalar Divide Quad-Precision */
5635 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5637 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5638 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5639 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5643 switch (PPC_FIELD (insn
, 11, 5))
5645 case 27: /* VSX Scalar Square Root Quad-Precision */
5646 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5648 case 0: /* VSX Scalar Absolute Quad-Precision */
5649 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5650 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5651 case 16: /* VSX Scalar Negate Quad-Precision */
5652 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5653 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5659 switch (PPC_FIELD (insn
, 11, 5))
5661 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5662 to Unsigned Word format */
5663 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5664 Quad-Precision format */
5665 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5666 to Signed Word format */
5667 case 10: /* VSX Scalar Convert Signed Doubleword format to
5668 Quad-Precision format */
5669 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5670 to Unsigned Doubleword format */
5671 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5672 Double-Precision format */
5673 case 22: /* VSX Scalar Convert Double-Precision format to
5674 Quad-Precision format */
5675 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5676 to Signed Doubleword format */
5677 record_full_arch_list_add_reg (regcache
, tdep
->ppc_fpscr_regnum
);
5678 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5683 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5684 "at %s, 63-%d.\n", insn
, paddress (gdbarch
, addr
), ext
);
5688 /* Parse the current instruction and record the values of the registers and
5689 memory that will be changed in current instruction to "record_arch_list".
5690 Return -1 if something wrong. */
5693 ppc_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5696 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5697 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5701 insn
= read_memory_unsigned_integer (addr
, 4, byte_order
);
5702 op6
= PPC_OP6 (insn
);
5706 case 2: /* Trap Doubleword Immediate */
5707 case 3: /* Trap Word Immediate */
5712 if (ppc_process_record_op4 (gdbarch
, regcache
, addr
, insn
) != 0)
5716 case 17: /* System call */
5717 if (PPC_LEV (insn
) != 0)
5720 if (tdep
->ppc_syscall_record
!= NULL
)
5722 if (tdep
->ppc_syscall_record (regcache
) != 0)
5727 printf_unfiltered (_("no syscall record support\n"));
5732 case 7: /* Multiply Low Immediate */
5733 record_full_arch_list_add_reg (regcache
,
5734 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5737 case 8: /* Subtract From Immediate Carrying */
5738 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5739 record_full_arch_list_add_reg (regcache
,
5740 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5743 case 10: /* Compare Logical Immediate */
5744 case 11: /* Compare Immediate */
5745 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5748 case 13: /* Add Immediate Carrying and Record */
5749 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5751 case 12: /* Add Immediate Carrying */
5752 record_full_arch_list_add_reg (regcache
, tdep
->ppc_xer_regnum
);
5754 case 14: /* Add Immediate */
5755 case 15: /* Add Immediate Shifted */
5756 record_full_arch_list_add_reg (regcache
,
5757 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5760 case 16: /* Branch Conditional */
5761 if ((PPC_BO (insn
) & 0x4) == 0)
5762 record_full_arch_list_add_reg (regcache
, tdep
->ppc_ctr_regnum
);
5764 case 18: /* Branch */
5766 record_full_arch_list_add_reg (regcache
, tdep
->ppc_lr_regnum
);
5770 if (ppc_process_record_op19 (gdbarch
, regcache
, addr
, insn
) != 0)
5774 case 20: /* Rotate Left Word Immediate then Mask Insert */
5775 case 21: /* Rotate Left Word Immediate then AND with Mask */
5776 case 23: /* Rotate Left Word then AND with Mask */
5777 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5778 /* Rotate Left Doubleword Immediate then Clear Right */
5779 /* Rotate Left Doubleword Immediate then Clear */
5780 /* Rotate Left Doubleword then Clear Left */
5781 /* Rotate Left Doubleword then Clear Right */
5782 /* Rotate Left Doubleword Immediate then Mask Insert */
5784 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5785 record_full_arch_list_add_reg (regcache
,
5786 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5789 case 28: /* AND Immediate */
5790 case 29: /* AND Immediate Shifted */
5791 record_full_arch_list_add_reg (regcache
, tdep
->ppc_cr_regnum
);
5793 case 24: /* OR Immediate */
5794 case 25: /* OR Immediate Shifted */
5795 case 26: /* XOR Immediate */
5796 case 27: /* XOR Immediate Shifted */
5797 record_full_arch_list_add_reg (regcache
,
5798 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5802 if (ppc_process_record_op31 (gdbarch
, regcache
, addr
, insn
) != 0)
5806 case 33: /* Load Word and Zero with Update */
5807 case 35: /* Load Byte and Zero with Update */
5808 case 41: /* Load Halfword and Zero with Update */
5809 case 43: /* Load Halfword Algebraic with Update */
5810 record_full_arch_list_add_reg (regcache
,
5811 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5813 case 32: /* Load Word and Zero */
5814 case 34: /* Load Byte and Zero */
5815 case 40: /* Load Halfword and Zero */
5816 case 42: /* Load Halfword Algebraic */
5817 record_full_arch_list_add_reg (regcache
,
5818 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5821 case 46: /* Load Multiple Word */
5822 for (i
= PPC_RT (insn
); i
< 32; i
++)
5823 record_full_arch_list_add_reg (regcache
, tdep
->ppc_gp0_regnum
+ i
);
5826 case 56: /* Load Quadword */
5827 tmp
= tdep
->ppc_gp0_regnum
+ (PPC_RT (insn
) & ~1);
5828 record_full_arch_list_add_reg (regcache
, tmp
);
5829 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5832 case 49: /* Load Floating-Point Single with Update */
5833 case 51: /* Load Floating-Point Double with Update */
5834 record_full_arch_list_add_reg (regcache
,
5835 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5837 case 48: /* Load Floating-Point Single */
5838 case 50: /* Load Floating-Point Double */
5839 record_full_arch_list_add_reg (regcache
,
5840 tdep
->ppc_fp0_regnum
+ PPC_FRT (insn
));
5843 case 47: /* Store Multiple Word */
5847 if (PPC_RA (insn
) != 0)
5848 regcache_raw_read_unsigned (regcache
,
5849 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5852 addr
+= PPC_D (insn
);
5853 record_full_arch_list_add_mem (addr
, 4 * (32 - PPC_RS (insn
)));
5857 case 37: /* Store Word with Update */
5858 case 39: /* Store Byte with Update */
5859 case 45: /* Store Halfword with Update */
5860 case 53: /* Store Floating-Point Single with Update */
5861 case 55: /* Store Floating-Point Double with Update */
5862 record_full_arch_list_add_reg (regcache
,
5863 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5865 case 36: /* Store Word */
5866 case 38: /* Store Byte */
5867 case 44: /* Store Halfword */
5868 case 52: /* Store Floating-Point Single */
5869 case 54: /* Store Floating-Point Double */
5874 if (PPC_RA (insn
) != 0)
5875 regcache_raw_read_unsigned (regcache
,
5876 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5878 addr
+= PPC_D (insn
);
5880 if (op6
== 36 || op6
== 37 || op6
== 52 || op6
== 53)
5882 else if (op6
== 54 || op6
== 55)
5884 else if (op6
== 44 || op6
== 45)
5886 else if (op6
== 38 || op6
== 39)
5891 record_full_arch_list_add_mem (addr
, size
);
5898 case 0: /* Load Floating-Point Double Pair */
5899 tmp
= tdep
->ppc_fp0_regnum
+ (PPC_RT (insn
) & ~1);
5900 record_full_arch_list_add_reg (regcache
, tmp
);
5901 record_full_arch_list_add_reg (regcache
, tmp
+ 1);
5903 case 2: /* Load VSX Scalar Doubleword */
5904 case 3: /* Load VSX Scalar Single */
5905 ppc_record_vsr (regcache
, tdep
, PPC_VRT (insn
) + 32);
5912 case 58: /* Load Doubleword */
5913 /* Load Doubleword with Update */
5914 /* Load Word Algebraic */
5915 if (PPC_FIELD (insn
, 30, 2) > 2)
5918 record_full_arch_list_add_reg (regcache
,
5919 tdep
->ppc_gp0_regnum
+ PPC_RT (insn
));
5920 if (PPC_BIT (insn
, 31))
5921 record_full_arch_list_add_reg (regcache
,
5922 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
));
5926 if (ppc_process_record_op59 (gdbarch
, regcache
, addr
, insn
) != 0)
5931 if (ppc_process_record_op60 (gdbarch
, regcache
, addr
, insn
) != 0)
5936 if (ppc_process_record_op61 (gdbarch
, regcache
, addr
, insn
) != 0)
5940 case 62: /* Store Doubleword */
5941 /* Store Doubleword with Update */
5942 /* Store Quadword with Update */
5946 int sub2
= PPC_FIELD (insn
, 30, 2);
5951 if (PPC_RA (insn
) != 0)
5952 regcache_raw_read_unsigned (regcache
,
5953 tdep
->ppc_gp0_regnum
+ PPC_RA (insn
),
5956 size
= (sub2
== 2) ? 16 : 8;
5958 addr
+= PPC_DS (insn
) << 2;
5959 record_full_arch_list_add_mem (addr
, size
);
5961 if (op6
== 62 && sub2
== 1)
5962 record_full_arch_list_add_reg (regcache
,
5963 tdep
->ppc_gp0_regnum
+
5970 if (ppc_process_record_op63 (gdbarch
, regcache
, addr
, insn
) != 0)
5976 fprintf_unfiltered (gdb_stdlog
, "Warning: Don't know how to record %08x "
5977 "at %s, %d.\n", insn
, paddress (gdbarch
, addr
), op6
);
5981 if (record_full_arch_list_add_reg (regcache
, PPC_PC_REGNUM
))
5983 if (record_full_arch_list_add_end ())
5988 /* Initialize the current architecture based on INFO. If possible, re-use an
5989 architecture from ARCHES, which is a list of architectures already created
5990 during this debugging session.
5992 Called e.g. at program startup, when reading a core file, and when reading
5995 static struct gdbarch
*
5996 rs6000_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5998 struct gdbarch
*gdbarch
;
5999 struct gdbarch_tdep
*tdep
;
6000 int wordsize
, from_xcoff_exec
, from_elf_exec
;
6001 enum bfd_architecture arch
;
6004 enum auto_boolean soft_float_flag
= powerpc_soft_float_global
;
6006 enum powerpc_long_double_abi long_double_abi
= POWERPC_LONG_DOUBLE_AUTO
;
6007 enum powerpc_vector_abi vector_abi
= powerpc_vector_abi_global
;
6008 enum powerpc_elf_abi elf_abi
= POWERPC_ELF_AUTO
;
6009 int have_fpu
= 1, have_spe
= 0, have_mq
= 0, have_altivec
= 0, have_dfp
= 0,
6011 int tdesc_wordsize
= -1;
6012 const struct target_desc
*tdesc
= info
.target_desc
;
6013 struct tdesc_arch_data
*tdesc_data
= NULL
;
6014 int num_pseudoregs
= 0;
6017 /* INFO may refer to a binary that is not of the PowerPC architecture,
6018 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
6019 In this case, we must not attempt to infer properties of the (PowerPC
6020 side) of the target system from properties of that executable. Trust
6021 the target description instead. */
6023 && bfd_get_arch (info
.abfd
) != bfd_arch_powerpc
6024 && bfd_get_arch (info
.abfd
) != bfd_arch_rs6000
)
6027 from_xcoff_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6028 bfd_get_flavour (info
.abfd
) == bfd_target_xcoff_flavour
;
6030 from_elf_exec
= info
.abfd
&& info
.abfd
->format
== bfd_object
&&
6031 bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
;
6033 /* Check word size. If INFO is from a binary file, infer it from
6034 that, else choose a likely default. */
6035 if (from_xcoff_exec
)
6037 if (bfd_xcoff_is_xcoff64 (info
.abfd
))
6042 else if (from_elf_exec
)
6044 if (elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
6049 else if (tdesc_has_registers (tdesc
))
6053 if (info
.bfd_arch_info
!= NULL
&& info
.bfd_arch_info
->bits_per_word
!= 0)
6054 wordsize
= (info
.bfd_arch_info
->bits_per_word
6055 / info
.bfd_arch_info
->bits_per_byte
);
6060 /* Get the architecture and machine from the BFD. */
6061 arch
= info
.bfd_arch_info
->arch
;
6062 mach
= info
.bfd_arch_info
->mach
;
6064 /* For e500 executables, the apuinfo section is of help here. Such
6065 section contains the identifier and revision number of each
6066 Application-specific Processing Unit that is present on the
6067 chip. The content of the section is determined by the assembler
6068 which looks at each instruction and determines which unit (and
6069 which version of it) can execute it. Grovel through the section
6070 looking for relevant e500 APUs. */
6072 if (bfd_uses_spe_extensions (info
.abfd
))
6074 arch
= info
.bfd_arch_info
->arch
;
6075 mach
= bfd_mach_ppc_e500
;
6076 bfd_default_set_arch_mach (&abfd
, arch
, mach
);
6077 info
.bfd_arch_info
= bfd_get_arch_info (&abfd
);
6080 /* Find a default target description which describes our register
6081 layout, if we do not already have one. */
6082 if (! tdesc_has_registers (tdesc
))
6084 const struct variant
*v
;
6086 /* Choose variant. */
6087 v
= find_variant_by_arch (arch
, mach
);
6094 gdb_assert (tdesc_has_registers (tdesc
));
6096 /* Check any target description for validity. */
6097 if (tdesc_has_registers (tdesc
))
6099 static const char *const gprs
[] = {
6100 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6101 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6102 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6103 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6105 const struct tdesc_feature
*feature
;
6107 static const char *const msr_names
[] = { "msr", "ps" };
6108 static const char *const cr_names
[] = { "cr", "cnd" };
6109 static const char *const ctr_names
[] = { "ctr", "cnt" };
6111 feature
= tdesc_find_feature (tdesc
,
6112 "org.gnu.gdb.power.core");
6113 if (feature
== NULL
)
6116 tdesc_data
= tdesc_data_alloc ();
6119 for (i
= 0; i
< ppc_num_gprs
; i
++)
6120 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
, gprs
[i
]);
6121 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_PC_REGNUM
,
6123 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_LR_REGNUM
,
6125 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, PPC_XER_REGNUM
,
6128 /* Allow alternate names for these registers, to accomodate GDB's
6130 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6131 PPC_MSR_REGNUM
, msr_names
);
6132 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6133 PPC_CR_REGNUM
, cr_names
);
6134 valid_p
&= tdesc_numbered_register_choices (feature
, tdesc_data
,
6135 PPC_CTR_REGNUM
, ctr_names
);
6139 tdesc_data_cleanup (tdesc_data
);
6143 have_mq
= tdesc_numbered_register (feature
, tdesc_data
, PPC_MQ_REGNUM
,
6146 tdesc_wordsize
= tdesc_register_size (feature
, "pc") / 8;
6148 wordsize
= tdesc_wordsize
;
6150 feature
= tdesc_find_feature (tdesc
,
6151 "org.gnu.gdb.power.fpu");
6152 if (feature
!= NULL
)
6154 static const char *const fprs
[] = {
6155 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6156 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6157 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6158 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6161 for (i
= 0; i
< ppc_num_fprs
; i
++)
6162 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6163 PPC_F0_REGNUM
+ i
, fprs
[i
]);
6164 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6165 PPC_FPSCR_REGNUM
, "fpscr");
6169 tdesc_data_cleanup (tdesc_data
);
6177 /* The DFP pseudo-registers will be available when there are floating
6179 have_dfp
= have_fpu
;
6181 feature
= tdesc_find_feature (tdesc
,
6182 "org.gnu.gdb.power.altivec");
6183 if (feature
!= NULL
)
6185 static const char *const vector_regs
[] = {
6186 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6187 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6188 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6189 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6193 for (i
= 0; i
< ppc_num_gprs
; i
++)
6194 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6197 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6198 PPC_VSCR_REGNUM
, "vscr");
6199 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6200 PPC_VRSAVE_REGNUM
, "vrsave");
6202 if (have_spe
|| !valid_p
)
6204 tdesc_data_cleanup (tdesc_data
);
6212 /* Check for POWER7 VSX registers support. */
6213 feature
= tdesc_find_feature (tdesc
,
6214 "org.gnu.gdb.power.vsx");
6216 if (feature
!= NULL
)
6218 static const char *const vsx_regs
[] = {
6219 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6220 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6221 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6222 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6223 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6229 for (i
= 0; i
< ppc_num_vshrs
; i
++)
6230 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6231 PPC_VSR0_UPPER_REGNUM
+ i
,
6235 tdesc_data_cleanup (tdesc_data
);
6244 /* On machines supporting the SPE APU, the general-purpose registers
6245 are 64 bits long. There are SIMD vector instructions to treat them
6246 as pairs of floats, but the rest of the instruction set treats them
6247 as 32-bit registers, and only operates on their lower halves.
6249 In the GDB regcache, we treat their high and low halves as separate
6250 registers. The low halves we present as the general-purpose
6251 registers, and then we have pseudo-registers that stitch together
6252 the upper and lower halves and present them as pseudo-registers.
6254 Thus, the target description is expected to supply the upper
6255 halves separately. */
6257 feature
= tdesc_find_feature (tdesc
,
6258 "org.gnu.gdb.power.spe");
6259 if (feature
!= NULL
)
6261 static const char *const upper_spe
[] = {
6262 "ev0h", "ev1h", "ev2h", "ev3h",
6263 "ev4h", "ev5h", "ev6h", "ev7h",
6264 "ev8h", "ev9h", "ev10h", "ev11h",
6265 "ev12h", "ev13h", "ev14h", "ev15h",
6266 "ev16h", "ev17h", "ev18h", "ev19h",
6267 "ev20h", "ev21h", "ev22h", "ev23h",
6268 "ev24h", "ev25h", "ev26h", "ev27h",
6269 "ev28h", "ev29h", "ev30h", "ev31h"
6273 for (i
= 0; i
< ppc_num_gprs
; i
++)
6274 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6275 PPC_SPE_UPPER_GP0_REGNUM
+ i
,
6277 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6278 PPC_SPE_ACC_REGNUM
, "acc");
6279 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
6280 PPC_SPE_FSCR_REGNUM
, "spefscr");
6282 if (have_mq
|| have_fpu
|| !valid_p
)
6284 tdesc_data_cleanup (tdesc_data
);
6293 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6294 complain for a 32-bit binary on a 64-bit target; we do not yet
6295 support that. For instance, the 32-bit ABI routines expect
6298 As long as there isn't an explicit target description, we'll
6299 choose one based on the BFD architecture and get a word size
6300 matching the binary (probably powerpc:common or
6301 powerpc:common64). So there is only trouble if a 64-bit target
6302 supplies a 64-bit description while debugging a 32-bit
6304 if (tdesc_wordsize
!= -1 && tdesc_wordsize
!= wordsize
)
6306 tdesc_data_cleanup (tdesc_data
);
6313 switch (elf_elfheader (info
.abfd
)->e_flags
& EF_PPC64_ABI
)
6316 elf_abi
= POWERPC_ELF_V1
;
6319 elf_abi
= POWERPC_ELF_V2
;
6326 if (soft_float_flag
== AUTO_BOOLEAN_AUTO
&& from_elf_exec
)
6328 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6329 Tag_GNU_Power_ABI_FP
) & 3)
6332 soft_float_flag
= AUTO_BOOLEAN_FALSE
;
6335 soft_float_flag
= AUTO_BOOLEAN_TRUE
;
6342 if (long_double_abi
== POWERPC_LONG_DOUBLE_AUTO
&& from_elf_exec
)
6344 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6345 Tag_GNU_Power_ABI_FP
) >> 2)
6348 long_double_abi
= POWERPC_LONG_DOUBLE_IBM128
;
6351 long_double_abi
= POWERPC_LONG_DOUBLE_IEEE128
;
6358 if (vector_abi
== POWERPC_VEC_AUTO
&& from_elf_exec
)
6360 switch (bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
6361 Tag_GNU_Power_ABI_Vector
))
6364 vector_abi
= POWERPC_VEC_GENERIC
;
6367 vector_abi
= POWERPC_VEC_ALTIVEC
;
6370 vector_abi
= POWERPC_VEC_SPE
;
6378 /* At this point, the only supported ELF-based 64-bit little-endian
6379 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6380 default. All other supported ELF-based operating systems use the
6381 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6382 e.g. because we run a legacy binary, or have attached to a process
6383 and have not found any associated binary file, set the default
6384 according to this heuristic. */
6385 if (elf_abi
== POWERPC_ELF_AUTO
)
6387 if (wordsize
== 8 && info
.byte_order
== BFD_ENDIAN_LITTLE
)
6388 elf_abi
= POWERPC_ELF_V2
;
6390 elf_abi
= POWERPC_ELF_V1
;
6393 if (soft_float_flag
== AUTO_BOOLEAN_TRUE
)
6395 else if (soft_float_flag
== AUTO_BOOLEAN_FALSE
)
6398 soft_float
= !have_fpu
;
6400 /* If we have a hard float binary or setting but no floating point
6401 registers, downgrade to soft float anyway. We're still somewhat
6402 useful in this scenario. */
6403 if (!soft_float
&& !have_fpu
)
6406 /* Similarly for vector registers. */
6407 if (vector_abi
== POWERPC_VEC_ALTIVEC
&& !have_altivec
)
6408 vector_abi
= POWERPC_VEC_GENERIC
;
6410 if (vector_abi
== POWERPC_VEC_SPE
&& !have_spe
)
6411 vector_abi
= POWERPC_VEC_GENERIC
;
6413 if (vector_abi
== POWERPC_VEC_AUTO
)
6416 vector_abi
= POWERPC_VEC_ALTIVEC
;
6418 vector_abi
= POWERPC_VEC_SPE
;
6420 vector_abi
= POWERPC_VEC_GENERIC
;
6423 /* Do not limit the vector ABI based on available hardware, since we
6424 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6426 /* Find a candidate among extant architectures. */
6427 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
6429 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
6431 /* Word size in the various PowerPC bfd_arch_info structs isn't
6432 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6433 separate word size check. */
6434 tdep
= gdbarch_tdep (arches
->gdbarch
);
6435 if (tdep
&& tdep
->elf_abi
!= elf_abi
)
6437 if (tdep
&& tdep
->soft_float
!= soft_float
)
6439 if (tdep
&& tdep
->long_double_abi
!= long_double_abi
)
6441 if (tdep
&& tdep
->vector_abi
!= vector_abi
)
6443 if (tdep
&& tdep
->wordsize
== wordsize
)
6445 if (tdesc_data
!= NULL
)
6446 tdesc_data_cleanup (tdesc_data
);
6447 return arches
->gdbarch
;
6451 /* None found, create a new architecture from INFO, whose bfd_arch_info
6452 validity depends on the source:
6453 - executable useless
6454 - rs6000_host_arch() good
6456 - "set arch" trust blindly
6457 - GDB startup useless but harmless */
6459 tdep
= XCNEW (struct gdbarch_tdep
);
6460 tdep
->wordsize
= wordsize
;
6461 tdep
->elf_abi
= elf_abi
;
6462 tdep
->soft_float
= soft_float
;
6463 tdep
->long_double_abi
= long_double_abi
;
6464 tdep
->vector_abi
= vector_abi
;
6466 gdbarch
= gdbarch_alloc (&info
, tdep
);
6468 tdep
->ppc_gp0_regnum
= PPC_R0_REGNUM
;
6469 tdep
->ppc_toc_regnum
= PPC_R0_REGNUM
+ 2;
6470 tdep
->ppc_ps_regnum
= PPC_MSR_REGNUM
;
6471 tdep
->ppc_cr_regnum
= PPC_CR_REGNUM
;
6472 tdep
->ppc_lr_regnum
= PPC_LR_REGNUM
;
6473 tdep
->ppc_ctr_regnum
= PPC_CTR_REGNUM
;
6474 tdep
->ppc_xer_regnum
= PPC_XER_REGNUM
;
6475 tdep
->ppc_mq_regnum
= have_mq
? PPC_MQ_REGNUM
: -1;
6477 tdep
->ppc_fp0_regnum
= have_fpu
? PPC_F0_REGNUM
: -1;
6478 tdep
->ppc_fpscr_regnum
= have_fpu
? PPC_FPSCR_REGNUM
: -1;
6479 tdep
->ppc_vsr0_upper_regnum
= have_vsx
? PPC_VSR0_UPPER_REGNUM
: -1;
6480 tdep
->ppc_vr0_regnum
= have_altivec
? PPC_VR0_REGNUM
: -1;
6481 tdep
->ppc_vrsave_regnum
= have_altivec
? PPC_VRSAVE_REGNUM
: -1;
6482 tdep
->ppc_ev0_upper_regnum
= have_spe
? PPC_SPE_UPPER_GP0_REGNUM
: -1;
6483 tdep
->ppc_acc_regnum
= have_spe
? PPC_SPE_ACC_REGNUM
: -1;
6484 tdep
->ppc_spefscr_regnum
= have_spe
? PPC_SPE_FSCR_REGNUM
: -1;
6486 set_gdbarch_pc_regnum (gdbarch
, PPC_PC_REGNUM
);
6487 set_gdbarch_sp_regnum (gdbarch
, PPC_R0_REGNUM
+ 1);
6488 set_gdbarch_fp0_regnum (gdbarch
, tdep
->ppc_fp0_regnum
);
6489 set_gdbarch_register_sim_regno (gdbarch
, rs6000_register_sim_regno
);
6491 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6492 GDB traditionally called it "ps", though, so let GDB add an
6494 set_gdbarch_ps_regnum (gdbarch
, tdep
->ppc_ps_regnum
);
6497 set_gdbarch_return_value (gdbarch
, ppc64_sysv_abi_return_value
);
6499 set_gdbarch_return_value (gdbarch
, ppc_sysv_abi_return_value
);
6501 /* Set lr_frame_offset. */
6503 tdep
->lr_frame_offset
= 16;
6505 tdep
->lr_frame_offset
= 4;
6507 if (have_spe
|| have_dfp
|| have_vsx
)
6509 set_gdbarch_pseudo_register_read (gdbarch
, rs6000_pseudo_register_read
);
6510 set_gdbarch_pseudo_register_write (gdbarch
,
6511 rs6000_pseudo_register_write
);
6512 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
6513 rs6000_ax_pseudo_register_collect
);
6516 set_gdbarch_gen_return_address (gdbarch
, rs6000_gen_return_address
);
6518 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
6520 set_gdbarch_num_regs (gdbarch
, PPC_NUM_REGS
);
6523 num_pseudoregs
+= 32;
6525 num_pseudoregs
+= 16;
6527 /* Include both VSX and Extended FP registers. */
6528 num_pseudoregs
+= 96;
6530 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudoregs
);
6532 set_gdbarch_ptr_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6533 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
6534 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6535 set_gdbarch_long_bit (gdbarch
, wordsize
* TARGET_CHAR_BIT
);
6536 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6537 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
6538 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
6539 set_gdbarch_long_double_bit (gdbarch
, 16 * TARGET_CHAR_BIT
);
6540 set_gdbarch_char_signed (gdbarch
, 0);
6542 set_gdbarch_frame_align (gdbarch
, rs6000_frame_align
);
6545 set_gdbarch_frame_red_zone_size (gdbarch
, 288);
6547 set_gdbarch_convert_register_p (gdbarch
, rs6000_convert_register_p
);
6548 set_gdbarch_register_to_value (gdbarch
, rs6000_register_to_value
);
6549 set_gdbarch_value_to_register (gdbarch
, rs6000_value_to_register
);
6551 set_gdbarch_stab_reg_to_regnum (gdbarch
, rs6000_stab_reg_to_regnum
);
6552 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, rs6000_dwarf2_reg_to_regnum
);
6555 set_gdbarch_push_dummy_call (gdbarch
, ppc_sysv_abi_push_dummy_call
);
6556 else if (wordsize
== 8)
6557 set_gdbarch_push_dummy_call (gdbarch
, ppc64_sysv_abi_push_dummy_call
);
6559 set_gdbarch_skip_prologue (gdbarch
, rs6000_skip_prologue
);
6560 set_gdbarch_stack_frame_destroyed_p (gdbarch
, rs6000_stack_frame_destroyed_p
);
6561 set_gdbarch_skip_main_prologue (gdbarch
, rs6000_skip_main_prologue
);
6563 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
6565 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
6566 rs6000_breakpoint::kind_from_pc
);
6567 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
6568 rs6000_breakpoint::bp_from_kind
);
6570 /* The value of symbols of type N_SO and N_FUN maybe null when
6572 set_gdbarch_sofun_address_maybe_missing (gdbarch
, 1);
6574 /* Handles single stepping of atomic sequences. */
6575 set_gdbarch_software_single_step (gdbarch
, ppc_deal_with_atomic_sequence
);
6577 /* Not sure on this. FIXMEmgo */
6578 set_gdbarch_frame_args_skip (gdbarch
, 8);
6580 /* Helpers for function argument information. */
6581 set_gdbarch_fetch_pointer_argument (gdbarch
, rs6000_fetch_pointer_argument
);
6584 set_gdbarch_in_solib_return_trampoline
6585 (gdbarch
, rs6000_in_solib_return_trampoline
);
6586 set_gdbarch_skip_trampoline_code (gdbarch
, rs6000_skip_trampoline_code
);
6588 /* Hook in the DWARF CFI frame unwinder. */
6589 dwarf2_append_unwinders (gdbarch
);
6590 dwarf2_frame_set_adjust_regnum (gdbarch
, rs6000_adjust_frame_regnum
);
6592 /* Frame handling. */
6593 dwarf2_frame_set_init_reg (gdbarch
, ppc_dwarf2_frame_init_reg
);
6595 /* Setup displaced stepping. */
6596 set_gdbarch_displaced_step_copy_insn (gdbarch
,
6597 ppc_displaced_step_copy_insn
);
6598 set_gdbarch_displaced_step_hw_singlestep (gdbarch
,
6599 ppc_displaced_step_hw_singlestep
);
6600 set_gdbarch_displaced_step_fixup (gdbarch
, ppc_displaced_step_fixup
);
6601 set_gdbarch_displaced_step_location (gdbarch
,
6602 displaced_step_at_entry_point
);
6604 set_gdbarch_max_insn_length (gdbarch
, PPC_INSN_SIZE
);
6606 /* Hook in ABI-specific overrides, if they have been registered. */
6607 info
.target_desc
= tdesc
;
6608 info
.tdesc_data
= tdesc_data
;
6609 gdbarch_init_osabi (info
, gdbarch
);
6613 case GDB_OSABI_LINUX
:
6614 case GDB_OSABI_NETBSD
:
6615 case GDB_OSABI_UNKNOWN
:
6616 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6617 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6618 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6619 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6620 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6623 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
6625 set_gdbarch_unwind_pc (gdbarch
, rs6000_unwind_pc
);
6626 frame_unwind_append_unwinder (gdbarch
, &rs6000_epilogue_frame_unwind
);
6627 frame_unwind_append_unwinder (gdbarch
, &rs6000_frame_unwind
);
6628 set_gdbarch_dummy_id (gdbarch
, rs6000_dummy_id
);
6629 frame_base_append_sniffer (gdbarch
, rs6000_frame_base_sniffer
);
6632 set_tdesc_pseudo_register_type (gdbarch
, rs6000_pseudo_register_type
);
6633 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
6634 rs6000_pseudo_register_reggroup_p
);
6635 tdesc_use_registers (gdbarch
, tdesc
, tdesc_data
);
6637 /* Override the normal target description method to make the SPE upper
6638 halves anonymous. */
6639 set_gdbarch_register_name (gdbarch
, rs6000_register_name
);
6641 /* Choose register numbers for all supported pseudo-registers. */
6642 tdep
->ppc_ev0_regnum
= -1;
6643 tdep
->ppc_dl0_regnum
= -1;
6644 tdep
->ppc_vsr0_regnum
= -1;
6645 tdep
->ppc_efpr0_regnum
= -1;
6647 cur_reg
= gdbarch_num_regs (gdbarch
);
6651 tdep
->ppc_ev0_regnum
= cur_reg
;
6656 tdep
->ppc_dl0_regnum
= cur_reg
;
6661 tdep
->ppc_vsr0_regnum
= cur_reg
;
6663 tdep
->ppc_efpr0_regnum
= cur_reg
;
6667 gdb_assert (gdbarch_num_regs (gdbarch
)
6668 + gdbarch_num_pseudo_regs (gdbarch
) == cur_reg
);
6670 /* Register the ravenscar_arch_ops. */
6671 if (mach
== bfd_mach_ppc_e500
)
6672 register_e500_ravenscar_ops (gdbarch
);
6674 register_ppc_ravenscar_ops (gdbarch
);
6676 set_gdbarch_disassembler_options (gdbarch
, &powerpc_disassembler_options
);
6677 set_gdbarch_valid_disassembler_options (gdbarch
,
6678 disassembler_options_powerpc ());
6684 rs6000_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
6686 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
6691 /* FIXME: Dump gdbarch_tdep. */
6694 /* PowerPC-specific commands. */
6697 set_powerpc_command (const char *args
, int from_tty
)
6699 printf_unfiltered (_("\
6700 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6701 help_list (setpowerpccmdlist
, "set powerpc ", all_commands
, gdb_stdout
);
6705 show_powerpc_command (const char *args
, int from_tty
)
6707 cmd_show_list (showpowerpccmdlist
, from_tty
, "");
6711 powerpc_set_soft_float (const char *args
, int from_tty
,
6712 struct cmd_list_element
*c
)
6714 struct gdbarch_info info
;
6716 /* Update the architecture. */
6717 gdbarch_info_init (&info
);
6718 if (!gdbarch_update_p (info
))
6719 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6723 powerpc_set_vector_abi (const char *args
, int from_tty
,
6724 struct cmd_list_element
*c
)
6726 struct gdbarch_info info
;
6729 for (vector_abi
= POWERPC_VEC_AUTO
;
6730 vector_abi
!= POWERPC_VEC_LAST
;
6732 if (strcmp (powerpc_vector_abi_string
,
6733 powerpc_vector_strings
[vector_abi
]) == 0)
6735 powerpc_vector_abi_global
= (enum powerpc_vector_abi
) vector_abi
;
6739 if (vector_abi
== POWERPC_VEC_LAST
)
6740 internal_error (__FILE__
, __LINE__
, _("Invalid vector ABI accepted: %s."),
6741 powerpc_vector_abi_string
);
6743 /* Update the architecture. */
6744 gdbarch_info_init (&info
);
6745 if (!gdbarch_update_p (info
))
6746 internal_error (__FILE__
, __LINE__
, _("could not update architecture"));
6749 /* Show the current setting of the exact watchpoints flag. */
6752 show_powerpc_exact_watchpoints (struct ui_file
*file
, int from_tty
,
6753 struct cmd_list_element
*c
,
6756 fprintf_filtered (file
, _("Use of exact watchpoints is %s.\n"), value
);
6759 /* Read a PPC instruction from memory. */
6762 read_insn (struct frame_info
*frame
, CORE_ADDR pc
)
6764 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6765 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
6767 return read_memory_unsigned_integer (pc
, 4, byte_order
);
6770 /* Return non-zero if the instructions at PC match the series
6771 described in PATTERN, or zero otherwise. PATTERN is an array of
6772 'struct ppc_insn_pattern' objects, terminated by an entry whose
6775 When the match is successful, fill INSNS[i] with what PATTERN[i]
6776 matched. If PATTERN[i] is optional, and the instruction wasn't
6777 present, set INSNS[i] to 0 (which is not a valid PPC instruction).
6778 INSNS should have as many elements as PATTERN, minus the terminator.
6779 Note that, if PATTERN contains optional instructions which aren't
6780 present in memory, then INSNS will have holes, so INSNS[i] isn't
6781 necessarily the i'th instruction in memory. */
6784 ppc_insns_match_pattern (struct frame_info
*frame
, CORE_ADDR pc
,
6785 const struct ppc_insn_pattern
*pattern
,
6786 unsigned int *insns
)
6791 for (i
= 0, insn
= 0; pattern
[i
].mask
; i
++)
6794 insn
= read_insn (frame
, pc
);
6796 if ((insn
& pattern
[i
].mask
) == pattern
[i
].data
)
6802 else if (!pattern
[i
].optional
)
6809 /* Return the 'd' field of the d-form instruction INSN, properly
6813 ppc_insn_d_field (unsigned int insn
)
6815 return ((((CORE_ADDR
) insn
& 0xffff) ^ 0x8000) - 0x8000);
6818 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6819 zero bits concatenated at the right, and properly
6823 ppc_insn_ds_field (unsigned int insn
)
6825 return ((((CORE_ADDR
) insn
& 0xfffc) ^ 0x8000) - 0x8000);
6828 /* Initialization code. */
6831 _initialize_rs6000_tdep (void)
6833 gdbarch_register (bfd_arch_rs6000
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6834 gdbarch_register (bfd_arch_powerpc
, rs6000_gdbarch_init
, rs6000_dump_tdep
);
6836 /* Initialize the standard target descriptions. */
6837 initialize_tdesc_powerpc_32 ();
6838 initialize_tdesc_powerpc_altivec32 ();
6839 initialize_tdesc_powerpc_vsx32 ();
6840 initialize_tdesc_powerpc_403 ();
6841 initialize_tdesc_powerpc_403gc ();
6842 initialize_tdesc_powerpc_405 ();
6843 initialize_tdesc_powerpc_505 ();
6844 initialize_tdesc_powerpc_601 ();
6845 initialize_tdesc_powerpc_602 ();
6846 initialize_tdesc_powerpc_603 ();
6847 initialize_tdesc_powerpc_604 ();
6848 initialize_tdesc_powerpc_64 ();
6849 initialize_tdesc_powerpc_altivec64 ();
6850 initialize_tdesc_powerpc_vsx64 ();
6851 initialize_tdesc_powerpc_7400 ();
6852 initialize_tdesc_powerpc_750 ();
6853 initialize_tdesc_powerpc_860 ();
6854 initialize_tdesc_powerpc_e500 ();
6855 initialize_tdesc_rs6000 ();
6857 /* Add root prefix command for all "set powerpc"/"show powerpc"
6859 add_prefix_cmd ("powerpc", no_class
, set_powerpc_command
,
6860 _("Various PowerPC-specific commands."),
6861 &setpowerpccmdlist
, "set powerpc ", 0, &setlist
);
6863 add_prefix_cmd ("powerpc", no_class
, show_powerpc_command
,
6864 _("Various PowerPC-specific commands."),
6865 &showpowerpccmdlist
, "show powerpc ", 0, &showlist
);
6867 /* Add a command to allow the user to force the ABI. */
6868 add_setshow_auto_boolean_cmd ("soft-float", class_support
,
6869 &powerpc_soft_float_global
,
6870 _("Set whether to use a soft-float ABI."),
6871 _("Show whether to use a soft-float ABI."),
6873 powerpc_set_soft_float
, NULL
,
6874 &setpowerpccmdlist
, &showpowerpccmdlist
);
6876 add_setshow_enum_cmd ("vector-abi", class_support
, powerpc_vector_strings
,
6877 &powerpc_vector_abi_string
,
6878 _("Set the vector ABI."),
6879 _("Show the vector ABI."),
6880 NULL
, powerpc_set_vector_abi
, NULL
,
6881 &setpowerpccmdlist
, &showpowerpccmdlist
);
6883 add_setshow_boolean_cmd ("exact-watchpoints", class_support
,
6884 &target_exact_watchpoints
,
6886 Set whether to use just one debug register for watchpoints on scalars."),
6888 Show whether to use just one debug register for watchpoints on scalars."),
6890 If true, GDB will use only one debug register when watching a variable of\n\
6891 scalar type, thus assuming that the variable is accessed through the address\n\
6892 of its first byte."),
6893 NULL
, show_powerpc_exact_watchpoints
,
6894 &setpowerpccmdlist
, &showpowerpccmdlist
);