gdb/sh-tdep.c

   1 /* Target-dependent code for Hitachi Super-H, for GDB.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000 Free Software
   3    Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 /*
  23    Contributed by Steve Chamberlain
  24    sac@cygnus.com
  25  */
  26
  27 #include "defs.h"
  28 #include "frame.h"
  29 #include "obstack.h"
  30 #include "symtab.h"
  31 #include "symfile.h"
  32 #include "gdbtypes.h"
  33 #include "gdbcmd.h"
  34 #include "gdbcore.h"
  35 #include "value.h"
  36 #include "dis-asm.h"
  37 #include "inferior.h"           /* for BEFORE_TEXT_END etc. */
  38 #include "gdb_string.h"
  39 #include "arch-utils.h"
  40
  41 /* A set of original names, to be used when restoring back to generic
  42    registers from a specific set.  */
  43 /* *INDENT-OFF* */
  44 static char *sh_generic_reg_names[] = {
  45   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  46   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  47   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  48   "fpul", "fpscr",
  49   "fr0",  "fr1",  "fr2",  "fr3",  "fr4",  "fr5",  "fr6",  "fr7",
  50   "fr8",  "fr9",  "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  51   "ssr",  "spc",
  52   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  53   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  54 };
  55
  56 static char *sh_reg_names[] = {
  57   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  58   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  59   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  60   "",     "",
  61   "",     "",     "",     "",     "",     "",     "",     "",
  62   "",     "",     "",     "",     "",     "",     "",     "",
  63   "",     "",
  64   "",     "",     "",     "",     "",     "",     "",     "",
  65   "",     "",     "",     "",     "",     "",     "",     "",
  66 };
  67
  68 static char *sh3_reg_names[] = {
  69   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  70   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  71   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  72   "",     "",
  73   "",     "",     "",     "",     "",     "",     "",     "",
  74   "",     "",     "",     "",     "",     "",     "",     "",
  75   "ssr",  "spc",
  76   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  77   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
  78 };
  79
  80 static char *sh3e_reg_names[] = {
  81   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  82   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  83   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  84   "fpul", "fpscr",
  85   "fr0",  "fr1",  "fr2",  "fr3",  "fr4",  "fr5",  "fr6",  "fr7",
  86   "fr8",  "fr9",  "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  87   "ssr",  "spc",
  88   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  89   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  90 };
  91
  92 static char *sh_dsp_reg_names[] = {
  93   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  94   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  95   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  96   "",     "dsr",
  97   "a0g",  "a0",   "a1g",  "a1",   "m0",   "m1",   "x0",   "x1",
  98   "y0",   "y1",   "",     "",     "",     "",     "",     "mod",
  99   "",     "",
 100   "rs",   "re",   "",     "",     "",     "",     "",     "",
 101   "",     "",     "",     "",     "",     "",     "",     "",
 102 };
 103
 104 static char *sh3_dsp_reg_names[] = {
 105   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
 106   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
 107   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
 108   "",     "dsr",
 109   "a0g",  "a0",   "a1g",  "a1",   "m0",   "m1",   "x0",   "x1",
 110   "y0",   "y1",   "",     "",     "",     "",     "",     "mod",
 111   "ssr",  "spc",
 112   "rs",   "re",   "",     "",     "",     "",     "",     "",
 113   "r0b",  "r1b",  "r2b",  "r3b",  "r4b",  "r5b",  "r6b",  "r7b",
 114 };
 115 /* *INDENT-ON* */
 116
 117 #ifdef _WIN32_WCE
 118 char **sh_register_names = sh3_reg_names;
 119 #else
 120 char **sh_register_names = sh_generic_reg_names;
 121 #endif
 122
 123 struct
 124   {
 125     char **regnames;
 126     int mach;
 127   }
 128 sh_processor_type_table[] =
 129 {
 130   {
 131     sh_reg_names, bfd_mach_sh
 132   }
 133   ,
 134   {
 135     sh_reg_names, bfd_mach_sh2
 136   }
 137   ,
 138   {
 139     sh_dsp_reg_names, bfd_mach_sh_dsp
 140   }
 141   ,
 142   {
 143     sh3_reg_names, bfd_mach_sh3
 144   }
 145   ,
 146   {
 147     sh3_dsp_reg_names, bfd_mach_sh3_dsp
 148   }
 149   ,
 150   {
 151     sh3e_reg_names, bfd_mach_sh3e
 152   }
 153   ,
 154   {
 155     NULL, 0
 156   }
 157 };
 158
 159 /* Prologue looks like
 160    [mov.l       <regs>,@-r15]...
 161    [sts.l       pr,@-r15]
 162    [mov.l       r14,@-r15]
 163    [mov         r15,r14]
 164  */
 165
 166 #define IS_STS(x)               ((x) == 0x4f22)
 167 #define IS_PUSH(x)              (((x) & 0xff0f) == 0x2f06)
 168 #define GET_PUSHED_REG(x)       (((x) >> 4) & 0xf)
 169 #define IS_MOV_SP_FP(x)         ((x) == 0x6ef3)
 170 #define IS_ADD_SP(x)            (((x) & 0xff00) == 0x7f00)
 171 #define IS_MOV_R3(x)            (((x) & 0xff00) == 0x1a00)
 172 #define IS_SHLL_R3(x)           ((x) == 0x4300)
 173 #define IS_ADD_R3SP(x)          ((x) == 0x3f3c)
 174 #define IS_FMOV(x)              (((x) & 0xf00f) == 0xf00b)
 175 #define FPSCR_SZ                (1 << 20)
 176
 177
 178 /* Should call_function allocate stack space for a struct return?  */
 179 int
 180 sh_use_struct_convention (gcc_p, type)
 181      int gcc_p;
 182      struct type *type;
 183 {
 184   return (TYPE_LENGTH (type) > 1);
 185 }
 186
 187
 188 /* Skip any prologue before the guts of a function */
 189
 190 CORE_ADDR
 191 sh_skip_prologue (start_pc)
 192      CORE_ADDR start_pc;
 193 {
 194   CORE_ADDR here, end;
 195
 196   if (!start_pc)
 197     return 0;
 198
 199   for (here = start_pc, end = start_pc + (2 * 28); here < end;)
 200     {
 201       int w = read_memory_integer (here, 2);
 202       here += 2;
 203       if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
 204           || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w))
 205         start_pc = here;
 206
 207       if (IS_MOV_SP_FP (w))
 208         {
 209           start_pc = here;
 210           break;
 211         }
 212     }
 213
 214   return start_pc;
 215 }
 216
 217 /* Disassemble an instruction.  */
 218
 219 int
 220 gdb_print_insn_sh (memaddr, info)
 221      bfd_vma memaddr;
 222      disassemble_info *info;
 223 {
 224   if (TARGET_BYTE_ORDER == BIG_ENDIAN)
 225     return print_insn_sh (memaddr, info);
 226   else
 227     return print_insn_shl (memaddr, info);
 228 }
 229
 230 /* Given a GDB frame, determine the address of the calling function's frame.
 231    This will be used to create a new GDB frame struct, and then
 232    INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
 233
 234    For us, the frame address is its stack pointer value, so we look up
 235    the function prologue to determine the caller's sp value, and return it.  */
 236
 237 CORE_ADDR
 238 sh_frame_chain (frame)
 239      struct frame_info *frame;
 240 {
 241   if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
 242     return frame->frame;        /* dummy frame same as caller's frame */
 243   if (frame->pc && !inside_entry_file (frame->pc))
 244     return read_memory_integer (FRAME_FP (frame) + frame->f_offset, 4);
 245   else
 246     return 0;
 247 }
 248
 249 /* Find REGNUM on the stack.  Otherwise, it's in an active register.  One thing
 250    we might want to do here is to check REGNUM against the clobber mask, and
 251    somehow flag it as invalid if it isn't saved on the stack somewhere.  This
 252    would provide a graceful failure mode when trying to get the value of
 253    caller-saves registers for an inner frame.  */
 254
 255 CORE_ADDR
 256 sh_find_callers_reg (fi, regnum)
 257      struct frame_info *fi;
 258      int regnum;
 259 {
 260   struct frame_saved_regs fsr;
 261
 262   for (; fi; fi = fi->next)
 263     if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
 264       /* When the caller requests PR from the dummy frame, we return PC because
 265          that's where the previous routine appears to have done a call from. */
 266       return generic_read_register_dummy (fi->pc, fi->frame, regnum);
 267     else
 268       {
 269         FRAME_FIND_SAVED_REGS (fi, fsr);
 270         if (!fi->pc)
 271           return 0;
 272         if (fsr.regs[regnum] != 0)
 273           return read_memory_integer (fsr.regs[regnum],
 274                                       REGISTER_RAW_SIZE (regnum));
 275       }
 276   return read_register (regnum);
 277 }
 278
 279 /* Put here the code to store, into a struct frame_saved_regs, the
 280    addresses of the saved registers of frame described by FRAME_INFO.
 281    This includes special registers such as pc and fp saved in special
 282    ways in the stack frame.  sp is even more special: the address we
 283    return for it IS the sp for the next frame. */
 284
 285 void
 286 sh_frame_find_saved_regs (fi, fsr)
 287      struct frame_info *fi;
 288      struct frame_saved_regs *fsr;
 289 {
 290   int where[NUM_REGS];
 291   int rn;
 292   int have_fp = 0;
 293   int depth;
 294   int pc;
 295   int opc;
 296   int insn;
 297   int r3_val = 0;
 298   char *dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
 299
 300   if (dummy_regs)
 301     {
 302       /* DANGER!  This is ONLY going to work if the char buffer format of
 303          the saved registers is byte-for-byte identical to the
 304          CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
 305       memcpy (&fsr->regs, dummy_regs, sizeof (fsr));
 306       return;
 307     }
 308
 309   fi->leaf_function = 1;
 310   fi->f_offset = 0;
 311
 312   for (rn = 0; rn < NUM_REGS; rn++)
 313     where[rn] = -1;
 314
 315   depth = 0;
 316
 317   /* Loop around examining the prologue insns until we find something
 318      that does not appear to be part of the prologue.  But give up
 319      after 20 of them, since we're getting silly then. */
 320
 321   pc = get_pc_function_start (fi->pc);
 322   if (!pc)
 323     {
 324       fi->pc = 0;
 325       return;
 326     }
 327
 328   for (opc = pc + (2 * 28); pc < opc; pc += 2)
 329     {
 330       insn = read_memory_integer (pc, 2);
 331       /* See where the registers will be saved to */
 332       if (IS_PUSH (insn))
 333         {
 334           rn = GET_PUSHED_REG (insn);
 335           where[rn] = depth;
 336           depth += 4;
 337         }
 338       else if (IS_STS (insn))
 339         {
 340           where[PR_REGNUM] = depth;
 341           /* If we're storing the pr then this isn't a leaf */
 342           fi->leaf_function = 0;
 343           depth += 4;
 344         }
 345       else if (IS_MOV_R3 (insn))
 346         {
 347           r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
 348         }
 349       else if (IS_SHLL_R3 (insn))
 350         {
 351           r3_val <<= 1;
 352         }
 353       else if (IS_ADD_R3SP (insn))
 354         {
 355           depth += -r3_val;
 356         }
 357       else if (IS_ADD_SP (insn))
 358         {
 359           depth -= ((insn & 0xff) ^ 0x80) - 0x80;
 360         }
 361       else if (IS_FMOV (insn))
 362         {
 363           if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
 364             {
 365               depth += 8;
 366             }
 367           else
 368             {
 369               depth += 4;
 370             }
 371         }
 372       else if (IS_MOV_SP_FP (insn))
 373         break;
 374 #if 0 /* This used to just stop when it found an instruction that
 375          was not considered part of the prologue.  Now, we just
 376          keep going looking for likely instructions. */
 377       else
 378         break;
 379 #endif
 380     }
 381
 382   /* Now we know how deep things are, we can work out their addresses */
 383
 384   for (rn = 0; rn < NUM_REGS; rn++)
 385     {
 386       if (where[rn] >= 0)
 387         {
 388           if (rn == FP_REGNUM)
 389             have_fp = 1;
 390
 391           fsr->regs[rn] = fi->frame - where[rn] + depth - 4;
 392         }
 393       else
 394         {
 395           fsr->regs[rn] = 0;
 396         }
 397     }
 398
 399   if (have_fp)
 400     {
 401       fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[FP_REGNUM], 4);
 402     }
 403   else
 404     {
 405       fsr->regs[SP_REGNUM] = fi->frame - 4;
 406     }
 407
 408   fi->f_offset = depth - where[FP_REGNUM] - 4;
 409   /* Work out the return pc - either from the saved pr or the pr
 410      value */
 411 }
 412
 413 /* initialize the extra info saved in a FRAME */
 414
 415 void
 416 sh_init_extra_frame_info (fromleaf, fi)
 417      int fromleaf;
 418      struct frame_info *fi;
 419 {
 420   struct frame_saved_regs fsr;
 421
 422   if (fi->next)
 423     fi->pc = FRAME_SAVED_PC (fi->next);
 424
 425   if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
 426     {
 427       /* We need to setup fi->frame here because run_stack_dummy gets it wrong
 428          by assuming it's always FP.  */
 429       fi->frame = generic_read_register_dummy (fi->pc, fi->frame,
 430                                                SP_REGNUM);
 431       fi->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
 432                                                    PC_REGNUM);
 433       fi->f_offset = -(CALL_DUMMY_LENGTH + 4);
 434       fi->leaf_function = 0;
 435       return;
 436     }
 437   else
 438     {
 439       FRAME_FIND_SAVED_REGS (fi, fsr);
 440       fi->return_pc = sh_find_callers_reg (fi, PR_REGNUM);
 441     }
 442 }
 443
 444 /* Discard from the stack the innermost frame,
 445    restoring all saved registers.  */
 446
 447 void
 448 sh_pop_frame ()
 449 {
 450   register struct frame_info *frame = get_current_frame ();
 451   register CORE_ADDR fp;
 452   register int regnum;
 453   struct frame_saved_regs fsr;
 454
 455   if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
 456     generic_pop_dummy_frame ();
 457   else
 458     {
 459       fp = FRAME_FP (frame);
 460       get_frame_saved_regs (frame, &fsr);
 461
 462       /* Copy regs from where they were saved in the frame */
 463       for (regnum = 0; regnum < NUM_REGS; regnum++)
 464         if (fsr.regs[regnum])
 465           write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
 466
 467       write_register (PC_REGNUM, frame->return_pc);
 468       write_register (SP_REGNUM, fp + 4);
 469     }
 470   flush_cached_frames ();
 471 }
 472
 473 /* Function: push_arguments
 474    Setup the function arguments for calling a function in the inferior.
 475
 476    On the Hitachi SH architecture, there are four registers (R4 to R7)
 477    which are dedicated for passing function arguments.  Up to the first
 478    four arguments (depending on size) may go into these registers.
 479    The rest go on the stack.
 480
 481    Arguments that are smaller than 4 bytes will still take up a whole
 482    register or a whole 32-bit word on the stack, and will be
 483    right-justified in the register or the stack word.  This includes
 484    chars, shorts, and small aggregate types.
 485
 486    Arguments that are larger than 4 bytes may be split between two or
 487    more registers.  If there are not enough registers free, an argument
 488    may be passed partly in a register (or registers), and partly on the
 489    stack.  This includes doubles, long longs, and larger aggregates.
 490    As far as I know, there is no upper limit to the size of aggregates
 491    that will be passed in this way; in other words, the convention of
 492    passing a pointer to a large aggregate instead of a copy is not used.
 493
 494    An exceptional case exists for struct arguments (and possibly other
 495    aggregates such as arrays) if the size is larger than 4 bytes but
 496    not a multiple of 4 bytes.  In this case the argument is never split
 497    between the registers and the stack, but instead is copied in its
 498    entirety onto the stack, AND also copied into as many registers as
 499    there is room for.  In other words, space in registers permitting,
 500    two copies of the same argument are passed in.  As far as I can tell,
 501    only the one on the stack is used, although that may be a function
 502    of the level of compiler optimization.  I suspect this is a compiler
 503    bug.  Arguments of these odd sizes are left-justified within the
 504    word (as opposed to arguments smaller than 4 bytes, which are
 505    right-justified).
 506
 507
 508    If the function is to return an aggregate type such as a struct, it
 509    is either returned in the normal return value register R0 (if its
 510    size is no greater than one byte), or else the caller must allocate
 511    space into which the callee will copy the return value (if the size
 512    is greater than one byte).  In this case, a pointer to the return
 513    value location is passed into the callee in register R2, which does
 514    not displace any of the other arguments passed in via registers R4
 515    to R7.   */
 516
 517 CORE_ADDR
 518 sh_push_arguments (nargs, args, sp, struct_return, struct_addr)
 519      int nargs;
 520      value_ptr *args;
 521      CORE_ADDR sp;
 522      unsigned char struct_return;
 523      CORE_ADDR struct_addr;
 524 {
 525   int stack_offset, stack_alloc;
 526   int argreg;
 527   int argnum;
 528   struct type *type;
 529   CORE_ADDR regval;
 530   char *val;
 531   char valbuf[4];
 532   int len;
 533   int odd_sized_struct;
 534
 535   /* first force sp to a 4-byte alignment */
 536   sp = sp & ~3;
 537
 538   /* The "struct return pointer" pseudo-argument has its own dedicated
 539      register */
 540   if (struct_return)
 541     write_register (STRUCT_RETURN_REGNUM, struct_addr);
 542
 543   /* Now make sure there's space on the stack */
 544   for (argnum = 0, stack_alloc = 0;
 545        argnum < nargs; argnum++)
 546     stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
 547   sp -= stack_alloc;            /* make room on stack for args */
 548
 549
 550   /* Now load as many as possible of the first arguments into
 551      registers, and push the rest onto the stack.  There are 16 bytes
 552      in four registers available.  Loop thru args from first to last.  */
 553
 554   argreg = ARG0_REGNUM;
 555   for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
 556     {
 557       type = VALUE_TYPE (args[argnum]);
 558       len = TYPE_LENGTH (type);
 559       memset (valbuf, 0, sizeof (valbuf));
 560       if (len < 4)
 561         {                       /* value gets right-justified in the register or stack word */
 562           memcpy (valbuf + (4 - len),
 563                   (char *) VALUE_CONTENTS (args[argnum]), len);
 564           val = valbuf;
 565         }
 566       else
 567         val = (char *) VALUE_CONTENTS (args[argnum]);
 568
 569       if (len > 4 && (len & 3) != 0)
 570         odd_sized_struct = 1;   /* such structs go entirely on stack */
 571       else
 572         odd_sized_struct = 0;
 573       while (len > 0)
 574         {
 575           if (argreg > ARGLAST_REGNUM || odd_sized_struct)
 576             {                   /* must go on the stack */
 577               write_memory (sp + stack_offset, val, 4);
 578               stack_offset += 4;
 579             }
 580           /* NOTE WELL!!!!!  This is not an "else if" clause!!!
 581              That's because some *&^%$ things get passed on the stack
 582              AND in the registers!   */
 583           if (argreg <= ARGLAST_REGNUM)
 584             {                   /* there's room in a register */
 585               regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
 586               write_register (argreg++, regval);
 587             }
 588           /* Store the value 4 bytes at a time.  This means that things
 589              larger than 4 bytes may go partly in registers and partly
 590              on the stack.  */
 591           len -= REGISTER_RAW_SIZE (argreg);
 592           val += REGISTER_RAW_SIZE (argreg);
 593         }
 594     }
 595   return sp;
 596 }
 597
 598 /* Function: push_return_address (pc)
 599    Set up the return address for the inferior function call.
 600    Needed for targets where we don't actually execute a JSR/BSR instruction */
 601
 602 CORE_ADDR
 603 sh_push_return_address (pc, sp)
 604      CORE_ADDR pc;
 605      CORE_ADDR sp;
 606 {
 607   write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ());
 608   return sp;
 609 }
 610
 611 /* Function: fix_call_dummy
 612    Poke the callee function's address into the destination part of
 613    the CALL_DUMMY.  The address is actually stored in a data word
 614    following the actualy CALL_DUMMY instructions, which will load
 615    it into a register using PC-relative addressing.  This function
 616    expects the CALL_DUMMY to look like this:
 617
 618    mov.w @(2,PC), R8
 619    jsr   @R8
 620    nop
 621    trap
 622    <destination>
 623  */
 624
 625 #if 0
 626 void
 627 sh_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p)
 628      char *dummy;
 629      CORE_ADDR pc;
 630      CORE_ADDR fun;
 631      int nargs;
 632      value_ptr *args;
 633      struct type *type;
 634      int gcc_p;
 635 {
 636   *(unsigned long *) (dummy + 8) = fun;
 637 }
 638 #endif
 639
 640
 641 /* Modify the actual processor type. */
 642
 643 int
 644 sh_target_architecture_hook (ap)
 645      const bfd_arch_info_type *ap;
 646 {
 647   int i, j;
 648
 649   if (ap->arch != bfd_arch_sh)
 650     return 0;
 651
 652   for (i = 0; sh_processor_type_table[i].regnames != NULL; i++)
 653     {
 654       if (sh_processor_type_table[i].mach == ap->mach)
 655         {
 656           sh_register_names = sh_processor_type_table[i].regnames;
 657           return 1;
 658         }
 659     }
 660
 661   internal_error ("Architecture `%s' unreconized", ap->printable_name);
 662 }
 663
 664 /* Print the registers in a form similar to the E7000 */
 665
 666 static void
 667 sh_show_regs (args, from_tty)
 668      char *args;
 669      int from_tty;
 670 {
 671   int cpu;
 672   if (TARGET_ARCHITECTURE->arch == bfd_arch_sh)
 673     cpu = TARGET_ARCHITECTURE->mach;
 674   else
 675     cpu = 0;
 676
 677   printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
 678                    paddr (read_register (PC_REGNUM)),
 679                    (long) read_register (SR_REGNUM),
 680                    (long) read_register (PR_REGNUM),
 681                    (long) read_register (MACH_REGNUM),
 682                    (long) read_register (MACL_REGNUM));
 683
 684   printf_filtered ("GBR=%08lx VBR=%08lx",
 685                    (long) read_register (GBR_REGNUM),
 686                    (long) read_register (VBR_REGNUM));
 687   if (cpu == bfd_mach_sh3 || cpu == bfd_mach_sh3e || cpu == bfd_mach_sh3_dsp
 688       || cpu == bfd_mach_sh4)
 689     {
 690       printf_filtered (" SSR=%08lx SPC=%08lx",
 691                        (long) read_register (SSR_REGNUM),
 692                        (long) read_register (SPC_REGNUM));
 693       if (cpu == bfd_mach_sh3e || cpu == bfd_mach_sh4)
 694         {
 695           printf_filtered (" FPUL=%08lx FPSCR=%08lx",
 696                            (long) read_register (FPUL_REGNUM),
 697                            (long) read_register (FPSCR_REGNUM));
 698         }
 699     }
 700   if (cpu == bfd_mach_sh_dsp || cpu == bfd_mach_sh3_dsp)
 701     printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
 702
 703   printf_filtered ("\nR0-R7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
 704                    (long) read_register (0),
 705                    (long) read_register (1),
 706                    (long) read_register (2),
 707                    (long) read_register (3),
 708                    (long) read_register (4),
 709                    (long) read_register (5),
 710                    (long) read_register (6),
 711                    (long) read_register (7));
 712   printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
 713                    (long) read_register (8),
 714                    (long) read_register (9),
 715                    (long) read_register (10),
 716                    (long) read_register (11),
 717                    (long) read_register (12),
 718                    (long) read_register (13),
 719                    (long) read_register (14),
 720                    (long) read_register (15));
 721   if (cpu == bfd_mach_sh3e || cpu == bfd_mach_sh4)
 722     {
 723       int pr = cpu == bfd_mach_sh4 && (read_register (FPSCR_REGNUM) & 0x80000);
 724
 725       printf_filtered ((pr
 726                         ? "DR0-DR6  %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
 727                         : "FP0-FP7  %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
 728                        (long) read_register (FP0_REGNUM + 0),
 729                        (long) read_register (FP0_REGNUM + 1),
 730                        (long) read_register (FP0_REGNUM + 2),
 731                        (long) read_register (FP0_REGNUM + 3),
 732                        (long) read_register (FP0_REGNUM + 4),
 733                        (long) read_register (FP0_REGNUM + 5),
 734                        (long) read_register (FP0_REGNUM + 6),
 735                        (long) read_register (FP0_REGNUM + 7));
 736       printf_filtered ((pr
 737                         ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
 738                         : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
 739                        (long) read_register (FP0_REGNUM + 8),
 740                        (long) read_register (FP0_REGNUM + 9),
 741                        (long) read_register (FP0_REGNUM + 10),
 742                        (long) read_register (FP0_REGNUM + 11),
 743                        (long) read_register (FP0_REGNUM + 12),
 744                        (long) read_register (FP0_REGNUM + 13),
 745                        (long) read_register (FP0_REGNUM + 14),
 746                        (long) read_register (FP0_REGNUM + 15));
 747     }
 748   /* FIXME: sh4 has more registers */
 749   if (cpu == bfd_mach_sh_dsp || cpu == bfd_mach_sh3_dsp)
 750     {
 751       printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
 752                        (long) read_register (A0G_REGNUM) & 0xff,
 753                        (long) read_register (A0_REGNUM),
 754                        (long) read_register (M0_REGNUM),
 755                        (long) read_register (X0_REGNUM),
 756                        (long) read_register (Y0_REGNUM),
 757                        (long) read_register (RS_REGNUM),
 758                        (long) read_register (MOD_REGNUM));
 759       printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
 760                        (long) read_register (A1G_REGNUM) & 0xff,
 761                        (long) read_register (A1_REGNUM),
 762                        (long) read_register (M1_REGNUM),
 763                        (long) read_register (X1_REGNUM),
 764                        (long) read_register (Y1_REGNUM),
 765                        (long) read_register (RE_REGNUM));
 766     }
 767 }
 768
 769 /* Function: extract_return_value
 770    Find a function's return value in the appropriate registers (in regbuf),
 771    and copy it into valbuf.  */
 772
 773 void
 774 sh_extract_return_value (type, regbuf, valbuf)
 775      struct type *type;
 776      void *regbuf;
 777      void *valbuf;
 778 {
 779   int len = TYPE_LENGTH (type);
 780
 781   if (len <= 4)
 782     memcpy (valbuf, ((char *) regbuf) + 4 - len, len);
 783   else if (len <= 8)
 784     memcpy (valbuf, ((char *) regbuf) + 8 - len, len);
 785   else
 786     error ("bad size for return value");
 787 }
 788
 789 void
 790 _initialize_sh_tdep ()
 791 {
 792   struct cmd_list_element *c;
 793
 794   tm_print_insn = gdb_print_insn_sh;
 795
 796   target_architecture_hook = sh_target_architecture_hook;
 797
 798   add_com ("regs", class_vars, sh_show_regs, "Print all registers");
 799 }