1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "floatformat.h"
51 #include "solib-svr4.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
58 static void (*sh_show_regs
) (void);
60 #define SH_NUM_REGS 59
69 /* Flag showing that a frame has been created in the prologue code. */
72 /* Saved registers. */
73 CORE_ADDR saved_regs
[SH_NUM_REGS
];
78 sh_generic_register_name (int reg_nr
)
80 static char *register_names
[] = {
81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
83 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
85 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
86 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
88 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
89 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
93 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
95 return register_names
[reg_nr
];
99 sh_sh_register_name (int reg_nr
)
101 static char *register_names
[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
114 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
116 return register_names
[reg_nr
];
120 sh_sh3_register_name (int reg_nr
)
122 static char *register_names
[] = {
123 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
130 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
131 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
135 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
137 return register_names
[reg_nr
];
141 sh_sh3e_register_name (int reg_nr
)
143 static char *register_names
[] = {
144 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
145 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
146 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
148 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
149 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
151 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
152 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
156 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
158 return register_names
[reg_nr
];
162 sh_sh2e_register_name (int reg_nr
)
164 static char *register_names
[] = {
165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
167 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
169 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
170 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
172 "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "",
177 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
179 return register_names
[reg_nr
];
183 sh_sh_dsp_register_name (int reg_nr
)
185 static char *register_names
[] = {
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
193 "rs", "re", "", "", "", "", "", "",
194 "", "", "", "", "", "", "", "",
198 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
200 return register_names
[reg_nr
];
204 sh_sh3_dsp_register_name (int reg_nr
)
206 static char *register_names
[] = {
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
212 "y0", "y1", "", "", "", "", "", "mod",
214 "rs", "re", "", "", "", "", "", "",
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
216 "", "", "", "", "", "", "", "",
220 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
222 return register_names
[reg_nr
];
226 sh_sh4_register_name (int reg_nr
)
228 static char *register_names
[] = {
229 /* general registers 0-15 */
230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
233 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
236 /* floating point registers 25 - 40 */
237 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
238 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
242 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
244 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
245 /* double precision (pseudo) 59 - 66 */
246 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
247 /* vectors (pseudo) 67 - 70 */
248 "fv0", "fv4", "fv8", "fv12",
249 /* FIXME: missing XF 71 - 86 */
250 /* FIXME: missing XD 87 - 94 */
254 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
256 return register_names
[reg_nr
];
259 static const unsigned char *
260 sh_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
262 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
263 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
265 *lenptr
= sizeof (breakpoint
);
269 /* Prologue looks like
273 sub <room_for_loca_vars>,r15
276 Actually it can be more complicated than this but that's it, basically.
279 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
280 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
282 /* STS.L PR,@-r15 0100111100100010
283 r15-4-->r15, PR-->(r15) */
284 #define IS_STS(x) ((x) == 0x4f22)
286 /* MOV.L Rm,@-r15 00101111mmmm0110
287 r15-4-->r15, Rm-->(R15) */
288 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
290 /* MOV r15,r14 0110111011110011
292 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
294 /* ADD #imm,r15 01111111iiiiiiii
296 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
298 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
299 #define IS_SHLL_R3(x) ((x) == 0x4300)
301 /* ADD r3,r15 0011111100111100
303 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
305 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
306 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
307 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
308 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
309 make this entirely clear. */
310 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
311 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
313 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
314 #define IS_MOV_ARG_TO_REG(x) \
315 (((x) & 0xf00f) == 0x6003 && \
316 ((x) & 0x00f0) >= 0x0040 && \
317 ((x) & 0x00f0) <= 0x0070)
318 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
319 #define IS_MOV_ARG_TO_IND_R14(x) \
320 (((x) & 0xff0f) == 0x2e02 && \
321 ((x) & 0x00f0) >= 0x0040 && \
322 ((x) & 0x00f0) <= 0x0070)
323 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
324 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
325 (((x) & 0xff00) == 0x1e00 && \
326 ((x) & 0x00f0) >= 0x0040 && \
327 ((x) & 0x00f0) <= 0x0070)
329 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
330 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
331 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
332 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
333 /* SUB Rn,R15 00111111nnnn1000 */
334 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
336 #define FPSCR_SZ (1 << 20)
338 /* The following instructions are used for epilogue testing. */
339 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
340 #define IS_RTS(x) ((x) == 0x000b)
341 #define IS_LDS(x) ((x) == 0x4f26)
342 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
343 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
344 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
346 /* Disassemble an instruction. */
348 gdb_print_insn_sh (bfd_vma memaddr
, disassemble_info
* info
)
350 info
->endian
= TARGET_BYTE_ORDER
;
351 return print_insn_sh (memaddr
, info
);
355 sh_analyze_prologue (CORE_ADDR pc
, CORE_ADDR current_pc
,
356 struct sh_frame_cache
*cache
)
363 int reg
, sav_reg
= -1;
365 if (pc
>= current_pc
)
369 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
371 inst
= read_memory_unsigned_integer (pc
, 2);
372 /* See where the registers will be saved to */
375 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
376 cache
->sp_offset
+= 4;
378 else if (IS_STS (inst
))
380 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
381 cache
->sp_offset
+= 4;
383 else if (IS_MOV_R3 (inst
))
385 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
387 else if (IS_SHLL_R3 (inst
))
391 else if (IS_ADD_R3SP (inst
))
393 cache
->sp_offset
+= -r3_val
;
395 else if (IS_ADD_IMM_SP (inst
))
397 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
398 cache
->sp_offset
-= offset
;
400 else if (IS_MOVW_PCREL_TO_REG (inst
))
404 reg
= GET_TARGET_REG (inst
);
408 offset
= (((inst
& 0xff) ^ 0x80) - 0x80) << 1;
410 read_memory_integer (((pc
+ 4) & ~3) + offset
, 2);
414 else if (IS_MOVL_PCREL_TO_REG (inst
))
418 reg
= (inst
& 0x0f00) >> 8;
422 offset
= (((inst
& 0xff) ^ 0x80) - 0x80) << 1;
424 read_memory_integer (((pc
+ 4) & ~3) + offset
, 4);
428 else if (IS_SUB_REG_FROM_SP (inst
))
430 reg
= GET_SOURCE_REG (inst
);
431 if (sav_reg
> 0 && reg
== sav_reg
)
435 cache
->sp_offset
+= sav_offset
;
437 else if (IS_FPUSH (inst
))
439 if (read_register (FPSCR_REGNUM
) & FPSCR_SZ
)
441 cache
->sp_offset
+= 8;
445 cache
->sp_offset
+= 4;
448 else if (IS_MOV_SP_FP (inst
))
452 /* At this point, only allow argument register moves to other
453 registers or argument register moves to @(X,fp) which are
454 moving the register arguments onto the stack area allocated
455 by a former add somenumber to SP call. Don't allow moving
456 to an fp indirect address above fp + cache->sp_offset. */
458 for (opc
= pc
+ 12; pc
< opc
; pc
+= 2)
460 inst
= read_memory_integer (pc
, 2);
461 if (IS_MOV_ARG_TO_IND_R14 (inst
))
463 reg
= GET_SOURCE_REG (inst
);
464 if (cache
->sp_offset
> 0)
465 cache
->saved_regs
[reg
] = cache
->sp_offset
;
467 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
469 reg
= GET_SOURCE_REG (inst
);
470 offset
= (inst
& 0xf) * 4;
471 if (cache
->sp_offset
> offset
)
472 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
474 else if (IS_MOV_ARG_TO_REG (inst
))
481 #if 0 /* This used to just stop when it found an instruction that
482 was not considered part of the prologue. Now, we just
483 keep going looking for likely instructions. */
492 /* Skip any prologue before the guts of a function */
494 /* Skip the prologue using the debug information. If this fails we'll
495 fall back on the 'guess' method below. */
497 after_prologue (CORE_ADDR pc
)
499 struct symtab_and_line sal
;
500 CORE_ADDR func_addr
, func_end
;
502 /* If we can not find the symbol in the partial symbol table, then
503 there is no hope we can determine the function's start address
505 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
508 /* Get the line associated with FUNC_ADDR. */
509 sal
= find_pc_line (func_addr
, 0);
511 /* There are only two cases to consider. First, the end of the source line
512 is within the function bounds. In that case we return the end of the
513 source line. Second is the end of the source line extends beyond the
514 bounds of the current function. We need to use the slow code to
515 examine instructions in that case. */
516 if (sal
.end
< func_end
)
523 sh_skip_prologue (CORE_ADDR start_pc
)
526 struct sh_frame_cache cache
;
528 /* See if we can determine the end of the prologue via the symbol table.
529 If so, then return either PC, or the PC after the prologue, whichever
531 pc
= after_prologue (start_pc
);
533 /* If after_prologue returned a useful address, then use it. Else
534 fall back on the instruction skipping code. */
536 return max (pc
, start_pc
);
538 cache
.sp_offset
= -4;
539 pc
= sh_analyze_prologue (start_pc
, (CORE_ADDR
) -1, &cache
);
546 /* Should call_function allocate stack space for a struct return?
550 Aggregate types not bigger than 8 bytes that have the same size and
551 alignment as one of the integer scalar types are returned in the
552 same registers as the integer type they match.
554 For example, a 2-byte aligned structure with size 2 bytes has the
555 same size and alignment as a short int, and will be returned in R0.
556 A 4-byte aligned structure with size 8 bytes has the same size and
557 alignment as a long long int, and will be returned in R0 and R1.
559 When an aggregate type is returned in R0 and R1, R0 contains the
560 first four bytes of the aggregate, and R1 contains the
561 remainder. If the size of the aggregate type is not a multiple of 4
562 bytes, the aggregate is tail-padded up to a multiple of 4
563 bytes. The value of the padding is undefined. For little-endian
564 targets the padding will appear at the most significant end of the
565 last element, for big-endian targets the padding appears at the
566 least significant end of the last element.
568 All other aggregate types are returned by address. The caller
569 function passes the address of an area large enough to hold the
570 aggregate value in R2. The called function stores the result in
573 To reiterate, structs smaller than 8 bytes could also be returned
574 in memory, if they don't pass the "same size and alignment as an
579 struct s { char c[3]; } wibble;
580 struct s foo(void) { return wibble; }
582 the return value from foo() will be in memory, not
583 in R0, because there is no 3-byte integer type.
588 sh_use_struct_convention (int gcc_p
, struct type
*type
)
590 int len
= TYPE_LENGTH (type
);
591 int nelem
= TYPE_NFIELDS (type
);
592 return ((len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8) || nelem
!= 1) &&
593 (len
!= 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) != 4);
596 /* Extract from an array REGBUF containing the (raw) register state
597 the address in which a function should return its structure value,
598 as a CORE_ADDR (or an expression that can be used as one). */
600 sh_extract_struct_value_address (struct regcache
*regcache
)
604 regcache_cooked_read_unsigned (regcache
, STRUCT_RETURN_REGNUM
, &addr
);
609 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
614 /* Function: push_dummy_call (formerly push_arguments)
615 Setup the function arguments for calling a function in the inferior.
617 On the Hitachi SH architecture, there are four registers (R4 to R7)
618 which are dedicated for passing function arguments. Up to the first
619 four arguments (depending on size) may go into these registers.
620 The rest go on the stack.
622 MVS: Except on SH variants that have floating point registers.
623 In that case, float and double arguments are passed in the same
624 manner, but using FP registers instead of GP registers.
626 Arguments that are smaller than 4 bytes will still take up a whole
627 register or a whole 32-bit word on the stack, and will be
628 right-justified in the register or the stack word. This includes
629 chars, shorts, and small aggregate types.
631 Arguments that are larger than 4 bytes may be split between two or
632 more registers. If there are not enough registers free, an argument
633 may be passed partly in a register (or registers), and partly on the
634 stack. This includes doubles, long longs, and larger aggregates.
635 As far as I know, there is no upper limit to the size of aggregates
636 that will be passed in this way; in other words, the convention of
637 passing a pointer to a large aggregate instead of a copy is not used.
639 MVS: The above appears to be true for the SH variants that do not
640 have an FPU, however those that have an FPU appear to copy the
641 aggregate argument onto the stack (and not place it in registers)
642 if it is larger than 16 bytes (four GP registers).
644 An exceptional case exists for struct arguments (and possibly other
645 aggregates such as arrays) if the size is larger than 4 bytes but
646 not a multiple of 4 bytes. In this case the argument is never split
647 between the registers and the stack, but instead is copied in its
648 entirety onto the stack, AND also copied into as many registers as
649 there is room for. In other words, space in registers permitting,
650 two copies of the same argument are passed in. As far as I can tell,
651 only the one on the stack is used, although that may be a function
652 of the level of compiler optimization. I suspect this is a compiler
653 bug. Arguments of these odd sizes are left-justified within the
654 word (as opposed to arguments smaller than 4 bytes, which are
657 If the function is to return an aggregate type such as a struct, it
658 is either returned in the normal return value register R0 (if its
659 size is no greater than one byte), or else the caller must allocate
660 space into which the callee will copy the return value (if the size
661 is greater than one byte). In this case, a pointer to the return
662 value location is passed into the callee in register R2, which does
663 not displace any of the other arguments passed in via registers R4
666 /* Helper function to justify value in register according to endianess. */
668 sh_justify_value_in_reg (struct value
*val
, int len
)
670 static char valbuf
[4];
672 memset (valbuf
, 0, sizeof (valbuf
));
675 /* value gets right-justified in the register or stack word */
676 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
677 memcpy (valbuf
+ (4 - len
), (char *) VALUE_CONTENTS (val
), len
);
679 memcpy (valbuf
, (char *) VALUE_CONTENTS (val
), len
);
682 return (char *) VALUE_CONTENTS (val
);
685 /* Helper function to eval number of bytes to allocate on stack. */
687 sh_stack_allocsize (int nargs
, struct value
**args
)
691 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[nargs
])) + 3) & ~3);
695 /* Helper functions for getting the float arguments right. Registers usage
696 depends on the ABI and the endianess. The comments should enlighten how
697 it's intended to work. */
699 /* This array stores which of the float arg registers are already in use. */
700 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
702 /* This function just resets the above array to "no reg used so far". */
704 sh_init_flt_argreg (void)
706 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
709 /* This function returns the next register to use for float arg passing.
710 It returns either a valid value between FLOAT_ARG0_REGNUM and
711 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
712 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
714 Note that register number 0 in flt_argreg_array corresponds with the
715 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
716 29) the parity of the register number is preserved, which is important
717 for the double register passing test (see the "argreg & 1" test below). */
719 sh_next_flt_argreg (int len
)
723 /* First search for the next free register. */
724 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
726 if (!flt_argreg_array
[argreg
])
729 /* No register left? */
730 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
731 return FLOAT_ARGLAST_REGNUM
+ 1;
735 /* Doubles are always starting in a even register number. */
738 flt_argreg_array
[argreg
] = 1;
742 /* No register left? */
743 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
744 return FLOAT_ARGLAST_REGNUM
+ 1;
746 /* Also mark the next register as used. */
747 flt_argreg_array
[argreg
+ 1] = 1;
749 else if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
751 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
752 if (!flt_argreg_array
[argreg
+ 1])
755 flt_argreg_array
[argreg
] = 1;
756 return FLOAT_ARG0_REGNUM
+ argreg
;
760 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
762 struct regcache
*regcache
,
763 CORE_ADDR bp_addr
, int nargs
,
765 CORE_ADDR sp
, int struct_return
,
766 CORE_ADDR struct_addr
)
768 int stack_offset
= 0;
769 int argreg
= ARG0_REGNUM
;
775 int len
, reg_size
= 0;
778 /* first force sp to a 4-byte alignment */
779 sp
= sh_frame_align (gdbarch
, sp
);
782 regcache_cooked_write_unsigned (regcache
,
783 STRUCT_RETURN_REGNUM
, struct_addr
);
785 /* make room on stack for args */
786 sp
-= sh_stack_allocsize (nargs
, args
);
788 /* Initialize float argument mechanism. */
789 sh_init_flt_argreg ();
791 /* Now load as many as possible of the first arguments into
792 registers, and push the rest onto the stack. There are 16 bytes
793 in four registers available. Loop thru args from first to last. */
794 for (argnum
= 0; argnum
< nargs
; argnum
++)
796 type
= VALUE_TYPE (args
[argnum
]);
797 len
= TYPE_LENGTH (type
);
798 val
= sh_justify_value_in_reg (args
[argnum
], len
);
800 /* Some decisions have to be made how various types are handled.
801 This also differs in different ABIs. */
804 pass_on_stack
= 1; /* Types bigger than 16 bytes are passed on stack. */
806 /* Find out the next register to use for a floating point value. */
807 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
808 flt_argreg
= sh_next_flt_argreg (len
);
812 if ((TYPE_CODE (type
) == TYPE_CODE_FLT
813 && flt_argreg
> FLOAT_ARGLAST_REGNUM
)
814 || argreg
> ARGLAST_REGNUM
|| pass_on_stack
)
816 /* The remainder of the data goes entirely on the stack,
818 reg_size
= (len
+ 3) & ~3;
819 write_memory (sp
+ stack_offset
, val
, reg_size
);
820 stack_offset
+= reg_size
;
822 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
823 && flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
825 /* Argument goes in a float argument register. */
826 reg_size
= register_size (gdbarch
, flt_argreg
);
827 regval
= extract_unsigned_integer (val
, reg_size
);
828 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
830 else if (argreg
<= ARGLAST_REGNUM
)
832 /* there's room in a register */
833 reg_size
= register_size (gdbarch
, argreg
);
834 regval
= extract_unsigned_integer (val
, reg_size
);
835 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
837 /* Store the value reg_size bytes at a time. This means that things
838 larger than reg_size bytes may go partly in registers and partly
845 /* Store return address. */
846 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
848 /* Update stack pointer. */
849 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
855 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
857 struct regcache
*regcache
,
859 int nargs
, struct value
**args
,
860 CORE_ADDR sp
, int struct_return
,
861 CORE_ADDR struct_addr
)
863 int stack_offset
= 0;
864 int argreg
= ARG0_REGNUM
;
871 /* first force sp to a 4-byte alignment */
872 sp
= sh_frame_align (gdbarch
, sp
);
875 regcache_cooked_write_unsigned (regcache
,
876 STRUCT_RETURN_REGNUM
, struct_addr
);
878 /* make room on stack for args */
879 sp
-= sh_stack_allocsize (nargs
, args
);
881 /* Now load as many as possible of the first arguments into
882 registers, and push the rest onto the stack. There are 16 bytes
883 in four registers available. Loop thru args from first to last. */
884 for (argnum
= 0; argnum
< nargs
; argnum
++)
886 type
= VALUE_TYPE (args
[argnum
]);
887 len
= TYPE_LENGTH (type
);
888 val
= sh_justify_value_in_reg (args
[argnum
], len
);
892 if (argreg
> ARGLAST_REGNUM
)
894 /* The remainder of the data goes entirely on the stack,
896 reg_size
= (len
+ 3) & ~3;
897 write_memory (sp
+ stack_offset
, val
, reg_size
);
898 stack_offset
+= reg_size
;
900 else if (argreg
<= ARGLAST_REGNUM
)
902 /* there's room in a register */
903 reg_size
= register_size (gdbarch
, argreg
);
904 regval
= extract_unsigned_integer (val
, reg_size
);
905 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
907 /* Store the value reg_size bytes at a time. This means that things
908 larger than reg_size bytes may go partly in registers and partly
915 /* Store return address. */
916 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
918 /* Update stack pointer. */
919 regcache_cooked_write_unsigned (regcache
, SP_REGNUM
, sp
);
924 /* Find a function's return value in the appropriate registers (in
925 regbuf), and copy it into valbuf. Extract from an array REGBUF
926 containing the (raw) register state a function return value of type
927 TYPE, and copy that, in virtual format, into VALBUF. */
929 sh_default_extract_return_value (struct type
*type
, struct regcache
*regcache
,
932 int len
= TYPE_LENGTH (type
);
933 int return_register
= R0_REGNUM
;
940 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
941 store_unsigned_integer (valbuf
, len
, c
);
945 int i
, regnum
= R0_REGNUM
;
946 for (i
= 0; i
< len
; i
+= 4)
947 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
950 error ("bad size for return value");
954 sh3e_sh4_extract_return_value (struct type
*type
, struct regcache
*regcache
,
957 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
959 int len
= TYPE_LENGTH (type
);
960 int i
, regnum
= FP0_REGNUM
;
961 for (i
= 0; i
< len
; i
+= 4)
962 regcache_raw_read (regcache
, regnum
++, (char *) valbuf
+ i
);
965 sh_default_extract_return_value (type
, regcache
, valbuf
);
968 /* Write into appropriate registers a function return value
969 of type TYPE, given in virtual format.
970 If the architecture is sh4 or sh3e, store a function's return value
971 in the R0 general register or in the FP0 floating point register,
972 depending on the type of the return value. In all the other cases
973 the result is stored in r0, left-justified. */
975 sh_default_store_return_value (struct type
*type
, struct regcache
*regcache
,
979 int len
= TYPE_LENGTH (type
);
983 val
= extract_unsigned_integer (valbuf
, len
);
984 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
988 int i
, regnum
= R0_REGNUM
;
989 for (i
= 0; i
< len
; i
+= 4)
990 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
995 sh3e_sh4_store_return_value (struct type
*type
, struct regcache
*regcache
,
998 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1000 int len
= TYPE_LENGTH (type
);
1001 int i
, regnum
= FP0_REGNUM
;
1002 for (i
= 0; i
< len
; i
+= 4)
1003 regcache_raw_write (regcache
, regnum
++, (char *) valbuf
+ i
);
1006 sh_default_store_return_value (type
, regcache
, valbuf
);
1009 /* Print the registers in a form similar to the E7000 */
1012 sh_generic_show_regs (void)
1014 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1015 paddr (read_register (PC_REGNUM
)),
1016 (long) read_register (SR_REGNUM
),
1017 (long) read_register (PR_REGNUM
),
1018 (long) read_register (MACH_REGNUM
),
1019 (long) read_register (MACL_REGNUM
));
1021 printf_filtered ("GBR=%08lx VBR=%08lx",
1022 (long) read_register (GBR_REGNUM
),
1023 (long) read_register (VBR_REGNUM
));
1026 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1027 (long) read_register (0), (long) read_register (1),
1028 (long) read_register (2), (long) read_register (3),
1029 (long) read_register (4), (long) read_register (5),
1030 (long) read_register (6), (long) read_register (7));
1031 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1032 (long) read_register (8), (long) read_register (9),
1033 (long) read_register (10), (long) read_register (11),
1034 (long) read_register (12), (long) read_register (13),
1035 (long) read_register (14), (long) read_register (15));
1039 sh3_show_regs (void)
1041 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1042 paddr (read_register (PC_REGNUM
)),
1043 (long) read_register (SR_REGNUM
),
1044 (long) read_register (PR_REGNUM
),
1045 (long) read_register (MACH_REGNUM
),
1046 (long) read_register (MACL_REGNUM
));
1048 printf_filtered ("GBR=%08lx VBR=%08lx",
1049 (long) read_register (GBR_REGNUM
),
1050 (long) read_register (VBR_REGNUM
));
1051 printf_filtered (" SSR=%08lx SPC=%08lx",
1052 (long) read_register (SSR_REGNUM
),
1053 (long) read_register (SPC_REGNUM
));
1056 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1057 (long) read_register (0), (long) read_register (1),
1058 (long) read_register (2), (long) read_register (3),
1059 (long) read_register (4), (long) read_register (5),
1060 (long) read_register (6), (long) read_register (7));
1061 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1062 (long) read_register (8), (long) read_register (9),
1063 (long) read_register (10), (long) read_register (11),
1064 (long) read_register (12), (long) read_register (13),
1065 (long) read_register (14), (long) read_register (15));
1070 sh2e_show_regs (void)
1072 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1073 paddr (read_register (PC_REGNUM
)),
1074 (long) read_register (SR_REGNUM
),
1075 (long) read_register (PR_REGNUM
),
1076 (long) read_register (MACH_REGNUM
),
1077 (long) read_register (MACL_REGNUM
));
1079 printf_filtered ("GBR=%08lx VBR=%08lx",
1080 (long) read_register (GBR_REGNUM
),
1081 (long) read_register (VBR_REGNUM
));
1082 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1083 (long) read_register (FPUL_REGNUM
),
1084 (long) read_register (FPSCR_REGNUM
));
1087 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1088 (long) read_register (0), (long) read_register (1),
1089 (long) read_register (2), (long) read_register (3),
1090 (long) read_register (4), (long) read_register (5),
1091 (long) read_register (6), (long) read_register (7));
1092 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1093 (long) read_register (8), (long) read_register (9),
1094 (long) read_register (10), (long) read_register (11),
1095 (long) read_register (12), (long) read_register (13),
1096 (long) read_register (14), (long) read_register (15));
1098 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 0), (long) read_register (FP0_REGNUM
+ 1), (long) read_register (FP0_REGNUM
+ 2), (long) read_register (FP0_REGNUM
+ 3), (long) read_register (FP0_REGNUM
+ 4), (long) read_register (FP0_REGNUM
+ 5), (long) read_register (FP0_REGNUM
+ 6), (long) read_register (FP0_REGNUM
+ 7));
1099 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 8), (long) read_register (FP0_REGNUM
+ 9), (long) read_register (FP0_REGNUM
+ 10), (long) read_register (FP0_REGNUM
+ 11), (long) read_register (FP0_REGNUM
+ 12), (long) read_register (FP0_REGNUM
+ 13), (long) read_register (FP0_REGNUM
+ 14), (long) read_register (FP0_REGNUM
+ 15));
1103 sh3e_show_regs (void)
1105 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1106 paddr (read_register (PC_REGNUM
)),
1107 (long) read_register (SR_REGNUM
),
1108 (long) read_register (PR_REGNUM
),
1109 (long) read_register (MACH_REGNUM
),
1110 (long) read_register (MACL_REGNUM
));
1112 printf_filtered ("GBR=%08lx VBR=%08lx",
1113 (long) read_register (GBR_REGNUM
),
1114 (long) read_register (VBR_REGNUM
));
1115 printf_filtered (" SSR=%08lx SPC=%08lx",
1116 (long) read_register (SSR_REGNUM
),
1117 (long) read_register (SPC_REGNUM
));
1118 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1119 (long) read_register (FPUL_REGNUM
),
1120 (long) read_register (FPSCR_REGNUM
));
1123 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1124 (long) read_register (0), (long) read_register (1),
1125 (long) read_register (2), (long) read_register (3),
1126 (long) read_register (4), (long) read_register (5),
1127 (long) read_register (6), (long) read_register (7));
1128 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1129 (long) read_register (8), (long) read_register (9),
1130 (long) read_register (10), (long) read_register (11),
1131 (long) read_register (12), (long) read_register (13),
1132 (long) read_register (14), (long) read_register (15));
1134 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 0), (long) read_register (FP0_REGNUM
+ 1), (long) read_register (FP0_REGNUM
+ 2), (long) read_register (FP0_REGNUM
+ 3), (long) read_register (FP0_REGNUM
+ 4), (long) read_register (FP0_REGNUM
+ 5), (long) read_register (FP0_REGNUM
+ 6), (long) read_register (FP0_REGNUM
+ 7));
1135 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM
+ 8), (long) read_register (FP0_REGNUM
+ 9), (long) read_register (FP0_REGNUM
+ 10), (long) read_register (FP0_REGNUM
+ 11), (long) read_register (FP0_REGNUM
+ 12), (long) read_register (FP0_REGNUM
+ 13), (long) read_register (FP0_REGNUM
+ 14), (long) read_register (FP0_REGNUM
+ 15));
1139 sh3_dsp_show_regs (void)
1141 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1142 paddr (read_register (PC_REGNUM
)),
1143 (long) read_register (SR_REGNUM
),
1144 (long) read_register (PR_REGNUM
),
1145 (long) read_register (MACH_REGNUM
),
1146 (long) read_register (MACL_REGNUM
));
1148 printf_filtered ("GBR=%08lx VBR=%08lx",
1149 (long) read_register (GBR_REGNUM
),
1150 (long) read_register (VBR_REGNUM
));
1152 printf_filtered (" SSR=%08lx SPC=%08lx",
1153 (long) read_register (SSR_REGNUM
),
1154 (long) read_register (SPC_REGNUM
));
1156 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM
));
1159 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1160 (long) read_register (0), (long) read_register (1),
1161 (long) read_register (2), (long) read_register (3),
1162 (long) read_register (4), (long) read_register (5),
1163 (long) read_register (6), (long) read_register (7));
1164 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1165 (long) read_register (8), (long) read_register (9),
1166 (long) read_register (10), (long) read_register (11),
1167 (long) read_register (12), (long) read_register (13),
1168 (long) read_register (14), (long) read_register (15));
1171 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1172 (long) read_register (A0G_REGNUM
) & 0xff,
1173 (long) read_register (A0_REGNUM
), (long) read_register (M0_REGNUM
),
1174 (long) read_register (X0_REGNUM
), (long) read_register (Y0_REGNUM
),
1175 (long) read_register (RS_REGNUM
), (long) read_register (MOD_REGNUM
));
1176 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1177 (long) read_register (A1G_REGNUM
) & 0xff,
1178 (long) read_register (A1_REGNUM
),
1179 (long) read_register (M1_REGNUM
),
1180 (long) read_register (X1_REGNUM
),
1181 (long) read_register (Y1_REGNUM
),
1182 (long) read_register (RE_REGNUM
));
1186 sh4_show_regs (void)
1188 int pr
= read_register (FPSCR_REGNUM
) & 0x80000;
1189 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1190 paddr (read_register (PC_REGNUM
)),
1191 (long) read_register (SR_REGNUM
),
1192 (long) read_register (PR_REGNUM
),
1193 (long) read_register (MACH_REGNUM
),
1194 (long) read_register (MACL_REGNUM
));
1196 printf_filtered ("GBR=%08lx VBR=%08lx",
1197 (long) read_register (GBR_REGNUM
),
1198 (long) read_register (VBR_REGNUM
));
1199 printf_filtered (" SSR=%08lx SPC=%08lx",
1200 (long) read_register (SSR_REGNUM
),
1201 (long) read_register (SPC_REGNUM
));
1202 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1203 (long) read_register (FPUL_REGNUM
),
1204 (long) read_register (FPSCR_REGNUM
));
1207 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1208 (long) read_register (0), (long) read_register (1),
1209 (long) read_register (2), (long) read_register (3),
1210 (long) read_register (4), (long) read_register (5),
1211 (long) read_register (6), (long) read_register (7));
1212 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1213 (long) read_register (8), (long) read_register (9),
1214 (long) read_register (10), (long) read_register (11),
1215 (long) read_register (12), (long) read_register (13),
1216 (long) read_register (14), (long) read_register (15));
1218 printf_filtered ((pr
1219 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1221 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1222 (long) read_register (FP0_REGNUM
+ 0),
1223 (long) read_register (FP0_REGNUM
+ 1),
1224 (long) read_register (FP0_REGNUM
+ 2),
1225 (long) read_register (FP0_REGNUM
+ 3),
1226 (long) read_register (FP0_REGNUM
+ 4),
1227 (long) read_register (FP0_REGNUM
+ 5),
1228 (long) read_register (FP0_REGNUM
+ 6),
1229 (long) read_register (FP0_REGNUM
+ 7));
1230 printf_filtered ((pr
?
1231 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1232 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1233 (long) read_register (FP0_REGNUM
+ 8),
1234 (long) read_register (FP0_REGNUM
+ 9),
1235 (long) read_register (FP0_REGNUM
+ 10),
1236 (long) read_register (FP0_REGNUM
+ 11),
1237 (long) read_register (FP0_REGNUM
+ 12),
1238 (long) read_register (FP0_REGNUM
+ 13),
1239 (long) read_register (FP0_REGNUM
+ 14),
1240 (long) read_register (FP0_REGNUM
+ 15));
1244 sh_dsp_show_regs (void)
1246 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1247 paddr (read_register (PC_REGNUM
)),
1248 (long) read_register (SR_REGNUM
),
1249 (long) read_register (PR_REGNUM
),
1250 (long) read_register (MACH_REGNUM
),
1251 (long) read_register (MACL_REGNUM
));
1253 printf_filtered ("GBR=%08lx VBR=%08lx",
1254 (long) read_register (GBR_REGNUM
),
1255 (long) read_register (VBR_REGNUM
));
1257 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM
));
1260 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1261 (long) read_register (0), (long) read_register (1),
1262 (long) read_register (2), (long) read_register (3),
1263 (long) read_register (4), (long) read_register (5),
1264 (long) read_register (6), (long) read_register (7));
1265 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1266 (long) read_register (8), (long) read_register (9),
1267 (long) read_register (10), (long) read_register (11),
1268 (long) read_register (12), (long) read_register (13),
1269 (long) read_register (14), (long) read_register (15));
1272 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1273 (long) read_register (A0G_REGNUM
) & 0xff,
1274 (long) read_register (A0_REGNUM
), (long) read_register (M0_REGNUM
),
1275 (long) read_register (X0_REGNUM
), (long) read_register (Y0_REGNUM
),
1276 (long) read_register (RS_REGNUM
), (long) read_register (MOD_REGNUM
));
1277 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1278 (long) read_register (A1G_REGNUM
) & 0xff,
1279 (long) read_register (A1_REGNUM
),
1280 (long) read_register (M1_REGNUM
),
1281 (long) read_register (X1_REGNUM
),
1282 (long) read_register (Y1_REGNUM
),
1283 (long) read_register (RE_REGNUM
));
1287 sh_show_regs_command (char *args
, int from_tty
)
1293 /* Return the GDB type object for the "standard" data type
1294 of data in register N. */
1295 static struct type
*
1296 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1298 if ((reg_nr
>= FP0_REGNUM
1299 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1300 return builtin_type_float
;
1302 return builtin_type_int
;
1305 static struct type
*
1306 sh_sh4_build_float_register_type (int high
)
1310 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
1311 return create_array_type (NULL
, builtin_type_float
, temp
);
1314 static struct type
*
1315 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1317 if ((reg_nr
>= FP0_REGNUM
1318 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1319 return builtin_type_float
;
1320 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1321 return builtin_type_double
;
1322 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1323 return sh_sh4_build_float_register_type (3);
1325 return builtin_type_int
;
1328 static struct type
*
1329 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1331 return builtin_type_int
;
1334 /* On the sh4, the DRi pseudo registers are problematic if the target
1335 is little endian. When the user writes one of those registers, for
1336 instance with 'ser var $dr0=1', we want the double to be stored
1338 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1339 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1341 This corresponds to little endian byte order & big endian word
1342 order. However if we let gdb write the register w/o conversion, it
1343 will write fr0 and fr1 this way:
1344 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1345 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1346 because it will consider fr0 and fr1 as a single LE stretch of memory.
1348 To achieve what we want we must force gdb to store things in
1349 floatformat_ieee_double_littlebyte_bigword (which is defined in
1350 include/floatformat.h and libiberty/floatformat.c.
1352 In case the target is big endian, there is no problem, the
1353 raw bytes will look like:
1354 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1355 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1357 The other pseudo registers (the FVs) also don't pose a problem
1358 because they are stored as 4 individual FP elements. */
1361 sh_sh4_register_convert_to_virtual (int regnum
, struct type
*type
,
1362 char *from
, char *to
)
1364 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1367 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1369 store_typed_floating (to
, type
, val
);
1373 ("sh_register_convert_to_virtual called with non DR register number");
1377 sh_sh4_register_convert_to_raw (struct type
*type
, int regnum
,
1378 const void *from
, void *to
)
1380 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1382 DOUBLEST val
= extract_typed_floating (from
, type
);
1383 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1387 error ("sh_register_convert_to_raw called with non DR register number");
1390 /* For vectors of 4 floating point registers. */
1392 fv_reg_base_num (int fv_regnum
)
1396 fp_regnum
= FP0_REGNUM
+ (fv_regnum
- FV0_REGNUM
) * 4;
1400 /* For double precision floating point registers, i.e 2 fp regs.*/
1402 dr_reg_base_num (int dr_regnum
)
1406 fp_regnum
= FP0_REGNUM
+ (dr_regnum
- DR0_REGNUM
) * 2;
1411 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1412 int reg_nr
, void *buffer
)
1414 int base_regnum
, portion
;
1415 char temp_buffer
[MAX_REGISTER_SIZE
];
1417 if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1419 base_regnum
= dr_reg_base_num (reg_nr
);
1421 /* Build the value in the provided buffer. */
1422 /* Read the real regs for which this one is an alias. */
1423 for (portion
= 0; portion
< 2; portion
++)
1424 regcache_raw_read (regcache
, base_regnum
+ portion
,
1426 + register_size (gdbarch
,
1427 base_regnum
) * portion
));
1428 /* We must pay attention to the endiannes. */
1429 sh_sh4_register_convert_to_virtual (reg_nr
,
1430 gdbarch_register_type (gdbarch
,
1432 temp_buffer
, buffer
);
1434 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1436 base_regnum
= fv_reg_base_num (reg_nr
);
1438 /* Read the real regs for which this one is an alias. */
1439 for (portion
= 0; portion
< 4; portion
++)
1440 regcache_raw_read (regcache
, base_regnum
+ portion
,
1442 + register_size (gdbarch
,
1443 base_regnum
) * portion
));
1448 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1449 int reg_nr
, const void *buffer
)
1451 int base_regnum
, portion
;
1452 char temp_buffer
[MAX_REGISTER_SIZE
];
1454 if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1456 base_regnum
= dr_reg_base_num (reg_nr
);
1458 /* We must pay attention to the endiannes. */
1459 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch
, reg_nr
),
1460 reg_nr
, buffer
, temp_buffer
);
1462 /* Write the real regs for which this one is an alias. */
1463 for (portion
= 0; portion
< 2; portion
++)
1464 regcache_raw_write (regcache
, base_regnum
+ portion
,
1466 + register_size (gdbarch
,
1467 base_regnum
) * portion
));
1469 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1471 base_regnum
= fv_reg_base_num (reg_nr
);
1473 /* Write the real regs for which this one is an alias. */
1474 for (portion
= 0; portion
< 4; portion
++)
1475 regcache_raw_write (regcache
, base_regnum
+ portion
,
1477 + register_size (gdbarch
,
1478 base_regnum
) * portion
));
1482 /* Floating point vector of 4 float registers. */
1484 do_fv_register_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1487 int first_fp_reg_num
= fv_reg_base_num (fv_regnum
);
1488 fprintf_filtered (file
, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1489 fv_regnum
- FV0_REGNUM
,
1490 (int) read_register (first_fp_reg_num
),
1491 (int) read_register (first_fp_reg_num
+ 1),
1492 (int) read_register (first_fp_reg_num
+ 2),
1493 (int) read_register (first_fp_reg_num
+ 3));
1496 /* Double precision registers. */
1498 do_dr_register_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1501 int first_fp_reg_num
= dr_reg_base_num (dr_regnum
);
1503 fprintf_filtered (file
, "dr%d\t0x%08x%08x\n",
1504 dr_regnum
- DR0_REGNUM
,
1505 (int) read_register (first_fp_reg_num
),
1506 (int) read_register (first_fp_reg_num
+ 1));
1510 sh_print_pseudo_register (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1513 if (regnum
< NUM_REGS
|| regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
1514 internal_error (__FILE__
, __LINE__
,
1515 "Invalid pseudo register number %d\n", regnum
);
1516 else if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1517 do_dr_register_info (gdbarch
, file
, regnum
);
1518 else if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
1519 do_fv_register_info (gdbarch
, file
, regnum
);
1523 sh_do_fp_register (struct gdbarch
*gdbarch
, struct ui_file
*file
, int regnum
)
1524 { /* do values for FP (float) regs */
1526 double flt
; /* double extracted from raw hex data */
1530 /* Allocate space for the float. */
1531 raw_buffer
= (char *) alloca (register_size (gdbarch
, FP0_REGNUM
));
1533 /* Get the data in raw format. */
1534 if (!frame_register_read (get_selected_frame (), regnum
, raw_buffer
))
1535 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
1537 /* Get the register as a number */
1538 flt
= unpack_double (builtin_type_float
, raw_buffer
, &inv
);
1540 /* Print the name and some spaces. */
1541 fputs_filtered (REGISTER_NAME (regnum
), file
);
1542 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), file
);
1544 /* Print the value. */
1546 fprintf_filtered (file
, "<invalid float>");
1548 fprintf_filtered (file
, "%-10.9g", flt
);
1550 /* Print the fp register as hex. */
1551 fprintf_filtered (file
, "\t(raw 0x");
1552 for (j
= 0; j
< register_size (gdbarch
, regnum
); j
++)
1554 register int idx
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? j
1555 : register_size (gdbarch
, regnum
) - 1 - j
;
1556 fprintf_filtered (file
, "%02x", (unsigned char) raw_buffer
[idx
]);
1558 fprintf_filtered (file
, ")");
1559 fprintf_filtered (file
, "\n");
1563 sh_do_register (struct gdbarch
*gdbarch
, struct ui_file
*file
, int regnum
)
1565 char raw_buffer
[MAX_REGISTER_SIZE
];
1567 fputs_filtered (REGISTER_NAME (regnum
), file
);
1568 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), file
);
1570 /* Get the data in raw format. */
1571 if (!frame_register_read (get_selected_frame (), regnum
, raw_buffer
))
1572 fprintf_filtered (file
, "*value not available*\n");
1574 val_print (gdbarch_register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
1575 file
, 'x', 1, 0, Val_pretty_default
);
1576 fprintf_filtered (file
, "\t");
1577 val_print (gdbarch_register_type (gdbarch
, regnum
), raw_buffer
, 0, 0,
1578 file
, 0, 1, 0, Val_pretty_default
);
1579 fprintf_filtered (file
, "\n");
1583 sh_print_register (struct gdbarch
*gdbarch
, struct ui_file
*file
, int regnum
)
1585 if (regnum
< 0 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
1586 internal_error (__FILE__
, __LINE__
,
1587 "Invalid register number %d\n", regnum
);
1589 else if (regnum
>= 0 && regnum
< NUM_REGS
)
1591 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
1593 sh_do_fp_register (gdbarch
, file
, regnum
); /* FP regs */
1595 sh_do_register (gdbarch
, file
, regnum
); /* All other regs */
1598 else if (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
1600 sh_print_pseudo_register (gdbarch
, file
, regnum
);
1605 sh_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1606 struct frame_info
*frame
, int regnum
, int fpregs
)
1608 if (regnum
!= -1) /* do one specified register */
1610 if (*(REGISTER_NAME (regnum
)) == '\0')
1611 error ("Not a valid register for the current processor type");
1613 sh_print_register (gdbarch
, file
, regnum
);
1616 /* do all (or most) registers */
1619 while (regnum
< NUM_REGS
)
1621 /* If the register name is empty, it is undefined for this
1622 processor, so don't display anything. */
1623 if (REGISTER_NAME (regnum
) == NULL
1624 || *(REGISTER_NAME (regnum
)) == '\0')
1630 if (TYPE_CODE (gdbarch_register_type (gdbarch
, regnum
)) ==
1635 /* true for "INFO ALL-REGISTERS" command */
1636 sh_do_fp_register (gdbarch
, file
, regnum
); /* FP regs */
1640 regnum
+= (FP_LAST_REGNUM
- FP0_REGNUM
); /* skip FP regs */
1644 sh_do_register (gdbarch
, file
, regnum
); /* All other regs */
1650 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
1652 sh_print_pseudo_register (gdbarch
, file
, regnum
);
1658 #ifdef SVR4_SHARED_LIBS
1660 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1661 for native i386 linux targets using the struct offsets defined in
1662 link.h (but without actual reference to that file).
1664 This makes it possible to access i386-linux shared libraries from
1665 a gdb that was not built on an i386-linux host (for cross debugging).
1668 struct link_map_offsets
*
1669 sh_linux_svr4_fetch_link_map_offsets (void)
1671 static struct link_map_offsets lmo
;
1672 static struct link_map_offsets
*lmp
= 0;
1678 lmo
.r_debug_size
= 8; /* 20 not actual size but all we need */
1680 lmo
.r_map_offset
= 4;
1683 lmo
.link_map_size
= 20; /* 552 not actual size but all we need */
1685 lmo
.l_addr_offset
= 0;
1686 lmo
.l_addr_size
= 4;
1688 lmo
.l_name_offset
= 4;
1689 lmo
.l_name_size
= 4;
1691 lmo
.l_next_offset
= 12;
1692 lmo
.l_next_size
= 4;
1694 lmo
.l_prev_offset
= 16;
1695 lmo
.l_prev_size
= 4;
1700 #endif /* SVR4_SHARED_LIBS */
1703 sh_dsp_register_sim_regno (int nr
)
1705 if (legacy_register_sim_regno (nr
) < 0)
1706 return legacy_register_sim_regno (nr
);
1707 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
1708 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
1709 if (nr
== MOD_REGNUM
)
1710 return SIM_SH_MOD_REGNUM
;
1711 if (nr
== RS_REGNUM
)
1712 return SIM_SH_RS_REGNUM
;
1713 if (nr
== RE_REGNUM
)
1714 return SIM_SH_RE_REGNUM
;
1715 if (nr
>= R0_BANK_REGNUM
&& nr
<= R7_BANK_REGNUM
)
1716 return nr
- R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
1720 static struct sh_frame_cache
*
1721 sh_alloc_frame_cache (void)
1723 struct sh_frame_cache
*cache
;
1726 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
1730 cache
->saved_sp
= 0;
1731 cache
->sp_offset
= 0;
1734 /* Frameless until proven otherwise. */
1737 /* Saved registers. We initialize these to -1 since zero is a valid
1738 offset (that's where fp is supposed to be stored). */
1739 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1741 cache
->saved_regs
[i
] = -1;
1747 static struct sh_frame_cache
*
1748 sh_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1750 struct sh_frame_cache
*cache
;
1751 CORE_ADDR current_pc
;
1757 cache
= sh_alloc_frame_cache ();
1758 *this_cache
= cache
;
1760 /* In principle, for normal frames, fp holds the frame pointer,
1761 which holds the base address for the current stack frame.
1762 However, for functions that don't need it, the frame pointer is
1763 optional. For these "frameless" functions the frame pointer is
1764 actually the frame pointer of the calling frame. */
1765 cache
->base
= frame_unwind_register_unsigned (next_frame
, FP_REGNUM
);
1766 if (cache
->base
== 0)
1769 cache
->pc
= frame_func_unwind (next_frame
);
1770 current_pc
= frame_pc_unwind (next_frame
);
1772 sh_analyze_prologue (cache
->pc
, current_pc
, cache
);
1774 if (!cache
->uses_fp
)
1776 /* We didn't find a valid frame, which means that CACHE->base
1777 currently holds the frame pointer for our calling frame. If
1778 we're at the start of a function, or somewhere half-way its
1779 prologue, the function's frame probably hasn't been fully
1780 setup yet. Try to reconstruct the base address for the stack
1781 frame by looking at the stack pointer. For truly "frameless"
1782 functions this might work too. */
1783 cache
->base
= frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
1786 /* Now that we have the base address for the stack frame we can
1787 calculate the value of sp in the calling frame. */
1788 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
1790 /* Adjust all the saved registers such that they contain addresses
1791 instead of offsets. */
1792 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1793 if (cache
->saved_regs
[i
] != -1)
1794 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
1800 sh_frame_prev_register (struct frame_info
*next_frame
, void **this_cache
,
1801 int regnum
, int *optimizedp
,
1802 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1803 int *realnump
, void *valuep
)
1805 struct sh_frame_cache
*cache
= sh_frame_cache (next_frame
, this_cache
);
1807 gdb_assert (regnum
>= 0);
1809 if (regnum
== SP_REGNUM
&& cache
->saved_sp
)
1817 /* Store the value. */
1818 store_unsigned_integer (valuep
, 4, cache
->saved_sp
);
1823 /* The PC of the previous frame is stored in the PR register of
1824 the current frame. Frob regnum so that we pull the value from
1825 the correct place. */
1826 if (regnum
== PC_REGNUM
)
1829 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
1832 *lvalp
= lval_memory
;
1833 *addrp
= cache
->saved_regs
[regnum
];
1837 /* Read the value in from memory. */
1838 read_memory (*addrp
, valuep
,
1839 register_size (current_gdbarch
, regnum
));
1844 frame_register_unwind (next_frame
, regnum
,
1845 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1849 sh_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1850 struct frame_id
*this_id
)
1852 struct sh_frame_cache
*cache
= sh_frame_cache (next_frame
, this_cache
);
1854 /* This marks the outermost frame. */
1855 if (cache
->base
== 0)
1858 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
1861 static const struct frame_unwind sh_frame_unwind
= {
1864 sh_frame_prev_register
1867 static const struct frame_unwind
*
1868 sh_frame_sniffer (struct frame_info
*next_frame
)
1870 return &sh_frame_unwind
;
1874 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1876 return frame_unwind_register_unsigned (next_frame
, SP_REGNUM
);
1880 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1882 return frame_unwind_register_unsigned (next_frame
, PC_REGNUM
);
1885 static struct frame_id
1886 sh_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1888 return frame_id_build (sh_unwind_sp (gdbarch
, next_frame
),
1889 frame_pc_unwind (next_frame
));
1893 sh_frame_base_address (struct frame_info
*next_frame
, void **this_cache
)
1895 struct sh_frame_cache
*cache
= sh_frame_cache (next_frame
, this_cache
);
1900 static const struct frame_base sh_frame_base
= {
1902 sh_frame_base_address
,
1903 sh_frame_base_address
,
1904 sh_frame_base_address
1907 /* The epilogue is defined here as the area at the end of a function,
1908 either on the `ret' instruction itself or after an instruction which
1909 destroys the function's stack frame. */
1911 sh_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1913 CORE_ADDR func_addr
= 0, func_end
= 0;
1915 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
1918 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
1919 for a nop and some fixed data (e.g. big offsets) which are
1920 unfortunately also treated as part of the function (which
1921 means, they are below func_end. */
1922 CORE_ADDR addr
= func_end
- 28;
1923 if (addr
< func_addr
+ 4)
1924 addr
= func_addr
+ 4;
1928 /* First search forward until hitting an rts. */
1929 while (addr
< func_end
1930 && !IS_RTS (read_memory_unsigned_integer (addr
, 2)))
1932 if (addr
>= func_end
)
1935 /* At this point we should find a mov.l @r15+,r14 instruction,
1936 either before or after the rts. If not, then the function has
1937 probably no "normal" epilogue and we bail out here. */
1938 inst
= read_memory_unsigned_integer (addr
- 2, 2);
1939 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2)))
1941 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2)))
1944 /* Step over possible lds.l @r15+,pr. */
1945 inst
= read_memory_unsigned_integer (addr
- 2, 2);
1949 inst
= read_memory_unsigned_integer (addr
- 2, 2);
1952 /* Step over possible mov r14,r15. */
1953 if (IS_MOV_FP_SP (inst
))
1956 inst
= read_memory_unsigned_integer (addr
- 2, 2);
1959 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
1961 while (addr
> func_addr
+ 4
1962 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
1965 inst
= read_memory_unsigned_integer (addr
- 2, 2);
1974 static gdbarch_init_ftype sh_gdbarch_init
;
1976 static struct gdbarch
*
1977 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1979 struct gdbarch
*gdbarch
;
1981 sh_show_regs
= sh_generic_show_regs
;
1982 switch (info
.bfd_arch_info
->mach
)
1985 sh_show_regs
= sh2e_show_regs
;
1987 case bfd_mach_sh_dsp
:
1988 sh_show_regs
= sh_dsp_show_regs
;
1992 sh_show_regs
= sh3_show_regs
;
1996 sh_show_regs
= sh3e_show_regs
;
1999 case bfd_mach_sh3_dsp
:
2000 sh_show_regs
= sh3_dsp_show_regs
;
2004 sh_show_regs
= sh4_show_regs
;
2008 sh_show_regs
= sh64_show_regs
;
2009 /* SH5 is handled entirely in sh64-tdep.c */
2010 return sh64_gdbarch_init (info
, arches
);
2013 /* If there is already a candidate, use it. */
2014 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2016 return arches
->gdbarch
;
2018 /* None found, create a new architecture from the information
2020 gdbarch
= gdbarch_alloc (&info
, NULL
);
2022 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2023 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2024 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2025 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2026 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2027 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2028 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2029 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2031 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2032 set_gdbarch_sp_regnum (gdbarch
, 15);
2033 set_gdbarch_pc_regnum (gdbarch
, 16);
2034 set_gdbarch_fp0_regnum (gdbarch
, -1);
2035 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2037 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2039 set_gdbarch_print_registers_info (gdbarch
, sh_print_registers_info
);
2041 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
2042 set_gdbarch_use_struct_convention (gdbarch
, sh_use_struct_convention
);
2044 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh
);
2045 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2047 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
2049 set_gdbarch_store_return_value (gdbarch
, sh_default_store_return_value
);
2050 set_gdbarch_extract_return_value (gdbarch
, sh_default_extract_return_value
);
2051 set_gdbarch_extract_struct_value_address (gdbarch
,
2052 sh_extract_struct_value_address
);
2054 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2055 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2056 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
2057 set_gdbarch_function_start_offset (gdbarch
, 0);
2059 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2061 set_gdbarch_frame_args_skip (gdbarch
, 0);
2062 set_gdbarch_frameless_function_invocation (gdbarch
,
2063 frameless_look_for_prologue
);
2064 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2066 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2067 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2068 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2069 set_gdbarch_unwind_dummy_id (gdbarch
, sh_unwind_dummy_id
);
2070 frame_base_set_default (gdbarch
, &sh_frame_base
);
2072 set_gdbarch_in_function_epilogue_p (gdbarch
, sh_in_function_epilogue_p
);
2074 switch (info
.bfd_arch_info
->mach
)
2077 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2081 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2085 /* doubles on sh2e and sh3e are actually 4 byte. */
2086 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2088 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2089 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2090 set_gdbarch_fp0_regnum (gdbarch
, 25);
2091 set_gdbarch_store_return_value (gdbarch
, sh3e_sh4_store_return_value
);
2092 set_gdbarch_extract_return_value (gdbarch
,
2093 sh3e_sh4_extract_return_value
);
2094 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2097 case bfd_mach_sh_dsp
:
2098 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
2099 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2103 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
2107 /* doubles on sh2e and sh3e are actually 4 byte. */
2108 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2110 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
2111 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2112 set_gdbarch_fp0_regnum (gdbarch
, 25);
2113 set_gdbarch_store_return_value (gdbarch
, sh3e_sh4_store_return_value
);
2114 set_gdbarch_extract_return_value (gdbarch
,
2115 sh3e_sh4_extract_return_value
);
2116 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2119 case bfd_mach_sh3_dsp
:
2120 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
2121 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2125 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
2126 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
2127 set_gdbarch_fp0_regnum (gdbarch
, 25);
2128 set_gdbarch_num_pseudo_regs (gdbarch
, 12);
2129 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2130 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2131 set_gdbarch_store_return_value (gdbarch
, sh3e_sh4_store_return_value
);
2132 set_gdbarch_extract_return_value (gdbarch
,
2133 sh3e_sh4_extract_return_value
);
2134 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2138 set_gdbarch_register_name (gdbarch
, sh_generic_register_name
);
2142 /* Hook in ABI-specific overrides, if they have been registered. */
2143 gdbarch_init_osabi (info
, gdbarch
);
2145 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
2146 frame_unwind_append_sniffer (gdbarch
, sh_frame_sniffer
);
2151 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
2154 _initialize_sh_tdep (void)
2156 struct cmd_list_element
*c
;
2158 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
2160 add_com ("regs", class_vars
, sh_show_regs_command
, "Print all registers");