1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "arch-utils.h"
36 #include "floatformat.h"
40 #include "reggroups.h"
45 #include "sh64-tdep.h"
48 #include "solib-svr4.h"
53 /* registers numbers shared with the simulator. */
54 #include "gdb/sim-sh.h"
57 /* List of "set sh ..." and "show sh ..." commands. */
58 static struct cmd_list_element
*setshcmdlist
= NULL
;
59 static struct cmd_list_element
*showshcmdlist
= NULL
;
61 static const char sh_cc_gcc
[] = "gcc";
62 static const char sh_cc_renesas
[] = "renesas";
63 static const char *const sh_cc_enum
[] = {
69 static const char *sh_active_calling_convention
= sh_cc_gcc
;
71 #define SH_NUM_REGS 67
80 /* Flag showing that a frame has been created in the prologue code. */
83 /* Saved registers. */
84 CORE_ADDR saved_regs
[SH_NUM_REGS
];
89 sh_is_renesas_calling_convention (struct type
*func_type
)
95 func_type
= check_typedef (func_type
);
97 if (TYPE_CODE (func_type
) == TYPE_CODE_PTR
)
98 func_type
= check_typedef (TYPE_TARGET_TYPE (func_type
));
100 if (TYPE_CODE (func_type
) == TYPE_CODE_FUNC
101 && TYPE_CALLING_CONVENTION (func_type
) == DW_CC_GNU_renesas_sh
)
105 if (sh_active_calling_convention
== sh_cc_renesas
)
112 sh_sh_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
114 static char *register_names
[] = {
115 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
116 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
117 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
119 "", "", "", "", "", "", "", "",
120 "", "", "", "", "", "", "", "",
122 "", "", "", "", "", "", "", "",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
128 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
130 return register_names
[reg_nr
];
134 sh_sh3_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
136 static char *register_names
[] = {
137 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
138 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
139 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
141 "", "", "", "", "", "", "", "",
142 "", "", "", "", "", "", "", "",
144 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
145 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
146 "", "", "", "", "", "", "", "",
150 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
152 return register_names
[reg_nr
];
156 sh_sh3e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
158 static char *register_names
[] = {
159 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
160 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
161 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
163 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
164 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
166 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
167 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
168 "", "", "", "", "", "", "", "",
172 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
174 return register_names
[reg_nr
];
178 sh_sh2e_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
180 static char *register_names
[] = {
181 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
182 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
183 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
185 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
186 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
188 "", "", "", "", "", "", "", "",
189 "", "", "", "", "", "", "", "",
190 "", "", "", "", "", "", "", "",
194 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
196 return register_names
[reg_nr
];
200 sh_sh2a_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
202 static char *register_names
[] = {
203 /* general registers 0-15 */
204 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
205 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
207 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 /* floating point registers 25 - 40 */
211 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
212 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
215 /* 43 - 62. Banked registers. The bank number used is determined by
216 the bank register (63). */
217 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
218 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
219 "machb", "ivnb", "prb", "gbrb", "maclb",
220 /* 63: register bank number, not a real register but used to
221 communicate the register bank currently get/set. This register
222 is hidden to the user, who manipulates it using the pseudo
223 register called "bank" (67). See below. */
226 "ibcr", "ibnr", "tbr",
227 /* 67: register bank number, the user visible pseudo register. */
229 /* double precision (pseudo) 68 - 75 */
230 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
234 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
236 return register_names
[reg_nr
];
240 sh_sh2a_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
242 static char *register_names
[] = {
243 /* general registers 0-15 */
244 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
245 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
247 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
250 /* floating point registers 25 - 40 */
251 "", "", "", "", "", "", "", "",
252 "", "", "", "", "", "", "", "",
255 /* 43 - 62. Banked registers. The bank number used is determined by
256 the bank register (63). */
257 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
258 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
259 "machb", "ivnb", "prb", "gbrb", "maclb",
260 /* 63: register bank number, not a real register but used to
261 communicate the register bank currently get/set. This register
262 is hidden to the user, who manipulates it using the pseudo
263 register called "bank" (67). See below. */
266 "ibcr", "ibnr", "tbr",
267 /* 67: register bank number, the user visible pseudo register. */
269 /* double precision (pseudo) 68 - 75 */
270 "", "", "", "", "", "", "", "",
274 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
276 return register_names
[reg_nr
];
280 sh_sh_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
282 static char *register_names
[] = {
283 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
284 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
285 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
287 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
288 "y0", "y1", "", "", "", "", "", "mod",
290 "rs", "re", "", "", "", "", "", "",
291 "", "", "", "", "", "", "", "",
292 "", "", "", "", "", "", "", "",
296 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
298 return register_names
[reg_nr
];
302 sh_sh3_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
304 static char *register_names
[] = {
305 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
306 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
307 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
309 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
310 "y0", "y1", "", "", "", "", "", "mod",
312 "rs", "re", "", "", "", "", "", "",
313 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
314 "", "", "", "", "", "", "", "",
315 "", "", "", "", "", "", "", "",
319 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
321 return register_names
[reg_nr
];
325 sh_sh4_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
327 static char *register_names
[] = {
328 /* general registers 0-15 */
329 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
330 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
332 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
335 /* floating point registers 25 - 40 */
336 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
337 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
341 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
343 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
345 "", "", "", "", "", "", "", "",
346 /* pseudo bank register. */
348 /* double precision (pseudo) 68 - 75 */
349 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
350 /* vectors (pseudo) 76 - 79 */
351 "fv0", "fv4", "fv8", "fv12",
352 /* FIXME: missing XF */
353 /* FIXME: missing XD */
357 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
359 return register_names
[reg_nr
];
363 sh_sh4_nofpu_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
365 static char *register_names
[] = {
366 /* general registers 0-15 */
367 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
370 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
373 /* floating point registers 25 - 40 -- not for nofpu target */
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
379 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
381 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
383 "", "", "", "", "", "", "", "",
384 /* pseudo bank register. */
386 /* double precision (pseudo) 68 - 75 -- not for nofpu target */
387 "", "", "", "", "", "", "", "",
388 /* vectors (pseudo) 76 - 79 -- not for nofpu target */
393 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
395 return register_names
[reg_nr
];
399 sh_sh4al_dsp_register_name (struct gdbarch
*gdbarch
, int reg_nr
)
401 static char *register_names
[] = {
402 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
403 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
404 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
406 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
407 "y0", "y1", "", "", "", "", "", "mod",
409 "rs", "re", "", "", "", "", "", "",
410 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
411 "", "", "", "", "", "", "", "",
412 "", "", "", "", "", "", "", "",
416 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
418 return register_names
[reg_nr
];
421 /* Implement the breakpoint_kind_from_pc gdbarch method. */
424 sh_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
429 /* Implement the sw_breakpoint_from_kind gdbarch method. */
431 static const gdb_byte
*
432 sh_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
436 /* For remote stub targets, trapa #20 is used. */
437 if (strcmp (target_shortname
, "remote") == 0)
439 static unsigned char big_remote_breakpoint
[] = { 0xc3, 0x20 };
440 static unsigned char little_remote_breakpoint
[] = { 0x20, 0xc3 };
442 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
443 return big_remote_breakpoint
;
445 return little_remote_breakpoint
;
449 /* 0xc3c3 is trapa #c3, and it works in big and little endian
451 static unsigned char breakpoint
[] = { 0xc3, 0xc3 };
457 GDBARCH_BREAKPOINT_FROM_PC (sh
)
459 /* Prologue looks like
463 sub <room_for_loca_vars>,r15
466 Actually it can be more complicated than this but that's it, basically. */
468 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
469 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
471 /* JSR @Rm 0100mmmm00001011 */
472 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
474 /* STS.L PR,@-r15 0100111100100010
475 r15-4-->r15, PR-->(r15) */
476 #define IS_STS(x) ((x) == 0x4f22)
478 /* STS.L MACL,@-r15 0100111100010010
479 r15-4-->r15, MACL-->(r15) */
480 #define IS_MACL_STS(x) ((x) == 0x4f12)
482 /* MOV.L Rm,@-r15 00101111mmmm0110
483 r15-4-->r15, Rm-->(R15) */
484 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
486 /* MOV r15,r14 0110111011110011
488 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
490 /* ADD #imm,r15 01111111iiiiiiii
492 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
494 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
495 #define IS_SHLL_R3(x) ((x) == 0x4300)
497 /* ADD r3,r15 0011111100111100
499 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
501 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
502 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
503 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
504 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
505 make this entirely clear. */
506 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
507 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
509 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
510 #define IS_MOV_ARG_TO_REG(x) \
511 (((x) & 0xf00f) == 0x6003 && \
512 ((x) & 0x00f0) >= 0x0040 && \
513 ((x) & 0x00f0) <= 0x0070)
514 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
515 #define IS_MOV_ARG_TO_IND_R14(x) \
516 (((x) & 0xff0f) == 0x2e02 && \
517 ((x) & 0x00f0) >= 0x0040 && \
518 ((x) & 0x00f0) <= 0x0070)
519 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
520 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
521 (((x) & 0xff00) == 0x1e00 && \
522 ((x) & 0x00f0) >= 0x0040 && \
523 ((x) & 0x00f0) <= 0x0070)
525 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
526 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
527 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
528 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
529 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
530 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
531 /* SUB Rn,R15 00111111nnnn1000 */
532 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
534 #define FPSCR_SZ (1 << 20)
536 /* The following instructions are used for epilogue testing. */
537 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
538 #define IS_RTS(x) ((x) == 0x000b)
539 #define IS_LDS(x) ((x) == 0x4f26)
540 #define IS_MACL_LDS(x) ((x) == 0x4f16)
541 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
542 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
543 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
546 sh_analyze_prologue (struct gdbarch
*gdbarch
,
547 CORE_ADDR pc
, CORE_ADDR limit_pc
,
548 struct sh_frame_cache
*cache
, ULONGEST fpscr
)
550 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
555 int reg
, sav_reg
= -1;
558 for (; pc
< limit_pc
; pc
+= 2)
560 inst
= read_memory_unsigned_integer (pc
, 2, byte_order
);
561 /* See where the registers will be saved to. */
564 cache
->saved_regs
[GET_SOURCE_REG (inst
)] = cache
->sp_offset
;
565 cache
->sp_offset
+= 4;
567 else if (IS_STS (inst
))
569 cache
->saved_regs
[PR_REGNUM
] = cache
->sp_offset
;
570 cache
->sp_offset
+= 4;
572 else if (IS_MACL_STS (inst
))
574 cache
->saved_regs
[MACL_REGNUM
] = cache
->sp_offset
;
575 cache
->sp_offset
+= 4;
577 else if (IS_MOV_R3 (inst
))
579 r3_val
= ((inst
& 0xff) ^ 0x80) - 0x80;
581 else if (IS_SHLL_R3 (inst
))
585 else if (IS_ADD_R3SP (inst
))
587 cache
->sp_offset
+= -r3_val
;
589 else if (IS_ADD_IMM_SP (inst
))
591 offset
= ((inst
& 0xff) ^ 0x80) - 0x80;
592 cache
->sp_offset
-= offset
;
594 else if (IS_MOVW_PCREL_TO_REG (inst
))
598 reg
= GET_TARGET_REG (inst
);
602 offset
= (inst
& 0xff) << 1;
604 read_memory_integer ((pc
+ 4) + offset
, 2, byte_order
);
608 else if (IS_MOVL_PCREL_TO_REG (inst
))
612 reg
= GET_TARGET_REG (inst
);
616 offset
= (inst
& 0xff) << 2;
618 read_memory_integer (((pc
& 0xfffffffc) + 4) + offset
,
623 else if (IS_MOVI20 (inst
)
624 && (pc
+ 2 < limit_pc
))
628 reg
= GET_TARGET_REG (inst
);
632 sav_offset
= GET_SOURCE_REG (inst
) << 16;
633 /* MOVI20 is a 32 bit instruction! */
636 |= read_memory_unsigned_integer (pc
, 2, byte_order
);
637 /* Now sav_offset contains an unsigned 20 bit value.
638 It must still get sign extended. */
639 if (sav_offset
& 0x00080000)
640 sav_offset
|= 0xfff00000;
644 else if (IS_SUB_REG_FROM_SP (inst
))
646 reg
= GET_SOURCE_REG (inst
);
647 if (sav_reg
> 0 && reg
== sav_reg
)
651 cache
->sp_offset
+= sav_offset
;
653 else if (IS_FPUSH (inst
))
655 if (fpscr
& FPSCR_SZ
)
657 cache
->sp_offset
+= 8;
661 cache
->sp_offset
+= 4;
664 else if (IS_MOV_SP_FP (inst
))
667 /* Don't go any further than six more instructions. */
668 limit_pc
= std::min (limit_pc
, pc
+ (2 * 6));
671 /* At this point, only allow argument register moves to other
672 registers or argument register moves to @(X,fp) which are
673 moving the register arguments onto the stack area allocated
674 by a former add somenumber to SP call. Don't allow moving
675 to an fp indirect address above fp + cache->sp_offset. */
676 for (; pc
< limit_pc
; pc
+= 2)
678 inst
= read_memory_integer (pc
, 2, byte_order
);
679 if (IS_MOV_ARG_TO_IND_R14 (inst
))
681 reg
= GET_SOURCE_REG (inst
);
682 if (cache
->sp_offset
> 0)
683 cache
->saved_regs
[reg
] = cache
->sp_offset
;
685 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst
))
687 reg
= GET_SOURCE_REG (inst
);
688 offset
= (inst
& 0xf) * 4;
689 if (cache
->sp_offset
> offset
)
690 cache
->saved_regs
[reg
] = cache
->sp_offset
- offset
;
692 else if (IS_MOV_ARG_TO_REG (inst
))
699 else if (IS_JSR (inst
))
701 /* We have found a jsr that has been scheduled into the prologue.
702 If we continue the scan and return a pc someplace after this,
703 then setting a breakpoint on this function will cause it to
704 appear to be called after the function it is calling via the
705 jsr, which will be very confusing. Most likely the next
706 instruction is going to be IS_MOV_SP_FP in the delay slot. If
707 so, note that before returning the current pc. */
708 if (pc
+ 2 < limit_pc
)
710 inst
= read_memory_integer (pc
+ 2, 2, byte_order
);
711 if (IS_MOV_SP_FP (inst
))
716 #if 0 /* This used to just stop when it found an instruction
717 that was not considered part of the prologue. Now,
718 we just keep going looking for likely
728 /* Skip any prologue before the guts of a function. */
730 sh_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
732 CORE_ADDR post_prologue_pc
, func_addr
, func_end_addr
, limit_pc
;
733 struct sh_frame_cache cache
;
735 /* See if we can determine the end of the prologue via the symbol table.
736 If so, then return either PC, or the PC after the prologue, whichever
738 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end_addr
))
740 post_prologue_pc
= skip_prologue_using_sal (gdbarch
, func_addr
);
741 if (post_prologue_pc
!= 0)
742 return std::max (pc
, post_prologue_pc
);
745 /* Can't determine prologue from the symbol table, need to examine
748 /* Find an upper limit on the function prologue using the debug
749 information. If the debug information could not be used to provide
750 that bound, then use an arbitrary large number as the upper bound. */
751 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
753 /* Don't go any further than 28 instructions. */
754 limit_pc
= pc
+ (2 * 28);
756 /* Do not allow limit_pc to be past the function end, if we know
757 where that end is... */
758 if (func_end_addr
!= 0)
759 limit_pc
= std::min (limit_pc
, func_end_addr
);
761 cache
.sp_offset
= -4;
762 post_prologue_pc
= sh_analyze_prologue (gdbarch
, pc
, limit_pc
, &cache
, 0);
764 pc
= post_prologue_pc
;
771 Aggregate types not bigger than 8 bytes that have the same size and
772 alignment as one of the integer scalar types are returned in the
773 same registers as the integer type they match.
775 For example, a 2-byte aligned structure with size 2 bytes has the
776 same size and alignment as a short int, and will be returned in R0.
777 A 4-byte aligned structure with size 8 bytes has the same size and
778 alignment as a long long int, and will be returned in R0 and R1.
780 When an aggregate type is returned in R0 and R1, R0 contains the
781 first four bytes of the aggregate, and R1 contains the
782 remainder. If the size of the aggregate type is not a multiple of 4
783 bytes, the aggregate is tail-padded up to a multiple of 4
784 bytes. The value of the padding is undefined. For little-endian
785 targets the padding will appear at the most significant end of the
786 last element, for big-endian targets the padding appears at the
787 least significant end of the last element.
789 All other aggregate types are returned by address. The caller
790 function passes the address of an area large enough to hold the
791 aggregate value in R2. The called function stores the result in
794 To reiterate, structs smaller than 8 bytes could also be returned
795 in memory, if they don't pass the "same size and alignment as an
800 struct s { char c[3]; } wibble;
801 struct s foo(void) { return wibble; }
803 the return value from foo() will be in memory, not
804 in R0, because there is no 3-byte integer type.
808 struct s { char c[2]; } wibble;
809 struct s foo(void) { return wibble; }
811 because a struct containing two chars has alignment 1, that matches
812 type char, but size 2, that matches type short. There's no integer
813 type that has alignment 1 and size 2, so the struct is returned in
817 sh_use_struct_convention (int renesas_abi
, struct type
*type
)
819 int len
= TYPE_LENGTH (type
);
820 int nelem
= TYPE_NFIELDS (type
);
822 /* The Renesas ABI returns aggregate types always on stack. */
823 if (renesas_abi
&& (TYPE_CODE (type
) == TYPE_CODE_STRUCT
824 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
827 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
828 fit in two registers anyway) use struct convention. */
829 if (len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8)
832 /* Scalar types and aggregate types with exactly one field are aligned
833 by definition. They are returned in registers. */
837 /* If the first field in the aggregate has the same length as the entire
838 aggregate type, the type is returned in registers. */
839 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == len
)
842 /* If the size of the aggregate is 8 bytes and the first field is
843 of size 4 bytes its alignment is equal to long long's alignment,
844 so it's returned in registers. */
845 if (len
== 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) == 4)
848 /* Otherwise use struct convention. */
853 sh_use_struct_convention_nofpu (int renesas_abi
, struct type
*type
)
855 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
856 if (renesas_abi
&& TYPE_NFIELDS (type
) == 0 && TYPE_LENGTH (type
) >= 8)
858 return sh_use_struct_convention (renesas_abi
, type
);
862 sh_frame_align (struct gdbarch
*ignore
, CORE_ADDR sp
)
867 /* Function: push_dummy_call (formerly push_arguments)
868 Setup the function arguments for calling a function in the inferior.
870 On the Renesas SH architecture, there are four registers (R4 to R7)
871 which are dedicated for passing function arguments. Up to the first
872 four arguments (depending on size) may go into these registers.
873 The rest go on the stack.
875 MVS: Except on SH variants that have floating point registers.
876 In that case, float and double arguments are passed in the same
877 manner, but using FP registers instead of GP registers.
879 Arguments that are smaller than 4 bytes will still take up a whole
880 register or a whole 32-bit word on the stack, and will be
881 right-justified in the register or the stack word. This includes
882 chars, shorts, and small aggregate types.
884 Arguments that are larger than 4 bytes may be split between two or
885 more registers. If there are not enough registers free, an argument
886 may be passed partly in a register (or registers), and partly on the
887 stack. This includes doubles, long longs, and larger aggregates.
888 As far as I know, there is no upper limit to the size of aggregates
889 that will be passed in this way; in other words, the convention of
890 passing a pointer to a large aggregate instead of a copy is not used.
892 MVS: The above appears to be true for the SH variants that do not
893 have an FPU, however those that have an FPU appear to copy the
894 aggregate argument onto the stack (and not place it in registers)
895 if it is larger than 16 bytes (four GP registers).
897 An exceptional case exists for struct arguments (and possibly other
898 aggregates such as arrays) if the size is larger than 4 bytes but
899 not a multiple of 4 bytes. In this case the argument is never split
900 between the registers and the stack, but instead is copied in its
901 entirety onto the stack, AND also copied into as many registers as
902 there is room for. In other words, space in registers permitting,
903 two copies of the same argument are passed in. As far as I can tell,
904 only the one on the stack is used, although that may be a function
905 of the level of compiler optimization. I suspect this is a compiler
906 bug. Arguments of these odd sizes are left-justified within the
907 word (as opposed to arguments smaller than 4 bytes, which are
910 If the function is to return an aggregate type such as a struct, it
911 is either returned in the normal return value register R0 (if its
912 size is no greater than one byte), or else the caller must allocate
913 space into which the callee will copy the return value (if the size
914 is greater than one byte). In this case, a pointer to the return
915 value location is passed into the callee in register R2, which does
916 not displace any of the other arguments passed in via registers R4
919 /* Helper function to justify value in register according to endianess. */
920 static const gdb_byte
*
921 sh_justify_value_in_reg (struct gdbarch
*gdbarch
, struct value
*val
, int len
)
923 static gdb_byte valbuf
[4];
925 memset (valbuf
, 0, sizeof (valbuf
));
928 /* value gets right-justified in the register or stack word. */
929 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
930 memcpy (valbuf
+ (4 - len
), value_contents (val
), len
);
932 memcpy (valbuf
, value_contents (val
), len
);
935 return value_contents (val
);
938 /* Helper function to eval number of bytes to allocate on stack. */
940 sh_stack_allocsize (int nargs
, struct value
**args
)
944 stack_alloc
+= ((TYPE_LENGTH (value_type (args
[nargs
])) + 3) & ~3);
948 /* Helper functions for getting the float arguments right. Registers usage
949 depends on the ABI and the endianess. The comments should enlighten how
950 it's intended to work. */
952 /* This array stores which of the float arg registers are already in use. */
953 static int flt_argreg_array
[FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
+ 1];
955 /* This function just resets the above array to "no reg used so far". */
957 sh_init_flt_argreg (void)
959 memset (flt_argreg_array
, 0, sizeof flt_argreg_array
);
962 /* This function returns the next register to use for float arg passing.
963 It returns either a valid value between FLOAT_ARG0_REGNUM and
964 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
965 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
967 Note that register number 0 in flt_argreg_array corresponds with the
968 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
969 29) the parity of the register number is preserved, which is important
970 for the double register passing test (see the "argreg & 1" test below). */
972 sh_next_flt_argreg (struct gdbarch
*gdbarch
, int len
, struct type
*func_type
)
976 /* First search for the next free register. */
977 for (argreg
= 0; argreg
<= FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
;
979 if (!flt_argreg_array
[argreg
])
982 /* No register left? */
983 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
984 return FLOAT_ARGLAST_REGNUM
+ 1;
988 /* Doubles are always starting in a even register number. */
991 /* In gcc ABI, the skipped register is lost for further argument
992 passing now. Not so in Renesas ABI. */
993 if (!sh_is_renesas_calling_convention (func_type
))
994 flt_argreg_array
[argreg
] = 1;
998 /* No register left? */
999 if (argreg
> FLOAT_ARGLAST_REGNUM
- FLOAT_ARG0_REGNUM
)
1000 return FLOAT_ARGLAST_REGNUM
+ 1;
1002 /* Also mark the next register as used. */
1003 flt_argreg_array
[argreg
+ 1] = 1;
1005 else if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1006 && !sh_is_renesas_calling_convention (func_type
))
1008 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
1009 if (!flt_argreg_array
[argreg
+ 1])
1012 flt_argreg_array
[argreg
] = 1;
1013 return FLOAT_ARG0_REGNUM
+ argreg
;
1016 /* Helper function which figures out, if a type is treated like a float type.
1018 The FPU ABIs have a special way how to treat types as float types.
1019 Structures with exactly one member, which is of type float or double, are
1020 treated exactly as the base types float or double:
1030 are handled the same way as just
1036 As a result, arguments of these struct types are pushed into floating point
1037 registers exactly as floats or doubles, using the same decision algorithm.
1039 The same is valid if these types are used as function return types. The
1040 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1041 or even using struct convention as it is for other structs. */
1044 sh_treat_as_flt_p (struct type
*type
)
1046 /* Ordinary float types are obviously treated as float. */
1047 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
1049 /* Otherwise non-struct types are not treated as float. */
1050 if (TYPE_CODE (type
) != TYPE_CODE_STRUCT
)
1052 /* Otherwise structs with more than one memeber are not treated as float. */
1053 if (TYPE_NFIELDS (type
) != 1)
1055 /* Otherwise if the type of that member is float, the whole type is
1056 treated as float. */
1057 if (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0)) == TYPE_CODE_FLT
)
1059 /* Otherwise it's not treated as float. */
1064 sh_push_dummy_call_fpu (struct gdbarch
*gdbarch
,
1065 struct value
*function
,
1066 struct regcache
*regcache
,
1067 CORE_ADDR bp_addr
, int nargs
,
1068 struct value
**args
,
1069 CORE_ADDR sp
, int struct_return
,
1070 CORE_ADDR struct_addr
)
1072 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1073 int stack_offset
= 0;
1074 int argreg
= ARG0_REGNUM
;
1077 struct type
*func_type
= value_type (function
);
1080 const gdb_byte
*val
;
1081 int len
, reg_size
= 0;
1082 int pass_on_stack
= 0;
1084 int last_reg_arg
= INT_MAX
;
1086 /* The Renesas ABI expects all varargs arguments, plus the last
1087 non-vararg argument to be on the stack, no matter how many
1088 registers have been used so far. */
1089 if (sh_is_renesas_calling_convention (func_type
)
1090 && TYPE_VARARGS (func_type
))
1091 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1093 /* First force sp to a 4-byte alignment. */
1094 sp
= sh_frame_align (gdbarch
, sp
);
1096 /* Make room on stack for args. */
1097 sp
-= sh_stack_allocsize (nargs
, args
);
1099 /* Initialize float argument mechanism. */
1100 sh_init_flt_argreg ();
1102 /* Now load as many as possible of the first arguments into
1103 registers, and push the rest onto the stack. There are 16 bytes
1104 in four registers available. Loop thru args from first to last. */
1105 for (argnum
= 0; argnum
< nargs
; argnum
++)
1107 type
= value_type (args
[argnum
]);
1108 len
= TYPE_LENGTH (type
);
1109 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1111 /* Some decisions have to be made how various types are handled.
1112 This also differs in different ABIs. */
1115 /* Find out the next register to use for a floating point value. */
1116 treat_as_flt
= sh_treat_as_flt_p (type
);
1118 flt_argreg
= sh_next_flt_argreg (gdbarch
, len
, func_type
);
1119 /* In Renesas ABI, long longs and aggregate types are always passed
1121 else if (sh_is_renesas_calling_convention (func_type
)
1122 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
== 8)
1123 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1124 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1126 /* In contrast to non-FPU CPUs, arguments are never split between
1127 registers and stack. If an argument doesn't fit in the remaining
1128 registers it's always pushed entirely on the stack. */
1129 else if (len
> ((ARGLAST_REGNUM
- argreg
+ 1) * 4))
1134 if ((treat_as_flt
&& flt_argreg
> FLOAT_ARGLAST_REGNUM
)
1135 || (!treat_as_flt
&& (argreg
> ARGLAST_REGNUM
1137 || argnum
> last_reg_arg
)
1139 /* The data goes entirely on the stack, 4-byte aligned. */
1140 reg_size
= (len
+ 3) & ~3;
1141 write_memory (sp
+ stack_offset
, val
, reg_size
);
1142 stack_offset
+= reg_size
;
1144 else if (treat_as_flt
&& flt_argreg
<= FLOAT_ARGLAST_REGNUM
)
1146 /* Argument goes in a float argument register. */
1147 reg_size
= register_size (gdbarch
, flt_argreg
);
1148 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1149 /* In little endian mode, float types taking two registers
1150 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1151 be stored swapped in the argument registers. The below
1152 code first writes the first 32 bits in the next but one
1153 register, increments the val and len values accordingly
1154 and then proceeds as normal by writing the second 32 bits
1155 into the next register. */
1156 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
1157 && TYPE_LENGTH (type
) == 2 * reg_size
)
1159 regcache_cooked_write_unsigned (regcache
, flt_argreg
+ 1,
1163 regval
= extract_unsigned_integer (val
, reg_size
,
1166 regcache_cooked_write_unsigned (regcache
, flt_argreg
++, regval
);
1168 else if (!treat_as_flt
&& argreg
<= ARGLAST_REGNUM
)
1170 /* there's room in a register */
1171 reg_size
= register_size (gdbarch
, argreg
);
1172 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1173 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1175 /* Store the value one register at a time or in one step on
1184 if (sh_is_renesas_calling_convention (func_type
))
1185 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1186 the stack and store the struct return address there. */
1187 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1189 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1190 its own dedicated register. */
1191 regcache_cooked_write_unsigned (regcache
,
1192 STRUCT_RETURN_REGNUM
, struct_addr
);
1195 /* Store return address. */
1196 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1198 /* Update stack pointer. */
1199 regcache_cooked_write_unsigned (regcache
,
1200 gdbarch_sp_regnum (gdbarch
), sp
);
1206 sh_push_dummy_call_nofpu (struct gdbarch
*gdbarch
,
1207 struct value
*function
,
1208 struct regcache
*regcache
,
1210 int nargs
, struct value
**args
,
1211 CORE_ADDR sp
, int struct_return
,
1212 CORE_ADDR struct_addr
)
1214 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1215 int stack_offset
= 0;
1216 int argreg
= ARG0_REGNUM
;
1218 struct type
*func_type
= value_type (function
);
1221 const gdb_byte
*val
;
1222 int len
, reg_size
= 0;
1223 int pass_on_stack
= 0;
1224 int last_reg_arg
= INT_MAX
;
1226 /* The Renesas ABI expects all varargs arguments, plus the last
1227 non-vararg argument to be on the stack, no matter how many
1228 registers have been used so far. */
1229 if (sh_is_renesas_calling_convention (func_type
)
1230 && TYPE_VARARGS (func_type
))
1231 last_reg_arg
= TYPE_NFIELDS (func_type
) - 2;
1233 /* First force sp to a 4-byte alignment. */
1234 sp
= sh_frame_align (gdbarch
, sp
);
1236 /* Make room on stack for args. */
1237 sp
-= sh_stack_allocsize (nargs
, args
);
1239 /* Now load as many as possible of the first arguments into
1240 registers, and push the rest onto the stack. There are 16 bytes
1241 in four registers available. Loop thru args from first to last. */
1242 for (argnum
= 0; argnum
< nargs
; argnum
++)
1244 type
= value_type (args
[argnum
]);
1245 len
= TYPE_LENGTH (type
);
1246 val
= sh_justify_value_in_reg (gdbarch
, args
[argnum
], len
);
1248 /* Some decisions have to be made how various types are handled.
1249 This also differs in different ABIs. */
1251 /* Renesas ABI pushes doubles and long longs entirely on stack.
1252 Same goes for aggregate types. */
1253 if (sh_is_renesas_calling_convention (func_type
)
1254 && ((TYPE_CODE (type
) == TYPE_CODE_INT
&& len
>= 8)
1255 || (TYPE_CODE (type
) == TYPE_CODE_FLT
&& len
>= 8)
1256 || TYPE_CODE (type
) == TYPE_CODE_STRUCT
1257 || TYPE_CODE (type
) == TYPE_CODE_UNION
))
1261 if (argreg
> ARGLAST_REGNUM
|| pass_on_stack
1262 || argnum
> last_reg_arg
)
1264 /* The remainder of the data goes entirely on the stack,
1266 reg_size
= (len
+ 3) & ~3;
1267 write_memory (sp
+ stack_offset
, val
, reg_size
);
1268 stack_offset
+= reg_size
;
1270 else if (argreg
<= ARGLAST_REGNUM
)
1272 /* There's room in a register. */
1273 reg_size
= register_size (gdbarch
, argreg
);
1274 regval
= extract_unsigned_integer (val
, reg_size
, byte_order
);
1275 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
1277 /* Store the value reg_size bytes at a time. This means that things
1278 larger than reg_size bytes may go partly in registers and partly
1287 if (sh_is_renesas_calling_convention (func_type
))
1288 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1289 the stack and store the struct return address there. */
1290 write_memory_unsigned_integer (sp
-= 4, 4, byte_order
, struct_addr
);
1292 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1293 its own dedicated register. */
1294 regcache_cooked_write_unsigned (regcache
,
1295 STRUCT_RETURN_REGNUM
, struct_addr
);
1298 /* Store return address. */
1299 regcache_cooked_write_unsigned (regcache
, PR_REGNUM
, bp_addr
);
1301 /* Update stack pointer. */
1302 regcache_cooked_write_unsigned (regcache
,
1303 gdbarch_sp_regnum (gdbarch
), sp
);
1308 /* Find a function's return value in the appropriate registers (in
1309 regbuf), and copy it into valbuf. Extract from an array REGBUF
1310 containing the (raw) register state a function return value of type
1311 TYPE, and copy that, in virtual format, into VALBUF. */
1313 sh_extract_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1316 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1317 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1318 int len
= TYPE_LENGTH (type
);
1324 regcache_cooked_read_unsigned (regcache
, R0_REGNUM
, &c
);
1325 store_unsigned_integer (valbuf
, len
, byte_order
, c
);
1329 int i
, regnum
= R0_REGNUM
;
1330 for (i
= 0; i
< len
; i
+= 4)
1331 regcache_raw_read (regcache
, regnum
++, valbuf
+ i
);
1334 error (_("bad size for return value"));
1338 sh_extract_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1341 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1342 if (sh_treat_as_flt_p (type
))
1344 int len
= TYPE_LENGTH (type
);
1345 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1346 for (i
= 0; i
< len
; i
+= 4)
1347 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1348 regcache_raw_read (regcache
, regnum
++,
1349 valbuf
+ len
- 4 - i
);
1351 regcache_raw_read (regcache
, regnum
++, valbuf
+ i
);
1354 sh_extract_return_value_nofpu (type
, regcache
, valbuf
);
1357 /* Write into appropriate registers a function return value
1358 of type TYPE, given in virtual format.
1359 If the architecture is sh4 or sh3e, store a function's return value
1360 in the R0 general register or in the FP0 floating point register,
1361 depending on the type of the return value. In all the other cases
1362 the result is stored in r0, left-justified. */
1364 sh_store_return_value_nofpu (struct type
*type
, struct regcache
*regcache
,
1365 const gdb_byte
*valbuf
)
1367 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1368 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1370 int len
= TYPE_LENGTH (type
);
1374 val
= extract_unsigned_integer (valbuf
, len
, byte_order
);
1375 regcache_cooked_write_unsigned (regcache
, R0_REGNUM
, val
);
1379 int i
, regnum
= R0_REGNUM
;
1380 for (i
= 0; i
< len
; i
+= 4)
1381 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1386 sh_store_return_value_fpu (struct type
*type
, struct regcache
*regcache
,
1387 const gdb_byte
*valbuf
)
1389 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
1390 if (sh_treat_as_flt_p (type
))
1392 int len
= TYPE_LENGTH (type
);
1393 int i
, regnum
= gdbarch_fp0_regnum (gdbarch
);
1394 for (i
= 0; i
< len
; i
+= 4)
1395 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_LITTLE
)
1396 regcache_raw_write (regcache
, regnum
++,
1397 valbuf
+ len
- 4 - i
);
1399 regcache_raw_write (regcache
, regnum
++, valbuf
+ i
);
1402 sh_store_return_value_nofpu (type
, regcache
, valbuf
);
1405 static enum return_value_convention
1406 sh_return_value_nofpu (struct gdbarch
*gdbarch
, struct value
*function
,
1407 struct type
*type
, struct regcache
*regcache
,
1408 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1410 struct type
*func_type
= function
? value_type (function
) : NULL
;
1412 if (sh_use_struct_convention_nofpu (
1413 sh_is_renesas_calling_convention (func_type
), type
))
1414 return RETURN_VALUE_STRUCT_CONVENTION
;
1416 sh_store_return_value_nofpu (type
, regcache
, writebuf
);
1418 sh_extract_return_value_nofpu (type
, regcache
, readbuf
);
1419 return RETURN_VALUE_REGISTER_CONVENTION
;
1422 static enum return_value_convention
1423 sh_return_value_fpu (struct gdbarch
*gdbarch
, struct value
*function
,
1424 struct type
*type
, struct regcache
*regcache
,
1425 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1427 struct type
*func_type
= function
? value_type (function
) : NULL
;
1429 if (sh_use_struct_convention (
1430 sh_is_renesas_calling_convention (func_type
), type
))
1431 return RETURN_VALUE_STRUCT_CONVENTION
;
1433 sh_store_return_value_fpu (type
, regcache
, writebuf
);
1435 sh_extract_return_value_fpu (type
, regcache
, readbuf
);
1436 return RETURN_VALUE_REGISTER_CONVENTION
;
1439 static struct type
*
1440 sh_sh2a_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1442 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1443 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1444 return builtin_type (gdbarch
)->builtin_float
;
1445 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1446 return builtin_type (gdbarch
)->builtin_double
;
1448 return builtin_type (gdbarch
)->builtin_int
;
1451 /* Return the GDB type object for the "standard" data type
1452 of data in register N. */
1453 static struct type
*
1454 sh_sh3e_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1456 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1457 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1458 return builtin_type (gdbarch
)->builtin_float
;
1460 return builtin_type (gdbarch
)->builtin_int
;
1463 static struct type
*
1464 sh_sh4_build_float_register_type (struct gdbarch
*gdbarch
, int high
)
1466 return lookup_array_range_type (builtin_type (gdbarch
)->builtin_float
,
1470 static struct type
*
1471 sh_sh4_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1473 if ((reg_nr
>= gdbarch_fp0_regnum (gdbarch
)
1474 && (reg_nr
<= FP_LAST_REGNUM
)) || (reg_nr
== FPUL_REGNUM
))
1475 return builtin_type (gdbarch
)->builtin_float
;
1476 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1477 return builtin_type (gdbarch
)->builtin_double
;
1478 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1479 return sh_sh4_build_float_register_type (gdbarch
, 3);
1481 return builtin_type (gdbarch
)->builtin_int
;
1484 static struct type
*
1485 sh_default_register_type (struct gdbarch
*gdbarch
, int reg_nr
)
1487 return builtin_type (gdbarch
)->builtin_int
;
1490 /* Is a register in a reggroup?
1491 The default code in reggroup.c doesn't identify system registers, some
1492 float registers or any of the vector registers.
1493 TODO: sh2a and dsp registers. */
1495 sh_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
1496 struct reggroup
*reggroup
)
1498 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
1499 || *gdbarch_register_name (gdbarch
, regnum
) == '\0')
1502 if (reggroup
== float_reggroup
1503 && (regnum
== FPUL_REGNUM
1504 || regnum
== FPSCR_REGNUM
))
1507 if (regnum
>= FV0_REGNUM
&& regnum
<= FV_LAST_REGNUM
)
1509 if (reggroup
== vector_reggroup
|| reggroup
== float_reggroup
)
1511 if (reggroup
== general_reggroup
)
1515 if (regnum
== VBR_REGNUM
1516 || regnum
== SR_REGNUM
1517 || regnum
== FPSCR_REGNUM
1518 || regnum
== SSR_REGNUM
1519 || regnum
== SPC_REGNUM
)
1521 if (reggroup
== system_reggroup
)
1523 if (reggroup
== general_reggroup
)
1527 /* The default code can cope with any other registers. */
1528 return default_register_reggroup_p (gdbarch
, regnum
, reggroup
);
1531 /* On the sh4, the DRi pseudo registers are problematic if the target
1532 is little endian. When the user writes one of those registers, for
1533 instance with 'set var $dr0=1', we want the double to be stored
1535 fr0 = 0x00 0x00 0xf0 0x3f
1536 fr1 = 0x00 0x00 0x00 0x00
1538 This corresponds to little endian byte order & big endian word
1539 order. However if we let gdb write the register w/o conversion, it
1540 will write fr0 and fr1 this way:
1541 fr0 = 0x00 0x00 0x00 0x00
1542 fr1 = 0x00 0x00 0xf0 0x3f
1543 because it will consider fr0 and fr1 as a single LE stretch of memory.
1545 To achieve what we want we must force gdb to store things in
1546 floatformat_ieee_double_littlebyte_bigword (which is defined in
1547 include/floatformat.h and libiberty/floatformat.c.
1549 In case the target is big endian, there is no problem, the
1550 raw bytes will look like:
1551 fr0 = 0x3f 0xf0 0x00 0x00
1552 fr1 = 0x00 0x00 0x00 0x00
1554 The other pseudo registers (the FVs) also don't pose a problem
1555 because they are stored as 4 individual FP elements. */
1558 sh_register_convert_to_virtual (struct gdbarch
*gdbarch
, int regnum
,
1559 struct type
*type
, gdb_byte
*from
, gdb_byte
*to
)
1561 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1563 /* It is a no-op. */
1564 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1568 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1571 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1573 store_typed_floating (to
, type
, val
);
1577 ("sh_register_convert_to_virtual called with non DR register number");
1581 sh_register_convert_to_raw (struct gdbarch
*gdbarch
, struct type
*type
,
1582 int regnum
, const gdb_byte
*from
, gdb_byte
*to
)
1584 if (gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_LITTLE
)
1586 /* It is a no-op. */
1587 memcpy (to
, from
, register_size (gdbarch
, regnum
));
1591 if (regnum
>= DR0_REGNUM
&& regnum
<= DR_LAST_REGNUM
)
1593 DOUBLEST val
= extract_typed_floating (from
, type
);
1594 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
,
1598 error (_("sh_register_convert_to_raw called with non DR register number"));
1601 /* For vectors of 4 floating point registers. */
1603 fv_reg_base_num (struct gdbarch
*gdbarch
, int fv_regnum
)
1607 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
1608 + (fv_regnum
- FV0_REGNUM
) * 4;
1612 /* For double precision floating point registers, i.e 2 fp regs. */
1614 dr_reg_base_num (struct gdbarch
*gdbarch
, int dr_regnum
)
1618 fp_regnum
= gdbarch_fp0_regnum (gdbarch
)
1619 + (dr_regnum
- DR0_REGNUM
) * 2;
1623 /* Concatenate PORTIONS contiguous raw registers starting at
1624 BASE_REGNUM into BUFFER. */
1626 static enum register_status
1627 pseudo_register_read_portions (struct gdbarch
*gdbarch
,
1628 struct regcache
*regcache
,
1630 int base_regnum
, gdb_byte
*buffer
)
1634 for (portion
= 0; portion
< portions
; portion
++)
1636 enum register_status status
;
1639 b
= buffer
+ register_size (gdbarch
, base_regnum
) * portion
;
1640 status
= regcache_raw_read (regcache
, base_regnum
+ portion
, b
);
1641 if (status
!= REG_VALID
)
1648 static enum register_status
1649 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1650 int reg_nr
, gdb_byte
*buffer
)
1653 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1654 enum register_status status
;
1656 if (reg_nr
== PSEUDO_BANK_REGNUM
)
1657 return regcache_raw_read (regcache
, BANK_REGNUM
, buffer
);
1658 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1660 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
1662 /* Build the value in the provided buffer. */
1663 /* Read the real regs for which this one is an alias. */
1664 status
= pseudo_register_read_portions (gdbarch
, regcache
,
1665 2, base_regnum
, temp_buffer
);
1666 if (status
== REG_VALID
)
1668 /* We must pay attention to the endiannes. */
1669 sh_register_convert_to_virtual (gdbarch
, reg_nr
,
1670 register_type (gdbarch
, reg_nr
),
1671 temp_buffer
, buffer
);
1675 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1677 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
1679 /* Read the real regs for which this one is an alias. */
1680 return pseudo_register_read_portions (gdbarch
, regcache
,
1681 4, base_regnum
, buffer
);
1684 gdb_assert_not_reached ("invalid pseudo register number");
1688 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1689 int reg_nr
, const gdb_byte
*buffer
)
1691 int base_regnum
, portion
;
1692 gdb_byte temp_buffer
[MAX_REGISTER_SIZE
];
1694 if (reg_nr
== PSEUDO_BANK_REGNUM
)
1696 /* When the bank register is written to, the whole register bank
1697 is switched and all values in the bank registers must be read
1698 from the target/sim again. We're just invalidating the regcache
1699 so that a re-read happens next time it's necessary. */
1702 regcache_raw_write (regcache
, BANK_REGNUM
, buffer
);
1703 for (bregnum
= R0_BANK0_REGNUM
; bregnum
< MACLB_REGNUM
; ++bregnum
)
1704 regcache_invalidate (regcache
, bregnum
);
1706 else if (reg_nr
>= DR0_REGNUM
&& reg_nr
<= DR_LAST_REGNUM
)
1708 base_regnum
= dr_reg_base_num (gdbarch
, reg_nr
);
1710 /* We must pay attention to the endiannes. */
1711 sh_register_convert_to_raw (gdbarch
, register_type (gdbarch
, reg_nr
),
1712 reg_nr
, buffer
, temp_buffer
);
1714 /* Write the real regs for which this one is an alias. */
1715 for (portion
= 0; portion
< 2; portion
++)
1716 regcache_raw_write (regcache
, base_regnum
+ portion
,
1718 + register_size (gdbarch
,
1719 base_regnum
) * portion
));
1721 else if (reg_nr
>= FV0_REGNUM
&& reg_nr
<= FV_LAST_REGNUM
)
1723 base_regnum
= fv_reg_base_num (gdbarch
, reg_nr
);
1725 /* Write the real regs for which this one is an alias. */
1726 for (portion
= 0; portion
< 4; portion
++)
1727 regcache_raw_write (regcache
, base_regnum
+ portion
,
1729 + register_size (gdbarch
,
1730 base_regnum
) * portion
));
1735 sh_dsp_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
1737 if (legacy_register_sim_regno (gdbarch
, nr
) < 0)
1738 return legacy_register_sim_regno (gdbarch
, nr
);
1739 if (nr
>= DSR_REGNUM
&& nr
<= Y1_REGNUM
)
1740 return nr
- DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
1741 if (nr
== MOD_REGNUM
)
1742 return SIM_SH_MOD_REGNUM
;
1743 if (nr
== RS_REGNUM
)
1744 return SIM_SH_RS_REGNUM
;
1745 if (nr
== RE_REGNUM
)
1746 return SIM_SH_RE_REGNUM
;
1747 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
1748 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
1753 sh_sh2a_register_sim_regno (struct gdbarch
*gdbarch
, int nr
)
1758 return SIM_SH_TBR_REGNUM
;
1760 return SIM_SH_IBNR_REGNUM
;
1762 return SIM_SH_IBCR_REGNUM
;
1764 return SIM_SH_BANK_REGNUM
;
1766 return SIM_SH_BANK_MACL_REGNUM
;
1768 return SIM_SH_BANK_GBR_REGNUM
;
1770 return SIM_SH_BANK_PR_REGNUM
;
1772 return SIM_SH_BANK_IVN_REGNUM
;
1774 return SIM_SH_BANK_MACH_REGNUM
;
1778 return legacy_register_sim_regno (gdbarch
, nr
);
1781 /* Set up the register unwinding such that call-clobbered registers are
1782 not displayed in frames >0 because the true value is not certain.
1783 The 'undefined' registers will show up as 'not available' unless the
1786 This function is currently set up for SH4 and compatible only. */
1789 sh_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1790 struct dwarf2_frame_state_reg
*reg
,
1791 struct frame_info
*this_frame
)
1793 /* Mark the PC as the destination for the return address. */
1794 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1795 reg
->how
= DWARF2_FRAME_REG_RA
;
1797 /* Mark the stack pointer as the call frame address. */
1798 else if (regnum
== gdbarch_sp_regnum (gdbarch
))
1799 reg
->how
= DWARF2_FRAME_REG_CFA
;
1801 /* The above was taken from the default init_reg in dwarf2-frame.c
1802 while the below is SH specific. */
1804 /* Caller save registers. */
1805 else if ((regnum
>= R0_REGNUM
&& regnum
<= R0_REGNUM
+7)
1806 || (regnum
>= FR0_REGNUM
&& regnum
<= FR0_REGNUM
+11)
1807 || (regnum
>= DR0_REGNUM
&& regnum
<= DR0_REGNUM
+5)
1808 || (regnum
>= FV0_REGNUM
&& regnum
<= FV0_REGNUM
+2)
1809 || (regnum
== MACH_REGNUM
)
1810 || (regnum
== MACL_REGNUM
)
1811 || (regnum
== FPUL_REGNUM
)
1812 || (regnum
== SR_REGNUM
))
1813 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
1815 /* Callee save registers. */
1816 else if ((regnum
>= R0_REGNUM
+8 && regnum
<= R0_REGNUM
+15)
1817 || (regnum
>= FR0_REGNUM
+12 && regnum
<= FR0_REGNUM
+15)
1818 || (regnum
>= DR0_REGNUM
+6 && regnum
<= DR0_REGNUM
+8)
1819 || (regnum
== FV0_REGNUM
+3))
1820 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1822 /* Other registers. These are not in the ABI and may or may not
1823 mean anything in frames >0 so don't show them. */
1824 else if ((regnum
>= R0_BANK0_REGNUM
&& regnum
<= R0_BANK0_REGNUM
+15)
1825 || (regnum
== GBR_REGNUM
)
1826 || (regnum
== VBR_REGNUM
)
1827 || (regnum
== FPSCR_REGNUM
)
1828 || (regnum
== SSR_REGNUM
)
1829 || (regnum
== SPC_REGNUM
))
1830 reg
->how
= DWARF2_FRAME_REG_UNDEFINED
;
1833 static struct sh_frame_cache
*
1834 sh_alloc_frame_cache (void)
1836 struct sh_frame_cache
*cache
;
1839 cache
= FRAME_OBSTACK_ZALLOC (struct sh_frame_cache
);
1843 cache
->saved_sp
= 0;
1844 cache
->sp_offset
= 0;
1847 /* Frameless until proven otherwise. */
1850 /* Saved registers. We initialize these to -1 since zero is a valid
1851 offset (that's where fp is supposed to be stored). */
1852 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1854 cache
->saved_regs
[i
] = -1;
1860 static struct sh_frame_cache
*
1861 sh_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
1863 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1864 struct sh_frame_cache
*cache
;
1865 CORE_ADDR current_pc
;
1869 return (struct sh_frame_cache
*) *this_cache
;
1871 cache
= sh_alloc_frame_cache ();
1872 *this_cache
= cache
;
1874 /* In principle, for normal frames, fp holds the frame pointer,
1875 which holds the base address for the current stack frame.
1876 However, for functions that don't need it, the frame pointer is
1877 optional. For these "frameless" functions the frame pointer is
1878 actually the frame pointer of the calling frame. */
1879 cache
->base
= get_frame_register_unsigned (this_frame
, FP_REGNUM
);
1880 if (cache
->base
== 0)
1883 cache
->pc
= get_frame_func (this_frame
);
1884 current_pc
= get_frame_pc (this_frame
);
1889 /* Check for the existence of the FPSCR register. If it exists,
1890 fetch its value for use in prologue analysis. Passing a zero
1891 value is the best choice for architecture variants upon which
1892 there's no FPSCR register. */
1893 if (gdbarch_register_reggroup_p (gdbarch
, FPSCR_REGNUM
, all_reggroup
))
1894 fpscr
= get_frame_register_unsigned (this_frame
, FPSCR_REGNUM
);
1898 sh_analyze_prologue (gdbarch
, cache
->pc
, current_pc
, cache
, fpscr
);
1901 if (!cache
->uses_fp
)
1903 /* We didn't find a valid frame, which means that CACHE->base
1904 currently holds the frame pointer for our calling frame. If
1905 we're at the start of a function, or somewhere half-way its
1906 prologue, the function's frame probably hasn't been fully
1907 setup yet. Try to reconstruct the base address for the stack
1908 frame by looking at the stack pointer. For truly "frameless"
1909 functions this might work too. */
1910 cache
->base
= get_frame_register_unsigned
1911 (this_frame
, gdbarch_sp_regnum (gdbarch
));
1914 /* Now that we have the base address for the stack frame we can
1915 calculate the value of sp in the calling frame. */
1916 cache
->saved_sp
= cache
->base
+ cache
->sp_offset
;
1918 /* Adjust all the saved registers such that they contain addresses
1919 instead of offsets. */
1920 for (i
= 0; i
< SH_NUM_REGS
; i
++)
1921 if (cache
->saved_regs
[i
] != -1)
1922 cache
->saved_regs
[i
] = cache
->saved_sp
- cache
->saved_regs
[i
] - 4;
1927 static struct value
*
1928 sh_frame_prev_register (struct frame_info
*this_frame
,
1929 void **this_cache
, int regnum
)
1931 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1932 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1934 gdb_assert (regnum
>= 0);
1936 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
1937 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
1939 /* The PC of the previous frame is stored in the PR register of
1940 the current frame. Frob regnum so that we pull the value from
1941 the correct place. */
1942 if (regnum
== gdbarch_pc_regnum (gdbarch
))
1945 if (regnum
< SH_NUM_REGS
&& cache
->saved_regs
[regnum
] != -1)
1946 return frame_unwind_got_memory (this_frame
, regnum
,
1947 cache
->saved_regs
[regnum
]);
1949 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
1953 sh_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
1954 struct frame_id
*this_id
)
1956 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
1958 /* This marks the outermost frame. */
1959 if (cache
->base
== 0)
1962 *this_id
= frame_id_build (cache
->saved_sp
, cache
->pc
);
1965 static const struct frame_unwind sh_frame_unwind
= {
1967 default_frame_unwind_stop_reason
,
1969 sh_frame_prev_register
,
1971 default_frame_sniffer
1975 sh_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1977 return frame_unwind_register_unsigned (next_frame
,
1978 gdbarch_sp_regnum (gdbarch
));
1982 sh_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1984 return frame_unwind_register_unsigned (next_frame
,
1985 gdbarch_pc_regnum (gdbarch
));
1988 static struct frame_id
1989 sh_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1991 CORE_ADDR sp
= get_frame_register_unsigned (this_frame
,
1992 gdbarch_sp_regnum (gdbarch
));
1993 return frame_id_build (sp
, get_frame_pc (this_frame
));
1997 sh_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
1999 struct sh_frame_cache
*cache
= sh_frame_cache (this_frame
, this_cache
);
2004 static const struct frame_base sh_frame_base
= {
2006 sh_frame_base_address
,
2007 sh_frame_base_address
,
2008 sh_frame_base_address
2011 static struct sh_frame_cache
*
2012 sh_make_stub_cache (struct frame_info
*this_frame
)
2014 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2015 struct sh_frame_cache
*cache
;
2017 cache
= sh_alloc_frame_cache ();
2020 = get_frame_register_unsigned (this_frame
, gdbarch_sp_regnum (gdbarch
));
2026 sh_stub_this_id (struct frame_info
*this_frame
, void **this_cache
,
2027 struct frame_id
*this_id
)
2029 struct sh_frame_cache
*cache
;
2031 if (*this_cache
== NULL
)
2032 *this_cache
= sh_make_stub_cache (this_frame
);
2033 cache
= (struct sh_frame_cache
*) *this_cache
;
2035 *this_id
= frame_id_build (cache
->saved_sp
, get_frame_pc (this_frame
));
2039 sh_stub_unwind_sniffer (const struct frame_unwind
*self
,
2040 struct frame_info
*this_frame
,
2041 void **this_prologue_cache
)
2043 CORE_ADDR addr_in_block
;
2045 addr_in_block
= get_frame_address_in_block (this_frame
);
2046 if (in_plt_section (addr_in_block
))
2052 static const struct frame_unwind sh_stub_unwind
=
2055 default_frame_unwind_stop_reason
,
2057 sh_frame_prev_register
,
2059 sh_stub_unwind_sniffer
2062 /* Implement the stack_frame_destroyed_p gdbarch method.
2064 The epilogue is defined here as the area at the end of a function,
2065 either on the `ret' instruction itself or after an instruction which
2066 destroys the function's stack frame. */
2069 sh_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2071 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2072 CORE_ADDR func_addr
= 0, func_end
= 0;
2074 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
2077 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2078 for a nop and some fixed data (e.g. big offsets) which are
2079 unfortunately also treated as part of the function (which
2080 means, they are below func_end. */
2081 CORE_ADDR addr
= func_end
- 28;
2082 if (addr
< func_addr
+ 4)
2083 addr
= func_addr
+ 4;
2087 /* First search forward until hitting an rts. */
2088 while (addr
< func_end
2089 && !IS_RTS (read_memory_unsigned_integer (addr
, 2, byte_order
)))
2091 if (addr
>= func_end
)
2094 /* At this point we should find a mov.l @r15+,r14 instruction,
2095 either before or after the rts. If not, then the function has
2096 probably no "normal" epilogue and we bail out here. */
2097 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2098 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr
- 2, 2,
2101 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr
+ 2, 2,
2105 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2107 /* Step over possible lds.l @r15+,macl. */
2108 if (IS_MACL_LDS (inst
))
2111 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2114 /* Step over possible lds.l @r15+,pr. */
2118 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2121 /* Step over possible mov r14,r15. */
2122 if (IS_MOV_FP_SP (inst
))
2125 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2128 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2130 while (addr
> func_addr
+ 4
2131 && (IS_ADD_REG_TO_FP (inst
) || IS_ADD_IMM_FP (inst
)))
2134 inst
= read_memory_unsigned_integer (addr
- 2, 2, byte_order
);
2137 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2138 That's allowed for the epilogue. */
2139 if ((gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a
2140 || gdbarch_bfd_arch_info (gdbarch
)->mach
== bfd_mach_sh2a_nofpu
)
2141 && addr
> func_addr
+ 6
2142 && IS_MOVI20 (read_memory_unsigned_integer (addr
- 4, 2,
2153 /* Supply register REGNUM from the buffer specified by REGS and LEN
2154 in the register set REGSET to register cache REGCACHE.
2155 REGTABLE specifies where each register can be found in REGS.
2156 If REGNUM is -1, do this for all registers in REGSET. */
2159 sh_corefile_supply_regset (const struct regset
*regset
,
2160 struct regcache
*regcache
,
2161 int regnum
, const void *regs
, size_t len
)
2163 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2165 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2166 ? tdep
->core_gregmap
2167 : tdep
->core_fpregmap
);
2170 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2172 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2173 && regmap
[i
].offset
+ 4 <= len
)
2174 regcache_raw_supply (regcache
, regmap
[i
].regnum
,
2175 (char *)regs
+ regmap
[i
].offset
);
2179 /* Collect register REGNUM in the register set REGSET from register cache
2180 REGCACHE into the buffer specified by REGS and LEN.
2181 REGTABLE specifies where each register can be found in REGS.
2182 If REGNUM is -1, do this for all registers in REGSET. */
2185 sh_corefile_collect_regset (const struct regset
*regset
,
2186 const struct regcache
*regcache
,
2187 int regnum
, void *regs
, size_t len
)
2189 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2190 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2191 const struct sh_corefile_regmap
*regmap
= (regset
== &sh_corefile_gregset
2192 ? tdep
->core_gregmap
2193 : tdep
->core_fpregmap
);
2196 for (i
= 0; regmap
[i
].regnum
!= -1; i
++)
2198 if ((regnum
== -1 || regnum
== regmap
[i
].regnum
)
2199 && regmap
[i
].offset
+ 4 <= len
)
2200 regcache_raw_collect (regcache
, regmap
[i
].regnum
,
2201 (char *)regs
+ regmap
[i
].offset
);
2205 /* The following two regsets have the same contents, so it is tempting to
2206 unify them, but they are distiguished by their address, so don't. */
2208 const struct regset sh_corefile_gregset
=
2211 sh_corefile_supply_regset
,
2212 sh_corefile_collect_regset
2215 static const struct regset sh_corefile_fpregset
=
2218 sh_corefile_supply_regset
,
2219 sh_corefile_collect_regset
2223 sh_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
2224 iterate_over_regset_sections_cb
*cb
,
2226 const struct regcache
*regcache
)
2228 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2230 if (tdep
->core_gregmap
!= NULL
)
2231 cb (".reg", tdep
->sizeof_gregset
, &sh_corefile_gregset
, NULL
, cb_data
);
2233 if (tdep
->core_fpregmap
!= NULL
)
2234 cb (".reg2", tdep
->sizeof_fpregset
, &sh_corefile_fpregset
, NULL
, cb_data
);
2237 /* This is the implementation of gdbarch method
2238 return_in_first_hidden_param_p. */
2241 sh_return_in_first_hidden_param_p (struct gdbarch
*gdbarch
,
2249 static struct gdbarch
*
2250 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2252 struct gdbarch
*gdbarch
;
2253 struct gdbarch_tdep
*tdep
;
2255 /* SH5 is handled entirely in sh64-tdep.c. */
2256 if (info
.bfd_arch_info
->mach
== bfd_mach_sh5
)
2257 return sh64_gdbarch_init (info
, arches
);
2259 /* If there is already a candidate, use it. */
2260 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
2262 return arches
->gdbarch
;
2264 /* None found, create a new architecture from the information
2266 tdep
= XCNEW (struct gdbarch_tdep
);
2267 gdbarch
= gdbarch_alloc (&info
, tdep
);
2269 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
2270 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2271 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2272 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2273 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2274 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2275 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
2276 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2278 set_gdbarch_num_regs (gdbarch
, SH_NUM_REGS
);
2279 set_gdbarch_sp_regnum (gdbarch
, 15);
2280 set_gdbarch_pc_regnum (gdbarch
, 16);
2281 set_gdbarch_fp0_regnum (gdbarch
, -1);
2282 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
2284 set_gdbarch_register_type (gdbarch
, sh_default_register_type
);
2285 set_gdbarch_register_reggroup_p (gdbarch
, sh_register_reggroup_p
);
2287 SET_GDBARCH_BREAKPOINT_MANIPULATION (sh
);
2289 set_gdbarch_print_insn (gdbarch
, print_insn_sh
);
2290 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
2292 set_gdbarch_return_value (gdbarch
, sh_return_value_nofpu
);
2294 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
2295 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2297 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_nofpu
);
2298 set_gdbarch_return_in_first_hidden_param_p (gdbarch
,
2299 sh_return_in_first_hidden_param_p
);
2301 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
2303 set_gdbarch_frame_align (gdbarch
, sh_frame_align
);
2304 set_gdbarch_unwind_sp (gdbarch
, sh_unwind_sp
);
2305 set_gdbarch_unwind_pc (gdbarch
, sh_unwind_pc
);
2306 set_gdbarch_dummy_id (gdbarch
, sh_dummy_id
);
2307 frame_base_set_default (gdbarch
, &sh_frame_base
);
2309 set_gdbarch_stack_frame_destroyed_p (gdbarch
, sh_stack_frame_destroyed_p
);
2311 dwarf2_frame_set_init_reg (gdbarch
, sh_dwarf2_frame_init_reg
);
2313 set_gdbarch_iterate_over_regset_sections
2314 (gdbarch
, sh_iterate_over_regset_sections
);
2316 switch (info
.bfd_arch_info
->mach
)
2319 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2323 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2327 /* doubles on sh2e and sh3e are actually 4 byte. */
2328 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2329 set_gdbarch_double_format (gdbarch
, floatformats_ieee_single
);
2331 set_gdbarch_register_name (gdbarch
, sh_sh2e_register_name
);
2332 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2333 set_gdbarch_fp0_regnum (gdbarch
, 25);
2334 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2335 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2339 set_gdbarch_register_name (gdbarch
, sh_sh2a_register_name
);
2340 set_gdbarch_register_type (gdbarch
, sh_sh2a_register_type
);
2341 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2343 set_gdbarch_fp0_regnum (gdbarch
, 25);
2344 set_gdbarch_num_pseudo_regs (gdbarch
, 9);
2345 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2346 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2347 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2348 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2351 case bfd_mach_sh2a_nofpu
:
2352 set_gdbarch_register_name (gdbarch
, sh_sh2a_nofpu_register_name
);
2353 set_gdbarch_register_sim_regno (gdbarch
, sh_sh2a_register_sim_regno
);
2355 set_gdbarch_num_pseudo_regs (gdbarch
, 1);
2356 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2357 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2360 case bfd_mach_sh_dsp
:
2361 set_gdbarch_register_name (gdbarch
, sh_sh_dsp_register_name
);
2362 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2366 case bfd_mach_sh3_nommu
:
2367 case bfd_mach_sh2a_nofpu_or_sh3_nommu
:
2368 set_gdbarch_register_name (gdbarch
, sh_sh3_register_name
);
2372 case bfd_mach_sh2a_or_sh3e
:
2373 /* doubles on sh2e and sh3e are actually 4 byte. */
2374 set_gdbarch_double_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
2375 set_gdbarch_double_format (gdbarch
, floatformats_ieee_single
);
2377 set_gdbarch_register_name (gdbarch
, sh_sh3e_register_name
);
2378 set_gdbarch_register_type (gdbarch
, sh_sh3e_register_type
);
2379 set_gdbarch_fp0_regnum (gdbarch
, 25);
2380 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2381 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2384 case bfd_mach_sh3_dsp
:
2385 set_gdbarch_register_name (gdbarch
, sh_sh3_dsp_register_name
);
2386 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2391 case bfd_mach_sh2a_or_sh4
:
2392 set_gdbarch_register_name (gdbarch
, sh_sh4_register_name
);
2393 set_gdbarch_register_type (gdbarch
, sh_sh4_register_type
);
2394 set_gdbarch_fp0_regnum (gdbarch
, 25);
2395 set_gdbarch_num_pseudo_regs (gdbarch
, 13);
2396 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
2397 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
2398 set_gdbarch_return_value (gdbarch
, sh_return_value_fpu
);
2399 set_gdbarch_push_dummy_call (gdbarch
, sh_push_dummy_call_fpu
);
2402 case bfd_mach_sh4_nofpu
:
2403 case bfd_mach_sh4a_nofpu
:
2404 case bfd_mach_sh4_nommu_nofpu
:
2405 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu
:
2406 set_gdbarch_register_name (gdbarch
, sh_sh4_nofpu_register_name
);
2409 case bfd_mach_sh4al_dsp
:
2410 set_gdbarch_register_name (gdbarch
, sh_sh4al_dsp_register_name
);
2411 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
2415 set_gdbarch_register_name (gdbarch
, sh_sh_register_name
);
2419 /* Hook in ABI-specific overrides, if they have been registered. */
2420 gdbarch_init_osabi (info
, gdbarch
);
2422 dwarf2_append_unwinders (gdbarch
);
2423 frame_unwind_append_unwinder (gdbarch
, &sh_stub_unwind
);
2424 frame_unwind_append_unwinder (gdbarch
, &sh_frame_unwind
);
2430 show_sh_command (char *args
, int from_tty
)
2432 help_list (showshcmdlist
, "show sh ", all_commands
, gdb_stdout
);
2436 set_sh_command (char *args
, int from_tty
)
2439 ("\"set sh\" must be followed by an appropriate subcommand.\n");
2440 help_list (setshcmdlist
, "set sh ", all_commands
, gdb_stdout
);
2443 extern initialize_file_ftype _initialize_sh_tdep
; /* -Wmissing-prototypes */
2446 _initialize_sh_tdep (void)
2448 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, NULL
);
2450 add_prefix_cmd ("sh", no_class
, set_sh_command
, "SH specific commands.",
2451 &setshcmdlist
, "set sh ", 0, &setlist
);
2452 add_prefix_cmd ("sh", no_class
, show_sh_command
, "SH specific commands.",
2453 &showshcmdlist
, "show sh ", 0, &showlist
);
2455 add_setshow_enum_cmd ("calling-convention", class_vars
, sh_cc_enum
,
2456 &sh_active_calling_convention
,
2457 _("Set calling convention used when calling target "
2458 "functions from GDB."),
2459 _("Show calling convention used when calling target "
2460 "functions from GDB."),
2461 _("gcc - Use GCC calling convention (default).\n"
2462 "renesas - Enforce Renesas calling convention."),
2464 &setshcmdlist
, &showshcmdlist
);