gdb/sh-tdep.c

   1 /* Target-dependent code for Hitachi Super-H, for GDB.
   2    Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc.
   3
   4 This file is part of GDB.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program; if not, write to the Free Software
  18 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  19
  20 /*
  21  Contributed by Steve Chamberlain
  22                 sac@cygnus.com
  23  */
  24
  25 #include "defs.h"
  26 #include "frame.h"
  27 #include "obstack.h"
  28 #include "symtab.h"
  29 #include "symfile.h"
  30 #include "gdbtypes.h"
  31 #include "gdbcmd.h"
  32 #include "gdbcore.h"
  33 #include "value.h"
  34 #include "dis-asm.h"
  35 #include "inferior.h"           /* for BEFORE_TEXT_END etc. */
  36 #include "gdb_string.h"
  37
  38 extern int remote_write_size;   /* in remote.c */
  39
  40 /* A set of original names, to be used when restoring back to generic
  41    registers from a specific set.  */
  42
  43 char *sh_generic_reg_names[] = REGISTER_NAMES;
  44
  45 char *sh_reg_names[] = {
  46   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  47   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  48   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  49   "",     "",
  50   "",     "",     "",     "",     "",     "",     "",     "",
  51   "",     "",     "",     "",     "",     "",     "",     "",
  52   "",     "",
  53   "",     "",     "",     "",     "",     "",     "",     "",
  54   "",     "",     "",     "",     "",     "",     "",     "",
  55 };
  56
  57 char *sh3_reg_names[] = {
  58   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  59   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  60   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  61   "",     "",
  62   "",     "",     "",     "",     "",     "",     "",     "",
  63   "",     "",     "",     "",     "",     "",     "",     "",
  64   "ssr",  "spc",
  65   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  66   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
  67 };
  68
  69 char *sh3e_reg_names[] = {
  70   "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
  71   "r8",   "r9",   "r10",  "r11",  "r12",  "r13",  "r14",  "r15",
  72   "pc",   "pr",   "gbr",  "vbr",  "mach", "macl", "sr",
  73   "fpul", "fpscr",
  74   "fr0",  "fr1",  "fr2",  "fr3",  "fr4",  "fr5",  "fr6",  "fr7",
  75   "fr8",  "fr9",  "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
  76   "ssr",  "spc",
  77   "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
  78   "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
  79 };
  80
  81 struct {
  82   char **regnames;
  83   int mach;
  84 } sh_processor_type_table[] = {
  85   { sh_reg_names, bfd_mach_sh },
  86   { sh3_reg_names, bfd_mach_sh3 },
  87   { sh3e_reg_names, bfd_mach_sh3e },
  88   /* start-sanitize-sh4 */
  89   { sh3e_reg_names, bfd_mach_sh4 },
  90   /* end-sanitize-sh4 */
  91   { NULL, 0 }
  92 };
  93
  94 /* Prologue looks like
  95    [mov.l       <regs>,@-r15]...
  96    [sts.l       pr,@-r15]
  97    [mov.l       r14,@-r15]
  98    [mov         r15,r14]
  99 */
 100
 101 #define IS_STS(x)               ((x) == 0x4f22)
 102 #define IS_PUSH(x)              (((x) & 0xff0f) == 0x2f06)
 103 #define GET_PUSHED_REG(x)       (((x) >> 4) & 0xf)
 104 #define IS_MOV_SP_FP(x)         ((x) == 0x6ef3)
 105 #define IS_ADD_SP(x)            (((x) & 0xff00) == 0x7f00)
 106 #define IS_MOV_R3(x)            (((x) & 0xff00) == 0x1a00)
 107 #define IS_SHLL_R3(x)           ((x) == 0x4300)
 108 #define IS_ADD_R3SP(x)          ((x) == 0x3f3c)
 109 /* start-sanitize-sh4 */
 110 #define IS_FMOV(x)              (((x) & 0xf00f) == 0xf00b)
 111 #define FPSCR_SZ                (1 << 20)
 112 /* end-sanitize-sh4 */
 113
 114 /* Skip any prologue before the guts of a function */
 115
 116 CORE_ADDR
 117 sh_skip_prologue (start_pc)
 118      CORE_ADDR start_pc;
 119 {
 120   int w;
 121
 122   w = read_memory_integer (start_pc, 2);
 123   while (IS_STS (w)
 124          /* start-sanitize-sh4 */
 125          || IS_FMOV (w)
 126          /* end-sanitize-sh4 */
 127          || IS_PUSH (w)
 128          || IS_MOV_SP_FP (w)
 129          || IS_MOV_R3 (w)
 130          || IS_ADD_R3SP (w)
 131          || IS_ADD_SP (w)
 132          || IS_SHLL_R3 (w))
 133     {
 134       start_pc += 2;
 135       w = read_memory_integer (start_pc, 2);
 136     }
 137
 138   return start_pc;
 139 }
 140
 141 /* Disassemble an instruction.  */
 142
 143 int
 144 gdb_print_insn_sh (memaddr, info)
 145      bfd_vma memaddr;
 146      disassemble_info *info;
 147 {
 148   if (TARGET_BYTE_ORDER == BIG_ENDIAN)
 149     return print_insn_sh (memaddr, info);
 150   else
 151     return print_insn_shl (memaddr, info);
 152 }
 153
 154 /* Given a GDB frame, determine the address of the calling function's frame.
 155    This will be used to create a new GDB frame struct, and then
 156    INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
 157
 158    For us, the frame address is its stack pointer value, so we look up
 159    the function prologue to determine the caller's sp value, and return it.  */
 160
 161 CORE_ADDR
 162 sh_frame_chain (frame)
 163      struct frame_info *frame;
 164 {
 165   if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
 166     return frame->frame;        /* dummy frame same as caller's frame */
 167   if (!inside_entry_file (frame->pc))
 168     return read_memory_integer (FRAME_FP (frame) + frame->f_offset, 4);
 169   else
 170     return 0;
 171 }
 172
 173 /* Find REGNUM on the stack.  Otherwise, it's in an active register.  One thing
 174    we might want to do here is to check REGNUM against the clobber mask, and
 175    somehow flag it as invalid if it isn't saved on the stack somewhere.  This
 176    would provide a graceful failure mode when trying to get the value of
 177    caller-saves registers for an inner frame.  */
 178
 179 CORE_ADDR
 180 sh_find_callers_reg (fi, regnum)
 181      struct frame_info *fi;
 182      int regnum;
 183 {
 184   struct frame_saved_regs fsr;
 185
 186   for (; fi; fi = fi->next)
 187     if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
 188       /* When the caller requests PR from the dummy frame, we return PC because
 189          that's where the previous routine appears to have done a call from. */
 190       return generic_read_register_dummy (fi->pc, fi->frame, regnum);
 191     else
 192       {
 193         FRAME_FIND_SAVED_REGS(fi, fsr);
 194         if (fsr.regs[regnum] != 0)
 195           return read_memory_integer (fsr.regs[regnum],
 196                                       REGISTER_RAW_SIZE(regnum));
 197       }
 198   return read_register (regnum);
 199 }
 200
 201 /* Put here the code to store, into a struct frame_saved_regs, the
 202    addresses of the saved registers of frame described by FRAME_INFO.
 203    This includes special registers such as pc and fp saved in special
 204    ways in the stack frame.  sp is even more special: the address we
 205    return for it IS the sp for the next frame. */
 206
 207 void
 208 sh_frame_find_saved_regs (fi, fsr)
 209      struct frame_info *fi;
 210      struct frame_saved_regs *fsr;
 211 {
 212   int where[NUM_REGS];
 213   int rn;
 214   int have_fp = 0;
 215   int depth;
 216   int pc;
 217   int opc;
 218   int insn;
 219   int r3_val = 0;
 220   char * dummy_regs = generic_find_dummy_frame (fi->pc, fi->frame);
 221
 222   if (dummy_regs)
 223     {
 224       /* DANGER!  This is ONLY going to work if the char buffer format of
 225          the saved registers is byte-for-byte identical to the
 226          CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
 227       memcpy (&fsr->regs, dummy_regs, sizeof(fsr));
 228       return;
 229     }
 230
 231   opc = pc = get_pc_function_start (fi->pc);
 232
 233   insn = read_memory_integer (pc, 2);
 234
 235   fi->leaf_function = 1;
 236   fi->f_offset = 0;
 237
 238   for (rn = 0; rn < NUM_REGS; rn++)
 239     where[rn] = -1;
 240
 241   depth = 0;
 242
 243   /* Loop around examining the prologue insns until we find something
 244      that does not appear to be part of the prologue.  But give up
 245      after 20 of them, since we're getting silly then. */
 246
 247   while (pc < opc + 20 * 2)
 248     {
 249       /* See where the registers will be saved to */
 250       if (IS_PUSH (insn))
 251         {
 252           pc += 2;
 253           rn = GET_PUSHED_REG (insn);
 254           where[rn] = depth;
 255           insn = read_memory_integer (pc, 2);
 256           depth += 4;
 257         }
 258       else if (IS_STS (insn))
 259         {
 260           pc += 2;
 261           where[PR_REGNUM] = depth;
 262           insn = read_memory_integer (pc, 2);
 263           /* If we're storing the pr then this isn't a leaf */
 264           fi->leaf_function = 0;
 265           depth += 4;
 266         }
 267       else if (IS_MOV_R3 (insn))
 268         {
 269           r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
 270           pc += 2;
 271           insn = read_memory_integer (pc, 2);
 272         }
 273       else if (IS_SHLL_R3 (insn))
 274         {
 275           r3_val <<= 1;
 276           pc += 2;
 277           insn = read_memory_integer (pc, 2);
 278         }
 279       else if (IS_ADD_R3SP (insn))
 280         {
 281           depth += -r3_val;
 282           pc += 2;
 283           insn = read_memory_integer (pc, 2);
 284         }
 285       else if (IS_ADD_SP (insn))
 286         {
 287           pc += 2;
 288           depth -= ((insn & 0xff) ^ 0x80) - 0x80;
 289           insn = read_memory_integer (pc, 2);
 290         }
 291       /* start-sanitize-sh4 */
 292       else if (IS_FMOV (insn))
 293         {
 294           pc += 2;
 295           insn = read_memory_integer (pc, 2);
 296           if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
 297             {
 298               depth += 8;
 299             }
 300           else
 301             {
 302               depth += 4;
 303             }
 304         }
 305       /* end-sanitize-sh4 */
 306       else
 307         break;
 308     }
 309
 310   /* Now we know how deep things are, we can work out their addresses */
 311
 312   for (rn = 0; rn < NUM_REGS; rn++)
 313     {
 314       if (where[rn] >= 0)
 315         {
 316           if (rn == FP_REGNUM)
 317             have_fp = 1;
 318
 319           fsr->regs[rn] = fi->frame - where[rn] + depth - 4;
 320         }
 321       else
 322         {
 323           fsr->regs[rn] = 0;
 324         }
 325     }
 326
 327   if (have_fp)
 328     {
 329       fsr->regs[SP_REGNUM] = read_memory_integer (fsr->regs[FP_REGNUM], 4);
 330     }
 331   else
 332     {
 333       fsr->regs[SP_REGNUM] = fi->frame - 4;
 334     }
 335
 336   fi->f_offset = depth - where[FP_REGNUM] - 4;
 337   /* Work out the return pc - either from the saved pr or the pr
 338      value */
 339 }
 340
 341 /* initialize the extra info saved in a FRAME */
 342
 343 void
 344 sh_init_extra_frame_info (fromleaf, fi)
 345      int fromleaf;
 346      struct frame_info *fi;
 347 {
 348   struct frame_saved_regs fsr;
 349
 350   if (fi->next)
 351     fi->pc = FRAME_SAVED_PC (fi->next);
 352
 353   if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
 354     {
 355       /* We need to setup fi->frame here because run_stack_dummy gets it wrong
 356          by assuming it's always FP.  */
 357       fi->frame     = generic_read_register_dummy (fi->pc, fi->frame,
 358                                                    SP_REGNUM);
 359       fi->return_pc = generic_read_register_dummy (fi->pc, fi->frame,
 360                                                    PC_REGNUM);
 361       fi->f_offset = -(CALL_DUMMY_LENGTH + 4);
 362       fi->leaf_function = 0;
 363       return;
 364     }
 365   else
 366     {
 367       FRAME_FIND_SAVED_REGS (fi, fsr);
 368       fi->return_pc = sh_find_callers_reg (fi, PR_REGNUM);
 369     }
 370 }
 371
 372 /* Discard from the stack the innermost frame,
 373    restoring all saved registers.  */
 374
 375 void
 376 sh_pop_frame ()
 377 {
 378   register struct frame_info *frame = get_current_frame ();
 379   register CORE_ADDR fp;
 380   register int regnum;
 381   struct frame_saved_regs fsr;
 382
 383   if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
 384     generic_pop_dummy_frame ();
 385   else
 386   {
 387     fp = FRAME_FP (frame);
 388     get_frame_saved_regs (frame, &fsr);
 389
 390     /* Copy regs from where they were saved in the frame */
 391     for (regnum = 0; regnum < NUM_REGS; regnum++)
 392       if (fsr.regs[regnum])
 393         write_register (regnum, read_memory_integer (fsr.regs[regnum], 4));
 394
 395     write_register (PC_REGNUM, frame->return_pc);
 396     write_register (SP_REGNUM, fp + 4);
 397   }
 398   flush_cached_frames ();
 399 }
 400
 401 /* Function: push_arguments
 402    Setup the function arguments for calling a function in the inferior.
 403
 404    On the Hitachi SH architecture, there are four registers (R4 to R7)
 405    which are dedicated for passing function arguments.  Up to the first
 406    four arguments (depending on size) may go into these registers.
 407    The rest go on the stack.
 408
 409    Arguments that are smaller than 4 bytes will still take up a whole
 410    register or a whole 32-bit word on the stack, and will be
 411    right-justified in the register or the stack word.  This includes
 412    chars, shorts, and small aggregate types.
 413
 414    Arguments that are larger than 4 bytes may be split between two or
 415    more registers.  If there are not enough registers free, an argument
 416    may be passed partly in a register (or registers), and partly on the
 417    stack.  This includes doubles, long longs, and larger aggregates.
 418    As far as I know, there is no upper limit to the size of aggregates
 419    that will be passed in this way; in other words, the convention of
 420    passing a pointer to a large aggregate instead of a copy is not used.
 421
 422    An exceptional case exists for struct arguments (and possibly other
 423    aggregates such as arrays) if the size is larger than 4 bytes but
 424    not a multiple of 4 bytes.  In this case the argument is never split
 425    between the registers and the stack, but instead is copied in its
 426    entirety onto the stack, AND also copied into as many registers as
 427    there is room for.  In other words, space in registers permitting,
 428    two copies of the same argument are passed in.  As far as I can tell,
 429    only the one on the stack is used, although that may be a function
 430    of the level of compiler optimization.  I suspect this is a compiler
 431    bug.  Arguments of these odd sizes are left-justified within the
 432    word (as opposed to arguments smaller than 4 bytes, which are
 433    right-justified).
 434
 435
 436    If the function is to return an aggregate type such as a struct, it
 437    is either returned in the normal return value register R0 (if its
 438    size is no greater than one byte), or else the caller must allocate
 439    space into which the callee will copy the return value (if the size
 440    is greater than one byte).  In this case, a pointer to the return
 441    value location is passed into the callee in register R2, which does
 442    not displace any of the other arguments passed in via registers R4
 443    to R7.   */
 444
 445 CORE_ADDR
 446 sh_push_arguments (nargs, args, sp, struct_return, struct_addr)
 447      int nargs;
 448      value_ptr *args;
 449      CORE_ADDR sp;
 450      unsigned char struct_return;
 451      CORE_ADDR struct_addr;
 452 {
 453   int stack_offset, stack_alloc;
 454   int argreg;
 455   int argnum;
 456   struct type *type;
 457   CORE_ADDR regval;
 458   char *val;
 459   char valbuf[4];
 460   int len;
 461   int odd_sized_struct;
 462
 463   /* first force sp to a 4-byte alignment */
 464   sp = sp & ~3;
 465
 466   /* The "struct return pointer" pseudo-argument has its own dedicated
 467      register */
 468   if (struct_return)
 469       write_register (STRUCT_RETURN_REGNUM, struct_addr);
 470
 471   /* Now make sure there's space on the stack */
 472   for (argnum = 0, stack_alloc = 0;
 473        argnum < nargs; argnum++)
 474     stack_alloc += ((TYPE_LENGTH(VALUE_TYPE(args[argnum])) + 3) & ~3);
 475   sp -= stack_alloc;    /* make room on stack for args */
 476
 477
 478   /* Now load as many as possible of the first arguments into
 479      registers, and push the rest onto the stack.  There are 16 bytes
 480      in four registers available.  Loop thru args from first to last.  */
 481
 482   argreg = ARG0_REGNUM;
 483   for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
 484     {
 485       type = VALUE_TYPE (args[argnum]);
 486       len  = TYPE_LENGTH (type);
 487       memset(valbuf, 0, sizeof(valbuf));
 488       if (len < 4)
 489         { /* value gets right-justified in the register or stack word */
 490           memcpy(valbuf + (4 - len),
 491                  (char *) VALUE_CONTENTS (args[argnum]), len);
 492           val = valbuf;
 493         }
 494       else
 495         val = (char *) VALUE_CONTENTS (args[argnum]);
 496
 497       if (len > 4 && (len & 3) != 0)
 498         odd_sized_struct = 1;           /* such structs go entirely on stack */
 499       else
 500         odd_sized_struct = 0;
 501       while (len > 0)
 502         {
 503           if (argreg > ARGLAST_REGNUM || odd_sized_struct)
 504             {                           /* must go on the stack */
 505               write_memory (sp + stack_offset, val, 4);
 506               stack_offset += 4;
 507             }
 508           /* NOTE WELL!!!!!  This is not an "else if" clause!!!
 509              That's because some *&^%$ things get passed on the stack
 510              AND in the registers!   */
 511           if (argreg <= ARGLAST_REGNUM)
 512             {                           /* there's room in a register */
 513               regval = extract_address (val, REGISTER_RAW_SIZE(argreg));
 514               write_register (argreg++, regval);
 515             }
 516           /* Store the value 4 bytes at a time.  This means that things
 517              larger than 4 bytes may go partly in registers and partly
 518              on the stack.  */
 519           len -= REGISTER_RAW_SIZE(argreg);
 520           val += REGISTER_RAW_SIZE(argreg);
 521         }
 522     }
 523   return sp;
 524 }
 525
 526 /* Function: push_return_address (pc)
 527    Set up the return address for the inferior function call.
 528    Needed for targets where we don't actually execute a JSR/BSR instruction */
 529
 530 CORE_ADDR
 531 sh_push_return_address (pc, sp)
 532      CORE_ADDR pc;
 533      CORE_ADDR sp;
 534 {
 535   write_register (PR_REGNUM, CALL_DUMMY_ADDRESS ());
 536   return sp;
 537 }
 538
 539 /* Function: fix_call_dummy
 540    Poke the callee function's address into the destination part of
 541    the CALL_DUMMY.  The address is actually stored in a data word
 542    following the actualy CALL_DUMMY instructions, which will load
 543    it into a register using PC-relative addressing.  This function
 544    expects the CALL_DUMMY to look like this:
 545
 546         mov.w @(2,PC), R8
 547         jsr   @R8
 548         nop
 549         trap
 550         <destination>
 551   */
 552
 553 #if 0
 554 void
 555 sh_fix_call_dummy (dummy, pc, fun, nargs, args, type, gcc_p)
 556      char *dummy;
 557      CORE_ADDR pc;
 558      CORE_ADDR fun;
 559      int nargs;
 560      value_ptr *args;
 561      struct type *type;
 562      int gcc_p;
 563 {
 564   *(unsigned long *) (dummy + 8) = fun;
 565 }
 566 #endif
 567
 568 /* Function: get_saved_register
 569    Just call the generic_get_saved_register function.  */
 570
 571 void
 572 get_saved_register (raw_buffer, optimized, addrp, frame, regnum, lval)
 573      char *raw_buffer;
 574      int *optimized;
 575      CORE_ADDR *addrp;
 576      struct frame_info *frame;
 577      int regnum;
 578      enum lval_type *lval;
 579 {
 580   generic_get_saved_register (raw_buffer, optimized, addrp,
 581                               frame, regnum, lval);
 582 }
 583
 584
 585 /* Modify the actual processor type. */
 586
 587 int
 588 sh_target_architecture_hook (ap)
 589      const bfd_arch_info_type *ap;
 590 {
 591   int i, j;
 592
 593   if (ap->arch != bfd_arch_sh)
 594     return 0;
 595
 596   for (i = 0; sh_processor_type_table[i].regnames != NULL; i++)
 597     {
 598       if (sh_processor_type_table[i].mach == ap->mach)
 599         {
 600           for (j = 0; j < NUM_REGS; ++j)
 601             reg_names[j] = sh_processor_type_table[i].regnames[j];
 602           return 1;
 603         }
 604     }
 605
 606   fatal ("Architecture `%s' unreconized", ap->printable_name);
 607 }
 608
 609 /* Print the registers in a form similar to the E7000 */
 610
 611 static void
 612 sh_show_regs (args, from_tty)
 613      char *args;
 614      int from_tty;
 615 {
 616   int cpu;
 617   if (target_architecture->arch == bfd_arch_sh)
 618     cpu = target_architecture->mach;
 619   else
 620     cpu = 0;
 621   /* start-sanitize-sh4 */
 622   /* FIXME: sh4 has more registers */
 623   if (cpu == bfd_mach_sh4)
 624     cpu = bfd_mach_sh3;
 625   /* end-sanitize-sh4 */
 626
 627   printf_filtered ("PC=%08x SR=%08x PR=%08x MACH=%08x MACHL=%08x\n",
 628                    read_register (PC_REGNUM),
 629                    read_register (SR_REGNUM),
 630                    read_register (PR_REGNUM),
 631                    read_register (MACH_REGNUM),
 632                    read_register (MACL_REGNUM));
 633
 634   printf_filtered ("GBR=%08x VBR=%08x",
 635                    read_register (GBR_REGNUM),
 636                    read_register (VBR_REGNUM));
 637   if (cpu == bfd_mach_sh3 || cpu == bfd_mach_sh3e)
 638     {
 639       printf_filtered (" SSR=%08x SPC=%08x",
 640                        read_register (SSR_REGNUM),
 641                        read_register (SPC_REGNUM));
 642       if (cpu == bfd_mach_sh3e)
 643         {
 644           printf_filtered (" FPUL=%08x FPSCR=%08x",
 645                            read_register (FPUL_REGNUM),
 646                            read_register (FPSCR_REGNUM));
 647         }
 648     }
 649
 650   printf_filtered ("\nR0-R7  %08x %08x %08x %08x %08x %08x %08x %08x\n",
 651                    read_register (0),
 652                    read_register (1),
 653                    read_register (2),
 654                    read_register (3),
 655                    read_register (4),
 656                    read_register (5),
 657                    read_register (6),
 658                    read_register (7));
 659   printf_filtered ("R8-R15 %08x %08x %08x %08x %08x %08x %08x %08x\n",
 660                    read_register (8),
 661                    read_register (9),
 662                    read_register (10),
 663                    read_register (11),
 664                    read_register (12),
 665                    read_register (13),
 666                    read_register (14),
 667                    read_register (15));
 668   if (cpu == bfd_mach_sh3e)
 669     {
 670       printf_filtered ("FP0-FP7  %08x %08x %08x %08x %08x %08x %08x %08x\n",
 671                        read_register (FP0_REGNUM + 0),
 672                        read_register (FP0_REGNUM + 1),
 673                        read_register (FP0_REGNUM + 2),
 674                        read_register (FP0_REGNUM + 3),
 675                        read_register (FP0_REGNUM + 4),
 676                        read_register (FP0_REGNUM + 5),
 677                        read_register (FP0_REGNUM + 6),
 678                        read_register (FP0_REGNUM + 7));
 679       printf_filtered ("FP8-FP15 %08x %08x %08x %08x %08x %08x %08x %08x\n",
 680                        read_register (FP0_REGNUM + 8),
 681                        read_register (FP0_REGNUM + 9),
 682                        read_register (FP0_REGNUM + 10),
 683                        read_register (FP0_REGNUM + 11),
 684                        read_register (FP0_REGNUM + 12),
 685                        read_register (FP0_REGNUM + 13),
 686                        read_register (FP0_REGNUM + 14),
 687                        read_register (FP0_REGNUM + 15));
 688     }
 689 }
 690
 691 /* Function: extract_return_value
 692    Find a function's return value in the appropriate registers (in regbuf),
 693    and copy it into valbuf.  */
 694
 695 void
 696 sh_extract_return_value (type, regbuf, valbuf)
 697      struct type *type;
 698      void *regbuf;
 699      void *valbuf;
 700 {
 701   int len = TYPE_LENGTH(type);
 702
 703   if (len <= 4)
 704     memcpy (valbuf, ((char *) regbuf) + 4 - len, len);
 705   else if (len <= 8)
 706     memcpy (valbuf, ((char *) regbuf) + 8 - len, len);
 707   else
 708     error ("bad size for return value");
 709 }
 710
 711 void
 712 _initialize_sh_tdep ()
 713 {
 714   struct cmd_list_element *c;
 715
 716   tm_print_insn = gdb_print_insn_sh;
 717
 718   target_architecture_hook = sh_target_architecture_hook;
 719
 720   add_com ("regs", class_vars, sh_show_regs, "Print all registers");
 721 }