1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
36 #include "inferior.h" /* for BEFORE_TEXT_END etc. */
37 #include "gdb_string.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
47 #include "solib-svr4.h"
51 /* registers numbers shared with the simulator */
52 #include "gdb/sim-sh.h"
54 void (*sh_show_regs
) (void);
55 CORE_ADDR (*skip_prologue_hard_way
) (CORE_ADDR
);
56 void (*do_pseudo_register
) (int);
58 #define SH_DEFAULT_NUM_REGS 59
60 /* Define other aspects of the stack frame.
61 we keep a copy of the worked out return pc lying around, since it
62 is a useful bit of info */
64 struct frame_extra_info
72 sh_generic_register_name (int reg_nr
)
74 static char *register_names
[] =
76 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
77 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
78 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
80 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
81 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
83 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
84 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
88 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
90 return register_names
[reg_nr
];
94 sh_sh_register_name (int reg_nr
)
96 static char *register_names
[] =
98 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
99 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
100 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
102 "", "", "", "", "", "", "", "",
103 "", "", "", "", "", "", "", "",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
110 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
112 return register_names
[reg_nr
];
116 sh_sh3_register_name (int reg_nr
)
118 static char *register_names
[] =
120 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
127 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
128 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
132 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
134 return register_names
[reg_nr
];
138 sh_sh3e_register_name (int reg_nr
)
140 static char *register_names
[] =
142 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
143 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
144 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
146 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
147 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
149 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
150 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
154 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
156 return register_names
[reg_nr
];
160 sh_sh_dsp_register_name (int reg_nr
)
162 static char *register_names
[] =
164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
168 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
169 "y0", "y1", "", "", "", "", "", "mod",
171 "rs", "re", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
176 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
178 return register_names
[reg_nr
];
182 sh_sh3_dsp_register_name (int reg_nr
)
184 static char *register_names
[] =
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
193 "rs", "re", "", "", "", "", "", "",
194 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
195 "", "", "", "", "", "", "", "",
199 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
201 return register_names
[reg_nr
];
205 sh_sh4_register_name (int reg_nr
)
207 static char *register_names
[] =
209 /* general registers 0-15 */
210 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
211 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
213 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
216 /* floating point registers 25 - 40 */
217 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
218 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
222 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
224 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
225 /* double precision (pseudo) 59 - 66 */
226 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
227 /* vectors (pseudo) 67 - 70 */
228 "fv0", "fv4", "fv8", "fv12",
229 /* FIXME: missing XF 71 - 86 */
230 /* FIXME: missing XD 87 - 94 */
234 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
236 return register_names
[reg_nr
];
240 sh_sh64_register_name (int reg_nr
)
242 static char *register_names
[] =
244 /* SH MEDIA MODE (ISA 32) */
245 /* general registers (64-bit) 0-63 */
246 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
247 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
248 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
249 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
250 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
251 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
252 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
253 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
258 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
261 /* target registers (64-bit) 68-75*/
262 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
264 /* floating point state control register (32-bit) 76 */
267 /* single precision floating point registers (32-bit) 77-140*/
268 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
269 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
270 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
271 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
272 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
273 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
274 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
275 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
277 /* double precision registers (pseudo) 141-172 */
278 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
279 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
280 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
281 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
283 /* floating point pairs (pseudo) 173-204*/
284 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
285 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
286 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
287 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
289 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
290 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
291 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
293 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
294 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
295 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
297 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
299 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
300 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
301 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
302 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
303 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
308 if (reg_nr
>= (sizeof (register_names
) / sizeof (*register_names
)))
310 return register_names
[reg_nr
];
313 #define NUM_PSEUDO_REGS_SH_MEDIA 80
314 #define NUM_PSEUDO_REGS_SH_COMPACT 51
316 static const unsigned char *
317 sh_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
319 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
320 static unsigned char breakpoint
[] = {0xc3, 0xc3};
322 *lenptr
= sizeof (breakpoint
);
326 /* Macros and functions for setting and testing a bit in a minimal
327 symbol that marks it as 32-bit function. The MSB of the minimal
328 symbol's "info" field is used for this purpose. This field is
329 already being used to store the symbol size, so the assumption is
330 that the symbol size cannot exceed 2^31.
332 ELF_MAKE_MSYMBOL_SPECIAL
333 tests whether an ELF symbol is "special", i.e. refers
334 to a 32-bit function, and sets a "special" bit in a
335 minimal symbol to mark it as a 32-bit function
336 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
337 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
338 the "info" field with the "special" bit masked out */
340 #define MSYMBOL_IS_SPECIAL(msym) \
341 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
344 sh64_elf_make_msymbol_special (asymbol
*sym
, struct minimal_symbol
*msym
)
349 if (((elf_symbol_type
*)(sym
))->internal_elf_sym
.st_other
== STO_SH5_ISA32
)
351 MSYMBOL_INFO (msym
) = (char *) (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
352 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
356 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
357 are some macros to test, set, or clear bit 0 of addresses. */
358 #define IS_ISA32_ADDR(addr) ((addr) & 1)
359 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
360 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
363 pc_is_isa32 (bfd_vma memaddr
)
365 struct minimal_symbol
*sym
;
367 /* If bit 0 of the address is set, assume this is a
368 ISA32 (shmedia) address. */
369 if (IS_ISA32_ADDR (memaddr
))
372 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
373 the high bit of the info field. Use this to decide if the function is
375 sym
= lookup_minimal_symbol_by_pc (memaddr
);
377 return MSYMBOL_IS_SPECIAL (sym
);
382 static const unsigned char *
383 sh_sh64_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
385 /* The BRK instruction for shmedia is
386 01101111 11110101 11111111 11110000
387 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
388 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
390 /* The BRK instruction for shcompact is
392 which translates in big endian mode to 0x0, 0x3b
393 and in little endian mode to 0x3b, 0x0*/
395 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
397 if (pc_is_isa32 (*pcptr
))
399 static unsigned char big_breakpoint_media
[] = {0x6f, 0xf5, 0xff, 0xf0};
400 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
401 *lenptr
= sizeof (big_breakpoint_media
);
402 return big_breakpoint_media
;
406 static unsigned char big_breakpoint_compact
[] = {0x0, 0x3b};
407 *lenptr
= sizeof (big_breakpoint_compact
);
408 return big_breakpoint_compact
;
413 if (pc_is_isa32 (*pcptr
))
415 static unsigned char little_breakpoint_media
[] = {0xf0, 0xff, 0xf5, 0x6f};
416 *pcptr
= UNMAKE_ISA32_ADDR (*pcptr
);
417 *lenptr
= sizeof (little_breakpoint_media
);
418 return little_breakpoint_media
;
422 static unsigned char little_breakpoint_compact
[] = {0x3b, 0x0};
423 *lenptr
= sizeof (little_breakpoint_compact
);
424 return little_breakpoint_compact
;
429 /* Prologue looks like
430 [mov.l <regs>,@-r15]...
435 Actually it can be more complicated than this. For instance, with
453 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
454 with l=1 and n = 18 0110101111110001010010100aaa0000 */
455 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
457 /* STS.L PR,@-r0 0100000000100010
458 r0-4-->r0, PR-->(r0) */
459 #define IS_STS_R0(x) ((x) == 0x4022)
461 /* STS PR, Rm 0000mmmm00101010
463 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
465 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
467 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
469 /* MOV.L R14,@(disp,r15) 000111111110dddd
470 R14-->(dispx4+r15) */
471 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
473 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
474 R18-->(dispx8+R14) */
475 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
477 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
478 R18-->(dispx8+R15) */
479 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
481 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
482 R18-->(dispx4+R15) */
483 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
485 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
486 R14-->(dispx8+R15) */
487 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
489 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
490 R14-->(dispx4+R15) */
491 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
493 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
495 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
497 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
499 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
501 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
503 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
505 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
507 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
509 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
511 /* MOV #imm, R0 1110 0000 ssss ssss
513 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
515 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
516 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
518 /* ADD r15,r0 0011 0000 1111 1100
520 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
522 /* MOV.L R14 @-R0 0010 0000 1110 0110
523 R14-->(R0-4), R0-4-->R0 */
524 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
526 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
527 where Rm is one of r2-r9 which are the argument registers. */
528 /* FIXME: Recognize the float and double register moves too! */
529 #define IS_MEDIA_IND_ARG_MOV(x) \
530 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
532 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
533 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
534 where Rm is one of r2-r9 which are the argument registers. */
535 #define IS_MEDIA_ARG_MOV(x) \
536 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
537 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
539 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
540 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
541 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
542 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
543 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
544 #define IS_MEDIA_MOV_TO_R14(x) \
545 ((((x) & 0xfffffc0f) == 0xa0e00000) \
546 || (((x) & 0xfffffc0f) == 0xa4e00000) \
547 || (((x) & 0xfffffc0f) == 0xa8e00000) \
548 || (((x) & 0xfffffc0f) == 0xb4e00000) \
549 || (((x) & 0xfffffc0f) == 0xbce00000))
551 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
553 #define IS_COMPACT_IND_ARG_MOV(x) \
554 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
556 /* compact direct arg move!
557 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
558 #define IS_COMPACT_ARG_MOV(x) \
559 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
561 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
562 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
563 #define IS_COMPACT_MOV_TO_R14(x) \
564 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
566 #define IS_JSR_R0(x) ((x) == 0x400b)
567 #define IS_NOP(x) ((x) == 0x0009)
570 /* STS.L PR,@-r15 0100111100100010
571 r15-4-->r15, PR-->(r15) */
572 #define IS_STS(x) ((x) == 0x4f22)
574 /* MOV.L Rm,@-r15 00101111mmmm0110
575 r15-4-->r15, Rm-->(R15) */
576 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
578 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
580 /* MOV r15,r14 0110111011110011
582 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
584 /* ADD #imm,r15 01111111iiiiiiii
586 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
588 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
589 #define IS_SHLL_R3(x) ((x) == 0x4300)
591 /* ADD r3,r15 0011111100111100
593 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
595 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
596 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
597 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
598 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
600 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
601 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
602 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
603 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
604 #define IS_ARG_MOV(x) \
605 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
606 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
607 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
609 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
610 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
611 #define IS_MOV_TO_R14(x) \
612 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
614 #define FPSCR_SZ (1 << 20)
616 /* Skip any prologue before the guts of a function */
618 /* Skip the prologue using the debug information. If this fails we'll
619 fall back on the 'guess' method below. */
621 after_prologue (CORE_ADDR pc
)
623 struct symtab_and_line sal
;
624 CORE_ADDR func_addr
, func_end
;
626 /* If we can not find the symbol in the partial symbol table, then
627 there is no hope we can determine the function's start address
629 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
632 /* Get the line associated with FUNC_ADDR. */
633 sal
= find_pc_line (func_addr
, 0);
635 /* There are only two cases to consider. First, the end of the source line
636 is within the function bounds. In that case we return the end of the
637 source line. Second is the end of the source line extends beyond the
638 bounds of the current function. We need to use the slow code to
639 examine instructions in that case. */
640 if (sal
.end
< func_end
)
646 /* Here we look at each instruction in the function, and try to guess
647 where the prologue ends. Unfortunately this is not always
650 sh_skip_prologue_hard_way (CORE_ADDR start_pc
)
658 for (here
= start_pc
, end
= start_pc
+ (2 * 28); here
< end
;)
660 int w
= read_memory_integer (here
, 2);
662 if (IS_FMOV (w
) || IS_PUSH (w
) || IS_STS (w
) || IS_MOV_R3 (w
)
663 || IS_ADD_R3SP (w
) || IS_ADD_SP (w
) || IS_SHLL_R3 (w
)
664 || IS_ARG_MOV (w
) || IS_MOV_TO_R14 (w
))
668 else if (IS_MOV_SP_FP (w
))
674 /* Don't bail out yet, if we are before the copy of sp. */
683 look_for_args_moves (CORE_ADDR start_pc
, int media_mode
)
687 int insn_size
= (media_mode
? 4 : 2);
689 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
693 w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
695 if (IS_MEDIA_IND_ARG_MOV (w
))
697 /* This must be followed by a store to r14, so the argument
698 is where the debug info says it is. This can happen after
699 the SP has been saved, unfortunately. */
701 int next_insn
= read_memory_integer (UNMAKE_ISA32_ADDR (here
),
704 if (IS_MEDIA_MOV_TO_R14 (next_insn
))
707 else if (IS_MEDIA_ARG_MOV (w
))
709 /* These instructions store directly the argument in r14. */
717 w
= read_memory_integer (here
, insn_size
);
720 if (IS_COMPACT_IND_ARG_MOV (w
))
722 /* This must be followed by a store to r14, so the argument
723 is where the debug info says it is. This can happen after
724 the SP has been saved, unfortunately. */
726 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
728 if (IS_COMPACT_MOV_TO_R14 (next_insn
))
731 else if (IS_COMPACT_ARG_MOV (w
))
733 /* These instructions store directly the argument in r14. */
736 else if (IS_MOVL_R0 (w
))
738 /* There is a function that gcc calls to get the arguments
739 passed correctly to the function. Only after this
740 function call the arguments will be found at the place
741 where they are supposed to be. This happens in case the
742 argument has to be stored into a 64-bit register (for
743 instance doubles, long longs). SHcompact doesn't have
744 access to the full 64-bits, so we store the register in
745 stack slot and store the address of the stack slot in
746 the register, then do a call through a wrapper that
747 loads the memory value into the register. A SHcompact
748 callee calls an argument decoder
749 (GCC_shcompact_incoming_args) that stores the 64-bit
750 value in a stack slot and stores the address of the
751 stack slot in the register. GCC thinks the argument is
752 just passed by transparent reference, but this is only
753 true after the argument decoder is called. Such a call
754 needs to be considered part of the prologue. */
756 /* This must be followed by a JSR @r0 instruction and by
757 a NOP instruction. After these, the prologue is over! */
759 int next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
761 if (IS_JSR_R0 (next_insn
))
763 next_insn
= 0xffff & read_memory_integer (here
, insn_size
);
766 if (IS_NOP (next_insn
))
779 sh64_skip_prologue_hard_way (CORE_ADDR start_pc
)
789 if (pc_is_isa32 (start_pc
) == 0)
795 for (here
= start_pc
, end
= start_pc
+ (insn_size
* 28); here
< end
;)
800 int w
= read_memory_integer (UNMAKE_ISA32_ADDR (here
), insn_size
);
802 if (IS_STQ_R18_R14 (w
) || IS_STQ_R18_R15 (w
) || IS_STQ_R14_R15 (w
)
803 || IS_STL_R14_R15 (w
) || IS_STL_R18_R15 (w
)
804 || IS_ADDIL_SP_MEDIA (w
) || IS_ADDI_SP_MEDIA (w
) || IS_PTABSL_R18 (w
))
808 else if (IS_MOV_SP_FP (w
) || IS_MOV_SP_FP_MEDIA(w
))
816 /* Don't bail out yet, we may have arguments stored in
817 registers here, according to the debug info, so that
818 gdb can print the frames correctly. */
819 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
825 int w
= 0xffff & read_memory_integer (here
, insn_size
);
828 if (IS_STS_R0 (w
) || IS_STS_PR (w
)
829 || IS_MOV_TO_R15 (w
) || IS_MOV_R14 (w
)
830 || IS_MOV_R0 (w
) || IS_ADD_SP_R0 (w
) || IS_MOV_R14_R0 (w
))
834 else if (IS_MOV_SP_FP (w
))
842 /* Don't bail out yet, we may have arguments stored in
843 registers here, according to the debug info, so that
844 gdb can print the frames correctly. */
845 start_pc
= look_for_args_moves (here
- insn_size
, media_mode
);
855 sh_skip_prologue (CORE_ADDR pc
)
857 CORE_ADDR post_prologue_pc
;
859 /* See if we can determine the end of the prologue via the symbol table.
860 If so, then return either PC, or the PC after the prologue, whichever
862 post_prologue_pc
= after_prologue (pc
);
864 /* If after_prologue returned a useful address, then use it. Else
865 fall back on the instruction skipping code. */
866 if (post_prologue_pc
!= 0)
867 return max (pc
, post_prologue_pc
);
869 return (skip_prologue_hard_way (pc
));
872 /* Immediately after a function call, return the saved pc.
873 Can't always go through the frames for this because on some machines
874 the new frame is not set up until the new function executes
877 The return address is the value saved in the PR register + 4 */
879 sh_saved_pc_after_call (struct frame_info
*frame
)
881 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
)));
884 /* Should call_function allocate stack space for a struct return? */
886 sh_use_struct_convention (int gcc_p
, struct type
*type
)
889 return (TYPE_LENGTH (type
) > 1);
891 int len
= TYPE_LENGTH (type
);
892 int nelem
= TYPE_NFIELDS (type
);
893 return ((len
!= 1 && len
!= 2 && len
!= 4 && len
!= 8) || nelem
!= 1) &&
894 (len
!= 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type
, 0)) != 4);
899 sh64_use_struct_convention (int gcc_p
, struct type
*type
)
901 return (TYPE_LENGTH (type
) > 8);
904 /* Store the address of the place in which to copy the structure the
905 subroutine will return. This is called from call_function.
907 We store structs through a pointer passed in R2 */
909 sh_store_struct_return (CORE_ADDR addr
, CORE_ADDR sp
)
911 write_register (STRUCT_RETURN_REGNUM
, (addr
));
914 /* Disassemble an instruction. */
916 gdb_print_insn_sh (bfd_vma memaddr
, disassemble_info
*info
)
918 info
->endian
= TARGET_BYTE_ORDER
;
919 return print_insn_sh (memaddr
, info
);
922 /* Given a GDB frame, determine the address of the calling function's
923 frame. This will be used to create a new GDB frame struct, and
924 then INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC will be
925 called for the new frame.
927 For us, the frame address is its stack pointer value, so we look up
928 the function prologue to determine the caller's sp value, and return it. */
930 sh_frame_chain (struct frame_info
*frame
)
932 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
),
933 get_frame_base (frame
),
934 get_frame_base (frame
)))
935 return get_frame_base (frame
); /* dummy frame same as caller's frame */
936 if (get_frame_pc (frame
) && !inside_entry_file (get_frame_pc (frame
)))
937 return read_memory_integer (get_frame_base (frame
) + frame
->extra_info
->f_offset
, 4);
942 /* Given a register number RN as it appears in an assembly
943 instruction, find the corresponding register number in the GDB
946 translate_insn_rn (int rn
, int media_mode
)
948 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
950 /* FIXME: this assumes that the number rn is for a not pseudo
956 /* These registers don't have a corresponding compact one. */
957 /* FIXME: This is probably not enough. */
959 if ((rn
>= 16 && rn
<= 63) || (rn
>= 93 && rn
<= 140))
962 if (rn
>= 0 && rn
<= tdep
->R0_C_REGNUM
)
963 return tdep
->R0_C_REGNUM
+ rn
;
970 sh64_frame_chain (struct frame_info
*frame
)
972 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
),
973 get_frame_base (frame
),
974 get_frame_base (frame
)))
975 return get_frame_base (frame
); /* dummy frame same as caller's frame */
976 if (get_frame_pc (frame
) && !inside_entry_file (get_frame_pc (frame
)))
978 int media_mode
= pc_is_isa32 (get_frame_pc (frame
));
980 if (gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
983 size
= REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM
, media_mode
));
984 return read_memory_integer (get_frame_base (frame
) + frame
->extra_info
->f_offset
, size
);
990 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
991 we might want to do here is to check REGNUM against the clobber mask, and
992 somehow flag it as invalid if it isn't saved on the stack somewhere. This
993 would provide a graceful failure mode when trying to get the value of
994 caller-saves registers for an inner frame. */
996 sh_find_callers_reg (struct frame_info
*fi
, int regnum
)
998 for (; fi
; fi
= get_next_frame (fi
))
999 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi
), get_frame_base (fi
),
1000 get_frame_base (fi
)))
1001 /* When the caller requests PR from the dummy frame, we return PC because
1002 that's where the previous routine appears to have done a call from. */
1003 return deprecated_read_register_dummy (get_frame_pc (fi
),
1004 get_frame_base (fi
), regnum
);
1007 FRAME_INIT_SAVED_REGS (fi
);
1008 if (!get_frame_pc (fi
))
1010 if (get_frame_saved_regs (fi
)[regnum
] != 0)
1011 return read_memory_integer (get_frame_saved_regs (fi
)[regnum
],
1012 REGISTER_RAW_SIZE (regnum
));
1014 return read_register (regnum
);
1018 sh64_get_saved_pr (struct frame_info
*fi
, int pr_regnum
)
1022 for (; fi
; fi
= get_next_frame (fi
))
1023 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi
), get_frame_base (fi
),
1024 get_frame_base (fi
)))
1025 /* When the caller requests PR from the dummy frame, we return PC because
1026 that's where the previous routine appears to have done a call from. */
1027 return deprecated_read_register_dummy (get_frame_pc (fi
),
1028 get_frame_base (fi
), pr_regnum
);
1031 FRAME_INIT_SAVED_REGS (fi
);
1032 if (!get_frame_pc (fi
))
1035 media_mode
= pc_is_isa32 (get_frame_pc (fi
));
1037 if (get_frame_saved_regs (fi
)[pr_regnum
] != 0)
1039 int gdb_reg_num
= translate_insn_rn (pr_regnum
, media_mode
);
1040 int size
= ((gdbarch_tdep (current_gdbarch
)->sh_abi
== SH_ABI_32
)
1042 : REGISTER_RAW_SIZE (gdb_reg_num
));
1043 return read_memory_integer (get_frame_saved_regs (fi
)[pr_regnum
], size
);
1046 return read_register (pr_regnum
);
1049 /* Put here the code to store, into a struct frame_saved_regs, the
1050 addresses of the saved registers of frame described by FRAME_INFO.
1051 This includes special registers such as pc and fp saved in special
1052 ways in the stack frame. sp is even more special: the address we
1053 return for it IS the sp for the next frame. */
1055 sh_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1057 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof(int));
1065 char *dummy_regs
= deprecated_generic_find_dummy_frame (get_frame_pc (fi
),
1066 get_frame_base (fi
));
1068 if (get_frame_saved_regs (fi
) == NULL
)
1069 frame_saved_regs_zalloc (fi
);
1071 memset (get_frame_saved_regs (fi
), 0, SIZEOF_FRAME_SAVED_REGS
);
1075 /* DANGER! This is ONLY going to work if the char buffer format of
1076 the saved registers is byte-for-byte identical to the
1077 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1078 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1082 fi
->extra_info
->leaf_function
= 1;
1083 fi
->extra_info
->f_offset
= 0;
1085 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1090 /* Loop around examining the prologue insns until we find something
1091 that does not appear to be part of the prologue. But give up
1092 after 20 of them, since we're getting silly then. */
1094 pc
= get_pc_function_start (get_frame_pc (fi
));
1097 deprecated_update_frame_pc_hack (fi
, 0);
1101 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1103 insn
= read_memory_integer (pc
, 2);
1104 /* See where the registers will be saved to */
1107 rn
= GET_PUSHED_REG (insn
);
1111 else if (IS_STS (insn
))
1113 where
[gdbarch_tdep (current_gdbarch
)->PR_REGNUM
] = depth
;
1114 /* If we're storing the pr then this isn't a leaf */
1115 fi
->extra_info
->leaf_function
= 0;
1118 else if (IS_MOV_R3 (insn
))
1120 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1122 else if (IS_SHLL_R3 (insn
))
1126 else if (IS_ADD_R3SP (insn
))
1130 else if (IS_ADD_SP (insn
))
1132 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1134 else if (IS_MOV_SP_FP (insn
))
1136 #if 0 /* This used to just stop when it found an instruction that
1137 was not considered part of the prologue. Now, we just
1138 keep going looking for likely instructions. */
1144 /* Now we know how deep things are, we can work out their addresses */
1146 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1150 if (rn
== FP_REGNUM
)
1153 get_frame_saved_regs (fi
)[rn
] = get_frame_base (fi
) - where
[rn
] + depth
- 4;
1157 get_frame_saved_regs (fi
)[rn
] = 0;
1163 get_frame_saved_regs (fi
)[SP_REGNUM
] = read_memory_integer (get_frame_saved_regs (fi
)[FP_REGNUM
], 4);
1167 get_frame_saved_regs (fi
)[SP_REGNUM
] = get_frame_base (fi
) - 4;
1170 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1171 /* Work out the return pc - either from the saved pr or the pr
1175 /* For vectors of 4 floating point registers. */
1177 fv_reg_base_num (int fv_regnum
)
1181 fp_regnum
= FP0_REGNUM
+
1182 (fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
) * 4;
1186 /* For double precision floating point registers, i.e 2 fp regs.*/
1188 dr_reg_base_num (int dr_regnum
)
1192 fp_regnum
= FP0_REGNUM
+
1193 (dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
) * 2;
1197 /* For pairs of floating point registers */
1199 fpp_reg_base_num (int fpp_regnum
)
1203 fp_regnum
= FP0_REGNUM
+
1204 (fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
) * 2;
1209 is_media_pseudo (int rn
)
1211 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1213 return (rn
>= tdep
->DR0_REGNUM
1214 && rn
<= tdep
->FV_LAST_REGNUM
);
1218 sh64_get_gdb_regnum (int gcc_regnum
, CORE_ADDR pc
)
1220 return translate_insn_rn (gcc_regnum
, pc_is_isa32 (pc
));
1224 sh64_media_reg_base_num (int reg_nr
)
1226 int base_regnum
= -1;
1227 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1229 if (reg_nr
>= tdep
->DR0_REGNUM
1230 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
1231 base_regnum
= dr_reg_base_num (reg_nr
);
1233 else if (reg_nr
>= tdep
->FPP0_REGNUM
1234 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
1235 base_regnum
= fpp_reg_base_num (reg_nr
);
1237 else if (reg_nr
>= tdep
->FV0_REGNUM
1238 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
1239 base_regnum
= fv_reg_base_num (reg_nr
);
1246 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1247 GDB_REGNUM BASE_REGNUM
1307 sh64_compact_reg_base_num (int reg_nr
)
1309 int base_regnum
= -1;
1310 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1312 /* general register N maps to general register N */
1313 if (reg_nr
>= tdep
->R0_C_REGNUM
1314 && reg_nr
<= tdep
->R_LAST_C_REGNUM
)
1315 base_regnum
= reg_nr
- tdep
->R0_C_REGNUM
;
1317 /* floating point register N maps to floating point register N */
1318 else if (reg_nr
>= tdep
->FP0_C_REGNUM
1319 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
1320 base_regnum
= reg_nr
- tdep
->FP0_C_REGNUM
+ FP0_REGNUM
;
1322 /* double prec register N maps to base regnum for double prec register N */
1323 else if (reg_nr
>= tdep
->DR0_C_REGNUM
1324 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
1325 base_regnum
= dr_reg_base_num (tdep
->DR0_REGNUM
1326 + reg_nr
- tdep
->DR0_C_REGNUM
);
1328 /* vector N maps to base regnum for vector register N */
1329 else if (reg_nr
>= tdep
->FV0_C_REGNUM
1330 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
1331 base_regnum
= fv_reg_base_num (tdep
->FV0_REGNUM
1332 + reg_nr
- tdep
->FV0_C_REGNUM
);
1334 else if (reg_nr
== tdep
->PC_C_REGNUM
)
1335 base_regnum
= PC_REGNUM
;
1337 else if (reg_nr
== tdep
->GBR_C_REGNUM
)
1340 else if (reg_nr
== tdep
->MACH_C_REGNUM
1341 || reg_nr
== tdep
->MACL_C_REGNUM
)
1344 else if (reg_nr
== tdep
->PR_C_REGNUM
)
1347 else if (reg_nr
== tdep
->T_C_REGNUM
)
1350 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
1351 base_regnum
= tdep
->FPSCR_REGNUM
; /*???? this register is a mess. */
1353 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
1354 base_regnum
= FP0_REGNUM
+ 32;
1359 /* Given a register number RN (according to the gdb scheme) , return
1360 its corresponding architectural register. In media mode, only a
1361 subset of the registers is pseudo registers. For compact mode, all
1362 the registers are pseudo. */
1364 translate_rn_to_arch_reg_num (int rn
, int media_mode
)
1369 if (!is_media_pseudo (rn
))
1372 return sh64_media_reg_base_num (rn
);
1375 /* All compact registers are pseudo. */
1376 return sh64_compact_reg_base_num (rn
);
1380 sign_extend (int value
, int bits
)
1382 value
= value
& ((1 << bits
) - 1);
1383 return (value
& (1 << (bits
- 1))
1384 ? value
| (~((1 << bits
) - 1))
1389 sh64_nofp_frame_init_saved_regs (struct frame_info
*fi
)
1391 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof (int));
1403 int gdb_register_number
;
1404 int register_number
;
1405 char *dummy_regs
= deprecated_generic_find_dummy_frame (get_frame_pc (fi
), get_frame_base (fi
));
1406 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1408 if (get_frame_saved_regs (fi
) == NULL
)
1409 frame_saved_regs_zalloc (fi
);
1411 memset (get_frame_saved_regs (fi
), 0, SIZEOF_FRAME_SAVED_REGS
);
1415 /* DANGER! This is ONLY going to work if the char buffer format of
1416 the saved registers is byte-for-byte identical to the
1417 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1418 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1422 fi
->extra_info
->leaf_function
= 1;
1423 fi
->extra_info
->f_offset
= 0;
1425 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1430 /* Loop around examining the prologue insns until we find something
1431 that does not appear to be part of the prologue. But give up
1432 after 20 of them, since we're getting silly then. */
1434 pc
= get_pc_function_start (get_frame_pc (fi
));
1437 deprecated_update_frame_pc_hack (fi
, 0);
1441 if (pc_is_isa32 (pc
))
1452 /* The frame pointer register is general register 14 in shmedia and
1453 shcompact modes. In sh compact it is a pseudo register. Same goes
1454 for the stack pointer register, which is register 15. */
1455 fp_regnum
= translate_insn_rn (FP_REGNUM
, media_mode
);
1456 sp_regnum
= translate_insn_rn (SP_REGNUM
, media_mode
);
1458 for (opc
= pc
+ (insn_size
* 28); pc
< opc
; pc
+= insn_size
)
1460 insn
= read_memory_integer (media_mode
? UNMAKE_ISA32_ADDR (pc
) : pc
,
1463 if (media_mode
== 0)
1465 if (IS_STS_PR (insn
))
1467 int next_insn
= read_memory_integer (pc
+ insn_size
, insn_size
);
1468 if (IS_MOV_TO_R15 (next_insn
))
1470 int reg_nr
= tdep
->PR_C_REGNUM
;
1472 where
[reg_nr
] = depth
- ((((next_insn
& 0xf) ^ 0x8) - 0x8) << 2);
1473 fi
->extra_info
->leaf_function
= 0;
1477 else if (IS_MOV_R14 (insn
))
1479 where
[fp_regnum
] = depth
- ((((insn
& 0xf) ^ 0x8) - 0x8) << 2);
1482 else if (IS_MOV_R0 (insn
))
1484 /* Put in R0 the offset from SP at which to store some
1485 registers. We are interested in this value, because it
1486 will tell us where the given registers are stored within
1488 r0_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1490 else if (IS_ADD_SP_R0 (insn
))
1492 /* This instruction still prepares r0, but we don't care.
1493 We already have the offset in r0_val. */
1495 else if (IS_STS_R0 (insn
))
1497 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1498 int reg_nr
= tdep
->PR_C_REGNUM
;
1499 where
[reg_nr
] = depth
- (r0_val
- 4);
1501 fi
->extra_info
->leaf_function
= 0;
1503 else if (IS_MOV_R14_R0 (insn
))
1505 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1506 where
[fp_regnum
] = depth
- (r0_val
- 4);
1510 else if (IS_ADD_SP (insn
))
1512 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1514 else if (IS_MOV_SP_FP (insn
))
1519 if (IS_ADDIL_SP_MEDIA (insn
)
1520 || IS_ADDI_SP_MEDIA (insn
))
1522 depth
-= sign_extend ((((insn
& 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1525 else if (IS_STQ_R18_R15 (insn
))
1527 where
[tdep
->PR_REGNUM
] =
1528 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1529 fi
->extra_info
->leaf_function
= 0;
1532 else if (IS_STL_R18_R15 (insn
))
1534 where
[tdep
->PR_REGNUM
] =
1535 depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1536 fi
->extra_info
->leaf_function
= 0;
1539 else if (IS_STQ_R14_R15 (insn
))
1541 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 3);
1544 else if (IS_STL_R14_R15 (insn
))
1546 where
[fp_regnum
] = depth
- (sign_extend ((insn
& 0xffc00) >> 10, 9) << 2);
1549 else if (IS_MOV_SP_FP_MEDIA (insn
))
1554 /* Now we know how deep things are, we can work out their addresses. */
1555 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1557 register_number
= translate_rn_to_arch_reg_num (rn
, media_mode
);
1561 if (rn
== fp_regnum
)
1564 /* Watch out! saved_regs is only for the real registers, and
1565 doesn't include space for the pseudo registers. */
1566 get_frame_saved_regs (fi
)[register_number
]= get_frame_base (fi
) - where
[rn
] + depth
;
1570 get_frame_saved_regs (fi
)[register_number
] = 0;
1575 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1576 shcompact 15 is the arch register corresponding to the pseudo
1577 register r15 which still is the SP register. */
1578 /* The place on the stack where fp is stored contains the sp of
1580 /* Again, saved_registers contains only space for the real registers,
1581 so we store in FP_REGNUM position. */
1583 if (tdep
->sh_abi
== SH_ABI_32
)
1586 size
= REGISTER_RAW_SIZE (fp_regnum
);
1587 get_frame_saved_regs (fi
)[sp_regnum
] = read_memory_integer (get_frame_saved_regs (fi
)[fp_regnum
], size
);
1590 get_frame_saved_regs (fi
)[sp_regnum
] = get_frame_base (fi
);
1592 fi
->extra_info
->f_offset
= depth
- where
[fp_regnum
];
1596 sh_fp_frame_init_saved_regs (struct frame_info
*fi
)
1598 int *where
= (int *) alloca ((NUM_REGS
+ NUM_PSEUDO_REGS
) * sizeof (int));
1606 char *dummy_regs
= deprecated_generic_find_dummy_frame (get_frame_pc (fi
), get_frame_base (fi
));
1607 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1609 if (get_frame_saved_regs (fi
) == NULL
)
1610 frame_saved_regs_zalloc (fi
);
1612 memset (get_frame_saved_regs (fi
), 0, SIZEOF_FRAME_SAVED_REGS
);
1616 /* DANGER! This is ONLY going to work if the char buffer format of
1617 the saved registers is byte-for-byte identical to the
1618 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1619 memcpy (fi
->saved_regs
, dummy_regs
, sizeof (fi
->saved_regs
));
1623 fi
->extra_info
->leaf_function
= 1;
1624 fi
->extra_info
->f_offset
= 0;
1626 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1631 /* Loop around examining the prologue insns until we find something
1632 that does not appear to be part of the prologue. But give up
1633 after 20 of them, since we're getting silly then. */
1635 pc
= get_pc_function_start (get_frame_pc (fi
));
1638 deprecated_update_frame_pc_hack (fi
, 0);
1642 for (opc
= pc
+ (2 * 28); pc
< opc
; pc
+= 2)
1644 insn
= read_memory_integer (pc
, 2);
1645 /* See where the registers will be saved to */
1648 rn
= GET_PUSHED_REG (insn
);
1652 else if (IS_STS (insn
))
1654 where
[tdep
->PR_REGNUM
] = depth
;
1655 /* If we're storing the pr then this isn't a leaf */
1656 fi
->extra_info
->leaf_function
= 0;
1659 else if (IS_MOV_R3 (insn
))
1661 r3_val
= ((insn
& 0xff) ^ 0x80) - 0x80;
1663 else if (IS_SHLL_R3 (insn
))
1667 else if (IS_ADD_R3SP (insn
))
1671 else if (IS_ADD_SP (insn
))
1673 depth
-= ((insn
& 0xff) ^ 0x80) - 0x80;
1675 else if (IS_FMOV (insn
))
1677 if (read_register (tdep
->FPSCR_REGNUM
) & FPSCR_SZ
)
1686 else if (IS_MOV_SP_FP (insn
))
1688 #if 0 /* This used to just stop when it found an instruction that
1689 was not considered part of the prologue. Now, we just
1690 keep going looking for likely instructions. */
1696 /* Now we know how deep things are, we can work out their addresses */
1698 for (rn
= 0; rn
< NUM_REGS
+ NUM_PSEUDO_REGS
; rn
++)
1702 if (rn
== FP_REGNUM
)
1705 get_frame_saved_regs (fi
)[rn
] = get_frame_base (fi
) - where
[rn
] + depth
- 4;
1709 get_frame_saved_regs (fi
)[rn
] = 0;
1715 get_frame_saved_regs (fi
)[SP_REGNUM
] =
1716 read_memory_integer (get_frame_saved_regs (fi
)[FP_REGNUM
], 4);
1720 get_frame_saved_regs (fi
)[SP_REGNUM
] = get_frame_base (fi
) - 4;
1723 fi
->extra_info
->f_offset
= depth
- where
[FP_REGNUM
] - 4;
1724 /* Work out the return pc - either from the saved pr or the pr
1728 /* Initialize the extra info saved in a FRAME */
1730 sh_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1733 frame_extra_info_zalloc (fi
, sizeof (struct frame_extra_info
));
1735 if (get_next_frame (fi
))
1736 deprecated_update_frame_pc_hack (fi
, FRAME_SAVED_PC (get_next_frame (fi
)));
1738 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi
), get_frame_base (fi
),
1739 get_frame_base (fi
)))
1741 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1742 by assuming it's always FP. */
1743 deprecated_update_frame_base_hack (fi
, deprecated_read_register_dummy (get_frame_pc (fi
), get_frame_base (fi
),
1745 fi
->extra_info
->return_pc
= deprecated_read_register_dummy (get_frame_pc (fi
),
1746 get_frame_base (fi
),
1748 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1749 fi
->extra_info
->leaf_function
= 0;
1754 FRAME_INIT_SAVED_REGS (fi
);
1755 fi
->extra_info
->return_pc
=
1756 sh_find_callers_reg (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1761 sh64_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
1763 int media_mode
= pc_is_isa32 (get_frame_pc (fi
));
1765 frame_extra_info_zalloc (fi
, sizeof (struct frame_extra_info
));
1767 if (get_next_frame (fi
))
1768 deprecated_update_frame_pc_hack (fi
, FRAME_SAVED_PC (get_next_frame (fi
)));
1770 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi
), get_frame_base (fi
),
1771 get_frame_base (fi
)))
1773 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1774 by assuming it's always FP. */
1775 deprecated_update_frame_base_hack (fi
, deprecated_read_register_dummy (get_frame_pc (fi
), get_frame_base (fi
), SP_REGNUM
));
1776 fi
->extra_info
->return_pc
=
1777 deprecated_read_register_dummy (get_frame_pc (fi
),
1778 get_frame_base (fi
), PC_REGNUM
);
1779 fi
->extra_info
->f_offset
= -(CALL_DUMMY_LENGTH
+ 4);
1780 fi
->extra_info
->leaf_function
= 0;
1785 FRAME_INIT_SAVED_REGS (fi
);
1786 fi
->extra_info
->return_pc
=
1787 sh64_get_saved_pr (fi
, gdbarch_tdep (current_gdbarch
)->PR_REGNUM
);
1792 sh64_get_saved_register (char *raw_buffer
, int *optimized
, CORE_ADDR
*addrp
,
1793 struct frame_info
*frame
, int regnum
,
1794 enum lval_type
*lval
)
1797 int live_regnum
= regnum
;
1798 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1800 if (!target_has_registers
)
1801 error ("No registers.");
1803 /* Normal systems don't optimize out things with register numbers. */
1804 if (optimized
!= NULL
)
1807 if (addrp
) /* default assumption: not found in memory */
1811 memset (raw_buffer
, 0, sizeof (raw_buffer
));
1813 /* We must do this here, before the following while loop changes
1814 frame, and makes it NULL. If this is a media register number,
1815 but we are in compact mode, it will become the corresponding
1816 compact pseudo register. If there is no corresponding compact
1817 pseudo-register what do we do?*/
1818 media_mode
= pc_is_isa32 (get_frame_pc (frame
));
1819 live_regnum
= translate_insn_rn (regnum
, media_mode
);
1821 /* Note: since the current frame's registers could only have been
1822 saved by frames INTERIOR TO the current frame, we skip examining
1823 the current frame itself: otherwise, we would be getting the
1824 previous frame's registers which were saved by the current frame. */
1826 while (frame
&& ((frame
= get_next_frame (frame
)) != NULL
))
1828 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
),
1829 get_frame_base (frame
),
1830 get_frame_base (frame
)))
1832 if (lval
) /* found it in a CALL_DUMMY frame */
1836 (deprecated_generic_find_dummy_frame (get_frame_pc (frame
), get_frame_base (frame
))
1837 + REGISTER_BYTE (regnum
)),
1838 REGISTER_RAW_SIZE (regnum
));
1842 FRAME_INIT_SAVED_REGS (frame
);
1843 if (get_frame_saved_regs (frame
) != NULL
1844 && get_frame_saved_regs (frame
)[regnum
] != 0)
1846 if (lval
) /* found it saved on the stack */
1847 *lval
= lval_memory
;
1848 if (regnum
== SP_REGNUM
)
1850 if (raw_buffer
) /* SP register treated specially */
1851 store_address (raw_buffer
, REGISTER_RAW_SIZE (regnum
),
1852 get_frame_saved_regs (frame
)[regnum
]);
1855 { /* any other register */
1858 *addrp
= get_frame_saved_regs (frame
)[regnum
];
1862 if (tdep
->sh_abi
== SH_ABI_32
1863 && (live_regnum
== FP_REGNUM
1864 || live_regnum
== tdep
->PR_REGNUM
))
1867 size
= REGISTER_RAW_SIZE (live_regnum
);
1868 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
1869 read_memory (get_frame_saved_regs (frame
)[regnum
], raw_buffer
, size
);
1871 read_memory (get_frame_saved_regs (frame
)[regnum
],
1873 + REGISTER_RAW_SIZE (live_regnum
)
1882 /* If we get thru the loop to this point, it means the register was
1883 not saved in any frame. Return the actual live-register value. */
1885 if (lval
) /* found it in a live register */
1886 *lval
= lval_register
;
1888 *addrp
= REGISTER_BYTE (live_regnum
);
1890 deprecated_read_register_gen (live_regnum
, raw_buffer
);
1893 /* Extract from an array REGBUF containing the (raw) register state
1894 the address in which a function should return its structure value,
1895 as a CORE_ADDR (or an expression that can be used as one). */
1897 sh_extract_struct_value_address (char *regbuf
)
1899 return (extract_address ((regbuf
), REGISTER_RAW_SIZE (0)));
1903 sh64_extract_struct_value_address (char *regbuf
)
1905 return (extract_address ((regbuf
+ REGISTER_BYTE (STRUCT_RETURN_REGNUM
)),
1906 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM
)));
1910 sh_frame_saved_pc (struct frame_info
*frame
)
1912 return ((frame
)->extra_info
->return_pc
);
1915 /* Discard from the stack the innermost frame,
1916 restoring all saved registers. */
1920 register struct frame_info
*frame
= get_current_frame ();
1921 register CORE_ADDR fp
;
1922 register int regnum
;
1924 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
),
1925 get_frame_base (frame
),
1926 get_frame_base (frame
)))
1927 generic_pop_dummy_frame ();
1930 fp
= get_frame_base (frame
);
1931 FRAME_INIT_SAVED_REGS (frame
);
1933 /* Copy regs from where they were saved in the frame */
1934 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1935 if (get_frame_saved_regs (frame
)[regnum
])
1936 write_register (regnum
,
1937 read_memory_integer (get_frame_saved_regs (frame
)[regnum
], 4));
1939 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1940 write_register (SP_REGNUM
, fp
+ 4);
1942 flush_cached_frames ();
1945 /* Used in the 'return' command. */
1947 sh64_pop_frame (void)
1949 register struct frame_info
*frame
= get_current_frame ();
1950 register CORE_ADDR fp
;
1951 register int regnum
;
1952 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1954 int media_mode
= pc_is_isa32 (get_frame_pc (frame
));
1956 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame
),
1957 get_frame_base (frame
),
1958 get_frame_base (frame
)))
1959 generic_pop_dummy_frame ();
1962 fp
= get_frame_base (frame
);
1963 FRAME_INIT_SAVED_REGS (frame
);
1965 /* Copy regs from where they were saved in the frame */
1966 for (regnum
= 0; regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
; regnum
++)
1967 if (get_frame_saved_regs (frame
)[regnum
])
1970 if (tdep
->sh_abi
== SH_ABI_32
1971 && (regnum
== FP_REGNUM
1972 || regnum
== tdep
->PR_REGNUM
))
1975 size
= REGISTER_RAW_SIZE (translate_insn_rn (regnum
,
1977 write_register (regnum
,
1978 read_memory_integer (get_frame_saved_regs (frame
)[regnum
],
1982 write_register (PC_REGNUM
, frame
->extra_info
->return_pc
);
1983 write_register (SP_REGNUM
, fp
+ 8);
1985 flush_cached_frames ();
1988 /* Function: push_arguments
1989 Setup the function arguments for calling a function in the inferior.
1991 On the Hitachi SH architecture, there are four registers (R4 to R7)
1992 which are dedicated for passing function arguments. Up to the first
1993 four arguments (depending on size) may go into these registers.
1994 The rest go on the stack.
1996 Arguments that are smaller than 4 bytes will still take up a whole
1997 register or a whole 32-bit word on the stack, and will be
1998 right-justified in the register or the stack word. This includes
1999 chars, shorts, and small aggregate types.
2001 Arguments that are larger than 4 bytes may be split between two or
2002 more registers. If there are not enough registers free, an argument
2003 may be passed partly in a register (or registers), and partly on the
2004 stack. This includes doubles, long longs, and larger aggregates.
2005 As far as I know, there is no upper limit to the size of aggregates
2006 that will be passed in this way; in other words, the convention of
2007 passing a pointer to a large aggregate instead of a copy is not used.
2009 An exceptional case exists for struct arguments (and possibly other
2010 aggregates such as arrays) if the size is larger than 4 bytes but
2011 not a multiple of 4 bytes. In this case the argument is never split
2012 between the registers and the stack, but instead is copied in its
2013 entirety onto the stack, AND also copied into as many registers as
2014 there is room for. In other words, space in registers permitting,
2015 two copies of the same argument are passed in. As far as I can tell,
2016 only the one on the stack is used, although that may be a function
2017 of the level of compiler optimization. I suspect this is a compiler
2018 bug. Arguments of these odd sizes are left-justified within the
2019 word (as opposed to arguments smaller than 4 bytes, which are
2022 If the function is to return an aggregate type such as a struct, it
2023 is either returned in the normal return value register R0 (if its
2024 size is no greater than one byte), or else the caller must allocate
2025 space into which the callee will copy the return value (if the size
2026 is greater than one byte). In this case, a pointer to the return
2027 value location is passed into the callee in register R2, which does
2028 not displace any of the other arguments passed in via registers R4
2032 sh_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2033 int struct_return
, CORE_ADDR struct_addr
)
2035 int stack_offset
, stack_alloc
;
2043 int odd_sized_struct
;
2044 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2046 /* first force sp to a 4-byte alignment */
2049 /* The "struct return pointer" pseudo-argument has its own dedicated
2052 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2054 /* Now make sure there's space on the stack */
2055 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2056 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 3) & ~3);
2057 sp
-= stack_alloc
; /* make room on stack for args */
2059 /* Now load as many as possible of the first arguments into
2060 registers, and push the rest onto the stack. There are 16 bytes
2061 in four registers available. Loop thru args from first to last. */
2063 argreg
= tdep
->ARG0_REGNUM
;
2064 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2066 type
= VALUE_TYPE (args
[argnum
]);
2067 len
= TYPE_LENGTH (type
);
2068 memset (valbuf
, 0, sizeof (valbuf
));
2071 /* value gets right-justified in the register or stack word */
2072 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2073 memcpy (valbuf
+ (4 - len
),
2074 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2076 memcpy (valbuf
, (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2080 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2082 if (len
> 4 && (len
& 3) != 0)
2083 odd_sized_struct
= 1; /* such structs go entirely on stack */
2085 odd_sized_struct
= 0;
2088 if (argreg
> tdep
->ARGLAST_REGNUM
2089 || odd_sized_struct
)
2091 /* must go on the stack */
2092 write_memory (sp
+ stack_offset
, val
, 4);
2095 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2096 That's because some *&^%$ things get passed on the stack
2097 AND in the registers! */
2098 if (argreg
<= tdep
->ARGLAST_REGNUM
)
2100 /* there's room in a register */
2101 regval
= extract_address (val
, REGISTER_RAW_SIZE (argreg
));
2102 write_register (argreg
++, regval
);
2104 /* Store the value 4 bytes at a time. This means that things
2105 larger than 4 bytes may go partly in registers and partly
2107 len
-= REGISTER_RAW_SIZE (argreg
);
2108 val
+= REGISTER_RAW_SIZE (argreg
);
2114 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2115 non-scalar (struct, union) elements (even if the elements are
2117 FR0-FR11 for single precision floating point (float)
2118 DR0-DR10 for double precision floating point (double)
2120 If a float is argument number 3 (for instance) and arguments number
2121 1,2, and 4 are integer, the mapping will be:
2122 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2124 If a float is argument number 10 (for instance) and arguments number
2125 1 through 10 are integer, the mapping will be:
2126 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2127 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2128 I.e. there is hole in the stack.
2130 Different rules apply for variable arguments functions, and for functions
2131 for which the prototype is not known. */
2134 sh64_push_arguments (int nargs
, struct value
**args
, CORE_ADDR sp
,
2135 int struct_return
, CORE_ADDR struct_addr
)
2137 int stack_offset
, stack_alloc
;
2141 int float_arg_index
= 0;
2142 int double_arg_index
= 0;
2152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2154 memset (fp_args
, 0, sizeof (fp_args
));
2156 /* first force sp to a 8-byte alignment */
2159 /* The "struct return pointer" pseudo-argument has its own dedicated
2163 write_register (STRUCT_RETURN_REGNUM
, struct_addr
);
2165 /* Now make sure there's space on the stack */
2166 for (argnum
= 0, stack_alloc
= 0; argnum
< nargs
; argnum
++)
2167 stack_alloc
+= ((TYPE_LENGTH (VALUE_TYPE (args
[argnum
])) + 7) & ~7);
2168 sp
-= stack_alloc
; /* make room on stack for args */
2170 /* Now load as many as possible of the first arguments into
2171 registers, and push the rest onto the stack. There are 64 bytes
2172 in eight registers available. Loop thru args from first to last. */
2174 int_argreg
= tdep
->ARG0_REGNUM
;
2175 float_argreg
= FP0_REGNUM
;
2176 double_argreg
= tdep
->DR0_REGNUM
;
2178 for (argnum
= 0, stack_offset
= 0; argnum
< nargs
; argnum
++)
2180 type
= VALUE_TYPE (args
[argnum
]);
2181 len
= TYPE_LENGTH (type
);
2182 memset (valbuf
, 0, sizeof (valbuf
));
2184 if (TYPE_CODE (type
) != TYPE_CODE_FLT
)
2186 argreg_size
= REGISTER_RAW_SIZE (int_argreg
);
2188 if (len
< argreg_size
)
2190 /* value gets right-justified in the register or stack word */
2191 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2192 memcpy (valbuf
+ argreg_size
- len
,
2193 (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2195 memcpy (valbuf
, (char *) VALUE_CONTENTS (args
[argnum
]), len
);
2200 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2204 if (int_argreg
> tdep
->ARGLAST_REGNUM
)
2206 /* must go on the stack */
2207 write_memory (sp
+ stack_offset
, val
, argreg_size
);
2208 stack_offset
+= 8;/*argreg_size;*/
2210 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2211 That's because some *&^%$ things get passed on the stack
2212 AND in the registers! */
2213 if (int_argreg
<= tdep
->ARGLAST_REGNUM
)
2215 /* there's room in a register */
2216 regval
= extract_address (val
, argreg_size
);
2217 write_register (int_argreg
, regval
);
2219 /* Store the value 8 bytes at a time. This means that
2220 things larger than 8 bytes may go partly in registers
2221 and partly on the stack. FIXME: argreg is incremented
2222 before we use its size. */
2230 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
2233 /* Where is it going to be stored? */
2234 while (fp_args
[float_arg_index
])
2237 /* Now float_argreg points to the register where it
2238 should be stored. Are we still within the allowed
2240 if (float_arg_index
<= tdep
->FLOAT_ARGLAST_REGNUM
)
2242 /* Goes in FR0...FR11 */
2243 deprecated_write_register_gen (FP0_REGNUM
+ float_arg_index
,
2245 fp_args
[float_arg_index
] = 1;
2246 /* Skip the corresponding general argument register. */
2251 /* Store it as the integers, 8 bytes at the time, if
2252 necessary spilling on the stack. */
2257 /* Where is it going to be stored? */
2258 while (fp_args
[double_arg_index
])
2259 double_arg_index
+= 2;
2260 /* Now double_argreg points to the register
2261 where it should be stored.
2262 Are we still within the allowed register set? */
2263 if (double_arg_index
< tdep
->FLOAT_ARGLAST_REGNUM
)
2265 /* Goes in DR0...DR10 */
2266 /* The numbering of the DRi registers is consecutive,
2267 i.e. includes odd numbers. */
2268 int double_register_offset
= double_arg_index
/ 2;
2269 int regnum
= tdep
->DR0_REGNUM
+
2270 double_register_offset
;
2272 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2274 memset (valbuf_tmp
, 0, sizeof (valbuf_tmp
));
2275 REGISTER_CONVERT_TO_VIRTUAL (regnum
,
2276 type
, val
, valbuf_tmp
);
2280 /* Note: must use write_register_gen here instead
2281 of regcache_raw_write, because
2282 regcache_raw_write works only for real
2283 registers, not pseudo. write_register_gen will
2284 call the gdbarch function to do register
2285 writes, and that will properly know how to deal
2287 deprecated_write_register_gen (regnum
, val
);
2288 fp_args
[double_arg_index
] = 1;
2289 fp_args
[double_arg_index
+ 1] = 1;
2290 /* Skip the corresponding general argument register. */
2295 /* Store it as the integers, 8 bytes at the time, if
2296 necessary spilling on the stack. */
2303 /* Function: push_return_address (pc)
2304 Set up the return address for the inferior function call.
2305 Needed for targets where we don't actually execute a JSR/BSR instruction */
2308 sh_push_return_address (CORE_ADDR pc
, CORE_ADDR sp
)
2310 write_register (gdbarch_tdep (current_gdbarch
)->PR_REGNUM
,
2311 CALL_DUMMY_ADDRESS ());
2315 /* Function: fix_call_dummy
2316 Poke the callee function's address into the destination part of
2317 the CALL_DUMMY. The address is actually stored in a data word
2318 following the actualy CALL_DUMMY instructions, which will load
2319 it into a register using PC-relative addressing. This function
2320 expects the CALL_DUMMY to look like this:
2331 sh_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
2332 struct value
**args
, struct type
*type
, int gcc_p
)
2334 *(unsigned long *) (dummy
+ 8) = fun
;
2338 /* Find a function's return value in the appropriate registers (in
2339 regbuf), and copy it into valbuf. Extract from an array REGBUF
2340 containing the (raw) register state a function return value of type
2341 TYPE, and copy that, in virtual format, into VALBUF. */
2343 sh_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2345 int len
= TYPE_LENGTH (type
);
2346 int return_register
= R0_REGNUM
;
2351 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2352 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2354 offset
= REGISTER_BYTE (return_register
);
2355 memcpy (valbuf
, regbuf
+ offset
, len
);
2359 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2360 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2362 offset
= REGISTER_BYTE (return_register
);
2363 memcpy (valbuf
, regbuf
+ offset
, len
);
2366 error ("bad size for return value");
2370 sh3e_sh4_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2372 int return_register
;
2374 int len
= TYPE_LENGTH (type
);
2376 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2377 return_register
= FP0_REGNUM
;
2379 return_register
= R0_REGNUM
;
2381 if (len
== 8 && TYPE_CODE (type
) == TYPE_CODE_FLT
)
2384 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2385 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2386 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2389 floatformat_to_doublest (&floatformat_ieee_double_big
,
2390 (char *) regbuf
+ REGISTER_BYTE (return_register
),
2392 store_floating (valbuf
, len
, val
);
2396 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2397 offset
= REGISTER_BYTE (return_register
) + 4 - len
;
2399 offset
= REGISTER_BYTE (return_register
);
2400 memcpy (valbuf
, regbuf
+ offset
, len
);
2404 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2405 offset
= REGISTER_BYTE (return_register
) + 8 - len
;
2407 offset
= REGISTER_BYTE (return_register
);
2408 memcpy (valbuf
, regbuf
+ offset
, len
);
2411 error ("bad size for return value");
2415 sh64_extract_return_value (struct type
*type
, char *regbuf
, char *valbuf
)
2418 int return_register
;
2419 int len
= TYPE_LENGTH (type
);
2420 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2422 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2426 /* Return value stored in FP0_REGNUM */
2427 return_register
= FP0_REGNUM
;
2428 offset
= REGISTER_BYTE (return_register
);
2429 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2433 /* return value stored in DR0_REGNUM */
2436 return_register
= tdep
->DR0_REGNUM
;
2437 offset
= REGISTER_BYTE (return_register
);
2439 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2440 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
,
2441 (char *) regbuf
+ offset
, &val
);
2443 floatformat_to_doublest (&floatformat_ieee_double_big
,
2444 (char *) regbuf
+ offset
, &val
);
2445 store_floating (valbuf
, len
, val
);
2452 /* Result is in register 2. If smaller than 8 bytes, it is padded
2453 at the most significant end. */
2454 return_register
= tdep
->RETURN_REGNUM
;
2455 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2456 offset
= REGISTER_BYTE (return_register
) +
2457 REGISTER_RAW_SIZE (return_register
) - len
;
2459 offset
= REGISTER_BYTE (return_register
);
2460 memcpy (valbuf
, (char *) regbuf
+ offset
, len
);
2463 error ("bad size for return value");
2467 /* Write into appropriate registers a function return value
2468 of type TYPE, given in virtual format.
2469 If the architecture is sh4 or sh3e, store a function's return value
2470 in the R0 general register or in the FP0 floating point register,
2471 depending on the type of the return value. In all the other cases
2472 the result is stored in r0, left-justified. */
2474 sh_default_store_return_value (struct type
*type
, char *valbuf
)
2476 char buf
[32]; /* more than enough... */
2478 if (TYPE_LENGTH (type
) < REGISTER_RAW_SIZE (R0_REGNUM
))
2480 /* Add leading zeros to the value. */
2481 memset (buf
, 0, REGISTER_RAW_SIZE (R0_REGNUM
));
2482 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
2483 memcpy (buf
+ REGISTER_RAW_SIZE (R0_REGNUM
) - TYPE_LENGTH (type
),
2484 valbuf
, TYPE_LENGTH (type
));
2486 memcpy (buf
, valbuf
, TYPE_LENGTH (type
));
2487 deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM
), buf
,
2488 REGISTER_RAW_SIZE (R0_REGNUM
));
2491 deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM
), valbuf
,
2492 TYPE_LENGTH (type
));
2496 sh3e_sh4_store_return_value (struct type
*type
, char *valbuf
)
2498 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2499 deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM
),
2500 valbuf
, TYPE_LENGTH (type
));
2502 sh_default_store_return_value (type
, valbuf
);
2506 sh64_store_return_value (struct type
*type
, char *valbuf
)
2508 char buf
[64]; /* more than enough... */
2509 int len
= TYPE_LENGTH (type
);
2511 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2515 /* Return value stored in FP0_REGNUM */
2516 deprecated_write_register_gen (FP0_REGNUM
, valbuf
);
2520 /* return value stored in DR0_REGNUM */
2521 /* FIXME: Implement */
2526 int return_register
= gdbarch_tdep (current_gdbarch
)->RETURN_REGNUM
;
2529 if (len
<= REGISTER_RAW_SIZE (return_register
))
2531 /* Pad with zeros. */
2532 memset (buf
, 0, REGISTER_RAW_SIZE (return_register
));
2533 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_LITTLE
)
2534 offset
= 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2536 offset
= REGISTER_RAW_SIZE (return_register
) - len
;
2538 memcpy (buf
+ offset
, valbuf
, len
);
2539 deprecated_write_register_gen (return_register
, buf
);
2542 deprecated_write_register_gen (return_register
, valbuf
);
2546 /* Print the registers in a form similar to the E7000 */
2549 sh_generic_show_regs (void)
2551 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2553 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2554 paddr (read_register (PC_REGNUM
)),
2555 (long) read_register (tdep
->SR_REGNUM
),
2556 (long) read_register (tdep
->PR_REGNUM
),
2557 (long) read_register (MACH_REGNUM
),
2558 (long) read_register (MACL_REGNUM
));
2560 printf_filtered ("GBR=%08lx VBR=%08lx",
2561 (long) read_register (GBR_REGNUM
),
2562 (long) read_register (VBR_REGNUM
));
2564 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2565 (long) read_register (0),
2566 (long) read_register (1),
2567 (long) read_register (2),
2568 (long) read_register (3),
2569 (long) read_register (4),
2570 (long) read_register (5),
2571 (long) read_register (6),
2572 (long) read_register (7));
2573 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2574 (long) read_register (8),
2575 (long) read_register (9),
2576 (long) read_register (10),
2577 (long) read_register (11),
2578 (long) read_register (12),
2579 (long) read_register (13),
2580 (long) read_register (14),
2581 (long) read_register (15));
2585 sh3_show_regs (void)
2587 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2589 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2590 paddr (read_register (PC_REGNUM
)),
2591 (long) read_register (tdep
->SR_REGNUM
),
2592 (long) read_register (tdep
->PR_REGNUM
),
2593 (long) read_register (MACH_REGNUM
),
2594 (long) read_register (MACL_REGNUM
));
2596 printf_filtered ("GBR=%08lx VBR=%08lx",
2597 (long) read_register (GBR_REGNUM
),
2598 (long) read_register (VBR_REGNUM
));
2599 printf_filtered (" SSR=%08lx SPC=%08lx",
2600 (long) read_register (tdep
->SSR_REGNUM
),
2601 (long) read_register (tdep
->SPC_REGNUM
));
2603 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2604 (long) read_register (0),
2605 (long) read_register (1),
2606 (long) read_register (2),
2607 (long) read_register (3),
2608 (long) read_register (4),
2609 (long) read_register (5),
2610 (long) read_register (6),
2611 (long) read_register (7));
2612 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2613 (long) read_register (8),
2614 (long) read_register (9),
2615 (long) read_register (10),
2616 (long) read_register (11),
2617 (long) read_register (12),
2618 (long) read_register (13),
2619 (long) read_register (14),
2620 (long) read_register (15));
2625 sh3e_show_regs (void)
2627 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2629 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2630 paddr (read_register (PC_REGNUM
)),
2631 (long) read_register (tdep
->SR_REGNUM
),
2632 (long) read_register (tdep
->PR_REGNUM
),
2633 (long) read_register (MACH_REGNUM
),
2634 (long) read_register (MACL_REGNUM
));
2636 printf_filtered ("GBR=%08lx VBR=%08lx",
2637 (long) read_register (GBR_REGNUM
),
2638 (long) read_register (VBR_REGNUM
));
2639 printf_filtered (" SSR=%08lx SPC=%08lx",
2640 (long) read_register (tdep
->SSR_REGNUM
),
2641 (long) read_register (tdep
->SPC_REGNUM
));
2642 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2643 (long) read_register (tdep
->FPUL_REGNUM
),
2644 (long) read_register (tdep
->FPSCR_REGNUM
));
2646 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2647 (long) read_register (0),
2648 (long) read_register (1),
2649 (long) read_register (2),
2650 (long) read_register (3),
2651 (long) read_register (4),
2652 (long) read_register (5),
2653 (long) read_register (6),
2654 (long) read_register (7));
2655 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2656 (long) read_register (8),
2657 (long) read_register (9),
2658 (long) read_register (10),
2659 (long) read_register (11),
2660 (long) read_register (12),
2661 (long) read_register (13),
2662 (long) read_register (14),
2663 (long) read_register (15));
2665 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2666 (long) read_register (FP0_REGNUM
+ 0),
2667 (long) read_register (FP0_REGNUM
+ 1),
2668 (long) read_register (FP0_REGNUM
+ 2),
2669 (long) read_register (FP0_REGNUM
+ 3),
2670 (long) read_register (FP0_REGNUM
+ 4),
2671 (long) read_register (FP0_REGNUM
+ 5),
2672 (long) read_register (FP0_REGNUM
+ 6),
2673 (long) read_register (FP0_REGNUM
+ 7));
2674 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2675 (long) read_register (FP0_REGNUM
+ 8),
2676 (long) read_register (FP0_REGNUM
+ 9),
2677 (long) read_register (FP0_REGNUM
+ 10),
2678 (long) read_register (FP0_REGNUM
+ 11),
2679 (long) read_register (FP0_REGNUM
+ 12),
2680 (long) read_register (FP0_REGNUM
+ 13),
2681 (long) read_register (FP0_REGNUM
+ 14),
2682 (long) read_register (FP0_REGNUM
+ 15));
2686 sh3_dsp_show_regs (void)
2688 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2690 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2691 paddr (read_register (PC_REGNUM
)),
2692 (long) read_register (tdep
->SR_REGNUM
),
2693 (long) read_register (tdep
->PR_REGNUM
),
2694 (long) read_register (MACH_REGNUM
),
2695 (long) read_register (MACL_REGNUM
));
2697 printf_filtered ("GBR=%08lx VBR=%08lx",
2698 (long) read_register (GBR_REGNUM
),
2699 (long) read_register (VBR_REGNUM
));
2701 printf_filtered (" SSR=%08lx SPC=%08lx",
2702 (long) read_register (tdep
->SSR_REGNUM
),
2703 (long) read_register (tdep
->SPC_REGNUM
));
2705 printf_filtered (" DSR=%08lx",
2706 (long) read_register (tdep
->DSR_REGNUM
));
2708 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2709 (long) read_register (0),
2710 (long) read_register (1),
2711 (long) read_register (2),
2712 (long) read_register (3),
2713 (long) read_register (4),
2714 (long) read_register (5),
2715 (long) read_register (6),
2716 (long) read_register (7));
2717 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2718 (long) read_register (8),
2719 (long) read_register (9),
2720 (long) read_register (10),
2721 (long) read_register (11),
2722 (long) read_register (12),
2723 (long) read_register (13),
2724 (long) read_register (14),
2725 (long) read_register (15));
2727 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2728 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2729 (long) read_register (tdep
->A0_REGNUM
),
2730 (long) read_register (tdep
->M0_REGNUM
),
2731 (long) read_register (tdep
->X0_REGNUM
),
2732 (long) read_register (tdep
->Y0_REGNUM
),
2733 (long) read_register (tdep
->RS_REGNUM
),
2734 (long) read_register (tdep
->MOD_REGNUM
));
2735 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2736 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2737 (long) read_register (tdep
->A1_REGNUM
),
2738 (long) read_register (tdep
->M1_REGNUM
),
2739 (long) read_register (tdep
->X1_REGNUM
),
2740 (long) read_register (tdep
->Y1_REGNUM
),
2741 (long) read_register (tdep
->RE_REGNUM
));
2745 sh4_show_regs (void)
2747 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2749 int pr
= read_register (tdep
->FPSCR_REGNUM
) & 0x80000;
2750 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2751 paddr (read_register (PC_REGNUM
)),
2752 (long) read_register (tdep
->SR_REGNUM
),
2753 (long) read_register (tdep
->PR_REGNUM
),
2754 (long) read_register (MACH_REGNUM
),
2755 (long) read_register (MACL_REGNUM
));
2757 printf_filtered ("GBR=%08lx VBR=%08lx",
2758 (long) read_register (GBR_REGNUM
),
2759 (long) read_register (VBR_REGNUM
));
2760 printf_filtered (" SSR=%08lx SPC=%08lx",
2761 (long) read_register (tdep
->SSR_REGNUM
),
2762 (long) read_register (tdep
->SPC_REGNUM
));
2763 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2764 (long) read_register (tdep
->FPUL_REGNUM
),
2765 (long) read_register (tdep
->FPSCR_REGNUM
));
2767 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2768 (long) read_register (0),
2769 (long) read_register (1),
2770 (long) read_register (2),
2771 (long) read_register (3),
2772 (long) read_register (4),
2773 (long) read_register (5),
2774 (long) read_register (6),
2775 (long) read_register (7));
2776 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2777 (long) read_register (8),
2778 (long) read_register (9),
2779 (long) read_register (10),
2780 (long) read_register (11),
2781 (long) read_register (12),
2782 (long) read_register (13),
2783 (long) read_register (14),
2784 (long) read_register (15));
2786 printf_filtered ((pr
2787 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2788 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2789 (long) read_register (FP0_REGNUM
+ 0),
2790 (long) read_register (FP0_REGNUM
+ 1),
2791 (long) read_register (FP0_REGNUM
+ 2),
2792 (long) read_register (FP0_REGNUM
+ 3),
2793 (long) read_register (FP0_REGNUM
+ 4),
2794 (long) read_register (FP0_REGNUM
+ 5),
2795 (long) read_register (FP0_REGNUM
+ 6),
2796 (long) read_register (FP0_REGNUM
+ 7));
2797 printf_filtered ((pr
2798 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2799 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2800 (long) read_register (FP0_REGNUM
+ 8),
2801 (long) read_register (FP0_REGNUM
+ 9),
2802 (long) read_register (FP0_REGNUM
+ 10),
2803 (long) read_register (FP0_REGNUM
+ 11),
2804 (long) read_register (FP0_REGNUM
+ 12),
2805 (long) read_register (FP0_REGNUM
+ 13),
2806 (long) read_register (FP0_REGNUM
+ 14),
2807 (long) read_register (FP0_REGNUM
+ 15));
2811 sh_dsp_show_regs (void)
2813 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2815 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2816 paddr (read_register (PC_REGNUM
)),
2817 (long) read_register (tdep
->SR_REGNUM
),
2818 (long) read_register (tdep
->PR_REGNUM
),
2819 (long) read_register (MACH_REGNUM
),
2820 (long) read_register (MACL_REGNUM
));
2822 printf_filtered ("GBR=%08lx VBR=%08lx",
2823 (long) read_register (GBR_REGNUM
),
2824 (long) read_register (VBR_REGNUM
));
2826 printf_filtered (" DSR=%08lx",
2827 (long) read_register (tdep
->DSR_REGNUM
));
2829 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2830 (long) read_register (0),
2831 (long) read_register (1),
2832 (long) read_register (2),
2833 (long) read_register (3),
2834 (long) read_register (4),
2835 (long) read_register (5),
2836 (long) read_register (6),
2837 (long) read_register (7));
2838 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2839 (long) read_register (8),
2840 (long) read_register (9),
2841 (long) read_register (10),
2842 (long) read_register (11),
2843 (long) read_register (12),
2844 (long) read_register (13),
2845 (long) read_register (14),
2846 (long) read_register (15));
2848 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2849 (long) read_register (tdep
->A0G_REGNUM
) & 0xff,
2850 (long) read_register (tdep
->A0_REGNUM
),
2851 (long) read_register (tdep
->M0_REGNUM
),
2852 (long) read_register (tdep
->X0_REGNUM
),
2853 (long) read_register (tdep
->Y0_REGNUM
),
2854 (long) read_register (tdep
->RS_REGNUM
),
2855 (long) read_register (tdep
->MOD_REGNUM
));
2856 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2857 (long) read_register (tdep
->A1G_REGNUM
) & 0xff,
2858 (long) read_register (tdep
->A1_REGNUM
),
2859 (long) read_register (tdep
->M1_REGNUM
),
2860 (long) read_register (tdep
->X1_REGNUM
),
2861 (long) read_register (tdep
->Y1_REGNUM
),
2862 (long) read_register (tdep
->RE_REGNUM
));
2866 sh64_show_media_regs (void)
2869 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2871 printf_filtered ("PC=%s SR=%016llx \n",
2872 paddr (read_register (PC_REGNUM
)),
2873 (long long) read_register (tdep
->SR_REGNUM
));
2875 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2876 (long long) read_register (tdep
->SSR_REGNUM
),
2877 (long long) read_register (tdep
->SPC_REGNUM
));
2878 printf_filtered ("FPSCR=%016lx\n ",
2879 (long) read_register (tdep
->FPSCR_REGNUM
));
2881 for (i
= 0; i
< 64; i
= i
+ 4)
2882 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2884 (long long) read_register (i
+ 0),
2885 (long long) read_register (i
+ 1),
2886 (long long) read_register (i
+ 2),
2887 (long long) read_register (i
+ 3));
2889 printf_filtered ("\n");
2891 for (i
= 0; i
< 64; i
= i
+ 8)
2892 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2894 (long) read_register (FP0_REGNUM
+ i
+ 0),
2895 (long) read_register (FP0_REGNUM
+ i
+ 1),
2896 (long) read_register (FP0_REGNUM
+ i
+ 2),
2897 (long) read_register (FP0_REGNUM
+ i
+ 3),
2898 (long) read_register (FP0_REGNUM
+ i
+ 4),
2899 (long) read_register (FP0_REGNUM
+ i
+ 5),
2900 (long) read_register (FP0_REGNUM
+ i
+ 6),
2901 (long) read_register (FP0_REGNUM
+ i
+ 7));
2905 sh64_show_compact_regs (void)
2908 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2910 printf_filtered ("PC=%s \n",
2911 paddr (read_register (tdep
->PC_C_REGNUM
)));
2913 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2914 (long) read_register (tdep
->GBR_C_REGNUM
),
2915 (long) read_register (tdep
->MACH_C_REGNUM
),
2916 (long) read_register (tdep
->MACL_C_REGNUM
),
2917 (long) read_register (tdep
->PR_C_REGNUM
),
2918 (long) read_register (tdep
->T_C_REGNUM
));
2919 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2920 (long) read_register (tdep
->FPSCR_REGNUM
),
2921 (long) read_register (tdep
->FPUL_REGNUM
));
2923 for (i
= 0; i
< 16; i
= i
+ 4)
2924 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2926 (long) read_register (i
+ 0),
2927 (long) read_register (i
+ 1),
2928 (long) read_register (i
+ 2),
2929 (long) read_register (i
+ 3));
2931 printf_filtered ("\n");
2933 for (i
= 0; i
< 16; i
= i
+ 8)
2934 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2936 (long) read_register (FP0_REGNUM
+ i
+ 0),
2937 (long) read_register (FP0_REGNUM
+ i
+ 1),
2938 (long) read_register (FP0_REGNUM
+ i
+ 2),
2939 (long) read_register (FP0_REGNUM
+ i
+ 3),
2940 (long) read_register (FP0_REGNUM
+ i
+ 4),
2941 (long) read_register (FP0_REGNUM
+ i
+ 5),
2942 (long) read_register (FP0_REGNUM
+ i
+ 6),
2943 (long) read_register (FP0_REGNUM
+ i
+ 7));
2946 /*FIXME!!! This only shows the registers for shmedia, excluding the
2947 pseudo registers. */
2949 sh64_show_regs (void)
2951 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame
)))
2952 sh64_show_media_regs ();
2954 sh64_show_compact_regs ();
2957 void sh_show_regs_command (char *args
, int from_tty
)
2963 /* Index within `registers' of the first byte of the space for
2966 sh_default_register_byte (int reg_nr
)
2968 return (reg_nr
* 4);
2972 sh_sh4_register_byte (int reg_nr
)
2974 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2976 if (reg_nr
>= tdep
->DR0_REGNUM
2977 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
2978 return (dr_reg_base_num (reg_nr
) * 4);
2979 else if (reg_nr
>= tdep
->FV0_REGNUM
2980 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
2981 return (fv_reg_base_num (reg_nr
) * 4);
2983 return (reg_nr
* 4);
2988 SH MEDIA MODE (ISA 32)
2989 general registers (64-bit) 0-63
2990 0 r0, r1, r2, r3, r4, r5, r6, r7,
2991 64 r8, r9, r10, r11, r12, r13, r14, r15,
2992 128 r16, r17, r18, r19, r20, r21, r22, r23,
2993 192 r24, r25, r26, r27, r28, r29, r30, r31,
2994 256 r32, r33, r34, r35, r36, r37, r38, r39,
2995 320 r40, r41, r42, r43, r44, r45, r46, r47,
2996 384 r48, r49, r50, r51, r52, r53, r54, r55,
2997 448 r56, r57, r58, r59, r60, r61, r62, r63,
3002 status reg., saved status reg., saved pc reg. (64-bit) 65-67
3005 target registers (64-bit) 68-75
3006 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
3008 floating point state control register (32-bit) 76
3011 single precision floating point registers (32-bit) 77-140
3012 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
3013 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
3014 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
3015 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
3016 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
3017 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
3018 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
3019 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
3021 TOTAL SPACE FOR REGISTERS: 868 bytes
3023 From here on they are all pseudo registers: no memory allocated.
3024 REGISTER_BYTE returns the register byte for the base register.
3026 double precision registers (pseudo) 141-172
3027 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3028 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3029 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3030 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3032 floating point pairs (pseudo) 173-204
3033 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3034 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3035 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3036 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3038 floating point vectors (4 floating point regs) (pseudo) 205-220
3039 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3040 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3042 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3043 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3044 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3046 gbr_c, mach_c, macl_c, pr_c, t_c,
3048 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3049 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3050 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3051 fv0_c, fv4_c, fv8_c, fv12_c
3055 sh_sh64_register_byte (int reg_nr
)
3057 int base_regnum
= -1;
3058 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3060 /* If it is a pseudo register, get the number of the first floating
3061 point register that is part of it. */
3062 if (reg_nr
>= tdep
->DR0_REGNUM
3063 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3064 base_regnum
= dr_reg_base_num (reg_nr
);
3066 else if (reg_nr
>= tdep
->FPP0_REGNUM
3067 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3068 base_regnum
= fpp_reg_base_num (reg_nr
);
3070 else if (reg_nr
>= tdep
->FV0_REGNUM
3071 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3072 base_regnum
= fv_reg_base_num (reg_nr
);
3074 /* sh compact pseudo register. FPSCR is a pathological case, need to
3075 treat it as special. */
3076 else if ((reg_nr
>= tdep
->R0_C_REGNUM
3077 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3078 && reg_nr
!= tdep
->FPSCR_C_REGNUM
)
3079 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3081 /* Now return the offset in bytes within the register cache. */
3082 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3083 if (reg_nr
>= tdep
->DR0_REGNUM
3084 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3085 return (base_regnum
- FP0_REGNUM
+ 1) * 4
3086 + (tdep
->TR7_REGNUM
+ 1) * 8;
3088 /* sh compact pseudo register: general register */
3089 if ((reg_nr
>= tdep
->R0_C_REGNUM
3090 && reg_nr
<= tdep
->R_LAST_C_REGNUM
))
3091 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3092 ? base_regnum
* 8 + 4
3095 /* sh compact pseudo register: */
3096 if (reg_nr
== tdep
->PC_C_REGNUM
3097 || reg_nr
== tdep
->GBR_C_REGNUM
3098 || reg_nr
== tdep
->MACL_C_REGNUM
3099 || reg_nr
== tdep
->PR_C_REGNUM
)
3100 return (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
3101 ? base_regnum
* 8 + 4
3104 if (reg_nr
== tdep
->MACH_C_REGNUM
)
3105 return base_regnum
* 8;
3107 if (reg_nr
== tdep
->T_C_REGNUM
)
3108 return base_regnum
* 8; /* FIXME??? how do we get bit 0? Do we have to? */
3110 /* sh compact pseudo register: floating point register */
3111 else if (reg_nr
>=tdep
->FP0_C_REGNUM
3112 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3113 return (base_regnum
- FP0_REGNUM
) * 4
3114 + (tdep
->TR7_REGNUM
+ 1) * 8 + 4;
3116 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3117 /* This is complicated, for now return the beginning of the
3118 architectural FPSCR register. */
3119 return (tdep
->TR7_REGNUM
+ 1) * 8;
3121 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3122 return ((base_regnum
- FP0_REGNUM
) * 4 +
3123 (tdep
->TR7_REGNUM
+ 1) * 8 + 4);
3125 /* It is not a pseudo register. */
3126 /* It is a 64 bit register. */
3127 else if (reg_nr
<= tdep
->TR7_REGNUM
)
3130 /* It is a 32 bit register. */
3132 if (reg_nr
== tdep
->FPSCR_REGNUM
)
3133 return (tdep
->FPSCR_REGNUM
* 8);
3135 /* It is floating point 32-bit register */
3137 return ((tdep
->TR7_REGNUM
+ 1) * 8
3138 + (reg_nr
- FP0_REGNUM
+ 1) * 4);
3141 /* Number of bytes of storage in the actual machine representation for
3144 sh_default_register_raw_size (int reg_nr
)
3150 sh_sh4_register_raw_size (int reg_nr
)
3152 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3154 if (reg_nr
>= tdep
->DR0_REGNUM
3155 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3157 else if (reg_nr
>= tdep
->FV0_REGNUM
3158 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3165 sh_sh64_register_raw_size (int reg_nr
)
3167 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3169 if ((reg_nr
>= tdep
->DR0_REGNUM
3170 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3171 || (reg_nr
>= tdep
->FPP0_REGNUM
3172 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3173 || (reg_nr
>= tdep
->DR0_C_REGNUM
3174 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3175 || (reg_nr
<= tdep
->TR7_REGNUM
))
3178 else if ((reg_nr
>= tdep
->FV0_REGNUM
3179 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3180 || (reg_nr
>= tdep
->FV0_C_REGNUM
3181 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3184 else /* this covers also the 32-bit SH compact registers. */
3188 /* Number of bytes of storage in the program's representation
3191 sh_register_virtual_size (int reg_nr
)
3198 sh_sh64_register_virtual_size (int reg_nr
)
3200 if (reg_nr
>= FP0_REGNUM
3201 && reg_nr
<= gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
)
3207 /* Return the GDB type object for the "standard" data type
3208 of data in register N. */
3209 static struct type
*
3210 sh_sh3e_register_virtual_type (int reg_nr
)
3212 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3214 if ((reg_nr
>= FP0_REGNUM
3215 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3216 || (reg_nr
== tdep
->FPUL_REGNUM
))
3217 return builtin_type_float
;
3219 return builtin_type_int
;
3222 static struct type
*
3223 sh_sh4_build_float_register_type (int high
)
3227 temp
= create_range_type (NULL
, builtin_type_int
, 0, high
);
3228 return create_array_type (NULL
, builtin_type_float
, temp
);
3231 static struct type
*
3232 sh_sh4_register_virtual_type (int reg_nr
)
3234 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3236 if ((reg_nr
>= FP0_REGNUM
3237 && (reg_nr
<= tdep
->FP_LAST_REGNUM
))
3238 || (reg_nr
== tdep
->FPUL_REGNUM
))
3239 return builtin_type_float
;
3240 else if (reg_nr
>= tdep
->DR0_REGNUM
3241 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3242 return builtin_type_double
;
3243 else if (reg_nr
>= tdep
->FV0_REGNUM
3244 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3245 return sh_sh4_build_float_register_type (3);
3247 return builtin_type_int
;
3250 static struct type
*
3251 sh_sh64_register_virtual_type (int reg_nr
)
3253 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3255 if ((reg_nr
>= FP0_REGNUM
3256 && reg_nr
<= tdep
->FP_LAST_REGNUM
)
3257 || (reg_nr
>= tdep
->FP0_C_REGNUM
3258 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
))
3259 return builtin_type_float
;
3260 else if ((reg_nr
>= tdep
->DR0_REGNUM
3261 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3262 || (reg_nr
>= tdep
->DR0_C_REGNUM
3263 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
))
3264 return builtin_type_double
;
3265 else if (reg_nr
>= tdep
->FPP0_REGNUM
3266 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3267 return sh_sh4_build_float_register_type (1);
3268 else if ((reg_nr
>= tdep
->FV0_REGNUM
3269 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3270 ||(reg_nr
>= tdep
->FV0_C_REGNUM
3271 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
))
3272 return sh_sh4_build_float_register_type (3);
3273 else if (reg_nr
== tdep
->FPSCR_REGNUM
)
3274 return builtin_type_int
;
3275 else if (reg_nr
>= tdep
->R0_C_REGNUM
3276 && reg_nr
< tdep
->FP0_C_REGNUM
)
3277 return builtin_type_int
;
3279 return builtin_type_long_long
;
3282 static struct type
*
3283 sh_default_register_virtual_type (int reg_nr
)
3285 return builtin_type_int
;
3288 /* On the sh4, the DRi pseudo registers are problematic if the target
3289 is little endian. When the user writes one of those registers, for
3290 instance with 'ser var $dr0=1', we want the double to be stored
3292 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3293 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3295 This corresponds to little endian byte order & big endian word
3296 order. However if we let gdb write the register w/o conversion, it
3297 will write fr0 and fr1 this way:
3298 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3299 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3300 because it will consider fr0 and fr1 as a single LE stretch of memory.
3302 To achieve what we want we must force gdb to store things in
3303 floatformat_ieee_double_littlebyte_bigword (which is defined in
3304 include/floatformat.h and libiberty/floatformat.c.
3306 In case the target is big endian, there is no problem, the
3307 raw bytes will look like:
3308 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3309 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3311 The other pseudo registers (the FVs) also don't pose a problem
3312 because they are stored as 4 individual FP elements. */
3315 sh_sh4_register_convert_to_virtual (int regnum
, struct type
*type
,
3316 char *from
, char *to
)
3318 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3320 if (regnum
>= tdep
->DR0_REGNUM
3321 && regnum
<= tdep
->DR_LAST_REGNUM
)
3324 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3325 store_floating (to
, TYPE_LENGTH (type
), val
);
3328 error ("sh_register_convert_to_virtual called with non DR register number");
3332 sh_sh64_register_convert_to_virtual (int regnum
, struct type
*type
,
3333 char *from
, char *to
)
3335 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3337 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3339 /* It is a no-op. */
3340 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3344 if ((regnum
>= tdep
->DR0_REGNUM
3345 && regnum
<= tdep
->DR_LAST_REGNUM
)
3346 || (regnum
>= tdep
->DR0_C_REGNUM
3347 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3350 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword
, from
, &val
);
3351 store_floating(to
, TYPE_LENGTH(type
), val
);
3354 error("sh_register_convert_to_virtual called with non DR register number");
3358 sh_sh4_register_convert_to_raw (struct type
*type
, int regnum
,
3359 const void *from
, void *to
)
3361 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3363 if (regnum
>= tdep
->DR0_REGNUM
3364 && regnum
<= tdep
->DR_LAST_REGNUM
)
3366 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3367 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3370 error("sh_register_convert_to_raw called with non DR register number");
3374 sh_sh64_register_convert_to_raw (struct type
*type
, int regnum
,
3375 const void *from
, void *to
)
3377 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3379 if (TARGET_BYTE_ORDER
!= BFD_ENDIAN_LITTLE
)
3381 /* It is a no-op. */
3382 memcpy (to
, from
, REGISTER_RAW_SIZE (regnum
));
3386 if ((regnum
>= tdep
->DR0_REGNUM
3387 && regnum
<= tdep
->DR_LAST_REGNUM
)
3388 || (regnum
>= tdep
->DR0_C_REGNUM
3389 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3391 DOUBLEST val
= extract_floating (from
, TYPE_LENGTH(type
));
3392 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword
, &val
, to
);
3395 error("sh_register_convert_to_raw called with non DR register number");
3399 sh_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3400 int reg_nr
, void *buffer
)
3402 int base_regnum
, portion
;
3403 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3404 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3406 if (reg_nr
>= tdep
->DR0_REGNUM
3407 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3409 base_regnum
= dr_reg_base_num (reg_nr
);
3411 /* Build the value in the provided buffer. */
3412 /* Read the real regs for which this one is an alias. */
3413 for (portion
= 0; portion
< 2; portion
++)
3414 regcache_raw_read (regcache
, base_regnum
+ portion
,
3416 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3417 /* We must pay attention to the endiannes. */
3418 sh_sh4_register_convert_to_virtual (reg_nr
,
3419 REGISTER_VIRTUAL_TYPE (reg_nr
),
3420 temp_buffer
, buffer
);
3422 else if (reg_nr
>= tdep
->FV0_REGNUM
3423 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3425 base_regnum
= fv_reg_base_num (reg_nr
);
3427 /* Read the real regs for which this one is an alias. */
3428 for (portion
= 0; portion
< 4; portion
++)
3429 regcache_raw_read (regcache
, base_regnum
+ portion
,
3431 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3436 sh64_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3437 int reg_nr
, void *buffer
)
3442 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3443 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3445 if (reg_nr
>= tdep
->DR0_REGNUM
3446 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3448 base_regnum
= dr_reg_base_num (reg_nr
);
3450 /* Build the value in the provided buffer. */
3451 /* DR regs are double precision registers obtained by
3452 concatenating 2 single precision floating point registers. */
3453 for (portion
= 0; portion
< 2; portion
++)
3454 regcache_raw_read (regcache
, base_regnum
+ portion
,
3456 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3458 /* We must pay attention to the endiannes. */
3459 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3460 temp_buffer
, buffer
);
3464 else if (reg_nr
>= tdep
->FPP0_REGNUM
3465 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3467 base_regnum
= fpp_reg_base_num (reg_nr
);
3469 /* Build the value in the provided buffer. */
3470 /* FPP regs are pairs of single precision registers obtained by
3471 concatenating 2 single precision floating point registers. */
3472 for (portion
= 0; portion
< 2; portion
++)
3473 regcache_raw_read (regcache
, base_regnum
+ portion
,
3475 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3478 else if (reg_nr
>= tdep
->FV0_REGNUM
3479 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3481 base_regnum
= fv_reg_base_num (reg_nr
);
3483 /* Build the value in the provided buffer. */
3484 /* FV regs are vectors of single precision registers obtained by
3485 concatenating 4 single precision floating point registers. */
3486 for (portion
= 0; portion
< 4; portion
++)
3487 regcache_raw_read (regcache
, base_regnum
+ portion
,
3489 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3492 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3493 else if (reg_nr
>= tdep
->R0_C_REGNUM
3494 && reg_nr
<= tdep
->T_C_REGNUM
)
3496 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3498 /* Build the value in the provided buffer. */
3499 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
3500 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3502 memcpy (buffer
, temp_buffer
+ offset
, 4); /* get LOWER 32 bits only????*/
3505 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3506 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3508 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3510 /* Build the value in the provided buffer. */
3511 /* Floating point registers map 1-1 to the media fp regs,
3512 they have the same size and endienness. */
3513 regcache_raw_read (regcache
, base_regnum
, buffer
);
3516 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3517 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3519 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3521 /* DR_C regs are double precision registers obtained by
3522 concatenating 2 single precision floating point registers. */
3523 for (portion
= 0; portion
< 2; portion
++)
3524 regcache_raw_read (regcache
, base_regnum
+ portion
,
3526 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3528 /* We must pay attention to the endiannes. */
3529 sh_sh64_register_convert_to_virtual (reg_nr
, REGISTER_VIRTUAL_TYPE (reg_nr
),
3530 temp_buffer
, buffer
);
3533 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3534 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3536 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3538 /* Build the value in the provided buffer. */
3539 /* FV_C regs are vectors of single precision registers obtained by
3540 concatenating 4 single precision floating point registers. */
3541 for (portion
= 0; portion
< 4; portion
++)
3542 regcache_raw_read (regcache
, base_regnum
+ portion
,
3544 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3547 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3549 int fpscr_base_regnum
;
3551 unsigned int fpscr_value
;
3552 unsigned int sr_value
;
3553 unsigned int fpscr_c_value
;
3554 unsigned int fpscr_c_part1_value
;
3555 unsigned int fpscr_c_part2_value
;
3557 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3558 sr_base_regnum
= tdep
->SR_REGNUM
;
3560 /* Build the value in the provided buffer. */
3561 /* FPSCR_C is a very weird register that contains sparse bits
3562 from the FPSCR and the SR architectural registers.
3569 2-17 Bit 2-18 of FPSCR
3570 18-20 Bits 12,13,14 of SR
3574 /* Get FPSCR into a local buffer */
3575 regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
3576 /* Get value as an int. */
3577 fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3578 /* Get SR into a local buffer */
3579 regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
3580 /* Get value as an int. */
3581 sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3582 /* Build the new value. */
3583 fpscr_c_part1_value
= fpscr_value
& 0x3fffd;
3584 fpscr_c_part2_value
= (sr_value
& 0x7000) << 6;
3585 fpscr_c_value
= fpscr_c_part1_value
| fpscr_c_part2_value
;
3586 /* Store that in out buffer!!! */
3587 store_unsigned_integer (buffer
, 4, fpscr_c_value
);
3588 /* FIXME There is surely an endianness gotcha here. */
3591 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3593 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3595 /* FPUL_C register is floating point register 32,
3596 same size, same endianness. */
3597 regcache_raw_read (regcache
, base_regnum
, buffer
);
3602 sh_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3603 int reg_nr
, const void *buffer
)
3605 int base_regnum
, portion
;
3606 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3607 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3609 if (reg_nr
>= tdep
->DR0_REGNUM
3610 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3612 base_regnum
= dr_reg_base_num (reg_nr
);
3614 /* We must pay attention to the endiannes. */
3615 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3616 buffer
, temp_buffer
);
3618 /* Write the real regs for which this one is an alias. */
3619 for (portion
= 0; portion
< 2; portion
++)
3620 regcache_raw_write (regcache
, base_regnum
+ portion
,
3622 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3624 else if (reg_nr
>= tdep
->FV0_REGNUM
3625 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3627 base_regnum
= fv_reg_base_num (reg_nr
);
3629 /* Write the real regs for which this one is an alias. */
3630 for (portion
= 0; portion
< 4; portion
++)
3631 regcache_raw_write (regcache
, base_regnum
+ portion
,
3633 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3638 sh64_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3639 int reg_nr
, const void *buffer
)
3641 int base_regnum
, portion
;
3643 char *temp_buffer
= (char*) alloca (MAX_REGISTER_RAW_SIZE
);
3644 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3646 if (reg_nr
>= tdep
->DR0_REGNUM
3647 && reg_nr
<= tdep
->DR_LAST_REGNUM
)
3649 base_regnum
= dr_reg_base_num (reg_nr
);
3650 /* We must pay attention to the endiannes. */
3651 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3652 buffer
, temp_buffer
);
3655 /* Write the real regs for which this one is an alias. */
3656 for (portion
= 0; portion
< 2; portion
++)
3657 regcache_raw_write (regcache
, base_regnum
+ portion
,
3659 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3662 else if (reg_nr
>= tdep
->FPP0_REGNUM
3663 && reg_nr
<= tdep
->FPP_LAST_REGNUM
)
3665 base_regnum
= fpp_reg_base_num (reg_nr
);
3667 /* Write the real regs for which this one is an alias. */
3668 for (portion
= 0; portion
< 2; portion
++)
3669 regcache_raw_write (regcache
, base_regnum
+ portion
,
3671 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3674 else if (reg_nr
>= tdep
->FV0_REGNUM
3675 && reg_nr
<= tdep
->FV_LAST_REGNUM
)
3677 base_regnum
= fv_reg_base_num (reg_nr
);
3679 /* Write the real regs for which this one is an alias. */
3680 for (portion
= 0; portion
< 4; portion
++)
3681 regcache_raw_write (regcache
, base_regnum
+ portion
,
3683 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3686 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3687 register but only 4 bytes of it. */
3688 else if (reg_nr
>= tdep
->R0_C_REGNUM
3689 && reg_nr
<= tdep
->T_C_REGNUM
)
3691 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3692 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3693 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
3697 /* Let's read the value of the base register into a temporary
3698 buffer, so that overwriting the last four bytes with the new
3699 value of the pseudo will leave the upper 4 bytes unchanged. */
3700 regcache_raw_read (regcache
, base_regnum
, temp_buffer
);
3701 /* Write as an 8 byte quantity */
3702 memcpy (temp_buffer
+ offset
, buffer
, 4);
3703 regcache_raw_write (regcache
, base_regnum
, temp_buffer
);
3706 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3707 registers. Both are 4 bytes. */
3708 else if (reg_nr
>= tdep
->FP0_C_REGNUM
3709 && reg_nr
<= tdep
->FP_LAST_C_REGNUM
)
3711 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3712 regcache_raw_write (regcache
, base_regnum
, buffer
);
3715 else if (reg_nr
>= tdep
->DR0_C_REGNUM
3716 && reg_nr
<= tdep
->DR_LAST_C_REGNUM
)
3718 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3719 for (portion
= 0; portion
< 2; portion
++)
3721 /* We must pay attention to the endiannes. */
3722 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr
), reg_nr
,
3723 buffer
, temp_buffer
);
3725 regcache_raw_write (regcache
, base_regnum
+ portion
,
3727 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3731 else if (reg_nr
>= tdep
->FV0_C_REGNUM
3732 && reg_nr
<= tdep
->FV_LAST_C_REGNUM
)
3734 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3736 for (portion
= 0; portion
< 4; portion
++)
3738 regcache_raw_write (regcache
, base_regnum
+ portion
,
3740 + REGISTER_RAW_SIZE (base_regnum
) * portion
));
3744 else if (reg_nr
== tdep
->FPSCR_C_REGNUM
)
3746 int fpscr_base_regnum
;
3748 unsigned int fpscr_value
;
3749 unsigned int sr_value
;
3750 unsigned int old_fpscr_value
;
3751 unsigned int old_sr_value
;
3752 unsigned int fpscr_c_value
;
3753 unsigned int fpscr_mask
;
3754 unsigned int sr_mask
;
3756 fpscr_base_regnum
= tdep
->FPSCR_REGNUM
;
3757 sr_base_regnum
= tdep
->SR_REGNUM
;
3759 /* FPSCR_C is a very weird register that contains sparse bits
3760 from the FPSCR and the SR architectural registers.
3767 2-17 Bit 2-18 of FPSCR
3768 18-20 Bits 12,13,14 of SR
3772 /* Get value as an int. */
3773 fpscr_c_value
= extract_unsigned_integer (buffer
, 4);
3775 /* Build the new values. */
3776 fpscr_mask
= 0x0003fffd;
3777 sr_mask
= 0x001c0000;
3779 fpscr_value
= fpscr_c_value
& fpscr_mask
;
3780 sr_value
= (fpscr_value
& sr_mask
) >> 6;
3782 regcache_raw_read (regcache
, fpscr_base_regnum
, temp_buffer
);
3783 old_fpscr_value
= extract_unsigned_integer (temp_buffer
, 4);
3784 old_fpscr_value
&= 0xfffc0002;
3785 fpscr_value
|= old_fpscr_value
;
3786 store_unsigned_integer (temp_buffer
, 4, fpscr_value
);
3787 regcache_raw_write (regcache
, fpscr_base_regnum
, temp_buffer
);
3789 regcache_raw_read (regcache
, sr_base_regnum
, temp_buffer
);
3790 old_sr_value
= extract_unsigned_integer (temp_buffer
, 4);
3791 old_sr_value
&= 0xffff8fff;
3792 sr_value
|= old_sr_value
;
3793 store_unsigned_integer (temp_buffer
, 4, sr_value
);
3794 regcache_raw_write (regcache
, sr_base_regnum
, temp_buffer
);
3797 else if (reg_nr
== tdep
->FPUL_C_REGNUM
)
3799 base_regnum
= sh64_compact_reg_base_num (reg_nr
);
3800 regcache_raw_write (regcache
, base_regnum
, buffer
);
3804 /* Floating point vector of 4 float registers. */
3806 do_fv_register_info (int fv_regnum
)
3808 int first_fp_reg_num
= fv_reg_base_num (fv_regnum
);
3809 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3810 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_REGNUM
,
3811 (int) read_register (first_fp_reg_num
),
3812 (int) read_register (first_fp_reg_num
+ 1),
3813 (int) read_register (first_fp_reg_num
+ 2),
3814 (int) read_register (first_fp_reg_num
+ 3));
3817 /* Floating point vector of 4 float registers, compact mode. */
3819 do_fv_c_register_info (int fv_regnum
)
3821 int first_fp_reg_num
= sh64_compact_reg_base_num (fv_regnum
);
3822 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3823 fv_regnum
- gdbarch_tdep (current_gdbarch
)->FV0_C_REGNUM
,
3824 (int) read_register (first_fp_reg_num
),
3825 (int) read_register (first_fp_reg_num
+ 1),
3826 (int) read_register (first_fp_reg_num
+ 2),
3827 (int) read_register (first_fp_reg_num
+ 3));
3830 /* Pairs of single regs. The DR are instead double precision
3833 do_fpp_register_info (int fpp_regnum
)
3835 int first_fp_reg_num
= fpp_reg_base_num (fpp_regnum
);
3837 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3838 fpp_regnum
- gdbarch_tdep (current_gdbarch
)->FPP0_REGNUM
,
3839 (int) read_register (first_fp_reg_num
),
3840 (int) read_register (first_fp_reg_num
+ 1));
3843 /* Double precision registers. */
3845 do_dr_register_info (int dr_regnum
)
3847 int first_fp_reg_num
= dr_reg_base_num (dr_regnum
);
3849 printf_filtered ("dr%d\t0x%08x%08x\n",
3850 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_REGNUM
,
3851 (int) read_register (first_fp_reg_num
),
3852 (int) read_register (first_fp_reg_num
+ 1));
3855 /* Double precision registers, compact mode. */
3857 do_dr_c_register_info (int dr_regnum
)
3859 int first_fp_reg_num
= sh64_compact_reg_base_num (dr_regnum
);
3861 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3862 dr_regnum
- gdbarch_tdep (current_gdbarch
)->DR0_C_REGNUM
,
3863 (int) read_register (first_fp_reg_num
),
3864 (int) read_register (first_fp_reg_num
+1));
3867 /* General register in compact mode. */
3869 do_r_c_register_info (int r_c_regnum
)
3871 int regnum
= sh64_compact_reg_base_num (r_c_regnum
);
3873 printf_filtered ("r%d_c\t0x%08x\n",
3874 r_c_regnum
- gdbarch_tdep (current_gdbarch
)->R0_C_REGNUM
,
3875 /*FIXME!!!*/ (int) read_register (regnum
));
3878 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3879 shmedia REGISTERS. */
3880 /* Control registers, compact mode. */
3882 do_cr_c_register_info (int cr_c_regnum
)
3884 switch (cr_c_regnum
)
3886 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3888 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3890 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3892 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3894 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3896 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3898 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum
));
3900 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum
));
3906 sh_do_pseudo_register (int regnum
)
3908 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3910 if (regnum
< NUM_REGS
|| regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
3911 internal_error (__FILE__
, __LINE__
,
3912 "Invalid pseudo register number %d\n", regnum
);
3913 else if (regnum
>= tdep
->DR0_REGNUM
3914 && regnum
< tdep
->DR_LAST_REGNUM
)
3915 do_dr_register_info (regnum
);
3916 else if (regnum
>= tdep
->FV0_REGNUM
3917 && regnum
<= tdep
->FV_LAST_REGNUM
)
3918 do_fv_register_info (regnum
);
3922 sh_do_fp_register (int regnum
)
3923 { /* do values for FP (float) regs */
3925 double flt
; /* double extracted from raw hex data */
3929 /* Allocate space for the float. */
3930 raw_buffer
= (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM
));
3932 /* Get the data in raw format. */
3933 if (!frame_register_read (deprecated_selected_frame
, regnum
, raw_buffer
))
3934 error ("can't read register %d (%s)", regnum
, REGISTER_NAME (regnum
));
3936 /* Get the register as a number */
3937 flt
= unpack_double (builtin_type_float
, raw_buffer
, &inv
);
3939 /* Print the name and some spaces. */
3940 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
3941 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
3943 /* Print the value. */
3945 printf_filtered ("<invalid float>");
3947 printf_filtered ("%-10.9g", flt
);
3949 /* Print the fp register as hex. */
3950 printf_filtered ("\t(raw 0x");
3951 for (j
= 0; j
< REGISTER_RAW_SIZE (regnum
); j
++)
3953 register int idx
= TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
? j
3954 : REGISTER_RAW_SIZE (regnum
) - 1 - j
;
3955 printf_filtered ("%02x", (unsigned char) raw_buffer
[idx
]);
3957 printf_filtered (")");
3958 printf_filtered ("\n");
3962 sh64_do_pseudo_register (int regnum
)
3964 /* All the sh64-compact mode registers are pseudo registers. */
3965 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3967 if (regnum
< NUM_REGS
3968 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
)
3969 internal_error (__FILE__
, __LINE__
,
3970 "Invalid pseudo register number %d\n", regnum
);
3972 else if ((regnum
>= tdep
->DR0_REGNUM
3973 && regnum
<= tdep
->DR_LAST_REGNUM
))
3974 do_dr_register_info (regnum
);
3976 else if ((regnum
>= tdep
->DR0_C_REGNUM
3977 && regnum
<= tdep
->DR_LAST_C_REGNUM
))
3978 do_dr_c_register_info (regnum
);
3980 else if ((regnum
>= tdep
->FV0_REGNUM
3981 && regnum
<= tdep
->FV_LAST_REGNUM
))
3982 do_fv_register_info (regnum
);
3984 else if ((regnum
>= tdep
->FV0_C_REGNUM
3985 && regnum
<= tdep
->FV_LAST_C_REGNUM
))
3986 do_fv_c_register_info (regnum
);
3988 else if (regnum
>= tdep
->FPP0_REGNUM
3989 && regnum
<= tdep
->FPP_LAST_REGNUM
)
3990 do_fpp_register_info (regnum
);
3992 else if (regnum
>= tdep
->R0_C_REGNUM
3993 && regnum
<= tdep
->R_LAST_C_REGNUM
)
3994 do_r_c_register_info (regnum
); /* FIXME, this function will not print the right format */
3996 else if (regnum
>= tdep
->FP0_C_REGNUM
3997 && regnum
<= tdep
->FP_LAST_C_REGNUM
)
3998 sh_do_fp_register (regnum
); /* this should work also for pseudoregs */
4000 else if (regnum
>= tdep
->PC_C_REGNUM
4001 && regnum
<= tdep
->FPUL_C_REGNUM
)
4002 do_cr_c_register_info (regnum
);
4007 sh_do_register (int regnum
)
4009 char raw_buffer
[MAX_REGISTER_RAW_SIZE
];
4011 fputs_filtered (REGISTER_NAME (regnum
), gdb_stdout
);
4012 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum
)), gdb_stdout
);
4014 /* Get the data in raw format. */
4015 if (!frame_register_read (deprecated_selected_frame
, regnum
, raw_buffer
))
4016 printf_filtered ("*value not available*\n");
4018 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4019 gdb_stdout
, 'x', 1, 0, Val_pretty_default
);
4020 printf_filtered ("\t");
4021 val_print (REGISTER_VIRTUAL_TYPE (regnum
), raw_buffer
, 0, 0,
4022 gdb_stdout
, 0, 1, 0, Val_pretty_default
);
4023 printf_filtered ("\n");
4027 sh_print_register (int regnum
)
4029 if (regnum
< 0 || regnum
>= NUM_REGS
+ NUM_PSEUDO_REGS
)
4030 internal_error (__FILE__
, __LINE__
,
4031 "Invalid register number %d\n", regnum
);
4033 else if (regnum
>= 0 && regnum
< NUM_REGS
)
4035 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4036 sh_do_fp_register (regnum
); /* FP regs */
4038 sh_do_register (regnum
); /* All other regs */
4041 else if (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4042 do_pseudo_register (regnum
);
4046 sh_do_registers_info (int regnum
, int fpregs
)
4048 if (regnum
!= -1) /* do one specified register */
4050 if (*(REGISTER_NAME (regnum
)) == '\0')
4051 error ("Not a valid register for the current processor type");
4053 sh_print_register (regnum
);
4056 /* do all (or most) registers */
4059 while (regnum
< NUM_REGS
)
4061 /* If the register name is empty, it is undefined for this
4062 processor, so don't display anything. */
4063 if (REGISTER_NAME (regnum
) == NULL
4064 || *(REGISTER_NAME (regnum
)) == '\0')
4070 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum
)) == TYPE_CODE_FLT
)
4074 /* true for "INFO ALL-REGISTERS" command */
4075 sh_do_fp_register (regnum
); /* FP regs */
4079 regnum
+= (gdbarch_tdep (current_gdbarch
)->FP_LAST_REGNUM
- FP0_REGNUM
); /* skip FP regs */
4083 sh_do_register (regnum
); /* All other regs */
4089 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4091 do_pseudo_register (regnum
);
4098 sh_compact_do_registers_info (int regnum
, int fpregs
)
4100 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4101 if (regnum
!= -1) /* do one specified register */
4103 if (*(REGISTER_NAME (regnum
)) == '\0')
4104 error ("Not a valid register for the current processor type");
4106 if (regnum
>= 0 && regnum
< tdep
->R0_C_REGNUM
)
4107 error ("Not a valid register for the current processor mode.");
4109 sh_print_register (regnum
);
4112 /* do all compact registers */
4114 regnum
= tdep
->R0_C_REGNUM
;
4115 while (regnum
< NUM_REGS
+ NUM_PSEUDO_REGS
)
4117 do_pseudo_register (regnum
);
4124 sh64_do_registers_info (int regnum
, int fpregs
)
4126 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame
)))
4127 sh_do_registers_info (regnum
, fpregs
);
4129 sh_compact_do_registers_info (regnum
, fpregs
);
4132 #ifdef SVR4_SHARED_LIBS
4134 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4135 for native i386 linux targets using the struct offsets defined in
4136 link.h (but without actual reference to that file).
4138 This makes it possible to access i386-linux shared libraries from
4139 a gdb that was not built on an i386-linux host (for cross debugging).
4142 struct link_map_offsets
*
4143 sh_linux_svr4_fetch_link_map_offsets (void)
4145 static struct link_map_offsets lmo
;
4146 static struct link_map_offsets
*lmp
= 0;
4152 lmo
.r_debug_size
= 8; /* 20 not actual size but all we need */
4154 lmo
.r_map_offset
= 4;
4157 lmo
.link_map_size
= 20; /* 552 not actual size but all we need */
4159 lmo
.l_addr_offset
= 0;
4160 lmo
.l_addr_size
= 4;
4162 lmo
.l_name_offset
= 4;
4163 lmo
.l_name_size
= 4;
4165 lmo
.l_next_offset
= 12;
4166 lmo
.l_next_size
= 4;
4168 lmo
.l_prev_offset
= 16;
4169 lmo
.l_prev_size
= 4;
4174 #endif /* SVR4_SHARED_LIBS */
4179 DSP_DSR_REGNUM
= 24,
4191 DSP_MOD_REGNUM
= 40,
4196 DSP_R0_BANK_REGNUM
= 51,
4197 DSP_R7_BANK_REGNUM
= DSP_R0_BANK_REGNUM
+ 7
4201 sh_dsp_register_sim_regno (int nr
)
4203 if (legacy_register_sim_regno (nr
) < 0)
4204 return legacy_register_sim_regno (nr
);
4205 if (nr
>= DSP_DSR_REGNUM
&& nr
< DSP_Y1_REGNUM
)
4206 return nr
- DSP_DSR_REGNUM
+ SIM_SH_DSR_REGNUM
;
4207 if (nr
== DSP_MOD_REGNUM
)
4208 return SIM_SH_MOD_REGNUM
;
4209 if (nr
== DSP_RS_REGNUM
)
4210 return SIM_SH_RS_REGNUM
;
4211 if (nr
== DSP_RE_REGNUM
)
4212 return SIM_SH_RE_REGNUM
;
4213 if (nr
>= DSP_R0_BANK_REGNUM
&& nr
<= DSP_R7_BANK_REGNUM
)
4214 return nr
- DSP_R0_BANK_REGNUM
+ SIM_SH_R0_BANK_REGNUM
;
4218 static gdbarch_init_ftype sh_gdbarch_init
;
4220 static struct gdbarch
*
4221 sh_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
4223 static LONGEST sh_call_dummy_words
[] = {0};
4224 struct gdbarch
*gdbarch
;
4225 struct gdbarch_tdep
*tdep
;
4226 gdbarch_register_name_ftype
*sh_register_name
;
4227 gdbarch_deprecated_store_return_value_ftype
*sh_store_return_value
;
4228 gdbarch_register_virtual_type_ftype
*sh_register_virtual_type
;
4230 /* If there is already a candidate, use it. */
4231 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
4233 return arches
->gdbarch
;
4235 /* None found, create a new architecture from the information
4237 tdep
= XMALLOC (struct gdbarch_tdep
);
4238 gdbarch
= gdbarch_alloc (&info
, tdep
);
4240 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
4241 ready to unwind the PC first (see frame.c:get_prev_frame()). */
4242 set_gdbarch_deprecated_init_frame_pc (gdbarch
, init_frame_pc_default
);
4244 /* Initialize the register numbers that are not common to all the
4245 variants to -1, if necessary thse will be overwritten in the case
4247 tdep
->FPUL_REGNUM
= -1;
4248 tdep
->FPSCR_REGNUM
= -1;
4249 tdep
->PR_REGNUM
= 17;
4250 tdep
->SR_REGNUM
= 22;
4251 tdep
->DSR_REGNUM
= -1;
4252 tdep
->FP_LAST_REGNUM
= -1;
4253 tdep
->A0G_REGNUM
= -1;
4254 tdep
->A0_REGNUM
= -1;
4255 tdep
->A1G_REGNUM
= -1;
4256 tdep
->A1_REGNUM
= -1;
4257 tdep
->M0_REGNUM
= -1;
4258 tdep
->M1_REGNUM
= -1;
4259 tdep
->X0_REGNUM
= -1;
4260 tdep
->X1_REGNUM
= -1;
4261 tdep
->Y0_REGNUM
= -1;
4262 tdep
->Y1_REGNUM
= -1;
4263 tdep
->MOD_REGNUM
= -1;
4264 tdep
->RS_REGNUM
= -1;
4265 tdep
->RE_REGNUM
= -1;
4266 tdep
->SSR_REGNUM
= -1;
4267 tdep
->SPC_REGNUM
= -1;
4268 tdep
->DR0_REGNUM
= -1;
4269 tdep
->DR_LAST_REGNUM
= -1;
4270 tdep
->FV0_REGNUM
= -1;
4271 tdep
->FV_LAST_REGNUM
= -1;
4272 tdep
->ARG0_REGNUM
= 4;
4273 tdep
->ARGLAST_REGNUM
= 7;
4274 tdep
->RETURN_REGNUM
= 0;
4275 tdep
->FLOAT_ARGLAST_REGNUM
= -1;
4277 tdep
->sh_abi
= SH_ABI_UNKNOWN
;
4279 set_gdbarch_fp0_regnum (gdbarch
, -1);
4280 set_gdbarch_num_pseudo_regs (gdbarch
, 0);
4281 set_gdbarch_max_register_raw_size (gdbarch
, 4);
4282 set_gdbarch_max_register_virtual_size (gdbarch
, 4);
4283 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4284 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4285 set_gdbarch_num_regs (gdbarch
, SH_DEFAULT_NUM_REGS
);
4286 set_gdbarch_sp_regnum (gdbarch
, 15);
4287 set_gdbarch_fp_regnum (gdbarch
, 14);
4288 set_gdbarch_pc_regnum (gdbarch
, 16);
4289 set_gdbarch_register_size (gdbarch
, 4);
4290 set_gdbarch_register_bytes (gdbarch
, SH_DEFAULT_NUM_REGS
* 4);
4291 set_gdbarch_deprecated_do_registers_info (gdbarch
, sh_do_registers_info
);
4292 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_breakpoint_from_pc
);
4293 set_gdbarch_frame_chain (gdbarch
, sh_frame_chain
);
4294 set_gdbarch_get_saved_register (gdbarch
, deprecated_generic_get_saved_register
);
4295 set_gdbarch_init_extra_frame_info (gdbarch
, sh_init_extra_frame_info
);
4296 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh_extract_return_value
);
4297 set_gdbarch_push_arguments (gdbarch
, sh_push_arguments
);
4298 set_gdbarch_store_struct_return (gdbarch
, sh_store_struct_return
);
4299 set_gdbarch_use_struct_convention (gdbarch
, sh_use_struct_convention
);
4300 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, sh_extract_struct_value_address
);
4301 set_gdbarch_pop_frame (gdbarch
, sh_pop_frame
);
4302 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_sh
);
4303 set_gdbarch_register_sim_regno (gdbarch
, legacy_register_sim_regno
);
4304 skip_prologue_hard_way
= sh_skip_prologue_hard_way
;
4305 do_pseudo_register
= sh_do_pseudo_register
;
4307 switch (info
.bfd_arch_info
->mach
)
4310 sh_register_name
= sh_sh_register_name
;
4311 sh_show_regs
= sh_generic_show_regs
;
4312 sh_store_return_value
= sh_default_store_return_value
;
4313 sh_register_virtual_type
= sh_default_register_virtual_type
;
4314 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4315 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4316 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4317 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4320 sh_register_name
= sh_sh_register_name
;
4321 sh_show_regs
= sh_generic_show_regs
;
4322 sh_store_return_value
= sh_default_store_return_value
;
4323 sh_register_virtual_type
= sh_default_register_virtual_type
;
4324 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4325 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4326 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4327 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4329 case bfd_mach_sh_dsp
:
4330 sh_register_name
= sh_sh_dsp_register_name
;
4331 sh_show_regs
= sh_dsp_show_regs
;
4332 sh_store_return_value
= sh_default_store_return_value
;
4333 sh_register_virtual_type
= sh_default_register_virtual_type
;
4334 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4335 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4336 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4337 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4338 set_gdbarch_register_sim_regno (gdbarch
, sh_dsp_register_sim_regno
);
4339 tdep
->DSR_REGNUM
= 24;
4340 tdep
->A0G_REGNUM
= 25;
4341 tdep
->A0_REGNUM
= 26;
4342 tdep
->A1G_REGNUM
= 27;
4343 tdep
->A1_REGNUM
= 28;
4344 tdep
->M0_REGNUM
= 29;
4345 tdep
->M1_REGNUM
= 30;
4346 tdep
->X0_REGNUM
= 31;
4347 tdep
->X1_REGNUM
= 32;
4348 tdep
->Y0_REGNUM
= 33;
4349 tdep
->Y1_REGNUM
= 34;
4350 tdep
->MOD_REGNUM
= 40;
4351 tdep
->RS_REGNUM
= 43;
4352 tdep
->RE_REGNUM
= 44;
4355 sh_register_name
= sh_sh3_register_name
;
4356 sh_show_regs
= sh3_show_regs
;
4357 sh_store_return_value
= sh_default_store_return_value
;
4358 sh_register_virtual_type
= sh_default_register_virtual_type
;
4359 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4360 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4361 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4362 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4363 tdep
->SSR_REGNUM
= 41;
4364 tdep
->SPC_REGNUM
= 42;
4367 sh_register_name
= sh_sh3e_register_name
;
4368 sh_show_regs
= sh3e_show_regs
;
4369 sh_store_return_value
= sh3e_sh4_store_return_value
;
4370 sh_register_virtual_type
= sh_sh3e_register_virtual_type
;
4371 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4372 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4373 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4374 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4375 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4376 set_gdbarch_fp0_regnum (gdbarch
, 25);
4377 tdep
->FPUL_REGNUM
= 23;
4378 tdep
->FPSCR_REGNUM
= 24;
4379 tdep
->FP_LAST_REGNUM
= 40;
4380 tdep
->SSR_REGNUM
= 41;
4381 tdep
->SPC_REGNUM
= 42;
4383 case bfd_mach_sh3_dsp
:
4384 sh_register_name
= sh_sh3_dsp_register_name
;
4385 sh_show_regs
= sh3_dsp_show_regs
;
4386 sh_store_return_value
= sh_default_store_return_value
;
4387 sh_register_virtual_type
= sh_default_register_virtual_type
;
4388 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4389 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4390 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4391 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4392 tdep
->DSR_REGNUM
= 24;
4393 tdep
->A0G_REGNUM
= 25;
4394 tdep
->A0_REGNUM
= 26;
4395 tdep
->A1G_REGNUM
= 27;
4396 tdep
->A1_REGNUM
= 28;
4397 tdep
->M0_REGNUM
= 29;
4398 tdep
->M1_REGNUM
= 30;
4399 tdep
->X0_REGNUM
= 31;
4400 tdep
->X1_REGNUM
= 32;
4401 tdep
->Y0_REGNUM
= 33;
4402 tdep
->Y1_REGNUM
= 34;
4403 tdep
->MOD_REGNUM
= 40;
4404 tdep
->RS_REGNUM
= 43;
4405 tdep
->RE_REGNUM
= 44;
4406 tdep
->SSR_REGNUM
= 41;
4407 tdep
->SPC_REGNUM
= 42;
4410 sh_register_name
= sh_sh4_register_name
;
4411 sh_show_regs
= sh4_show_regs
;
4412 sh_store_return_value
= sh3e_sh4_store_return_value
;
4413 sh_register_virtual_type
= sh_sh4_register_virtual_type
;
4414 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_fp_frame_init_saved_regs
);
4415 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh3e_sh4_extract_return_value
);
4416 set_gdbarch_fp0_regnum (gdbarch
, 25);
4417 set_gdbarch_register_raw_size (gdbarch
, sh_sh4_register_raw_size
);
4418 set_gdbarch_register_virtual_size (gdbarch
, sh_sh4_register_raw_size
);
4419 set_gdbarch_register_byte (gdbarch
, sh_sh4_register_byte
);
4420 set_gdbarch_num_pseudo_regs (gdbarch
, 12);
4421 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4422 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4423 set_gdbarch_pseudo_register_read (gdbarch
, sh_pseudo_register_read
);
4424 set_gdbarch_pseudo_register_write (gdbarch
, sh_pseudo_register_write
);
4425 tdep
->FPUL_REGNUM
= 23;
4426 tdep
->FPSCR_REGNUM
= 24;
4427 tdep
->FP_LAST_REGNUM
= 40;
4428 tdep
->SSR_REGNUM
= 41;
4429 tdep
->SPC_REGNUM
= 42;
4430 tdep
->DR0_REGNUM
= 59;
4431 tdep
->DR_LAST_REGNUM
= 66;
4432 tdep
->FV0_REGNUM
= 67;
4433 tdep
->FV_LAST_REGNUM
= 70;
4436 tdep
->PR_REGNUM
= 18;
4437 tdep
->SR_REGNUM
= 65;
4438 tdep
->FPSCR_REGNUM
= SIM_SH64_FPCSR_REGNUM
;
4439 tdep
->FP_LAST_REGNUM
= SIM_SH64_FR0_REGNUM
+ SIM_SH64_NR_FP_REGS
- 1;
4440 tdep
->SSR_REGNUM
= SIM_SH64_SSR_REGNUM
;
4441 tdep
->SPC_REGNUM
= SIM_SH64_SPC_REGNUM
;
4442 tdep
->TR7_REGNUM
= SIM_SH64_TR0_REGNUM
+ 7;
4443 tdep
->FPP0_REGNUM
= 173;
4444 tdep
->FPP_LAST_REGNUM
= 204;
4445 tdep
->DR0_REGNUM
= 141;
4446 tdep
->DR_LAST_REGNUM
= 172;
4447 tdep
->FV0_REGNUM
= 205;
4448 tdep
->FV_LAST_REGNUM
= 220;
4449 tdep
->R0_C_REGNUM
= 221;
4450 tdep
->R_LAST_C_REGNUM
= 236;
4451 tdep
->PC_C_REGNUM
= 237;
4452 tdep
->GBR_C_REGNUM
= 238;
4453 tdep
->MACH_C_REGNUM
= 239;
4454 tdep
->MACL_C_REGNUM
= 240;
4455 tdep
->PR_C_REGNUM
= 241;
4456 tdep
->T_C_REGNUM
= 242;
4457 tdep
->FPSCR_C_REGNUM
= 243;
4458 tdep
->FPUL_C_REGNUM
= 244;
4459 tdep
->FP0_C_REGNUM
= 245;
4460 tdep
->FP_LAST_C_REGNUM
= 260;
4461 tdep
->DR0_C_REGNUM
= 261;
4462 tdep
->DR_LAST_C_REGNUM
= 268;
4463 tdep
->FV0_C_REGNUM
= 269;
4464 tdep
->FV_LAST_C_REGNUM
= 272;
4465 tdep
->ARG0_REGNUM
= 2;
4466 tdep
->ARGLAST_REGNUM
= 9;
4467 tdep
->RETURN_REGNUM
= 2;
4468 tdep
->FLOAT_ARGLAST_REGNUM
= 11;
4470 set_gdbarch_num_pseudo_regs (gdbarch
, NUM_PSEUDO_REGS_SH_MEDIA
+ NUM_PSEUDO_REGS_SH_COMPACT
);
4471 set_gdbarch_fp0_regnum (gdbarch
, SIM_SH64_FR0_REGNUM
);
4472 set_gdbarch_pc_regnum (gdbarch
, 64);
4474 /* Determine the ABI */
4475 if (bfd_get_arch_size (info
.abfd
) == 64)
4477 /* If the ABI is the 64-bit one, it can only be sh-media. */
4478 tdep
->sh_abi
= SH_ABI_64
;
4479 set_gdbarch_ptr_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4480 set_gdbarch_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4484 /* If the ABI is the 32-bit one it could be either media or
4486 tdep
->sh_abi
= SH_ABI_32
;
4487 set_gdbarch_ptr_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4488 set_gdbarch_long_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4491 /* the number of real registers is the same whether we are in
4492 ISA16(compact) or ISA32(media). */
4493 set_gdbarch_num_regs (gdbarch
, SIM_SH64_NR_REGS
);
4494 set_gdbarch_register_size (gdbarch
, 8); /*????*/
4495 set_gdbarch_register_bytes (gdbarch
,
4496 ((SIM_SH64_NR_FP_REGS
+ 1) * 4)
4497 + (SIM_SH64_NR_REGS
- SIM_SH64_NR_FP_REGS
-1) * 8);
4499 sh_register_name
= sh_sh64_register_name
;
4500 sh_show_regs
= sh64_show_regs
;
4501 sh_register_virtual_type
= sh_sh64_register_virtual_type
;
4502 sh_store_return_value
= sh64_store_return_value
;
4503 skip_prologue_hard_way
= sh64_skip_prologue_hard_way
;
4504 do_pseudo_register
= sh64_do_pseudo_register
;
4505 set_gdbarch_register_raw_size (gdbarch
, sh_sh64_register_raw_size
);
4506 set_gdbarch_register_virtual_size (gdbarch
, sh_sh64_register_raw_size
);
4507 set_gdbarch_register_byte (gdbarch
, sh_sh64_register_byte
);
4508 /* This seems awfully wrong!*/
4509 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4510 /* should include the size of the pseudo regs. */
4511 set_gdbarch_max_register_raw_size (gdbarch
, 4 * 4);
4512 /* Or should that go in the virtual_size? */
4513 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4514 set_gdbarch_max_register_virtual_size (gdbarch
, 4 * 4);
4515 set_gdbarch_pseudo_register_read (gdbarch
, sh64_pseudo_register_read
);
4516 set_gdbarch_pseudo_register_write (gdbarch
, sh64_pseudo_register_write
);
4518 set_gdbarch_deprecated_do_registers_info (gdbarch
, sh64_do_registers_info
);
4519 set_gdbarch_frame_init_saved_regs (gdbarch
, sh64_nofp_frame_init_saved_regs
);
4520 set_gdbarch_breakpoint_from_pc (gdbarch
, sh_sh64_breakpoint_from_pc
);
4521 set_gdbarch_init_extra_frame_info (gdbarch
, sh64_init_extra_frame_info
);
4522 set_gdbarch_frame_chain (gdbarch
, sh64_frame_chain
);
4523 set_gdbarch_get_saved_register (gdbarch
, sh64_get_saved_register
);
4524 set_gdbarch_deprecated_extract_return_value (gdbarch
, sh64_extract_return_value
);
4525 set_gdbarch_push_arguments (gdbarch
, sh64_push_arguments
);
4526 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
4527 set_gdbarch_deprecated_extract_struct_value_address (gdbarch
, sh64_extract_struct_value_address
);
4528 set_gdbarch_use_struct_convention (gdbarch
, sh64_use_struct_convention
);
4529 set_gdbarch_pop_frame (gdbarch
, sh64_pop_frame
);
4530 set_gdbarch_elf_make_msymbol_special (gdbarch
,
4531 sh64_elf_make_msymbol_special
);
4534 sh_register_name
= sh_generic_register_name
;
4535 sh_show_regs
= sh_generic_show_regs
;
4536 sh_store_return_value
= sh_default_store_return_value
;
4537 sh_register_virtual_type
= sh_default_register_virtual_type
;
4538 set_gdbarch_frame_init_saved_regs (gdbarch
, sh_nofp_frame_init_saved_regs
);
4539 set_gdbarch_register_raw_size (gdbarch
, sh_default_register_raw_size
);
4540 set_gdbarch_register_virtual_size (gdbarch
, sh_default_register_raw_size
);
4541 set_gdbarch_register_byte (gdbarch
, sh_default_register_byte
);
4545 set_gdbarch_read_pc (gdbarch
, generic_target_read_pc
);
4546 set_gdbarch_write_pc (gdbarch
, generic_target_write_pc
);
4547 set_gdbarch_read_fp (gdbarch
, generic_target_read_fp
);
4548 set_gdbarch_read_sp (gdbarch
, generic_target_read_sp
);
4549 set_gdbarch_write_sp (gdbarch
, generic_target_write_sp
);
4551 set_gdbarch_register_name (gdbarch
, sh_register_name
);
4552 set_gdbarch_register_virtual_type (gdbarch
, sh_register_virtual_type
);
4554 set_gdbarch_short_bit (gdbarch
, 2 * TARGET_CHAR_BIT
);
4555 set_gdbarch_int_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4556 set_gdbarch_long_long_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4557 set_gdbarch_float_bit (gdbarch
, 4 * TARGET_CHAR_BIT
);
4558 set_gdbarch_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4559 set_gdbarch_long_double_bit (gdbarch
, 8 * TARGET_CHAR_BIT
);
4561 set_gdbarch_call_dummy_length (gdbarch
, 0);
4562 set_gdbarch_call_dummy_address (gdbarch
, entry_point_address
);
4563 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch
, 1); /*???*/
4564 set_gdbarch_call_dummy_breakpoint_offset (gdbarch
, 0);
4565 set_gdbarch_call_dummy_start_offset (gdbarch
, 0);
4566 set_gdbarch_call_dummy_words (gdbarch
, sh_call_dummy_words
);
4567 set_gdbarch_sizeof_call_dummy_words (gdbarch
, sizeof (sh_call_dummy_words
));
4568 set_gdbarch_call_dummy_p (gdbarch
, 1);
4569 set_gdbarch_call_dummy_stack_adjust_p (gdbarch
, 0);
4570 set_gdbarch_fix_call_dummy (gdbarch
, generic_fix_call_dummy
);
4572 set_gdbarch_push_dummy_frame (gdbarch
, generic_push_dummy_frame
);
4573 set_gdbarch_push_return_address (gdbarch
, sh_push_return_address
);
4575 set_gdbarch_deprecated_store_return_value (gdbarch
, sh_store_return_value
);
4576 set_gdbarch_skip_prologue (gdbarch
, sh_skip_prologue
);
4577 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
4578 set_gdbarch_decr_pc_after_break (gdbarch
, 0);
4579 set_gdbarch_function_start_offset (gdbarch
, 0);
4581 set_gdbarch_frame_args_skip (gdbarch
, 0);
4582 set_gdbarch_frameless_function_invocation (gdbarch
, frameless_look_for_prologue
);
4583 set_gdbarch_frame_saved_pc (gdbarch
, sh_frame_saved_pc
);
4584 set_gdbarch_saved_pc_after_call (gdbarch
, sh_saved_pc_after_call
);
4585 set_gdbarch_frame_num_args (gdbarch
, frame_num_args_unknown
);
4586 set_gdbarch_believe_pcc_promotion (gdbarch
, 1);
4588 /* Hook in ABI-specific overrides, if they have been registered. */
4589 gdbarch_init_osabi (info
, gdbarch
);
4595 sh_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
4597 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4602 /* FIXME: dump the rest of gdbarch_tdep. */
4606 _initialize_sh_tdep (void)
4608 struct cmd_list_element
*c
;
4610 gdbarch_register (bfd_arch_sh
, sh_gdbarch_init
, sh_dump_tdep
);
4612 add_com ("regs", class_vars
, sh_show_regs_command
, "Print all registers");