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[deliverable/binutils-gdb.git] / gdb / sh-tdep.c
1 /* Target-dependent code for Renesas Super-H, for GDB.
2
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
5
6 This file is part of GDB.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20
21 /*
22 Contributed by Steve Chamberlain
23 sac@cygnus.com
24 */
25
26 #include "defs.h"
27 #include "frame.h"
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
31 #include "symtab.h"
32 #include "gdbtypes.h"
33 #include "gdbcmd.h"
34 #include "gdbcore.h"
35 #include "value.h"
36 #include "dis-asm.h"
37 #include "inferior.h"
38 #include "gdb_string.h"
39 #include "gdb_assert.h"
40 #include "arch-utils.h"
41 #include "floatformat.h"
42 #include "regcache.h"
43 #include "doublest.h"
44 #include "osabi.h"
45 #include "reggroups.h"
46
47 #include "sh-tdep.h"
48
49 #include "elf-bfd.h"
50 #include "solib-svr4.h"
51
52 /* sh flags */
53 #include "elf/sh.h"
54 /* registers numbers shared with the simulator */
55 #include "gdb/sim-sh.h"
56
57 static void (*sh_show_regs) (struct frame_info *);
58
59 #define SH_NUM_REGS 67
60
61 struct sh_frame_cache
62 {
63 /* Base address. */
64 CORE_ADDR base;
65 LONGEST sp_offset;
66 CORE_ADDR pc;
67
68 /* Flag showing that a frame has been created in the prologue code. */
69 int uses_fp;
70
71 /* Saved registers. */
72 CORE_ADDR saved_regs[SH_NUM_REGS];
73 CORE_ADDR saved_sp;
74 };
75
76 static const char *
77 sh_sh_register_name (int reg_nr)
78 {
79 static char *register_names[] = {
80 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
81 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
82 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
83 "", "",
84 "", "", "", "", "", "", "", "",
85 "", "", "", "", "", "", "", "",
86 "", "",
87 "", "", "", "", "", "", "", "",
88 "", "", "", "", "", "", "", "",
89 "", "", "", "", "", "", "", "",
90 };
91 if (reg_nr < 0)
92 return NULL;
93 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return NULL;
95 return register_names[reg_nr];
96 }
97
98 static const char *
99 sh_sh3_register_name (int reg_nr)
100 {
101 static char *register_names[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
108 "ssr", "spc",
109 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
110 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
111 "", "", "", "", "", "", "", "",
112 };
113 if (reg_nr < 0)
114 return NULL;
115 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
116 return NULL;
117 return register_names[reg_nr];
118 }
119
120 static const char *
121 sh_sh3e_register_name (int reg_nr)
122 {
123 static char *register_names[] = {
124 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
125 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
126 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
127 "fpul", "fpscr",
128 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
129 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
130 "ssr", "spc",
131 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
132 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
133 "", "", "", "", "", "", "", "",
134 };
135 if (reg_nr < 0)
136 return NULL;
137 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
138 return NULL;
139 return register_names[reg_nr];
140 }
141
142 static const char *
143 sh_sh2e_register_name (int reg_nr)
144 {
145 static char *register_names[] = {
146 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
147 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
148 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
149 "fpul", "fpscr",
150 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
151 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
152 "", "",
153 "", "", "", "", "", "", "", "",
154 "", "", "", "", "", "", "", "",
155 "", "", "", "", "", "", "", "",
156 };
157 if (reg_nr < 0)
158 return NULL;
159 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
160 return NULL;
161 return register_names[reg_nr];
162 }
163
164 static const char *
165 sh_sh2a_register_name (int reg_nr)
166 {
167 static char *register_names[] = {
168 /* general registers 0-15 */
169 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
170 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
171 /* 16 - 22 */
172 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
173 /* 23, 24 */
174 "fpul", "fpscr",
175 /* floating point registers 25 - 40 */
176 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
177 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
178 /* 41, 42 */
179 "", "",
180 /* 43 - 62. Banked registers. The bank number used is determined by
181 the bank register (63). */
182 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
183 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
184 "machb", "ivnb", "prb", "gbrb", "maclb",
185 /* 63: register bank number, not a real register but used to
186 communicate the register bank currently get/set. This register
187 is hidden to the user, who manipulates it using the pseudo
188 register called "bank" (67). See below. */
189 "",
190 /* 64 - 66 */
191 "ibcr", "ibnr", "tbr",
192 /* 67: register bank number, the user visible pseudo register. */
193 "bank",
194 /* double precision (pseudo) 68 - 75 */
195 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
196 };
197 if (reg_nr < 0)
198 return NULL;
199 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return NULL;
201 return register_names[reg_nr];
202 }
203
204 static const char *
205 sh_sh2a_nofpu_register_name (int reg_nr)
206 {
207 static char *register_names[] = {
208 /* general registers 0-15 */
209 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
210 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
211 /* 16 - 22 */
212 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
213 /* 23, 24 */
214 "", "",
215 /* floating point registers 25 - 40 */
216 "", "", "", "", "", "", "", "",
217 "", "", "", "", "", "", "", "",
218 /* 41, 42 */
219 "", "",
220 /* 43 - 62. Banked registers. The bank number used is determined by
221 the bank register (63). */
222 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
223 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
224 "machb", "ivnb", "prb", "gbrb", "maclb",
225 /* 63: register bank number, not a real register but used to
226 communicate the register bank currently get/set. This register
227 is hidden to the user, who manipulates it using the pseudo
228 register called "bank" (67). See below. */
229 "",
230 /* 64 - 66 */
231 "ibcr", "ibnr", "tbr",
232 /* 67: register bank number, the user visible pseudo register. */
233 "bank",
234 /* double precision (pseudo) 68 - 75 */
235 "", "", "", "", "", "", "", "",
236 };
237 if (reg_nr < 0)
238 return NULL;
239 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
240 return NULL;
241 return register_names[reg_nr];
242 }
243
244 static const char *
245 sh_sh_dsp_register_name (int reg_nr)
246 {
247 static char *register_names[] = {
248 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
249 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
250 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
251 "", "dsr",
252 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
253 "y0", "y1", "", "", "", "", "", "mod",
254 "", "",
255 "rs", "re", "", "", "", "", "", "",
256 "", "", "", "", "", "", "", "",
257 "", "", "", "", "", "", "", "",
258 };
259 if (reg_nr < 0)
260 return NULL;
261 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
262 return NULL;
263 return register_names[reg_nr];
264 }
265
266 static const char *
267 sh_sh3_dsp_register_name (int reg_nr)
268 {
269 static char *register_names[] = {
270 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
271 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
272 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
273 "", "dsr",
274 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
275 "y0", "y1", "", "", "", "", "", "mod",
276 "ssr", "spc",
277 "rs", "re", "", "", "", "", "", "",
278 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "",
281 };
282 if (reg_nr < 0)
283 return NULL;
284 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
285 return NULL;
286 return register_names[reg_nr];
287 }
288
289 static const char *
290 sh_sh4_register_name (int reg_nr)
291 {
292 static char *register_names[] = {
293 /* general registers 0-15 */
294 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
295 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
296 /* 16 - 22 */
297 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
298 /* 23, 24 */
299 "fpul", "fpscr",
300 /* floating point registers 25 - 40 */
301 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
302 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
303 /* 41, 42 */
304 "ssr", "spc",
305 /* bank 0 43 - 50 */
306 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
307 /* bank 1 51 - 58 */
308 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
309 "", "", "", "", "", "", "", "",
310 /* pseudo bank register. */
311 "",
312 /* double precision (pseudo) 59 - 66 */
313 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
314 /* vectors (pseudo) 67 - 70 */
315 "fv0", "fv4", "fv8", "fv12",
316 /* FIXME: missing XF 71 - 86 */
317 /* FIXME: missing XD 87 - 94 */
318 };
319 if (reg_nr < 0)
320 return NULL;
321 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
322 return NULL;
323 return register_names[reg_nr];
324 }
325
326 static const char *
327 sh_sh4_nofpu_register_name (int reg_nr)
328 {
329 static char *register_names[] = {
330 /* general registers 0-15 */
331 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
332 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
333 /* 16 - 22 */
334 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
335 /* 23, 24 */
336 "", "",
337 /* floating point registers 25 - 40 -- not for nofpu target */
338 "", "", "", "", "", "", "", "",
339 "", "", "", "", "", "", "", "",
340 /* 41, 42 */
341 "ssr", "spc",
342 /* bank 0 43 - 50 */
343 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
344 /* bank 1 51 - 58 */
345 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
346 "", "", "", "", "", "", "", "",
347 /* pseudo bank register. */
348 "",
349 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
350 "", "", "", "", "", "", "", "",
351 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
352 "", "", "", "",
353 };
354 if (reg_nr < 0)
355 return NULL;
356 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
357 return NULL;
358 return register_names[reg_nr];
359 }
360
361 static const char *
362 sh_sh4al_dsp_register_name (int reg_nr)
363 {
364 static char *register_names[] = {
365 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
366 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
367 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
368 "", "dsr",
369 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
370 "y0", "y1", "", "", "", "", "", "mod",
371 "ssr", "spc",
372 "rs", "re", "", "", "", "", "", "",
373 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
374 "", "", "", "", "", "", "", "",
375 "", "", "", "", "", "", "", "",
376 };
377 if (reg_nr < 0)
378 return NULL;
379 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
380 return NULL;
381 return register_names[reg_nr];
382 }
383
384 static const unsigned char *
385 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
386 {
387 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
388 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
389
390 /* For remote stub targets, trapa #20 is used. */
391 if (strcmp (target_shortname, "remote") == 0)
392 {
393 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
394 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
395
396 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
397 {
398 *lenptr = sizeof (big_remote_breakpoint);
399 return big_remote_breakpoint;
400 }
401 else
402 {
403 *lenptr = sizeof (little_remote_breakpoint);
404 return little_remote_breakpoint;
405 }
406 }
407
408 *lenptr = sizeof (breakpoint);
409 return breakpoint;
410 }
411
412 /* Prologue looks like
413 mov.l r14,@-r15
414 sts.l pr,@-r15
415 mov.l <regs>,@-r15
416 sub <room_for_loca_vars>,r15
417 mov r15,r14
418
419 Actually it can be more complicated than this but that's it, basically.
420 */
421
422 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
423 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
424
425 /* JSR @Rm 0100mmmm00001011 */
426 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
427
428 /* STS.L PR,@-r15 0100111100100010
429 r15-4-->r15, PR-->(r15) */
430 #define IS_STS(x) ((x) == 0x4f22)
431
432 /* STS.L MACL,@-r15 0100111100010010
433 r15-4-->r15, MACL-->(r15) */
434 #define IS_MACL_STS(x) ((x) == 0x4f12)
435
436 /* MOV.L Rm,@-r15 00101111mmmm0110
437 r15-4-->r15, Rm-->(R15) */
438 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
439
440 /* MOV r15,r14 0110111011110011
441 r15-->r14 */
442 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
443
444 /* ADD #imm,r15 01111111iiiiiiii
445 r15+imm-->r15 */
446 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
447
448 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
449 #define IS_SHLL_R3(x) ((x) == 0x4300)
450
451 /* ADD r3,r15 0011111100111100
452 r15+r3-->r15 */
453 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
454
455 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
456 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
457 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
458 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
459 make this entirely clear. */
460 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
461 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
462
463 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
464 #define IS_MOV_ARG_TO_REG(x) \
465 (((x) & 0xf00f) == 0x6003 && \
466 ((x) & 0x00f0) >= 0x0040 && \
467 ((x) & 0x00f0) <= 0x0070)
468 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
469 #define IS_MOV_ARG_TO_IND_R14(x) \
470 (((x) & 0xff0f) == 0x2e02 && \
471 ((x) & 0x00f0) >= 0x0040 && \
472 ((x) & 0x00f0) <= 0x0070)
473 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
474 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
475 (((x) & 0xff00) == 0x1e00 && \
476 ((x) & 0x00f0) >= 0x0040 && \
477 ((x) & 0x00f0) <= 0x0070)
478
479 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
480 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
481 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
482 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
483 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
484 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
485 /* SUB Rn,R15 00111111nnnn1000 */
486 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
487
488 #define FPSCR_SZ (1 << 20)
489
490 /* The following instructions are used for epilogue testing. */
491 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
492 #define IS_RTS(x) ((x) == 0x000b)
493 #define IS_LDS(x) ((x) == 0x4f26)
494 #define IS_MACL_LDS(x) ((x) == 0x4f16)
495 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
496 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
497 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
498
499 /* Disassemble an instruction. */
500 static int
501 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
502 {
503 info->endian = gdbarch_byte_order (current_gdbarch);
504 return print_insn_sh (memaddr, info);
505 }
506
507 static CORE_ADDR
508 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
509 struct sh_frame_cache *cache, ULONGEST fpscr)
510 {
511 ULONGEST inst;
512 CORE_ADDR opc;
513 int offset;
514 int sav_offset = 0;
515 int r3_val = 0;
516 int reg, sav_reg = -1;
517
518 if (pc >= current_pc)
519 return current_pc;
520
521 cache->uses_fp = 0;
522 for (opc = pc + (2 * 28); pc < opc; pc += 2)
523 {
524 inst = read_memory_unsigned_integer (pc, 2);
525 /* See where the registers will be saved to */
526 if (IS_PUSH (inst))
527 {
528 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
529 cache->sp_offset += 4;
530 }
531 else if (IS_STS (inst))
532 {
533 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
534 cache->sp_offset += 4;
535 }
536 else if (IS_MACL_STS (inst))
537 {
538 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
539 cache->sp_offset += 4;
540 }
541 else if (IS_MOV_R3 (inst))
542 {
543 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
544 }
545 else if (IS_SHLL_R3 (inst))
546 {
547 r3_val <<= 1;
548 }
549 else if (IS_ADD_R3SP (inst))
550 {
551 cache->sp_offset += -r3_val;
552 }
553 else if (IS_ADD_IMM_SP (inst))
554 {
555 offset = ((inst & 0xff) ^ 0x80) - 0x80;
556 cache->sp_offset -= offset;
557 }
558 else if (IS_MOVW_PCREL_TO_REG (inst))
559 {
560 if (sav_reg < 0)
561 {
562 reg = GET_TARGET_REG (inst);
563 if (reg < 14)
564 {
565 sav_reg = reg;
566 offset = (inst & 0xff) << 1;
567 sav_offset =
568 read_memory_integer ((pc + 4) + offset, 2);
569 }
570 }
571 }
572 else if (IS_MOVL_PCREL_TO_REG (inst))
573 {
574 if (sav_reg < 0)
575 {
576 reg = GET_TARGET_REG (inst);
577 if (reg < 14)
578 {
579 sav_reg = reg;
580 offset = (inst & 0xff) << 2;
581 sav_offset =
582 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
583 }
584 }
585 }
586 else if (IS_MOVI20 (inst))
587 {
588 if (sav_reg < 0)
589 {
590 reg = GET_TARGET_REG (inst);
591 if (reg < 14)
592 {
593 sav_reg = reg;
594 sav_offset = GET_SOURCE_REG (inst) << 16;
595 /* MOVI20 is a 32 bit instruction! */
596 pc += 2;
597 sav_offset |= read_memory_unsigned_integer (pc, 2);
598 /* Now sav_offset contains an unsigned 20 bit value.
599 It must still get sign extended. */
600 if (sav_offset & 0x00080000)
601 sav_offset |= 0xfff00000;
602 }
603 }
604 }
605 else if (IS_SUB_REG_FROM_SP (inst))
606 {
607 reg = GET_SOURCE_REG (inst);
608 if (sav_reg > 0 && reg == sav_reg)
609 {
610 sav_reg = -1;
611 }
612 cache->sp_offset += sav_offset;
613 }
614 else if (IS_FPUSH (inst))
615 {
616 if (fpscr & FPSCR_SZ)
617 {
618 cache->sp_offset += 8;
619 }
620 else
621 {
622 cache->sp_offset += 4;
623 }
624 }
625 else if (IS_MOV_SP_FP (inst))
626 {
627 cache->uses_fp = 1;
628 /* At this point, only allow argument register moves to other
629 registers or argument register moves to @(X,fp) which are
630 moving the register arguments onto the stack area allocated
631 by a former add somenumber to SP call. Don't allow moving
632 to an fp indirect address above fp + cache->sp_offset. */
633 pc += 2;
634 for (opc = pc + 12; pc < opc; pc += 2)
635 {
636 inst = read_memory_integer (pc, 2);
637 if (IS_MOV_ARG_TO_IND_R14 (inst))
638 {
639 reg = GET_SOURCE_REG (inst);
640 if (cache->sp_offset > 0)
641 cache->saved_regs[reg] = cache->sp_offset;
642 }
643 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
644 {
645 reg = GET_SOURCE_REG (inst);
646 offset = (inst & 0xf) * 4;
647 if (cache->sp_offset > offset)
648 cache->saved_regs[reg] = cache->sp_offset - offset;
649 }
650 else if (IS_MOV_ARG_TO_REG (inst))
651 continue;
652 else
653 break;
654 }
655 break;
656 }
657 else if (IS_JSR (inst))
658 {
659 /* We have found a jsr that has been scheduled into the prologue.
660 If we continue the scan and return a pc someplace after this,
661 then setting a breakpoint on this function will cause it to
662 appear to be called after the function it is calling via the
663 jsr, which will be very confusing. Most likely the next
664 instruction is going to be IS_MOV_SP_FP in the delay slot. If
665 so, note that before returning the current pc. */
666 inst = read_memory_integer (pc + 2, 2);
667 if (IS_MOV_SP_FP (inst))
668 cache->uses_fp = 1;
669 break;
670 }
671 #if 0 /* This used to just stop when it found an instruction that
672 was not considered part of the prologue. Now, we just
673 keep going looking for likely instructions. */
674 else
675 break;
676 #endif
677 }
678
679 return pc;
680 }
681
682 /* Skip any prologue before the guts of a function */
683
684 /* Skip the prologue using the debug information. If this fails we'll
685 fall back on the 'guess' method below. */
686 static CORE_ADDR
687 after_prologue (CORE_ADDR pc)
688 {
689 struct symtab_and_line sal;
690 CORE_ADDR func_addr, func_end;
691
692 /* If we can not find the symbol in the partial symbol table, then
693 there is no hope we can determine the function's start address
694 with this code. */
695 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
696 return 0;
697
698 /* Get the line associated with FUNC_ADDR. */
699 sal = find_pc_line (func_addr, 0);
700
701 /* There are only two cases to consider. First, the end of the source line
702 is within the function bounds. In that case we return the end of the
703 source line. Second is the end of the source line extends beyond the
704 bounds of the current function. We need to use the slow code to
705 examine instructions in that case. */
706 if (sal.end < func_end)
707 return sal.end;
708 else
709 return 0;
710 }
711
712 static CORE_ADDR
713 sh_skip_prologue (CORE_ADDR start_pc)
714 {
715 CORE_ADDR pc;
716 struct sh_frame_cache cache;
717
718 /* See if we can determine the end of the prologue via the symbol table.
719 If so, then return either PC, or the PC after the prologue, whichever
720 is greater. */
721 pc = after_prologue (start_pc);
722
723 /* If after_prologue returned a useful address, then use it. Else
724 fall back on the instruction skipping code. */
725 if (pc)
726 return max (pc, start_pc);
727
728 cache.sp_offset = -4;
729 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache, 0);
730 if (!cache.uses_fp)
731 return start_pc;
732
733 return pc;
734 }
735
736 /* The ABI says:
737
738 Aggregate types not bigger than 8 bytes that have the same size and
739 alignment as one of the integer scalar types are returned in the
740 same registers as the integer type they match.
741
742 For example, a 2-byte aligned structure with size 2 bytes has the
743 same size and alignment as a short int, and will be returned in R0.
744 A 4-byte aligned structure with size 8 bytes has the same size and
745 alignment as a long long int, and will be returned in R0 and R1.
746
747 When an aggregate type is returned in R0 and R1, R0 contains the
748 first four bytes of the aggregate, and R1 contains the
749 remainder. If the size of the aggregate type is not a multiple of 4
750 bytes, the aggregate is tail-padded up to a multiple of 4
751 bytes. The value of the padding is undefined. For little-endian
752 targets the padding will appear at the most significant end of the
753 last element, for big-endian targets the padding appears at the
754 least significant end of the last element.
755
756 All other aggregate types are returned by address. The caller
757 function passes the address of an area large enough to hold the
758 aggregate value in R2. The called function stores the result in
759 this location.
760
761 To reiterate, structs smaller than 8 bytes could also be returned
762 in memory, if they don't pass the "same size and alignment as an
763 integer type" rule.
764
765 For example, in
766
767 struct s { char c[3]; } wibble;
768 struct s foo(void) { return wibble; }
769
770 the return value from foo() will be in memory, not
771 in R0, because there is no 3-byte integer type.
772
773 Similarly, in
774
775 struct s { char c[2]; } wibble;
776 struct s foo(void) { return wibble; }
777
778 because a struct containing two chars has alignment 1, that matches
779 type char, but size 2, that matches type short. There's no integer
780 type that has alignment 1 and size 2, so the struct is returned in
781 memory.
782
783 */
784
785 static int
786 sh_use_struct_convention (int gcc_p, struct type *type)
787 {
788 int len = TYPE_LENGTH (type);
789 int nelem = TYPE_NFIELDS (type);
790
791 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
792 fit in two registers anyway) use struct convention. */
793 if (len != 1 && len != 2 && len != 4 && len != 8)
794 return 1;
795
796 /* Scalar types and aggregate types with exactly one field are aligned
797 by definition. They are returned in registers. */
798 if (nelem <= 1)
799 return 0;
800
801 /* If the first field in the aggregate has the same length as the entire
802 aggregate type, the type is returned in registers. */
803 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
804 return 0;
805
806 /* If the size of the aggregate is 8 bytes and the first field is
807 of size 4 bytes its alignment is equal to long long's alignment,
808 so it's returned in registers. */
809 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
810 return 0;
811
812 /* Otherwise use struct convention. */
813 return 1;
814 }
815
816 static CORE_ADDR
817 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
818 {
819 return sp & ~3;
820 }
821
822 /* Function: push_dummy_call (formerly push_arguments)
823 Setup the function arguments for calling a function in the inferior.
824
825 On the Renesas SH architecture, there are four registers (R4 to R7)
826 which are dedicated for passing function arguments. Up to the first
827 four arguments (depending on size) may go into these registers.
828 The rest go on the stack.
829
830 MVS: Except on SH variants that have floating point registers.
831 In that case, float and double arguments are passed in the same
832 manner, but using FP registers instead of GP registers.
833
834 Arguments that are smaller than 4 bytes will still take up a whole
835 register or a whole 32-bit word on the stack, and will be
836 right-justified in the register or the stack word. This includes
837 chars, shorts, and small aggregate types.
838
839 Arguments that are larger than 4 bytes may be split between two or
840 more registers. If there are not enough registers free, an argument
841 may be passed partly in a register (or registers), and partly on the
842 stack. This includes doubles, long longs, and larger aggregates.
843 As far as I know, there is no upper limit to the size of aggregates
844 that will be passed in this way; in other words, the convention of
845 passing a pointer to a large aggregate instead of a copy is not used.
846
847 MVS: The above appears to be true for the SH variants that do not
848 have an FPU, however those that have an FPU appear to copy the
849 aggregate argument onto the stack (and not place it in registers)
850 if it is larger than 16 bytes (four GP registers).
851
852 An exceptional case exists for struct arguments (and possibly other
853 aggregates such as arrays) if the size is larger than 4 bytes but
854 not a multiple of 4 bytes. In this case the argument is never split
855 between the registers and the stack, but instead is copied in its
856 entirety onto the stack, AND also copied into as many registers as
857 there is room for. In other words, space in registers permitting,
858 two copies of the same argument are passed in. As far as I can tell,
859 only the one on the stack is used, although that may be a function
860 of the level of compiler optimization. I suspect this is a compiler
861 bug. Arguments of these odd sizes are left-justified within the
862 word (as opposed to arguments smaller than 4 bytes, which are
863 right-justified).
864
865 If the function is to return an aggregate type such as a struct, it
866 is either returned in the normal return value register R0 (if its
867 size is no greater than one byte), or else the caller must allocate
868 space into which the callee will copy the return value (if the size
869 is greater than one byte). In this case, a pointer to the return
870 value location is passed into the callee in register R2, which does
871 not displace any of the other arguments passed in via registers R4
872 to R7. */
873
874 /* Helper function to justify value in register according to endianess. */
875 static char *
876 sh_justify_value_in_reg (struct value *val, int len)
877 {
878 static char valbuf[4];
879
880 memset (valbuf, 0, sizeof (valbuf));
881 if (len < 4)
882 {
883 /* value gets right-justified in the register or stack word */
884 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
885 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
886 else
887 memcpy (valbuf, (char *) value_contents (val), len);
888 return valbuf;
889 }
890 return (char *) value_contents (val);
891 }
892
893 /* Helper function to eval number of bytes to allocate on stack. */
894 static CORE_ADDR
895 sh_stack_allocsize (int nargs, struct value **args)
896 {
897 int stack_alloc = 0;
898 while (nargs-- > 0)
899 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
900 return stack_alloc;
901 }
902
903 /* Helper functions for getting the float arguments right. Registers usage
904 depends on the ABI and the endianess. The comments should enlighten how
905 it's intended to work. */
906
907 /* This array stores which of the float arg registers are already in use. */
908 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
909
910 /* This function just resets the above array to "no reg used so far". */
911 static void
912 sh_init_flt_argreg (void)
913 {
914 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
915 }
916
917 /* This function returns the next register to use for float arg passing.
918 It returns either a valid value between FLOAT_ARG0_REGNUM and
919 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
920 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
921
922 Note that register number 0 in flt_argreg_array corresponds with the
923 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
924 29) the parity of the register number is preserved, which is important
925 for the double register passing test (see the "argreg & 1" test below). */
926 static int
927 sh_next_flt_argreg (int len)
928 {
929 int argreg;
930
931 /* First search for the next free register. */
932 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
933 ++argreg)
934 if (!flt_argreg_array[argreg])
935 break;
936
937 /* No register left? */
938 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
939 return FLOAT_ARGLAST_REGNUM + 1;
940
941 if (len == 8)
942 {
943 /* Doubles are always starting in a even register number. */
944 if (argreg & 1)
945 {
946 flt_argreg_array[argreg] = 1;
947
948 ++argreg;
949
950 /* No register left? */
951 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
952 return FLOAT_ARGLAST_REGNUM + 1;
953 }
954 /* Also mark the next register as used. */
955 flt_argreg_array[argreg + 1] = 1;
956 }
957 else if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
958 {
959 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
960 if (!flt_argreg_array[argreg + 1])
961 ++argreg;
962 }
963 flt_argreg_array[argreg] = 1;
964 return FLOAT_ARG0_REGNUM + argreg;
965 }
966
967 /* Helper function which figures out, if a type is treated like a float type.
968
969 The FPU ABIs have a special way how to treat types as float types.
970 Structures with exactly one member, which is of type float or double, are
971 treated exactly as the base types float or double:
972
973 struct sf {
974 float f;
975 };
976
977 struct sd {
978 double d;
979 };
980
981 are handled the same way as just
982
983 float f;
984
985 double d;
986
987 As a result, arguments of these struct types are pushed into floating point
988 registers exactly as floats or doubles, using the same decision algorithm.
989
990 The same is valid if these types are used as function return types. The
991 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
992 or even using struct convention as it is for other structs. */
993
994 static int
995 sh_treat_as_flt_p (struct type *type)
996 {
997 int len = TYPE_LENGTH (type);
998
999 /* Ordinary float types are obviously treated as float. */
1000 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1001 return 1;
1002 /* Otherwise non-struct types are not treated as float. */
1003 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1004 return 0;
1005 /* Otherwise structs with more than one memeber are not treated as float. */
1006 if (TYPE_NFIELDS (type) != 1)
1007 return 0;
1008 /* Otherwise if the type of that member is float, the whole type is
1009 treated as float. */
1010 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1011 return 1;
1012 /* Otherwise it's not treated as float. */
1013 return 0;
1014 }
1015
1016 static CORE_ADDR
1017 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1018 struct value *function,
1019 struct regcache *regcache,
1020 CORE_ADDR bp_addr, int nargs,
1021 struct value **args,
1022 CORE_ADDR sp, int struct_return,
1023 CORE_ADDR struct_addr)
1024 {
1025 int stack_offset = 0;
1026 int argreg = ARG0_REGNUM;
1027 int flt_argreg = 0;
1028 int argnum;
1029 struct type *type;
1030 CORE_ADDR regval;
1031 char *val;
1032 int len, reg_size = 0;
1033 int pass_on_stack = 0;
1034 int treat_as_flt;
1035
1036 /* first force sp to a 4-byte alignment */
1037 sp = sh_frame_align (gdbarch, sp);
1038
1039 if (struct_return)
1040 regcache_cooked_write_unsigned (regcache,
1041 STRUCT_RETURN_REGNUM, struct_addr);
1042
1043 /* make room on stack for args */
1044 sp -= sh_stack_allocsize (nargs, args);
1045
1046 /* Initialize float argument mechanism. */
1047 sh_init_flt_argreg ();
1048
1049 /* Now load as many as possible of the first arguments into
1050 registers, and push the rest onto the stack. There are 16 bytes
1051 in four registers available. Loop thru args from first to last. */
1052 for (argnum = 0; argnum < nargs; argnum++)
1053 {
1054 type = value_type (args[argnum]);
1055 len = TYPE_LENGTH (type);
1056 val = sh_justify_value_in_reg (args[argnum], len);
1057
1058 /* Some decisions have to be made how various types are handled.
1059 This also differs in different ABIs. */
1060 pass_on_stack = 0;
1061
1062 /* Find out the next register to use for a floating point value. */
1063 treat_as_flt = sh_treat_as_flt_p (type);
1064 if (treat_as_flt)
1065 flt_argreg = sh_next_flt_argreg (len);
1066 /* In contrast to non-FPU CPUs, arguments are never split between
1067 registers and stack. If an argument doesn't fit in the remaining
1068 registers it's always pushed entirely on the stack. */
1069 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1070 pass_on_stack = 1;
1071
1072 while (len > 0)
1073 {
1074 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1075 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1076 || pass_on_stack)))
1077 {
1078 /* The data goes entirely on the stack, 4-byte aligned. */
1079 reg_size = (len + 3) & ~3;
1080 write_memory (sp + stack_offset, val, reg_size);
1081 stack_offset += reg_size;
1082 }
1083 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1084 {
1085 /* Argument goes in a float argument register. */
1086 reg_size = register_size (gdbarch, flt_argreg);
1087 regval = extract_unsigned_integer (val, reg_size);
1088 /* In little endian mode, float types taking two registers
1089 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1090 be stored swapped in the argument registers. The below
1091 code first writes the first 32 bits in the next but one
1092 register, increments the val and len values accordingly
1093 and then proceeds as normal by writing the second 32 bits
1094 into the next register. */
1095 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE
1096 && TYPE_LENGTH (type) == 2 * reg_size)
1097 {
1098 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1099 regval);
1100 val += reg_size;
1101 len -= reg_size;
1102 regval = extract_unsigned_integer (val, reg_size);
1103 }
1104 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1105 }
1106 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1107 {
1108 /* there's room in a register */
1109 reg_size = register_size (gdbarch, argreg);
1110 regval = extract_unsigned_integer (val, reg_size);
1111 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1112 }
1113 /* Store the value one register at a time or in one step on stack. */
1114 len -= reg_size;
1115 val += reg_size;
1116 }
1117 }
1118
1119 /* Store return address. */
1120 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1121
1122 /* Update stack pointer. */
1123 regcache_cooked_write_unsigned (regcache,
1124 gdbarch_sp_regnum (current_gdbarch), sp);
1125
1126 return sp;
1127 }
1128
1129 static CORE_ADDR
1130 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1131 struct value *function,
1132 struct regcache *regcache,
1133 CORE_ADDR bp_addr,
1134 int nargs, struct value **args,
1135 CORE_ADDR sp, int struct_return,
1136 CORE_ADDR struct_addr)
1137 {
1138 int stack_offset = 0;
1139 int argreg = ARG0_REGNUM;
1140 int argnum;
1141 struct type *type;
1142 CORE_ADDR regval;
1143 char *val;
1144 int len, reg_size;
1145
1146 /* first force sp to a 4-byte alignment */
1147 sp = sh_frame_align (gdbarch, sp);
1148
1149 if (struct_return)
1150 regcache_cooked_write_unsigned (regcache,
1151 STRUCT_RETURN_REGNUM, struct_addr);
1152
1153 /* make room on stack for args */
1154 sp -= sh_stack_allocsize (nargs, args);
1155
1156 /* Now load as many as possible of the first arguments into
1157 registers, and push the rest onto the stack. There are 16 bytes
1158 in four registers available. Loop thru args from first to last. */
1159 for (argnum = 0; argnum < nargs; argnum++)
1160 {
1161 type = value_type (args[argnum]);
1162 len = TYPE_LENGTH (type);
1163 val = sh_justify_value_in_reg (args[argnum], len);
1164
1165 while (len > 0)
1166 {
1167 if (argreg > ARGLAST_REGNUM)
1168 {
1169 /* The remainder of the data goes entirely on the stack,
1170 4-byte aligned. */
1171 reg_size = (len + 3) & ~3;
1172 write_memory (sp + stack_offset, val, reg_size);
1173 stack_offset += reg_size;
1174 }
1175 else if (argreg <= ARGLAST_REGNUM)
1176 {
1177 /* there's room in a register */
1178 reg_size = register_size (gdbarch, argreg);
1179 regval = extract_unsigned_integer (val, reg_size);
1180 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1181 }
1182 /* Store the value reg_size bytes at a time. This means that things
1183 larger than reg_size bytes may go partly in registers and partly
1184 on the stack. */
1185 len -= reg_size;
1186 val += reg_size;
1187 }
1188 }
1189
1190 /* Store return address. */
1191 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1192
1193 /* Update stack pointer. */
1194 regcache_cooked_write_unsigned (regcache,
1195 gdbarch_sp_regnum (current_gdbarch), sp);
1196
1197 return sp;
1198 }
1199
1200 /* Find a function's return value in the appropriate registers (in
1201 regbuf), and copy it into valbuf. Extract from an array REGBUF
1202 containing the (raw) register state a function return value of type
1203 TYPE, and copy that, in virtual format, into VALBUF. */
1204 static void
1205 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1206 void *valbuf)
1207 {
1208 int len = TYPE_LENGTH (type);
1209 int return_register = R0_REGNUM;
1210 int offset;
1211
1212 if (len <= 4)
1213 {
1214 ULONGEST c;
1215
1216 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1217 store_unsigned_integer (valbuf, len, c);
1218 }
1219 else if (len == 8)
1220 {
1221 int i, regnum = R0_REGNUM;
1222 for (i = 0; i < len; i += 4)
1223 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1224 }
1225 else
1226 error (_("bad size for return value"));
1227 }
1228
1229 static void
1230 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1231 void *valbuf)
1232 {
1233 if (sh_treat_as_flt_p (type))
1234 {
1235 int len = TYPE_LENGTH (type);
1236 int i, regnum = gdbarch_fp0_regnum (current_gdbarch);
1237 for (i = 0; i < len; i += 4)
1238 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1239 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1240 else
1241 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1242 }
1243 else
1244 sh_extract_return_value_nofpu (type, regcache, valbuf);
1245 }
1246
1247 /* Write into appropriate registers a function return value
1248 of type TYPE, given in virtual format.
1249 If the architecture is sh4 or sh3e, store a function's return value
1250 in the R0 general register or in the FP0 floating point register,
1251 depending on the type of the return value. In all the other cases
1252 the result is stored in r0, left-justified. */
1253 static void
1254 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1255 const void *valbuf)
1256 {
1257 ULONGEST val;
1258 int len = TYPE_LENGTH (type);
1259
1260 if (len <= 4)
1261 {
1262 val = extract_unsigned_integer (valbuf, len);
1263 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1264 }
1265 else
1266 {
1267 int i, regnum = R0_REGNUM;
1268 for (i = 0; i < len; i += 4)
1269 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1270 }
1271 }
1272
1273 static void
1274 sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1275 const void *valbuf)
1276 {
1277 if (sh_treat_as_flt_p (type))
1278 {
1279 int len = TYPE_LENGTH (type);
1280 int i, regnum = gdbarch_fp0_regnum (current_gdbarch);
1281 for (i = 0; i < len; i += 4)
1282 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1283 regcache_raw_write (regcache, regnum++,
1284 (char *) valbuf + len - 4 - i);
1285 else
1286 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1287 }
1288 else
1289 sh_store_return_value_nofpu (type, regcache, valbuf);
1290 }
1291
1292 static enum return_value_convention
1293 sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *type,
1294 struct regcache *regcache,
1295 gdb_byte *readbuf, const gdb_byte *writebuf)
1296 {
1297 if (sh_use_struct_convention (0, type))
1298 return RETURN_VALUE_STRUCT_CONVENTION;
1299 if (writebuf)
1300 sh_store_return_value_nofpu (type, regcache, writebuf);
1301 else if (readbuf)
1302 sh_extract_return_value_nofpu (type, regcache, readbuf);
1303 return RETURN_VALUE_REGISTER_CONVENTION;
1304 }
1305
1306 static enum return_value_convention
1307 sh_return_value_fpu (struct gdbarch *gdbarch, struct type *type,
1308 struct regcache *regcache,
1309 gdb_byte *readbuf, const gdb_byte *writebuf)
1310 {
1311 if (sh_use_struct_convention (0, type))
1312 return RETURN_VALUE_STRUCT_CONVENTION;
1313 if (writebuf)
1314 sh_store_return_value_fpu (type, regcache, writebuf);
1315 else if (readbuf)
1316 sh_extract_return_value_fpu (type, regcache, readbuf);
1317 return RETURN_VALUE_REGISTER_CONVENTION;
1318 }
1319
1320 /* Print the registers in a form similar to the E7000 */
1321
1322 static void
1323 sh_generic_show_regs (struct frame_info *frame)
1324 {
1325 printf_filtered
1326 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1327 paddr (get_frame_register_unsigned (frame,
1328 gdbarch_pc_regnum (current_gdbarch))),
1329 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1330 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1331 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1332
1333 printf_filtered
1334 (" GBR %08lx VBR %08lx MACL %08lx\n",
1335 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1336 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1337 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1338
1339 printf_filtered
1340 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1341 (long) get_frame_register_unsigned (frame, 0),
1342 (long) get_frame_register_unsigned (frame, 1),
1343 (long) get_frame_register_unsigned (frame, 2),
1344 (long) get_frame_register_unsigned (frame, 3),
1345 (long) get_frame_register_unsigned (frame, 4),
1346 (long) get_frame_register_unsigned (frame, 5),
1347 (long) get_frame_register_unsigned (frame, 6),
1348 (long) get_frame_register_unsigned (frame, 7));
1349 printf_filtered
1350 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1351 (long) get_frame_register_unsigned (frame, 8),
1352 (long) get_frame_register_unsigned (frame, 9),
1353 (long) get_frame_register_unsigned (frame, 10),
1354 (long) get_frame_register_unsigned (frame, 11),
1355 (long) get_frame_register_unsigned (frame, 12),
1356 (long) get_frame_register_unsigned (frame, 13),
1357 (long) get_frame_register_unsigned (frame, 14),
1358 (long) get_frame_register_unsigned (frame, 15));
1359 }
1360
1361 static void
1362 sh3_show_regs (struct frame_info *frame)
1363 {
1364 printf_filtered
1365 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1366 paddr (get_frame_register_unsigned (frame,
1367 gdbarch_pc_regnum (current_gdbarch))),
1368 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1369 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1370 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1371
1372 printf_filtered
1373 (" GBR %08lx VBR %08lx MACL %08lx\n",
1374 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1375 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1376 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1377 printf_filtered
1378 (" SSR %08lx SPC %08lx\n",
1379 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1380 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
1381
1382 printf_filtered
1383 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1384 (long) get_frame_register_unsigned (frame, 0),
1385 (long) get_frame_register_unsigned (frame, 1),
1386 (long) get_frame_register_unsigned (frame, 2),
1387 (long) get_frame_register_unsigned (frame, 3),
1388 (long) get_frame_register_unsigned (frame, 4),
1389 (long) get_frame_register_unsigned (frame, 5),
1390 (long) get_frame_register_unsigned (frame, 6),
1391 (long) get_frame_register_unsigned (frame, 7));
1392 printf_filtered
1393 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1394 (long) get_frame_register_unsigned (frame, 8),
1395 (long) get_frame_register_unsigned (frame, 9),
1396 (long) get_frame_register_unsigned (frame, 10),
1397 (long) get_frame_register_unsigned (frame, 11),
1398 (long) get_frame_register_unsigned (frame, 12),
1399 (long) get_frame_register_unsigned (frame, 13),
1400 (long) get_frame_register_unsigned (frame, 14),
1401 (long) get_frame_register_unsigned (frame, 15));
1402 }
1403
1404 static void
1405 sh2e_show_regs (struct frame_info *frame)
1406 {
1407 printf_filtered
1408 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1409 paddr (get_frame_register_unsigned (frame,
1410 gdbarch_pc_regnum (current_gdbarch))),
1411 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1412 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1413 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1414
1415 printf_filtered
1416 (" GBR %08lx VBR %08lx MACL %08lx\n",
1417 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1418 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1419 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1420 printf_filtered
1421 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1422 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1423 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1424 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1425 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1426
1427 printf_filtered
1428 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1429 (long) get_frame_register_unsigned (frame, 0),
1430 (long) get_frame_register_unsigned (frame, 1),
1431 (long) get_frame_register_unsigned (frame, 2),
1432 (long) get_frame_register_unsigned (frame, 3),
1433 (long) get_frame_register_unsigned (frame, 4),
1434 (long) get_frame_register_unsigned (frame, 5),
1435 (long) get_frame_register_unsigned (frame, 6),
1436 (long) get_frame_register_unsigned (frame, 7));
1437 printf_filtered
1438 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1439 (long) get_frame_register_unsigned (frame, 8),
1440 (long) get_frame_register_unsigned (frame, 9),
1441 (long) get_frame_register_unsigned (frame, 10),
1442 (long) get_frame_register_unsigned (frame, 11),
1443 (long) get_frame_register_unsigned (frame, 12),
1444 (long) get_frame_register_unsigned (frame, 13),
1445 (long) get_frame_register_unsigned (frame, 14),
1446 (long) get_frame_register_unsigned (frame, 15));
1447
1448 printf_filtered
1449 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1450 (long) get_frame_register_unsigned
1451 (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1452 (long) get_frame_register_unsigned
1453 (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1454 (long) get_frame_register_unsigned
1455 (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1456 (long) get_frame_register_unsigned
1457 (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1458 (long) get_frame_register_unsigned
1459 (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1460 (long) get_frame_register_unsigned
1461 (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1462 (long) get_frame_register_unsigned
1463 (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1464 (long) get_frame_register_unsigned
1465 (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1466 printf_filtered
1467 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1468 (long) get_frame_register_unsigned
1469 (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1470 (long) get_frame_register_unsigned
1471 (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1472 (long) get_frame_register_unsigned
1473 (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1474 (long) get_frame_register_unsigned
1475 (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1476 (long) get_frame_register_unsigned
1477 (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1478 (long) get_frame_register_unsigned
1479 (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1480 (long) get_frame_register_unsigned
1481 (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1482 (long) get_frame_register_unsigned
1483 (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1484 }
1485
1486 static void
1487 sh2a_show_regs (struct frame_info *frame)
1488 {
1489 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1490
1491 printf_filtered
1492 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1493 paddr (get_frame_register_unsigned (frame,
1494 gdbarch_pc_regnum (current_gdbarch))),
1495 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1496 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1497 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1498
1499 printf_filtered
1500 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1501 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1502 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1503 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1504 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1505 printf_filtered
1506 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1507 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1508 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1509 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1510 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1511
1512 printf_filtered
1513 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1514 (long) get_frame_register_unsigned (frame, 0),
1515 (long) get_frame_register_unsigned (frame, 1),
1516 (long) get_frame_register_unsigned (frame, 2),
1517 (long) get_frame_register_unsigned (frame, 3),
1518 (long) get_frame_register_unsigned (frame, 4),
1519 (long) get_frame_register_unsigned (frame, 5),
1520 (long) get_frame_register_unsigned (frame, 6),
1521 (long) get_frame_register_unsigned (frame, 7));
1522 printf_filtered
1523 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1524 (long) get_frame_register_unsigned (frame, 8),
1525 (long) get_frame_register_unsigned (frame, 9),
1526 (long) get_frame_register_unsigned (frame, 10),
1527 (long) get_frame_register_unsigned (frame, 11),
1528 (long) get_frame_register_unsigned (frame, 12),
1529 (long) get_frame_register_unsigned (frame, 13),
1530 (long) get_frame_register_unsigned (frame, 14),
1531 (long) get_frame_register_unsigned (frame, 15));
1532
1533 printf_filtered
1534 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1535 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1536 (long) get_frame_register_unsigned
1537 (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1538 (long) get_frame_register_unsigned
1539 (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1540 (long) get_frame_register_unsigned
1541 (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1542 (long) get_frame_register_unsigned
1543 (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1544 (long) get_frame_register_unsigned
1545 (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1546 (long) get_frame_register_unsigned
1547 (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1548 (long) get_frame_register_unsigned
1549 (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1550 (long) get_frame_register_unsigned
1551 (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1552 printf_filtered
1553 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1554 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1555 (long) get_frame_register_unsigned
1556 (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1557 (long) get_frame_register_unsigned
1558 (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1559 (long) get_frame_register_unsigned
1560 (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1561 (long) get_frame_register_unsigned
1562 (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1563 (long) get_frame_register_unsigned
1564 (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1565 (long) get_frame_register_unsigned
1566 (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1567 (long) get_frame_register_unsigned
1568 (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1569 (long) get_frame_register_unsigned
1570 (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1571 printf_filtered
1572 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1573 printf_filtered
1574 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1575 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1576 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1577 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1578 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1579 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1580 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1581 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1582 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1583 printf_filtered
1584 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1585 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1586 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1587 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1588 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1589 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1590 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1591 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1592 printf_filtered
1593 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1594 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1595 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1596 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1597 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1598 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1599 }
1600
1601 static void
1602 sh2a_nofpu_show_regs (struct frame_info *frame)
1603 {
1604 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1605
1606 printf_filtered
1607 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1608 paddr (get_frame_register_unsigned (frame,
1609 gdbarch_pc_regnum (current_gdbarch))),
1610 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1611 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1612 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1613
1614 printf_filtered
1615 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1616 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1617 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1618 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1619 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1620 printf_filtered
1621 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1622 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1623 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1624 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1625 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1626
1627 printf_filtered
1628 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1629 (long) get_frame_register_unsigned (frame, 0),
1630 (long) get_frame_register_unsigned (frame, 1),
1631 (long) get_frame_register_unsigned (frame, 2),
1632 (long) get_frame_register_unsigned (frame, 3),
1633 (long) get_frame_register_unsigned (frame, 4),
1634 (long) get_frame_register_unsigned (frame, 5),
1635 (long) get_frame_register_unsigned (frame, 6),
1636 (long) get_frame_register_unsigned (frame, 7));
1637 printf_filtered
1638 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1639 (long) get_frame_register_unsigned (frame, 8),
1640 (long) get_frame_register_unsigned (frame, 9),
1641 (long) get_frame_register_unsigned (frame, 10),
1642 (long) get_frame_register_unsigned (frame, 11),
1643 (long) get_frame_register_unsigned (frame, 12),
1644 (long) get_frame_register_unsigned (frame, 13),
1645 (long) get_frame_register_unsigned (frame, 14),
1646 (long) get_frame_register_unsigned (frame, 15));
1647
1648 printf_filtered
1649 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1650 printf_filtered
1651 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1652 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1653 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1654 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1655 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1656 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1657 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1658 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1659 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1660 printf_filtered
1661 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1662 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1663 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1664 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1665 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1666 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1667 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1668 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1669 printf_filtered
1670 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1671 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1672 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1673 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1674 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1675 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1676 }
1677
1678 static void
1679 sh3e_show_regs (struct frame_info *frame)
1680 {
1681 printf_filtered
1682 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1683 paddr (get_frame_register_unsigned (frame,
1684 gdbarch_pc_regnum (current_gdbarch))),
1685 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1686 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1687 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1688
1689 printf_filtered
1690 (" GBR %08lx VBR %08lx MACL %08lx\n",
1691 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1692 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1693 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1694 printf_filtered
1695 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1696 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1697 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1698 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1699 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1700
1701 printf_filtered
1702 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1703 (long) get_frame_register_unsigned (frame, 0),
1704 (long) get_frame_register_unsigned (frame, 1),
1705 (long) get_frame_register_unsigned (frame, 2),
1706 (long) get_frame_register_unsigned (frame, 3),
1707 (long) get_frame_register_unsigned (frame, 4),
1708 (long) get_frame_register_unsigned (frame, 5),
1709 (long) get_frame_register_unsigned (frame, 6),
1710 (long) get_frame_register_unsigned (frame, 7));
1711 printf_filtered
1712 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1713 (long) get_frame_register_unsigned (frame, 8),
1714 (long) get_frame_register_unsigned (frame, 9),
1715 (long) get_frame_register_unsigned (frame, 10),
1716 (long) get_frame_register_unsigned (frame, 11),
1717 (long) get_frame_register_unsigned (frame, 12),
1718 (long) get_frame_register_unsigned (frame, 13),
1719 (long) get_frame_register_unsigned (frame, 14),
1720 (long) get_frame_register_unsigned (frame, 15));
1721
1722 printf_filtered
1723 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1724 (long) get_frame_register_unsigned
1725 (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1726 (long) get_frame_register_unsigned
1727 (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1728 (long) get_frame_register_unsigned
1729 (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1730 (long) get_frame_register_unsigned
1731 (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1732 (long) get_frame_register_unsigned
1733 (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1734 (long) get_frame_register_unsigned
1735 (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1736 (long) get_frame_register_unsigned
1737 (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1738 (long) get_frame_register_unsigned
1739 (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1740 printf_filtered
1741 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1742 (long) get_frame_register_unsigned
1743 (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1744 (long) get_frame_register_unsigned
1745 (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1746 (long) get_frame_register_unsigned
1747 (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1748 (long) get_frame_register_unsigned
1749 (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1750 (long) get_frame_register_unsigned
1751 (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1752 (long) get_frame_register_unsigned
1753 (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1754 (long) get_frame_register_unsigned
1755 (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1756 (long) get_frame_register_unsigned
1757 (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1758 }
1759
1760 static void
1761 sh3_dsp_show_regs (struct frame_info *frame)
1762 {
1763 printf_filtered
1764 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1765 paddr (get_frame_register_unsigned (frame,
1766 gdbarch_pc_regnum (current_gdbarch))),
1767 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1768 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1769 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1770
1771 printf_filtered
1772 (" GBR %08lx VBR %08lx MACL %08lx\n",
1773 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1774 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1775 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1776
1777 printf_filtered
1778 (" SSR %08lx SPC %08lx DSR %08lx\n",
1779 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1780 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1781 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
1782
1783 printf_filtered
1784 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1785 (long) get_frame_register_unsigned (frame, 0),
1786 (long) get_frame_register_unsigned (frame, 1),
1787 (long) get_frame_register_unsigned (frame, 2),
1788 (long) get_frame_register_unsigned (frame, 3),
1789 (long) get_frame_register_unsigned (frame, 4),
1790 (long) get_frame_register_unsigned (frame, 5),
1791 (long) get_frame_register_unsigned (frame, 6),
1792 (long) get_frame_register_unsigned (frame, 7));
1793 printf_filtered
1794 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1795 (long) get_frame_register_unsigned (frame, 8),
1796 (long) get_frame_register_unsigned (frame, 9),
1797 (long) get_frame_register_unsigned (frame, 10),
1798 (long) get_frame_register_unsigned (frame, 11),
1799 (long) get_frame_register_unsigned (frame, 12),
1800 (long) get_frame_register_unsigned (frame, 13),
1801 (long) get_frame_register_unsigned (frame, 14),
1802 (long) get_frame_register_unsigned (frame, 15));
1803
1804 printf_filtered
1805 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1806 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1807 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1808 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1809 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1810 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1811 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1812 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1813 printf_filtered
1814 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1815 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1816 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1817 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1818 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1819 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1820 (long) get_frame_register_unsigned (frame, RE_REGNUM));
1821 }
1822
1823 static void
1824 sh4_show_regs (struct frame_info *frame)
1825 {
1826 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1827
1828 printf_filtered
1829 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1830 paddr (get_frame_register_unsigned (frame,
1831 gdbarch_pc_regnum (current_gdbarch))),
1832 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1833 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1834 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1835
1836 printf_filtered
1837 (" GBR %08lx VBR %08lx MACL %08lx\n",
1838 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1839 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1840 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1841 printf_filtered
1842 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1843 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1844 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1845 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1846 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1847
1848 printf_filtered
1849 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1850 (long) get_frame_register_unsigned (frame, 0),
1851 (long) get_frame_register_unsigned (frame, 1),
1852 (long) get_frame_register_unsigned (frame, 2),
1853 (long) get_frame_register_unsigned (frame, 3),
1854 (long) get_frame_register_unsigned (frame, 4),
1855 (long) get_frame_register_unsigned (frame, 5),
1856 (long) get_frame_register_unsigned (frame, 6),
1857 (long) get_frame_register_unsigned (frame, 7));
1858 printf_filtered
1859 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1860 (long) get_frame_register_unsigned (frame, 8),
1861 (long) get_frame_register_unsigned (frame, 9),
1862 (long) get_frame_register_unsigned (frame, 10),
1863 (long) get_frame_register_unsigned (frame, 11),
1864 (long) get_frame_register_unsigned (frame, 12),
1865 (long) get_frame_register_unsigned (frame, 13),
1866 (long) get_frame_register_unsigned (frame, 14),
1867 (long) get_frame_register_unsigned (frame, 15));
1868
1869 printf_filtered
1870 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1871 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1872 (long) get_frame_register_unsigned
1873 (frame, gdbarch_fp0_regnum (current_gdbarch) + 0),
1874 (long) get_frame_register_unsigned
1875 (frame, gdbarch_fp0_regnum (current_gdbarch) + 1),
1876 (long) get_frame_register_unsigned
1877 (frame, gdbarch_fp0_regnum (current_gdbarch) + 2),
1878 (long) get_frame_register_unsigned
1879 (frame, gdbarch_fp0_regnum (current_gdbarch) + 3),
1880 (long) get_frame_register_unsigned
1881 (frame, gdbarch_fp0_regnum (current_gdbarch) + 4),
1882 (long) get_frame_register_unsigned
1883 (frame, gdbarch_fp0_regnum (current_gdbarch) + 5),
1884 (long) get_frame_register_unsigned
1885 (frame, gdbarch_fp0_regnum (current_gdbarch) + 6),
1886 (long) get_frame_register_unsigned
1887 (frame, gdbarch_fp0_regnum (current_gdbarch) + 7));
1888 printf_filtered
1889 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1890 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1891 (long) get_frame_register_unsigned
1892 (frame, gdbarch_fp0_regnum (current_gdbarch) + 8),
1893 (long) get_frame_register_unsigned
1894 (frame, gdbarch_fp0_regnum (current_gdbarch) + 9),
1895 (long) get_frame_register_unsigned
1896 (frame, gdbarch_fp0_regnum (current_gdbarch) + 10),
1897 (long) get_frame_register_unsigned
1898 (frame, gdbarch_fp0_regnum (current_gdbarch) + 11),
1899 (long) get_frame_register_unsigned
1900 (frame, gdbarch_fp0_regnum (current_gdbarch) + 12),
1901 (long) get_frame_register_unsigned
1902 (frame, gdbarch_fp0_regnum (current_gdbarch) + 13),
1903 (long) get_frame_register_unsigned
1904 (frame, gdbarch_fp0_regnum (current_gdbarch) + 14),
1905 (long) get_frame_register_unsigned
1906 (frame, gdbarch_fp0_regnum (current_gdbarch) + 15));
1907 }
1908
1909 static void
1910 sh4_nofpu_show_regs (struct frame_info *frame)
1911 {
1912 printf_filtered
1913 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1914 paddr (get_frame_register_unsigned (frame,
1915 gdbarch_pc_regnum (current_gdbarch))),
1916 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1917 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1918 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1919
1920 printf_filtered
1921 (" GBR %08lx VBR %08lx MACL %08lx\n",
1922 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1923 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1924 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1925 printf_filtered
1926 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1927 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1928 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1929 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1930 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1931
1932 printf_filtered
1933 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1934 (long) get_frame_register_unsigned (frame, 0),
1935 (long) get_frame_register_unsigned (frame, 1),
1936 (long) get_frame_register_unsigned (frame, 2),
1937 (long) get_frame_register_unsigned (frame, 3),
1938 (long) get_frame_register_unsigned (frame, 4),
1939 (long) get_frame_register_unsigned (frame, 5),
1940 (long) get_frame_register_unsigned (frame, 6),
1941 (long) get_frame_register_unsigned (frame, 7));
1942 printf_filtered
1943 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1944 (long) get_frame_register_unsigned (frame, 8),
1945 (long) get_frame_register_unsigned (frame, 9),
1946 (long) get_frame_register_unsigned (frame, 10),
1947 (long) get_frame_register_unsigned (frame, 11),
1948 (long) get_frame_register_unsigned (frame, 12),
1949 (long) get_frame_register_unsigned (frame, 13),
1950 (long) get_frame_register_unsigned (frame, 14),
1951 (long) get_frame_register_unsigned (frame, 15));
1952 }
1953
1954 static void
1955 sh_dsp_show_regs (struct frame_info *frame)
1956 {
1957 printf_filtered
1958 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1959 paddr (get_frame_register_unsigned (frame,
1960 gdbarch_pc_regnum (current_gdbarch))),
1961 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1962 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1963 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1964
1965 printf_filtered
1966 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
1967 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1968 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1969 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
1970 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1971
1972 printf_filtered
1973 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1974 (long) get_frame_register_unsigned (frame, 0),
1975 (long) get_frame_register_unsigned (frame, 1),
1976 (long) get_frame_register_unsigned (frame, 2),
1977 (long) get_frame_register_unsigned (frame, 3),
1978 (long) get_frame_register_unsigned (frame, 4),
1979 (long) get_frame_register_unsigned (frame, 5),
1980 (long) get_frame_register_unsigned (frame, 6),
1981 (long) get_frame_register_unsigned (frame, 7));
1982 printf_filtered
1983 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1984 (long) get_frame_register_unsigned (frame, 8),
1985 (long) get_frame_register_unsigned (frame, 9),
1986 (long) get_frame_register_unsigned (frame, 10),
1987 (long) get_frame_register_unsigned (frame, 11),
1988 (long) get_frame_register_unsigned (frame, 12),
1989 (long) get_frame_register_unsigned (frame, 13),
1990 (long) get_frame_register_unsigned (frame, 14),
1991 (long) get_frame_register_unsigned (frame, 15));
1992
1993 printf_filtered
1994 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1995 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1996 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1997 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1998 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1999 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2000 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2001 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
2002 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2003 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2004 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2005 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2006 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2007 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2008 (long) get_frame_register_unsigned (frame, RE_REGNUM));
2009 }
2010
2011 static void
2012 sh_show_regs_command (char *args, int from_tty)
2013 {
2014 if (sh_show_regs)
2015 (*sh_show_regs) (get_current_frame ());
2016 }
2017
2018 static struct type *
2019 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2020 {
2021 if ((reg_nr >= gdbarch_fp0_regnum (current_gdbarch)
2022 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2023 return builtin_type_float;
2024 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2025 return builtin_type_double;
2026 else
2027 return builtin_type_int;
2028 }
2029
2030 /* Return the GDB type object for the "standard" data type
2031 of data in register N. */
2032 static struct type *
2033 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
2034 {
2035 if ((reg_nr >= gdbarch_fp0_regnum (current_gdbarch)
2036 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2037 return builtin_type_float;
2038 else
2039 return builtin_type_int;
2040 }
2041
2042 static struct type *
2043 sh_sh4_build_float_register_type (int high)
2044 {
2045 struct type *temp;
2046
2047 temp = create_range_type (NULL, builtin_type_int, 0, high);
2048 return create_array_type (NULL, builtin_type_float, temp);
2049 }
2050
2051 static struct type *
2052 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
2053 {
2054 if ((reg_nr >= gdbarch_fp0_regnum (current_gdbarch)
2055 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2056 return builtin_type_float;
2057 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2058 return builtin_type_double;
2059 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2060 return sh_sh4_build_float_register_type (3);
2061 else
2062 return builtin_type_int;
2063 }
2064
2065 static struct type *
2066 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
2067 {
2068 return builtin_type_int;
2069 }
2070
2071 /* Is a register in a reggroup?
2072 The default code in reggroup.c doesn't identify system registers, some
2073 float registers or any of the vector registers.
2074 TODO: sh2a and dsp registers. */
2075 int
2076 sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2077 struct reggroup *reggroup)
2078 {
2079 if (gdbarch_register_name (current_gdbarch, regnum) == NULL
2080 || *gdbarch_register_name (current_gdbarch, regnum) == '\0')
2081 return 0;
2082
2083 if (reggroup == float_reggroup
2084 && (regnum == FPUL_REGNUM
2085 || regnum == FPSCR_REGNUM))
2086 return 1;
2087
2088 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2089 {
2090 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2091 return 1;
2092 if (reggroup == general_reggroup)
2093 return 0;
2094 }
2095
2096 if (regnum == VBR_REGNUM
2097 || regnum == SR_REGNUM
2098 || regnum == FPSCR_REGNUM
2099 || regnum == SSR_REGNUM
2100 || regnum == SPC_REGNUM)
2101 {
2102 if (reggroup == system_reggroup)
2103 return 1;
2104 if (reggroup == general_reggroup)
2105 return 0;
2106 }
2107
2108 /* The default code can cope with any other registers. */
2109 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2110 }
2111
2112 /* On the sh4, the DRi pseudo registers are problematic if the target
2113 is little endian. When the user writes one of those registers, for
2114 instance with 'ser var $dr0=1', we want the double to be stored
2115 like this:
2116 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2117 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2118
2119 This corresponds to little endian byte order & big endian word
2120 order. However if we let gdb write the register w/o conversion, it
2121 will write fr0 and fr1 this way:
2122 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2123 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2124 because it will consider fr0 and fr1 as a single LE stretch of memory.
2125
2126 To achieve what we want we must force gdb to store things in
2127 floatformat_ieee_double_littlebyte_bigword (which is defined in
2128 include/floatformat.h and libiberty/floatformat.c.
2129
2130 In case the target is big endian, there is no problem, the
2131 raw bytes will look like:
2132 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2133 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2134
2135 The other pseudo registers (the FVs) also don't pose a problem
2136 because they are stored as 4 individual FP elements. */
2137
2138 static void
2139 sh_register_convert_to_virtual (int regnum, struct type *type,
2140 char *from, char *to)
2141 {
2142 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2143 {
2144 DOUBLEST val;
2145 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2146 from, &val);
2147 store_typed_floating (to, type, val);
2148 }
2149 else
2150 error
2151 ("sh_register_convert_to_virtual called with non DR register number");
2152 }
2153
2154 static void
2155 sh_register_convert_to_raw (struct type *type, int regnum,
2156 const void *from, void *to)
2157 {
2158 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2159 {
2160 DOUBLEST val = extract_typed_floating (from, type);
2161 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2162 &val, to);
2163 }
2164 else
2165 error (_("sh_register_convert_to_raw called with non DR register number"));
2166 }
2167
2168 /* For vectors of 4 floating point registers. */
2169 static int
2170 fv_reg_base_num (int fv_regnum)
2171 {
2172 int fp_regnum;
2173
2174 fp_regnum = gdbarch_fp0_regnum (current_gdbarch)
2175 + (fv_regnum - FV0_REGNUM) * 4;
2176 return fp_regnum;
2177 }
2178
2179 /* For double precision floating point registers, i.e 2 fp regs.*/
2180 static int
2181 dr_reg_base_num (int dr_regnum)
2182 {
2183 int fp_regnum;
2184
2185 fp_regnum = gdbarch_fp0_regnum (current_gdbarch)
2186 + (dr_regnum - DR0_REGNUM) * 2;
2187 return fp_regnum;
2188 }
2189
2190 static void
2191 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2192 int reg_nr, gdb_byte *buffer)
2193 {
2194 int base_regnum, portion;
2195 char temp_buffer[MAX_REGISTER_SIZE];
2196
2197 if (reg_nr == PSEUDO_BANK_REGNUM)
2198 regcache_raw_read (regcache, BANK_REGNUM, buffer);
2199 else
2200 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2201 {
2202 base_regnum = dr_reg_base_num (reg_nr);
2203
2204 /* Build the value in the provided buffer. */
2205 /* Read the real regs for which this one is an alias. */
2206 for (portion = 0; portion < 2; portion++)
2207 regcache_raw_read (regcache, base_regnum + portion,
2208 (temp_buffer
2209 + register_size (gdbarch,
2210 base_regnum) * portion));
2211 /* We must pay attention to the endiannes. */
2212 sh_register_convert_to_virtual (reg_nr,
2213 register_type (gdbarch, reg_nr),
2214 temp_buffer, buffer);
2215 }
2216 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2217 {
2218 base_regnum = fv_reg_base_num (reg_nr);
2219
2220 /* Read the real regs for which this one is an alias. */
2221 for (portion = 0; portion < 4; portion++)
2222 regcache_raw_read (regcache, base_regnum + portion,
2223 ((char *) buffer
2224 + register_size (gdbarch,
2225 base_regnum) * portion));
2226 }
2227 }
2228
2229 static void
2230 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2231 int reg_nr, const gdb_byte *buffer)
2232 {
2233 int base_regnum, portion;
2234 char temp_buffer[MAX_REGISTER_SIZE];
2235
2236 if (reg_nr == PSEUDO_BANK_REGNUM)
2237 {
2238 /* When the bank register is written to, the whole register bank
2239 is switched and all values in the bank registers must be read
2240 from the target/sim again. We're just invalidating the regcache
2241 so that a re-read happens next time it's necessary. */
2242 int bregnum;
2243
2244 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2245 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
2246 regcache_invalidate (regcache, bregnum);
2247 }
2248 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2249 {
2250 base_regnum = dr_reg_base_num (reg_nr);
2251
2252 /* We must pay attention to the endiannes. */
2253 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
2254 reg_nr, buffer, temp_buffer);
2255
2256 /* Write the real regs for which this one is an alias. */
2257 for (portion = 0; portion < 2; portion++)
2258 regcache_raw_write (regcache, base_regnum + portion,
2259 (temp_buffer
2260 + register_size (gdbarch,
2261 base_regnum) * portion));
2262 }
2263 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2264 {
2265 base_regnum = fv_reg_base_num (reg_nr);
2266
2267 /* Write the real regs for which this one is an alias. */
2268 for (portion = 0; portion < 4; portion++)
2269 regcache_raw_write (regcache, base_regnum + portion,
2270 ((char *) buffer
2271 + register_size (gdbarch,
2272 base_regnum) * portion));
2273 }
2274 }
2275
2276 static int
2277 sh_dsp_register_sim_regno (int nr)
2278 {
2279 if (legacy_register_sim_regno (nr) < 0)
2280 return legacy_register_sim_regno (nr);
2281 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2282 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2283 if (nr == MOD_REGNUM)
2284 return SIM_SH_MOD_REGNUM;
2285 if (nr == RS_REGNUM)
2286 return SIM_SH_RS_REGNUM;
2287 if (nr == RE_REGNUM)
2288 return SIM_SH_RE_REGNUM;
2289 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2290 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2291 return nr;
2292 }
2293
2294 static int
2295 sh_sh2a_register_sim_regno (int nr)
2296 {
2297 switch (nr)
2298 {
2299 case TBR_REGNUM:
2300 return SIM_SH_TBR_REGNUM;
2301 case IBNR_REGNUM:
2302 return SIM_SH_IBNR_REGNUM;
2303 case IBCR_REGNUM:
2304 return SIM_SH_IBCR_REGNUM;
2305 case BANK_REGNUM:
2306 return SIM_SH_BANK_REGNUM;
2307 case MACLB_REGNUM:
2308 return SIM_SH_BANK_MACL_REGNUM;
2309 case GBRB_REGNUM:
2310 return SIM_SH_BANK_GBR_REGNUM;
2311 case PRB_REGNUM:
2312 return SIM_SH_BANK_PR_REGNUM;
2313 case IVNB_REGNUM:
2314 return SIM_SH_BANK_IVN_REGNUM;
2315 case MACHB_REGNUM:
2316 return SIM_SH_BANK_MACH_REGNUM;
2317 default:
2318 break;
2319 }
2320 return legacy_register_sim_regno (nr);
2321 }
2322
2323 /* Set up the register unwinding such that call-clobbered registers are
2324 not displayed in frames >0 because the true value is not certain.
2325 The 'undefined' registers will show up as 'not available' unless the
2326 CFI says otherwise.
2327
2328 This function is currently set up for SH4 and compatible only. */
2329
2330 static void
2331 sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2332 struct dwarf2_frame_state_reg *reg,
2333 struct frame_info *next_frame)
2334 {
2335 /* Mark the PC as the destination for the return address. */
2336 if (regnum == gdbarch_pc_regnum (current_gdbarch))
2337 reg->how = DWARF2_FRAME_REG_RA;
2338
2339 /* Mark the stack pointer as the call frame address. */
2340 else if (regnum == gdbarch_sp_regnum (current_gdbarch))
2341 reg->how = DWARF2_FRAME_REG_CFA;
2342
2343 /* The above was taken from the default init_reg in dwarf2-frame.c
2344 while the below is SH specific. */
2345
2346 /* Caller save registers. */
2347 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2348 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2349 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2350 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2351 || (regnum == MACH_REGNUM)
2352 || (regnum == MACL_REGNUM)
2353 || (regnum == FPUL_REGNUM)
2354 || (regnum == SR_REGNUM))
2355 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2356
2357 /* Callee save registers. */
2358 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2359 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2360 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2361 || (regnum == FV0_REGNUM+3))
2362 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2363
2364 /* Other registers. These are not in the ABI and may or may not
2365 mean anything in frames >0 so don't show them. */
2366 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2367 || (regnum == GBR_REGNUM)
2368 || (regnum == VBR_REGNUM)
2369 || (regnum == FPSCR_REGNUM)
2370 || (regnum == SSR_REGNUM)
2371 || (regnum == SPC_REGNUM))
2372 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2373 }
2374
2375 static struct sh_frame_cache *
2376 sh_alloc_frame_cache (void)
2377 {
2378 struct sh_frame_cache *cache;
2379 int i;
2380
2381 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2382
2383 /* Base address. */
2384 cache->base = 0;
2385 cache->saved_sp = 0;
2386 cache->sp_offset = 0;
2387 cache->pc = 0;
2388
2389 /* Frameless until proven otherwise. */
2390 cache->uses_fp = 0;
2391
2392 /* Saved registers. We initialize these to -1 since zero is a valid
2393 offset (that's where fp is supposed to be stored). */
2394 for (i = 0; i < SH_NUM_REGS; i++)
2395 {
2396 cache->saved_regs[i] = -1;
2397 }
2398
2399 return cache;
2400 }
2401
2402 static struct sh_frame_cache *
2403 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
2404 {
2405 struct sh_frame_cache *cache;
2406 CORE_ADDR current_pc;
2407 int i;
2408
2409 if (*this_cache)
2410 return *this_cache;
2411
2412 cache = sh_alloc_frame_cache ();
2413 *this_cache = cache;
2414
2415 /* In principle, for normal frames, fp holds the frame pointer,
2416 which holds the base address for the current stack frame.
2417 However, for functions that don't need it, the frame pointer is
2418 optional. For these "frameless" functions the frame pointer is
2419 actually the frame pointer of the calling frame. */
2420 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
2421 if (cache->base == 0)
2422 return cache;
2423
2424 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
2425 current_pc = frame_pc_unwind (next_frame);
2426 if (cache->pc != 0)
2427 {
2428 ULONGEST fpscr;
2429 fpscr = frame_unwind_register_unsigned (next_frame, FPSCR_REGNUM);
2430 sh_analyze_prologue (cache->pc, current_pc, cache, fpscr);
2431 }
2432
2433 if (!cache->uses_fp)
2434 {
2435 /* We didn't find a valid frame, which means that CACHE->base
2436 currently holds the frame pointer for our calling frame. If
2437 we're at the start of a function, or somewhere half-way its
2438 prologue, the function's frame probably hasn't been fully
2439 setup yet. Try to reconstruct the base address for the stack
2440 frame by looking at the stack pointer. For truly "frameless"
2441 functions this might work too. */
2442 cache->base = frame_unwind_register_unsigned
2443 (next_frame, gdbarch_sp_regnum (current_gdbarch));
2444 }
2445
2446 /* Now that we have the base address for the stack frame we can
2447 calculate the value of sp in the calling frame. */
2448 cache->saved_sp = cache->base + cache->sp_offset;
2449
2450 /* Adjust all the saved registers such that they contain addresses
2451 instead of offsets. */
2452 for (i = 0; i < SH_NUM_REGS; i++)
2453 if (cache->saved_regs[i] != -1)
2454 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2455
2456 return cache;
2457 }
2458
2459 static void
2460 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2461 int regnum, int *optimizedp,
2462 enum lval_type *lvalp, CORE_ADDR *addrp,
2463 int *realnump, gdb_byte *valuep)
2464 {
2465 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2466
2467 gdb_assert (regnum >= 0);
2468
2469 if (regnum == gdbarch_sp_regnum (current_gdbarch) && cache->saved_sp)
2470 {
2471 *optimizedp = 0;
2472 *lvalp = not_lval;
2473 *addrp = 0;
2474 *realnump = -1;
2475 if (valuep)
2476 {
2477 /* Store the value. */
2478 store_unsigned_integer (valuep, 4, cache->saved_sp);
2479 }
2480 return;
2481 }
2482
2483 /* The PC of the previous frame is stored in the PR register of
2484 the current frame. Frob regnum so that we pull the value from
2485 the correct place. */
2486 if (regnum == gdbarch_pc_regnum (current_gdbarch))
2487 regnum = PR_REGNUM;
2488
2489 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2490 {
2491 *optimizedp = 0;
2492 *lvalp = lval_memory;
2493 *addrp = cache->saved_regs[regnum];
2494 *realnump = -1;
2495 if (valuep)
2496 {
2497 /* Read the value in from memory. */
2498 read_memory (*addrp, valuep,
2499 register_size (current_gdbarch, regnum));
2500 }
2501 return;
2502 }
2503
2504 *optimizedp = 0;
2505 *lvalp = lval_register;
2506 *addrp = 0;
2507 *realnump = regnum;
2508 if (valuep)
2509 frame_unwind_register (next_frame, (*realnump), valuep);
2510 }
2511
2512 static void
2513 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2514 struct frame_id *this_id)
2515 {
2516 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2517
2518 /* This marks the outermost frame. */
2519 if (cache->base == 0)
2520 return;
2521
2522 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2523 }
2524
2525 static const struct frame_unwind sh_frame_unwind = {
2526 NORMAL_FRAME,
2527 sh_frame_this_id,
2528 sh_frame_prev_register
2529 };
2530
2531 static const struct frame_unwind *
2532 sh_frame_sniffer (struct frame_info *next_frame)
2533 {
2534 return &sh_frame_unwind;
2535 }
2536
2537 static CORE_ADDR
2538 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2539 {
2540 return frame_unwind_register_unsigned (next_frame,
2541 gdbarch_sp_regnum (current_gdbarch));
2542 }
2543
2544 static CORE_ADDR
2545 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2546 {
2547 return frame_unwind_register_unsigned (next_frame,
2548 gdbarch_pc_regnum (current_gdbarch));
2549 }
2550
2551 static struct frame_id
2552 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2553 {
2554 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2555 frame_pc_unwind (next_frame));
2556 }
2557
2558 static CORE_ADDR
2559 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2560 {
2561 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2562
2563 return cache->base;
2564 }
2565
2566 static const struct frame_base sh_frame_base = {
2567 &sh_frame_unwind,
2568 sh_frame_base_address,
2569 sh_frame_base_address,
2570 sh_frame_base_address
2571 };
2572
2573 /* The epilogue is defined here as the area at the end of a function,
2574 either on the `ret' instruction itself or after an instruction which
2575 destroys the function's stack frame. */
2576 static int
2577 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2578 {
2579 CORE_ADDR func_addr = 0, func_end = 0;
2580
2581 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2582 {
2583 ULONGEST inst;
2584 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2585 for a nop and some fixed data (e.g. big offsets) which are
2586 unfortunately also treated as part of the function (which
2587 means, they are below func_end. */
2588 CORE_ADDR addr = func_end - 28;
2589 if (addr < func_addr + 4)
2590 addr = func_addr + 4;
2591 if (pc < addr)
2592 return 0;
2593
2594 /* First search forward until hitting an rts. */
2595 while (addr < func_end
2596 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2597 addr += 2;
2598 if (addr >= func_end)
2599 return 0;
2600
2601 /* At this point we should find a mov.l @r15+,r14 instruction,
2602 either before or after the rts. If not, then the function has
2603 probably no "normal" epilogue and we bail out here. */
2604 inst = read_memory_unsigned_integer (addr - 2, 2);
2605 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2606 addr -= 2;
2607 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2608 return 0;
2609
2610 inst = read_memory_unsigned_integer (addr - 2, 2);
2611
2612 /* Step over possible lds.l @r15+,macl. */
2613 if (IS_MACL_LDS (inst))
2614 {
2615 addr -= 2;
2616 inst = read_memory_unsigned_integer (addr - 2, 2);
2617 }
2618
2619 /* Step over possible lds.l @r15+,pr. */
2620 if (IS_LDS (inst))
2621 {
2622 addr -= 2;
2623 inst = read_memory_unsigned_integer (addr - 2, 2);
2624 }
2625
2626 /* Step over possible mov r14,r15. */
2627 if (IS_MOV_FP_SP (inst))
2628 {
2629 addr -= 2;
2630 inst = read_memory_unsigned_integer (addr - 2, 2);
2631 }
2632
2633 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2634 instructions. */
2635 while (addr > func_addr + 4
2636 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2637 {
2638 addr -= 2;
2639 inst = read_memory_unsigned_integer (addr - 2, 2);
2640 }
2641
2642 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2643 That's allowed for the epilogue. */
2644 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2645 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2646 && addr > func_addr + 6
2647 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2)))
2648 addr -= 4;
2649
2650 if (pc >= addr)
2651 return 1;
2652 }
2653 return 0;
2654 }
2655 \f
2656
2657 static struct gdbarch *
2658 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2659 {
2660 struct gdbarch *gdbarch;
2661
2662 sh_show_regs = sh_generic_show_regs;
2663 switch (info.bfd_arch_info->mach)
2664 {
2665 case bfd_mach_sh2e:
2666 sh_show_regs = sh2e_show_regs;
2667 break;
2668 case bfd_mach_sh2a:
2669 sh_show_regs = sh2a_show_regs;
2670 break;
2671 case bfd_mach_sh2a_nofpu:
2672 sh_show_regs = sh2a_nofpu_show_regs;
2673 break;
2674 case bfd_mach_sh_dsp:
2675 sh_show_regs = sh_dsp_show_regs;
2676 break;
2677
2678 case bfd_mach_sh3:
2679 sh_show_regs = sh3_show_regs;
2680 break;
2681
2682 case bfd_mach_sh3e:
2683 sh_show_regs = sh3e_show_regs;
2684 break;
2685
2686 case bfd_mach_sh3_dsp:
2687 case bfd_mach_sh4al_dsp:
2688 sh_show_regs = sh3_dsp_show_regs;
2689 break;
2690
2691 case bfd_mach_sh4:
2692 case bfd_mach_sh4a:
2693 sh_show_regs = sh4_show_regs;
2694 break;
2695
2696 case bfd_mach_sh4_nofpu:
2697 case bfd_mach_sh4a_nofpu:
2698 sh_show_regs = sh4_nofpu_show_regs;
2699 break;
2700
2701 case bfd_mach_sh5:
2702 sh_show_regs = sh64_show_regs;
2703 /* SH5 is handled entirely in sh64-tdep.c */
2704 return sh64_gdbarch_init (info, arches);
2705 }
2706
2707 /* If there is already a candidate, use it. */
2708 arches = gdbarch_list_lookup_by_info (arches, &info);
2709 if (arches != NULL)
2710 return arches->gdbarch;
2711
2712 /* None found, create a new architecture from the information
2713 provided. */
2714 gdbarch = gdbarch_alloc (&info, NULL);
2715
2716 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2717 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2718 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2719 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2720 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2721 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2722 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2723 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2724
2725 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2726 set_gdbarch_sp_regnum (gdbarch, 15);
2727 set_gdbarch_pc_regnum (gdbarch, 16);
2728 set_gdbarch_fp0_regnum (gdbarch, -1);
2729 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2730
2731 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2732 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
2733
2734 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2735
2736 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2737 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2738
2739 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2740
2741 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2742 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2743
2744 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2745
2746 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2747
2748 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2749 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2750 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2751 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2752 frame_base_set_default (gdbarch, &sh_frame_base);
2753
2754 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2755
2756 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2757
2758 switch (info.bfd_arch_info->mach)
2759 {
2760 case bfd_mach_sh:
2761 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2762 break;
2763
2764 case bfd_mach_sh2:
2765 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2766 break;
2767
2768 case bfd_mach_sh2e:
2769 /* doubles on sh2e and sh3e are actually 4 byte. */
2770 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2771
2772 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2773 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2774 set_gdbarch_fp0_regnum (gdbarch, 25);
2775 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2776 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2777 break;
2778
2779 case bfd_mach_sh2a:
2780 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2781 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2782 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2783
2784 set_gdbarch_fp0_regnum (gdbarch, 25);
2785 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2786 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2787 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2788 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2789 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2790 break;
2791
2792 case bfd_mach_sh2a_nofpu:
2793 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2794 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2795
2796 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2797 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2798 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2799 break;
2800
2801 case bfd_mach_sh_dsp:
2802 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2803 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2804 break;
2805
2806 case bfd_mach_sh3:
2807 case bfd_mach_sh3_nommu:
2808 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2809 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2810 break;
2811
2812 case bfd_mach_sh3e:
2813 case bfd_mach_sh2a_or_sh3e:
2814 /* doubles on sh2e and sh3e are actually 4 byte. */
2815 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2816
2817 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2818 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2819 set_gdbarch_fp0_regnum (gdbarch, 25);
2820 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2821 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2822 break;
2823
2824 case bfd_mach_sh3_dsp:
2825 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2826 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2827 break;
2828
2829 case bfd_mach_sh4:
2830 case bfd_mach_sh4a:
2831 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2832 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2833 set_gdbarch_fp0_regnum (gdbarch, 25);
2834 set_gdbarch_num_pseudo_regs (gdbarch, 13);
2835 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2836 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2837 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2838 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2839 break;
2840
2841 case bfd_mach_sh4_nofpu:
2842 case bfd_mach_sh4a_nofpu:
2843 case bfd_mach_sh4_nommu_nofpu:
2844 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2845 case bfd_mach_sh2a_or_sh4:
2846 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2847 break;
2848
2849 case bfd_mach_sh4al_dsp:
2850 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2851 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2852 break;
2853
2854 default:
2855 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2856 break;
2857 }
2858
2859 /* Hook in ABI-specific overrides, if they have been registered. */
2860 gdbarch_init_osabi (info, gdbarch);
2861
2862 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2863 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2864
2865 return gdbarch;
2866 }
2867
2868 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2869
2870 void
2871 _initialize_sh_tdep (void)
2872 {
2873 struct cmd_list_element *c;
2874
2875 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2876
2877 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
2878 }
GDB Binutils - Deliverables
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